├── stm32f2xx.h ├── Makefile ├── README.md ├── addr.c ├── stm32f2xx.idc ├── LICENSE ├── structs.h └── core_cm3.h /stm32f2xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stef/idapro-cortex-m-hwregs/master/stm32f2xx.h -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | stm32f2xx.idc: addr 2 | ./addr > stm32f2xx.idc 3 | 4 | addr: addr.c stm32f2xx.h core_cm3.h 5 | gcc -o addr addr.c 6 | 7 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32f2xx HW register setup for IDA Pro. 2 | 3 | This project contains a C header file that can be parsed by IDA to 4 | define the structures of the STM32F2xx HW registers, as well as a tool 5 | to generate an IDC script that creates segments for these HW registers 6 | and sets their type to the appropriate struct. The addresses are 7 | derived from the official CMSIS header files and the whole project 8 | should be easily adaptable to other Cortex-M class MCUs. 9 | 10 | ## Usage 11 | 12 | 1. Load your binary in IDA 13 | 2. Set up your compiler (Options -> Compiler...) - the GNU C compiler is a good choice 14 | 3. Load the `structs.h` file using (File -> Load File -> Parse C header file) 15 | 4. Sync the newly imported types (View -> Open Subviews -> Local types) and then (Edit -> Synchronize to IDB) 16 | 5. Verify you have a bunch of new structures in the Structures subview 17 | 6. Run the stm32f2xx.idc script (File -> Script File) 18 | 7. enjoy your properly set up HW registers. 19 | -------------------------------------------------------------------------------- /addr.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "stm32f2xx.h" 3 | 4 | // print 5 | //#define dump(name, str) printf("0x%08x\t%s\t%s\t%ld\n", name##_BASE, #name, #str, sizeof(str)) 6 | 7 | // c 8 | //ETH_TypeDef * ETH = ((ETH_TypeDef *) ETH_BASE) 9 | //#define dump(name, str) printf("%s* %s = (%s*) 0x%08x; //%ld\n", #str, #name, #str, name##_BASE,sizeof(str)) 10 | 11 | // idapython 12 | //#define dump(name, str) printf("AddSeg(0x%08x, 0x%08x, 0x0, 1, 1, 0); s = getseg(0x%08x); set_segm_name(s, '%s')\n", name##_BASE, name##_BASE+(unsigned int)sizeof(str), name##_BASE, #name); 13 | 14 | // idc 15 | #define dump(name, str) printf("add_segm_ex(0x%08x, 0x%08x, 0, 1, 0, 0, 0); set_segm_name(0x%08x, \"%s\"); apply_type(0x%08x, get_tinfo(\"%s\"), 1);set_name(0x%08x, \"%s\", 2);\n", name##_BASE, name##_BASE+(unsigned int)sizeof(str), name##_BASE, #name, name##_BASE, #str, name##_BASE, #name); 16 | 17 | int main(void) { 18 | //printf("from idautils import *\nfrom idc import *\nfrom idaapi import *\n\nSEGMENT_ARCH = 32\n"); 19 | printf("#include \nstatic main(){\n"); 20 | 21 | dump(SCS, InterruptType_Type); 22 | dump(ITM, ITM_Type); 23 | dump(CoreDebug, CoreDebug_Type); 24 | dump(SysTick, SysTick_Type); 25 | dump(NVIC, NVIC_Type); 26 | dump(SCB, SCB_Type); 27 | dump(MPU, MPU_Type); 28 | 29 | dump(TIM2, TIM_TypeDef); 30 | dump(TIM3, TIM_TypeDef); 31 | dump(TIM4, TIM_TypeDef); 32 | dump(TIM5, TIM_TypeDef); 33 | dump(TIM6, TIM_TypeDef); 34 | dump(TIM7, TIM_TypeDef); 35 | dump(TIM12, TIM_TypeDef); 36 | dump(TIM13, TIM_TypeDef); 37 | dump(TIM14, TIM_TypeDef); 38 | dump(RTC, RTC_TypeDef); 39 | dump(WWDG, WWDG_TypeDef); 40 | dump(IWDG, IWDG_TypeDef); 41 | dump(SPI2, SPI_TypeDef); 42 | dump(SPI3, SPI_TypeDef); 43 | dump(USART2, USART_TypeDef); 44 | dump(USART3, USART_TypeDef); 45 | dump(UART4, USART_TypeDef); 46 | dump(UART5, USART_TypeDef); 47 | dump(I2C1, I2C_TypeDef); 48 | dump(I2C2, I2C_TypeDef); 49 | dump(I2C3, I2C_TypeDef); 50 | dump(CAN1, CAN_TypeDef); 51 | dump(CAN2, CAN_TypeDef); 52 | dump(PWR, PWR_TypeDef); 53 | dump(DAC, DAC_TypeDef); 54 | dump(TIM1, TIM_TypeDef); 55 | dump(TIM8, TIM_TypeDef); 56 | dump(USART1, USART_TypeDef); 57 | dump(USART6, USART_TypeDef); 58 | dump(ADC1, ADC_TypeDef); 59 | dump(ADC2, ADC_TypeDef); 60 | dump(ADC3, ADC_TypeDef); 61 | dump(ADC, ADC_Common_TypeDef); 62 | dump(SDIO, SDIO_TypeDef); 63 | dump(SPI1, SPI_TypeDef); 64 | dump(SYSCFG, SYSCFG_TypeDef); 65 | dump(EXTI, EXTI_TypeDef); 66 | dump(TIM9, TIM_TypeDef); 67 | dump(TIM10, TIM_TypeDef); 68 | dump(TIM11, TIM_TypeDef); 69 | dump(GPIOA, GPIO_TypeDef); 70 | dump(GPIOB, GPIO_TypeDef); 71 | dump(GPIOC, GPIO_TypeDef); 72 | dump(GPIOD, GPIO_TypeDef); 73 | dump(GPIOE, GPIO_TypeDef); 74 | dump(GPIOF, GPIO_TypeDef); 75 | dump(GPIOG, GPIO_TypeDef); 76 | dump(GPIOH, GPIO_TypeDef); 77 | dump(GPIOI, GPIO_TypeDef); 78 | dump(CRC, CRC_TypeDef); 79 | dump(RCC, RCC_TypeDef); 80 | dump(FLASH_R, FLASH_TypeDef); 81 | dump(DMA1, DMA_TypeDef); 82 | dump(DMA1_Stream0, DMA_Stream_TypeDef); 83 | dump(DMA1_Stream1, DMA_Stream_TypeDef); 84 | dump(DMA1_Stream2, DMA_Stream_TypeDef); 85 | dump(DMA1_Stream3, DMA_Stream_TypeDef); 86 | dump(DMA1_Stream4, DMA_Stream_TypeDef); 87 | dump(DMA1_Stream5, DMA_Stream_TypeDef); 88 | dump(DMA1_Stream6, DMA_Stream_TypeDef); 89 | dump(DMA1_Stream7, DMA_Stream_TypeDef); 90 | dump(DMA2, DMA_TypeDef); 91 | dump(DMA2_Stream0, DMA_Stream_TypeDef); 92 | dump(DMA2_Stream1, DMA_Stream_TypeDef); 93 | dump(DMA2_Stream2, DMA_Stream_TypeDef); 94 | dump(DMA2_Stream3, DMA_Stream_TypeDef); 95 | dump(DMA2_Stream4, DMA_Stream_TypeDef); 96 | dump(DMA2_Stream5, DMA_Stream_TypeDef); 97 | dump(DMA2_Stream6, DMA_Stream_TypeDef); 98 | dump(DMA2_Stream7, DMA_Stream_TypeDef); 99 | dump(ETH, ETH_TypeDef); 100 | dump(DCMI, DCMI_TypeDef); 101 | dump(CRYP, CRYP_TypeDef); 102 | dump(HASH, HASH_TypeDef); 103 | dump(RNG, RNG_TypeDef); 104 | dump(FSMC_Bank1_R, FSMC_Bank1_TypeDef); 105 | dump(FSMC_Bank1E_R, FSMC_Bank1E_TypeDef); 106 | dump(FSMC_Bank2_R, FSMC_Bank2_TypeDef); 107 | dump(FSMC_Bank3_R, FSMC_Bank3_TypeDef); 108 | dump(FSMC_Bank4_R, FSMC_Bank4_TypeDef); 109 | dump(DBGMCU, DBGMCU_TypeDef); 110 | 111 | printf("}\n"); 112 | 113 | return 0; 114 | } 115 | 116 | -------------------------------------------------------------------------------- /stm32f2xx.idc: -------------------------------------------------------------------------------- 1 | #include 2 | static main(){ 3 | add_segm_ex(0xe000e000, 0xe000e00c, 0, 1, 0, 0, 0); set_segm_name(0xe000e000, "SCS"); apply_type(0xe000e000, get_tinfo("InterruptType_Type"), 1);set_name(0xe000e000, "SCS", 2); 4 | add_segm_ex(0xe0000000, 0xe0001000, 0, 1, 0, 0, 0); set_segm_name(0xe0000000, "ITM"); apply_type(0xe0000000, get_tinfo("ITM_Type"), 1);set_name(0xe0000000, "ITM", 2); 5 | add_segm_ex(0xe000edf0, 0xe000ee00, 0, 1, 0, 0, 0); set_segm_name(0xe000edf0, "CoreDebug"); apply_type(0xe000edf0, get_tinfo("CoreDebug_Type"), 1);set_name(0xe000edf0, "CoreDebug", 2); 6 | add_segm_ex(0xe000e010, 0xe000e020, 0, 1, 0, 0, 0); set_segm_name(0xe000e010, "SysTick"); apply_type(0xe000e010, get_tinfo("SysTick_Type"), 1);set_name(0xe000e010, "SysTick", 2); 7 | add_segm_ex(0xe000e100, 0xe000ef04, 0, 1, 0, 0, 0); set_segm_name(0xe000e100, "NVIC"); apply_type(0xe000e100, get_tinfo("NVIC_Type"), 1);set_name(0xe000e100, "NVIC", 2); 8 | add_segm_ex(0xe000ed00, 0xe000ed74, 0, 1, 0, 0, 0); set_segm_name(0xe000ed00, "SCB"); apply_type(0xe000ed00, get_tinfo("SCB_Type"), 1);set_name(0xe000ed00, "SCB", 2); 9 | add_segm_ex(0xe000ed90, 0xe000edbc, 0, 1, 0, 0, 0); set_segm_name(0xe000ed90, "MPU"); apply_type(0xe000ed90, get_tinfo("MPU_Type"), 1);set_name(0xe000ed90, "MPU", 2); 10 | add_segm_ex(0x40000000, 0x40000054, 0, 1, 0, 0, 0); set_segm_name(0x40000000, "TIM2"); apply_type(0x40000000, get_tinfo("TIM_TypeDef"), 1);set_name(0x40000000, "TIM2", 2); 11 | add_segm_ex(0x40000400, 0x40000454, 0, 1, 0, 0, 0); set_segm_name(0x40000400, "TIM3"); apply_type(0x40000400, get_tinfo("TIM_TypeDef"), 1);set_name(0x40000400, "TIM3", 2); 12 | add_segm_ex(0x40000800, 0x40000854, 0, 1, 0, 0, 0); set_segm_name(0x40000800, "TIM4"); apply_type(0x40000800, get_tinfo("TIM_TypeDef"), 1);set_name(0x40000800, "TIM4", 2); 13 | add_segm_ex(0x40000c00, 0x40000c54, 0, 1, 0, 0, 0); set_segm_name(0x40000c00, "TIM5"); apply_type(0x40000c00, get_tinfo("TIM_TypeDef"), 1);set_name(0x40000c00, "TIM5", 2); 14 | add_segm_ex(0x40001000, 0x40001054, 0, 1, 0, 0, 0); set_segm_name(0x40001000, "TIM6"); apply_type(0x40001000, get_tinfo("TIM_TypeDef"), 1);set_name(0x40001000, "TIM6", 2); 15 | add_segm_ex(0x40001400, 0x40001454, 0, 1, 0, 0, 0); set_segm_name(0x40001400, "TIM7"); apply_type(0x40001400, get_tinfo("TIM_TypeDef"), 1);set_name(0x40001400, "TIM7", 2); 16 | add_segm_ex(0x40001800, 0x40001854, 0, 1, 0, 0, 0); set_segm_name(0x40001800, "TIM12"); apply_type(0x40001800, get_tinfo("TIM_TypeDef"), 1);set_name(0x40001800, "TIM12", 2); 17 | add_segm_ex(0x40001c00, 0x40001c54, 0, 1, 0, 0, 0); set_segm_name(0x40001c00, "TIM13"); apply_type(0x40001c00, get_tinfo("TIM_TypeDef"), 1);set_name(0x40001c00, "TIM13", 2); 18 | add_segm_ex(0x40002000, 0x40002054, 0, 1, 0, 0, 0); set_segm_name(0x40002000, "TIM14"); apply_type(0x40002000, get_tinfo("TIM_TypeDef"), 1);set_name(0x40002000, "TIM14", 2); 19 | add_segm_ex(0x40002800, 0x400028a0, 0, 1, 0, 0, 0); set_segm_name(0x40002800, "RTC"); apply_type(0x40002800, get_tinfo("RTC_TypeDef"), 1);set_name(0x40002800, "RTC", 2); 20 | add_segm_ex(0x40002c00, 0x40002c0c, 0, 1, 0, 0, 0); set_segm_name(0x40002c00, "WWDG"); apply_type(0x40002c00, get_tinfo("WWDG_TypeDef"), 1);set_name(0x40002c00, "WWDG", 2); 21 | add_segm_ex(0x40003000, 0x40003010, 0, 1, 0, 0, 0); set_segm_name(0x40003000, "IWDG"); apply_type(0x40003000, get_tinfo("IWDG_TypeDef"), 1);set_name(0x40003000, "IWDG", 2); 22 | add_segm_ex(0x40003800, 0x40003824, 0, 1, 0, 0, 0); set_segm_name(0x40003800, "SPI2"); apply_type(0x40003800, get_tinfo("SPI_TypeDef"), 1);set_name(0x40003800, "SPI2", 2); 23 | add_segm_ex(0x40003c00, 0x40003c24, 0, 1, 0, 0, 0); set_segm_name(0x40003c00, "SPI3"); apply_type(0x40003c00, get_tinfo("SPI_TypeDef"), 1);set_name(0x40003c00, "SPI3", 2); 24 | add_segm_ex(0x40004400, 0x4000441c, 0, 1, 0, 0, 0); set_segm_name(0x40004400, "USART2"); apply_type(0x40004400, get_tinfo("USART_TypeDef"), 1);set_name(0x40004400, "USART2", 2); 25 | add_segm_ex(0x40004800, 0x4000481c, 0, 1, 0, 0, 0); set_segm_name(0x40004800, "USART3"); apply_type(0x40004800, get_tinfo("USART_TypeDef"), 1);set_name(0x40004800, "USART3", 2); 26 | add_segm_ex(0x40004c00, 0x40004c1c, 0, 1, 0, 0, 0); set_segm_name(0x40004c00, "UART4"); apply_type(0x40004c00, get_tinfo("USART_TypeDef"), 1);set_name(0x40004c00, "UART4", 2); 27 | add_segm_ex(0x40005000, 0x4000501c, 0, 1, 0, 0, 0); set_segm_name(0x40005000, "UART5"); apply_type(0x40005000, get_tinfo("USART_TypeDef"), 1);set_name(0x40005000, "UART5", 2); 28 | add_segm_ex(0x40005400, 0x40005424, 0, 1, 0, 0, 0); set_segm_name(0x40005400, "I2C1"); apply_type(0x40005400, get_tinfo("I2C_TypeDef"), 1);set_name(0x40005400, "I2C1", 2); 29 | add_segm_ex(0x40005800, 0x40005824, 0, 1, 0, 0, 0); set_segm_name(0x40005800, "I2C2"); apply_type(0x40005800, get_tinfo("I2C_TypeDef"), 1);set_name(0x40005800, "I2C2", 2); 30 | add_segm_ex(0x40005c00, 0x40005c24, 0, 1, 0, 0, 0); set_segm_name(0x40005c00, "I2C3"); apply_type(0x40005c00, get_tinfo("I2C_TypeDef"), 1);set_name(0x40005c00, "I2C3", 2); 31 | add_segm_ex(0x40006400, 0x40006720, 0, 1, 0, 0, 0); set_segm_name(0x40006400, "CAN1"); apply_type(0x40006400, get_tinfo("CAN_TypeDef"), 1);set_name(0x40006400, "CAN1", 2); 32 | add_segm_ex(0x40006800, 0x40006b20, 0, 1, 0, 0, 0); set_segm_name(0x40006800, "CAN2"); apply_type(0x40006800, get_tinfo("CAN_TypeDef"), 1);set_name(0x40006800, "CAN2", 2); 33 | add_segm_ex(0x40007000, 0x40007008, 0, 1, 0, 0, 0); set_segm_name(0x40007000, "PWR"); apply_type(0x40007000, get_tinfo("PWR_TypeDef"), 1);set_name(0x40007000, "PWR", 2); 34 | add_segm_ex(0x40007400, 0x40007438, 0, 1, 0, 0, 0); set_segm_name(0x40007400, "DAC"); apply_type(0x40007400, get_tinfo("DAC_TypeDef"), 1);set_name(0x40007400, "DAC", 2); 35 | add_segm_ex(0x40010000, 0x40010054, 0, 1, 0, 0, 0); set_segm_name(0x40010000, "TIM1"); apply_type(0x40010000, get_tinfo("TIM_TypeDef"), 1);set_name(0x40010000, "TIM1", 2); 36 | add_segm_ex(0x40010400, 0x40010454, 0, 1, 0, 0, 0); set_segm_name(0x40010400, "TIM8"); apply_type(0x40010400, get_tinfo("TIM_TypeDef"), 1);set_name(0x40010400, "TIM8", 2); 37 | add_segm_ex(0x40011000, 0x4001101c, 0, 1, 0, 0, 0); set_segm_name(0x40011000, "USART1"); apply_type(0x40011000, get_tinfo("USART_TypeDef"), 1);set_name(0x40011000, "USART1", 2); 38 | add_segm_ex(0x40011400, 0x4001141c, 0, 1, 0, 0, 0); set_segm_name(0x40011400, "USART6"); apply_type(0x40011400, get_tinfo("USART_TypeDef"), 1);set_name(0x40011400, "USART6", 2); 39 | add_segm_ex(0x40012000, 0x40012050, 0, 1, 0, 0, 0); set_segm_name(0x40012000, "ADC1"); apply_type(0x40012000, get_tinfo("ADC_TypeDef"), 1);set_name(0x40012000, "ADC1", 2); 40 | add_segm_ex(0x40012100, 0x40012150, 0, 1, 0, 0, 0); set_segm_name(0x40012100, "ADC2"); apply_type(0x40012100, get_tinfo("ADC_TypeDef"), 1);set_name(0x40012100, "ADC2", 2); 41 | add_segm_ex(0x40012200, 0x40012250, 0, 1, 0, 0, 0); set_segm_name(0x40012200, "ADC3"); apply_type(0x40012200, get_tinfo("ADC_TypeDef"), 1);set_name(0x40012200, "ADC3", 2); 42 | add_segm_ex(0x40012300, 0x4001230c, 0, 1, 0, 0, 0); set_segm_name(0x40012300, "ADC"); apply_type(0x40012300, get_tinfo("ADC_Common_TypeDef"), 1);set_name(0x40012300, "ADC", 2); 43 | add_segm_ex(0x40012c00, 0x40012c84, 0, 1, 0, 0, 0); set_segm_name(0x40012c00, "SDIO"); apply_type(0x40012c00, get_tinfo("SDIO_TypeDef"), 1);set_name(0x40012c00, "SDIO", 2); 44 | add_segm_ex(0x40013000, 0x40013024, 0, 1, 0, 0, 0); set_segm_name(0x40013000, "SPI1"); apply_type(0x40013000, get_tinfo("SPI_TypeDef"), 1);set_name(0x40013000, "SPI1", 2); 45 | add_segm_ex(0x40013800, 0x40013824, 0, 1, 0, 0, 0); set_segm_name(0x40013800, "SYSCFG"); apply_type(0x40013800, get_tinfo("SYSCFG_TypeDef"), 1);set_name(0x40013800, "SYSCFG", 2); 46 | add_segm_ex(0x40013c00, 0x40013c18, 0, 1, 0, 0, 0); set_segm_name(0x40013c00, "EXTI"); apply_type(0x40013c00, get_tinfo("EXTI_TypeDef"), 1);set_name(0x40013c00, "EXTI", 2); 47 | add_segm_ex(0x40014000, 0x40014054, 0, 1, 0, 0, 0); set_segm_name(0x40014000, "TIM9"); apply_type(0x40014000, get_tinfo("TIM_TypeDef"), 1);set_name(0x40014000, "TIM9", 2); 48 | add_segm_ex(0x40014400, 0x40014454, 0, 1, 0, 0, 0); set_segm_name(0x40014400, "TIM10"); apply_type(0x40014400, get_tinfo("TIM_TypeDef"), 1);set_name(0x40014400, "TIM10", 2); 49 | add_segm_ex(0x40014800, 0x40014854, 0, 1, 0, 0, 0); set_segm_name(0x40014800, "TIM11"); apply_type(0x40014800, get_tinfo("TIM_TypeDef"), 1);set_name(0x40014800, "TIM11", 2); 50 | add_segm_ex(0x40020000, 0x40020028, 0, 1, 0, 0, 0); set_segm_name(0x40020000, "GPIOA"); apply_type(0x40020000, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40020000, "GPIOA", 2); 51 | add_segm_ex(0x40020400, 0x40020428, 0, 1, 0, 0, 0); set_segm_name(0x40020400, "GPIOB"); apply_type(0x40020400, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40020400, "GPIOB", 2); 52 | add_segm_ex(0x40020800, 0x40020828, 0, 1, 0, 0, 0); set_segm_name(0x40020800, "GPIOC"); apply_type(0x40020800, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40020800, "GPIOC", 2); 53 | add_segm_ex(0x40020c00, 0x40020c28, 0, 1, 0, 0, 0); set_segm_name(0x40020c00, "GPIOD"); apply_type(0x40020c00, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40020c00, "GPIOD", 2); 54 | add_segm_ex(0x40021000, 0x40021028, 0, 1, 0, 0, 0); set_segm_name(0x40021000, "GPIOE"); apply_type(0x40021000, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40021000, "GPIOE", 2); 55 | add_segm_ex(0x40021400, 0x40021428, 0, 1, 0, 0, 0); set_segm_name(0x40021400, "GPIOF"); apply_type(0x40021400, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40021400, "GPIOF", 2); 56 | add_segm_ex(0x40021800, 0x40021828, 0, 1, 0, 0, 0); set_segm_name(0x40021800, "GPIOG"); apply_type(0x40021800, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40021800, "GPIOG", 2); 57 | add_segm_ex(0x40021c00, 0x40021c28, 0, 1, 0, 0, 0); set_segm_name(0x40021c00, "GPIOH"); apply_type(0x40021c00, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40021c00, "GPIOH", 2); 58 | add_segm_ex(0x40022000, 0x40022028, 0, 1, 0, 0, 0); set_segm_name(0x40022000, "GPIOI"); apply_type(0x40022000, get_tinfo("GPIO_TypeDef"), 1);set_name(0x40022000, "GPIOI", 2); 59 | add_segm_ex(0x40023000, 0x4002300c, 0, 1, 0, 0, 0); set_segm_name(0x40023000, "CRC"); apply_type(0x40023000, get_tinfo("CRC_TypeDef"), 1);set_name(0x40023000, "CRC", 2); 60 | add_segm_ex(0x40023800, 0x40023888, 0, 1, 0, 0, 0); set_segm_name(0x40023800, "RCC"); apply_type(0x40023800, get_tinfo("RCC_TypeDef"), 1);set_name(0x40023800, "RCC", 2); 61 | add_segm_ex(0x40023c00, 0x40023c18, 0, 1, 0, 0, 0); set_segm_name(0x40023c00, "FLASH_R"); apply_type(0x40023c00, get_tinfo("FLASH_TypeDef"), 1);set_name(0x40023c00, "FLASH_R", 2); 62 | add_segm_ex(0x40026000, 0x40026010, 0, 1, 0, 0, 0); set_segm_name(0x40026000, "DMA1"); apply_type(0x40026000, get_tinfo("DMA_TypeDef"), 1);set_name(0x40026000, "DMA1", 2); 63 | add_segm_ex(0x40026010, 0x40026028, 0, 1, 0, 0, 0); set_segm_name(0x40026010, "DMA1_Stream0"); apply_type(0x40026010, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026010, "DMA1_Stream0", 2); 64 | add_segm_ex(0x40026028, 0x40026040, 0, 1, 0, 0, 0); set_segm_name(0x40026028, "DMA1_Stream1"); apply_type(0x40026028, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026028, "DMA1_Stream1", 2); 65 | add_segm_ex(0x40026040, 0x40026058, 0, 1, 0, 0, 0); set_segm_name(0x40026040, "DMA1_Stream2"); apply_type(0x40026040, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026040, "DMA1_Stream2", 2); 66 | add_segm_ex(0x40026058, 0x40026070, 0, 1, 0, 0, 0); set_segm_name(0x40026058, "DMA1_Stream3"); apply_type(0x40026058, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026058, "DMA1_Stream3", 2); 67 | add_segm_ex(0x40026070, 0x40026088, 0, 1, 0, 0, 0); set_segm_name(0x40026070, "DMA1_Stream4"); apply_type(0x40026070, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026070, "DMA1_Stream4", 2); 68 | add_segm_ex(0x40026088, 0x400260a0, 0, 1, 0, 0, 0); set_segm_name(0x40026088, "DMA1_Stream5"); apply_type(0x40026088, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026088, "DMA1_Stream5", 2); 69 | add_segm_ex(0x400260a0, 0x400260b8, 0, 1, 0, 0, 0); set_segm_name(0x400260a0, "DMA1_Stream6"); apply_type(0x400260a0, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x400260a0, "DMA1_Stream6", 2); 70 | add_segm_ex(0x400260b8, 0x400260d0, 0, 1, 0, 0, 0); set_segm_name(0x400260b8, "DMA1_Stream7"); apply_type(0x400260b8, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x400260b8, "DMA1_Stream7", 2); 71 | add_segm_ex(0x40026400, 0x40026410, 0, 1, 0, 0, 0); set_segm_name(0x40026400, "DMA2"); apply_type(0x40026400, get_tinfo("DMA_TypeDef"), 1);set_name(0x40026400, "DMA2", 2); 72 | add_segm_ex(0x40026410, 0x40026428, 0, 1, 0, 0, 0); set_segm_name(0x40026410, "DMA2_Stream0"); apply_type(0x40026410, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026410, "DMA2_Stream0", 2); 73 | add_segm_ex(0x40026428, 0x40026440, 0, 1, 0, 0, 0); set_segm_name(0x40026428, "DMA2_Stream1"); apply_type(0x40026428, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026428, "DMA2_Stream1", 2); 74 | add_segm_ex(0x40026440, 0x40026458, 0, 1, 0, 0, 0); set_segm_name(0x40026440, "DMA2_Stream2"); apply_type(0x40026440, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026440, "DMA2_Stream2", 2); 75 | add_segm_ex(0x40026458, 0x40026470, 0, 1, 0, 0, 0); set_segm_name(0x40026458, "DMA2_Stream3"); apply_type(0x40026458, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026458, "DMA2_Stream3", 2); 76 | add_segm_ex(0x40026470, 0x40026488, 0, 1, 0, 0, 0); set_segm_name(0x40026470, "DMA2_Stream4"); apply_type(0x40026470, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026470, "DMA2_Stream4", 2); 77 | add_segm_ex(0x40026488, 0x400264a0, 0, 1, 0, 0, 0); set_segm_name(0x40026488, "DMA2_Stream5"); apply_type(0x40026488, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x40026488, "DMA2_Stream5", 2); 78 | add_segm_ex(0x400264a0, 0x400264b8, 0, 1, 0, 0, 0); set_segm_name(0x400264a0, "DMA2_Stream6"); apply_type(0x400264a0, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x400264a0, "DMA2_Stream6", 2); 79 | add_segm_ex(0x400264b8, 0x400264d0, 0, 1, 0, 0, 0); set_segm_name(0x400264b8, "DMA2_Stream7"); apply_type(0x400264b8, get_tinfo("DMA_Stream_TypeDef"), 1);set_name(0x400264b8, "DMA2_Stream7", 2); 80 | add_segm_ex(0x40028000, 0x40029058, 0, 1, 0, 0, 0); set_segm_name(0x40028000, "ETH"); apply_type(0x40028000, get_tinfo("ETH_TypeDef"), 1);set_name(0x40028000, "ETH", 2); 81 | add_segm_ex(0x50050000, 0x5005002c, 0, 1, 0, 0, 0); set_segm_name(0x50050000, "DCMI"); apply_type(0x50050000, get_tinfo("DCMI_TypeDef"), 1);set_name(0x50050000, "DCMI", 2); 82 | add_segm_ex(0x50060000, 0x50060050, 0, 1, 0, 0, 0); set_segm_name(0x50060000, "CRYP"); apply_type(0x50060000, get_tinfo("CRYP_TypeDef"), 1);set_name(0x50060000, "CRYP", 2); 83 | add_segm_ex(0x50060400, 0x500605c4, 0, 1, 0, 0, 0); set_segm_name(0x50060400, "HASH"); apply_type(0x50060400, get_tinfo("HASH_TypeDef"), 1);set_name(0x50060400, "HASH", 2); 84 | add_segm_ex(0x50060800, 0x5006080c, 0, 1, 0, 0, 0); set_segm_name(0x50060800, "RNG"); apply_type(0x50060800, get_tinfo("RNG_TypeDef"), 1);set_name(0x50060800, "RNG", 2); 85 | add_segm_ex(0xa0000000, 0xa0000020, 0, 1, 0, 0, 0); set_segm_name(0xa0000000, "FSMC_Bank1_R"); apply_type(0xa0000000, get_tinfo("FSMC_Bank1_TypeDef"), 1);set_name(0xa0000000, "FSMC_Bank1_R", 2); 86 | add_segm_ex(0xa0000104, 0xa0000120, 0, 1, 0, 0, 0); set_segm_name(0xa0000104, "FSMC_Bank1E_R"); apply_type(0xa0000104, get_tinfo("FSMC_Bank1E_TypeDef"), 1);set_name(0xa0000104, "FSMC_Bank1E_R", 2); 87 | add_segm_ex(0xa0000060, 0xa0000078, 0, 1, 0, 0, 0); set_segm_name(0xa0000060, "FSMC_Bank2_R"); apply_type(0xa0000060, get_tinfo("FSMC_Bank2_TypeDef"), 1);set_name(0xa0000060, "FSMC_Bank2_R", 2); 88 | add_segm_ex(0xa0000080, 0xa0000098, 0, 1, 0, 0, 0); set_segm_name(0xa0000080, "FSMC_Bank3_R"); apply_type(0xa0000080, get_tinfo("FSMC_Bank3_TypeDef"), 1);set_name(0xa0000080, "FSMC_Bank3_R", 2); 89 | add_segm_ex(0xa00000a0, 0xa00000b4, 0, 1, 0, 0, 0); set_segm_name(0xa00000a0, "FSMC_Bank4_R"); apply_type(0xa00000a0, get_tinfo("FSMC_Bank4_TypeDef"), 1);set_name(0xa00000a0, "FSMC_Bank4_R", 2); 90 | add_segm_ex(0xe0042000, 0xe0042010, 0, 1, 0, 0, 0); set_segm_name(0xe0042000, "DBGMCU"); apply_type(0xe0042000, get_tinfo("DBGMCU_TypeDef"), 1);set_name(0xe0042000, "DBGMCU", 2); 91 | } 92 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. By contrast, 15 | the GNU General Public License is intended to guarantee your freedom to 16 | share and change all versions of a program--to make sure it remains free 17 | software for all its users. We, the Free Software Foundation, use the 18 | GNU General Public License for most of our software; it applies also to 19 | any other work released this way by its authors. You can apply it to 20 | your programs, too. 21 | 22 | When we speak of free software, we are referring to freedom, not 23 | price. Our General Public Licenses are designed to make sure that you 24 | have the freedom to distribute copies of free software (and charge for 25 | them if you wish), that you receive source code or can get it if you 26 | want it, that you can change the software or use pieces of it in new 27 | free programs, and that you know you can do these things. 28 | 29 | To protect your rights, we need to prevent others from denying you 30 | these rights or asking you to surrender the rights. Therefore, you have 31 | certain responsibilities if you distribute copies of the software, or if 32 | you modify it: responsibilities to respect the freedom of others. 33 | 34 | For example, if you distribute copies of such a program, whether 35 | gratis or for a fee, you must pass on to the recipients the same 36 | freedoms that you received. You must make sure that they, too, receive 37 | or can get the source code. And you must show them these terms so they 38 | know their rights. 39 | 40 | Developers that use the GNU GPL protect your rights with two steps: 41 | (1) assert copyright on the software, and (2) offer you this License 42 | giving you legal permission to copy, distribute and/or modify it. 43 | 44 | For the developers' and authors' protection, the GPL clearly explains 45 | that there is no warranty for this free software. For both users' and 46 | authors' sake, the GPL requires that modified versions be marked as 47 | changed, so that their problems will not be attributed erroneously to 48 | authors of previous versions. 49 | 50 | Some devices are designed to deny users access to install or run 51 | modified versions of the software inside them, although the manufacturer 52 | can do so. This is fundamentally incompatible with the aim of 53 | protecting users' freedom to change the software. The systematic 54 | pattern of such abuse occurs in the area of products for individuals to 55 | use, which is precisely where it is most unacceptable. Therefore, we 56 | have designed this version of the GPL to prohibit the practice for those 57 | products. If such problems arise substantially in other domains, we 58 | stand ready to extend this provision to those domains in future versions 59 | of the GPL, as needed to protect the freedom of users. 60 | 61 | Finally, every program is threatened constantly by software patents. 62 | States should not allow patents to restrict development and use of 63 | software on general-purpose computers, but in those that do, we wish to 64 | avoid the special danger that patents applied to a free program could 65 | make it effectively proprietary. To prevent this, the GPL assures that 66 | patents cannot be used to render the program non-free. 67 | 68 | The precise terms and conditions for copying, distribution and 69 | modification follow. 70 | 71 | TERMS AND CONDITIONS 72 | 73 | 0. Definitions. 74 | 75 | "This License" refers to version 3 of the GNU General Public License. 76 | 77 | "Copyright" also means copyright-like laws that apply to other kinds of 78 | works, such as semiconductor masks. 79 | 80 | "The Program" refers to any copyrightable work licensed under this 81 | License. Each licensee is addressed as "you". "Licensees" and 82 | "recipients" may be individuals or organizations. 83 | 84 | To "modify" a work means to copy from or adapt all or part of the work 85 | in a fashion requiring copyright permission, other than the making of an 86 | exact copy. The resulting work is called a "modified version" of the 87 | earlier work or a work "based on" the earlier work. 88 | 89 | A "covered work" means either the unmodified Program or a work based 90 | on the Program. 91 | 92 | To "propagate" a work means to do anything with it that, without 93 | permission, would make you directly or secondarily liable for 94 | infringement under applicable copyright law, except executing it on a 95 | computer or modifying a private copy. Propagation includes copying, 96 | distribution (with or without modification), making available to the 97 | public, and in some countries other activities as well. 98 | 99 | To "convey" a work means any kind of propagation that enables other 100 | parties to make or receive copies. Mere interaction with a user through 101 | a computer network, with no transfer of a copy, is not conveying. 102 | 103 | An interactive user interface displays "Appropriate Legal Notices" 104 | to the extent that it includes a convenient and prominently visible 105 | feature that (1) displays an appropriate copyright notice, and (2) 106 | tells the user that there is no warranty for the work (except to the 107 | extent that warranties are provided), that licensees may convey the 108 | work under this License, and how to view a copy of this License. If 109 | the interface presents a list of user commands or options, such as a 110 | menu, a prominent item in the list meets this criterion. 111 | 112 | 1. Source Code. 113 | 114 | The "source code" for a work means the preferred form of the work 115 | for making modifications to it. "Object code" means any non-source 116 | form of a work. 117 | 118 | A "Standard Interface" means an interface that either is an official 119 | standard defined by a recognized standards body, or, in the case of 120 | interfaces specified for a particular programming language, one that 121 | is widely used among developers working in that language. 122 | 123 | The "System Libraries" of an executable work include anything, other 124 | than the work as a whole, that (a) is included in the normal form of 125 | packaging a Major Component, but which is not part of that Major 126 | Component, and (b) serves only to enable use of the work with that 127 | Major Component, or to implement a Standard Interface for which an 128 | implementation is available to the public in source code form. A 129 | "Major Component", in this context, means a major essential component 130 | (kernel, window system, and so on) of the specific operating system 131 | (if any) on which the executable work runs, or a compiler used to 132 | produce the work, or an object code interpreter used to run it. 133 | 134 | The "Corresponding Source" for a work in object code form means all 135 | the source code needed to generate, install, and (for an executable 136 | work) run the object code and to modify the work, including scripts to 137 | control those activities. However, it does not include the work's 138 | System Libraries, or general-purpose tools or generally available free 139 | programs which are used unmodified in performing those activities but 140 | which are not part of the work. For example, Corresponding Source 141 | includes interface definition files associated with source files for 142 | the work, and the source code for shared libraries and dynamically 143 | linked subprograms that the work is specifically designed to require, 144 | such as by intimate data communication or control flow between those 145 | subprograms and other parts of the work. 146 | 147 | The Corresponding Source need not include anything that users 148 | can regenerate automatically from other parts of the Corresponding 149 | Source. 150 | 151 | The Corresponding Source for a work in source code form is that 152 | same work. 153 | 154 | 2. Basic Permissions. 155 | 156 | All rights granted under this License are granted for the term of 157 | copyright on the Program, and are irrevocable provided the stated 158 | conditions are met. This License explicitly affirms your unlimited 159 | permission to run the unmodified Program. The output from running a 160 | covered work is covered by this License only if the output, given its 161 | content, constitutes a covered work. This License acknowledges your 162 | rights of fair use or other equivalent, as provided by copyright law. 163 | 164 | You may make, run and propagate covered works that you do not 165 | convey, without conditions so long as your license otherwise remains 166 | in force. You may convey covered works to others for the sole purpose 167 | of having them make modifications exclusively for you, or provide you 168 | with facilities for running those works, provided that you comply with 169 | the terms of this License in conveying all material for which you do 170 | not control copyright. Those thus making or running the covered works 171 | for you must do so exclusively on your behalf, under your direction 172 | and control, on terms that prohibit them from making any copies of 173 | your copyrighted material outside their relationship with you. 174 | 175 | Conveying under any other circumstances is permitted solely under 176 | the conditions stated below. Sublicensing is not allowed; section 10 177 | makes it unnecessary. 178 | 179 | 3. Protecting Users' Legal Rights From Anti-Circumvention Law. 180 | 181 | No covered work shall be deemed part of an effective technological 182 | measure under any applicable law fulfilling obligations under article 183 | 11 of the WIPO copyright treaty adopted on 20 December 1996, or 184 | similar laws prohibiting or restricting circumvention of such 185 | measures. 186 | 187 | When you convey a covered work, you waive any legal power to forbid 188 | circumvention of technological measures to the extent such circumvention 189 | is effected by exercising rights under this License with respect to 190 | the covered work, and you disclaim any intention to limit operation or 191 | modification of the work as a means of enforcing, against the work's 192 | users, your or third parties' legal rights to forbid circumvention of 193 | technological measures. 194 | 195 | 4. Conveying Verbatim Copies. 196 | 197 | You may convey verbatim copies of the Program's source code as you 198 | receive it, in any medium, provided that you conspicuously and 199 | appropriately publish on each copy an appropriate copyright notice; 200 | keep intact all notices stating that this License and any 201 | non-permissive terms added in accord with section 7 apply to the code; 202 | keep intact all notices of the absence of any warranty; and give all 203 | recipients a copy of this License along with the Program. 204 | 205 | You may charge any price or no price for each copy that you convey, 206 | and you may offer support or warranty protection for a fee. 207 | 208 | 5. Conveying Modified Source Versions. 209 | 210 | You may convey a work based on the Program, or the modifications to 211 | produce it from the Program, in the form of source code under the 212 | terms of section 4, provided that you also meet all of these conditions: 213 | 214 | a) The work must carry prominent notices stating that you modified 215 | it, and giving a relevant date. 216 | 217 | b) The work must carry prominent notices stating that it is 218 | released under this License and any conditions added under section 219 | 7. This requirement modifies the requirement in section 4 to 220 | "keep intact all notices". 221 | 222 | c) You must license the entire work, as a whole, under this 223 | License to anyone who comes into possession of a copy. This 224 | License will therefore apply, along with any applicable section 7 225 | additional terms, to the whole of the work, and all its parts, 226 | regardless of how they are packaged. This License gives no 227 | permission to license the work in any other way, but it does not 228 | invalidate such permission if you have separately received it. 229 | 230 | d) If the work has interactive user interfaces, each must display 231 | Appropriate Legal Notices; however, if the Program has interactive 232 | interfaces that do not display Appropriate Legal Notices, your 233 | work need not make them do so. 234 | 235 | A compilation of a covered work with other separate and independent 236 | works, which are not by their nature extensions of the covered work, 237 | and which are not combined with it such as to form a larger program, 238 | in or on a volume of a storage or distribution medium, is called an 239 | "aggregate" if the compilation and its resulting copyright are not 240 | used to limit the access or legal rights of the compilation's users 241 | beyond what the individual works permit. Inclusion of a covered work 242 | in an aggregate does not cause this License to apply to the other 243 | parts of the aggregate. 244 | 245 | 6. Conveying Non-Source Forms. 246 | 247 | You may convey a covered work in object code form under the terms 248 | of sections 4 and 5, provided that you also convey the 249 | machine-readable Corresponding Source under the terms of this License, 250 | in one of these ways: 251 | 252 | a) Convey the object code in, or embodied in, a physical product 253 | (including a physical distribution medium), accompanied by the 254 | Corresponding Source fixed on a durable physical medium 255 | customarily used for software interchange. 256 | 257 | b) Convey the object code in, or embodied in, a physical product 258 | (including a physical distribution medium), accompanied by a 259 | written offer, valid for at least three years and valid for as 260 | long as you offer spare parts or customer support for that product 261 | model, to give anyone who possesses the object code either (1) a 262 | copy of the Corresponding Source for all the software in the 263 | product that is covered by this License, on a durable physical 264 | medium customarily used for software interchange, for a price no 265 | more than your reasonable cost of physically performing this 266 | conveying of source, or (2) access to copy the 267 | Corresponding Source from a network server at no charge. 268 | 269 | c) Convey individual copies of the object code with a copy of the 270 | written offer to provide the Corresponding Source. This 271 | alternative is allowed only occasionally and noncommercially, and 272 | only if you received the object code with such an offer, in accord 273 | with subsection 6b. 274 | 275 | d) Convey the object code by offering access from a designated 276 | place (gratis or for a charge), and offer equivalent access to the 277 | Corresponding Source in the same way through the same place at no 278 | further charge. You need not require recipients to copy the 279 | Corresponding Source along with the object code. If the place to 280 | copy the object code is a network server, the Corresponding Source 281 | may be on a different server (operated by you or a third party) 282 | that supports equivalent copying facilities, provided you maintain 283 | clear directions next to the object code saying where to find the 284 | Corresponding Source. Regardless of what server hosts the 285 | Corresponding Source, you remain obligated to ensure that it is 286 | available for as long as needed to satisfy these requirements. 287 | 288 | e) Convey the object code using peer-to-peer transmission, provided 289 | you inform other peers where the object code and Corresponding 290 | Source of the work are being offered to the general public at no 291 | charge under subsection 6d. 292 | 293 | A separable portion of the object code, whose source code is excluded 294 | from the Corresponding Source as a System Library, need not be 295 | included in conveying the object code work. 296 | 297 | A "User Product" is either (1) a "consumer product", which means any 298 | tangible personal property which is normally used for personal, family, 299 | or household purposes, or (2) anything designed or sold for incorporation 300 | into a dwelling. In determining whether a product is a consumer product, 301 | doubtful cases shall be resolved in favor of coverage. For a particular 302 | product received by a particular user, "normally used" refers to a 303 | typical or common use of that class of product, regardless of the status 304 | of the particular user or of the way in which the particular user 305 | actually uses, or expects or is expected to use, the product. A product 306 | is a consumer product regardless of whether the product has substantial 307 | commercial, industrial or non-consumer uses, unless such uses represent 308 | the only significant mode of use of the product. 309 | 310 | "Installation Information" for a User Product means any methods, 311 | procedures, authorization keys, or other information required to install 312 | and execute modified versions of a covered work in that User Product from 313 | a modified version of its Corresponding Source. The information must 314 | suffice to ensure that the continued functioning of the modified object 315 | code is in no case prevented or interfered with solely because 316 | modification has been made. 317 | 318 | If you convey an object code work under this section in, or with, or 319 | specifically for use in, a User Product, and the conveying occurs as 320 | part of a transaction in which the right of possession and use of the 321 | User Product is transferred to the recipient in perpetuity or for a 322 | fixed term (regardless of how the transaction is characterized), the 323 | Corresponding Source conveyed under this section must be accompanied 324 | by the Installation Information. But this requirement does not apply 325 | if neither you nor any third party retains the ability to install 326 | modified object code on the User Product (for example, the work has 327 | been installed in ROM). 328 | 329 | The requirement to provide Installation Information does not include a 330 | requirement to continue to provide support service, warranty, or updates 331 | for a work that has been modified or installed by the recipient, or for 332 | the User Product in which it has been modified or installed. Access to a 333 | network may be denied when the modification itself materially and 334 | adversely affects the operation of the network or violates the rules and 335 | protocols for communication across the network. 336 | 337 | Corresponding Source conveyed, and Installation Information provided, 338 | in accord with this section must be in a format that is publicly 339 | documented (and with an implementation available to the public in 340 | source code form), and must require no special password or key for 341 | unpacking, reading or copying. 342 | 343 | 7. Additional Terms. 344 | 345 | "Additional permissions" are terms that supplement the terms of this 346 | License by making exceptions from one or more of its conditions. 347 | Additional permissions that are applicable to the entire Program shall 348 | be treated as though they were included in this License, to the extent 349 | that they are valid under applicable law. If additional permissions 350 | apply only to part of the Program, that part may be used separately 351 | under those permissions, but the entire Program remains governed by 352 | this License without regard to the additional permissions. 353 | 354 | When you convey a copy of a covered work, you may at your option 355 | remove any additional permissions from that copy, or from any part of 356 | it. (Additional permissions may be written to require their own 357 | removal in certain cases when you modify the work.) You may place 358 | additional permissions on material, added by you to a covered work, 359 | for which you have or can give appropriate copyright permission. 360 | 361 | Notwithstanding any other provision of this License, for material you 362 | add to a covered work, you may (if authorized by the copyright holders of 363 | that material) supplement the terms of this License with terms: 364 | 365 | a) Disclaiming warranty or limiting liability differently from the 366 | terms of sections 15 and 16 of this License; or 367 | 368 | b) Requiring preservation of specified reasonable legal notices or 369 | author attributions in that material or in the Appropriate Legal 370 | Notices displayed by works containing it; or 371 | 372 | c) Prohibiting misrepresentation of the origin of that material, or 373 | requiring that modified versions of such material be marked in 374 | reasonable ways as different from the original version; or 375 | 376 | d) Limiting the use for publicity purposes of names of licensors or 377 | authors of the material; or 378 | 379 | e) Declining to grant rights under trademark law for use of some 380 | trade names, trademarks, or service marks; or 381 | 382 | f) Requiring indemnification of licensors and authors of that 383 | material by anyone who conveys the material (or modified versions of 384 | it) with contractual assumptions of liability to the recipient, for 385 | any liability that these contractual assumptions directly impose on 386 | those licensors and authors. 387 | 388 | All other non-permissive additional terms are considered "further 389 | restrictions" within the meaning of section 10. If the Program as you 390 | received it, or any part of it, contains a notice stating that it is 391 | governed by this License along with a term that is a further 392 | restriction, you may remove that term. If a license document contains 393 | a further restriction but permits relicensing or conveying under this 394 | License, you may add to a covered work material governed by the terms 395 | of that license document, provided that the further restriction does 396 | not survive such relicensing or conveying. 397 | 398 | If you add terms to a covered work in accord with this section, you 399 | must place, in the relevant source files, a statement of the 400 | additional terms that apply to those files, or a notice indicating 401 | where to find the applicable terms. 402 | 403 | Additional terms, permissive or non-permissive, may be stated in the 404 | form of a separately written license, or stated as exceptions; 405 | the above requirements apply either way. 406 | 407 | 8. Termination. 408 | 409 | You may not propagate or modify a covered work except as expressly 410 | provided under this License. Any attempt otherwise to propagate or 411 | modify it is void, and will automatically terminate your rights under 412 | this License (including any patent licenses granted under the third 413 | paragraph of section 11). 414 | 415 | However, if you cease all violation of this License, then your 416 | license from a particular copyright holder is reinstated (a) 417 | provisionally, unless and until the copyright holder explicitly and 418 | finally terminates your license, and (b) permanently, if the copyright 419 | holder fails to notify you of the violation by some reasonable means 420 | prior to 60 days after the cessation. 421 | 422 | Moreover, your license from a particular copyright holder is 423 | reinstated permanently if the copyright holder notifies you of the 424 | violation by some reasonable means, this is the first time you have 425 | received notice of violation of this License (for any work) from that 426 | copyright holder, and you cure the violation prior to 30 days after 427 | your receipt of the notice. 428 | 429 | Termination of your rights under this section does not terminate the 430 | licenses of parties who have received copies or rights from you under 431 | this License. If your rights have been terminated and not permanently 432 | reinstated, you do not qualify to receive new licenses for the same 433 | material under section 10. 434 | 435 | 9. Acceptance Not Required for Having Copies. 436 | 437 | You are not required to accept this License in order to receive or 438 | run a copy of the Program. Ancillary propagation of a covered work 439 | occurring solely as a consequence of using peer-to-peer transmission 440 | to receive a copy likewise does not require acceptance. However, 441 | nothing other than this License grants you permission to propagate or 442 | modify any covered work. These actions infringe copyright if you do 443 | not accept this License. Therefore, by modifying or propagating a 444 | covered work, you indicate your acceptance of this License to do so. 445 | 446 | 10. Automatic Licensing of Downstream Recipients. 447 | 448 | Each time you convey a covered work, the recipient automatically 449 | receives a license from the original licensors, to run, modify and 450 | propagate that work, subject to this License. You are not responsible 451 | for enforcing compliance by third parties with this License. 452 | 453 | An "entity transaction" is a transaction transferring control of an 454 | organization, or substantially all assets of one, or subdividing an 455 | organization, or merging organizations. If propagation of a covered 456 | work results from an entity transaction, each party to that 457 | transaction who receives a copy of the work also receives whatever 458 | licenses to the work the party's predecessor in interest had or could 459 | give under the previous paragraph, plus a right to possession of the 460 | Corresponding Source of the work from the predecessor in interest, if 461 | the predecessor has it or can get it with reasonable efforts. 462 | 463 | You may not impose any further restrictions on the exercise of the 464 | rights granted or affirmed under this License. For example, you may 465 | not impose a license fee, royalty, or other charge for exercise of 466 | rights granted under this License, and you may not initiate litigation 467 | (including a cross-claim or counterclaim in a lawsuit) alleging that 468 | any patent claim is infringed by making, using, selling, offering for 469 | sale, or importing the Program or any portion of it. 470 | 471 | 11. Patents. 472 | 473 | A "contributor" is a copyright holder who authorizes use under this 474 | License of the Program or a work on which the Program is based. The 475 | work thus licensed is called the contributor's "contributor version". 476 | 477 | A contributor's "essential patent claims" are all patent claims 478 | owned or controlled by the contributor, whether already acquired or 479 | hereafter acquired, that would be infringed by some manner, permitted 480 | by this License, of making, using, or selling its contributor version, 481 | but do not include claims that would be infringed only as a 482 | consequence of further modification of the contributor version. For 483 | purposes of this definition, "control" includes the right to grant 484 | patent sublicenses in a manner consistent with the requirements of 485 | this License. 486 | 487 | Each contributor grants you a non-exclusive, worldwide, royalty-free 488 | patent license under the contributor's essential patent claims, to 489 | make, use, sell, offer for sale, import and otherwise run, modify and 490 | propagate the contents of its contributor version. 491 | 492 | In the following three paragraphs, a "patent license" is any express 493 | agreement or commitment, however denominated, not to enforce a patent 494 | (such as an express permission to practice a patent or covenant not to 495 | sue for patent infringement). To "grant" such a patent license to a 496 | party means to make such an agreement or commitment not to enforce a 497 | patent against the party. 498 | 499 | If you convey a covered work, knowingly relying on a patent license, 500 | and the Corresponding Source of the work is not available for anyone 501 | to copy, free of charge and under the terms of this License, through a 502 | publicly available network server or other readily accessible means, 503 | then you must either (1) cause the Corresponding Source to be so 504 | available, or (2) arrange to deprive yourself of the benefit of the 505 | patent license for this particular work, or (3) arrange, in a manner 506 | consistent with the requirements of this License, to extend the patent 507 | license to downstream recipients. "Knowingly relying" means you have 508 | actual knowledge that, but for the patent license, your conveying the 509 | covered work in a country, or your recipient's use of the covered work 510 | in a country, would infringe one or more identifiable patents in that 511 | country that you have reason to believe are valid. 512 | 513 | If, pursuant to or in connection with a single transaction or 514 | arrangement, you convey, or propagate by procuring conveyance of, a 515 | covered work, and grant a patent license to some of the parties 516 | receiving the covered work authorizing them to use, propagate, modify 517 | or convey a specific copy of the covered work, then the patent license 518 | you grant is automatically extended to all recipients of the covered 519 | work and works based on it. 520 | 521 | A patent license is "discriminatory" if it does not include within 522 | the scope of its coverage, prohibits the exercise of, or is 523 | conditioned on the non-exercise of one or more of the rights that are 524 | specifically granted under this License. You may not convey a covered 525 | work if you are a party to an arrangement with a third party that is 526 | in the business of distributing software, under which you make payment 527 | to the third party based on the extent of your activity of conveying 528 | the work, and under which the third party grants, to any of the 529 | parties who would receive the covered work from you, a discriminatory 530 | patent license (a) in connection with copies of the covered work 531 | conveyed by you (or copies made from those copies), or (b) primarily 532 | for and in connection with specific products or compilations that 533 | contain the covered work, unless you entered into that arrangement, 534 | or that patent license was granted, prior to 28 March 2007. 535 | 536 | Nothing in this License shall be construed as excluding or limiting 537 | any implied license or other defenses to infringement that may 538 | otherwise be available to you under applicable patent law. 539 | 540 | 12. No Surrender of Others' Freedom. 541 | 542 | If conditions are imposed on you (whether by court order, agreement or 543 | otherwise) that contradict the conditions of this License, they do not 544 | excuse you from the conditions of this License. If you cannot convey a 545 | covered work so as to satisfy simultaneously your obligations under this 546 | License and any other pertinent obligations, then as a consequence you may 547 | not convey it at all. For example, if you agree to terms that obligate you 548 | to collect a royalty for further conveying from those to whom you convey 549 | the Program, the only way you could satisfy both those terms and this 550 | License would be to refrain entirely from conveying the Program. 551 | 552 | 13. Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /structs.h: -------------------------------------------------------------------------------- 1 | typedef struct 2 | { 3 | unsigned int ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ 4 | unsigned int RESERVED0[24]; 5 | unsigned int ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ 6 | unsigned int RSERVED1[24]; 7 | unsigned int ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ 8 | unsigned int RESERVED2[24]; 9 | unsigned int ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ 10 | unsigned int RESERVED3[24]; 11 | unsigned int IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ 12 | unsigned int RESERVED4[56]; 13 | unsigned char IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ 14 | unsigned int RESERVED5[644]; 15 | unsigned int STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ 16 | } NVIC_Type; 17 | 18 | typedef struct 19 | { 20 | unsigned int CPUID; /*!< Offset: 0x00 CPU ID Base Register */ 21 | unsigned int ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ 22 | unsigned int VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ 23 | unsigned int AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ 24 | unsigned int SCR; /*!< Offset: 0x10 System Control Register */ 25 | unsigned int CCR; /*!< Offset: 0x14 Configuration Control Register */ 26 | unsigned char SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ 27 | unsigned int SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ 28 | unsigned int CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ 29 | unsigned int HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ 30 | unsigned int DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ 31 | unsigned int MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ 32 | unsigned int BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ 33 | unsigned int AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ 34 | unsigned int PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ 35 | unsigned int DFR; /*!< Offset: 0x48 Debug Feature Register */ 36 | unsigned int ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ 37 | unsigned int MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ 38 | unsigned int ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ 39 | } SCB_Type; 40 | 41 | typedef struct 42 | { 43 | unsigned int CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ 44 | unsigned int LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ 45 | unsigned int VAL; /*!< Offset: 0x08 SysTick Current Value Register */ 46 | unsigned int CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ 47 | } SysTick_Type; 48 | 49 | typedef struct 50 | { 51 | union 52 | { 53 | unsigned char u8; /*!< Offset: ITM Stimulus Port 8-bit */ 54 | unsigned short u16; /*!< Offset: ITM Stimulus Port 16-bit */ 55 | unsigned int u32; /*!< Offset: ITM Stimulus Port 32-bit */ 56 | } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ 57 | unsigned int RESERVED0[864]; 58 | unsigned int TER; /*!< Offset: ITM Trace Enable Register */ 59 | unsigned int RESERVED1[15]; 60 | unsigned int TPR; /*!< Offset: ITM Trace Privilege Register */ 61 | unsigned int RESERVED2[15]; 62 | unsigned int TCR; /*!< Offset: ITM Trace Control Register */ 63 | unsigned int RESERVED3[29]; 64 | unsigned int IWR; /*!< Offset: ITM Integration Write Register */ 65 | unsigned int IRR; /*!< Offset: ITM Integration Read Register */ 66 | unsigned int IMCR; /*!< Offset: ITM Integration Mode Control Register */ 67 | unsigned int RESERVED4[43]; 68 | unsigned int LAR; /*!< Offset: ITM Lock Access Register */ 69 | unsigned int LSR; /*!< Offset: ITM Lock Status Register */ 70 | unsigned int RESERVED5[6]; 71 | unsigned int PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ 72 | unsigned int PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ 73 | unsigned int PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ 74 | unsigned int PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ 75 | unsigned int PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ 76 | unsigned int PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ 77 | unsigned int PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ 78 | unsigned int PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ 79 | unsigned int CID0; /*!< Offset: ITM Component Identification Register #0 */ 80 | unsigned int CID1; /*!< Offset: ITM Component Identification Register #1 */ 81 | unsigned int CID2; /*!< Offset: ITM Component Identification Register #2 */ 82 | unsigned int CID3; /*!< Offset: ITM Component Identification Register #3 */ 83 | } ITM_Type; 84 | 85 | typedef struct 86 | { 87 | unsigned int RESERVED0; 88 | unsigned int ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ 89 | #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 90 | unsigned int ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ 91 | #else 92 | unsigned int RESERVED1; 93 | #endif 94 | } InterruptType_Type; 95 | 96 | typedef struct 97 | { 98 | unsigned int TYPE; /*!< Offset: 0x00 MPU Type Register */ 99 | unsigned int CTRL; /*!< Offset: 0x04 MPU Control Register */ 100 | unsigned int RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ 101 | unsigned int RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ 102 | unsigned int RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ 103 | unsigned int RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ 104 | unsigned int RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ 105 | unsigned int RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ 106 | unsigned int RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ 107 | unsigned int RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ 108 | unsigned int RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ 109 | } MPU_Type; 110 | 111 | typedef struct 112 | { 113 | unsigned int DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ 114 | unsigned int DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ 115 | unsigned int DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ 116 | unsigned int DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ 117 | } CoreDebug_Type; 118 | 119 | typedef struct 120 | { 121 | unsigned int SR; /*!< ADC status register, Address offset: 0x00 */ 122 | unsigned int CR1; /*!< ADC control register 1, Address offset: 0x04 */ 123 | unsigned int CR2; /*!< ADC control register 2, Address offset: 0x08 */ 124 | unsigned int SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ 125 | unsigned int SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ 126 | unsigned int JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ 127 | unsigned int JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ 128 | unsigned int JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ 129 | unsigned int JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ 130 | unsigned int HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ 131 | unsigned int LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ 132 | unsigned int SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ 133 | unsigned int SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ 134 | unsigned int SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ 135 | unsigned int JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ 136 | unsigned int JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ 137 | unsigned int JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ 138 | unsigned int JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ 139 | unsigned int JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ 140 | unsigned int DR; /*!< ADC regular data register, Address offset: 0x4C */ 141 | } ADC_TypeDef; 142 | 143 | typedef struct 144 | { 145 | unsigned int CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ 146 | unsigned int CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ 147 | unsigned int CDR; /*!< ADC common regular data register for dual 148 | AND triple modes, Address offset: ADC1 base address + 0x308 */ 149 | } ADC_Common_TypeDef; 150 | 151 | typedef struct 152 | { 153 | unsigned int TIR; /*!< CAN TX mailbox identifier register */ 154 | unsigned int TDTR; /*!< CAN mailbox data length control and time stamp register */ 155 | unsigned int TDLR; /*!< CAN mailbox data low register */ 156 | unsigned int TDHR; /*!< CAN mailbox data high register */ 157 | } CAN_TxMailBox_TypeDef; 158 | 159 | /** 160 | * @brief Controller Area Network FIFOMailBox 161 | */ 162 | 163 | typedef struct 164 | { 165 | unsigned int RIR; /*!< CAN receive FIFO mailbox identifier register */ 166 | unsigned int RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 167 | unsigned int RDLR; /*!< CAN receive FIFO mailbox data low register */ 168 | unsigned int RDHR; /*!< CAN receive FIFO mailbox data high register */ 169 | } CAN_FIFOMailBox_TypeDef; 170 | 171 | /** 172 | * @brief Controller Area Network FilterRegister 173 | */ 174 | 175 | typedef struct 176 | { 177 | unsigned int FR1; /*!< CAN Filter bank register 1 */ 178 | unsigned int FR2; /*!< CAN Filter bank register 1 */ 179 | } CAN_FilterRegister_TypeDef; 180 | 181 | /** 182 | * @brief Controller Area Network 183 | */ 184 | 185 | typedef struct 186 | { 187 | unsigned int MCR; /*!< CAN master control register, Address offset: 0x00 */ 188 | unsigned int MSR; /*!< CAN master status register, Address offset: 0x04 */ 189 | unsigned int TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 190 | unsigned int RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 191 | unsigned int RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 192 | unsigned int IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 193 | unsigned int ESR; /*!< CAN error status register, Address offset: 0x18 */ 194 | unsigned int BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 195 | unsigned int RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 196 | CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 197 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 198 | unsigned int RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 199 | unsigned int FMR; /*!< CAN filter master register, Address offset: 0x200 */ 200 | unsigned int FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 201 | unsigned int RESERVED2; /*!< Reserved, 0x208 */ 202 | unsigned int FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 203 | unsigned int RESERVED3; /*!< Reserved, 0x210 */ 204 | unsigned int FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 205 | unsigned int RESERVED4; /*!< Reserved, 0x218 */ 206 | unsigned int FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 207 | unsigned int RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 208 | CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ 209 | } CAN_TypeDef; 210 | 211 | typedef struct 212 | { 213 | unsigned int DR; /*!< CRC Data register, Address offset: 0x00 */ 214 | unsigned char IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 215 | unsigned char RESERVED0; /*!< Reserved, 0x05 */ 216 | unsigned short RESERVED1; /*!< Reserved, 0x06 */ 217 | unsigned int CR; /*!< CRC Control register, Address offset: 0x08 */ 218 | } CRC_TypeDef; 219 | 220 | typedef struct 221 | { 222 | unsigned int CR; /*!< DAC control register, Address offset: 0x00 */ 223 | unsigned int SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 224 | unsigned int DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 225 | unsigned int DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 226 | unsigned int DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 227 | unsigned int DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 228 | unsigned int DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 229 | unsigned int DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 230 | unsigned int DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 231 | unsigned int DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 232 | unsigned int DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 233 | unsigned int DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 234 | unsigned int DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 235 | unsigned int SR; /*!< DAC status register, Address offset: 0x34 */ 236 | } DAC_TypeDef; 237 | 238 | typedef struct 239 | { 240 | unsigned int IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 241 | unsigned int CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 242 | unsigned int APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 243 | unsigned int APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 244 | }DBGMCU_TypeDef; 245 | 246 | typedef struct 247 | { 248 | unsigned int CR; /*!< DCMI control register 1, Address offset: 0x00 */ 249 | unsigned int SR; /*!< DCMI status register, Address offset: 0x04 */ 250 | unsigned int RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ 251 | unsigned int IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ 252 | unsigned int MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ 253 | unsigned int ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ 254 | unsigned int ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ 255 | unsigned int ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ 256 | unsigned int CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ 257 | unsigned int CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ 258 | unsigned int DR; /*!< DCMI data register, Address offset: 0x28 */ 259 | } DCMI_TypeDef; 260 | 261 | typedef struct 262 | { 263 | unsigned int CR; /*!< DMA stream x configuration register */ 264 | unsigned int NDTR; /*!< DMA stream x number of data register */ 265 | unsigned int PAR; /*!< DMA stream x peripheral address register */ 266 | unsigned int M0AR; /*!< DMA stream x memory 0 address register */ 267 | unsigned int M1AR; /*!< DMA stream x memory 1 address register */ 268 | unsigned int FCR; /*!< DMA stream x FIFO control register */ 269 | } DMA_Stream_TypeDef; 270 | 271 | typedef struct 272 | { 273 | unsigned int LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ 274 | unsigned int HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ 275 | unsigned int LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ 276 | unsigned int HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ 277 | } DMA_TypeDef; 278 | 279 | typedef struct 280 | { 281 | unsigned int MACCR; 282 | unsigned int MACFFR; 283 | unsigned int MACHTHR; 284 | unsigned int MACHTLR; 285 | unsigned int MACMIIAR; 286 | unsigned int MACMIIDR; 287 | unsigned int MACFCR; 288 | unsigned int MACVLANTR; /* 8 */ 289 | unsigned int RESERVED0[2]; 290 | unsigned int MACRWUFFR; /* 11 */ 291 | unsigned int MACPMTCSR; 292 | unsigned int RESERVED1[2]; 293 | unsigned int MACSR; /* 15 */ 294 | unsigned int MACIMR; 295 | unsigned int MACA0HR; 296 | unsigned int MACA0LR; 297 | unsigned int MACA1HR; 298 | unsigned int MACA1LR; 299 | unsigned int MACA2HR; 300 | unsigned int MACA2LR; 301 | unsigned int MACA3HR; 302 | unsigned int MACA3LR; /* 24 */ 303 | unsigned int RESERVED2[40]; 304 | unsigned int MMCCR; /* 65 */ 305 | unsigned int MMCRIR; 306 | unsigned int MMCTIR; 307 | unsigned int MMCRIMR; 308 | unsigned int MMCTIMR; /* 69 */ 309 | unsigned int RESERVED3[14]; 310 | unsigned int MMCTGFSCCR; /* 84 */ 311 | unsigned int MMCTGFMSCCR; 312 | unsigned int RESERVED4[5]; 313 | unsigned int MMCTGFCR; 314 | unsigned int RESERVED5[10]; 315 | unsigned int MMCRFCECR; 316 | unsigned int MMCRFAECR; 317 | unsigned int RESERVED6[10]; 318 | unsigned int MMCRGUFCR; 319 | unsigned int RESERVED7[334]; 320 | unsigned int PTPTSCR; 321 | unsigned int PTPSSIR; 322 | unsigned int PTPTSHR; 323 | unsigned int PTPTSLR; 324 | unsigned int PTPTSHUR; 325 | unsigned int PTPTSLUR; 326 | unsigned int PTPTSAR; 327 | unsigned int PTPTTHR; 328 | unsigned int PTPTTLR; 329 | unsigned int RESERVED8; 330 | unsigned int PTPTSSR; /* added for STM32F2xx */ 331 | unsigned int RESERVED9[565]; 332 | unsigned int DMABMR; 333 | unsigned int DMATPDR; 334 | unsigned int DMARPDR; 335 | unsigned int DMARDLAR; 336 | unsigned int DMATDLAR; 337 | unsigned int DMASR; 338 | unsigned int DMAOMR; 339 | unsigned int DMAIER; 340 | unsigned int DMAMFBOCR; 341 | unsigned int DMARSWTR; /* added for STM32F2xx */ 342 | unsigned int RESERVED10[8]; 343 | unsigned int DMACHTDR; 344 | unsigned int DMACHRDR; 345 | unsigned int DMACHTBAR; 346 | unsigned int DMACHRBAR; 347 | } ETH_TypeDef; 348 | 349 | typedef struct 350 | { 351 | unsigned int IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ 352 | unsigned int EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ 353 | unsigned int RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ 354 | unsigned int FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ 355 | unsigned int SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ 356 | unsigned int PR; /*!< EXTI Pending register, Address offset: 0x14 */ 357 | } EXTI_TypeDef; 358 | 359 | typedef struct 360 | { 361 | unsigned int ACR; /*!< FLASH access control register, Address offset: 0x00 */ 362 | unsigned int KEYR; /*!< FLASH key register, Address offset: 0x04 */ 363 | unsigned int OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ 364 | unsigned int SR; /*!< FLASH status register, Address offset: 0x0C */ 365 | unsigned int CR; /*!< FLASH control register, Address offset: 0x10 */ 366 | unsigned int OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ 367 | } FLASH_TypeDef; 368 | 369 | typedef struct 370 | { 371 | unsigned int BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ 372 | } FSMC_Bank1_TypeDef; 373 | 374 | typedef struct 375 | { 376 | unsigned int BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ 377 | } FSMC_Bank1E_TypeDef; 378 | 379 | typedef struct 380 | { 381 | unsigned int PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ 382 | unsigned int SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ 383 | unsigned int PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ 384 | unsigned int PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ 385 | unsigned int RESERVED0; /*!< Reserved, 0x70 */ 386 | unsigned int ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ 387 | } FSMC_Bank2_TypeDef; 388 | 389 | typedef struct 390 | { 391 | unsigned int PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ 392 | unsigned int SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ 393 | unsigned int PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ 394 | unsigned int PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ 395 | unsigned int RESERVED0; /*!< Reserved, 0x90 */ 396 | unsigned int ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ 397 | } FSMC_Bank3_TypeDef; 398 | 399 | typedef struct 400 | { 401 | unsigned int PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ 402 | unsigned int SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ 403 | unsigned int PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ 404 | unsigned int PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ 405 | unsigned int PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ 406 | } FSMC_Bank4_TypeDef; 407 | 408 | typedef struct 409 | { 410 | unsigned int MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 411 | unsigned int OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 412 | unsigned int OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 413 | unsigned int PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 414 | unsigned int IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 415 | unsigned int ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 416 | unsigned short BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ 417 | unsigned short BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ 418 | unsigned int LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 419 | unsigned int AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */ 420 | } GPIO_TypeDef; 421 | 422 | typedef struct 423 | { 424 | unsigned int MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 425 | unsigned int PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ 426 | unsigned int EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 427 | unsigned int RESERVED[2]; /*!< Reserved, 0x18-0x1C */ 428 | unsigned int CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ 429 | } SYSCFG_TypeDef; 430 | 431 | typedef struct 432 | { 433 | unsigned short CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 434 | unsigned short RESERVED0; /*!< Reserved, 0x02 */ 435 | unsigned short CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 436 | unsigned short RESERVED1; /*!< Reserved, 0x06 */ 437 | unsigned short OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ 438 | unsigned short RESERVED2; /*!< Reserved, 0x0A */ 439 | unsigned short OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ 440 | unsigned short RESERVED3; /*!< Reserved, 0x0E */ 441 | unsigned short DR; /*!< I2C Data register, Address offset: 0x10 */ 442 | unsigned short RESERVED4; /*!< Reserved, 0x12 */ 443 | unsigned short SR1; /*!< I2C Status register 1, Address offset: 0x14 */ 444 | unsigned short RESERVED5; /*!< Reserved, 0x16 */ 445 | unsigned short SR2; /*!< I2C Status register 2, Address offset: 0x18 */ 446 | unsigned short RESERVED6; /*!< Reserved, 0x1A */ 447 | unsigned short CCR; /*!< I2C Clock control register, Address offset: 0x1C */ 448 | unsigned short RESERVED7; /*!< Reserved, 0x1E */ 449 | unsigned short TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ 450 | unsigned short RESERVED8; /*!< Reserved, 0x22 */ 451 | } I2C_TypeDef; 452 | 453 | typedef struct 454 | { 455 | unsigned int KR; /*!< IWDG Key register, Address offset: 0x00 */ 456 | unsigned int PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 457 | unsigned int RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 458 | unsigned int SR; /*!< IWDG Status register, Address offset: 0x0C */ 459 | } IWDG_TypeDef; 460 | 461 | typedef struct 462 | { 463 | unsigned int CR; /*!< PWR power control register, Address offset: 0x00 */ 464 | unsigned int CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 465 | } PWR_TypeDef; 466 | 467 | typedef struct 468 | { 469 | unsigned int CR; /*!< RCC clock control register, Address offset: 0x00 */ 470 | unsigned int PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ 471 | unsigned int CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ 472 | unsigned int CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ 473 | unsigned int AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ 474 | unsigned int AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ 475 | unsigned int AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ 476 | unsigned int RESERVED0; /*!< Reserved, 0x1C */ 477 | unsigned int APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ 478 | unsigned int APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ 479 | unsigned int RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ 480 | unsigned int AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ 481 | unsigned int AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ 482 | unsigned int AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ 483 | unsigned int RESERVED2; /*!< Reserved, 0x3C */ 484 | unsigned int APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ 485 | unsigned int APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ 486 | unsigned int RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ 487 | unsigned int AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ 488 | unsigned int AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ 489 | unsigned int AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ 490 | unsigned int RESERVED4; /*!< Reserved, 0x5C */ 491 | unsigned int APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ 492 | unsigned int APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ 493 | unsigned int RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ 494 | unsigned int BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ 495 | unsigned int CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ 496 | unsigned int RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ 497 | unsigned int SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ 498 | unsigned int PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ 499 | } RCC_TypeDef; 500 | 501 | typedef struct 502 | { 503 | unsigned int TR; /*!< RTC time register, Address offset: 0x00 */ 504 | unsigned int DR; /*!< RTC date register, Address offset: 0x04 */ 505 | unsigned int CR; /*!< RTC control register, Address offset: 0x08 */ 506 | unsigned int ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 507 | unsigned int PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 508 | unsigned int WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 509 | unsigned int CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ 510 | unsigned int ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 511 | unsigned int ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 512 | unsigned int WPR; /*!< RTC write protection register, Address offset: 0x24 */ 513 | unsigned int RESERVED1; /*!< Reserved, 0x28 */ 514 | unsigned int RESERVED2; /*!< Reserved, 0x2C */ 515 | unsigned int TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 516 | unsigned int TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 517 | unsigned int RESERVED3; /*!< Reserved, 0x38 */ 518 | unsigned int RESERVED4; /*!< Reserved, 0x3C */ 519 | unsigned int TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 520 | unsigned int RESERVED5; /*!< Reserved, 0x44 */ 521 | unsigned int RESERVED6; /*!< Reserved, 0x48 */ 522 | unsigned int RESERVED7; /*!< Reserved, 0x4C */ 523 | unsigned int BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ 524 | unsigned int BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 525 | unsigned int BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 526 | unsigned int BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 527 | unsigned int BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 528 | unsigned int BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 529 | unsigned int BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 530 | unsigned int BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 531 | unsigned int BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 532 | unsigned int BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 533 | unsigned int BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 534 | unsigned int BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 535 | unsigned int BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 536 | unsigned int BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 537 | unsigned int BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 538 | unsigned int BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 539 | unsigned int BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 540 | unsigned int BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 541 | unsigned int BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 542 | unsigned int BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 543 | } RTC_TypeDef; 544 | 545 | typedef struct 546 | { 547 | unsigned int POWER; /*!< SDIO power control register, Address offset: 0x00 */ 548 | unsigned int CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ 549 | unsigned int ARG; /*!< SDIO argument register, Address offset: 0x08 */ 550 | unsigned int CMD; /*!< SDIO command register, Address offset: 0x0C */ 551 | unsigned int RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ 552 | unsigned int RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ 553 | unsigned int RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ 554 | unsigned int RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ 555 | unsigned int RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ 556 | unsigned int DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ 557 | unsigned int DLEN; /*!< SDIO data length register, Address offset: 0x28 */ 558 | unsigned int DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ 559 | unsigned int DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ 560 | unsigned int STA; /*!< SDIO status register, Address offset: 0x34 */ 561 | unsigned int ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ 562 | unsigned int MASK; /*!< SDIO mask register, Address offset: 0x3C */ 563 | unsigned int RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ 564 | unsigned int FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ 565 | unsigned int RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ 566 | unsigned int FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ 567 | } SDIO_TypeDef; 568 | 569 | typedef struct 570 | { 571 | unsigned short CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ 572 | unsigned short RESERVED0; /*!< Reserved, 0x02 */ 573 | unsigned short CR2; /*!< SPI control register 2, Address offset: 0x04 */ 574 | unsigned short RESERVED1; /*!< Reserved, 0x06 */ 575 | unsigned short SR; /*!< SPI status register, Address offset: 0x08 */ 576 | unsigned short RESERVED2; /*!< Reserved, 0x0A */ 577 | unsigned short DR; /*!< SPI data register, Address offset: 0x0C */ 578 | unsigned short RESERVED3; /*!< Reserved, 0x0E */ 579 | unsigned short CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 580 | unsigned short RESERVED4; /*!< Reserved, 0x12 */ 581 | unsigned short RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ 582 | unsigned short RESERVED5; /*!< Reserved, 0x16 */ 583 | unsigned short TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ 584 | unsigned short RESERVED6; /*!< Reserved, 0x1A */ 585 | unsigned short I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 586 | unsigned short RESERVED7; /*!< Reserved, 0x1E */ 587 | unsigned short I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 588 | unsigned short RESERVED8; /*!< Reserved, 0x22 */ 589 | } SPI_TypeDef; 590 | 591 | typedef struct 592 | { 593 | unsigned short CR1; /*!< TIM control register 1, Address offset: 0x00 */ 594 | unsigned short RESERVED0; /*!< Reserved, 0x02 */ 595 | unsigned short CR2; /*!< TIM control register 2, Address offset: 0x04 */ 596 | unsigned short RESERVED1; /*!< Reserved, 0x06 */ 597 | unsigned short SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 598 | unsigned short RESERVED2; /*!< Reserved, 0x0A */ 599 | unsigned short DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 600 | unsigned short RESERVED3; /*!< Reserved, 0x0E */ 601 | unsigned short SR; /*!< TIM status register, Address offset: 0x10 */ 602 | unsigned short RESERVED4; /*!< Reserved, 0x12 */ 603 | unsigned short EGR; /*!< TIM event generation register, Address offset: 0x14 */ 604 | unsigned short RESERVED5; /*!< Reserved, 0x16 */ 605 | unsigned short CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 606 | unsigned short RESERVED6; /*!< Reserved, 0x1A */ 607 | unsigned short CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 608 | unsigned short RESERVED7; /*!< Reserved, 0x1E */ 609 | unsigned short CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 610 | unsigned short RESERVED8; /*!< Reserved, 0x22 */ 611 | unsigned int CNT; /*!< TIM counter register, Address offset: 0x24 */ 612 | unsigned short PSC; /*!< TIM prescaler, Address offset: 0x28 */ 613 | unsigned short RESERVED9; /*!< Reserved, 0x2A */ 614 | unsigned int ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 615 | unsigned short RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 616 | unsigned short RESERVED10; /*!< Reserved, 0x32 */ 617 | unsigned int CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 618 | unsigned int CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 619 | unsigned int CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 620 | unsigned int CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 621 | unsigned short BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 622 | unsigned short RESERVED11; /*!< Reserved, 0x46 */ 623 | unsigned short DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 624 | unsigned short RESERVED12; /*!< Reserved, 0x4A */ 625 | unsigned short DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 626 | unsigned short RESERVED13; /*!< Reserved, 0x4E */ 627 | unsigned short OR; /*!< TIM option register, Address offset: 0x50 */ 628 | unsigned short RESERVED14; /*!< Reserved, 0x52 */ 629 | } TIM_TypeDef; 630 | 631 | typedef struct 632 | { 633 | unsigned short SR; /*!< USART Status register, Address offset: 0x00 */ 634 | unsigned short RESERVED0; /*!< Reserved, 0x02 */ 635 | unsigned short DR; /*!< USART Data register, Address offset: 0x04 */ 636 | unsigned short RESERVED1; /*!< Reserved, 0x06 */ 637 | unsigned short BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 638 | unsigned short RESERVED2; /*!< Reserved, 0x0A */ 639 | unsigned short CR1; /*!< USART Control register 1, Address offset: 0x0C */ 640 | unsigned short RESERVED3; /*!< Reserved, 0x0E */ 641 | unsigned short CR2; /*!< USART Control register 2, Address offset: 0x10 */ 642 | unsigned short RESERVED4; /*!< Reserved, 0x12 */ 643 | unsigned short CR3; /*!< USART Control register 3, Address offset: 0x14 */ 644 | unsigned short RESERVED5; /*!< Reserved, 0x16 */ 645 | unsigned short GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 646 | unsigned short RESERVED6; /*!< Reserved, 0x1A */ 647 | } USART_TypeDef; 648 | 649 | typedef struct 650 | { 651 | unsigned int CR; /*!< WWDG Control register, Address offset: 0x00 */ 652 | unsigned int CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 653 | unsigned int SR; /*!< WWDG Status register, Address offset: 0x08 */ 654 | } WWDG_TypeDef; 655 | 656 | typedef struct 657 | { 658 | unsigned int CR; /*!< CRYP control register, Address offset: 0x00 */ 659 | unsigned int SR; /*!< CRYP status register, Address offset: 0x04 */ 660 | unsigned int DR; /*!< CRYP data input register, Address offset: 0x08 */ 661 | unsigned int DOUT; /*!< CRYP data output register, Address offset: 0x0C */ 662 | unsigned int DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ 663 | unsigned int IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ 664 | unsigned int RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ 665 | unsigned int MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ 666 | unsigned int K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ 667 | unsigned int K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ 668 | unsigned int K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ 669 | unsigned int K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ 670 | unsigned int K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ 671 | unsigned int K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ 672 | unsigned int K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ 673 | unsigned int K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ 674 | unsigned int IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ 675 | unsigned int IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ 676 | unsigned int IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ 677 | unsigned int IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ 678 | } CRYP_TypeDef; 679 | 680 | typedef struct 681 | { 682 | unsigned int CR; /*!< HASH control register, Address offset: 0x00 */ 683 | unsigned int DIN; /*!< HASH data input register, Address offset: 0x04 */ 684 | unsigned int STR; /*!< HASH start register, Address offset: 0x08 */ 685 | unsigned int HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ 686 | unsigned int IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ 687 | unsigned int SR; /*!< HASH status register, Address offset: 0x24 */ 688 | unsigned int RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ 689 | unsigned int CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ 690 | } HASH_TypeDef; 691 | 692 | typedef struct 693 | { 694 | unsigned int CR; /*!< RNG control register, Address offset: 0x00 */ 695 | unsigned int SR; /*!< RNG status register, Address offset: 0x04 */ 696 | unsigned int DR; /*!< RNG data register, Address offset: 0x08 */ 697 | } RNG_TypeDef; 698 | 699 | InterruptType_Type* SCS = (InterruptType_Type*) 0xe000e000; //12 700 | ITM_Type* ITM = (ITM_Type*) 0xe0000000; //4096 701 | CoreDebug_Type* CoreDebug = (CoreDebug_Type*) 0xe000edf0; //16 702 | SysTick_Type* SysTick = (SysTick_Type*) 0xe000e010; //16 703 | NVIC_Type* NVIC = (NVIC_Type*) 0xe000e100; //3588 704 | SCB_Type* SCB = (SCB_Type*) 0xe000ed00; //116 705 | MPU_Type* MPU = (MPU_Type*) 0xe000ed90; //44 706 | TIM_TypeDef* TIM2 = (TIM_TypeDef*) 0x40000000; //84 707 | TIM_TypeDef* TIM3 = (TIM_TypeDef*) 0x40000400; //84 708 | TIM_TypeDef* TIM4 = (TIM_TypeDef*) 0x40000800; //84 709 | TIM_TypeDef* TIM5 = (TIM_TypeDef*) 0x40000c00; //84 710 | TIM_TypeDef* TIM6 = (TIM_TypeDef*) 0x40001000; //84 711 | TIM_TypeDef* TIM7 = (TIM_TypeDef*) 0x40001400; //84 712 | TIM_TypeDef* TIM12 = (TIM_TypeDef*) 0x40001800; //84 713 | TIM_TypeDef* TIM13 = (TIM_TypeDef*) 0x40001c00; //84 714 | TIM_TypeDef* TIM14 = (TIM_TypeDef*) 0x40002000; //84 715 | RTC_TypeDef* RTC = (RTC_TypeDef*) 0x40002800; //160 716 | WWDG_TypeDef* WWDG = (WWDG_TypeDef*) 0x40002c00; //12 717 | IWDG_TypeDef* IWDG = (IWDG_TypeDef*) 0x40003000; //16 718 | SPI_TypeDef* SPI2 = (SPI_TypeDef*) 0x40003800; //36 719 | SPI_TypeDef* SPI3 = (SPI_TypeDef*) 0x40003c00; //36 720 | USART_TypeDef* USART2 = (USART_TypeDef*) 0x40004400; //28 721 | USART_TypeDef* USART3 = (USART_TypeDef*) 0x40004800; //28 722 | USART_TypeDef* UART4 = (USART_TypeDef*) 0x40004c00; //28 723 | USART_TypeDef* UART5 = (USART_TypeDef*) 0x40005000; //28 724 | I2C_TypeDef* I2C1 = (I2C_TypeDef*) 0x40005400; //36 725 | I2C_TypeDef* I2C2 = (I2C_TypeDef*) 0x40005800; //36 726 | I2C_TypeDef* I2C3 = (I2C_TypeDef*) 0x40005c00; //36 727 | CAN_TypeDef* CAN1 = (CAN_TypeDef*) 0x40006400; //800 728 | CAN_TypeDef* CAN2 = (CAN_TypeDef*) 0x40006800; //800 729 | PWR_TypeDef* PWR = (PWR_TypeDef*) 0x40007000; //8 730 | DAC_TypeDef* DAC = (DAC_TypeDef*) 0x40007400; //56 731 | TIM_TypeDef* TIM1 = (TIM_TypeDef*) 0x40010000; //84 732 | TIM_TypeDef* TIM8 = (TIM_TypeDef*) 0x40010400; //84 733 | USART_TypeDef* USART1 = (USART_TypeDef*) 0x40011000; //28 734 | USART_TypeDef* USART6 = (USART_TypeDef*) 0x40011400; //28 735 | ADC_TypeDef* ADC1 = (ADC_TypeDef*) 0x40012000; //80 736 | ADC_TypeDef* ADC2 = (ADC_TypeDef*) 0x40012100; //80 737 | ADC_TypeDef* ADC3 = (ADC_TypeDef*) 0x40012200; //80 738 | ADC_Common_TypeDef* ADC = (ADC_Common_TypeDef*) 0x40012300; //12 739 | SDIO_TypeDef* SDIO = (SDIO_TypeDef*) 0x40012c00; //132 740 | SPI_TypeDef* SPI1 = (SPI_TypeDef*) 0x40013000; //36 741 | SYSCFG_TypeDef* SYSCFG = (SYSCFG_TypeDef*) 0x40013800; //36 742 | EXTI_TypeDef* EXTI = (EXTI_TypeDef*) 0x40013c00; //24 743 | TIM_TypeDef* TIM9 = (TIM_TypeDef*) 0x40014000; //84 744 | TIM_TypeDef* TIM10 = (TIM_TypeDef*) 0x40014400; //84 745 | TIM_TypeDef* TIM11 = (TIM_TypeDef*) 0x40014800; //84 746 | GPIO_TypeDef* GPIOA = (GPIO_TypeDef*) 0x40020000; //40 747 | GPIO_TypeDef* GPIOB = (GPIO_TypeDef*) 0x40020400; //40 748 | GPIO_TypeDef* GPIOC = (GPIO_TypeDef*) 0x40020800; //40 749 | GPIO_TypeDef* GPIOD = (GPIO_TypeDef*) 0x40020c00; //40 750 | GPIO_TypeDef* GPIOE = (GPIO_TypeDef*) 0x40021000; //40 751 | GPIO_TypeDef* GPIOF = (GPIO_TypeDef*) 0x40021400; //40 752 | GPIO_TypeDef* GPIOG = (GPIO_TypeDef*) 0x40021800; //40 753 | GPIO_TypeDef* GPIOH = (GPIO_TypeDef*) 0x40021c00; //40 754 | GPIO_TypeDef* GPIOI = (GPIO_TypeDef*) 0x40022000; //40 755 | CRC_TypeDef* CRC = (CRC_TypeDef*) 0x40023000; //12 756 | RCC_TypeDef* RCC = (RCC_TypeDef*) 0x40023800; //136 757 | FLASH_TypeDef* FLASH_R = (FLASH_TypeDef*) 0x40023c00; //24 758 | DMA_TypeDef* DMA1 = (DMA_TypeDef*) 0x40026000; //16 759 | DMA_Stream_TypeDef* DMA1_Stream0 = (DMA_Stream_TypeDef*) 0x40026010; //24 760 | DMA_Stream_TypeDef* DMA1_Stream1 = (DMA_Stream_TypeDef*) 0x40026028; //24 761 | DMA_Stream_TypeDef* DMA1_Stream2 = (DMA_Stream_TypeDef*) 0x40026040; //24 762 | DMA_Stream_TypeDef* DMA1_Stream3 = (DMA_Stream_TypeDef*) 0x40026058; //24 763 | DMA_Stream_TypeDef* DMA1_Stream4 = (DMA_Stream_TypeDef*) 0x40026070; //24 764 | DMA_Stream_TypeDef* DMA1_Stream5 = (DMA_Stream_TypeDef*) 0x40026088; //24 765 | DMA_Stream_TypeDef* DMA1_Stream6 = (DMA_Stream_TypeDef*) 0x400260a0; //24 766 | DMA_Stream_TypeDef* DMA1_Stream7 = (DMA_Stream_TypeDef*) 0x400260b8; //24 767 | DMA_TypeDef* DMA2 = (DMA_TypeDef*) 0x40026400; //16 768 | DMA_Stream_TypeDef* DMA2_Stream0 = (DMA_Stream_TypeDef*) 0x40026410; //24 769 | DMA_Stream_TypeDef* DMA2_Stream1 = (DMA_Stream_TypeDef*) 0x40026428; //24 770 | DMA_Stream_TypeDef* DMA2_Stream2 = (DMA_Stream_TypeDef*) 0x40026440; //24 771 | DMA_Stream_TypeDef* DMA2_Stream3 = (DMA_Stream_TypeDef*) 0x40026458; //24 772 | DMA_Stream_TypeDef* DMA2_Stream4 = (DMA_Stream_TypeDef*) 0x40026470; //24 773 | DMA_Stream_TypeDef* DMA2_Stream5 = (DMA_Stream_TypeDef*) 0x40026488; //24 774 | DMA_Stream_TypeDef* DMA2_Stream6 = (DMA_Stream_TypeDef*) 0x400264a0; //24 775 | DMA_Stream_TypeDef* DMA2_Stream7 = (DMA_Stream_TypeDef*) 0x400264b8; //24 776 | ETH_TypeDef* ETH = (ETH_TypeDef*) 0x40028000; //4184 777 | DCMI_TypeDef* DCMI = (DCMI_TypeDef*) 0x50050000; //44 778 | CRYP_TypeDef* CRYP = (CRYP_TypeDef*) 0x50060000; //80 779 | HASH_TypeDef* HASH = (HASH_TypeDef*) 0x50060400; //452 780 | RNG_TypeDef* RNG = (RNG_TypeDef*) 0x50060800; //12 781 | FSMC_Bank1_TypeDef* FSMC_Bank1_R = (FSMC_Bank1_TypeDef*) 0xa0000000; //32 782 | FSMC_Bank1E_TypeDef* FSMC_Bank1E_R = (FSMC_Bank1E_TypeDef*) 0xa0000104; //28 783 | FSMC_Bank2_TypeDef* FSMC_Bank2_R = (FSMC_Bank2_TypeDef*) 0xa0000060; //24 784 | FSMC_Bank3_TypeDef* FSMC_Bank3_R = (FSMC_Bank3_TypeDef*) 0xa0000080; //24 785 | FSMC_Bank4_TypeDef* FSMC_Bank4_R = (FSMC_Bank4_TypeDef*) 0xa00000a0; //20 786 | DBGMCU_TypeDef* DBGMCU = (DBGMCU_TypeDef*) 0xe0042000; //16 787 | -------------------------------------------------------------------------------- /core_cm3.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cm3.h 3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 4 | * @version V1.30 5 | * @date 30. October 2009 6 | * 7 | * @note 8 | * Copyright (C) 2009 ARM Limited. All rights reserved. 9 | * 10 | * @par 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 | * processor based microcontrollers. This file can be freely distributed 13 | * within development tools that are supporting such ARM based processors. 14 | * 15 | * @par 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 | * 22 | ******************************************************************************/ 23 | 24 | #ifndef __CM3_CORE_H__ 25 | #define __CM3_CORE_H__ 26 | 27 | /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration 28 | * 29 | * List of Lint messages which will be suppressed and not shown: 30 | * - Error 10: \n 31 | * register uint32_t __regBasePri __asm("basepri"); \n 32 | * Error 10: Expecting ';' 33 | * . 34 | * - Error 530: \n 35 | * return(__regBasePri); \n 36 | * Warning 530: Symbol '__regBasePri' (line 264) not initialized 37 | * . 38 | * - Error 550: \n 39 | * __regBasePri = (basePri & 0x1ff); \n 40 | * Warning 550: Symbol '__regBasePri' (line 271) not accessed 41 | * . 42 | * - Error 754: \n 43 | * uint32_t RESERVED0[24]; \n 44 | * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced 45 | * . 46 | * - Error 750: \n 47 | * #define __CM3_CORE_H__ \n 48 | * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced 49 | * . 50 | * - Error 528: \n 51 | * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n 52 | * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced 53 | * . 54 | * - Error 751: \n 55 | * } InterruptType_Type; \n 56 | * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced 57 | * . 58 | * Note: To re-enable a Message, insert a space before 'lint' * 59 | * 60 | */ 61 | 62 | /*lint -save */ 63 | /*lint -e10 */ 64 | /*lint -e530 */ 65 | /*lint -e550 */ 66 | /*lint -e754 */ 67 | /*lint -e750 */ 68 | /*lint -e528 */ 69 | /*lint -e751 */ 70 | 71 | 72 | /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions 73 | This file defines all structures and symbols for CMSIS core: 74 | - CMSIS version number 75 | - Cortex-M core registers and bitfields 76 | - Cortex-M core peripheral base address 77 | @{ 78 | */ 79 | 80 | #ifdef __cplusplus 81 | extern "C" { 82 | #endif 83 | 84 | #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ 85 | #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ 86 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 87 | 88 | #define __CORTEX_M (0x03) /*!< Cortex core */ 89 | 90 | #include /* Include standard types */ 91 | 92 | #if defined (__ICCARM__) 93 | #include /* IAR Intrinsics */ 94 | #endif 95 | 96 | 97 | #ifndef __NVIC_PRIO_BITS 98 | #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ 99 | #endif 100 | 101 | 102 | 103 | 104 | /** 105 | * IO definitions 106 | * 107 | * define access restrictions to peripheral registers 108 | */ 109 | 110 | #ifdef __cplusplus 111 | #define __I volatile /*!< defines 'read only' permissions */ 112 | #else 113 | #define __I volatile const /*!< defines 'read only' permissions */ 114 | #endif 115 | #define __O volatile /*!< defines 'write only' permissions */ 116 | #define __IO volatile /*!< defines 'read / write' permissions */ 117 | 118 | 119 | 120 | /******************************************************************************* 121 | * Register Abstraction 122 | ******************************************************************************/ 123 | /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register 124 | @{ 125 | */ 126 | 127 | 128 | /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC 129 | memory mapped structure for Nested Vectored Interrupt Controller (NVIC) 130 | @{ 131 | */ 132 | typedef struct 133 | { 134 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ 135 | uint32_t RESERVED0[24]; 136 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ 137 | uint32_t RSERVED1[24]; 138 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ 139 | uint32_t RESERVED2[24]; 140 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ 141 | uint32_t RESERVED3[24]; 142 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ 143 | uint32_t RESERVED4[56]; 144 | __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ 145 | uint32_t RESERVED5[644]; 146 | __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ 147 | } NVIC_Type; 148 | /*@}*/ /* end of group CMSIS_CM3_NVIC */ 149 | 150 | 151 | /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB 152 | memory mapped structure for System Control Block (SCB) 153 | @{ 154 | */ 155 | typedef struct 156 | { 157 | __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ 158 | __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ 159 | __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ 160 | __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ 161 | __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ 162 | __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ 163 | __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ 164 | __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ 165 | __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ 166 | __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ 167 | __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ 168 | __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ 169 | __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ 170 | __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ 171 | __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ 172 | __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ 173 | __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ 174 | __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ 175 | __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ 176 | } SCB_Type; 177 | 178 | /* SCB CPUID Register Definitions */ 179 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 180 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 181 | 182 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 183 | #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 184 | 185 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 186 | #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 187 | 188 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 189 | #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 190 | 191 | /* SCB Interrupt Control State Register Definitions */ 192 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 193 | #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 194 | 195 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 196 | #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 197 | 198 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 199 | #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 200 | 201 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 202 | #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 203 | 204 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 205 | #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 206 | 207 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 208 | #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 209 | 210 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 211 | #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 212 | 213 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 214 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 215 | 216 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 217 | #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 218 | 219 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 220 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 221 | 222 | /* SCB Interrupt Control State Register Definitions */ 223 | #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ 224 | #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ 225 | 226 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 227 | #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 228 | 229 | /* SCB Application Interrupt and Reset Control Register Definitions */ 230 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 231 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 232 | 233 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 234 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 235 | 236 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 237 | #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 238 | 239 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 240 | #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 241 | 242 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 243 | #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 244 | 245 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 246 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 247 | 248 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 249 | #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ 250 | 251 | /* SCB System Control Register Definitions */ 252 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 253 | #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 254 | 255 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 256 | #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 257 | 258 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 259 | #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 260 | 261 | /* SCB Configuration Control Register Definitions */ 262 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 263 | #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 264 | 265 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 266 | #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 267 | 268 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 269 | #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 270 | 271 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 272 | #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 273 | 274 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 275 | #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 276 | 277 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 278 | #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ 279 | 280 | /* SCB System Handler Control and State Register Definitions */ 281 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 282 | #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 283 | 284 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 285 | #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 286 | 287 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 288 | #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 289 | 290 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 291 | #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 292 | 293 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 294 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 295 | 296 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 297 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 298 | 299 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 300 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 301 | 302 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 303 | #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 304 | 305 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 306 | #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 307 | 308 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 309 | #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 310 | 311 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 312 | #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 313 | 314 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 315 | #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 316 | 317 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 318 | #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 319 | 320 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 321 | #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ 322 | 323 | /* SCB Configurable Fault Status Registers Definitions */ 324 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 325 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 326 | 327 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 328 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 329 | 330 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 331 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 332 | 333 | /* SCB Hard Fault Status Registers Definitions */ 334 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 335 | #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 336 | 337 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 338 | #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 339 | 340 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 341 | #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 342 | 343 | /* SCB Debug Fault Status Register Definitions */ 344 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 345 | #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 346 | 347 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 348 | #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 349 | 350 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 351 | #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 352 | 353 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 354 | #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 355 | 356 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 357 | #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ 358 | /*@}*/ /* end of group CMSIS_CM3_SCB */ 359 | 360 | 361 | /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick 362 | memory mapped structure for SysTick 363 | @{ 364 | */ 365 | typedef struct 366 | { 367 | __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ 368 | __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ 369 | __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ 370 | __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ 371 | } SysTick_Type; 372 | 373 | /* SysTick Control / Status Register Definitions */ 374 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 375 | #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 376 | 377 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 378 | #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 379 | 380 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 381 | #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 382 | 383 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 384 | #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 385 | 386 | /* SysTick Reload Register Definitions */ 387 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 388 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 389 | 390 | /* SysTick Current Register Definitions */ 391 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 392 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 393 | 394 | /* SysTick Calibration Register Definitions */ 395 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 396 | #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 397 | 398 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 399 | #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 400 | 401 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 402 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ 403 | /*@}*/ /* end of group CMSIS_CM3_SysTick */ 404 | 405 | 406 | /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM 407 | memory mapped structure for Instrumentation Trace Macrocell (ITM) 408 | @{ 409 | */ 410 | typedef struct 411 | { 412 | __O union 413 | { 414 | __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ 415 | __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ 416 | __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ 417 | } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ 418 | uint32_t RESERVED0[864]; 419 | __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ 420 | uint32_t RESERVED1[15]; 421 | __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ 422 | uint32_t RESERVED2[15]; 423 | __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ 424 | uint32_t RESERVED3[29]; 425 | __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ 426 | __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ 427 | __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ 428 | uint32_t RESERVED4[43]; 429 | __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ 430 | __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ 431 | uint32_t RESERVED5[6]; 432 | __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ 433 | __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ 434 | __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ 435 | __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ 436 | __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ 437 | __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ 438 | __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ 439 | __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ 440 | __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ 441 | __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ 442 | __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ 443 | __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ 444 | } ITM_Type; 445 | 446 | /* ITM Trace Privilege Register Definitions */ 447 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 448 | #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ 449 | 450 | /* ITM Trace Control Register Definitions */ 451 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 452 | #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 453 | 454 | #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ 455 | #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ 456 | 457 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 458 | #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 459 | 460 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 461 | #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 462 | 463 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 464 | #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 465 | 466 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 467 | #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 468 | 469 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 470 | #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 471 | 472 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 473 | #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ 474 | 475 | /* ITM Integration Write Register Definitions */ 476 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 477 | #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ 478 | 479 | /* ITM Integration Read Register Definitions */ 480 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 481 | #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ 482 | 483 | /* ITM Integration Mode Control Register Definitions */ 484 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 485 | #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ 486 | 487 | /* ITM Lock Status Register Definitions */ 488 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 489 | #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 490 | 491 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 492 | #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 493 | 494 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 495 | #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ 496 | /*@}*/ /* end of group CMSIS_CM3_ITM */ 497 | 498 | 499 | /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type 500 | memory mapped structure for Interrupt Type 501 | @{ 502 | */ 503 | typedef struct 504 | { 505 | uint32_t RESERVED0; 506 | __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ 507 | #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 508 | __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ 509 | #else 510 | uint32_t RESERVED1; 511 | #endif 512 | } InterruptType_Type; 513 | 514 | /* Interrupt Controller Type Register Definitions */ 515 | #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ 516 | #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ 517 | 518 | /* Auxiliary Control Register Definitions */ 519 | #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ 520 | #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ 521 | 522 | #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ 523 | #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ 524 | 525 | #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ 526 | #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ 527 | /*@}*/ /* end of group CMSIS_CM3_InterruptType */ 528 | 529 | 530 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) 531 | /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU 532 | memory mapped structure for Memory Protection Unit (MPU) 533 | @{ 534 | */ 535 | typedef struct 536 | { 537 | __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ 538 | __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ 539 | __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ 540 | __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ 541 | __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ 542 | __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ 543 | __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ 544 | __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ 545 | __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ 546 | __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ 547 | __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ 548 | } MPU_Type; 549 | 550 | /* MPU Type Register */ 551 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 552 | #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 553 | 554 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 555 | #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 556 | 557 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 558 | #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 559 | 560 | /* MPU Control Register */ 561 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 562 | #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 563 | 564 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 565 | #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 566 | 567 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 568 | #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 569 | 570 | /* MPU Region Number Register */ 571 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 572 | #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 573 | 574 | /* MPU Region Base Address Register */ 575 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 576 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 577 | 578 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 579 | #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 580 | 581 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 582 | #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 583 | 584 | /* MPU Region Attribute and Size Register */ 585 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ 586 | #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ 587 | 588 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ 589 | #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ 590 | 591 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ 592 | #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ 593 | 594 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ 595 | #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ 596 | 597 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ 598 | #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ 599 | 600 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ 601 | #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ 602 | 603 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 604 | #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 605 | 606 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 607 | #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 608 | 609 | #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ 610 | #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 611 | 612 | /*@}*/ /* end of group CMSIS_CM3_MPU */ 613 | #endif 614 | 615 | 616 | /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug 617 | memory mapped structure for Core Debug Register 618 | @{ 619 | */ 620 | typedef struct 621 | { 622 | __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ 623 | __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ 624 | __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ 625 | __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ 626 | } CoreDebug_Type; 627 | 628 | /* Debug Halting Control and Status Register */ 629 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 630 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 631 | 632 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 633 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 634 | 635 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 636 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 637 | 638 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 639 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 640 | 641 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 642 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 643 | 644 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 645 | #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 646 | 647 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 648 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 649 | 650 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 651 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 652 | 653 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 654 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 655 | 656 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 657 | #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 658 | 659 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 660 | #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 661 | 662 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 663 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 664 | 665 | /* Debug Core Register Selector Register */ 666 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 667 | #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 668 | 669 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 670 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ 671 | 672 | /* Debug Exception and Monitor Control Register */ 673 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 674 | #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 675 | 676 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 677 | #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 678 | 679 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 680 | #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 681 | 682 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 683 | #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 684 | 685 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 686 | #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 687 | 688 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 689 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 690 | 691 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 692 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 693 | 694 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 695 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 696 | 697 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 698 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 699 | 700 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 701 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 702 | 703 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 704 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 705 | 706 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 707 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 708 | 709 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 710 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 711 | /*@}*/ /* end of group CMSIS_CM3_CoreDebug */ 712 | 713 | 714 | /* Memory mapping of Cortex-M3 Hardware */ 715 | #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ 716 | #define ITM_BASE (0xE0000000) /*!< ITM Base Address */ 717 | #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ 718 | #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ 719 | #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ 720 | #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ 721 | 722 | #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ 723 | #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ 724 | #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ 725 | #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ 726 | #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ 727 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 728 | 729 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) 730 | #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ 731 | #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ 732 | #endif 733 | 734 | /*@}*/ /* end of group CMSIS_CM3_core_register */ 735 | 736 | 737 | /******************************************************************************* 738 | * Hardware Abstraction Layer 739 | ******************************************************************************/ 740 | 741 | #if defined ( __CC_ARM ) 742 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ 743 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 744 | 745 | #elif defined ( __ICCARM__ ) 746 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ 747 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ 748 | 749 | #elif defined ( __GNUC__ ) 750 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ 751 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ 752 | 753 | #elif defined ( __TASKING__ ) 754 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 755 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 756 | 757 | #endif 758 | 759 | 760 | /* ################### Compiler specific Intrinsics ########################### */ 761 | 762 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 763 | /* ARM armcc specific functions */ 764 | 765 | #define __enable_fault_irq __enable_fiq 766 | #define __disable_fault_irq __disable_fiq 767 | 768 | #define __NOP __nop 769 | #define __WFI __wfi 770 | #define __WFE __wfe 771 | #define __SEV __sev 772 | #define __ISB() __isb(0) 773 | #define __DSB() __dsb(0) 774 | #define __DMB() __dmb(0) 775 | #define __REV __rev 776 | #define __RBIT __rbit 777 | #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) 778 | #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) 779 | #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) 780 | #define __STREXB(value, ptr) __strex(value, ptr) 781 | #define __STREXH(value, ptr) __strex(value, ptr) 782 | #define __STREXW(value, ptr) __strex(value, ptr) 783 | 784 | 785 | /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ 786 | /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ 787 | /* intrinsic void __enable_irq(); */ 788 | /* intrinsic void __disable_irq(); */ 789 | 790 | 791 | /** 792 | * @brief Return the Process Stack Pointer 793 | * 794 | * @return ProcessStackPointer 795 | * 796 | * Return the actual process stack pointer 797 | */ 798 | extern uint32_t __get_PSP(void); 799 | 800 | /** 801 | * @brief Set the Process Stack Pointer 802 | * 803 | * @param topOfProcStack Process Stack Pointer 804 | * 805 | * Assign the value ProcessStackPointer to the MSP 806 | * (process stack pointer) Cortex processor register 807 | */ 808 | extern void __set_PSP(uint32_t topOfProcStack); 809 | 810 | /** 811 | * @brief Return the Main Stack Pointer 812 | * 813 | * @return Main Stack Pointer 814 | * 815 | * Return the current value of the MSP (main stack pointer) 816 | * Cortex processor register 817 | */ 818 | extern uint32_t __get_MSP(void); 819 | 820 | /** 821 | * @brief Set the Main Stack Pointer 822 | * 823 | * @param topOfMainStack Main Stack Pointer 824 | * 825 | * Assign the value mainStackPointer to the MSP 826 | * (main stack pointer) Cortex processor register 827 | */ 828 | extern void __set_MSP(uint32_t topOfMainStack); 829 | 830 | /** 831 | * @brief Reverse byte order in unsigned short value 832 | * 833 | * @param value value to reverse 834 | * @return reversed value 835 | * 836 | * Reverse byte order in unsigned short value 837 | */ 838 | extern uint32_t __REV16(uint16_t value); 839 | 840 | /** 841 | * @brief Reverse byte order in signed short value with sign extension to integer 842 | * 843 | * @param value value to reverse 844 | * @return reversed value 845 | * 846 | * Reverse byte order in signed short value with sign extension to integer 847 | */ 848 | extern int32_t __REVSH(int16_t value); 849 | 850 | 851 | #if (__ARMCC_VERSION < 400000) 852 | 853 | /** 854 | * @brief Remove the exclusive lock created by ldrex 855 | * 856 | * Removes the exclusive lock which is created by ldrex. 857 | */ 858 | extern void __CLREX(void); 859 | 860 | /** 861 | * @brief Return the Base Priority value 862 | * 863 | * @return BasePriority 864 | * 865 | * Return the content of the base priority register 866 | */ 867 | extern uint32_t __get_BASEPRI(void); 868 | 869 | /** 870 | * @brief Set the Base Priority value 871 | * 872 | * @param basePri BasePriority 873 | * 874 | * Set the base priority register 875 | */ 876 | extern void __set_BASEPRI(uint32_t basePri); 877 | 878 | /** 879 | * @brief Return the Priority Mask value 880 | * 881 | * @return PriMask 882 | * 883 | * Return state of the priority mask bit from the priority mask register 884 | */ 885 | extern uint32_t __get_PRIMASK(void); 886 | 887 | /** 888 | * @brief Set the Priority Mask value 889 | * 890 | * @param priMask PriMask 891 | * 892 | * Set the priority mask bit in the priority mask register 893 | */ 894 | extern void __set_PRIMASK(uint32_t priMask); 895 | 896 | /** 897 | * @brief Return the Fault Mask value 898 | * 899 | * @return FaultMask 900 | * 901 | * Return the content of the fault mask register 902 | */ 903 | extern uint32_t __get_FAULTMASK(void); 904 | 905 | /** 906 | * @brief Set the Fault Mask value 907 | * 908 | * @param faultMask faultMask value 909 | * 910 | * Set the fault mask register 911 | */ 912 | extern void __set_FAULTMASK(uint32_t faultMask); 913 | 914 | /** 915 | * @brief Return the Control Register value 916 | * 917 | * @return Control value 918 | * 919 | * Return the content of the control register 920 | */ 921 | extern uint32_t __get_CONTROL(void); 922 | 923 | /** 924 | * @brief Set the Control Register value 925 | * 926 | * @param control Control value 927 | * 928 | * Set the control register 929 | */ 930 | extern void __set_CONTROL(uint32_t control); 931 | 932 | #else /* (__ARMCC_VERSION >= 400000) */ 933 | 934 | /** 935 | * @brief Remove the exclusive lock created by ldrex 936 | * 937 | * Removes the exclusive lock which is created by ldrex. 938 | */ 939 | #define __CLREX __clrex 940 | 941 | /** 942 | * @brief Return the Base Priority value 943 | * 944 | * @return BasePriority 945 | * 946 | * Return the content of the base priority register 947 | */ 948 | static __INLINE uint32_t __get_BASEPRI(void) 949 | { 950 | register uint32_t __regBasePri __ASM("basepri"); 951 | return(__regBasePri); 952 | } 953 | 954 | /** 955 | * @brief Set the Base Priority value 956 | * 957 | * @param basePri BasePriority 958 | * 959 | * Set the base priority register 960 | */ 961 | static __INLINE void __set_BASEPRI(uint32_t basePri) 962 | { 963 | register uint32_t __regBasePri __ASM("basepri"); 964 | __regBasePri = (basePri & 0xff); 965 | } 966 | 967 | /** 968 | * @brief Return the Priority Mask value 969 | * 970 | * @return PriMask 971 | * 972 | * Return state of the priority mask bit from the priority mask register 973 | */ 974 | static __INLINE uint32_t __get_PRIMASK(void) 975 | { 976 | register uint32_t __regPriMask __ASM("primask"); 977 | return(__regPriMask); 978 | } 979 | 980 | /** 981 | * @brief Set the Priority Mask value 982 | * 983 | * @param priMask PriMask 984 | * 985 | * Set the priority mask bit in the priority mask register 986 | */ 987 | static __INLINE void __set_PRIMASK(uint32_t priMask) 988 | { 989 | register uint32_t __regPriMask __ASM("primask"); 990 | __regPriMask = (priMask); 991 | } 992 | 993 | /** 994 | * @brief Return the Fault Mask value 995 | * 996 | * @return FaultMask 997 | * 998 | * Return the content of the fault mask register 999 | */ 1000 | static __INLINE uint32_t __get_FAULTMASK(void) 1001 | { 1002 | register uint32_t __regFaultMask __ASM("faultmask"); 1003 | return(__regFaultMask); 1004 | } 1005 | 1006 | /** 1007 | * @brief Set the Fault Mask value 1008 | * 1009 | * @param faultMask faultMask value 1010 | * 1011 | * Set the fault mask register 1012 | */ 1013 | static __INLINE void __set_FAULTMASK(uint32_t faultMask) 1014 | { 1015 | register uint32_t __regFaultMask __ASM("faultmask"); 1016 | __regFaultMask = (faultMask & 1); 1017 | } 1018 | 1019 | /** 1020 | * @brief Return the Control Register value 1021 | * 1022 | * @return Control value 1023 | * 1024 | * Return the content of the control register 1025 | */ 1026 | static __INLINE uint32_t __get_CONTROL(void) 1027 | { 1028 | register uint32_t __regControl __ASM("control"); 1029 | return(__regControl); 1030 | } 1031 | 1032 | /** 1033 | * @brief Set the Control Register value 1034 | * 1035 | * @param control Control value 1036 | * 1037 | * Set the control register 1038 | */ 1039 | static __INLINE void __set_CONTROL(uint32_t control) 1040 | { 1041 | register uint32_t __regControl __ASM("control"); 1042 | __regControl = control; 1043 | } 1044 | 1045 | #endif /* __ARMCC_VERSION */ 1046 | 1047 | 1048 | 1049 | #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ 1050 | /* IAR iccarm specific functions */ 1051 | 1052 | #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ 1053 | #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ 1054 | 1055 | static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } 1056 | static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } 1057 | 1058 | #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ 1059 | static __INLINE void __WFI() { __ASM ("wfi"); } 1060 | static __INLINE void __WFE() { __ASM ("wfe"); } 1061 | static __INLINE void __SEV() { __ASM ("sev"); } 1062 | static __INLINE void __CLREX() { __ASM ("clrex"); } 1063 | 1064 | /* intrinsic void __ISB(void) */ 1065 | /* intrinsic void __DSB(void) */ 1066 | /* intrinsic void __DMB(void) */ 1067 | /* intrinsic void __set_PRIMASK(); */ 1068 | /* intrinsic void __get_PRIMASK(); */ 1069 | /* intrinsic void __set_FAULTMASK(); */ 1070 | /* intrinsic void __get_FAULTMASK(); */ 1071 | /* intrinsic uint32_t __REV(uint32_t value); */ 1072 | /* intrinsic uint32_t __REVSH(uint32_t value); */ 1073 | /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ 1074 | /* intrinsic unsigned long __LDREX(unsigned long *); */ 1075 | 1076 | 1077 | /** 1078 | * @brief Return the Process Stack Pointer 1079 | * 1080 | * @return ProcessStackPointer 1081 | * 1082 | * Return the actual process stack pointer 1083 | */ 1084 | extern uint32_t __get_PSP(void); 1085 | 1086 | /** 1087 | * @brief Set the Process Stack Pointer 1088 | * 1089 | * @param topOfProcStack Process Stack Pointer 1090 | * 1091 | * Assign the value ProcessStackPointer to the MSP 1092 | * (process stack pointer) Cortex processor register 1093 | */ 1094 | extern void __set_PSP(uint32_t topOfProcStack); 1095 | 1096 | /** 1097 | * @brief Return the Main Stack Pointer 1098 | * 1099 | * @return Main Stack Pointer 1100 | * 1101 | * Return the current value of the MSP (main stack pointer) 1102 | * Cortex processor register 1103 | */ 1104 | extern uint32_t __get_MSP(void); 1105 | 1106 | /** 1107 | * @brief Set the Main Stack Pointer 1108 | * 1109 | * @param topOfMainStack Main Stack Pointer 1110 | * 1111 | * Assign the value mainStackPointer to the MSP 1112 | * (main stack pointer) Cortex processor register 1113 | */ 1114 | extern void __set_MSP(uint32_t topOfMainStack); 1115 | 1116 | /** 1117 | * @brief Reverse byte order in unsigned short value 1118 | * 1119 | * @param value value to reverse 1120 | * @return reversed value 1121 | * 1122 | * Reverse byte order in unsigned short value 1123 | */ 1124 | extern uint32_t __REV16(uint16_t value); 1125 | 1126 | /** 1127 | * @brief Reverse bit order of value 1128 | * 1129 | * @param value value to reverse 1130 | * @return reversed value 1131 | * 1132 | * Reverse bit order of value 1133 | */ 1134 | extern uint32_t __RBIT(uint32_t value); 1135 | 1136 | /** 1137 | * @brief LDR Exclusive (8 bit) 1138 | * 1139 | * @param *addr address pointer 1140 | * @return value of (*address) 1141 | * 1142 | * Exclusive LDR command for 8 bit values) 1143 | */ 1144 | extern uint8_t __LDREXB(uint8_t *addr); 1145 | 1146 | /** 1147 | * @brief LDR Exclusive (16 bit) 1148 | * 1149 | * @param *addr address pointer 1150 | * @return value of (*address) 1151 | * 1152 | * Exclusive LDR command for 16 bit values 1153 | */ 1154 | extern uint16_t __LDREXH(uint16_t *addr); 1155 | 1156 | /** 1157 | * @brief LDR Exclusive (32 bit) 1158 | * 1159 | * @param *addr address pointer 1160 | * @return value of (*address) 1161 | * 1162 | * Exclusive LDR command for 32 bit values 1163 | */ 1164 | extern uint32_t __LDREXW(uint32_t *addr); 1165 | 1166 | /** 1167 | * @brief STR Exclusive (8 bit) 1168 | * 1169 | * @param value value to store 1170 | * @param *addr address pointer 1171 | * @return successful / failed 1172 | * 1173 | * Exclusive STR command for 8 bit values 1174 | */ 1175 | extern uint32_t __STREXB(uint8_t value, uint8_t *addr); 1176 | 1177 | /** 1178 | * @brief STR Exclusive (16 bit) 1179 | * 1180 | * @param value value to store 1181 | * @param *addr address pointer 1182 | * @return successful / failed 1183 | * 1184 | * Exclusive STR command for 16 bit values 1185 | */ 1186 | extern uint32_t __STREXH(uint16_t value, uint16_t *addr); 1187 | 1188 | /** 1189 | * @brief STR Exclusive (32 bit) 1190 | * 1191 | * @param value value to store 1192 | * @param *addr address pointer 1193 | * @return successful / failed 1194 | * 1195 | * Exclusive STR command for 32 bit values 1196 | */ 1197 | extern uint32_t __STREXW(uint32_t value, uint32_t *addr); 1198 | 1199 | 1200 | 1201 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ 1202 | /* GNU gcc specific functions */ 1203 | 1204 | static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } 1205 | static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } 1206 | 1207 | static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } 1208 | static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } 1209 | 1210 | static __INLINE void __NOP() { __ASM volatile ("nop"); } 1211 | static __INLINE void __WFI() { __ASM volatile ("wfi"); } 1212 | static __INLINE void __WFE() { __ASM volatile ("wfe"); } 1213 | static __INLINE void __SEV() { __ASM volatile ("sev"); } 1214 | static __INLINE void __ISB() { __ASM volatile ("isb"); } 1215 | static __INLINE void __DSB() { __ASM volatile ("dsb"); } 1216 | static __INLINE void __DMB() { __ASM volatile ("dmb"); } 1217 | static __INLINE void __CLREX() { __ASM volatile ("clrex"); } 1218 | 1219 | 1220 | /** 1221 | * @brief Return the Process Stack Pointer 1222 | * 1223 | * @return ProcessStackPointer 1224 | * 1225 | * Return the actual process stack pointer 1226 | */ 1227 | extern uint32_t __get_PSP(void); 1228 | 1229 | /** 1230 | * @brief Set the Process Stack Pointer 1231 | * 1232 | * @param topOfProcStack Process Stack Pointer 1233 | * 1234 | * Assign the value ProcessStackPointer to the MSP 1235 | * (process stack pointer) Cortex processor register 1236 | */ 1237 | extern void __set_PSP(uint32_t topOfProcStack); 1238 | 1239 | /** 1240 | * @brief Return the Main Stack Pointer 1241 | * 1242 | * @return Main Stack Pointer 1243 | * 1244 | * Return the current value of the MSP (main stack pointer) 1245 | * Cortex processor register 1246 | */ 1247 | extern uint32_t __get_MSP(void); 1248 | 1249 | /** 1250 | * @brief Set the Main Stack Pointer 1251 | * 1252 | * @param topOfMainStack Main Stack Pointer 1253 | * 1254 | * Assign the value mainStackPointer to the MSP 1255 | * (main stack pointer) Cortex processor register 1256 | */ 1257 | extern void __set_MSP(uint32_t topOfMainStack); 1258 | 1259 | /** 1260 | * @brief Return the Base Priority value 1261 | * 1262 | * @return BasePriority 1263 | * 1264 | * Return the content of the base priority register 1265 | */ 1266 | extern uint32_t __get_BASEPRI(void); 1267 | 1268 | /** 1269 | * @brief Set the Base Priority value 1270 | * 1271 | * @param basePri BasePriority 1272 | * 1273 | * Set the base priority register 1274 | */ 1275 | extern void __set_BASEPRI(uint32_t basePri); 1276 | 1277 | /** 1278 | * @brief Return the Priority Mask value 1279 | * 1280 | * @return PriMask 1281 | * 1282 | * Return state of the priority mask bit from the priority mask register 1283 | */ 1284 | extern uint32_t __get_PRIMASK(void); 1285 | 1286 | /** 1287 | * @brief Set the Priority Mask value 1288 | * 1289 | * @param priMask PriMask 1290 | * 1291 | * Set the priority mask bit in the priority mask register 1292 | */ 1293 | extern void __set_PRIMASK(uint32_t priMask); 1294 | 1295 | /** 1296 | * @brief Return the Fault Mask value 1297 | * 1298 | * @return FaultMask 1299 | * 1300 | * Return the content of the fault mask register 1301 | */ 1302 | extern uint32_t __get_FAULTMASK(void); 1303 | 1304 | /** 1305 | * @brief Set the Fault Mask value 1306 | * 1307 | * @param faultMask faultMask value 1308 | * 1309 | * Set the fault mask register 1310 | */ 1311 | extern void __set_FAULTMASK(uint32_t faultMask); 1312 | 1313 | /** 1314 | * @brief Return the Control Register value 1315 | * 1316 | * @return Control value 1317 | * 1318 | * Return the content of the control register 1319 | */ 1320 | extern uint32_t __get_CONTROL(void); 1321 | 1322 | /** 1323 | * @brief Set the Control Register value 1324 | * 1325 | * @param control Control value 1326 | * 1327 | * Set the control register 1328 | */ 1329 | extern void __set_CONTROL(uint32_t control); 1330 | 1331 | /** 1332 | * @brief Reverse byte order in integer value 1333 | * 1334 | * @param value value to reverse 1335 | * @return reversed value 1336 | * 1337 | * Reverse byte order in integer value 1338 | */ 1339 | extern uint32_t __REV(uint32_t value); 1340 | 1341 | /** 1342 | * @brief Reverse byte order in unsigned short value 1343 | * 1344 | * @param value value to reverse 1345 | * @return reversed value 1346 | * 1347 | * Reverse byte order in unsigned short value 1348 | */ 1349 | extern uint32_t __REV16(uint16_t value); 1350 | 1351 | /** 1352 | * @brief Reverse byte order in signed short value with sign extension to integer 1353 | * 1354 | * @param value value to reverse 1355 | * @return reversed value 1356 | * 1357 | * Reverse byte order in signed short value with sign extension to integer 1358 | */ 1359 | extern int32_t __REVSH(int16_t value); 1360 | 1361 | /** 1362 | * @brief Reverse bit order of value 1363 | * 1364 | * @param value value to reverse 1365 | * @return reversed value 1366 | * 1367 | * Reverse bit order of value 1368 | */ 1369 | extern uint32_t __RBIT(uint32_t value); 1370 | 1371 | /** 1372 | * @brief LDR Exclusive (8 bit) 1373 | * 1374 | * @param *addr address pointer 1375 | * @return value of (*address) 1376 | * 1377 | * Exclusive LDR command for 8 bit value 1378 | */ 1379 | extern uint8_t __LDREXB(uint8_t *addr); 1380 | 1381 | /** 1382 | * @brief LDR Exclusive (16 bit) 1383 | * 1384 | * @param *addr address pointer 1385 | * @return value of (*address) 1386 | * 1387 | * Exclusive LDR command for 16 bit values 1388 | */ 1389 | extern uint16_t __LDREXH(uint16_t *addr); 1390 | 1391 | /** 1392 | * @brief LDR Exclusive (32 bit) 1393 | * 1394 | * @param *addr address pointer 1395 | * @return value of (*address) 1396 | * 1397 | * Exclusive LDR command for 32 bit values 1398 | */ 1399 | extern uint32_t __LDREXW(uint32_t *addr); 1400 | 1401 | /** 1402 | * @brief STR Exclusive (8 bit) 1403 | * 1404 | * @param value value to store 1405 | * @param *addr address pointer 1406 | * @return successful / failed 1407 | * 1408 | * Exclusive STR command for 8 bit values 1409 | */ 1410 | extern uint32_t __STREXB(uint8_t value, uint8_t *addr); 1411 | 1412 | /** 1413 | * @brief STR Exclusive (16 bit) 1414 | * 1415 | * @param value value to store 1416 | * @param *addr address pointer 1417 | * @return successful / failed 1418 | * 1419 | * Exclusive STR command for 16 bit values 1420 | */ 1421 | extern uint32_t __STREXH(uint16_t value, uint16_t *addr); 1422 | 1423 | /** 1424 | * @brief STR Exclusive (32 bit) 1425 | * 1426 | * @param value value to store 1427 | * @param *addr address pointer 1428 | * @return successful / failed 1429 | * 1430 | * Exclusive STR command for 32 bit values 1431 | */ 1432 | extern uint32_t __STREXW(uint32_t value, uint32_t *addr); 1433 | 1434 | 1435 | #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ 1436 | /* TASKING carm specific functions */ 1437 | 1438 | /* 1439 | * The CMSIS functions have been implemented as intrinsics in the compiler. 1440 | * Please use "carm -?i" to get an up to date list of all instrinsics, 1441 | * Including the CMSIS ones. 1442 | */ 1443 | 1444 | #endif 1445 | 1446 | 1447 | /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface 1448 | Core Function Interface containing: 1449 | - Core NVIC Functions 1450 | - Core SysTick Functions 1451 | - Core Reset Functions 1452 | */ 1453 | /*@{*/ 1454 | 1455 | /* ########################## NVIC functions #################################### */ 1456 | 1457 | /** 1458 | * @brief Set the Priority Grouping in NVIC Interrupt Controller 1459 | * 1460 | * @param PriorityGroup is priority grouping field 1461 | * 1462 | * Set the priority grouping field using the required unlock sequence. 1463 | * The parameter priority_grouping is assigned to the field 1464 | * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. 1465 | * In case of a conflict between priority grouping and available 1466 | * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1467 | */ 1468 | static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1469 | { 1470 | uint32_t reg_value; 1471 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1472 | 1473 | reg_value = SCB->AIRCR; /* read old register configuration */ 1474 | reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 1475 | reg_value = (reg_value | 1476 | (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 1477 | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 1478 | SCB->AIRCR = reg_value; 1479 | } 1480 | 1481 | /** 1482 | * @brief Get the Priority Grouping from NVIC Interrupt Controller 1483 | * 1484 | * @return priority grouping field 1485 | * 1486 | * Get the priority grouping from NVIC Interrupt Controller. 1487 | * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. 1488 | */ 1489 | static __INLINE uint32_t NVIC_GetPriorityGrouping(void) 1490 | { 1491 | return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 1492 | } 1493 | 1494 | /** 1495 | * @brief Enable Interrupt in NVIC Interrupt Controller 1496 | * 1497 | * @param IRQn The positive number of the external interrupt to enable 1498 | * 1499 | * Enable a device specific interupt in the NVIC interrupt controller. 1500 | * The interrupt number cannot be a negative value. 1501 | */ 1502 | static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 1503 | { 1504 | NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ 1505 | } 1506 | 1507 | /** 1508 | * @brief Disable the interrupt line for external interrupt specified 1509 | * 1510 | * @param IRQn The positive number of the external interrupt to disable 1511 | * 1512 | * Disable a device specific interupt in the NVIC interrupt controller. 1513 | * The interrupt number cannot be a negative value. 1514 | */ 1515 | static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 1516 | { 1517 | NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 1518 | } 1519 | 1520 | /** 1521 | * @brief Read the interrupt pending bit for a device specific interrupt source 1522 | * 1523 | * @param IRQn The number of the device specifc interrupt 1524 | * @return 1 = interrupt pending, 0 = interrupt not pending 1525 | * 1526 | * Read the pending register in NVIC and return 1 if its status is pending, 1527 | * otherwise it returns 0 1528 | */ 1529 | static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 1530 | { 1531 | return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 1532 | } 1533 | 1534 | /** 1535 | * @brief Set the pending bit for an external interrupt 1536 | * 1537 | * @param IRQn The number of the interrupt for set pending 1538 | * 1539 | * Set the pending bit for the specified interrupt. 1540 | * The interrupt number cannot be a negative value. 1541 | */ 1542 | static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 1543 | { 1544 | NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 1545 | } 1546 | 1547 | /** 1548 | * @brief Clear the pending bit for an external interrupt 1549 | * 1550 | * @param IRQn The number of the interrupt for clear pending 1551 | * 1552 | * Clear the pending bit for the specified interrupt. 1553 | * The interrupt number cannot be a negative value. 1554 | */ 1555 | static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1556 | { 1557 | NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 1558 | } 1559 | 1560 | /** 1561 | * @brief Read the active bit for an external interrupt 1562 | * 1563 | * @param IRQn The number of the interrupt for read active bit 1564 | * @return 1 = interrupt active, 0 = interrupt not active 1565 | * 1566 | * Read the active register in NVIC and returns 1 if its status is active, 1567 | * otherwise it returns 0. 1568 | */ 1569 | static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 1570 | { 1571 | return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 1572 | } 1573 | 1574 | /** 1575 | * @brief Set the priority for an interrupt 1576 | * 1577 | * @param IRQn The number of the interrupt for set priority 1578 | * @param priority The priority to set 1579 | * 1580 | * Set the priority for the specified interrupt. The interrupt 1581 | * number can be positive to specify an external (device specific) 1582 | * interrupt, or negative to specify an internal (core) interrupt. 1583 | * 1584 | * Note: The priority cannot be set for every core interrupt. 1585 | */ 1586 | static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1587 | { 1588 | if(IRQn < 0) { 1589 | SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ 1590 | else { 1591 | NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 1592 | } 1593 | 1594 | /** 1595 | * @brief Read the priority for an interrupt 1596 | * 1597 | * @param IRQn The number of the interrupt for get priority 1598 | * @return The priority for the interrupt 1599 | * 1600 | * Read the priority for the specified interrupt. The interrupt 1601 | * number can be positive to specify an external (device specific) 1602 | * interrupt, or negative to specify an internal (core) interrupt. 1603 | * 1604 | * The returned priority value is automatically aligned to the implemented 1605 | * priority bits of the microcontroller. 1606 | * 1607 | * Note: The priority cannot be set for every core interrupt. 1608 | */ 1609 | static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 1610 | { 1611 | 1612 | if(IRQn < 0) { 1613 | return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ 1614 | else { 1615 | return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 1616 | } 1617 | 1618 | 1619 | /** 1620 | * @brief Encode the priority for an interrupt 1621 | * 1622 | * @param PriorityGroup The used priority group 1623 | * @param PreemptPriority The preemptive priority value (starting from 0) 1624 | * @param SubPriority The sub priority value (starting from 0) 1625 | * @return The encoded priority for the interrupt 1626 | * 1627 | * Encode the priority for an interrupt with the given priority group, 1628 | * preemptive priority value and sub priority value. 1629 | * In case of a conflict between priority grouping and available 1630 | * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 1631 | * 1632 | * The returned priority value can be used for NVIC_SetPriority(...) function 1633 | */ 1634 | static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1635 | { 1636 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1637 | uint32_t PreemptPriorityBits; 1638 | uint32_t SubPriorityBits; 1639 | 1640 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1641 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1642 | 1643 | return ( 1644 | ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 1645 | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 1646 | ); 1647 | } 1648 | 1649 | 1650 | /** 1651 | * @brief Decode the priority of an interrupt 1652 | * 1653 | * @param Priority The priority for the interrupt 1654 | * @param PriorityGroup The used priority group 1655 | * @param pPreemptPriority The preemptive priority value (starting from 0) 1656 | * @param pSubPriority The sub priority value (starting from 0) 1657 | * 1658 | * Decode an interrupt priority value with the given priority group to 1659 | * preemptive priority value and sub priority value. 1660 | * In case of a conflict between priority grouping and available 1661 | * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 1662 | * 1663 | * The priority value can be retrieved with NVIC_GetPriority(...) function 1664 | */ 1665 | static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 1666 | { 1667 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1668 | uint32_t PreemptPriorityBits; 1669 | uint32_t SubPriorityBits; 1670 | 1671 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1672 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1673 | 1674 | *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 1675 | *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 1676 | } 1677 | 1678 | 1679 | 1680 | /* ################################## SysTick function ############################################ */ 1681 | 1682 | #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) 1683 | 1684 | /** 1685 | * @brief Initialize and start the SysTick counter and its interrupt. 1686 | * 1687 | * @param ticks number of ticks between two interrupts 1688 | * @return 1 = failed, 0 = successful 1689 | * 1690 | * Initialise the system tick timer and its interrupt and start the 1691 | * system tick timer / counter in free running mode to generate 1692 | * periodical interrupts. 1693 | */ 1694 | static __INLINE uint32_t SysTick_Config(uint32_t ticks) 1695 | { 1696 | if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 1697 | 1698 | SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 1699 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ 1700 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ 1701 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1702 | SysTick_CTRL_TICKINT_Msk | 1703 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1704 | return (0); /* Function successful */ 1705 | } 1706 | 1707 | #endif 1708 | 1709 | 1710 | 1711 | 1712 | /* ################################## Reset function ############################################ */ 1713 | 1714 | /** 1715 | * @brief Initiate a system reset request. 1716 | * 1717 | * Initiate a system reset request to reset the MCU 1718 | */ 1719 | static __INLINE void NVIC_SystemReset(void) 1720 | { 1721 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 1722 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1723 | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 1724 | __DSB(); /* Ensure completion of memory access */ 1725 | while(1); /* wait until reset */ 1726 | } 1727 | 1728 | /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ 1729 | 1730 | 1731 | 1732 | /* ##################################### Debug In/Output function ########################################### */ 1733 | 1734 | /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface 1735 | Core Debug Interface containing: 1736 | - Core Debug Receive / Transmit Functions 1737 | - Core Debug Defines 1738 | - Core Debug Variables 1739 | */ 1740 | /*@{*/ 1741 | 1742 | extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ 1743 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ 1744 | 1745 | 1746 | /** 1747 | * @brief Outputs a character via the ITM channel 0 1748 | * 1749 | * @param ch character to output 1750 | * @return character to output 1751 | * 1752 | * The function outputs a character via the ITM channel 0. 1753 | * The function returns when no debugger is connected that has booked the output. 1754 | * It is blocking when a debugger is connected, but the previous character send is not transmitted. 1755 | */ 1756 | static __INLINE uint32_t ITM_SendChar (uint32_t ch) 1757 | { 1758 | if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ 1759 | (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 1760 | (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ 1761 | { 1762 | while (ITM->PORT[0].u32 == 0); 1763 | ITM->PORT[0].u8 = (uint8_t) ch; 1764 | } 1765 | return (ch); 1766 | } 1767 | 1768 | 1769 | /** 1770 | * @brief Inputs a character via variable ITM_RxBuffer 1771 | * 1772 | * @return received character, -1 = no character received 1773 | * 1774 | * The function inputs a character via variable ITM_RxBuffer. 1775 | * The function returns when no debugger is connected that has booked the output. 1776 | * It is blocking when a debugger is connected, but the previous character send is not transmitted. 1777 | */ 1778 | static __INLINE int ITM_ReceiveChar (void) { 1779 | int ch = -1; /* no character available */ 1780 | 1781 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 1782 | ch = ITM_RxBuffer; 1783 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 1784 | } 1785 | 1786 | return (ch); 1787 | } 1788 | 1789 | 1790 | /** 1791 | * @brief Check if a character via variable ITM_RxBuffer is available 1792 | * 1793 | * @return 1 = character available, 0 = no character available 1794 | * 1795 | * The function checks variable ITM_RxBuffer whether a character is available or not. 1796 | * The function returns '1' if a character is available and '0' if no character is available. 1797 | */ 1798 | static __INLINE int ITM_CheckChar (void) { 1799 | 1800 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 1801 | return (0); /* no character available */ 1802 | } else { 1803 | return (1); /* character available */ 1804 | } 1805 | } 1806 | 1807 | /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ 1808 | 1809 | 1810 | #ifdef __cplusplus 1811 | } 1812 | #endif 1813 | 1814 | /*@}*/ /* end of group CMSIS_CM3_core_definitions */ 1815 | 1816 | #endif /* __CM3_CORE_H__ */ 1817 | 1818 | /*lint -restore */ 1819 | --------------------------------------------------------------------------------