├── data ├── options.tcl ├── de0_nano.sdc └── pinmap.tcl ├── readme ├── block.png ├── toplevel.png ├── wave-init.png ├── wave-read.png ├── wave-refresh.png └── wave-write.png ├── rtl ├── toplevel.sdc ├── double_click.v ├── dnano_interface.v ├── fifo.v ├── toplevel.v └── sdram_controller.v ├── .gitignore ├── dram_controller.system ├── dram_controller.core ├── bench ├── double_click_tb.v ├── fifo_tb.v └── sdram_controller_tb.v ├── quartus ├── dram_controller.qpf ├── vsim-wave.do ├── dram_controller.qsf ├── pll_1m.v └── pll_100m.v └── readme.md /data/options.tcl: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /readme/block.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stffrdhrn/sdram-controller/HEAD/readme/block.png -------------------------------------------------------------------------------- /readme/toplevel.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stffrdhrn/sdram-controller/HEAD/readme/toplevel.png -------------------------------------------------------------------------------- /readme/wave-init.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stffrdhrn/sdram-controller/HEAD/readme/wave-init.png -------------------------------------------------------------------------------- /readme/wave-read.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stffrdhrn/sdram-controller/HEAD/readme/wave-read.png -------------------------------------------------------------------------------- /readme/wave-refresh.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stffrdhrn/sdram-controller/HEAD/readme/wave-refresh.png -------------------------------------------------------------------------------- /readme/wave-write.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stffrdhrn/sdram-controller/HEAD/readme/wave-write.png -------------------------------------------------------------------------------- /rtl/toplevel.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period "20ns" CLOCK_50 2 | derive_pll_clocks 3 | derive_clock_uncertainty 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | fusesoc.log 2 | 3 | *.bak 4 | *.rpt 5 | *.qws 6 | *.bmp 7 | PLLJ_PLLSPE_INFO.txt 8 | 9 | work/ 10 | greybox_tmp/ 11 | simulation/ 12 | db/ 13 | incremental_db/ 14 | output_files/ 15 | junk/ 16 | .qsys_edit/ 17 | -------------------------------------------------------------------------------- /dram_controller.system: -------------------------------------------------------------------------------- 1 | SAPI=1 2 | [main] 3 | name = dram_controller 4 | description = "Stafford toy dram controller for de0 Nano" 5 | 6 | backend = quartus 7 | 8 | [quartus] 9 | family = "Cyclone IV E" 10 | device = EP4CE22F17C6 11 | top_module = toplevel 12 | sdc_files = data/de0_nano.sdc 13 | tcl_files = data/pinmap.tcl 14 | data/options.tcl 15 | -------------------------------------------------------------------------------- /data/de0_nano.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "sys_clk_pad_i" -period 20.000ns [get_ports {sys_clk_pad_i}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | 10 | # Ignore timing on the reset input 11 | # set_false_path -through [get_nets {rst_n_pad_i}] 12 | 13 | -------------------------------------------------------------------------------- /dram_controller.core: -------------------------------------------------------------------------------- 1 | CAPI=1 2 | [main] 3 | description = "Stafford's toy dram controller for de0 nano" 4 | simulators = icarus 5 | 6 | [fileset rtl_files] 7 | files = 8 | rtl/dnano_interface.v 9 | rtl/double_click.v 10 | rtl/fifo.v 11 | rtl/sdram_controller.v 12 | file_type = verilogSource 13 | usage = sim synth 14 | 15 | # Files only used when building the system top level 16 | [fileset top_files] 17 | scope = private 18 | files = 19 | rtl/toplevel.v 20 | quartus/pll_100m.v 21 | quartus/pll_1m.v 22 | file_type = verilogSource 23 | usage = synth 24 | 25 | # File only used when building and running tests 26 | [fileset tb_files] 27 | scope = private 28 | files = 29 | bench/double_click_tb.v 30 | bench/fifo_tb.v 31 | bench/sdram_controller_tb.v 32 | file_type = verilogSource 33 | usage = sim 34 | 35 | [icarus] 36 | depend = vlog_tb_utils-1.0 37 | 38 | [simulator] 39 | depend = vlog_tb_utils-1.0 40 | toplevel = sdram_controller_tb 41 | 42 | #[provider] 43 | #name = github 44 | #user = stffrdhrn 45 | #repo = dram_controller 46 | -------------------------------------------------------------------------------- /bench/double_click_tb.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Test bench for double click detector module, simulates 3 | * - Reset 4 | * - 1-Click 5 | * - 2-Click - expect 2 -click 6 | * - Long-Click - expect 1-click 7 | * - Multi-Click - exepect 2-click 8 | */ 9 | module double_click_tb(); 10 | 11 | vlog_tb_utils vlog_tb_utils0(); 12 | 13 | reg button_r; 14 | reg rst_n, clk; 15 | wire single, double; 16 | 17 | initial 18 | begin 19 | button_r = 1'b0; 20 | rst_n = 1'b1; 21 | clk = 1'b0; 22 | end 23 | 24 | always 25 | #1 clk <= ~clk; 26 | 27 | initial 28 | begin 29 | #3 rst_n = 1'b0; 30 | #3 rst_n = 1'b1; 31 | 32 | #10 button_r = 1'b1; 33 | #100 button_r = 1'b0; 34 | 35 | 36 | #3 rst_n = 1'b0; 37 | #3 rst_n = 1'b1; 38 | 39 | #10 button_r = 1'b1; 40 | #4 button_r = 1'b0; 41 | #5 button_r = 1'b1; 42 | #3 button_r = 1'b0; 43 | 44 | #100 $finish; 45 | 46 | end 47 | 48 | double_click #(.WAIT_WIDTH(4)) double_clicki ( 49 | .button(button_r), .single(single), .double(double), 50 | .clk(clk), .rst_n(rst_n) 51 | ); 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /quartus/dram_controller.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.2 Build 153 07/15/2015 SJ Web Edition 22 | # Date created = 20:55:03 February 03, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "15.0" 27 | DATE = "20:55:03 February 03, 2017" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "dram_controller" 32 | -------------------------------------------------------------------------------- /bench/fifo_tb.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Test bentch for fifo's 3 | * 1. fifo fast write read slow 4 | * 2. fifo write flow read fast 5 | * 3. fifo slight difference between clocks 6 | */ 7 | module fifo_tb(); 8 | 9 | vlog_tb_utils vlog_tb_utils0(); 10 | 11 | reg rst_n, clka, clkb, rd, wr; 12 | reg [3:0] datain; 13 | 14 | wire [3:0] dataout_slow; 15 | wire [3:0] dataout_fast; 16 | wire full_fast, empty_slow, full_slow, empty_fast; 17 | 18 | initial 19 | begin 20 | rd = 0; 21 | wr = 0; 22 | datain = 4'b0000; 23 | rst_n = 1'b1; 24 | clka = 1'b0; 25 | clkb = 1'b0; 26 | end 27 | 28 | always 29 | #1 clka <= ~clka; 30 | 31 | always 32 | #13 clkb <= ~clkb; 33 | 34 | initial 35 | begin 36 | #3 rst_n = 1'b0; 37 | #3 rst_n = 1'b1; 38 | 39 | 40 | #5 datain = 4'b0110; 41 | wr = 1'b1; 42 | #2 wr = 1'b0; 43 | #5 datain = 4'b0000; 44 | 45 | #80 rd = 1'b1; 46 | #26 rd = 1'b0; 47 | 48 | #100 $finish; 49 | 50 | end 51 | 52 | fifo #(.BUS_WIDTH(4)) fifo_f2si ( 53 | .wr_data (datain), 54 | .rd_data (dataout_slow), 55 | .wr_clk (clka), 56 | .rd_clk (clkb), 57 | .wr (wr), 58 | .rd (rd), 59 | .full (full_fast), 60 | .empty_n (empty_slow), 61 | .rst_n (rst_n) 62 | ); 63 | 64 | fifo #(.BUS_WIDTH(4)) fifo_s2fi ( 65 | .wr_data (datain), 66 | .rd_data (dataout_fast), 67 | .wr_clk (clkb), 68 | .rd_clk (clka), 69 | .wr (wr), 70 | .rd (rd), 71 | .full (full_slow), 72 | .empty_n (empty_fast), 73 | .rst_n (rst_n) 74 | ); 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /rtl/double_click.v: -------------------------------------------------------------------------------- 1 | /* Input is a button 2 | * Detect if the button is double clicked or single clicked in 3 | * a time interval. Outputs are maintained until reset. 4 | */ 5 | 6 | module double_click ( 7 | button, 8 | 9 | single, double, 10 | 11 | clk, rst_n 12 | ); 13 | 14 | parameter WAIT_WIDTH = 19; 15 | 16 | input button; 17 | output single, double; 18 | input clk, rst_n; 19 | 20 | reg btn_now, btn_last, collect; 21 | 22 | reg [2:0] click_cnt; 23 | reg [WAIT_WIDTH-1:0] dbl_click_cnt; 24 | 25 | // if we are done counting and we have 1 click its single, else double 26 | assign single = (!dbl_click_cnt & (click_cnt == 3'b001)) ? 1'b1 : 1'b0; 27 | assign double = (!dbl_click_cnt & (click_cnt != 3'b001)) ? 1'b1 : 1'b0; 28 | 29 | // detect button down vs button up 30 | wire btn_down = btn_now & ~btn_last; 31 | //wire btn_up = ~btn_now & btn_last; 32 | always @ (negedge clk) 33 | if (~rst_n) 34 | { btn_last, btn_now } <= 2'b00; 35 | else 36 | { btn_last, btn_now } <= { btn_now, button }; 37 | 38 | // start down counter and count clicks 39 | always @ (posedge clk) 40 | if (~rst_n) 41 | begin 42 | click_cnt <= 3'd0; 43 | dbl_click_cnt <= {WAIT_WIDTH{1'b1}}; 44 | collect <= 1'b0; 45 | end 46 | else 47 | begin 48 | if (collect & (dbl_click_cnt != {WAIT_WIDTH{1'b0}})) 49 | dbl_click_cnt <= dbl_click_cnt - 1'b1; 50 | else 51 | dbl_click_cnt <= dbl_click_cnt; 52 | 53 | if (btn_down) 54 | begin 55 | collect <= 1'b1; 56 | click_cnt <= click_cnt + 1'b1; 57 | end 58 | else 59 | begin 60 | collect <= collect; 61 | click_cnt <= click_cnt; 62 | end 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /quartus/vsim-wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -radix binary /init_tb/haddr 4 | add wave -noupdate /init_tb/data_input 5 | add wave -noupdate /init_tb/data_output 6 | add wave -noupdate /init_tb/busy 7 | add wave -noupdate /init_tb/rd_enable 8 | add wave -noupdate /init_tb/wr_enable 9 | add wave -noupdate /init_tb/rst_n 10 | add wave -noupdate /init_tb/clk 11 | add wave -noupdate -radix hexadecimal /init_tb/addr 12 | add wave -noupdate /init_tb/bank_addr 13 | add wave -noupdate /init_tb/data 14 | add wave -noupdate /init_tb/clock_enable 15 | add wave -noupdate /init_tb/cs_n 16 | add wave -noupdate /init_tb/ras_n 17 | add wave -noupdate /init_tb/cas_n 18 | add wave -noupdate /init_tb/we_n 19 | add wave -noupdate /init_tb/data_mask_low 20 | add wave -noupdate /init_tb/data_mask_high 21 | add wave -noupdate /init_tb/sdram_controlleri/data_input_r 22 | add wave -noupdate /init_tb/sdram_controlleri/data_output_r 23 | add wave -noupdate -radix unsigned /init_tb/sdram_controlleri/state_cnt 24 | add wave -noupdate -radix unsigned /init_tb/sdram_controlleri/refresh_cnt 25 | add wave -noupdate /init_tb/sdram_controlleri/state 26 | TreeUpdate [SetDefaultTree] 27 | WaveRestoreCursors {{Cursor 1} {270 ps} 0} 28 | quietly wave cursor active 1 29 | configure wave -namecolwidth 289 30 | configure wave -valuecolwidth 132 31 | configure wave -justifyvalue left 32 | configure wave -signalnamewidth 0 33 | configure wave -snapdistance 10 34 | configure wave -datasetprefix 0 35 | configure wave -rowmargin 4 36 | configure wave -childrowmargin 2 37 | configure wave -gridoffset 0 38 | configure wave -gridperiod 1 39 | configure wave -griddelta 40 40 | configure wave -timeline 0 41 | configure wave -timelineunits ps 42 | update 43 | WaveRestoreZoom {0 ps} {110 ps} 44 | -------------------------------------------------------------------------------- /bench/sdram_controller_tb.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Testbench for sdram_controller modules, simulates: 3 | * - Iinit 4 | * - Write 5 | * - Read 6 | */ 7 | module sdram_controller_tb(); 8 | 9 | vlog_tb_utils vlog_tb_utils0(); 10 | 11 | /* HOST CONTROLLS */ 12 | reg [23:0] haddr; 13 | reg [15:0] data_input; 14 | wire [15:0] data_output; 15 | wire busy; 16 | reg rd_enable, wr_enable, rst_n, clk; 17 | 18 | /* SDRAM SIDE */ 19 | wire [12:0] addr; 20 | wire [1:0] bank_addr; 21 | wire [15:0] data; 22 | wire clock_enable, cs_n, ras_n, cas_n, we_n, data_mask_low, data_mask_high; 23 | 24 | reg [15:0] data_r; 25 | 26 | assign data = data_r; 27 | 28 | 29 | initial 30 | begin 31 | haddr = 24'd0; 32 | data_input = 16'd0; 33 | rd_enable = 1'b0; 34 | wr_enable = 1'b0; 35 | rst_n = 1'b1; 36 | clk = 1'b0; 37 | data_r = 16'hzzzz; 38 | end 39 | 40 | always 41 | #1 clk <= ~clk; 42 | 43 | initial 44 | begin 45 | #3 rst_n = 1'b0; 46 | #3 rst_n = 1'b1; 47 | 48 | #120 haddr = 24'hfedbed; 49 | data_input = 16'd3333; 50 | 51 | #3 wr_enable = 1'b1; 52 | #6 wr_enable = 1'b0; 53 | haddr = 24'd0; 54 | data_input = 16'd0; 55 | 56 | #120 haddr = 24'hbedfed; 57 | #3 rd_enable = 1'b1; 58 | #6 rd_enable = 1'b0; 59 | haddr = 24'd0; 60 | 61 | #8 data_r = 16'hbbbb; 62 | #2 data_r = 16'hzzzz; 63 | 64 | #1000 $finish; 65 | end 66 | 67 | 68 | sdram_controller sdram_controlleri ( 69 | /* HOST INTERFACE */ 70 | .wr_addr(haddr), 71 | .wr_data(data_input), 72 | .rd_data(data_output), 73 | .busy(busy), .rd_enable(rd_enable), .wr_enable(wr_enable), .rst_n(rst_n), .clk(clk), 74 | 75 | /* SDRAM SIDE */ 76 | .addr(addr), .bank_addr(bank_addr), .data(data), .clock_enable(clock_enable), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n), .data_mask_low(data_mask_low), .data_mask_high(data_mask_high) 77 | ); 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /rtl/dnano_interface.v: -------------------------------------------------------------------------------- 1 | /* De0 Nano interface for testing sdram controller 2 | * Handles interpreting buttons and switches 3 | * to talk to the sdram controller. 4 | */ 5 | 6 | module dnano_interface ( 7 | /* Human Interface */ 8 | button_n, dip, leds, 9 | 10 | /* Controller Interface */ 11 | haddr, // RW-FIFO- data1 12 | busy, // RW-FIFO- full 13 | 14 | wr_enable, // WR-FIFO- write 15 | wr_data, // WR-FIFO- data2 16 | 17 | rd_enable, //RO-FIFO- write 18 | 19 | rd_data, //RI-FIFO- data 20 | rd_rdy, // RI-FIFO-~empty 21 | rd_ack, // RI-FIFO- read 22 | 23 | /* basics */ 24 | rst_n, clk 25 | 26 | ); 27 | 28 | parameter HADDR_WIDTH = 24; 29 | 30 | // @ 1mhz 19bit (512K) is about 1/2 second 31 | // @ 100mhz 26bit (64M) is about 1/2 second 32 | localparam DOUBlE_CLICK_WAIT = 19; 33 | localparam LED_BLINK = 20; 34 | 35 | input button_n; 36 | input [3:0] dip; 37 | output [7:0] leds; 38 | 39 | output [HADDR_WIDTH-1:0] haddr; 40 | output [15:0] wr_data; 41 | input [15:0] rd_data; 42 | input busy; 43 | output rd_enable; 44 | input rd_rdy; 45 | output rd_ack; 46 | output wr_enable; 47 | 48 | input rst_n; 49 | input clk; 50 | 51 | wire [15:0] wr_data; 52 | reg [15:0] rd_data_r; 53 | reg [LED_BLINK-1:0] led_cnt; 54 | wire [7:0] leds; 55 | wire wr_enable; 56 | reg rd_ack_r; 57 | 58 | wire dbl_clck_rst_n; 59 | 60 | // When to reset the double click output 61 | // we want to reset after we know the sdram is busy 62 | // busy | rst_n 63 | // 0 0 - reset is on (be-low ) 64 | // 0 1 - reset is off (be high) 65 | // 1 0 - busy + reset (be-low) 66 | // 1 1 - busy is on (be-low) 67 | assign dbl_clck_rst_n = rst_n & ~busy; 68 | 69 | // expand the dip data from 4 to 16 bits 70 | assign wr_data = {dip, dip, ~dip, ~dip}; 71 | // toggle leds between sdram msb and lsb 72 | assign leds = led_cnt[LED_BLINK-1] ? rd_data_r[15:8] : rd_data_r[7:0]; 73 | 74 | assign haddr = {(HADDR_WIDTH/4){dip}}; 75 | assign rd_ack = rd_ack_r; 76 | 77 | // handle led counter should just loop every half second 78 | always @ (posedge clk) 79 | if (~rst_n) 80 | led_cnt <= {LED_BLINK{1'b0}}; 81 | else 82 | led_cnt <= led_cnt + 1'b1; 83 | 84 | 85 | always @ (posedge clk) 86 | if (~rst_n) 87 | begin 88 | rd_data_r <= 16'b0; 89 | rd_ack_r <= 1'b0; 90 | end 91 | else 92 | begin 93 | rd_ack_r <= rd_rdy; 94 | 95 | if (rd_rdy) 96 | rd_data_r <= rd_data; 97 | else 98 | rd_data_r <= rd_data_r; 99 | end 100 | 101 | double_click #(.WAIT_WIDTH(DOUBlE_CLICK_WAIT)) double_clicki ( 102 | .button (~button_n), 103 | .single (wr_enable), 104 | .double (rd_enable), 105 | .clk (clk), 106 | .rst_n (dbl_clck_rst_n) 107 | ); 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /rtl/fifo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * This is a 2 clock fifo used for transferring data between 3 | * clock domains. 4 | * 5 | * I assume here that the output (read) clock is >5X slower than the 6 | * input (write) clock. 7 | * 8 | * Also, the fifo is just 1 word deep. 9 | * 10 | * Changes 11 | * - 2015-07-03 issue when writing from low speed clock, empty_n goes 12 | * high and stays high. The reader side will see and read, but 13 | * after complete empty_n is still high. It will continue 14 | * to read until empty_n is lowered based on the write side 15 | * clock. 16 | * The empty_n should go low once the reader reads. 17 | * 18 | */ 19 | module fifo ( 20 | // Write side 21 | wr_clk, 22 | wr_data, 23 | wr, 24 | full, // means don't write any more 25 | 26 | // Read side 27 | rd_data, 28 | rd_clk, 29 | rd, 30 | empty_n, // also means we can read 31 | 32 | rst_n 33 | ); 34 | 35 | parameter BUS_WIDTH = 16; 36 | 37 | input [BUS_WIDTH-1:0] wr_data; 38 | input wr_clk; 39 | input wr; 40 | output full; // Low-Means in side can write 41 | 42 | output [BUS_WIDTH-1:0] rd_data; 43 | input rd_clk; 44 | input rd; 45 | output empty_n; // High-Means out side can read 46 | 47 | input rst_n; 48 | 49 | reg [BUS_WIDTH-1:0] wr_data_r; 50 | reg [BUS_WIDTH-1:0] rd_data; 51 | 52 | /* 53 | * these reg sets span accross 2 clock domtains 54 | * CLK WR | CLK RD 55 | * [wr_r] ------------------> | -> [wr_syn1] -> [wr_syn2] -\ 56 | * <- [wr_ack2] <- [wr_ack1] | ---------------------------/ 57 | * ^^^^^^^^^^ | 58 | * Set wr_r when we get a wr | increment counter when we get 59 | * Clr wr when we get wr_ack2 | wr_syn2, and syncronize data 60 | * 61 | */ 62 | reg wr_r, wr_syn1, wr_syn2, wr_ack1, wr_ack2; 63 | reg rd_r, rd_syn1, rd_syn2, rd_ack1, rd_ack2; 64 | reg wr_fifo_cnt; 65 | reg rd_fifo_cnt; 66 | 67 | assign full = wr_fifo_cnt == 1'b1; 68 | assign empty_n = rd_fifo_cnt == 1'b1; 69 | 70 | always @ (posedge rd_clk) 71 | if (~rst_n) 72 | begin 73 | rd_fifo_cnt <= 1'b0; 74 | {rd_ack2, rd_ack1} <= 2'b00; 75 | {wr_syn2, wr_syn1} <= 2'b00; 76 | end 77 | else 78 | begin 79 | 80 | {rd_ack2, rd_ack1} <= {rd_ack1, rd_syn2}; 81 | {wr_syn2, wr_syn1} <= {wr_syn1, wr_r}; 82 | 83 | if (rd) 84 | rd_r <= 1'b1; 85 | else if (rd_ack2) 86 | rd_r <= 1'b0; 87 | 88 | if (rd) 89 | rd_fifo_cnt <= 1'b0; 90 | if ({wr_syn2, wr_syn1} == 2'b01) // if we want to just do increment 1 time, we can check posedge 91 | rd_fifo_cnt <= 1'b1; 92 | 93 | if (wr_syn2) 94 | rd_data <= wr_data_r; 95 | end 96 | 97 | always @ (posedge wr_clk) 98 | if (~rst_n) 99 | begin 100 | wr_fifo_cnt <= 1'b0; 101 | {rd_syn2, rd_syn1} <= 2'b00; 102 | {wr_ack2, wr_ack1} <= 2'b00; 103 | end 104 | else 105 | begin 106 | {wr_ack2, wr_ack1} <= {wr_ack1, wr_syn2}; 107 | {rd_syn2, rd_syn1} <= {rd_syn1, rd_r}; 108 | 109 | if (wr) 110 | wr_r <= 1'b1; 111 | if (wr_ack2) 112 | wr_r <= 1'b0; 113 | 114 | if (wr) 115 | wr_fifo_cnt <= 1'b1; 116 | if ({rd_syn2, rd_syn1} == 2'b01) 117 | wr_fifo_cnt <= 1'b0; 118 | 119 | // register write data on write 120 | if (wr) 121 | wr_data_r <= wr_data; 122 | 123 | end 124 | 125 | 126 | endmodule -------------------------------------------------------------------------------- /readme.md: -------------------------------------------------------------------------------- 1 | # _SDRAM Memory Controller_ 2 | 3 | `CURRENT STATUS : stable` 4 | 5 | This is a very a simple sdram controller which works on the De0 Nano. The project 6 | also contains a simple push button interface for testing on the dev board. 7 | 8 | Basic features 9 | - Operates at 100Mhz, CAS 3, 32MB, 16-bit data 10 | - On reset will go into `INIT` sequnce 11 | - After `INIT` the controller sits in `IDLE` waiting for `REFRESH`, `READ` or `WRITE` 12 | - `REFRESH` operations are spaced evenly 8192 times every 32ms 13 | - `READ` is always single read with auto precharge 14 | - `WRITE` is always single write with auto precharge 15 | 16 | ``` 17 | 18 | Host Interface SDRAM Interface 19 | 20 | /-----------------------------\ 21 | | sdram_controller | 22 | ==> wr_addr addr ==> 23 | ==> wr_data bank_addr ==> 24 | --> wr_enable data <=> 25 | | clock_enable --> 26 | ==> rd_addr cs_n --> 27 | --> rd_enable ras_n --> 28 | <== rd_data cas_n --> 29 | <-- rd_ready we_n --> 30 | <-- busy data_mask_low --> 31 | | data_mask_high --> 32 | --> rst_n | 33 | --> clk | 34 | \-----------------------------/ 35 | 36 | ``` 37 | 38 | From the above diagram most signals should be pretty much self explainatory. Here are some important points for now. It will be expanded on later. 39 | - `wr_addr` and `rd_addr` are equivelant to the concatenation of `{bank, row, column}` 40 | - `rd_enable` should be set to high once an address is presented on the `addr` bus and we wish to read data. 41 | - `wr_enable` should be set to high once `addr` and `data` is presented on the bus 42 | - `busy` will go high when the read or write command is acknowledged. `busy` will go low when the write or read operation is complete. 43 | - `rd_ready` will go high when data `rd_data` is available on the `data` bus. 44 | - **NOTE** For single reads and writes `wr_enable` and `rd_enable` should be set low once `busy` is observed. This will protect from the controller thinking another request is needed if left higher any longer. 45 | 46 | ## Build 47 | 48 | The recommended way to build is to use `fusesoc`. The build steps are then: 49 | 50 | ``` 51 | # Build the project with quartus 52 | fusesoc build dram_controller 53 | # Program the project to de0 nano 54 | fusesoc pgm dram_controller 55 | 56 | # Build with icarus verilog and test 57 | fusesoc sim dram_controller --vcd 58 | gtkwave $fusebuild/dram_controller/sim-icarus/testlog.vcd 59 | 60 | # Run other test cases 61 | fusesoc sim --testbench fifo_tb dram_controller --vcd 62 | fusesoc sim --testbench double_click_tb dram_controller --vcd 63 | ``` 64 | 65 | 66 | ## Timings 67 | 68 | # Initialization 69 | ![wave init](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-init.png) 70 | 71 | Initialization process showing: 72 | - Precharge all banks 73 | - 2 refresh cycles 74 | - Mode programming 75 | 76 | # Refresh 77 | ![wave refresh](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-refresh.png) 78 | 79 | Refresh process showing: 80 | - Precharge all banks 81 | - Single Refresh 82 | 83 | # Writes 84 | ![wave write](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-write.png) 85 | 86 | Write operation showing: 87 | - Bank Activation & Row Address Strobe 88 | - Column Address Strobe with Auto Precharge set and Data on bus 89 | 90 | # Reads 91 | ![wave read](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-read.png) 92 | 93 | Read operation showing: 94 | - Bank Activation & Row Address Strobe 95 | - Column Address Strobe with Auto Precharge set 96 | - Data on bus 97 | 98 | 99 | ## Test Application 100 | 101 | ![Test Application](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/block.png) 102 | *Figure - test application block diagram* 103 | 104 | The test application provides a simple user interface for testing the functionality 105 | of the sdram controller. 106 | 107 | Basics: 108 | - The clock input should be 50Mhz (a pll multiplies it up to 100Mhz) 109 | - One push button is used for `reset` 110 | - A Second push button is used for `read` and `write` 111 | - single click for `write` 112 | - double click for `read` 113 | - A 4-bit dip switch is used for inputting addresses and data 114 | - Upon `reset` the read/write addresses are read from the dip switch 115 | - When `writing` the dip switch is data is written to the sdram 116 | - Address and data busses are greather than 4 bits, data is duplicated to fill the bus 117 | - 8 LEDs are used to display the data read from the sdram. The data but is 16-bits, high and low bytes are alternated on the LEDs about every half second. 118 | 119 | ## Project Status/TODO 120 | - [x] Compiles 121 | - [x] Simulated `Init` 122 | - [x] Simulated `Refresh` 123 | - [x] Simulated `Read` 124 | - [x] Simulated `Write` 125 | - [x] Confirmed in De0 Nano 126 | 127 | 128 | ## Project Setup 129 | This project has been developed with altera quartus II. 130 | 131 | ## License 132 | BSD 133 | 134 | ## Further Reading 135 | I didn't look at these when designing my controller. But it might be good to take a look at for ideas. 136 | - http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller - featured on hackaday 137 | - http://ladybug.xs4all.nl/arlet/fpga/source/sdram.v - Arlet's implementation from a comment on the hackaday article 138 | -------------------------------------------------------------------------------- /rtl/toplevel.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // 3 | // toplevel for dram controller de0 nano board 4 | // 5 | ////////////////////////////////////////////////////////////////////// 6 | // 7 | // This source file may be used and distributed without 8 | // restriction provided that this copyright statement is not 9 | // removed from the file and that any derivative work contains 10 | // the original copyright notice and the associated disclaimer. 11 | // 12 | // This source file is free software; you can redistribute it 13 | // and/or modify it under the terms of the GNU Lesser General 14 | // Public License as published by the Free Software Foundation; 15 | // either version 2.1 of the License, or (at your option) any 16 | // later version. 17 | // 18 | // This source is distributed in the hope that it will be 19 | // useful, but WITHOUT ANY WARRANTY; without even the implied 20 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 21 | // PURPOSE. See the GNU Lesser General Public License for more 22 | // details. 23 | // 24 | // You should have received a copy of the GNU Lesser General 25 | // Public License along with this source; if not, download it 26 | // from http://www.opencores.org/lgpl.shtml 27 | // 28 | ////////////////////////////////////////////////////////////////////// 29 | 30 | module toplevel ( 31 | input sys_clk_pad_i, 32 | input rst_n_pad_i, 33 | input btn_n_pad_i, 34 | 35 | output [1:0] sdram_ba_pad_o, 36 | output [12:0] sdram_a_pad_o, 37 | output sdram_cs_n_pad_o, 38 | output sdram_ras_pad_o, 39 | output sdram_cas_pad_o, 40 | output sdram_we_pad_o, 41 | inout [15:0] sdram_dq_pad_io, 42 | output [1:0] sdram_dqm_pad_o, 43 | output sdram_cke_pad_o, 44 | output sdram_clk_pad_o, 45 | 46 | inout [7:0] gpio0_io, /* LEDs */ 47 | input [3:0] gpio1_i /* DIPs */ 48 | ); 49 | 50 | wire clk100m; 51 | wire clk1m; 52 | 53 | assign sdram_clk_pad_o = clk100m; 54 | 55 | // PLLs 56 | pll_100m pll_100mi ( 57 | .inclk0 (sys_clk_pad_i), 58 | .c0 (clk100m) 59 | ); 60 | 61 | pll_1m pll_1mi ( 62 | .inclk0 (sys_clk_pad_i), 63 | .c0 (clk1m) 64 | ); 65 | 66 | // Cross Clock FIFOs 67 | /* Address 24-bit and 16-bit Data transfers from in:1m out:100m */ 68 | 69 | /* 1 mhz side wires */ 70 | wire [39:0] wr_fifo; 71 | wire wr_enable; /* wr_enable ] <-> [ wr : wr_enable to push fifo */ 72 | wire wr_full; /* wr_full ] <-> [ full : signal that we are full */ 73 | /* 100mhz side wires */ 74 | wire [39:0] wro_fifo; 75 | wire ctrl_busy; /* rd ] <-> [ busy : pop fifo when ctrl not busy */ 76 | wire ctrl_wr_enable; /* .empty_n-wr_enable : signal ctrl data is ready */ 77 | 78 | fifo #(.BUS_WIDTH(40)) wr_fifoi ( 79 | .wr_clk (clk1m), 80 | .rd_clk (clk100m), 81 | .wr_data (wr_fifo), 82 | .rd_data (wro_fifo), 83 | .rd (ctrl_busy), 84 | .wr (wr_enable), 85 | .full (wr_full), 86 | .empty_n (ctrl_wr_enable), 87 | .rst_n (rst_n_pad_i) 88 | ); 89 | 90 | /* Address 24-bit transfers from in:1m out:100m */ 91 | /* 1 mhz side wires */ 92 | wire rd_enable; /* rd_enable -wr : rd_enable to push rd addr to fifo */ 93 | wire rdaddr_full;/* rdaddr_full-full : signal we cannot read more */ 94 | 95 | /* 100mhz side wires */ 96 | wire [23:0] rdao_fifo; 97 | wire ctrl_rd_enable; /* empty_n - rd_enable: signal ctrl addr ready */ 98 | 99 | fifo #(.BUS_WIDTH(24)) rdaddr_fifoi ( 100 | .wr_clk (clk1m), 101 | .rd_clk (clk100m), 102 | .wr_data (wr_fifo[39:16]), 103 | .rd_data (rdao_fifo), 104 | .rd (ctrl_busy), 105 | .wr (rd_enable), 106 | .full (rdaddr_full), 107 | .empty_n (ctrl_rd_enable), 108 | .rst_n (rst_n_pad_i) 109 | ); 110 | 111 | /* 100mhz side wires */ 112 | wire [15:0] rddo_fifo; 113 | wire ctrl_rd_ready; /* wr - rd_ready - push data from dram to fifo */ 114 | 115 | /* 1mhz side wires */ 116 | wire [15:0] rddata_fifo; 117 | wire rd_ready; /* rd_ready-empty_n- signal interface data ready */ 118 | wire rd_ack; /* rd_ack - rd - pop fifo after data read */ 119 | 120 | /* Incoming 16-bit data transfers from in:100m out:1m */ 121 | fifo #(.BUS_WIDTH(16)) rddata_fifoi ( 122 | .wr_clk (clk100m), 123 | .rd_clk (clk1m), 124 | .wr_data (rddo_fifo), 125 | .rd_data (rddata_fifo), 126 | .rd (rd_ack), 127 | .wr (ctrl_rd_ready), 128 | .full (), 129 | .empty_n (rd_ready), 130 | .rst_n (rst_n_pad_i) 131 | ); 132 | 133 | 134 | /* SDRAM */ 135 | 136 | 137 | sdram_controller sdram_controlleri ( 138 | /* HOST INTERFACE */ 139 | .wr_addr (wro_fifo[39:16]), 140 | .wr_data (wro_fifo[15:0]), 141 | .wr_enable (ctrl_wr_enable), 142 | 143 | .rd_addr (rdao_fifo), 144 | .rd_data (rddo_fifo), 145 | .rd_ready (ctrl_rd_ready), 146 | .rd_enable (ctrl_rd_enable), 147 | 148 | .busy (ctrl_busy), 149 | .rst_n (rst_n_pad_i), 150 | .clk (clk100m), 151 | 152 | /* SDRAM SIDE */ 153 | .addr (sdram_a_pad_o), 154 | .bank_addr (sdram_ba_pad_o), 155 | .data (sdram_dq_pad_io), 156 | .clock_enable (sdram_cke_pad_o), 157 | .cs_n (sdram_cs_n_pad_o), 158 | .ras_n (sdram_ras_pad_o), 159 | .cas_n (sdram_cas_pad_o), 160 | .we_n (sdram_we_pad_o), 161 | .data_mask_low (sdram_dqm_pad_o[0]), 162 | .data_mask_high(sdram_dqm_pad_o[1]) 163 | ); 164 | 165 | wire busy; 166 | 167 | assign busy = wr_full | rdaddr_full; 168 | 169 | dnano_interface #(.HADDR_WIDTH(24)) dnano_interfacei ( 170 | /* Human Interface */ 171 | .button_n (btn_n_pad_i), 172 | .dip (gpio1_i), 173 | .leds (gpio0_io), 174 | 175 | /* Controller Interface */ 176 | .haddr (wr_fifo[39:16]),// RW-FIFO- data1 177 | .busy (busy), // RW-FIFO- full 178 | 179 | .wr_enable (wr_enable), // WR-FIFO- write 180 | .wr_data (wr_fifo[15:00]),// WR-FIFO- data2 181 | 182 | .rd_enable (rd_enable), // RO-FIFO- write 183 | 184 | .rd_data (rddata_fifo), // RI-FIFO- data 185 | .rd_rdy (rd_ready), // RI-FIFO-~empty 186 | .rd_ack (rd_ack), // RI-FIFO- read 187 | 188 | /* basics */ 189 | .rst_n (rst_n_pad_i), 190 | .clk (clk1m) 191 | 192 | ); 193 | 194 | endmodule // toplevel 195 | -------------------------------------------------------------------------------- /data/pinmap.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Clock / Reset 3 | # 4 | set_location_assignment PIN_J15 -to rst_n_pad_i 5 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i 6 | set_location_assignment PIN_E1 -to btn_n_pad_i 7 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to btn_n_pad_i 8 | set_location_assignment PIN_R8 -to sys_clk_pad_i 9 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i 10 | 11 | # 12 | # UART0: RX <-> GPIO_2[0] (Pin 5, bottom header) 13 | # TX <-> GPIO_2[1] (Pin 6, bottom header) 14 | # 15 | set_location_assignment PIN_A14 -to uart0_srx_pad_i 16 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i 17 | set_location_assignment PIN_B16 -to uart0_stx_pad_o 18 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o 19 | 20 | # 21 | # I2C0: Connected to the EEPROM and Accelerometer 22 | # 23 | set_location_assignment PIN_F2 -to i2c0_scl_io 24 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c0_scl_io 25 | set_location_assignment PIN_F1 -to i2c0_sda_io 26 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c0_sda_io 27 | 28 | # 29 | # Accelerometer specific lines 30 | # 31 | set_location_assignment PIN_M2 -to accelerometer_irq_i 32 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to accelerometer_irq_i 33 | set_location_assignment PIN_G5 -to accelerometer_cs_o 34 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to accelerometer_cs_o 35 | 36 | # 37 | # I2C1: sda <-> GPIO_2[6] (Pin 11, bottom header) 38 | # scl <-> GPIO_2[7] (Pin 12, bottom header) 39 | # 40 | set_location_assignment PIN_D15 -to i2c1_sda_io 41 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c1_sda_io 42 | set_location_assignment PIN_D14 -to i2c1_scl_io 43 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c1_scl_io 44 | 45 | # 46 | # SPI0: Connected to the EPCS 47 | # 48 | set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" 49 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" 50 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" 51 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" 52 | set_location_assignment PIN_C1 -to spi0_mosi_o 53 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_mosi_o 54 | set_location_assignment PIN_H2 -to spi0_miso_i 55 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_miso_i 56 | set_location_assignment PIN_H1 -to spi0_sck_o 57 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_sck_o 58 | set_location_assignment PIN_D2 -to spi0_ss_o 59 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_ss_o 60 | 61 | # 62 | # SPI1: Connected to the AD converter 63 | # 64 | set_location_assignment PIN_B10 -to spi1_mosi_o 65 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_mosi_o 66 | set_location_assignment PIN_A9 -to spi1_miso_i 67 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_miso_i 68 | set_location_assignment PIN_B14 -to spi1_sck_o 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_sck_o 70 | set_location_assignment PIN_A10 -to spi1_ss_o 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_ss_o 72 | 73 | # 74 | # SPI2: MOSI <-> GPIO_2[2] (Pin 7, bottom header) 75 | # MISO <-> GPIO_2[3] (Pin 8, bottom header) 76 | # SCK <-> GPIO_2[4] (Pin 9, bottom header) 77 | # SS <-> GPIO_2[5] (Pin 10, bottom header) 78 | # 79 | set_location_assignment PIN_C14 -to spi2_mosi_o 80 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_mosi_o 81 | set_location_assignment PIN_C16 -to spi2_miso_i 82 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_miso_i 83 | set_location_assignment PIN_C15 -to spi2_sck_o 84 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_sck_o 85 | set_location_assignment PIN_D16 -to spi2_ss_o 86 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_ss_o 87 | 88 | # 89 | # SDRAM 90 | # 91 | set_location_assignment PIN_P2 -to sdram_a_pad_o[0] 92 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[0] 93 | set_location_assignment PIN_N5 -to sdram_a_pad_o[1] 94 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[1] 95 | set_location_assignment PIN_N6 -to sdram_a_pad_o[2] 96 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[2] 97 | set_location_assignment PIN_M8 -to sdram_a_pad_o[3] 98 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[3] 99 | set_location_assignment PIN_P8 -to sdram_a_pad_o[4] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[4] 101 | set_location_assignment PIN_T7 -to sdram_a_pad_o[5] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[5] 103 | set_location_assignment PIN_N8 -to sdram_a_pad_o[6] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[6] 105 | set_location_assignment PIN_T6 -to sdram_a_pad_o[7] 106 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[7] 107 | set_location_assignment PIN_R1 -to sdram_a_pad_o[8] 108 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[8] 109 | set_location_assignment PIN_P1 -to sdram_a_pad_o[9] 110 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[9] 111 | set_location_assignment PIN_N2 -to sdram_a_pad_o[10] 112 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[10] 113 | set_location_assignment PIN_N1 -to sdram_a_pad_o[11] 114 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[11] 115 | set_location_assignment PIN_L4 -to sdram_a_pad_o[12] 116 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[12] 117 | 118 | set_location_assignment PIN_G2 -to sdram_dq_pad_io[0] 119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[0] 120 | set_location_assignment PIN_G1 -to sdram_dq_pad_io[1] 121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[1] 122 | set_location_assignment PIN_L8 -to sdram_dq_pad_io[2] 123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[2] 124 | set_location_assignment PIN_K5 -to sdram_dq_pad_io[3] 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[3] 126 | set_location_assignment PIN_K2 -to sdram_dq_pad_io[4] 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[4] 128 | set_location_assignment PIN_J2 -to sdram_dq_pad_io[5] 129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[5] 130 | set_location_assignment PIN_J1 -to sdram_dq_pad_io[6] 131 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[6] 132 | set_location_assignment PIN_R7 -to sdram_dq_pad_io[7] 133 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[7] 134 | set_location_assignment PIN_T4 -to sdram_dq_pad_io[8] 135 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[8] 136 | set_location_assignment PIN_T2 -to sdram_dq_pad_io[9] 137 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[9] 138 | set_location_assignment PIN_T3 -to sdram_dq_pad_io[10] 139 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[10] 140 | set_location_assignment PIN_R3 -to sdram_dq_pad_io[11] 141 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[11] 142 | set_location_assignment PIN_R5 -to sdram_dq_pad_io[12] 143 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[12] 144 | set_location_assignment PIN_P3 -to sdram_dq_pad_io[13] 145 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[13] 146 | set_location_assignment PIN_N3 -to sdram_dq_pad_io[14] 147 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[14] 148 | set_location_assignment PIN_K1 -to sdram_dq_pad_io[15] 149 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[15] 150 | 151 | set_location_assignment PIN_R6 -to sdram_dqm_pad_o[0] 152 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[0] 153 | set_location_assignment PIN_T5 -to sdram_dqm_pad_o[1] 154 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[1] 155 | 156 | set_location_assignment PIN_M7 -to sdram_ba_pad_o[0] 157 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[0] 158 | set_location_assignment PIN_M6 -to sdram_ba_pad_o[1] 159 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[1] 160 | 161 | set_location_assignment PIN_L1 -to sdram_cas_pad_o 162 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cas_pad_o 163 | 164 | set_location_assignment PIN_L7 -to sdram_cke_pad_o 165 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cke_pad_o 166 | 167 | set_location_assignment PIN_P6 -to sdram_cs_n_pad_o 168 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cs_n_pad_o 169 | 170 | set_location_assignment PIN_L2 -to sdram_ras_pad_o 171 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ras_pad_o 172 | 173 | set_location_assignment PIN_C2 -to sdram_we_pad_o 174 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_pad_o 175 | 176 | set_location_assignment PIN_R4 -to sdram_clk_pad_o 177 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o 178 | 179 | # 180 | # GPIO0 (LEDs) 181 | # 182 | set_location_assignment PIN_A15 -to gpio0_io[0] 183 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0] 184 | set_location_assignment PIN_A13 -to gpio0_io[1] 185 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1] 186 | set_location_assignment PIN_B13 -to gpio0_io[2] 187 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2] 188 | set_location_assignment PIN_A11 -to gpio0_io[3] 189 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3] 190 | set_location_assignment PIN_D1 -to gpio0_io[4] 191 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4] 192 | set_location_assignment PIN_F3 -to gpio0_io[5] 193 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5] 194 | set_location_assignment PIN_B1 -to gpio0_io[6] 195 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6] 196 | set_location_assignment PIN_L3 -to gpio0_io[7] 197 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7] 198 | 199 | #============================================================ 200 | # GPIO1 (Switches) 201 | #============================================================ 202 | set_location_assignment PIN_M1 -to gpio1_i[0] 203 | set_location_assignment PIN_T8 -to gpio1_i[1] 204 | set_location_assignment PIN_B9 -to gpio1_i[2] 205 | set_location_assignment PIN_M15 -to gpio1_i[3] 206 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio1_i[*] 207 | -------------------------------------------------------------------------------- /rtl/sdram_controller.v: -------------------------------------------------------------------------------- 1 | /** 2 | * simple controller for ISSI IS42S16160G-7 SDRAM found in De0 Nano 3 | * 16Mbit x 16 data bit bus (32 megabytes) 4 | * Default options 5 | * 133Mhz 6 | * CAS 3 7 | * 8 | * Very simple host interface 9 | * * No burst support 10 | * * haddr - address for reading and wriging 16 bits of data 11 | * * data_input - data for writing, latched in when wr_enable is highz0 12 | * * data_output - data for reading, comes available sometime 13 | * *few clocks* after rd_enable and address is presented on bus 14 | * * rst_n - start init ram process 15 | * * rd_enable - read enable, on clk posedge haddr will be latched in, 16 | * after *few clocks* data will be available on the data_output port 17 | * * wr_enable - write enable, on clk posedge haddr and data_input will 18 | * be latched in, after *few clocks* data will be written to sdram 19 | * 20 | * Theory 21 | * This simple host interface has a busy signal to tell you when you are 22 | * not able to issue commands. 23 | */ 24 | 25 | module sdram_controller ( 26 | /* HOST INTERFACE */ 27 | wr_addr, 28 | wr_data, 29 | wr_enable, 30 | 31 | rd_addr, 32 | rd_data, 33 | rd_ready, 34 | rd_enable, 35 | 36 | busy, rst_n, clk, 37 | 38 | /* SDRAM SIDE */ 39 | addr, bank_addr, data, clock_enable, cs_n, ras_n, cas_n, we_n, 40 | data_mask_low, data_mask_high 41 | ); 42 | 43 | /* Internal Parameters */ 44 | parameter ROW_WIDTH = 13; 45 | parameter COL_WIDTH = 9; 46 | parameter BANK_WIDTH = 2; 47 | 48 | parameter SDRADDR_WIDTH = ROW_WIDTH > COL_WIDTH ? ROW_WIDTH : COL_WIDTH; 49 | parameter HADDR_WIDTH = BANK_WIDTH + ROW_WIDTH + COL_WIDTH; 50 | 51 | parameter CLK_FREQUENCY = 133; // Mhz 52 | parameter REFRESH_TIME = 32; // ms (how often we need to refresh) 53 | parameter REFRESH_COUNT = 8192; // cycles (how many refreshes required per refresh time) 54 | 55 | // clk / refresh = clk / sec 56 | // , sec / refbatch 57 | // , ref / refbatch 58 | localparam CYCLES_BETWEEN_REFRESH = ( CLK_FREQUENCY 59 | * 1_000 60 | * REFRESH_TIME 61 | ) / REFRESH_COUNT; 62 | 63 | // STATES - State 64 | localparam IDLE = 5'b00000; 65 | 66 | localparam INIT_NOP1 = 5'b01000, 67 | INIT_PRE1 = 5'b01001, 68 | INIT_NOP1_1=5'b00101, 69 | INIT_REF1 = 5'b01010, 70 | INIT_NOP2 = 5'b01011, 71 | INIT_REF2 = 5'b01100, 72 | INIT_NOP3 = 5'b01101, 73 | INIT_LOAD = 5'b01110, 74 | INIT_NOP4 = 5'b01111; 75 | 76 | localparam REF_PRE = 5'b00001, 77 | REF_NOP1 = 5'b00010, 78 | REF_REF = 5'b00011, 79 | REF_NOP2 = 5'b00100; 80 | 81 | localparam READ_ACT = 5'b10000, 82 | READ_NOP1 = 5'b10001, 83 | READ_CAS = 5'b10010, 84 | READ_NOP2 = 5'b10011, 85 | READ_READ = 5'b10100; 86 | 87 | localparam WRIT_ACT = 5'b11000, 88 | WRIT_NOP1 = 5'b11001, 89 | WRIT_CAS = 5'b11010, 90 | WRIT_NOP2 = 5'b11011; 91 | 92 | // Commands CCRCWBBA 93 | // ESSSE100 94 | localparam CMD_PALL = 8'b10010001, 95 | CMD_REF = 8'b10001000, 96 | CMD_NOP = 8'b10111000, 97 | CMD_MRS = 8'b1000000x, 98 | CMD_BACT = 8'b10011xxx, 99 | CMD_READ = 8'b10101xx1, 100 | CMD_WRIT = 8'b10100xx1; 101 | 102 | /* Interface Definition */ 103 | /* HOST INTERFACE */ 104 | input [HADDR_WIDTH-1:0] wr_addr; 105 | input [15:0] wr_data; 106 | input wr_enable; 107 | 108 | input [HADDR_WIDTH-1:0] rd_addr; 109 | output [15:0] rd_data; 110 | input rd_enable; 111 | output rd_ready; 112 | 113 | output busy; 114 | input rst_n; 115 | input clk; 116 | 117 | /* SDRAM SIDE */ 118 | output [SDRADDR_WIDTH-1:0] addr; 119 | output [BANK_WIDTH-1:0] bank_addr; 120 | inout [15:0] data; 121 | output clock_enable; 122 | output cs_n; 123 | output ras_n; 124 | output cas_n; 125 | output we_n; 126 | output data_mask_low; 127 | output data_mask_high; 128 | 129 | /* I/O Registers */ 130 | 131 | reg [HADDR_WIDTH-1:0] haddr_r; 132 | reg [15:0] wr_data_r; 133 | reg [15:0] rd_data_r; 134 | reg busy; 135 | reg data_mask_low_r; 136 | reg data_mask_high_r; 137 | reg [SDRADDR_WIDTH-1:0] addr_r; 138 | reg [BANK_WIDTH-1:0] bank_addr_r; 139 | reg rd_ready_r; 140 | 141 | wire [15:0] data_output; 142 | wire data_mask_low, data_mask_high; 143 | 144 | assign data_mask_high = data_mask_high_r; 145 | assign data_mask_low = data_mask_low_r; 146 | assign rd_data = rd_data_r; 147 | 148 | /* Internal Wiring */ 149 | reg [3:0] state_cnt; 150 | reg [9:0] refresh_cnt; 151 | 152 | reg [7:0] command; 153 | reg [4:0] state; 154 | 155 | // TODO output addr[6:4] when programming mode register 156 | 157 | reg [7:0] command_nxt; 158 | reg [3:0] state_cnt_nxt; 159 | reg [4:0] next; 160 | 161 | assign {clock_enable, cs_n, ras_n, cas_n, we_n} = command[7:3]; 162 | // state[4] will be set if mode is read/write 163 | assign bank_addr = (state[4]) ? bank_addr_r : command[2:1]; 164 | assign addr = (state[4] | state == INIT_LOAD) ? addr_r : { {SDRADDR_WIDTH-11{1'b0}}, command[0], 10'd0 }; 165 | 166 | assign data = (state == WRIT_CAS) ? wr_data_r : 16'bz; 167 | assign rd_ready = rd_ready_r; 168 | 169 | // HOST INTERFACE 170 | // all registered on posedge 171 | always @ (posedge clk) 172 | if (~rst_n) 173 | begin 174 | state <= INIT_NOP1; 175 | command <= CMD_NOP; 176 | state_cnt <= 4'hf; 177 | 178 | haddr_r <= {HADDR_WIDTH{1'b0}}; 179 | wr_data_r <= 16'b0; 180 | rd_data_r <= 16'b0; 181 | busy <= 1'b0; 182 | end 183 | else 184 | begin 185 | 186 | state <= next; 187 | command <= command_nxt; 188 | 189 | if (!state_cnt) 190 | state_cnt <= state_cnt_nxt; 191 | else 192 | state_cnt <= state_cnt - 1'b1; 193 | 194 | if (wr_enable) 195 | wr_data_r <= wr_data; 196 | 197 | if (state == READ_READ) 198 | begin 199 | rd_data_r <= data; 200 | rd_ready_r <= 1'b1; 201 | end 202 | else 203 | rd_ready_r <= 1'b0; 204 | 205 | busy <= state[4]; 206 | 207 | if (rd_enable) 208 | haddr_r <= rd_addr; 209 | else if (wr_enable) 210 | haddr_r <= wr_addr; 211 | 212 | end 213 | 214 | // Handle refresh counter 215 | always @ (posedge clk) 216 | if (~rst_n) 217 | refresh_cnt <= 10'b0; 218 | else 219 | if (state == REF_NOP2) 220 | refresh_cnt <= 10'b0; 221 | else 222 | refresh_cnt <= refresh_cnt + 1'b1; 223 | 224 | 225 | /* Handle logic for sending addresses to SDRAM based on current state*/ 226 | always @* 227 | begin 228 | if (state[4]) 229 | {data_mask_low_r, data_mask_high_r} = 2'b00; 230 | else 231 | {data_mask_low_r, data_mask_high_r} = 2'b11; 232 | 233 | bank_addr_r = 2'b00; 234 | addr_r = {SDRADDR_WIDTH{1'b0}}; 235 | 236 | if (state == READ_ACT | state == WRIT_ACT) 237 | begin 238 | bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)]; 239 | addr_r = haddr_r[HADDR_WIDTH-(BANK_WIDTH+1):HADDR_WIDTH-(BANK_WIDTH+ROW_WIDTH)]; 240 | end 241 | else if (state == READ_CAS | state == WRIT_CAS) 242 | begin 243 | // Send Column Address 244 | // Set bank to bank to precharge 245 | bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)]; 246 | 247 | // Examples for math 248 | // BANK ROW COL 249 | // HADDR_WIDTH 2 + 13 + 9 = 24 250 | // SDRADDR_WIDTH 13 251 | 252 | // Set CAS address to: 253 | // 0s, 254 | // 1 (A10 is always for auto precharge), 255 | // 0s, 256 | // column address 257 | addr_r = { 258 | {SDRADDR_WIDTH-(11){1'b0}}, 259 | 1'b1, /* A10 */ 260 | {10-COL_WIDTH{1'b0}}, 261 | haddr_r[COL_WIDTH-1:0] 262 | }; 263 | end 264 | else if (state == INIT_LOAD) 265 | begin 266 | // Program mode register during load cycle 267 | // B C SB 268 | // R A EUR 269 | // S S-3Q ST 270 | // T 654L210 271 | addr_r = {{SDRADDR_WIDTH-10{1'b0}}, 10'b1000110000}; 272 | end 273 | end 274 | 275 | // Next state logic 276 | always @* 277 | begin 278 | state_cnt_nxt = 4'd0; 279 | command_nxt = CMD_NOP; 280 | if (state == IDLE) 281 | // Monitor for refresh or hold 282 | if (refresh_cnt >= CYCLES_BETWEEN_REFRESH) 283 | begin 284 | next = REF_PRE; 285 | command_nxt = CMD_PALL; 286 | end 287 | else if (rd_enable) 288 | begin 289 | next = READ_ACT; 290 | command_nxt = CMD_BACT; 291 | end 292 | else if (wr_enable) 293 | begin 294 | next = WRIT_ACT; 295 | command_nxt = CMD_BACT; 296 | end 297 | else 298 | begin 299 | // HOLD 300 | next = IDLE; 301 | end 302 | else 303 | if (!state_cnt) 304 | case (state) 305 | // INIT ENGINE 306 | INIT_NOP1: 307 | begin 308 | next = INIT_PRE1; 309 | command_nxt = CMD_PALL; 310 | end 311 | INIT_PRE1: 312 | begin 313 | next = INIT_NOP1_1; 314 | end 315 | INIT_NOP1_1: 316 | begin 317 | next = INIT_REF1; 318 | command_nxt = CMD_REF; 319 | end 320 | INIT_REF1: 321 | begin 322 | next = INIT_NOP2; 323 | state_cnt_nxt = 4'd7; 324 | end 325 | INIT_NOP2: 326 | begin 327 | next = INIT_REF2; 328 | command_nxt = CMD_REF; 329 | end 330 | INIT_REF2: 331 | begin 332 | next = INIT_NOP3; 333 | state_cnt_nxt = 4'd7; 334 | end 335 | INIT_NOP3: 336 | begin 337 | next = INIT_LOAD; 338 | command_nxt = CMD_MRS; 339 | end 340 | INIT_LOAD: 341 | begin 342 | next = INIT_NOP4; 343 | state_cnt_nxt = 4'd1; 344 | end 345 | // INIT_NOP4: default - IDLE 346 | 347 | // REFRESH 348 | REF_PRE: 349 | begin 350 | next = REF_NOP1; 351 | end 352 | REF_NOP1: 353 | begin 354 | next = REF_REF; 355 | command_nxt = CMD_REF; 356 | end 357 | REF_REF: 358 | begin 359 | next = REF_NOP2; 360 | state_cnt_nxt = 4'd7; 361 | end 362 | // REF_NOP2: default - IDLE 363 | 364 | // WRITE 365 | WRIT_ACT: 366 | begin 367 | next = WRIT_NOP1; 368 | state_cnt_nxt = 4'd1; 369 | end 370 | WRIT_NOP1: 371 | begin 372 | next = WRIT_CAS; 373 | command_nxt = CMD_WRIT; 374 | end 375 | WRIT_CAS: 376 | begin 377 | next = WRIT_NOP2; 378 | state_cnt_nxt = 4'd1; 379 | end 380 | // WRIT_NOP2: default - IDLE 381 | 382 | // READ 383 | READ_ACT: 384 | begin 385 | next = READ_NOP1; 386 | state_cnt_nxt = 4'd1; 387 | end 388 | READ_NOP1: 389 | begin 390 | next = READ_CAS; 391 | command_nxt = CMD_READ; 392 | end 393 | READ_CAS: 394 | begin 395 | next = READ_NOP2; 396 | state_cnt_nxt = 4'd1; 397 | end 398 | READ_NOP2: 399 | begin 400 | next = READ_READ; 401 | end 402 | // READ_READ: default - IDLE 403 | 404 | default: 405 | begin 406 | next = IDLE; 407 | end 408 | endcase 409 | else 410 | begin 411 | // Counter Not Reached - HOLD 412 | next = state; 413 | command_nxt = command; 414 | end 415 | end 416 | 417 | endmodule 418 | -------------------------------------------------------------------------------- /quartus/dram_controller.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.2 Build 153 07/15/2015 SJ Web Edition 22 | # Date created = 20:55:03 February 03, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # dram_controller_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus II software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone IV E" 41 | set_global_assignment -name DEVICE EP4CE22F17C6 42 | set_global_assignment -name TOP_LEVEL_ENTITY toplevel 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.2 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:55:03 FEBRUARY 03, 2017" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 15.0.2 46 | set_global_assignment -name VERILOG_FILE ../rtl/dnano_interface.v 47 | set_global_assignment -name VERILOG_FILE ../rtl/double_click.v 48 | set_global_assignment -name VERILOG_FILE ../rtl/fifo.v 49 | set_global_assignment -name VERILOG_FILE ../rtl/sdram_controller.v 50 | set_global_assignment -name VERILOG_FILE ../rtl/toplevel.v 51 | set_global_assignment -name VERILOG_FILE ../quartus/pll_100m.v 52 | set_global_assignment -name VERILOG_FILE ../quartus/pll_1m.v 53 | set_global_assignment -name SDC_FILE ../data/de0_nano.sdc 54 | set_location_assignment PIN_J15 -to rst_n_pad_i 55 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i 56 | set_location_assignment PIN_E1 -to btn_n_pad_i 57 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to btn_n_pad_i 58 | set_location_assignment PIN_R8 -to sys_clk_pad_i 59 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i 60 | set_location_assignment PIN_A14 -to uart0_srx_pad_i 61 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i 62 | set_location_assignment PIN_B16 -to uart0_stx_pad_o 63 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o 64 | set_location_assignment PIN_F2 -to i2c0_scl_io 65 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c0_scl_io 66 | set_location_assignment PIN_F1 -to i2c0_sda_io 67 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c0_sda_io 68 | set_location_assignment PIN_M2 -to accelerometer_irq_i 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to accelerometer_irq_i 70 | set_location_assignment PIN_G5 -to accelerometer_cs_o 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to accelerometer_cs_o 72 | set_location_assignment PIN_D15 -to i2c1_sda_io 73 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c1_sda_io 74 | set_location_assignment PIN_D14 -to i2c1_scl_io 75 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c1_scl_io 76 | set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" 77 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" 78 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" 79 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" 80 | set_location_assignment PIN_C1 -to spi0_mosi_o 81 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_mosi_o 82 | set_location_assignment PIN_H2 -to spi0_miso_i 83 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_miso_i 84 | set_location_assignment PIN_H1 -to spi0_sck_o 85 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_sck_o 86 | set_location_assignment PIN_D2 -to spi0_ss_o 87 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi0_ss_o 88 | set_location_assignment PIN_B10 -to spi1_mosi_o 89 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_mosi_o 90 | set_location_assignment PIN_A9 -to spi1_miso_i 91 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_miso_i 92 | set_location_assignment PIN_B14 -to spi1_sck_o 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_sck_o 94 | set_location_assignment PIN_A10 -to spi1_ss_o 95 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_ss_o 96 | set_location_assignment PIN_C14 -to spi2_mosi_o 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_mosi_o 98 | set_location_assignment PIN_C16 -to spi2_miso_i 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_miso_i 100 | set_location_assignment PIN_C15 -to spi2_sck_o 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_sck_o 102 | set_location_assignment PIN_D16 -to spi2_ss_o 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi2_ss_o 104 | set_location_assignment PIN_P2 -to sdram_a_pad_o[0] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[0] 106 | set_location_assignment PIN_N5 -to sdram_a_pad_o[1] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[1] 108 | set_location_assignment PIN_N6 -to sdram_a_pad_o[2] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[2] 110 | set_location_assignment PIN_M8 -to sdram_a_pad_o[3] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[3] 112 | set_location_assignment PIN_P8 -to sdram_a_pad_o[4] 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[4] 114 | set_location_assignment PIN_T7 -to sdram_a_pad_o[5] 115 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[5] 116 | set_location_assignment PIN_N8 -to sdram_a_pad_o[6] 117 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[6] 118 | set_location_assignment PIN_T6 -to sdram_a_pad_o[7] 119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[7] 120 | set_location_assignment PIN_R1 -to sdram_a_pad_o[8] 121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[8] 122 | set_location_assignment PIN_P1 -to sdram_a_pad_o[9] 123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[9] 124 | set_location_assignment PIN_N2 -to sdram_a_pad_o[10] 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[10] 126 | set_location_assignment PIN_N1 -to sdram_a_pad_o[11] 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[11] 128 | set_location_assignment PIN_L4 -to sdram_a_pad_o[12] 129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[12] 130 | set_location_assignment PIN_G2 -to sdram_dq_pad_io[0] 131 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[0] 132 | set_location_assignment PIN_G1 -to sdram_dq_pad_io[1] 133 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[1] 134 | set_location_assignment PIN_L8 -to sdram_dq_pad_io[2] 135 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[2] 136 | set_location_assignment PIN_K5 -to sdram_dq_pad_io[3] 137 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[3] 138 | set_location_assignment PIN_K2 -to sdram_dq_pad_io[4] 139 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[4] 140 | set_location_assignment PIN_J2 -to sdram_dq_pad_io[5] 141 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[5] 142 | set_location_assignment PIN_J1 -to sdram_dq_pad_io[6] 143 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[6] 144 | set_location_assignment PIN_R7 -to sdram_dq_pad_io[7] 145 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[7] 146 | set_location_assignment PIN_T4 -to sdram_dq_pad_io[8] 147 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[8] 148 | set_location_assignment PIN_T2 -to sdram_dq_pad_io[9] 149 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[9] 150 | set_location_assignment PIN_T3 -to sdram_dq_pad_io[10] 151 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[10] 152 | set_location_assignment PIN_R3 -to sdram_dq_pad_io[11] 153 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[11] 154 | set_location_assignment PIN_R5 -to sdram_dq_pad_io[12] 155 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[12] 156 | set_location_assignment PIN_P3 -to sdram_dq_pad_io[13] 157 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[13] 158 | set_location_assignment PIN_N3 -to sdram_dq_pad_io[14] 159 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[14] 160 | set_location_assignment PIN_K1 -to sdram_dq_pad_io[15] 161 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[15] 162 | set_location_assignment PIN_R6 -to sdram_dqm_pad_o[0] 163 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[0] 164 | set_location_assignment PIN_T5 -to sdram_dqm_pad_o[1] 165 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[1] 166 | set_location_assignment PIN_M7 -to sdram_ba_pad_o[0] 167 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[0] 168 | set_location_assignment PIN_M6 -to sdram_ba_pad_o[1] 169 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[1] 170 | set_location_assignment PIN_L1 -to sdram_cas_pad_o 171 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cas_pad_o 172 | set_location_assignment PIN_L7 -to sdram_cke_pad_o 173 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cke_pad_o 174 | set_location_assignment PIN_P6 -to sdram_cs_n_pad_o 175 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cs_n_pad_o 176 | set_location_assignment PIN_L2 -to sdram_ras_pad_o 177 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ras_pad_o 178 | set_location_assignment PIN_C2 -to sdram_we_pad_o 179 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_pad_o 180 | set_location_assignment PIN_R4 -to sdram_clk_pad_o 181 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o 182 | set_location_assignment PIN_A15 -to gpio0_io[0] 183 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0] 184 | set_location_assignment PIN_A13 -to gpio0_io[1] 185 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1] 186 | set_location_assignment PIN_B13 -to gpio0_io[2] 187 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2] 188 | set_location_assignment PIN_A11 -to gpio0_io[3] 189 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3] 190 | set_location_assignment PIN_D1 -to gpio0_io[4] 191 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4] 192 | set_location_assignment PIN_F3 -to gpio0_io[5] 193 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5] 194 | set_location_assignment PIN_B1 -to gpio0_io[6] 195 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6] 196 | set_location_assignment PIN_L3 -to gpio0_io[7] 197 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7] 198 | set_location_assignment PIN_M1 -to gpio1_i[0] 199 | set_location_assignment PIN_T8 -to gpio1_i[1] 200 | set_location_assignment PIN_B9 -to gpio1_i[2] 201 | set_location_assignment PIN_M15 -to gpio1_i[3] 202 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio1_i[*] 203 | 204 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 205 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 206 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 207 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /quartus/pll_1m.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll_1m.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module pll_1m ( 41 | inclk0, 42 | c0); 43 | 44 | input inclk0; 45 | output c0; 46 | 47 | wire [0:0] sub_wire2 = 1'h0; 48 | wire [4:0] sub_wire3; 49 | wire sub_wire0 = inclk0; 50 | wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; 51 | wire [0:0] sub_wire4 = sub_wire3[0:0]; 52 | wire c0 = sub_wire4; 53 | 54 | altpll altpll_component ( 55 | .inclk (sub_wire1), 56 | .clk (sub_wire3), 57 | .activeclock (), 58 | .areset (1'b0), 59 | .clkbad (), 60 | .clkena ({6{1'b1}}), 61 | .clkloss (), 62 | .clkswitch (1'b0), 63 | .configupdate (1'b0), 64 | .enable0 (), 65 | .enable1 (), 66 | .extclk (), 67 | .extclkena ({4{1'b1}}), 68 | .fbin (1'b1), 69 | .fbmimicbidir (), 70 | .fbout (), 71 | .fref (), 72 | .icdrclk (), 73 | .locked (), 74 | .pfdena (1'b1), 75 | .phasecounterselect ({4{1'b1}}), 76 | .phasedone (), 77 | .phasestep (1'b1), 78 | .phaseupdown (1'b1), 79 | .pllena (1'b1), 80 | .scanaclr (1'b0), 81 | .scanclk (1'b0), 82 | .scanclkena (1'b1), 83 | .scandata (1'b0), 84 | .scandataout (), 85 | .scandone (), 86 | .scanread (1'b0), 87 | .scanwrite (1'b0), 88 | .sclkout0 (), 89 | .sclkout1 (), 90 | .vcooverrange (), 91 | .vcounderrange ()); 92 | defparam 93 | altpll_component.bandwidth_type = "AUTO", 94 | altpll_component.clk0_divide_by = 50, 95 | altpll_component.clk0_duty_cycle = 50, 96 | altpll_component.clk0_multiply_by = 1, 97 | altpll_component.clk0_phase_shift = "0", 98 | altpll_component.compensate_clock = "CLK0", 99 | altpll_component.inclk0_input_frequency = 20000, 100 | altpll_component.intended_device_family = "Cyclone IV E", 101 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_1m", 102 | altpll_component.lpm_type = "altpll", 103 | altpll_component.operation_mode = "NORMAL", 104 | altpll_component.pll_type = "AUTO", 105 | altpll_component.port_activeclock = "PORT_UNUSED", 106 | altpll_component.port_areset = "PORT_UNUSED", 107 | altpll_component.port_clkbad0 = "PORT_UNUSED", 108 | altpll_component.port_clkbad1 = "PORT_UNUSED", 109 | altpll_component.port_clkloss = "PORT_UNUSED", 110 | altpll_component.port_clkswitch = "PORT_UNUSED", 111 | altpll_component.port_configupdate = "PORT_UNUSED", 112 | altpll_component.port_fbin = "PORT_UNUSED", 113 | altpll_component.port_inclk0 = "PORT_USED", 114 | altpll_component.port_inclk1 = "PORT_UNUSED", 115 | altpll_component.port_locked = "PORT_UNUSED", 116 | altpll_component.port_pfdena = "PORT_UNUSED", 117 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 118 | altpll_component.port_phasedone = "PORT_UNUSED", 119 | altpll_component.port_phasestep = "PORT_UNUSED", 120 | altpll_component.port_phaseupdown = "PORT_UNUSED", 121 | altpll_component.port_pllena = "PORT_UNUSED", 122 | altpll_component.port_scanaclr = "PORT_UNUSED", 123 | altpll_component.port_scanclk = "PORT_UNUSED", 124 | altpll_component.port_scanclkena = "PORT_UNUSED", 125 | altpll_component.port_scandata = "PORT_UNUSED", 126 | altpll_component.port_scandataout = "PORT_UNUSED", 127 | altpll_component.port_scandone = "PORT_UNUSED", 128 | altpll_component.port_scanread = "PORT_UNUSED", 129 | altpll_component.port_scanwrite = "PORT_UNUSED", 130 | altpll_component.port_clk0 = "PORT_USED", 131 | altpll_component.port_clk1 = "PORT_UNUSED", 132 | altpll_component.port_clk2 = "PORT_UNUSED", 133 | altpll_component.port_clk3 = "PORT_UNUSED", 134 | altpll_component.port_clk4 = "PORT_UNUSED", 135 | altpll_component.port_clk5 = "PORT_UNUSED", 136 | altpll_component.port_clkena0 = "PORT_UNUSED", 137 | altpll_component.port_clkena1 = "PORT_UNUSED", 138 | altpll_component.port_clkena2 = "PORT_UNUSED", 139 | altpll_component.port_clkena3 = "PORT_UNUSED", 140 | altpll_component.port_clkena4 = "PORT_UNUSED", 141 | altpll_component.port_clkena5 = "PORT_UNUSED", 142 | altpll_component.port_extclk0 = "PORT_UNUSED", 143 | altpll_component.port_extclk1 = "PORT_UNUSED", 144 | altpll_component.port_extclk2 = "PORT_UNUSED", 145 | altpll_component.port_extclk3 = "PORT_UNUSED", 146 | altpll_component.width_clock = 5; 147 | 148 | 149 | endmodule 150 | 151 | // ============================================================ 152 | // CNX file retrieval info 153 | // ============================================================ 154 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 155 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 156 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 157 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 158 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 159 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 160 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 161 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 162 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 163 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 164 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 165 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 166 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 168 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 169 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" 170 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 171 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 172 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" 173 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 174 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 175 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 176 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 177 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 179 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 180 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 181 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 182 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 183 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 184 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 185 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 186 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 187 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 188 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 189 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 190 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 191 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 192 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 193 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 194 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 195 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 196 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 197 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000" 198 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 199 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 200 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 201 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 202 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 203 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 204 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 205 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 206 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 207 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 208 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 209 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 210 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 212 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 213 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 214 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 215 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_1m.mif" 216 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 217 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 218 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 219 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 220 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 221 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 222 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 223 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 224 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 225 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 226 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 227 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 228 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 229 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 230 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 231 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 232 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 233 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 234 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 235 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 236 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" 237 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 238 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" 239 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 240 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 241 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 242 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 243 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 244 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 245 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 246 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 247 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 248 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 249 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 250 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 251 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 252 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 253 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 254 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 255 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 256 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 257 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 258 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 259 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 260 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 261 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 262 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 263 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 264 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 265 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 266 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 267 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 268 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 269 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 270 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 271 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 272 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 273 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 274 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 275 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 276 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 277 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 278 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 279 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 280 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 281 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 282 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 283 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 284 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 285 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 286 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 287 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 288 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 289 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 290 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 291 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 292 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 293 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 294 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.v TRUE 295 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.ppf TRUE 296 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.inc FALSE 297 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.cmp FALSE 298 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.bsf FALSE 299 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m_inst.v FALSE 300 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m_bb.v FALSE 301 | // Retrieval info: LIB_FILE: altera_mf 302 | // Retrieval info: CBX_MODULE_PREFIX: ON 303 | -------------------------------------------------------------------------------- /quartus/pll_100m.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll_100m.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module pll_100m ( 41 | inclk0, 42 | c0); 43 | 44 | input inclk0; 45 | output c0; 46 | 47 | wire [0:0] sub_wire2 = 1'h0; 48 | wire [4:0] sub_wire3; 49 | wire sub_wire0 = inclk0; 50 | wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; 51 | wire [0:0] sub_wire4 = sub_wire3[0:0]; 52 | wire c0 = sub_wire4; 53 | 54 | altpll altpll_component ( 55 | .inclk (sub_wire1), 56 | .clk (sub_wire3), 57 | .activeclock (), 58 | .areset (1'b0), 59 | .clkbad (), 60 | .clkena ({6{1'b1}}), 61 | .clkloss (), 62 | .clkswitch (1'b0), 63 | .configupdate (1'b0), 64 | .enable0 (), 65 | .enable1 (), 66 | .extclk (), 67 | .extclkena ({4{1'b1}}), 68 | .fbin (1'b1), 69 | .fbmimicbidir (), 70 | .fbout (), 71 | .fref (), 72 | .icdrclk (), 73 | .locked (), 74 | .pfdena (1'b1), 75 | .phasecounterselect ({4{1'b1}}), 76 | .phasedone (), 77 | .phasestep (1'b1), 78 | .phaseupdown (1'b1), 79 | .pllena (1'b1), 80 | .scanaclr (1'b0), 81 | .scanclk (1'b0), 82 | .scanclkena (1'b1), 83 | .scandata (1'b0), 84 | .scandataout (), 85 | .scandone (), 86 | .scanread (1'b0), 87 | .scanwrite (1'b0), 88 | .sclkout0 (), 89 | .sclkout1 (), 90 | .vcooverrange (), 91 | .vcounderrange ()); 92 | defparam 93 | altpll_component.bandwidth_type = "AUTO", 94 | altpll_component.clk0_divide_by = 1, 95 | altpll_component.clk0_duty_cycle = 50, 96 | altpll_component.clk0_multiply_by = 2, 97 | altpll_component.clk0_phase_shift = "0", 98 | altpll_component.compensate_clock = "CLK0", 99 | altpll_component.inclk0_input_frequency = 20000, 100 | altpll_component.intended_device_family = "Cyclone IV E", 101 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_100m", 102 | altpll_component.lpm_type = "altpll", 103 | altpll_component.operation_mode = "NORMAL", 104 | altpll_component.pll_type = "AUTO", 105 | altpll_component.port_activeclock = "PORT_UNUSED", 106 | altpll_component.port_areset = "PORT_UNUSED", 107 | altpll_component.port_clkbad0 = "PORT_UNUSED", 108 | altpll_component.port_clkbad1 = "PORT_UNUSED", 109 | altpll_component.port_clkloss = "PORT_UNUSED", 110 | altpll_component.port_clkswitch = "PORT_UNUSED", 111 | altpll_component.port_configupdate = "PORT_UNUSED", 112 | altpll_component.port_fbin = "PORT_UNUSED", 113 | altpll_component.port_inclk0 = "PORT_USED", 114 | altpll_component.port_inclk1 = "PORT_UNUSED", 115 | altpll_component.port_locked = "PORT_UNUSED", 116 | altpll_component.port_pfdena = "PORT_UNUSED", 117 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 118 | altpll_component.port_phasedone = "PORT_UNUSED", 119 | altpll_component.port_phasestep = "PORT_UNUSED", 120 | altpll_component.port_phaseupdown = "PORT_UNUSED", 121 | altpll_component.port_pllena = "PORT_UNUSED", 122 | altpll_component.port_scanaclr = "PORT_UNUSED", 123 | altpll_component.port_scanclk = "PORT_UNUSED", 124 | altpll_component.port_scanclkena = "PORT_UNUSED", 125 | altpll_component.port_scandata = "PORT_UNUSED", 126 | altpll_component.port_scandataout = "PORT_UNUSED", 127 | altpll_component.port_scandone = "PORT_UNUSED", 128 | altpll_component.port_scanread = "PORT_UNUSED", 129 | altpll_component.port_scanwrite = "PORT_UNUSED", 130 | altpll_component.port_clk0 = "PORT_USED", 131 | altpll_component.port_clk1 = "PORT_UNUSED", 132 | altpll_component.port_clk2 = "PORT_UNUSED", 133 | altpll_component.port_clk3 = "PORT_UNUSED", 134 | altpll_component.port_clk4 = "PORT_UNUSED", 135 | altpll_component.port_clk5 = "PORT_UNUSED", 136 | altpll_component.port_clkena0 = "PORT_UNUSED", 137 | altpll_component.port_clkena1 = "PORT_UNUSED", 138 | altpll_component.port_clkena2 = "PORT_UNUSED", 139 | altpll_component.port_clkena3 = "PORT_UNUSED", 140 | altpll_component.port_clkena4 = "PORT_UNUSED", 141 | altpll_component.port_clkena5 = "PORT_UNUSED", 142 | altpll_component.port_extclk0 = "PORT_UNUSED", 143 | altpll_component.port_extclk1 = "PORT_UNUSED", 144 | altpll_component.port_extclk2 = "PORT_UNUSED", 145 | altpll_component.port_extclk3 = "PORT_UNUSED", 146 | altpll_component.width_clock = 5; 147 | 148 | 149 | endmodule 150 | 151 | // ============================================================ 152 | // CNX file retrieval info 153 | // ============================================================ 154 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 155 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 156 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 157 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 158 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 159 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 160 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 161 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 162 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 163 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 164 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 165 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 166 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 168 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 169 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" 170 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 171 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 172 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" 173 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 174 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 175 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 176 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 177 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 179 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 180 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 181 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 182 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 183 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 184 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 185 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 186 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 187 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 188 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 189 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 190 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 191 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 192 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 193 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 194 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 195 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 196 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 197 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" 198 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 199 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 200 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 201 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 202 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 203 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 204 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 205 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 206 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 207 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 208 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 209 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 210 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 212 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 213 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 214 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 215 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_100m.mif" 216 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 217 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 218 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 219 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 220 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 221 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 222 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 223 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 224 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 225 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 226 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 227 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 228 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 229 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1" 230 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 231 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 232 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 233 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 234 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 235 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 236 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 237 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 238 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" 239 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 240 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 241 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 242 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 243 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 244 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 245 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 246 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 247 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 248 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 249 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 250 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 251 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 252 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 253 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 254 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 255 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 256 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 257 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 258 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 259 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 260 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 261 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 262 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 263 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 264 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 265 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 266 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 267 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 268 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 269 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 270 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 271 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 272 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 273 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 274 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 275 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 276 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 277 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 278 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 279 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 280 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 281 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 282 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 283 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 284 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 285 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 286 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 287 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 288 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 289 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 290 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 291 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 292 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 293 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 294 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.v TRUE 295 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.ppf TRUE 296 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.inc FALSE 297 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.cmp FALSE 298 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.bsf FALSE 299 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m_inst.v FALSE 300 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m_bb.v FALSE 301 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m_syn.v TRUE 302 | // Retrieval info: LIB_FILE: altera_mf 303 | // Retrieval info: CBX_MODULE_PREFIX: ON 304 | --------------------------------------------------------------------------------