├── .github ├── bors.toml └── workflows │ ├── ci.yml │ └── hil.yml ├── .gitignore ├── CHANGELOG.md ├── Cargo.toml ├── LICENSE-APACHE ├── LICENSE-MIT ├── README.md ├── RELEASE_PROCESS.md ├── src ├── embedded_hal.rs ├── filter.rs ├── frame.rs ├── frame │ └── tests.rs ├── id.rs ├── interrupt.rs ├── lib.rs └── pac │ ├── can.rs │ ├── can │ ├── btr.rs │ ├── esr.rs │ ├── fa1r.rs │ ├── fb.rs │ ├── fb │ │ ├── fr1.rs │ │ └── fr2.rs │ ├── ffa1r.rs │ ├── fm1r.rs │ ├── fmr.rs │ ├── fs1r.rs │ ├── ier.rs │ ├── mcr.rs │ ├── msr.rs │ ├── rfr.rs │ ├── rx.rs │ ├── rx │ │ ├── rdhr.rs │ │ ├── rdlr.rs │ │ ├── rdtr.rs │ │ └── rir.rs │ ├── tsr.rs │ ├── tx.rs │ └── tx │ │ ├── tdhr.rs │ │ ├── tdlr.rs │ │ ├── tdtr.rs │ │ └── tir.rs │ ├── generic.rs │ └── mod.rs └── testsuite ├── .cargo └── config.toml ├── Cargo.toml ├── README.md ├── build.rs ├── memory.x ├── src ├── interrupt.rs └── lib.rs └── tests ├── integration.rs └── interrupts.rs /.github/bors.toml: -------------------------------------------------------------------------------- 1 | status = ["ci"] 2 | -------------------------------------------------------------------------------- /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | name: CI 2 | 3 | on: 4 | push: 5 | branches: 6 | - master 7 | - staging 8 | - trying 9 | pull_request: 10 | branches: 11 | - master 12 | 13 | env: 14 | CARGO_TERM_COLOR: always 15 | 16 | jobs: 17 | test: 18 | strategy: 19 | matrix: 20 | rust: 21 | - stable 22 | - nightly 23 | os: 24 | - ubuntu-latest 25 | - macOS-latest 26 | - windows-latest 27 | runs-on: ${{ matrix.os }} 28 | env: 29 | RUSTFLAGS: "--deny warnings" 30 | steps: 31 | - uses: actions/checkout@v2 32 | - uses: actions-rs/toolchain@v1 33 | with: 34 | profile: minimal 35 | toolchain: ${{ matrix.rust }} 36 | override: true 37 | - name: Build 38 | run: cargo build --all-targets 39 | - name: Build All Features 40 | # defmt 0.3 doesn't build when targeting windows 41 | if: ${{ matrix.os != 'windows-latest' }} 42 | run: cargo build --all-targets --all-features 43 | - name: Run tests 44 | run: cargo test 45 | 46 | no-std: 47 | runs-on: ubuntu-latest 48 | steps: 49 | - uses: actions/checkout@v2 50 | - uses: actions-rs/toolchain@v1 51 | with: 52 | profile: minimal 53 | toolchain: stable 54 | override: true 55 | - name: Install embedded targets 56 | run: rustup target add thumbv6m-none-eabi thumbv7m-none-eabi 57 | - name: Install flip-link 58 | run: cargo install flip-link 59 | - name: Build bxcan for thumbv6m 60 | run: cargo build --target thumbv6m-none-eabi 61 | - name: Build testsuite for thumbv7m 62 | working-directory: testsuite 63 | run: cargo test --no-run --verbose --no-default-features --target thumbv7m-none-eabi 64 | 65 | lint: 66 | runs-on: ubuntu-latest 67 | steps: 68 | - uses: actions/checkout@v2 69 | - uses: actions-rs/toolchain@v1 70 | with: 71 | profile: minimal 72 | toolchain: stable 73 | override: true 74 | components: rustfmt 75 | - name: Check code formatting 76 | run: cargo fmt -- --check 77 | 78 | # I haven't found a good way to host the runner, and don't really have time to fix infra issues 79 | # at the moment, so the HIL suite is currently skipped. 80 | hil: 81 | runs-on: ubuntu-latest 82 | # The secrets are not supplied for 'pull_request' events, so don't run for those. 83 | if: github.event_name == 'push' && false 84 | steps: 85 | - uses: actions/checkout@v2 86 | with: 87 | fetch-depth: 0 # everything 88 | - name: Install SSH key 89 | uses: shimataro/ssh-key-action@v2 90 | with: 91 | key: ${{ secrets.SSH_KEY }} 92 | known_hosts: not needed 93 | - name: Push changes to CI repository 94 | run: | 95 | git checkout -b bxcan-ci-master 96 | git remote add ci git@github.com:jonas-schievink/bxcan-ci.git 97 | git push -u ci -f 98 | sleep 5 99 | - name: Trigger and wait for HIL workflow 100 | uses: jonas-schievink/workflow-proxy@v1 101 | with: 102 | workflow: HIL 103 | ref: bxcan-ci-master 104 | repo: jonas-schievink/bxcan-ci 105 | token: ${{ secrets.PRIVATE_CI_PERSONAL_ACCESS_TOKEN }} 106 | repost-logs: true 107 | 108 | ci: 109 | if: ${{ success() }} 110 | # all new jobs must be added to this list 111 | needs: [test, no-std, lint] 112 | runs-on: ubuntu-latest 113 | steps: 114 | - name: CI succeeded 115 | run: exit 0 116 | -------------------------------------------------------------------------------- /.github/workflows/hil.yml: -------------------------------------------------------------------------------- 1 | # This is a Hardware-In-the-Loop (HIL) workflow running on a self-hosted GHA runner. 2 | # 3 | # Due to security issues with the self-hosted runner, it is triggered from the `hil` job in 4 | # `ci.yml` and runs in a private repo. That way, only people that can push to this repo gain access 5 | # to the runner. 6 | # 7 | # The runner environment is the Docker image `myoung34/github-runner`. Additional packages must be 8 | # installed manually by the workflow. The working directory is *not* cleared between runs, in order 9 | # to avoid recompiling all the tooling. 10 | 11 | name: HIL 12 | 13 | on: 14 | workflow_dispatch: 15 | 16 | env: 17 | CARGO_TERM_COLOR: always 18 | NO_STD_TARGET: thumbv6m-none-eabi 19 | 20 | jobs: 21 | hil: 22 | runs-on: self-hosted 23 | steps: 24 | - uses: actions/checkout@v2 25 | - uses: actions-rs/toolchain@v1 26 | with: 27 | profile: minimal 28 | toolchain: stable 29 | override: true 30 | target: ${{ env.NO_STD_TARGET }} 31 | - name: Install native dependencies 32 | run: | 33 | sudo apt-get update 34 | sudo apt-get install -y libusb-1.0-0-dev pkg-config 35 | - name: Install probe-run / flip-link 36 | run: cargo install probe-run flip-link 37 | - name: Run tests on hardware 38 | working-directory: testsuite 39 | run: cargo test 40 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | target 2 | Cargo.lock 3 | -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Changelog 2 | 3 | ## Unreleased 4 | 5 | No changes. 6 | 7 | ## [0.8.0 - 2024-09-17](https://github.com/stm32-rs/bxcan/releases/tag/v0.8.0) 8 | 9 | ### Fixes 10 | 11 | * Mask out all reserved bits in `set_bit_timing` before writing the register. 12 | 13 | ### Other Changes 14 | 15 | * Update the embedded hal dependency to use the new embedded-can crate instead. 16 | 17 | ## [0.7.0 - 2022-05-30](https://github.com/stm32-rs/bxcan/releases/tag/v0.7.0) 18 | 19 | ### New Features 20 | 21 | * [*breaking change*] Add support for using the second RX FIFO. 22 | * The `Rx` type has been renamed to `Rx0`, and an `Rx1` type has been introduced that accesses the second FIFO. 23 | * `enable_bank` now takes the `Fifo` the filter should be assigned to as an additional argument. 24 | * Implement the `embedded-hal` 0.2.7 CAN traits. 25 | 26 | ### Other Changes 27 | 28 | * [*breaking change*] Removed the `embedded-can-03` feature as the `embedded-can` crate is deprecated. 29 | * [*breaking change*] Use a new `OverrunError` type as the receive error instead of `()`. 30 | 31 | ## [0.6.2 - 2021-11-15](https://github.com/stm32-rs/bxcan/releases/tag/v0.6.2) 32 | 33 | ### Fixes 34 | 35 | * Enter initialization mode when constructing a `CanBuilder` ([#49]). 36 | 37 | [#49]: https://github.com/stm32-rs/bxcan/pull/49 38 | 39 | ## [0.6.1 - 2021-11-15](https://github.com/stm32-rs/bxcan/releases/tag/v0.6.1) 40 | 41 | ### New Features 42 | 43 | * Updated to defmt 0.3.0 ([#47]). 44 | 45 | [#47]: https://github.com/stm32-rs/bxcan/pull/47 46 | 47 | ## [0.6.0 - 2021-09-05](https://github.com/stm32-rs/bxcan/releases/tag/v0.6.0) 48 | 49 | ### New Features 50 | 51 | * Add `CanConfig::set_automatic_retransmit` function to enable or disable automatic frame retransmission ([#42]). 52 | * [*breaking change*] Remove `transmit_and_get_mailbox` in favor of an improved `transmit` method ([#40]). 53 | * `Can::transmit` now returns a `TransmitStatus` struct, which contains the dequeued frame and 54 | the mailbox the new frame was placed into. 55 | * [*breaking change*] Make `CanConfig` harder to misuse ([#37]): 56 | * Methods now take `self` by value. 57 | * The `CanConfig` struct is now `#[must_use]`. 58 | * `CanConfig` leaves init mode on drop, and enables the peripheral when `.enable()` is called. 59 | * These changes make it very hard to forget to enable the peripheral after configuring, which was 60 | a common mistake in previous versions. 61 | * [*breaking change*] Replace `Can::new` with `Can::builder`, which makes it harder to forget enabling the peripheral ([#46]). 62 | 63 | ### Other Changes 64 | 65 | * [*breaking change*] Make `Can::clear_sleep_interrupt` and `Can::clear_wakeup_interrupt` take `&self` instead of `&mut self`. 66 | * [*breaking change*] Gate `embedded_can` impls behind the `embedded-can-03` Cargo feature. 67 | * [*breaking change*] Gate defmt support behind the `defmt` Cargo feature. 68 | * [*breaking change*] Removed `Can::configure` in favor of `Can::modify_config` ([#36]). 69 | 70 | [#36]: https://github.com/stm32-rs/bxcan/pull/36 71 | [#37]: https://github.com/stm32-rs/bxcan/pull/37 72 | [#40]: https://github.com/stm32-rs/bxcan/pull/40 73 | [#42]: https://github.com/stm32-rs/bxcan/pull/42 74 | [#46]: https://github.com/stm32-rs/bxcan/pull/46 75 | 76 | ## [0.5.1 - 2021-05-15](https://github.com/stm32-rs/bxcan/releases/tag/v0.5.1) 77 | 78 | ### New Features 79 | 80 | * Add transmit function that returns the mailbox number, and transmit abort function ([#25]). 81 | * Add more methods to acknowledge interrupts ([#30]). 82 | * Add `Can::free`, a way to get back ownership of the raw peripheral ([#33]). 83 | 84 | ### Fixes 85 | 86 | * The `Can::enable_interrupt` and `Can::disable_interrupt` functions now manipulate the correct bits in the interrupt 87 | enable register ([#29]). 88 | 89 | ### Misc 90 | 91 | * Improve documentation of interrupts ([#30]). 92 | 93 | [#25]: https://github.com/stm32-rs/bxcan/pull/25 94 | [#29]: https://github.com/stm32-rs/bxcan/pull/29 95 | [#30]: https://github.com/stm32-rs/bxcan/pull/30 96 | [#33]: https://github.com/stm32-rs/bxcan/pull/33 97 | 98 | ## [0.5.0 - 2021-03-15](https://github.com/stm32-rs/bxcan/releases/tag/v0.5.0) 99 | 100 | ### Breaking Changes 101 | 102 | * Update to defmt 0.2.0 ([#17]). 103 | 104 | [#17]: https://github.com/stm32-rs/bxcan/pull/17 105 | 106 | ## [0.4.0 - 2021-01-23](https://github.com/stm32-rs/bxcan/releases/tag/v0.4.0) 107 | 108 | ### Breaking Changes 109 | 110 | * Revamp filter and configuration API to allow method chaining ([#10] [#12]). 111 | 112 | ### Bugfixes 113 | 114 | * Wait for SLAK and INAK bits when changing mode ([#8]). 115 | 116 | [#8]: https://github.com/stm32-rs/bxcan/pull/8 117 | [#10]: https://github.com/stm32-rs/bxcan/pull/10 118 | [#12]: https://github.com/stm32-rs/bxcan/pull/12 119 | 120 | ### Misc 121 | 122 | * Clarify comments for the `transmit()` method ([#9]). 123 | 124 | [#9]: https://github.com/stm32-rs/bxcan/pull/9 125 | 126 | ## [0.3.0 - 2020-12-28](https://github.com/stm32-rs/bxcan/releases/tag/v0.3.0) 127 | 128 | ### New Features 129 | 130 | * Configurable mask for masked filters. 131 | * Implement the `embedded-can` traits. 132 | 133 | ### Breaking Changes 134 | 135 | * Changes to masked filters required some breaking API changes. 136 | 137 | ## [0.2.3 - 2020-12-09](https://github.com/stm32-rs/bxcan/releases/tag/v0.2.3) 138 | 139 | ### Fixes 140 | 141 | * Fix a panic when aborting transmission of a lower-priority frame. 142 | * Fix comparison when checking for a lower-priority mailbox. 143 | 144 | ## [0.2.2 - 2020-12-05](https://github.com/stm32-rs/bxcan/releases/tag/v0.2.2) 145 | 146 | ### New Features 147 | 148 | * Add `Can::is_transmitter_idle`. 149 | 150 | ## [0.2.1 - 2020-12-05](https://github.com/stm32-rs/bxcan/releases/tag/v0.2.1) 151 | 152 | ### Breaking Changes 153 | 154 | * Update `SlaveFilters::enable_bank` to also take `impl Into`. 155 | 156 | ## [0.2.0 - 2020-12-05](https://github.com/stm32-rs/bxcan/releases/tag/v0.2.0) 157 | 158 | ### New Features 159 | 160 | * Add associated constants for highest/lowest CAN IDs. 161 | 162 | ### Fixes 163 | 164 | * Update bank count when changing filter bank split. 165 | * Fix filter bank logic and document the expected behavior. 166 | * Fix filter accesses for the slave peripheral. 167 | * Fix DLC range check in `Frame::new_remote`. 168 | * Fix `PartialEq` implementation of `Frame`. 169 | 170 | ### Breaking Changes 171 | 172 | * Change some APIs to accept `impl Into` arguments to improve ergonomics. 173 | * Rename some filter methods to clarify their meaning. 174 | * Remove `MasterInstance::Slave` associated type. 175 | 176 | ## [0.1.0 - 2020-12-01](https://github.com/stm32-rs/bxcan/releases/tag/v0.1.0) 177 | 178 | Initial release. 179 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bxcan" 3 | version = "0.8.0" 4 | authors = [ 5 | "Jonas Schievink ", 6 | "Timo Kröger ", 7 | ] 8 | edition = "2021" 9 | description = "STM32 bxCAN peripheral driver" 10 | documentation = "https://docs.rs/bxcan/" 11 | repository = "https://github.com/stm32-rs/bxcan.git" 12 | keywords = ["can", "hal", "bus"] 13 | categories = ["no-std", "embedded"] 14 | readme = "README.md" 15 | license = "MIT OR Apache-2.0" 16 | 17 | [workspace] 18 | members = ["testsuite"] 19 | 20 | [badges] 21 | maintenance = { status = "actively-developed" } 22 | 23 | [dependencies] 24 | bitflags = "1.2.1" 25 | vcell = "0.1.2" 26 | nb = "1.0.0" 27 | 28 | [dependencies.embedded-can-04] 29 | version = "0.4.1" 30 | package = "embedded-can" 31 | 32 | [dependencies.defmt] 33 | optional = true 34 | version = ">=0.2.3,<0.4.0" 35 | 36 | [features] 37 | unstable-defmt = ["defmt"] 38 | 39 | [profile.test] 40 | opt-level = "s" 41 | # FIXME: Turning LTO off makes the testsuite executables 2.5x larger. 42 | # Turning it on makes `cargo test` on the host take a bit long to build. 43 | lto = true 44 | 45 | # cargo-release configuration 46 | [package.metadata.release] 47 | tag-message = "{{version}}" 48 | pre-release-commit-message = "Release {{version}}" 49 | 50 | # Change the changelog's `Unreleased` section to refer to this release and 51 | # prepend a new `Unreleased` section 52 | [[package.metadata.release.pre-release-replacements]] 53 | file = "CHANGELOG.md" 54 | search = "## Unreleased\n" 55 | replace = """ 56 | ## Unreleased 57 | 58 | No changes. 59 | 60 | ## [{{version}} - {{date}}](https://github.com/stm32-rs/bxcan/releases/tag/v{{version}}) 61 | """ 62 | 63 | # Bump the version inside the example manifest in `README.md` 64 | [[package.metadata.release.pre-release-replacements]] 65 | file = "README.md" 66 | search = 'bxcan = "[a-z0-9\\.-]+"' 67 | replace = 'bxcan = "{{version}}"' 68 | 69 | # Bump the version referenced by the `html_root_url` attribute in `lib.rs` 70 | [[package.metadata.release.pre-release-replacements]] 71 | file = "src/lib.rs" 72 | search = "https://docs.rs/bxcan/[a-z0-9\\.-]+" 73 | replace = "https://docs.rs/bxcan/{{version}}" 74 | -------------------------------------------------------------------------------- /LICENSE-APACHE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | Copyright (c) 2020 2 | 3 | Permission is hereby granted, free of charge, to any 4 | person obtaining a copy of this software and associated 5 | documentation files (the "Software"), to deal in the 6 | Software without restriction, including without 7 | limitation the rights to use, copy, modify, merge, 8 | publish, distribute, sublicense, and/or sell copies of 9 | the Software, and to permit persons to whom the Software 10 | is furnished to do so, subject to the following 11 | conditions: 12 | 13 | The above copyright notice and this permission notice 14 | shall be included in all copies or substantial portions 15 | of the Software. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF 18 | ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 19 | TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 20 | PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT 21 | SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 22 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR 24 | IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 | DEALINGS IN THE SOFTWARE. 26 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # bxCAN peripheral driver 2 | 3 | [![crates.io](https://img.shields.io/crates/v/bxcan.svg)](https://crates.io/crates/bxcan) 4 | [![docs.rs](https://docs.rs/bxcan/badge.svg)](https://docs.rs/bxcan/) 5 | ![CI](https://github.com/stm32-rs/bxcan/workflows/CI/badge.svg) 6 | 7 | This crate implements a driver for the bxCAN peripheral found in many low- to 8 | middle-end STM32 microcontrollers. 9 | 10 | Please refer to the [changelog](CHANGELOG.md) to see what changed in the last 11 | releases. 12 | 13 | ## Usage 14 | 15 | Add an entry to your `Cargo.toml`: 16 | 17 | ```toml 18 | [dependencies] 19 | bxcan = "0.8.0" 20 | ``` 21 | 22 | Check the [API Documentation](https://docs.rs/bxcan/) for how to use the 23 | crate's functionality. 24 | 25 | ## Rust version support 26 | 27 | This crate supports at least the 3 latest stable Rust releases. Bumping the 28 | minimum supported Rust version (MSRV) is not considered a breaking change as 29 | long as these 3 versions are still supported. 30 | -------------------------------------------------------------------------------- /RELEASE_PROCESS.md: -------------------------------------------------------------------------------- 1 | # What to do to publish a new release 2 | 3 | 1. Ensure all notable changes are in the changelog under "Unreleased". 4 | 5 | 2. Execute `cargo release ` to bump version(s), tag and publish 6 | everything. External subcommand, must be installed with `cargo install 7 | cargo-release`. 8 | 9 | `` can be one of `major|minor|patch`. If this is the first release 10 | (`0.1.0`), use `minor`, since the version starts out as `0.0.0`. 11 | 12 | 3. Go to the GitHub releases, edit the just-pushed tag. Copy the release notes 13 | from the changelog. 14 | -------------------------------------------------------------------------------- /src/embedded_hal.rs: -------------------------------------------------------------------------------- 1 | //! `embedded_hal` trait impls. 2 | 3 | use crate::{Can, Data, ExtendedId, Frame, Id, Instance, OverrunError, StandardId}; 4 | 5 | use embedded_can_04 as can; 6 | 7 | impl can::nb::Can for Can 8 | where 9 | I: Instance, 10 | { 11 | type Frame = Frame; 12 | 13 | type Error = OverrunError; 14 | 15 | fn transmit(&mut self, frame: &Self::Frame) -> nb::Result, Self::Error> { 16 | match self.transmit(frame) { 17 | Ok(status) => Ok(status.dequeued_frame().cloned()), 18 | Err(nb::Error::WouldBlock) => Err(nb::Error::WouldBlock), 19 | Err(nb::Error::Other(e)) => match e {}, 20 | } 21 | } 22 | 23 | fn receive(&mut self) -> nb::Result { 24 | self.receive() 25 | } 26 | } 27 | 28 | impl can::Error for OverrunError { 29 | fn kind(&self) -> can::ErrorKind { 30 | can::ErrorKind::Overrun 31 | } 32 | } 33 | 34 | impl can::Frame for Frame { 35 | fn new(id: impl Into, data: &[u8]) -> Option { 36 | let id = match id.into() { 37 | can::Id::Standard(id) => unsafe { 38 | Id::Standard(StandardId::new_unchecked(id.as_raw())) 39 | }, 40 | can::Id::Extended(id) => unsafe { 41 | Id::Extended(ExtendedId::new_unchecked(id.as_raw())) 42 | }, 43 | }; 44 | 45 | let data = Data::new(data)?; 46 | Some(Frame::new_data(id, data)) 47 | } 48 | 49 | fn new_remote(id: impl Into, dlc: usize) -> Option { 50 | let id = match id.into() { 51 | can::Id::Standard(id) => unsafe { 52 | Id::Standard(StandardId::new_unchecked(id.as_raw())) 53 | }, 54 | can::Id::Extended(id) => unsafe { 55 | Id::Extended(ExtendedId::new_unchecked(id.as_raw())) 56 | }, 57 | }; 58 | 59 | if dlc <= 8 { 60 | Some(Frame::new_remote(id, dlc as u8)) 61 | } else { 62 | None 63 | } 64 | } 65 | 66 | #[inline] 67 | fn is_extended(&self) -> bool { 68 | self.is_extended() 69 | } 70 | 71 | #[inline] 72 | fn is_remote_frame(&self) -> bool { 73 | self.is_remote_frame() 74 | } 75 | 76 | #[inline] 77 | fn id(&self) -> can::Id { 78 | match self.id() { 79 | Id::Standard(id) => unsafe { 80 | can::Id::Standard(can::StandardId::new_unchecked(id.as_raw())) 81 | }, 82 | Id::Extended(id) => unsafe { 83 | can::Id::Extended(can::ExtendedId::new_unchecked(id.as_raw())) 84 | }, 85 | } 86 | } 87 | 88 | #[inline] 89 | fn dlc(&self) -> usize { 90 | self.dlc().into() 91 | } 92 | 93 | fn data(&self) -> &[u8] { 94 | if let Some(data) = self.data() { 95 | data 96 | } else { 97 | &[] 98 | } 99 | } 100 | } 101 | -------------------------------------------------------------------------------- /src/frame.rs: -------------------------------------------------------------------------------- 1 | #[cfg(test)] 2 | mod tests; 3 | 4 | use core::cmp::Ordering; 5 | use core::ops::{Deref, DerefMut}; 6 | 7 | use crate::{Id, IdReg}; 8 | 9 | /// A CAN data or remote frame. 10 | #[derive(Clone, Debug, Eq)] 11 | #[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))] 12 | pub struct Frame { 13 | pub(crate) id: IdReg, 14 | pub(crate) data: Data, 15 | } 16 | 17 | impl Frame { 18 | /// Creates a new data frame. 19 | pub fn new_data(id: impl Into, data: impl Into) -> Self { 20 | let id = match id.into() { 21 | Id::Standard(id) => IdReg::new_standard(id), 22 | Id::Extended(id) => IdReg::new_extended(id), 23 | }; 24 | 25 | Self { 26 | id, 27 | data: data.into(), 28 | } 29 | } 30 | 31 | /// Creates a new remote frame with configurable data length code (DLC). 32 | /// 33 | /// # Panics 34 | /// 35 | /// This function will panic if `dlc` is not inside the valid range `0..=8`. 36 | pub fn new_remote(id: impl Into, dlc: u8) -> Self { 37 | assert!(dlc <= 8); 38 | 39 | let mut frame = Self::new_data(id, []); 40 | // Just extend the data length, even with no data present. The API does not hand out this 41 | // `Data` object. 42 | frame.data.len = dlc; 43 | frame.id = frame.id.with_rtr(true); 44 | frame 45 | } 46 | 47 | /// Returns true if this frame is an extended frame. 48 | #[inline] 49 | pub fn is_extended(&self) -> bool { 50 | self.id.is_extended() 51 | } 52 | 53 | /// Returns true if this frame is a standard frame. 54 | #[inline] 55 | pub fn is_standard(&self) -> bool { 56 | self.id.is_standard() 57 | } 58 | 59 | /// Returns true if this frame is a remote frame. 60 | #[inline] 61 | pub fn is_remote_frame(&self) -> bool { 62 | self.id.rtr() 63 | } 64 | 65 | /// Returns true if this frame is a data frame. 66 | #[inline] 67 | pub fn is_data_frame(&self) -> bool { 68 | !self.is_remote_frame() 69 | } 70 | 71 | /// Returns the frame identifier. 72 | #[inline] 73 | pub fn id(&self) -> Id { 74 | self.id.to_id() 75 | } 76 | 77 | /// Returns the priority of this frame. 78 | #[inline] 79 | pub fn priority(&self) -> FramePriority { 80 | FramePriority(self.id) 81 | } 82 | 83 | /// Returns the data length code (DLC) which is in the range 0..8. 84 | /// 85 | /// For data frames the DLC value always matches the length of the data. 86 | /// Remote frames do not carry any data, yet the DLC can be greater than 0. 87 | #[inline] 88 | pub fn dlc(&self) -> u8 { 89 | self.data.len() as u8 90 | } 91 | 92 | /// Returns the frame data (0..8 bytes in length) if this is a data frame. 93 | /// 94 | /// If this is a remote frame, returns `None`. 95 | pub fn data(&self) -> Option<&Data> { 96 | if self.is_data_frame() { 97 | Some(&self.data) 98 | } else { 99 | None 100 | } 101 | } 102 | } 103 | 104 | impl PartialEq for Frame { 105 | fn eq(&self, other: &Self) -> bool { 106 | match (self.data(), other.data()) { 107 | (None, None) => self.id.eq(&other.id), 108 | (Some(a), Some(b)) => self.id.eq(&other.id) && a.eq(b), 109 | (None, Some(_)) | (Some(_), None) => false, 110 | } 111 | } 112 | } 113 | 114 | /// Priority of a CAN frame. 115 | /// 116 | /// Returned by [`Frame::priority`]. 117 | /// 118 | /// The priority of a frame is determined by the bits that are part of the *arbitration field*. 119 | /// These consist of the frame identifier bits (including the *IDE* bit, which is 0 for extended 120 | /// frames and 1 for standard frames), as well as the *RTR* bit, which determines whether a frame 121 | /// is a data or remote frame. Lower values of the *arbitration field* have higher priority. 122 | /// 123 | /// This struct wraps the *arbitration field* and implements `PartialOrd` and `Ord` accordingly, 124 | /// ordering higher priorities greater than lower ones. 125 | #[derive(Debug, Copy, Clone)] 126 | pub struct FramePriority(IdReg); 127 | 128 | /// Ordering is based on the Identifier and frame type (data vs. remote) and can be used to sort 129 | /// frames by priority. 130 | impl Ord for FramePriority { 131 | fn cmp(&self, other: &Self) -> Ordering { 132 | self.0.cmp(&other.0) 133 | } 134 | } 135 | 136 | impl PartialOrd for FramePriority { 137 | fn partial_cmp(&self, other: &Self) -> Option { 138 | Some(self.cmp(other)) 139 | } 140 | } 141 | 142 | impl PartialEq for FramePriority { 143 | fn eq(&self, other: &Self) -> bool { 144 | self.cmp(other) == Ordering::Equal 145 | } 146 | } 147 | 148 | impl Eq for FramePriority {} 149 | 150 | /// Payload of a CAN data frame. 151 | /// 152 | /// Contains 0 to 8 Bytes of data. 153 | /// 154 | /// `Data` implements `From<[u8; N]>` for all `N` up to 8, which provides a convenient lossless 155 | /// conversion from fixed-length arrays. 156 | #[derive(Debug, Copy, Clone)] 157 | pub struct Data { 158 | pub(crate) len: u8, 159 | pub(crate) bytes: [u8; 8], 160 | } 161 | 162 | impl Data { 163 | /// Creates a data payload from a raw byte slice. 164 | /// 165 | /// Returns `None` if `data` contains more than 8 Bytes (which is the maximum). 166 | /// 167 | /// `Data` can also be constructed from fixed-length arrays up to length 8 via `From`/`Into`. 168 | pub fn new(data: &[u8]) -> Option { 169 | if data.len() > 8 { 170 | return None; 171 | } 172 | 173 | let mut bytes = [0; 8]; 174 | bytes[..data.len()].copy_from_slice(data); 175 | 176 | Some(Self { 177 | len: data.len() as u8, 178 | bytes, 179 | }) 180 | } 181 | 182 | /// Creates an empty data payload containing 0 bytes. 183 | #[inline] 184 | pub const fn empty() -> Self { 185 | Self { 186 | len: 0, 187 | bytes: [0; 8], 188 | } 189 | } 190 | } 191 | 192 | impl Deref for Data { 193 | type Target = [u8]; 194 | 195 | #[inline] 196 | fn deref(&self) -> &[u8] { 197 | &self.bytes[..usize::from(self.len)] 198 | } 199 | } 200 | 201 | impl DerefMut for Data { 202 | #[inline] 203 | fn deref_mut(&mut self) -> &mut [u8] { 204 | &mut self.bytes[..usize::from(self.len)] 205 | } 206 | } 207 | 208 | impl AsRef<[u8]> for Data { 209 | #[inline] 210 | fn as_ref(&self) -> &[u8] { 211 | self.deref() 212 | } 213 | } 214 | 215 | impl AsMut<[u8]> for Data { 216 | #[inline] 217 | fn as_mut(&mut self) -> &mut [u8] { 218 | self.deref_mut() 219 | } 220 | } 221 | 222 | impl PartialEq for Data { 223 | fn eq(&self, other: &Self) -> bool { 224 | self.as_ref() == other.as_ref() 225 | } 226 | } 227 | 228 | impl Eq for Data {} 229 | 230 | #[cfg(feature = "unstable-defmt")] 231 | impl defmt::Format for Data { 232 | fn format(&self, fmt: defmt::Formatter<'_>) { 233 | self.as_ref().format(fmt) 234 | } 235 | } 236 | 237 | macro_rules! data_from_array { 238 | ( $($len:literal),+ ) => { 239 | $( 240 | impl From<[u8; $len]> for Data { 241 | #[inline] 242 | fn from(arr: [u8; $len]) -> Self { 243 | let mut bytes = [0; 8]; 244 | bytes[..$len].copy_from_slice(&arr); 245 | Self { 246 | len: $len, 247 | bytes, 248 | } 249 | } 250 | } 251 | )+ 252 | }; 253 | } 254 | 255 | data_from_array!(0, 1, 2, 3, 4, 5, 6, 7, 8); 256 | -------------------------------------------------------------------------------- /src/frame/tests.rs: -------------------------------------------------------------------------------- 1 | use crate::{ExtendedId, Frame, StandardId}; 2 | 3 | #[test] 4 | fn data_greater_remote() { 5 | let id = StandardId::new(0).unwrap(); 6 | 7 | let data_frame = Frame::new_data(id, []); 8 | let remote_frame = Frame::new_remote(id, 0); 9 | assert!(data_frame.is_data_frame()); 10 | assert!(remote_frame.is_remote_frame()); 11 | 12 | assert!(data_frame.priority() > remote_frame.priority()); 13 | } 14 | 15 | #[test] 16 | fn lower_ids_win_arbitration() { 17 | let zero = Frame::new_data(StandardId::new(0).unwrap(), []); 18 | let one = Frame::new_data(StandardId::new(1).unwrap(), []); 19 | assert!(zero.is_standard()); 20 | assert!(!zero.is_extended()); 21 | assert!(one.is_standard()); 22 | assert!(!one.is_extended()); 23 | assert!(zero.priority() > one.priority()); 24 | 25 | // Standard IDs have priority over Extended IDs if the Base ID matches. 26 | let ext_one = Frame::new_data( 27 | ExtendedId::new(0b00000000001_000000000000000000).unwrap(), 28 | [], 29 | ); 30 | assert!(!ext_one.is_standard()); 31 | assert!(ext_one.is_extended()); 32 | assert!(one.priority() > ext_one.priority()); 33 | assert!(zero.priority() > ext_one.priority()); 34 | 35 | // Ext. ID with Base ID 0 has priority over Standard ID 1. 36 | let ext_zero = Frame::new_data( 37 | ExtendedId::new(0b00000000000_100000000000000000).unwrap(), 38 | [], 39 | ); 40 | assert!(!ext_zero.is_standard()); 41 | assert!(ext_zero.is_extended()); 42 | assert!(one.priority() < ext_zero.priority()); 43 | // ...but not over Standard ID 0. 44 | assert!(zero.priority() > ext_zero.priority()); 45 | } 46 | 47 | #[test] 48 | fn highest_standard_higher_prio_than_highest_ext() { 49 | let std = Frame::new_data(StandardId::MAX, []); 50 | let ext = Frame::new_data(ExtendedId::MAX, []); 51 | 52 | assert!(std.is_standard()); 53 | assert!(!std.is_extended()); 54 | assert!(!ext.is_standard()); 55 | assert!(ext.is_extended()); 56 | assert!(std.priority() > ext.priority()); 57 | } 58 | 59 | #[test] 60 | fn data_neq_remote() { 61 | let id = StandardId::new(0).unwrap(); 62 | 63 | let data_frame = Frame::new_data(id, []); 64 | let remote_frame = Frame::new_remote(id, 0); 65 | 66 | assert_ne!(data_frame, remote_frame); 67 | } 68 | 69 | #[test] 70 | fn remote_eq_remote_ignores_data() { 71 | let mut remote1 = Frame::new_remote(StandardId::MAX, 7); 72 | let mut remote2 = Frame::new_remote(StandardId::MAX, 7); 73 | 74 | remote1.data.bytes = [0xAA; 8]; 75 | remote2.data.bytes = [0x55; 8]; 76 | 77 | assert_eq!(remote1, remote2); 78 | } 79 | 80 | #[test] 81 | fn max_len() { 82 | Frame::new_data(StandardId::MAX, [0; 8]); 83 | Frame::new_remote(StandardId::MAX, 8); 84 | } 85 | -------------------------------------------------------------------------------- /src/id.rs: -------------------------------------------------------------------------------- 1 | //! CAN Identifiers. 2 | 3 | /// Standard 11-bit CAN Identifier (`0..=0x7FF`). 4 | #[derive(Debug, Copy, Clone, Eq, PartialEq)] 5 | pub struct StandardId(u16); 6 | 7 | impl StandardId { 8 | /// CAN ID `0`, the highest priority. 9 | pub const ZERO: Self = Self(0); 10 | 11 | /// CAN ID `0x7FF`, the lowest priority. 12 | pub const MAX: Self = Self(0x7FF); 13 | 14 | /// Tries to create a `StandardId` from a raw 16-bit integer. 15 | /// 16 | /// This will return `None` if `raw` is out of range of an 11-bit integer (`> 0x7FF`). 17 | #[inline] 18 | pub const fn new(raw: u16) -> Option { 19 | if raw <= 0x7FF { 20 | Some(Self(raw)) 21 | } else { 22 | None 23 | } 24 | } 25 | 26 | /// Creates a new `StandardId` without checking if it is inside the valid range. 27 | /// 28 | /// # Safety 29 | /// 30 | /// The caller must ensure that `raw` is in the valid range, otherwise the behavior is 31 | /// undefined. 32 | #[inline] 33 | pub const unsafe fn new_unchecked(raw: u16) -> Self { 34 | Self(raw) 35 | } 36 | 37 | /// Returns this CAN Identifier as a raw 16-bit integer. 38 | #[inline] 39 | pub fn as_raw(&self) -> u16 { 40 | self.0 41 | } 42 | } 43 | 44 | /// Extended 29-bit CAN Identifier (`0..=1FFF_FFFF`). 45 | #[derive(Debug, Copy, Clone, Eq, PartialEq)] 46 | pub struct ExtendedId(u32); 47 | 48 | impl ExtendedId { 49 | /// CAN ID `0`, the highest priority. 50 | pub const ZERO: Self = Self(0); 51 | 52 | /// CAN ID `0x1FFFFFFF`, the lowest priority. 53 | pub const MAX: Self = Self(0x1FFF_FFFF); 54 | 55 | /// Tries to create a `ExtendedId` from a raw 32-bit integer. 56 | /// 57 | /// This will return `None` if `raw` is out of range of an 29-bit integer (`> 0x1FFF_FFFF`). 58 | #[inline] 59 | pub const fn new(raw: u32) -> Option { 60 | if raw <= 0x1FFF_FFFF { 61 | Some(Self(raw)) 62 | } else { 63 | None 64 | } 65 | } 66 | 67 | /// Creates a new `ExtendedId` without checking if it is inside the valid range. 68 | /// 69 | /// # Safety 70 | /// 71 | /// The caller must ensure that `raw` is in the valid range, otherwise the behavior is 72 | /// undefined. 73 | #[inline] 74 | pub const unsafe fn new_unchecked(raw: u32) -> Self { 75 | Self(raw) 76 | } 77 | 78 | /// Returns this CAN Identifier as a raw 32-bit integer. 79 | #[inline] 80 | pub fn as_raw(&self) -> u32 { 81 | self.0 82 | } 83 | 84 | /// Returns the Base ID part of this extended identifier. 85 | pub fn standard_id(&self) -> StandardId { 86 | // ID-28 to ID-18 87 | StandardId((self.0 >> 18) as u16) 88 | } 89 | } 90 | 91 | /// A CAN Identifier (standard or extended). 92 | #[derive(Debug, Copy, Clone, Eq, PartialEq)] 93 | pub enum Id { 94 | /// Standard 11-bit Identifier (`0..=0x7FF`). 95 | Standard(StandardId), 96 | 97 | /// Extended 29-bit Identifier (`0..=0x1FFF_FFFF`). 98 | Extended(ExtendedId), 99 | } 100 | 101 | impl From for Id { 102 | #[inline] 103 | fn from(id: StandardId) -> Self { 104 | Id::Standard(id) 105 | } 106 | } 107 | 108 | impl From for Id { 109 | #[inline] 110 | fn from(id: ExtendedId) -> Self { 111 | Id::Extended(id) 112 | } 113 | } 114 | -------------------------------------------------------------------------------- /src/interrupt.rs: -------------------------------------------------------------------------------- 1 | //! Interrupt types. 2 | 3 | use core::ops; 4 | 5 | #[allow(unused_imports)] // for intra-doc links only 6 | use crate::{Can, Rx0}; 7 | 8 | /// bxCAN interrupt sources. 9 | /// 10 | /// These can be individually enabled and disabled in the bxCAN peripheral. Note that the bxCAN 11 | /// peripheral only exposes 4 interrupts to the microcontroller: 12 | /// 13 | /// * TX 14 | /// * RX FIFO 1 15 | /// * RX FIFO 2 16 | /// * SCE (Status Change Error) 17 | /// 18 | /// This means that some of the interrupts listed here will result in the same interrupt handler 19 | /// being invoked. 20 | #[derive(Debug, Copy, Clone, Eq, PartialEq)] 21 | #[cfg_attr(feature = "unstable-defmt", derive(defmt::Format))] 22 | #[non_exhaustive] 23 | pub enum Interrupt { 24 | /// Fires the **TX** interrupt when one of the transmit mailboxes returns to empty state. 25 | /// 26 | /// This usually happens because its message was either transmitted successfully, or 27 | /// transmission was aborted successfully. 28 | /// 29 | /// The interrupt handler must clear the interrupt condition by calling 30 | /// [`Can::clear_request_completed_flag`] or [`Can::clear_tx_interrupt`]. 31 | TransmitMailboxEmpty = 1 << 0, 32 | 33 | /// Fires the **RX FIFO 0** interrupt when FIFO 0 holds a message. 34 | /// 35 | /// The interrupt handler must clear the interrupt condition by receiving all messages from the 36 | /// FIFO by calling [`Can::receive`] or [`Rx0::receive`]. 37 | Fifo0MessagePending = 1 << 1, 38 | 39 | /// Fires the **RX FIFO 0** interrupt when FIFO 0 holds 3 incoming messages. 40 | /// 41 | /// The interrupt handler must clear the interrupt condition by receiving at least one message 42 | /// from the FIFO (making it no longer "full"). This can be done by calling [`Can::receive`] or 43 | /// [`Rx0::receive`]. 44 | Fifo0Full = 1 << 2, 45 | 46 | /// Fires the **RX FIFO 0** interrupt when FIFO 0 drops an incoming message. 47 | /// 48 | /// The interrupt handler must clear the interrupt condition by calling [`Can::receive`] or 49 | /// [`Rx0::receive`] (which will return an error). 50 | Fifo0Overrun = 1 << 3, 51 | 52 | /// Fires the **RX FIFO 1** interrupt when FIFO 1 holds a message. 53 | /// 54 | /// Behavior is otherwise identical to [`Self::Fifo0MessagePending`]. 55 | Fifo1MessagePending = 1 << 4, 56 | 57 | /// Fires the **RX FIFO 1** interrupt when FIFO 1 holds 3 incoming messages. 58 | /// 59 | /// Behavior is otherwise identical to [`Self::Fifo0Full`]. 60 | Fifo1Full = 1 << 5, 61 | 62 | /// Fires the **RX FIFO 1** interrupt when FIFO 1 drops an incoming message. 63 | /// 64 | /// Behavior is otherwise identical to [`Self::Fifo0Overrun`]. 65 | Fifo1Overrun = 1 << 6, 66 | 67 | /// Fires the **SCE** interrupt when the error warning limit (receive or transmit error counter 68 | /// >= 96) has been reached. 69 | /// 70 | /// [`Interrupt::Error`] must also be enabled for the interrupt to fire. 71 | /// 72 | /// The interrupt handler must clear the interrupt condition by calling 73 | /// [`Can::clear_error_interrupt`]. 74 | ErrorWarning = 1 << 8, 75 | 76 | /// Fires the **SCE** interrupt when the peripheral enters the error passive state. 77 | /// 78 | /// [`Interrupt::Error`] must also be enabled for the interrupt to fire. 79 | /// 80 | /// The interrupt handler must clear the interrupt condition by calling 81 | /// [`Can::clear_error_interrupt`]. 82 | ErrorPassive = 1 << 9, 83 | 84 | /// Fires the **SCE** interrupt when the peripheral has entered bus-off. 85 | /// 86 | /// [`Interrupt::Error`] must also be enabled for the interrupt to fire. 87 | /// 88 | /// The interrupt handler must clear the interrupt condition by calling 89 | /// [`Can::clear_error_interrupt`]. 90 | BusOff = 1 << 10, 91 | 92 | /// Fires the **SCE** interrupt when the peripheral updates the last error code. 93 | /// 94 | /// [`Interrupt::Error`] must also be enabled for the interrupt to fire. 95 | /// 96 | /// The interrupt handler must clear the interrupt condition by calling 97 | /// [`Can::clear_error_interrupt`]. 98 | LastErrorCode = 1 << 11, 99 | 100 | /// Fires the **SCE** interrupt when the peripheral enters an error state. 101 | /// 102 | /// The error states that will cause the interrupt to fire are determined by the subset of 103 | /// [`Interrupt::ErrorWarning`], [`Interrupt::ErrorPassive`], [`Interrupt::BusOff`], and 104 | /// [`Interrupt::LastErrorCode`] that are enabled along with this flag. 105 | /// 106 | /// The interrupt handler must clear the interrupt condition by calling 107 | /// [`Can::clear_error_interrupt`]. 108 | Error = 1 << 15, 109 | 110 | /// Fires the **SCE** interrupt when an incoming CAN frame is detected while the peripheral is 111 | /// in sleep mode. 112 | /// 113 | /// The interrupt handler must clear the interrupt condition by calling 114 | /// [`Can::clear_wakeup_interrupt`]. 115 | Wakeup = 1 << 16, 116 | 117 | /// Fires the **SCE** interrupt when the peripheral enters sleep mode. 118 | /// 119 | /// The interrupt handler must clear the interrupt condition by calling 120 | /// [`Can::clear_sleep_interrupt`]. 121 | Sleep = 1 << 17, 122 | } 123 | 124 | bitflags::bitflags! { 125 | /// A set of bxCAN interrupts. 126 | pub struct Interrupts: u32 { 127 | const TRANSMIT_MAILBOX_EMPTY = 1 << 0; 128 | const FIFO0_MESSAGE_PENDING = 1 << 1; 129 | const FIFO0_FULL = 1 << 2; 130 | const FIFO0_OVERRUN = 1 << 3; 131 | const FIFO1_MESSAGE_PENDING = 1 << 4; 132 | const FIFO1_FULL = 1 << 5; 133 | const FIFO1_OVERRUN = 1 << 6; 134 | const ERROR_WARNING = 1 << 8; 135 | const ERROR_PASSIVE = 1 << 9; 136 | const BUS_OFF = 1 << 10; 137 | const LAST_ERROR_CODE = 1 << 11; 138 | const ERROR = 1 << 15; 139 | const WAKEUP = 1 << 16; 140 | const SLEEP = 1 << 17; 141 | } 142 | } 143 | 144 | impl From for Interrupts { 145 | #[inline] 146 | fn from(i: Interrupt) -> Self { 147 | Self::from_bits_truncate(i as u32) 148 | } 149 | } 150 | 151 | /// Adds an interrupt to the interrupt set. 152 | impl ops::BitOrAssign for Interrupts { 153 | #[inline] 154 | fn bitor_assign(&mut self, rhs: Interrupt) { 155 | *self |= Self::from(rhs); 156 | } 157 | } 158 | 159 | #[cfg(test)] 160 | mod tests { 161 | use super::*; 162 | 163 | #[test] 164 | fn interrupt_flags() { 165 | assert_eq!(Interrupts::from(Interrupt::Sleep), Interrupts::SLEEP); 166 | assert_eq!( 167 | Interrupts::from(Interrupt::TransmitMailboxEmpty), 168 | Interrupts::TRANSMIT_MAILBOX_EMPTY 169 | ); 170 | 171 | let mut ints = Interrupts::FIFO0_FULL; 172 | ints |= Interrupt::Fifo1Full; 173 | assert_eq!(ints, Interrupts::FIFO0_FULL | Interrupts::FIFO1_FULL); 174 | } 175 | } 176 | -------------------------------------------------------------------------------- /src/pac/can.rs: -------------------------------------------------------------------------------- 1 | /// Register block of bxCAN peripherals. 2 | #[repr(C)] 3 | pub struct RegisterBlock { 4 | #[doc = "0x00 - CAN_MCR"] 5 | pub(crate) mcr: MCR, 6 | #[doc = "0x04 - CAN_MSR"] 7 | pub(crate) msr: MSR, 8 | #[doc = "0x08 - CAN_TSR"] 9 | pub(crate) tsr: TSR, 10 | #[doc = "0x0c - CAN_RF0R"] 11 | pub(crate) rfr: [RFR; 2], 12 | #[doc = "0x14 - CAN_IER"] 13 | pub(crate) ier: IER, 14 | #[doc = "0x18 - CAN_ESR"] 15 | pub(crate) esr: ESR, 16 | #[doc = "0x1c - CAN_BTR"] 17 | pub(crate) btr: BTR, 18 | _reserved7: [u8; 352usize], 19 | #[doc = "0x180 - CAN Transmit cluster"] 20 | pub(crate) tx: [TX; 3], 21 | #[doc = "0x1b0 - CAN Receive cluster"] 22 | pub(crate) rx: [RX; 2], 23 | _reserved9: [u8; 48usize], 24 | #[doc = "0x200 - CAN_FMR"] 25 | pub(crate) fmr: FMR, 26 | #[doc = "0x204 - CAN_FM1R"] 27 | pub(crate) fm1r: FM1R, 28 | _reserved11: [u8; 4usize], 29 | #[doc = "0x20c - CAN_FS1R"] 30 | pub(crate) fs1r: FS1R, 31 | _reserved12: [u8; 4usize], 32 | #[doc = "0x214 - CAN_FFA1R"] 33 | pub(crate) ffa1r: FFA1R, 34 | _reserved13: [u8; 4usize], 35 | #[doc = "0x21c - CAN_FA1R"] 36 | pub(crate) fa1r: FA1R, 37 | _reserved14: [u8; 32usize], 38 | #[doc = "0x240 - CAN Filter Bank cluster"] 39 | pub(crate) fb: [FB; 28], // UP TO 28, but 14 in some devices 40 | } 41 | #[doc = r"Register block"] 42 | #[repr(C)] 43 | pub struct TX { 44 | #[doc = "0x00 - CAN_TI0R"] 45 | pub tir: self::tx::TIR, 46 | #[doc = "0x04 - CAN_TDT0R"] 47 | pub tdtr: self::tx::TDTR, 48 | #[doc = "0x08 - CAN_TDL0R"] 49 | pub tdlr: self::tx::TDLR, 50 | #[doc = "0x0c - CAN_TDH0R"] 51 | pub tdhr: self::tx::TDHR, 52 | } 53 | #[doc = r"Register block"] 54 | #[doc = "CAN Transmit cluster"] 55 | pub mod tx; 56 | #[doc = r"Register block"] 57 | #[repr(C)] 58 | pub struct RX { 59 | #[doc = "0x00 - CAN_RI0R"] 60 | pub rir: self::rx::RIR, 61 | #[doc = "0x04 - CAN_RDT0R"] 62 | pub rdtr: self::rx::RDTR, 63 | #[doc = "0x08 - CAN_RDL0R"] 64 | pub rdlr: self::rx::RDLR, 65 | #[doc = "0x0c - CAN_RDH0R"] 66 | pub rdhr: self::rx::RDHR, 67 | } 68 | #[doc = r"Register block"] 69 | #[doc = "CAN Receive cluster"] 70 | pub mod rx; 71 | #[doc = r"Register block"] 72 | #[repr(C)] 73 | pub struct FB { 74 | #[doc = "0x00 - Filter bank 0 register 1"] 75 | pub fr1: self::fb::FR1, 76 | #[doc = "0x04 - Filter bank 0 register 2"] 77 | pub fr2: self::fb::FR2, 78 | } 79 | #[doc = r"Register block"] 80 | #[doc = "CAN Filter Bank cluster"] 81 | pub mod fb; 82 | #[doc = "CAN_MCR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](mcr) module"] 83 | pub type MCR = crate::Reg; 84 | #[allow(missing_docs)] 85 | #[doc(hidden)] 86 | pub struct _MCR; 87 | #[doc = "`read()` method returns [mcr::R](mcr::R) reader structure"] 88 | impl crate::Readable for MCR {} 89 | #[doc = "`write(|w| ..)` method takes [mcr::W](mcr::W) writer structure"] 90 | impl crate::Writable for MCR {} 91 | #[doc = "CAN_MCR"] 92 | pub mod mcr; 93 | #[doc = "CAN_MSR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](msr) module"] 94 | pub type MSR = crate::Reg; 95 | #[allow(missing_docs)] 96 | #[doc(hidden)] 97 | pub struct _MSR; 98 | #[doc = "`read()` method returns [msr::R](msr::R) reader structure"] 99 | impl crate::Readable for MSR {} 100 | #[doc = "`write(|w| ..)` method takes [msr::W](msr::W) writer structure"] 101 | impl crate::Writable for MSR {} 102 | #[doc = "CAN_MSR"] 103 | pub mod msr; 104 | #[doc = "CAN_TSR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tsr](tsr) module"] 105 | pub type TSR = crate::Reg; 106 | #[allow(missing_docs)] 107 | #[doc(hidden)] 108 | pub struct _TSR; 109 | #[doc = "`read()` method returns [tsr::R](tsr::R) reader structure"] 110 | impl crate::Readable for TSR {} 111 | #[doc = "`write(|w| ..)` method takes [tsr::W](tsr::W) writer structure"] 112 | impl crate::Writable for TSR {} 113 | #[doc = "CAN_TSR"] 114 | pub mod tsr; 115 | #[doc = "CAN_RF0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfr](rfr) module"] 116 | pub type RFR = crate::Reg; 117 | #[allow(missing_docs)] 118 | #[doc(hidden)] 119 | pub struct _RFR; 120 | #[doc = "`read()` method returns [rfr::R](rfr::R) reader structure"] 121 | impl crate::Readable for RFR {} 122 | #[doc = "`write(|w| ..)` method takes [rfr::W](rfr::W) writer structure"] 123 | impl crate::Writable for RFR {} 124 | #[doc = "CAN_RF0R"] 125 | pub mod rfr; 126 | #[doc = "CAN_IER\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](ier) module"] 127 | pub type IER = crate::Reg; 128 | #[allow(missing_docs)] 129 | #[doc(hidden)] 130 | pub struct _IER; 131 | #[doc = "`read()` method returns [ier::R](ier::R) reader structure"] 132 | impl crate::Readable for IER {} 133 | #[doc = "`write(|w| ..)` method takes [ier::W](ier::W) writer structure"] 134 | impl crate::Writable for IER {} 135 | #[doc = "CAN_IER"] 136 | pub mod ier; 137 | #[doc = "CAN_ESR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [esr](esr) module"] 138 | pub type ESR = crate::Reg; 139 | #[allow(missing_docs)] 140 | #[doc(hidden)] 141 | pub struct _ESR; 142 | #[doc = "`read()` method returns [esr::R](esr::R) reader structure"] 143 | impl crate::Readable for ESR {} 144 | #[doc = "`write(|w| ..)` method takes [esr::W](esr::W) writer structure"] 145 | impl crate::Writable for ESR {} 146 | #[doc = "CAN_ESR"] 147 | pub mod esr; 148 | #[doc = "CAN_BTR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [btr](btr) module"] 149 | pub type BTR = crate::Reg; 150 | #[allow(missing_docs)] 151 | #[doc(hidden)] 152 | pub struct _BTR; 153 | #[doc = "`read()` method returns [btr::R](btr::R) reader structure"] 154 | impl crate::Readable for BTR {} 155 | #[doc = "`write(|w| ..)` method takes [btr::W](btr::W) writer structure"] 156 | impl crate::Writable for BTR {} 157 | #[doc = "CAN_BTR"] 158 | pub mod btr; 159 | #[doc = "CAN_FMR\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fmr](fmr) module"] 160 | pub type FMR = crate::Reg; 161 | #[allow(missing_docs)] 162 | #[doc(hidden)] 163 | pub struct _FMR; 164 | #[doc = "`read()` method returns [fmr::R](fmr::R) reader structure"] 165 | impl crate::Readable for FMR {} 166 | #[doc = "`write(|w| ..)` method takes [fmr::W](fmr::W) writer structure"] 167 | impl crate::Writable for FMR {} 168 | #[doc = "CAN_FMR"] 169 | pub mod fmr; 170 | #[doc = "CAN_FM1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fm1r](fm1r) module"] 171 | pub type FM1R = crate::Reg; 172 | #[allow(missing_docs)] 173 | #[doc(hidden)] 174 | pub struct _FM1R; 175 | #[doc = "`read()` method returns [fm1r::R](fm1r::R) reader structure"] 176 | impl crate::Readable for FM1R {} 177 | #[doc = "`write(|w| ..)` method takes [fm1r::W](fm1r::W) writer structure"] 178 | impl crate::Writable for FM1R {} 179 | #[doc = "CAN_FM1R"] 180 | pub mod fm1r; 181 | #[doc = "CAN_FS1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fs1r](fs1r) module"] 182 | pub type FS1R = crate::Reg; 183 | #[allow(missing_docs)] 184 | #[doc(hidden)] 185 | pub struct _FS1R; 186 | #[doc = "`read()` method returns [fs1r::R](fs1r::R) reader structure"] 187 | impl crate::Readable for FS1R {} 188 | #[doc = "`write(|w| ..)` method takes [fs1r::W](fs1r::W) writer structure"] 189 | impl crate::Writable for FS1R {} 190 | #[doc = "CAN_FS1R"] 191 | pub mod fs1r; 192 | #[doc = "CAN_FFA1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ffa1r](ffa1r) module"] 193 | pub type FFA1R = crate::Reg; 194 | #[allow(missing_docs)] 195 | #[doc(hidden)] 196 | pub struct _FFA1R; 197 | #[doc = "`read()` method returns [ffa1r::R](ffa1r::R) reader structure"] 198 | impl crate::Readable for FFA1R {} 199 | #[doc = "`write(|w| ..)` method takes [ffa1r::W](ffa1r::W) writer structure"] 200 | impl crate::Writable for FFA1R {} 201 | #[doc = "CAN_FFA1R"] 202 | pub mod ffa1r; 203 | #[doc = "CAN_FA1R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fa1r](fa1r) module"] 204 | pub type FA1R = crate::Reg; 205 | #[allow(missing_docs)] 206 | #[doc(hidden)] 207 | pub struct _FA1R; 208 | #[doc = "`read()` method returns [fa1r::R](fa1r::R) reader structure"] 209 | impl crate::Readable for FA1R {} 210 | #[doc = "`write(|w| ..)` method takes [fa1r::W](fa1r::W) writer structure"] 211 | impl crate::Writable for FA1R {} 212 | #[doc = "CAN_FA1R"] 213 | pub mod fa1r; 214 | -------------------------------------------------------------------------------- /src/pac/can/btr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register BTR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register BTR"] 4 | pub type W = crate::W; 5 | #[doc = "Register BTR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::BTR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "SILM\n\nValue on reset: 0"] 14 | #[derive(Clone, Copy, Debug, PartialEq)] 15 | pub enum SILM_A { 16 | #[doc = "0: Normal operation"] 17 | NORMAL = 0, 18 | #[doc = "1: Silent Mode"] 19 | SILENT = 1, 20 | } 21 | impl From for bool { 22 | #[inline(always)] 23 | fn from(variant: SILM_A) -> Self { 24 | variant as u8 != 0 25 | } 26 | } 27 | #[doc = "Reader of field `SILM`"] 28 | pub type SILM_R = crate::R; 29 | impl SILM_R { 30 | #[doc = r"Get enumerated values variant"] 31 | #[inline(always)] 32 | pub fn variant(&self) -> SILM_A { 33 | match self.bits { 34 | false => SILM_A::NORMAL, 35 | true => SILM_A::SILENT, 36 | } 37 | } 38 | #[doc = "Checks if the value of the field is `NORMAL`"] 39 | #[inline(always)] 40 | pub fn is_normal(&self) -> bool { 41 | *self == SILM_A::NORMAL 42 | } 43 | #[doc = "Checks if the value of the field is `SILENT`"] 44 | #[inline(always)] 45 | pub fn is_silent(&self) -> bool { 46 | *self == SILM_A::SILENT 47 | } 48 | } 49 | #[doc = "Write proxy for field `SILM`"] 50 | pub struct SILM_W<'a> { 51 | w: &'a mut W, 52 | } 53 | impl<'a> SILM_W<'a> { 54 | #[doc = r"Writes `variant` to the field"] 55 | #[inline(always)] 56 | pub fn variant(self, variant: SILM_A) -> &'a mut W { 57 | { 58 | self.bit(variant.into()) 59 | } 60 | } 61 | #[doc = "Normal operation"] 62 | #[inline(always)] 63 | pub fn normal(self) -> &'a mut W { 64 | self.variant(SILM_A::NORMAL) 65 | } 66 | #[doc = "Silent Mode"] 67 | #[inline(always)] 68 | pub fn silent(self) -> &'a mut W { 69 | self.variant(SILM_A::SILENT) 70 | } 71 | #[doc = r"Sets the field bit"] 72 | #[inline(always)] 73 | pub fn set_bit(self) -> &'a mut W { 74 | self.bit(true) 75 | } 76 | #[doc = r"Clears the field bit"] 77 | #[inline(always)] 78 | pub fn clear_bit(self) -> &'a mut W { 79 | self.bit(false) 80 | } 81 | #[doc = r"Writes raw bits to the field"] 82 | #[inline(always)] 83 | pub fn bit(self, value: bool) -> &'a mut W { 84 | self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); 85 | self.w 86 | } 87 | } 88 | #[doc = "LBKM\n\nValue on reset: 0"] 89 | #[derive(Clone, Copy, Debug, PartialEq)] 90 | pub enum LBKM_A { 91 | #[doc = "0: Loop Back Mode disabled"] 92 | DISABLED = 0, 93 | #[doc = "1: Loop Back Mode enabled"] 94 | ENABLED = 1, 95 | } 96 | impl From for bool { 97 | #[inline(always)] 98 | fn from(variant: LBKM_A) -> Self { 99 | variant as u8 != 0 100 | } 101 | } 102 | #[doc = "Reader of field `LBKM`"] 103 | pub type LBKM_R = crate::R; 104 | impl LBKM_R { 105 | #[doc = r"Get enumerated values variant"] 106 | #[inline(always)] 107 | pub fn variant(&self) -> LBKM_A { 108 | match self.bits { 109 | false => LBKM_A::DISABLED, 110 | true => LBKM_A::ENABLED, 111 | } 112 | } 113 | #[doc = "Checks if the value of the field is `DISABLED`"] 114 | #[inline(always)] 115 | pub fn is_disabled(&self) -> bool { 116 | *self == LBKM_A::DISABLED 117 | } 118 | #[doc = "Checks if the value of the field is `ENABLED`"] 119 | #[inline(always)] 120 | pub fn is_enabled(&self) -> bool { 121 | *self == LBKM_A::ENABLED 122 | } 123 | } 124 | #[doc = "Write proxy for field `LBKM`"] 125 | pub struct LBKM_W<'a> { 126 | w: &'a mut W, 127 | } 128 | impl<'a> LBKM_W<'a> { 129 | #[doc = r"Writes `variant` to the field"] 130 | #[inline(always)] 131 | pub fn variant(self, variant: LBKM_A) -> &'a mut W { 132 | { 133 | self.bit(variant.into()) 134 | } 135 | } 136 | #[doc = "Loop Back Mode disabled"] 137 | #[inline(always)] 138 | pub fn disabled(self) -> &'a mut W { 139 | self.variant(LBKM_A::DISABLED) 140 | } 141 | #[doc = "Loop Back Mode enabled"] 142 | #[inline(always)] 143 | pub fn enabled(self) -> &'a mut W { 144 | self.variant(LBKM_A::ENABLED) 145 | } 146 | #[doc = r"Sets the field bit"] 147 | #[inline(always)] 148 | pub fn set_bit(self) -> &'a mut W { 149 | self.bit(true) 150 | } 151 | #[doc = r"Clears the field bit"] 152 | #[inline(always)] 153 | pub fn clear_bit(self) -> &'a mut W { 154 | self.bit(false) 155 | } 156 | #[doc = r"Writes raw bits to the field"] 157 | #[inline(always)] 158 | pub fn bit(self, value: bool) -> &'a mut W { 159 | self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); 160 | self.w 161 | } 162 | } 163 | #[doc = "Reader of field `SJW`"] 164 | pub type SJW_R = crate::R; 165 | #[doc = "Write proxy for field `SJW`"] 166 | pub struct SJW_W<'a> { 167 | w: &'a mut W, 168 | } 169 | impl<'a> SJW_W<'a> { 170 | #[doc = r"Writes raw bits to the field"] 171 | #[inline(always)] 172 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 173 | self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24); 174 | self.w 175 | } 176 | } 177 | #[doc = "Reader of field `TS2`"] 178 | pub type TS2_R = crate::R; 179 | #[doc = "Write proxy for field `TS2`"] 180 | pub struct TS2_W<'a> { 181 | w: &'a mut W, 182 | } 183 | impl<'a> TS2_W<'a> { 184 | #[doc = r"Writes raw bits to the field"] 185 | #[inline(always)] 186 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 187 | self.w.bits = (self.w.bits & !(0x07 << 20)) | (((value as u32) & 0x07) << 20); 188 | self.w 189 | } 190 | } 191 | #[doc = "Reader of field `TS1`"] 192 | pub type TS1_R = crate::R; 193 | #[doc = "Write proxy for field `TS1`"] 194 | pub struct TS1_W<'a> { 195 | w: &'a mut W, 196 | } 197 | impl<'a> TS1_W<'a> { 198 | #[doc = r"Writes raw bits to the field"] 199 | #[inline(always)] 200 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 201 | self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); 202 | self.w 203 | } 204 | } 205 | #[doc = "Reader of field `BRP`"] 206 | pub type BRP_R = crate::R; 207 | #[doc = "Write proxy for field `BRP`"] 208 | pub struct BRP_W<'a> { 209 | w: &'a mut W, 210 | } 211 | impl<'a> BRP_W<'a> { 212 | #[doc = r"Writes raw bits to the field"] 213 | #[inline(always)] 214 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 215 | self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff); 216 | self.w 217 | } 218 | } 219 | impl R { 220 | #[doc = "Bit 31 - SILM"] 221 | #[inline(always)] 222 | pub fn silm(&self) -> SILM_R { 223 | SILM_R::new(((self.bits >> 31) & 0x01) != 0) 224 | } 225 | #[doc = "Bit 30 - LBKM"] 226 | #[inline(always)] 227 | pub fn lbkm(&self) -> LBKM_R { 228 | LBKM_R::new(((self.bits >> 30) & 0x01) != 0) 229 | } 230 | #[doc = "Bits 24:25 - SJW"] 231 | #[inline(always)] 232 | pub fn sjw(&self) -> SJW_R { 233 | SJW_R::new(((self.bits >> 24) & 0x03) as u8) 234 | } 235 | #[doc = "Bits 20:22 - TS2"] 236 | #[inline(always)] 237 | pub fn ts2(&self) -> TS2_R { 238 | TS2_R::new(((self.bits >> 20) & 0x07) as u8) 239 | } 240 | #[doc = "Bits 16:19 - TS1"] 241 | #[inline(always)] 242 | pub fn ts1(&self) -> TS1_R { 243 | TS1_R::new(((self.bits >> 16) & 0x0f) as u8) 244 | } 245 | #[doc = "Bits 0:9 - BRP"] 246 | #[inline(always)] 247 | pub fn brp(&self) -> BRP_R { 248 | BRP_R::new((self.bits & 0x03ff) as u16) 249 | } 250 | } 251 | impl W { 252 | #[doc = "Bit 31 - SILM"] 253 | #[inline(always)] 254 | pub fn silm(&mut self) -> SILM_W { 255 | SILM_W { w: self } 256 | } 257 | #[doc = "Bit 30 - LBKM"] 258 | #[inline(always)] 259 | pub fn lbkm(&mut self) -> LBKM_W { 260 | LBKM_W { w: self } 261 | } 262 | #[doc = "Bits 24:25 - SJW"] 263 | #[inline(always)] 264 | pub fn sjw(&mut self) -> SJW_W { 265 | SJW_W { w: self } 266 | } 267 | #[doc = "Bits 20:22 - TS2"] 268 | #[inline(always)] 269 | pub fn ts2(&mut self) -> TS2_W { 270 | TS2_W { w: self } 271 | } 272 | #[doc = "Bits 16:19 - TS1"] 273 | #[inline(always)] 274 | pub fn ts1(&mut self) -> TS1_W { 275 | TS1_W { w: self } 276 | } 277 | #[doc = "Bits 0:9 - BRP"] 278 | #[inline(always)] 279 | pub fn brp(&mut self) -> BRP_W { 280 | BRP_W { w: self } 281 | } 282 | } 283 | -------------------------------------------------------------------------------- /src/pac/can/esr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register ESR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register ESR"] 4 | pub type W = crate::W; 5 | #[doc = "Register ESR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::ESR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `REC`"] 14 | pub type REC_R = crate::R; 15 | #[doc = "Reader of field `TEC`"] 16 | pub type TEC_R = crate::R; 17 | #[doc = "LEC\n\nValue on reset: 0"] 18 | #[derive(Clone, Copy, Debug, PartialEq)] 19 | #[repr(u8)] 20 | pub enum LEC_A { 21 | #[doc = "0: No Error"] 22 | NOERROR = 0, 23 | #[doc = "1: Stuff Error"] 24 | STUFF = 1, 25 | #[doc = "2: Form Error"] 26 | FORM = 2, 27 | #[doc = "3: Acknowledgment Error"] 28 | ACK = 3, 29 | #[doc = "4: Bit recessive Error"] 30 | BITRECESSIVE = 4, 31 | #[doc = "5: Bit dominant Error"] 32 | BITDOMINANT = 5, 33 | #[doc = "6: CRC Error"] 34 | CRC = 6, 35 | #[doc = "7: Set by software"] 36 | CUSTOM = 7, 37 | } 38 | impl From for u8 { 39 | #[inline(always)] 40 | fn from(variant: LEC_A) -> Self { 41 | variant as _ 42 | } 43 | } 44 | #[doc = "Reader of field `LEC`"] 45 | pub type LEC_R = crate::R; 46 | impl LEC_R { 47 | #[doc = r"Get enumerated values variant"] 48 | #[inline(always)] 49 | pub fn variant(&self) -> LEC_A { 50 | match self.bits { 51 | 0 => LEC_A::NOERROR, 52 | 1 => LEC_A::STUFF, 53 | 2 => LEC_A::FORM, 54 | 3 => LEC_A::ACK, 55 | 4 => LEC_A::BITRECESSIVE, 56 | 5 => LEC_A::BITDOMINANT, 57 | 6 => LEC_A::CRC, 58 | 7 => LEC_A::CUSTOM, 59 | _ => unreachable!(), 60 | } 61 | } 62 | #[doc = "Checks if the value of the field is `NOERROR`"] 63 | #[inline(always)] 64 | pub fn is_no_error(&self) -> bool { 65 | *self == LEC_A::NOERROR 66 | } 67 | #[doc = "Checks if the value of the field is `STUFF`"] 68 | #[inline(always)] 69 | pub fn is_stuff(&self) -> bool { 70 | *self == LEC_A::STUFF 71 | } 72 | #[doc = "Checks if the value of the field is `FORM`"] 73 | #[inline(always)] 74 | pub fn is_form(&self) -> bool { 75 | *self == LEC_A::FORM 76 | } 77 | #[doc = "Checks if the value of the field is `ACK`"] 78 | #[inline(always)] 79 | pub fn is_ack(&self) -> bool { 80 | *self == LEC_A::ACK 81 | } 82 | #[doc = "Checks if the value of the field is `BITRECESSIVE`"] 83 | #[inline(always)] 84 | pub fn is_bit_recessive(&self) -> bool { 85 | *self == LEC_A::BITRECESSIVE 86 | } 87 | #[doc = "Checks if the value of the field is `BITDOMINANT`"] 88 | #[inline(always)] 89 | pub fn is_bit_dominant(&self) -> bool { 90 | *self == LEC_A::BITDOMINANT 91 | } 92 | #[doc = "Checks if the value of the field is `CRC`"] 93 | #[inline(always)] 94 | pub fn is_crc(&self) -> bool { 95 | *self == LEC_A::CRC 96 | } 97 | #[doc = "Checks if the value of the field is `CUSTOM`"] 98 | #[inline(always)] 99 | pub fn is_custom(&self) -> bool { 100 | *self == LEC_A::CUSTOM 101 | } 102 | } 103 | #[doc = "Write proxy for field `LEC`"] 104 | pub struct LEC_W<'a> { 105 | w: &'a mut W, 106 | } 107 | impl<'a> LEC_W<'a> { 108 | #[doc = r"Writes `variant` to the field"] 109 | #[inline(always)] 110 | pub fn variant(self, variant: LEC_A) -> &'a mut W { 111 | { 112 | self.bits(variant.into()) 113 | } 114 | } 115 | #[doc = "No Error"] 116 | #[inline(always)] 117 | pub fn no_error(self) -> &'a mut W { 118 | self.variant(LEC_A::NOERROR) 119 | } 120 | #[doc = "Stuff Error"] 121 | #[inline(always)] 122 | pub fn stuff(self) -> &'a mut W { 123 | self.variant(LEC_A::STUFF) 124 | } 125 | #[doc = "Form Error"] 126 | #[inline(always)] 127 | pub fn form(self) -> &'a mut W { 128 | self.variant(LEC_A::FORM) 129 | } 130 | #[doc = "Acknowledgment Error"] 131 | #[inline(always)] 132 | pub fn ack(self) -> &'a mut W { 133 | self.variant(LEC_A::ACK) 134 | } 135 | #[doc = "Bit recessive Error"] 136 | #[inline(always)] 137 | pub fn bit_recessive(self) -> &'a mut W { 138 | self.variant(LEC_A::BITRECESSIVE) 139 | } 140 | #[doc = "Bit dominant Error"] 141 | #[inline(always)] 142 | pub fn bit_dominant(self) -> &'a mut W { 143 | self.variant(LEC_A::BITDOMINANT) 144 | } 145 | #[doc = "CRC Error"] 146 | #[inline(always)] 147 | pub fn crc(self) -> &'a mut W { 148 | self.variant(LEC_A::CRC) 149 | } 150 | #[doc = "Set by software"] 151 | #[inline(always)] 152 | pub fn custom(self) -> &'a mut W { 153 | self.variant(LEC_A::CUSTOM) 154 | } 155 | #[doc = r"Writes raw bits to the field"] 156 | #[inline(always)] 157 | pub fn bits(self, value: u8) -> &'a mut W { 158 | self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4); 159 | self.w 160 | } 161 | } 162 | #[doc = "Reader of field `BOFF`"] 163 | pub type BOFF_R = crate::R; 164 | #[doc = "Reader of field `EPVF`"] 165 | pub type EPVF_R = crate::R; 166 | #[doc = "Reader of field `EWGF`"] 167 | pub type EWGF_R = crate::R; 168 | impl R { 169 | #[doc = "Bits 24:31 - REC"] 170 | #[inline(always)] 171 | pub fn rec(&self) -> REC_R { 172 | REC_R::new(((self.bits >> 24) & 0xff) as u8) 173 | } 174 | #[doc = "Bits 16:23 - TEC"] 175 | #[inline(always)] 176 | pub fn tec(&self) -> TEC_R { 177 | TEC_R::new(((self.bits >> 16) & 0xff) as u8) 178 | } 179 | #[doc = "Bits 4:6 - LEC"] 180 | #[inline(always)] 181 | pub fn lec(&self) -> LEC_R { 182 | LEC_R::new(((self.bits >> 4) & 0x07) as u8) 183 | } 184 | #[doc = "Bit 2 - BOFF"] 185 | #[inline(always)] 186 | pub fn boff(&self) -> BOFF_R { 187 | BOFF_R::new(((self.bits >> 2) & 0x01) != 0) 188 | } 189 | #[doc = "Bit 1 - EPVF"] 190 | #[inline(always)] 191 | pub fn epvf(&self) -> EPVF_R { 192 | EPVF_R::new(((self.bits >> 1) & 0x01) != 0) 193 | } 194 | #[doc = "Bit 0 - EWGF"] 195 | #[inline(always)] 196 | pub fn ewgf(&self) -> EWGF_R { 197 | EWGF_R::new((self.bits & 0x01) != 0) 198 | } 199 | } 200 | impl W { 201 | #[doc = "Bits 4:6 - LEC"] 202 | #[inline(always)] 203 | pub fn lec(&mut self) -> LEC_W { 204 | LEC_W { w: self } 205 | } 206 | } 207 | -------------------------------------------------------------------------------- /src/pac/can/fa1r.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register FA1R"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register FA1R"] 4 | pub type W = crate::W; 5 | #[doc = "Register FA1R `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::FA1R { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `FACT0`"] 14 | pub type FACT0_R = crate::R; 15 | #[doc = "Write proxy for field `FACT0`"] 16 | pub struct FACT0_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> FACT0_W<'a> { 20 | #[doc = r"Sets the field bit"] 21 | #[inline(always)] 22 | pub fn set_bit(self) -> &'a mut W { 23 | self.bit(true) 24 | } 25 | #[doc = r"Clears the field bit"] 26 | #[inline(always)] 27 | pub fn clear_bit(self) -> &'a mut W { 28 | self.bit(false) 29 | } 30 | #[doc = r"Writes raw bits to the field"] 31 | #[inline(always)] 32 | pub fn bit(self, value: bool) -> &'a mut W { 33 | self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); 34 | self.w 35 | } 36 | } 37 | #[doc = "Reader of field `FACT1`"] 38 | pub type FACT1_R = crate::R; 39 | #[doc = "Write proxy for field `FACT1`"] 40 | pub struct FACT1_W<'a> { 41 | w: &'a mut W, 42 | } 43 | impl<'a> FACT1_W<'a> { 44 | #[doc = r"Sets the field bit"] 45 | #[inline(always)] 46 | pub fn set_bit(self) -> &'a mut W { 47 | self.bit(true) 48 | } 49 | #[doc = r"Clears the field bit"] 50 | #[inline(always)] 51 | pub fn clear_bit(self) -> &'a mut W { 52 | self.bit(false) 53 | } 54 | #[doc = r"Writes raw bits to the field"] 55 | #[inline(always)] 56 | pub fn bit(self, value: bool) -> &'a mut W { 57 | self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); 58 | self.w 59 | } 60 | } 61 | #[doc = "Reader of field `FACT2`"] 62 | pub type FACT2_R = crate::R; 63 | #[doc = "Write proxy for field `FACT2`"] 64 | pub struct FACT2_W<'a> { 65 | w: &'a mut W, 66 | } 67 | impl<'a> FACT2_W<'a> { 68 | #[doc = r"Sets the field bit"] 69 | #[inline(always)] 70 | pub fn set_bit(self) -> &'a mut W { 71 | self.bit(true) 72 | } 73 | #[doc = r"Clears the field bit"] 74 | #[inline(always)] 75 | pub fn clear_bit(self) -> &'a mut W { 76 | self.bit(false) 77 | } 78 | #[doc = r"Writes raw bits to the field"] 79 | #[inline(always)] 80 | pub fn bit(self, value: bool) -> &'a mut W { 81 | self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); 82 | self.w 83 | } 84 | } 85 | #[doc = "Reader of field `FACT3`"] 86 | pub type FACT3_R = crate::R; 87 | #[doc = "Write proxy for field `FACT3`"] 88 | pub struct FACT3_W<'a> { 89 | w: &'a mut W, 90 | } 91 | impl<'a> FACT3_W<'a> { 92 | #[doc = r"Sets the field bit"] 93 | #[inline(always)] 94 | pub fn set_bit(self) -> &'a mut W { 95 | self.bit(true) 96 | } 97 | #[doc = r"Clears the field bit"] 98 | #[inline(always)] 99 | pub fn clear_bit(self) -> &'a mut W { 100 | self.bit(false) 101 | } 102 | #[doc = r"Writes raw bits to the field"] 103 | #[inline(always)] 104 | pub fn bit(self, value: bool) -> &'a mut W { 105 | self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); 106 | self.w 107 | } 108 | } 109 | #[doc = "Reader of field `FACT4`"] 110 | pub type FACT4_R = crate::R; 111 | #[doc = "Write proxy for field `FACT4`"] 112 | pub struct FACT4_W<'a> { 113 | w: &'a mut W, 114 | } 115 | impl<'a> FACT4_W<'a> { 116 | #[doc = r"Sets the field bit"] 117 | #[inline(always)] 118 | pub fn set_bit(self) -> &'a mut W { 119 | self.bit(true) 120 | } 121 | #[doc = r"Clears the field bit"] 122 | #[inline(always)] 123 | pub fn clear_bit(self) -> &'a mut W { 124 | self.bit(false) 125 | } 126 | #[doc = r"Writes raw bits to the field"] 127 | #[inline(always)] 128 | pub fn bit(self, value: bool) -> &'a mut W { 129 | self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); 130 | self.w 131 | } 132 | } 133 | #[doc = "Reader of field `FACT5`"] 134 | pub type FACT5_R = crate::R; 135 | #[doc = "Write proxy for field `FACT5`"] 136 | pub struct FACT5_W<'a> { 137 | w: &'a mut W, 138 | } 139 | impl<'a> FACT5_W<'a> { 140 | #[doc = r"Sets the field bit"] 141 | #[inline(always)] 142 | pub fn set_bit(self) -> &'a mut W { 143 | self.bit(true) 144 | } 145 | #[doc = r"Clears the field bit"] 146 | #[inline(always)] 147 | pub fn clear_bit(self) -> &'a mut W { 148 | self.bit(false) 149 | } 150 | #[doc = r"Writes raw bits to the field"] 151 | #[inline(always)] 152 | pub fn bit(self, value: bool) -> &'a mut W { 153 | self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); 154 | self.w 155 | } 156 | } 157 | #[doc = "Reader of field `FACT6`"] 158 | pub type FACT6_R = crate::R; 159 | #[doc = "Write proxy for field `FACT6`"] 160 | pub struct FACT6_W<'a> { 161 | w: &'a mut W, 162 | } 163 | impl<'a> FACT6_W<'a> { 164 | #[doc = r"Sets the field bit"] 165 | #[inline(always)] 166 | pub fn set_bit(self) -> &'a mut W { 167 | self.bit(true) 168 | } 169 | #[doc = r"Clears the field bit"] 170 | #[inline(always)] 171 | pub fn clear_bit(self) -> &'a mut W { 172 | self.bit(false) 173 | } 174 | #[doc = r"Writes raw bits to the field"] 175 | #[inline(always)] 176 | pub fn bit(self, value: bool) -> &'a mut W { 177 | self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); 178 | self.w 179 | } 180 | } 181 | #[doc = "Reader of field `FACT7`"] 182 | pub type FACT7_R = crate::R; 183 | #[doc = "Write proxy for field `FACT7`"] 184 | pub struct FACT7_W<'a> { 185 | w: &'a mut W, 186 | } 187 | impl<'a> FACT7_W<'a> { 188 | #[doc = r"Sets the field bit"] 189 | #[inline(always)] 190 | pub fn set_bit(self) -> &'a mut W { 191 | self.bit(true) 192 | } 193 | #[doc = r"Clears the field bit"] 194 | #[inline(always)] 195 | pub fn clear_bit(self) -> &'a mut W { 196 | self.bit(false) 197 | } 198 | #[doc = r"Writes raw bits to the field"] 199 | #[inline(always)] 200 | pub fn bit(self, value: bool) -> &'a mut W { 201 | self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); 202 | self.w 203 | } 204 | } 205 | #[doc = "Reader of field `FACT8`"] 206 | pub type FACT8_R = crate::R; 207 | #[doc = "Write proxy for field `FACT8`"] 208 | pub struct FACT8_W<'a> { 209 | w: &'a mut W, 210 | } 211 | impl<'a> FACT8_W<'a> { 212 | #[doc = r"Sets the field bit"] 213 | #[inline(always)] 214 | pub fn set_bit(self) -> &'a mut W { 215 | self.bit(true) 216 | } 217 | #[doc = r"Clears the field bit"] 218 | #[inline(always)] 219 | pub fn clear_bit(self) -> &'a mut W { 220 | self.bit(false) 221 | } 222 | #[doc = r"Writes raw bits to the field"] 223 | #[inline(always)] 224 | pub fn bit(self, value: bool) -> &'a mut W { 225 | self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); 226 | self.w 227 | } 228 | } 229 | #[doc = "Reader of field `FACT9`"] 230 | pub type FACT9_R = crate::R; 231 | #[doc = "Write proxy for field `FACT9`"] 232 | pub struct FACT9_W<'a> { 233 | w: &'a mut W, 234 | } 235 | impl<'a> FACT9_W<'a> { 236 | #[doc = r"Sets the field bit"] 237 | #[inline(always)] 238 | pub fn set_bit(self) -> &'a mut W { 239 | self.bit(true) 240 | } 241 | #[doc = r"Clears the field bit"] 242 | #[inline(always)] 243 | pub fn clear_bit(self) -> &'a mut W { 244 | self.bit(false) 245 | } 246 | #[doc = r"Writes raw bits to the field"] 247 | #[inline(always)] 248 | pub fn bit(self, value: bool) -> &'a mut W { 249 | self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); 250 | self.w 251 | } 252 | } 253 | #[doc = "Reader of field `FACT10`"] 254 | pub type FACT10_R = crate::R; 255 | #[doc = "Write proxy for field `FACT10`"] 256 | pub struct FACT10_W<'a> { 257 | w: &'a mut W, 258 | } 259 | impl<'a> FACT10_W<'a> { 260 | #[doc = r"Sets the field bit"] 261 | #[inline(always)] 262 | pub fn set_bit(self) -> &'a mut W { 263 | self.bit(true) 264 | } 265 | #[doc = r"Clears the field bit"] 266 | #[inline(always)] 267 | pub fn clear_bit(self) -> &'a mut W { 268 | self.bit(false) 269 | } 270 | #[doc = r"Writes raw bits to the field"] 271 | #[inline(always)] 272 | pub fn bit(self, value: bool) -> &'a mut W { 273 | self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); 274 | self.w 275 | } 276 | } 277 | #[doc = "Reader of field `FACT11`"] 278 | pub type FACT11_R = crate::R; 279 | #[doc = "Write proxy for field `FACT11`"] 280 | pub struct FACT11_W<'a> { 281 | w: &'a mut W, 282 | } 283 | impl<'a> FACT11_W<'a> { 284 | #[doc = r"Sets the field bit"] 285 | #[inline(always)] 286 | pub fn set_bit(self) -> &'a mut W { 287 | self.bit(true) 288 | } 289 | #[doc = r"Clears the field bit"] 290 | #[inline(always)] 291 | pub fn clear_bit(self) -> &'a mut W { 292 | self.bit(false) 293 | } 294 | #[doc = r"Writes raw bits to the field"] 295 | #[inline(always)] 296 | pub fn bit(self, value: bool) -> &'a mut W { 297 | self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); 298 | self.w 299 | } 300 | } 301 | #[doc = "Reader of field `FACT12`"] 302 | pub type FACT12_R = crate::R; 303 | #[doc = "Write proxy for field `FACT12`"] 304 | pub struct FACT12_W<'a> { 305 | w: &'a mut W, 306 | } 307 | impl<'a> FACT12_W<'a> { 308 | #[doc = r"Sets the field bit"] 309 | #[inline(always)] 310 | pub fn set_bit(self) -> &'a mut W { 311 | self.bit(true) 312 | } 313 | #[doc = r"Clears the field bit"] 314 | #[inline(always)] 315 | pub fn clear_bit(self) -> &'a mut W { 316 | self.bit(false) 317 | } 318 | #[doc = r"Writes raw bits to the field"] 319 | #[inline(always)] 320 | pub fn bit(self, value: bool) -> &'a mut W { 321 | self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); 322 | self.w 323 | } 324 | } 325 | #[doc = "Reader of field `FACT13`"] 326 | pub type FACT13_R = crate::R; 327 | #[doc = "Write proxy for field `FACT13`"] 328 | pub struct FACT13_W<'a> { 329 | w: &'a mut W, 330 | } 331 | impl<'a> FACT13_W<'a> { 332 | #[doc = r"Sets the field bit"] 333 | #[inline(always)] 334 | pub fn set_bit(self) -> &'a mut W { 335 | self.bit(true) 336 | } 337 | #[doc = r"Clears the field bit"] 338 | #[inline(always)] 339 | pub fn clear_bit(self) -> &'a mut W { 340 | self.bit(false) 341 | } 342 | #[doc = r"Writes raw bits to the field"] 343 | #[inline(always)] 344 | pub fn bit(self, value: bool) -> &'a mut W { 345 | self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); 346 | self.w 347 | } 348 | } 349 | impl R { 350 | #[doc = "Bit 0 - Filter active"] 351 | #[inline(always)] 352 | pub fn fact0(&self) -> FACT0_R { 353 | FACT0_R::new((self.bits & 0x01) != 0) 354 | } 355 | #[doc = "Bit 1 - Filter active"] 356 | #[inline(always)] 357 | pub fn fact1(&self) -> FACT1_R { 358 | FACT1_R::new(((self.bits >> 1) & 0x01) != 0) 359 | } 360 | #[doc = "Bit 2 - Filter active"] 361 | #[inline(always)] 362 | pub fn fact2(&self) -> FACT2_R { 363 | FACT2_R::new(((self.bits >> 2) & 0x01) != 0) 364 | } 365 | #[doc = "Bit 3 - Filter active"] 366 | #[inline(always)] 367 | pub fn fact3(&self) -> FACT3_R { 368 | FACT3_R::new(((self.bits >> 3) & 0x01) != 0) 369 | } 370 | #[doc = "Bit 4 - Filter active"] 371 | #[inline(always)] 372 | pub fn fact4(&self) -> FACT4_R { 373 | FACT4_R::new(((self.bits >> 4) & 0x01) != 0) 374 | } 375 | #[doc = "Bit 5 - Filter active"] 376 | #[inline(always)] 377 | pub fn fact5(&self) -> FACT5_R { 378 | FACT5_R::new(((self.bits >> 5) & 0x01) != 0) 379 | } 380 | #[doc = "Bit 6 - Filter active"] 381 | #[inline(always)] 382 | pub fn fact6(&self) -> FACT6_R { 383 | FACT6_R::new(((self.bits >> 6) & 0x01) != 0) 384 | } 385 | #[doc = "Bit 7 - Filter active"] 386 | #[inline(always)] 387 | pub fn fact7(&self) -> FACT7_R { 388 | FACT7_R::new(((self.bits >> 7) & 0x01) != 0) 389 | } 390 | #[doc = "Bit 8 - Filter active"] 391 | #[inline(always)] 392 | pub fn fact8(&self) -> FACT8_R { 393 | FACT8_R::new(((self.bits >> 8) & 0x01) != 0) 394 | } 395 | #[doc = "Bit 9 - Filter active"] 396 | #[inline(always)] 397 | pub fn fact9(&self) -> FACT9_R { 398 | FACT9_R::new(((self.bits >> 9) & 0x01) != 0) 399 | } 400 | #[doc = "Bit 10 - Filter active"] 401 | #[inline(always)] 402 | pub fn fact10(&self) -> FACT10_R { 403 | FACT10_R::new(((self.bits >> 10) & 0x01) != 0) 404 | } 405 | #[doc = "Bit 11 - Filter active"] 406 | #[inline(always)] 407 | pub fn fact11(&self) -> FACT11_R { 408 | FACT11_R::new(((self.bits >> 11) & 0x01) != 0) 409 | } 410 | #[doc = "Bit 12 - Filter active"] 411 | #[inline(always)] 412 | pub fn fact12(&self) -> FACT12_R { 413 | FACT12_R::new(((self.bits >> 12) & 0x01) != 0) 414 | } 415 | #[doc = "Bit 13 - Filter active"] 416 | #[inline(always)] 417 | pub fn fact13(&self) -> FACT13_R { 418 | FACT13_R::new(((self.bits >> 13) & 0x01) != 0) 419 | } 420 | } 421 | impl W { 422 | #[doc = "Bit 0 - Filter active"] 423 | #[inline(always)] 424 | pub fn fact0(&mut self) -> FACT0_W { 425 | FACT0_W { w: self } 426 | } 427 | #[doc = "Bit 1 - Filter active"] 428 | #[inline(always)] 429 | pub fn fact1(&mut self) -> FACT1_W { 430 | FACT1_W { w: self } 431 | } 432 | #[doc = "Bit 2 - Filter active"] 433 | #[inline(always)] 434 | pub fn fact2(&mut self) -> FACT2_W { 435 | FACT2_W { w: self } 436 | } 437 | #[doc = "Bit 3 - Filter active"] 438 | #[inline(always)] 439 | pub fn fact3(&mut self) -> FACT3_W { 440 | FACT3_W { w: self } 441 | } 442 | #[doc = "Bit 4 - Filter active"] 443 | #[inline(always)] 444 | pub fn fact4(&mut self) -> FACT4_W { 445 | FACT4_W { w: self } 446 | } 447 | #[doc = "Bit 5 - Filter active"] 448 | #[inline(always)] 449 | pub fn fact5(&mut self) -> FACT5_W { 450 | FACT5_W { w: self } 451 | } 452 | #[doc = "Bit 6 - Filter active"] 453 | #[inline(always)] 454 | pub fn fact6(&mut self) -> FACT6_W { 455 | FACT6_W { w: self } 456 | } 457 | #[doc = "Bit 7 - Filter active"] 458 | #[inline(always)] 459 | pub fn fact7(&mut self) -> FACT7_W { 460 | FACT7_W { w: self } 461 | } 462 | #[doc = "Bit 8 - Filter active"] 463 | #[inline(always)] 464 | pub fn fact8(&mut self) -> FACT8_W { 465 | FACT8_W { w: self } 466 | } 467 | #[doc = "Bit 9 - Filter active"] 468 | #[inline(always)] 469 | pub fn fact9(&mut self) -> FACT9_W { 470 | FACT9_W { w: self } 471 | } 472 | #[doc = "Bit 10 - Filter active"] 473 | #[inline(always)] 474 | pub fn fact10(&mut self) -> FACT10_W { 475 | FACT10_W { w: self } 476 | } 477 | #[doc = "Bit 11 - Filter active"] 478 | #[inline(always)] 479 | pub fn fact11(&mut self) -> FACT11_W { 480 | FACT11_W { w: self } 481 | } 482 | #[doc = "Bit 12 - Filter active"] 483 | #[inline(always)] 484 | pub fn fact12(&mut self) -> FACT12_W { 485 | FACT12_W { w: self } 486 | } 487 | #[doc = "Bit 13 - Filter active"] 488 | #[inline(always)] 489 | pub fn fact13(&mut self) -> FACT13_W { 490 | FACT13_W { w: self } 491 | } 492 | } 493 | -------------------------------------------------------------------------------- /src/pac/can/fb.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Filter bank 0 register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr1](fr1) module"] 2 | pub type FR1 = crate::Reg; 3 | #[allow(missing_docs)] 4 | #[doc(hidden)] 5 | pub struct _FR1; 6 | #[doc = "`read()` method returns [fr1::R](fr1::R) reader structure"] 7 | impl crate::Readable for FR1 {} 8 | #[doc = "`write(|w| ..)` method takes [fr1::W](fr1::W) writer structure"] 9 | impl crate::Writable for FR1 {} 10 | #[doc = "Filter bank 0 register 1"] 11 | pub mod fr1; 12 | #[doc = "Filter bank 0 register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr2](fr2) module"] 13 | pub type FR2 = crate::Reg; 14 | #[allow(missing_docs)] 15 | #[doc(hidden)] 16 | pub struct _FR2; 17 | #[doc = "`read()` method returns [fr2::R](fr2::R) reader structure"] 18 | impl crate::Readable for FR2 {} 19 | #[doc = "`write(|w| ..)` method takes [fr2::W](fr2::W) writer structure"] 20 | impl crate::Writable for FR2 {} 21 | #[doc = "Filter bank 0 register 2"] 22 | pub mod fr2; 23 | -------------------------------------------------------------------------------- /src/pac/can/fb/fr1.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register FR1"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register FR1"] 4 | pub type W = crate::W; 5 | #[doc = "Register FR1 `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::FR1 { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `FB`"] 14 | pub type FB_R = crate::R; 15 | #[doc = "Write proxy for field `FB`"] 16 | pub struct FB_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> FB_W<'a> { 20 | #[doc = r"Writes raw bits to the field"] 21 | #[inline(always)] 22 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 23 | self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); 24 | self.w 25 | } 26 | } 27 | impl R { 28 | #[doc = "Bits 0:31 - Filter bits"] 29 | #[inline(always)] 30 | pub fn fb(&self) -> FB_R { 31 | FB_R::new((self.bits & 0xffff_ffff) as u32) 32 | } 33 | } 34 | impl W { 35 | #[doc = "Bits 0:31 - Filter bits"] 36 | #[inline(always)] 37 | pub fn fb(&mut self) -> FB_W { 38 | FB_W { w: self } 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /src/pac/can/fb/fr2.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register FR2"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register FR2"] 4 | pub type W = crate::W; 5 | #[doc = "Register FR2 `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::FR2 { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `FB`"] 14 | pub type FB_R = crate::R; 15 | #[doc = "Write proxy for field `FB`"] 16 | pub struct FB_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> FB_W<'a> { 20 | #[doc = r"Writes raw bits to the field"] 21 | #[inline(always)] 22 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 23 | self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); 24 | self.w 25 | } 26 | } 27 | impl R { 28 | #[doc = "Bits 0:31 - Filter bits"] 29 | #[inline(always)] 30 | pub fn fb(&self) -> FB_R { 31 | FB_R::new((self.bits & 0xffff_ffff) as u32) 32 | } 33 | } 34 | impl W { 35 | #[doc = "Bits 0:31 - Filter bits"] 36 | #[inline(always)] 37 | pub fn fb(&mut self) -> FB_W { 38 | FB_W { w: self } 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /src/pac/can/fm1r.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register FM1R"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register FM1R"] 4 | pub type W = crate::W; 5 | #[doc = "Register FM1R `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::FM1R { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `FBM0`"] 14 | pub type FBM0_R = crate::R; 15 | #[doc = "Write proxy for field `FBM0`"] 16 | pub struct FBM0_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> FBM0_W<'a> { 20 | #[doc = r"Sets the field bit"] 21 | #[inline(always)] 22 | pub fn set_bit(self) -> &'a mut W { 23 | self.bit(true) 24 | } 25 | #[doc = r"Clears the field bit"] 26 | #[inline(always)] 27 | pub fn clear_bit(self) -> &'a mut W { 28 | self.bit(false) 29 | } 30 | #[doc = r"Writes raw bits to the field"] 31 | #[inline(always)] 32 | pub fn bit(self, value: bool) -> &'a mut W { 33 | self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); 34 | self.w 35 | } 36 | } 37 | #[doc = "Reader of field `FBM1`"] 38 | pub type FBM1_R = crate::R; 39 | #[doc = "Write proxy for field `FBM1`"] 40 | pub struct FBM1_W<'a> { 41 | w: &'a mut W, 42 | } 43 | impl<'a> FBM1_W<'a> { 44 | #[doc = r"Sets the field bit"] 45 | #[inline(always)] 46 | pub fn set_bit(self) -> &'a mut W { 47 | self.bit(true) 48 | } 49 | #[doc = r"Clears the field bit"] 50 | #[inline(always)] 51 | pub fn clear_bit(self) -> &'a mut W { 52 | self.bit(false) 53 | } 54 | #[doc = r"Writes raw bits to the field"] 55 | #[inline(always)] 56 | pub fn bit(self, value: bool) -> &'a mut W { 57 | self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); 58 | self.w 59 | } 60 | } 61 | #[doc = "Reader of field `FBM2`"] 62 | pub type FBM2_R = crate::R; 63 | #[doc = "Write proxy for field `FBM2`"] 64 | pub struct FBM2_W<'a> { 65 | w: &'a mut W, 66 | } 67 | impl<'a> FBM2_W<'a> { 68 | #[doc = r"Sets the field bit"] 69 | #[inline(always)] 70 | pub fn set_bit(self) -> &'a mut W { 71 | self.bit(true) 72 | } 73 | #[doc = r"Clears the field bit"] 74 | #[inline(always)] 75 | pub fn clear_bit(self) -> &'a mut W { 76 | self.bit(false) 77 | } 78 | #[doc = r"Writes raw bits to the field"] 79 | #[inline(always)] 80 | pub fn bit(self, value: bool) -> &'a mut W { 81 | self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); 82 | self.w 83 | } 84 | } 85 | #[doc = "Reader of field `FBM3`"] 86 | pub type FBM3_R = crate::R; 87 | #[doc = "Write proxy for field `FBM3`"] 88 | pub struct FBM3_W<'a> { 89 | w: &'a mut W, 90 | } 91 | impl<'a> FBM3_W<'a> { 92 | #[doc = r"Sets the field bit"] 93 | #[inline(always)] 94 | pub fn set_bit(self) -> &'a mut W { 95 | self.bit(true) 96 | } 97 | #[doc = r"Clears the field bit"] 98 | #[inline(always)] 99 | pub fn clear_bit(self) -> &'a mut W { 100 | self.bit(false) 101 | } 102 | #[doc = r"Writes raw bits to the field"] 103 | #[inline(always)] 104 | pub fn bit(self, value: bool) -> &'a mut W { 105 | self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); 106 | self.w 107 | } 108 | } 109 | #[doc = "Reader of field `FBM4`"] 110 | pub type FBM4_R = crate::R; 111 | #[doc = "Write proxy for field `FBM4`"] 112 | pub struct FBM4_W<'a> { 113 | w: &'a mut W, 114 | } 115 | impl<'a> FBM4_W<'a> { 116 | #[doc = r"Sets the field bit"] 117 | #[inline(always)] 118 | pub fn set_bit(self) -> &'a mut W { 119 | self.bit(true) 120 | } 121 | #[doc = r"Clears the field bit"] 122 | #[inline(always)] 123 | pub fn clear_bit(self) -> &'a mut W { 124 | self.bit(false) 125 | } 126 | #[doc = r"Writes raw bits to the field"] 127 | #[inline(always)] 128 | pub fn bit(self, value: bool) -> &'a mut W { 129 | self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); 130 | self.w 131 | } 132 | } 133 | #[doc = "Reader of field `FBM5`"] 134 | pub type FBM5_R = crate::R; 135 | #[doc = "Write proxy for field `FBM5`"] 136 | pub struct FBM5_W<'a> { 137 | w: &'a mut W, 138 | } 139 | impl<'a> FBM5_W<'a> { 140 | #[doc = r"Sets the field bit"] 141 | #[inline(always)] 142 | pub fn set_bit(self) -> &'a mut W { 143 | self.bit(true) 144 | } 145 | #[doc = r"Clears the field bit"] 146 | #[inline(always)] 147 | pub fn clear_bit(self) -> &'a mut W { 148 | self.bit(false) 149 | } 150 | #[doc = r"Writes raw bits to the field"] 151 | #[inline(always)] 152 | pub fn bit(self, value: bool) -> &'a mut W { 153 | self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); 154 | self.w 155 | } 156 | } 157 | #[doc = "Reader of field `FBM6`"] 158 | pub type FBM6_R = crate::R; 159 | #[doc = "Write proxy for field `FBM6`"] 160 | pub struct FBM6_W<'a> { 161 | w: &'a mut W, 162 | } 163 | impl<'a> FBM6_W<'a> { 164 | #[doc = r"Sets the field bit"] 165 | #[inline(always)] 166 | pub fn set_bit(self) -> &'a mut W { 167 | self.bit(true) 168 | } 169 | #[doc = r"Clears the field bit"] 170 | #[inline(always)] 171 | pub fn clear_bit(self) -> &'a mut W { 172 | self.bit(false) 173 | } 174 | #[doc = r"Writes raw bits to the field"] 175 | #[inline(always)] 176 | pub fn bit(self, value: bool) -> &'a mut W { 177 | self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); 178 | self.w 179 | } 180 | } 181 | #[doc = "Reader of field `FBM7`"] 182 | pub type FBM7_R = crate::R; 183 | #[doc = "Write proxy for field `FBM7`"] 184 | pub struct FBM7_W<'a> { 185 | w: &'a mut W, 186 | } 187 | impl<'a> FBM7_W<'a> { 188 | #[doc = r"Sets the field bit"] 189 | #[inline(always)] 190 | pub fn set_bit(self) -> &'a mut W { 191 | self.bit(true) 192 | } 193 | #[doc = r"Clears the field bit"] 194 | #[inline(always)] 195 | pub fn clear_bit(self) -> &'a mut W { 196 | self.bit(false) 197 | } 198 | #[doc = r"Writes raw bits to the field"] 199 | #[inline(always)] 200 | pub fn bit(self, value: bool) -> &'a mut W { 201 | self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); 202 | self.w 203 | } 204 | } 205 | #[doc = "Reader of field `FBM8`"] 206 | pub type FBM8_R = crate::R; 207 | #[doc = "Write proxy for field `FBM8`"] 208 | pub struct FBM8_W<'a> { 209 | w: &'a mut W, 210 | } 211 | impl<'a> FBM8_W<'a> { 212 | #[doc = r"Sets the field bit"] 213 | #[inline(always)] 214 | pub fn set_bit(self) -> &'a mut W { 215 | self.bit(true) 216 | } 217 | #[doc = r"Clears the field bit"] 218 | #[inline(always)] 219 | pub fn clear_bit(self) -> &'a mut W { 220 | self.bit(false) 221 | } 222 | #[doc = r"Writes raw bits to the field"] 223 | #[inline(always)] 224 | pub fn bit(self, value: bool) -> &'a mut W { 225 | self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); 226 | self.w 227 | } 228 | } 229 | #[doc = "Reader of field `FBM9`"] 230 | pub type FBM9_R = crate::R; 231 | #[doc = "Write proxy for field `FBM9`"] 232 | pub struct FBM9_W<'a> { 233 | w: &'a mut W, 234 | } 235 | impl<'a> FBM9_W<'a> { 236 | #[doc = r"Sets the field bit"] 237 | #[inline(always)] 238 | pub fn set_bit(self) -> &'a mut W { 239 | self.bit(true) 240 | } 241 | #[doc = r"Clears the field bit"] 242 | #[inline(always)] 243 | pub fn clear_bit(self) -> &'a mut W { 244 | self.bit(false) 245 | } 246 | #[doc = r"Writes raw bits to the field"] 247 | #[inline(always)] 248 | pub fn bit(self, value: bool) -> &'a mut W { 249 | self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); 250 | self.w 251 | } 252 | } 253 | #[doc = "Reader of field `FBM10`"] 254 | pub type FBM10_R = crate::R; 255 | #[doc = "Write proxy for field `FBM10`"] 256 | pub struct FBM10_W<'a> { 257 | w: &'a mut W, 258 | } 259 | impl<'a> FBM10_W<'a> { 260 | #[doc = r"Sets the field bit"] 261 | #[inline(always)] 262 | pub fn set_bit(self) -> &'a mut W { 263 | self.bit(true) 264 | } 265 | #[doc = r"Clears the field bit"] 266 | #[inline(always)] 267 | pub fn clear_bit(self) -> &'a mut W { 268 | self.bit(false) 269 | } 270 | #[doc = r"Writes raw bits to the field"] 271 | #[inline(always)] 272 | pub fn bit(self, value: bool) -> &'a mut W { 273 | self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); 274 | self.w 275 | } 276 | } 277 | #[doc = "Reader of field `FBM11`"] 278 | pub type FBM11_R = crate::R; 279 | #[doc = "Write proxy for field `FBM11`"] 280 | pub struct FBM11_W<'a> { 281 | w: &'a mut W, 282 | } 283 | impl<'a> FBM11_W<'a> { 284 | #[doc = r"Sets the field bit"] 285 | #[inline(always)] 286 | pub fn set_bit(self) -> &'a mut W { 287 | self.bit(true) 288 | } 289 | #[doc = r"Clears the field bit"] 290 | #[inline(always)] 291 | pub fn clear_bit(self) -> &'a mut W { 292 | self.bit(false) 293 | } 294 | #[doc = r"Writes raw bits to the field"] 295 | #[inline(always)] 296 | pub fn bit(self, value: bool) -> &'a mut W { 297 | self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); 298 | self.w 299 | } 300 | } 301 | #[doc = "Reader of field `FBM12`"] 302 | pub type FBM12_R = crate::R; 303 | #[doc = "Write proxy for field `FBM12`"] 304 | pub struct FBM12_W<'a> { 305 | w: &'a mut W, 306 | } 307 | impl<'a> FBM12_W<'a> { 308 | #[doc = r"Sets the field bit"] 309 | #[inline(always)] 310 | pub fn set_bit(self) -> &'a mut W { 311 | self.bit(true) 312 | } 313 | #[doc = r"Clears the field bit"] 314 | #[inline(always)] 315 | pub fn clear_bit(self) -> &'a mut W { 316 | self.bit(false) 317 | } 318 | #[doc = r"Writes raw bits to the field"] 319 | #[inline(always)] 320 | pub fn bit(self, value: bool) -> &'a mut W { 321 | self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); 322 | self.w 323 | } 324 | } 325 | #[doc = "Reader of field `FBM13`"] 326 | pub type FBM13_R = crate::R; 327 | #[doc = "Write proxy for field `FBM13`"] 328 | pub struct FBM13_W<'a> { 329 | w: &'a mut W, 330 | } 331 | impl<'a> FBM13_W<'a> { 332 | #[doc = r"Sets the field bit"] 333 | #[inline(always)] 334 | pub fn set_bit(self) -> &'a mut W { 335 | self.bit(true) 336 | } 337 | #[doc = r"Clears the field bit"] 338 | #[inline(always)] 339 | pub fn clear_bit(self) -> &'a mut W { 340 | self.bit(false) 341 | } 342 | #[doc = r"Writes raw bits to the field"] 343 | #[inline(always)] 344 | pub fn bit(self, value: bool) -> &'a mut W { 345 | self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); 346 | self.w 347 | } 348 | } 349 | impl R { 350 | #[doc = "Bit 0 - Filter mode"] 351 | #[inline(always)] 352 | pub fn fbm0(&self) -> FBM0_R { 353 | FBM0_R::new((self.bits & 0x01) != 0) 354 | } 355 | #[doc = "Bit 1 - Filter mode"] 356 | #[inline(always)] 357 | pub fn fbm1(&self) -> FBM1_R { 358 | FBM1_R::new(((self.bits >> 1) & 0x01) != 0) 359 | } 360 | #[doc = "Bit 2 - Filter mode"] 361 | #[inline(always)] 362 | pub fn fbm2(&self) -> FBM2_R { 363 | FBM2_R::new(((self.bits >> 2) & 0x01) != 0) 364 | } 365 | #[doc = "Bit 3 - Filter mode"] 366 | #[inline(always)] 367 | pub fn fbm3(&self) -> FBM3_R { 368 | FBM3_R::new(((self.bits >> 3) & 0x01) != 0) 369 | } 370 | #[doc = "Bit 4 - Filter mode"] 371 | #[inline(always)] 372 | pub fn fbm4(&self) -> FBM4_R { 373 | FBM4_R::new(((self.bits >> 4) & 0x01) != 0) 374 | } 375 | #[doc = "Bit 5 - Filter mode"] 376 | #[inline(always)] 377 | pub fn fbm5(&self) -> FBM5_R { 378 | FBM5_R::new(((self.bits >> 5) & 0x01) != 0) 379 | } 380 | #[doc = "Bit 6 - Filter mode"] 381 | #[inline(always)] 382 | pub fn fbm6(&self) -> FBM6_R { 383 | FBM6_R::new(((self.bits >> 6) & 0x01) != 0) 384 | } 385 | #[doc = "Bit 7 - Filter mode"] 386 | #[inline(always)] 387 | pub fn fbm7(&self) -> FBM7_R { 388 | FBM7_R::new(((self.bits >> 7) & 0x01) != 0) 389 | } 390 | #[doc = "Bit 8 - Filter mode"] 391 | #[inline(always)] 392 | pub fn fbm8(&self) -> FBM8_R { 393 | FBM8_R::new(((self.bits >> 8) & 0x01) != 0) 394 | } 395 | #[doc = "Bit 9 - Filter mode"] 396 | #[inline(always)] 397 | pub fn fbm9(&self) -> FBM9_R { 398 | FBM9_R::new(((self.bits >> 9) & 0x01) != 0) 399 | } 400 | #[doc = "Bit 10 - Filter mode"] 401 | #[inline(always)] 402 | pub fn fbm10(&self) -> FBM10_R { 403 | FBM10_R::new(((self.bits >> 10) & 0x01) != 0) 404 | } 405 | #[doc = "Bit 11 - Filter mode"] 406 | #[inline(always)] 407 | pub fn fbm11(&self) -> FBM11_R { 408 | FBM11_R::new(((self.bits >> 11) & 0x01) != 0) 409 | } 410 | #[doc = "Bit 12 - Filter mode"] 411 | #[inline(always)] 412 | pub fn fbm12(&self) -> FBM12_R { 413 | FBM12_R::new(((self.bits >> 12) & 0x01) != 0) 414 | } 415 | #[doc = "Bit 13 - Filter mode"] 416 | #[inline(always)] 417 | pub fn fbm13(&self) -> FBM13_R { 418 | FBM13_R::new(((self.bits >> 13) & 0x01) != 0) 419 | } 420 | } 421 | impl W { 422 | #[doc = "Bit 0 - Filter mode"] 423 | #[inline(always)] 424 | pub fn fbm0(&mut self) -> FBM0_W { 425 | FBM0_W { w: self } 426 | } 427 | #[doc = "Bit 1 - Filter mode"] 428 | #[inline(always)] 429 | pub fn fbm1(&mut self) -> FBM1_W { 430 | FBM1_W { w: self } 431 | } 432 | #[doc = "Bit 2 - Filter mode"] 433 | #[inline(always)] 434 | pub fn fbm2(&mut self) -> FBM2_W { 435 | FBM2_W { w: self } 436 | } 437 | #[doc = "Bit 3 - Filter mode"] 438 | #[inline(always)] 439 | pub fn fbm3(&mut self) -> FBM3_W { 440 | FBM3_W { w: self } 441 | } 442 | #[doc = "Bit 4 - Filter mode"] 443 | #[inline(always)] 444 | pub fn fbm4(&mut self) -> FBM4_W { 445 | FBM4_W { w: self } 446 | } 447 | #[doc = "Bit 5 - Filter mode"] 448 | #[inline(always)] 449 | pub fn fbm5(&mut self) -> FBM5_W { 450 | FBM5_W { w: self } 451 | } 452 | #[doc = "Bit 6 - Filter mode"] 453 | #[inline(always)] 454 | pub fn fbm6(&mut self) -> FBM6_W { 455 | FBM6_W { w: self } 456 | } 457 | #[doc = "Bit 7 - Filter mode"] 458 | #[inline(always)] 459 | pub fn fbm7(&mut self) -> FBM7_W { 460 | FBM7_W { w: self } 461 | } 462 | #[doc = "Bit 8 - Filter mode"] 463 | #[inline(always)] 464 | pub fn fbm8(&mut self) -> FBM8_W { 465 | FBM8_W { w: self } 466 | } 467 | #[doc = "Bit 9 - Filter mode"] 468 | #[inline(always)] 469 | pub fn fbm9(&mut self) -> FBM9_W { 470 | FBM9_W { w: self } 471 | } 472 | #[doc = "Bit 10 - Filter mode"] 473 | #[inline(always)] 474 | pub fn fbm10(&mut self) -> FBM10_W { 475 | FBM10_W { w: self } 476 | } 477 | #[doc = "Bit 11 - Filter mode"] 478 | #[inline(always)] 479 | pub fn fbm11(&mut self) -> FBM11_W { 480 | FBM11_W { w: self } 481 | } 482 | #[doc = "Bit 12 - Filter mode"] 483 | #[inline(always)] 484 | pub fn fbm12(&mut self) -> FBM12_W { 485 | FBM12_W { w: self } 486 | } 487 | #[doc = "Bit 13 - Filter mode"] 488 | #[inline(always)] 489 | pub fn fbm13(&mut self) -> FBM13_W { 490 | FBM13_W { w: self } 491 | } 492 | } 493 | -------------------------------------------------------------------------------- /src/pac/can/fmr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register FMR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register FMR"] 4 | pub type W = crate::W; 5 | #[doc = "Register FMR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::FMR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `CAN2SB`"] 14 | pub type CAN2SB_R = crate::R; 15 | #[doc = "Write proxy for field `CAN2SB`"] 16 | pub struct CAN2SB_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> CAN2SB_W<'a> { 20 | #[doc = r"Writes raw bits to the field"] 21 | #[inline(always)] 22 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 23 | self.w.bits = (self.w.bits & !(0x3f << 8)) | (((value as u32) & 0x3f) << 8); 24 | self.w 25 | } 26 | } 27 | #[doc = "Reader of field `FINIT`"] 28 | pub type FINIT_R = crate::R; 29 | #[doc = "Write proxy for field `FINIT`"] 30 | pub struct FINIT_W<'a> { 31 | w: &'a mut W, 32 | } 33 | impl<'a> FINIT_W<'a> { 34 | #[doc = r"Sets the field bit"] 35 | #[inline(always)] 36 | pub fn set_bit(self) -> &'a mut W { 37 | self.bit(true) 38 | } 39 | #[doc = r"Clears the field bit"] 40 | #[inline(always)] 41 | pub fn clear_bit(self) -> &'a mut W { 42 | self.bit(false) 43 | } 44 | #[doc = r"Writes raw bits to the field"] 45 | #[inline(always)] 46 | pub fn bit(self, value: bool) -> &'a mut W { 47 | self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); 48 | self.w 49 | } 50 | } 51 | impl R { 52 | #[doc = "Bits 8:13 - CAN2SB"] 53 | #[inline(always)] 54 | pub fn can2sb(&self) -> CAN2SB_R { 55 | CAN2SB_R::new(((self.bits >> 8) & 0x3f) as u8) 56 | } 57 | #[doc = "Bit 0 - FINIT"] 58 | #[inline(always)] 59 | pub fn finit(&self) -> FINIT_R { 60 | FINIT_R::new((self.bits & 0x01) != 0) 61 | } 62 | } 63 | impl W { 64 | #[doc = "Bits 8:13 - CAN2SB"] 65 | #[inline(always)] 66 | pub fn can2sb(&mut self) -> CAN2SB_W { 67 | CAN2SB_W { w: self } 68 | } 69 | #[doc = "Bit 0 - FINIT"] 70 | #[inline(always)] 71 | pub fn finit(&mut self) -> FINIT_W { 72 | FINIT_W { w: self } 73 | } 74 | } 75 | -------------------------------------------------------------------------------- /src/pac/can/fs1r.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register FS1R"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register FS1R"] 4 | pub type W = crate::W; 5 | #[doc = "Register FS1R `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::FS1R { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `FSC0`"] 14 | pub type FSC0_R = crate::R; 15 | #[doc = "Write proxy for field `FSC0`"] 16 | pub struct FSC0_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> FSC0_W<'a> { 20 | #[doc = r"Sets the field bit"] 21 | #[inline(always)] 22 | pub fn set_bit(self) -> &'a mut W { 23 | self.bit(true) 24 | } 25 | #[doc = r"Clears the field bit"] 26 | #[inline(always)] 27 | pub fn clear_bit(self) -> &'a mut W { 28 | self.bit(false) 29 | } 30 | #[doc = r"Writes raw bits to the field"] 31 | #[inline(always)] 32 | pub fn bit(self, value: bool) -> &'a mut W { 33 | self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); 34 | self.w 35 | } 36 | } 37 | #[doc = "Reader of field `FSC1`"] 38 | pub type FSC1_R = crate::R; 39 | #[doc = "Write proxy for field `FSC1`"] 40 | pub struct FSC1_W<'a> { 41 | w: &'a mut W, 42 | } 43 | impl<'a> FSC1_W<'a> { 44 | #[doc = r"Sets the field bit"] 45 | #[inline(always)] 46 | pub fn set_bit(self) -> &'a mut W { 47 | self.bit(true) 48 | } 49 | #[doc = r"Clears the field bit"] 50 | #[inline(always)] 51 | pub fn clear_bit(self) -> &'a mut W { 52 | self.bit(false) 53 | } 54 | #[doc = r"Writes raw bits to the field"] 55 | #[inline(always)] 56 | pub fn bit(self, value: bool) -> &'a mut W { 57 | self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); 58 | self.w 59 | } 60 | } 61 | #[doc = "Reader of field `FSC2`"] 62 | pub type FSC2_R = crate::R; 63 | #[doc = "Write proxy for field `FSC2`"] 64 | pub struct FSC2_W<'a> { 65 | w: &'a mut W, 66 | } 67 | impl<'a> FSC2_W<'a> { 68 | #[doc = r"Sets the field bit"] 69 | #[inline(always)] 70 | pub fn set_bit(self) -> &'a mut W { 71 | self.bit(true) 72 | } 73 | #[doc = r"Clears the field bit"] 74 | #[inline(always)] 75 | pub fn clear_bit(self) -> &'a mut W { 76 | self.bit(false) 77 | } 78 | #[doc = r"Writes raw bits to the field"] 79 | #[inline(always)] 80 | pub fn bit(self, value: bool) -> &'a mut W { 81 | self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); 82 | self.w 83 | } 84 | } 85 | #[doc = "Reader of field `FSC3`"] 86 | pub type FSC3_R = crate::R; 87 | #[doc = "Write proxy for field `FSC3`"] 88 | pub struct FSC3_W<'a> { 89 | w: &'a mut W, 90 | } 91 | impl<'a> FSC3_W<'a> { 92 | #[doc = r"Sets the field bit"] 93 | #[inline(always)] 94 | pub fn set_bit(self) -> &'a mut W { 95 | self.bit(true) 96 | } 97 | #[doc = r"Clears the field bit"] 98 | #[inline(always)] 99 | pub fn clear_bit(self) -> &'a mut W { 100 | self.bit(false) 101 | } 102 | #[doc = r"Writes raw bits to the field"] 103 | #[inline(always)] 104 | pub fn bit(self, value: bool) -> &'a mut W { 105 | self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); 106 | self.w 107 | } 108 | } 109 | #[doc = "Reader of field `FSC4`"] 110 | pub type FSC4_R = crate::R; 111 | #[doc = "Write proxy for field `FSC4`"] 112 | pub struct FSC4_W<'a> { 113 | w: &'a mut W, 114 | } 115 | impl<'a> FSC4_W<'a> { 116 | #[doc = r"Sets the field bit"] 117 | #[inline(always)] 118 | pub fn set_bit(self) -> &'a mut W { 119 | self.bit(true) 120 | } 121 | #[doc = r"Clears the field bit"] 122 | #[inline(always)] 123 | pub fn clear_bit(self) -> &'a mut W { 124 | self.bit(false) 125 | } 126 | #[doc = r"Writes raw bits to the field"] 127 | #[inline(always)] 128 | pub fn bit(self, value: bool) -> &'a mut W { 129 | self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); 130 | self.w 131 | } 132 | } 133 | #[doc = "Reader of field `FSC5`"] 134 | pub type FSC5_R = crate::R; 135 | #[doc = "Write proxy for field `FSC5`"] 136 | pub struct FSC5_W<'a> { 137 | w: &'a mut W, 138 | } 139 | impl<'a> FSC5_W<'a> { 140 | #[doc = r"Sets the field bit"] 141 | #[inline(always)] 142 | pub fn set_bit(self) -> &'a mut W { 143 | self.bit(true) 144 | } 145 | #[doc = r"Clears the field bit"] 146 | #[inline(always)] 147 | pub fn clear_bit(self) -> &'a mut W { 148 | self.bit(false) 149 | } 150 | #[doc = r"Writes raw bits to the field"] 151 | #[inline(always)] 152 | pub fn bit(self, value: bool) -> &'a mut W { 153 | self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); 154 | self.w 155 | } 156 | } 157 | #[doc = "Reader of field `FSC6`"] 158 | pub type FSC6_R = crate::R; 159 | #[doc = "Write proxy for field `FSC6`"] 160 | pub struct FSC6_W<'a> { 161 | w: &'a mut W, 162 | } 163 | impl<'a> FSC6_W<'a> { 164 | #[doc = r"Sets the field bit"] 165 | #[inline(always)] 166 | pub fn set_bit(self) -> &'a mut W { 167 | self.bit(true) 168 | } 169 | #[doc = r"Clears the field bit"] 170 | #[inline(always)] 171 | pub fn clear_bit(self) -> &'a mut W { 172 | self.bit(false) 173 | } 174 | #[doc = r"Writes raw bits to the field"] 175 | #[inline(always)] 176 | pub fn bit(self, value: bool) -> &'a mut W { 177 | self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); 178 | self.w 179 | } 180 | } 181 | #[doc = "Reader of field `FSC7`"] 182 | pub type FSC7_R = crate::R; 183 | #[doc = "Write proxy for field `FSC7`"] 184 | pub struct FSC7_W<'a> { 185 | w: &'a mut W, 186 | } 187 | impl<'a> FSC7_W<'a> { 188 | #[doc = r"Sets the field bit"] 189 | #[inline(always)] 190 | pub fn set_bit(self) -> &'a mut W { 191 | self.bit(true) 192 | } 193 | #[doc = r"Clears the field bit"] 194 | #[inline(always)] 195 | pub fn clear_bit(self) -> &'a mut W { 196 | self.bit(false) 197 | } 198 | #[doc = r"Writes raw bits to the field"] 199 | #[inline(always)] 200 | pub fn bit(self, value: bool) -> &'a mut W { 201 | self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); 202 | self.w 203 | } 204 | } 205 | #[doc = "Reader of field `FSC8`"] 206 | pub type FSC8_R = crate::R; 207 | #[doc = "Write proxy for field `FSC8`"] 208 | pub struct FSC8_W<'a> { 209 | w: &'a mut W, 210 | } 211 | impl<'a> FSC8_W<'a> { 212 | #[doc = r"Sets the field bit"] 213 | #[inline(always)] 214 | pub fn set_bit(self) -> &'a mut W { 215 | self.bit(true) 216 | } 217 | #[doc = r"Clears the field bit"] 218 | #[inline(always)] 219 | pub fn clear_bit(self) -> &'a mut W { 220 | self.bit(false) 221 | } 222 | #[doc = r"Writes raw bits to the field"] 223 | #[inline(always)] 224 | pub fn bit(self, value: bool) -> &'a mut W { 225 | self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); 226 | self.w 227 | } 228 | } 229 | #[doc = "Reader of field `FSC9`"] 230 | pub type FSC9_R = crate::R; 231 | #[doc = "Write proxy for field `FSC9`"] 232 | pub struct FSC9_W<'a> { 233 | w: &'a mut W, 234 | } 235 | impl<'a> FSC9_W<'a> { 236 | #[doc = r"Sets the field bit"] 237 | #[inline(always)] 238 | pub fn set_bit(self) -> &'a mut W { 239 | self.bit(true) 240 | } 241 | #[doc = r"Clears the field bit"] 242 | #[inline(always)] 243 | pub fn clear_bit(self) -> &'a mut W { 244 | self.bit(false) 245 | } 246 | #[doc = r"Writes raw bits to the field"] 247 | #[inline(always)] 248 | pub fn bit(self, value: bool) -> &'a mut W { 249 | self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); 250 | self.w 251 | } 252 | } 253 | #[doc = "Reader of field `FSC10`"] 254 | pub type FSC10_R = crate::R; 255 | #[doc = "Write proxy for field `FSC10`"] 256 | pub struct FSC10_W<'a> { 257 | w: &'a mut W, 258 | } 259 | impl<'a> FSC10_W<'a> { 260 | #[doc = r"Sets the field bit"] 261 | #[inline(always)] 262 | pub fn set_bit(self) -> &'a mut W { 263 | self.bit(true) 264 | } 265 | #[doc = r"Clears the field bit"] 266 | #[inline(always)] 267 | pub fn clear_bit(self) -> &'a mut W { 268 | self.bit(false) 269 | } 270 | #[doc = r"Writes raw bits to the field"] 271 | #[inline(always)] 272 | pub fn bit(self, value: bool) -> &'a mut W { 273 | self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); 274 | self.w 275 | } 276 | } 277 | #[doc = "Reader of field `FSC11`"] 278 | pub type FSC11_R = crate::R; 279 | #[doc = "Write proxy for field `FSC11`"] 280 | pub struct FSC11_W<'a> { 281 | w: &'a mut W, 282 | } 283 | impl<'a> FSC11_W<'a> { 284 | #[doc = r"Sets the field bit"] 285 | #[inline(always)] 286 | pub fn set_bit(self) -> &'a mut W { 287 | self.bit(true) 288 | } 289 | #[doc = r"Clears the field bit"] 290 | #[inline(always)] 291 | pub fn clear_bit(self) -> &'a mut W { 292 | self.bit(false) 293 | } 294 | #[doc = r"Writes raw bits to the field"] 295 | #[inline(always)] 296 | pub fn bit(self, value: bool) -> &'a mut W { 297 | self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); 298 | self.w 299 | } 300 | } 301 | #[doc = "Reader of field `FSC12`"] 302 | pub type FSC12_R = crate::R; 303 | #[doc = "Write proxy for field `FSC12`"] 304 | pub struct FSC12_W<'a> { 305 | w: &'a mut W, 306 | } 307 | impl<'a> FSC12_W<'a> { 308 | #[doc = r"Sets the field bit"] 309 | #[inline(always)] 310 | pub fn set_bit(self) -> &'a mut W { 311 | self.bit(true) 312 | } 313 | #[doc = r"Clears the field bit"] 314 | #[inline(always)] 315 | pub fn clear_bit(self) -> &'a mut W { 316 | self.bit(false) 317 | } 318 | #[doc = r"Writes raw bits to the field"] 319 | #[inline(always)] 320 | pub fn bit(self, value: bool) -> &'a mut W { 321 | self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); 322 | self.w 323 | } 324 | } 325 | #[doc = "Reader of field `FSC13`"] 326 | pub type FSC13_R = crate::R; 327 | #[doc = "Write proxy for field `FSC13`"] 328 | pub struct FSC13_W<'a> { 329 | w: &'a mut W, 330 | } 331 | impl<'a> FSC13_W<'a> { 332 | #[doc = r"Sets the field bit"] 333 | #[inline(always)] 334 | pub fn set_bit(self) -> &'a mut W { 335 | self.bit(true) 336 | } 337 | #[doc = r"Clears the field bit"] 338 | #[inline(always)] 339 | pub fn clear_bit(self) -> &'a mut W { 340 | self.bit(false) 341 | } 342 | #[doc = r"Writes raw bits to the field"] 343 | #[inline(always)] 344 | pub fn bit(self, value: bool) -> &'a mut W { 345 | self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); 346 | self.w 347 | } 348 | } 349 | impl R { 350 | #[doc = "Bit 0 - Filter scale configuration"] 351 | #[inline(always)] 352 | pub fn fsc0(&self) -> FSC0_R { 353 | FSC0_R::new((self.bits & 0x01) != 0) 354 | } 355 | #[doc = "Bit 1 - Filter scale configuration"] 356 | #[inline(always)] 357 | pub fn fsc1(&self) -> FSC1_R { 358 | FSC1_R::new(((self.bits >> 1) & 0x01) != 0) 359 | } 360 | #[doc = "Bit 2 - Filter scale configuration"] 361 | #[inline(always)] 362 | pub fn fsc2(&self) -> FSC2_R { 363 | FSC2_R::new(((self.bits >> 2) & 0x01) != 0) 364 | } 365 | #[doc = "Bit 3 - Filter scale configuration"] 366 | #[inline(always)] 367 | pub fn fsc3(&self) -> FSC3_R { 368 | FSC3_R::new(((self.bits >> 3) & 0x01) != 0) 369 | } 370 | #[doc = "Bit 4 - Filter scale configuration"] 371 | #[inline(always)] 372 | pub fn fsc4(&self) -> FSC4_R { 373 | FSC4_R::new(((self.bits >> 4) & 0x01) != 0) 374 | } 375 | #[doc = "Bit 5 - Filter scale configuration"] 376 | #[inline(always)] 377 | pub fn fsc5(&self) -> FSC5_R { 378 | FSC5_R::new(((self.bits >> 5) & 0x01) != 0) 379 | } 380 | #[doc = "Bit 6 - Filter scale configuration"] 381 | #[inline(always)] 382 | pub fn fsc6(&self) -> FSC6_R { 383 | FSC6_R::new(((self.bits >> 6) & 0x01) != 0) 384 | } 385 | #[doc = "Bit 7 - Filter scale configuration"] 386 | #[inline(always)] 387 | pub fn fsc7(&self) -> FSC7_R { 388 | FSC7_R::new(((self.bits >> 7) & 0x01) != 0) 389 | } 390 | #[doc = "Bit 8 - Filter scale configuration"] 391 | #[inline(always)] 392 | pub fn fsc8(&self) -> FSC8_R { 393 | FSC8_R::new(((self.bits >> 8) & 0x01) != 0) 394 | } 395 | #[doc = "Bit 9 - Filter scale configuration"] 396 | #[inline(always)] 397 | pub fn fsc9(&self) -> FSC9_R { 398 | FSC9_R::new(((self.bits >> 9) & 0x01) != 0) 399 | } 400 | #[doc = "Bit 10 - Filter scale configuration"] 401 | #[inline(always)] 402 | pub fn fsc10(&self) -> FSC10_R { 403 | FSC10_R::new(((self.bits >> 10) & 0x01) != 0) 404 | } 405 | #[doc = "Bit 11 - Filter scale configuration"] 406 | #[inline(always)] 407 | pub fn fsc11(&self) -> FSC11_R { 408 | FSC11_R::new(((self.bits >> 11) & 0x01) != 0) 409 | } 410 | #[doc = "Bit 12 - Filter scale configuration"] 411 | #[inline(always)] 412 | pub fn fsc12(&self) -> FSC12_R { 413 | FSC12_R::new(((self.bits >> 12) & 0x01) != 0) 414 | } 415 | #[doc = "Bit 13 - Filter scale configuration"] 416 | #[inline(always)] 417 | pub fn fsc13(&self) -> FSC13_R { 418 | FSC13_R::new(((self.bits >> 13) & 0x01) != 0) 419 | } 420 | } 421 | impl W { 422 | #[doc = "Bit 0 - Filter scale configuration"] 423 | #[inline(always)] 424 | pub fn fsc0(&mut self) -> FSC0_W { 425 | FSC0_W { w: self } 426 | } 427 | #[doc = "Bit 1 - Filter scale configuration"] 428 | #[inline(always)] 429 | pub fn fsc1(&mut self) -> FSC1_W { 430 | FSC1_W { w: self } 431 | } 432 | #[doc = "Bit 2 - Filter scale configuration"] 433 | #[inline(always)] 434 | pub fn fsc2(&mut self) -> FSC2_W { 435 | FSC2_W { w: self } 436 | } 437 | #[doc = "Bit 3 - Filter scale configuration"] 438 | #[inline(always)] 439 | pub fn fsc3(&mut self) -> FSC3_W { 440 | FSC3_W { w: self } 441 | } 442 | #[doc = "Bit 4 - Filter scale configuration"] 443 | #[inline(always)] 444 | pub fn fsc4(&mut self) -> FSC4_W { 445 | FSC4_W { w: self } 446 | } 447 | #[doc = "Bit 5 - Filter scale configuration"] 448 | #[inline(always)] 449 | pub fn fsc5(&mut self) -> FSC5_W { 450 | FSC5_W { w: self } 451 | } 452 | #[doc = "Bit 6 - Filter scale configuration"] 453 | #[inline(always)] 454 | pub fn fsc6(&mut self) -> FSC6_W { 455 | FSC6_W { w: self } 456 | } 457 | #[doc = "Bit 7 - Filter scale configuration"] 458 | #[inline(always)] 459 | pub fn fsc7(&mut self) -> FSC7_W { 460 | FSC7_W { w: self } 461 | } 462 | #[doc = "Bit 8 - Filter scale configuration"] 463 | #[inline(always)] 464 | pub fn fsc8(&mut self) -> FSC8_W { 465 | FSC8_W { w: self } 466 | } 467 | #[doc = "Bit 9 - Filter scale configuration"] 468 | #[inline(always)] 469 | pub fn fsc9(&mut self) -> FSC9_W { 470 | FSC9_W { w: self } 471 | } 472 | #[doc = "Bit 10 - Filter scale configuration"] 473 | #[inline(always)] 474 | pub fn fsc10(&mut self) -> FSC10_W { 475 | FSC10_W { w: self } 476 | } 477 | #[doc = "Bit 11 - Filter scale configuration"] 478 | #[inline(always)] 479 | pub fn fsc11(&mut self) -> FSC11_W { 480 | FSC11_W { w: self } 481 | } 482 | #[doc = "Bit 12 - Filter scale configuration"] 483 | #[inline(always)] 484 | pub fn fsc12(&mut self) -> FSC12_W { 485 | FSC12_W { w: self } 486 | } 487 | #[doc = "Bit 13 - Filter scale configuration"] 488 | #[inline(always)] 489 | pub fn fsc13(&mut self) -> FSC13_W { 490 | FSC13_W { w: self } 491 | } 492 | } 493 | -------------------------------------------------------------------------------- /src/pac/can/mcr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register MCR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register MCR"] 4 | pub type W = crate::W; 5 | #[doc = "Register MCR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::MCR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `DBF`"] 14 | pub type DBF_R = crate::R; 15 | #[doc = "Write proxy for field `DBF`"] 16 | pub struct DBF_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> DBF_W<'a> { 20 | #[doc = r"Sets the field bit"] 21 | #[inline(always)] 22 | pub fn set_bit(self) -> &'a mut W { 23 | self.bit(true) 24 | } 25 | #[doc = r"Clears the field bit"] 26 | #[inline(always)] 27 | pub fn clear_bit(self) -> &'a mut W { 28 | self.bit(false) 29 | } 30 | #[doc = r"Writes raw bits to the field"] 31 | #[inline(always)] 32 | pub fn bit(self, value: bool) -> &'a mut W { 33 | self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); 34 | self.w 35 | } 36 | } 37 | #[doc = "Reader of field `RESET`"] 38 | pub type RESET_R = crate::R; 39 | #[doc = "Write proxy for field `RESET`"] 40 | pub struct RESET_W<'a> { 41 | w: &'a mut W, 42 | } 43 | impl<'a> RESET_W<'a> { 44 | #[doc = r"Sets the field bit"] 45 | #[inline(always)] 46 | pub fn set_bit(self) -> &'a mut W { 47 | self.bit(true) 48 | } 49 | #[doc = r"Clears the field bit"] 50 | #[inline(always)] 51 | pub fn clear_bit(self) -> &'a mut W { 52 | self.bit(false) 53 | } 54 | #[doc = r"Writes raw bits to the field"] 55 | #[inline(always)] 56 | pub fn bit(self, value: bool) -> &'a mut W { 57 | self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); 58 | self.w 59 | } 60 | } 61 | #[doc = "Reader of field `TTCM`"] 62 | pub type TTCM_R = crate::R; 63 | #[doc = "Write proxy for field `TTCM`"] 64 | pub struct TTCM_W<'a> { 65 | w: &'a mut W, 66 | } 67 | impl<'a> TTCM_W<'a> { 68 | #[doc = r"Sets the field bit"] 69 | #[inline(always)] 70 | pub fn set_bit(self) -> &'a mut W { 71 | self.bit(true) 72 | } 73 | #[doc = r"Clears the field bit"] 74 | #[inline(always)] 75 | pub fn clear_bit(self) -> &'a mut W { 76 | self.bit(false) 77 | } 78 | #[doc = r"Writes raw bits to the field"] 79 | #[inline(always)] 80 | pub fn bit(self, value: bool) -> &'a mut W { 81 | self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); 82 | self.w 83 | } 84 | } 85 | #[doc = "Reader of field `ABOM`"] 86 | pub type ABOM_R = crate::R; 87 | #[doc = "Write proxy for field `ABOM`"] 88 | pub struct ABOM_W<'a> { 89 | w: &'a mut W, 90 | } 91 | impl<'a> ABOM_W<'a> { 92 | #[doc = r"Sets the field bit"] 93 | #[inline(always)] 94 | pub fn set_bit(self) -> &'a mut W { 95 | self.bit(true) 96 | } 97 | #[doc = r"Clears the field bit"] 98 | #[inline(always)] 99 | pub fn clear_bit(self) -> &'a mut W { 100 | self.bit(false) 101 | } 102 | #[doc = r"Writes raw bits to the field"] 103 | #[inline(always)] 104 | pub fn bit(self, value: bool) -> &'a mut W { 105 | self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); 106 | self.w 107 | } 108 | } 109 | #[doc = "Reader of field `AWUM`"] 110 | pub type AWUM_R = crate::R; 111 | #[doc = "Write proxy for field `AWUM`"] 112 | pub struct AWUM_W<'a> { 113 | w: &'a mut W, 114 | } 115 | impl<'a> AWUM_W<'a> { 116 | #[doc = r"Sets the field bit"] 117 | #[inline(always)] 118 | pub fn set_bit(self) -> &'a mut W { 119 | self.bit(true) 120 | } 121 | #[doc = r"Clears the field bit"] 122 | #[inline(always)] 123 | pub fn clear_bit(self) -> &'a mut W { 124 | self.bit(false) 125 | } 126 | #[doc = r"Writes raw bits to the field"] 127 | #[inline(always)] 128 | pub fn bit(self, value: bool) -> &'a mut W { 129 | self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); 130 | self.w 131 | } 132 | } 133 | #[doc = "Reader of field `NART`"] 134 | pub type NART_R = crate::R; 135 | #[doc = "Write proxy for field `NART`"] 136 | pub struct NART_W<'a> { 137 | w: &'a mut W, 138 | } 139 | impl<'a> NART_W<'a> { 140 | #[doc = r"Sets the field bit"] 141 | #[inline(always)] 142 | pub fn set_bit(self) -> &'a mut W { 143 | self.bit(true) 144 | } 145 | #[doc = r"Clears the field bit"] 146 | #[inline(always)] 147 | pub fn clear_bit(self) -> &'a mut W { 148 | self.bit(false) 149 | } 150 | #[doc = r"Writes raw bits to the field"] 151 | #[inline(always)] 152 | pub fn bit(self, value: bool) -> &'a mut W { 153 | self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); 154 | self.w 155 | } 156 | } 157 | #[doc = "Reader of field `RFLM`"] 158 | pub type RFLM_R = crate::R; 159 | #[doc = "Write proxy for field `RFLM`"] 160 | pub struct RFLM_W<'a> { 161 | w: &'a mut W, 162 | } 163 | impl<'a> RFLM_W<'a> { 164 | #[doc = r"Sets the field bit"] 165 | #[inline(always)] 166 | pub fn set_bit(self) -> &'a mut W { 167 | self.bit(true) 168 | } 169 | #[doc = r"Clears the field bit"] 170 | #[inline(always)] 171 | pub fn clear_bit(self) -> &'a mut W { 172 | self.bit(false) 173 | } 174 | #[doc = r"Writes raw bits to the field"] 175 | #[inline(always)] 176 | pub fn bit(self, value: bool) -> &'a mut W { 177 | self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); 178 | self.w 179 | } 180 | } 181 | #[doc = "Reader of field `TXFP`"] 182 | pub type TXFP_R = crate::R; 183 | #[doc = "Write proxy for field `TXFP`"] 184 | pub struct TXFP_W<'a> { 185 | w: &'a mut W, 186 | } 187 | impl<'a> TXFP_W<'a> { 188 | #[doc = r"Sets the field bit"] 189 | #[inline(always)] 190 | pub fn set_bit(self) -> &'a mut W { 191 | self.bit(true) 192 | } 193 | #[doc = r"Clears the field bit"] 194 | #[inline(always)] 195 | pub fn clear_bit(self) -> &'a mut W { 196 | self.bit(false) 197 | } 198 | #[doc = r"Writes raw bits to the field"] 199 | #[inline(always)] 200 | pub fn bit(self, value: bool) -> &'a mut W { 201 | self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); 202 | self.w 203 | } 204 | } 205 | #[doc = "Reader of field `SLEEP`"] 206 | pub type SLEEP_R = crate::R; 207 | #[doc = "Write proxy for field `SLEEP`"] 208 | pub struct SLEEP_W<'a> { 209 | w: &'a mut W, 210 | } 211 | impl<'a> SLEEP_W<'a> { 212 | #[doc = r"Sets the field bit"] 213 | #[inline(always)] 214 | pub fn set_bit(self) -> &'a mut W { 215 | self.bit(true) 216 | } 217 | #[doc = r"Clears the field bit"] 218 | #[inline(always)] 219 | pub fn clear_bit(self) -> &'a mut W { 220 | self.bit(false) 221 | } 222 | #[doc = r"Writes raw bits to the field"] 223 | #[inline(always)] 224 | pub fn bit(self, value: bool) -> &'a mut W { 225 | self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); 226 | self.w 227 | } 228 | } 229 | #[doc = "Reader of field `INRQ`"] 230 | pub type INRQ_R = crate::R; 231 | #[doc = "Write proxy for field `INRQ`"] 232 | pub struct INRQ_W<'a> { 233 | w: &'a mut W, 234 | } 235 | impl<'a> INRQ_W<'a> { 236 | #[doc = r"Sets the field bit"] 237 | #[inline(always)] 238 | pub fn set_bit(self) -> &'a mut W { 239 | self.bit(true) 240 | } 241 | #[doc = r"Clears the field bit"] 242 | #[inline(always)] 243 | pub fn clear_bit(self) -> &'a mut W { 244 | self.bit(false) 245 | } 246 | #[doc = r"Writes raw bits to the field"] 247 | #[inline(always)] 248 | pub fn bit(self, value: bool) -> &'a mut W { 249 | self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); 250 | self.w 251 | } 252 | } 253 | impl R { 254 | #[doc = "Bit 16 - DBF"] 255 | #[inline(always)] 256 | pub fn dbf(&self) -> DBF_R { 257 | DBF_R::new(((self.bits >> 16) & 0x01) != 0) 258 | } 259 | #[doc = "Bit 15 - RESET"] 260 | #[inline(always)] 261 | pub fn reset(&self) -> RESET_R { 262 | RESET_R::new(((self.bits >> 15) & 0x01) != 0) 263 | } 264 | #[doc = "Bit 7 - TTCM"] 265 | #[inline(always)] 266 | pub fn ttcm(&self) -> TTCM_R { 267 | TTCM_R::new(((self.bits >> 7) & 0x01) != 0) 268 | } 269 | #[doc = "Bit 6 - ABOM"] 270 | #[inline(always)] 271 | pub fn abom(&self) -> ABOM_R { 272 | ABOM_R::new(((self.bits >> 6) & 0x01) != 0) 273 | } 274 | #[doc = "Bit 5 - AWUM"] 275 | #[inline(always)] 276 | pub fn awum(&self) -> AWUM_R { 277 | AWUM_R::new(((self.bits >> 5) & 0x01) != 0) 278 | } 279 | #[doc = "Bit 4 - NART"] 280 | #[inline(always)] 281 | pub fn nart(&self) -> NART_R { 282 | NART_R::new(((self.bits >> 4) & 0x01) != 0) 283 | } 284 | #[doc = "Bit 3 - RFLM"] 285 | #[inline(always)] 286 | pub fn rflm(&self) -> RFLM_R { 287 | RFLM_R::new(((self.bits >> 3) & 0x01) != 0) 288 | } 289 | #[doc = "Bit 2 - TXFP"] 290 | #[inline(always)] 291 | pub fn txfp(&self) -> TXFP_R { 292 | TXFP_R::new(((self.bits >> 2) & 0x01) != 0) 293 | } 294 | #[doc = "Bit 1 - SLEEP"] 295 | #[inline(always)] 296 | pub fn sleep(&self) -> SLEEP_R { 297 | SLEEP_R::new(((self.bits >> 1) & 0x01) != 0) 298 | } 299 | #[doc = "Bit 0 - INRQ"] 300 | #[inline(always)] 301 | pub fn inrq(&self) -> INRQ_R { 302 | INRQ_R::new((self.bits & 0x01) != 0) 303 | } 304 | } 305 | impl W { 306 | #[doc = "Bit 16 - DBF"] 307 | #[inline(always)] 308 | pub fn dbf(&mut self) -> DBF_W { 309 | DBF_W { w: self } 310 | } 311 | #[doc = "Bit 15 - RESET"] 312 | #[inline(always)] 313 | pub fn reset(&mut self) -> RESET_W { 314 | RESET_W { w: self } 315 | } 316 | #[doc = "Bit 7 - TTCM"] 317 | #[inline(always)] 318 | pub fn ttcm(&mut self) -> TTCM_W { 319 | TTCM_W { w: self } 320 | } 321 | #[doc = "Bit 6 - ABOM"] 322 | #[inline(always)] 323 | pub fn abom(&mut self) -> ABOM_W { 324 | ABOM_W { w: self } 325 | } 326 | #[doc = "Bit 5 - AWUM"] 327 | #[inline(always)] 328 | pub fn awum(&mut self) -> AWUM_W { 329 | AWUM_W { w: self } 330 | } 331 | #[doc = "Bit 4 - NART"] 332 | #[inline(always)] 333 | pub fn nart(&mut self) -> NART_W { 334 | NART_W { w: self } 335 | } 336 | #[doc = "Bit 3 - RFLM"] 337 | #[inline(always)] 338 | pub fn rflm(&mut self) -> RFLM_W { 339 | RFLM_W { w: self } 340 | } 341 | #[doc = "Bit 2 - TXFP"] 342 | #[inline(always)] 343 | pub fn txfp(&mut self) -> TXFP_W { 344 | TXFP_W { w: self } 345 | } 346 | #[doc = "Bit 1 - SLEEP"] 347 | #[inline(always)] 348 | pub fn sleep(&mut self) -> SLEEP_W { 349 | SLEEP_W { w: self } 350 | } 351 | #[doc = "Bit 0 - INRQ"] 352 | #[inline(always)] 353 | pub fn inrq(&mut self) -> INRQ_W { 354 | INRQ_W { w: self } 355 | } 356 | } 357 | -------------------------------------------------------------------------------- /src/pac/can/msr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register MSR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register MSR"] 4 | pub type W = crate::W; 5 | #[doc = "Register MSR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::MSR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `RX`"] 14 | pub type RX_R = crate::R; 15 | #[doc = "Reader of field `SAMP`"] 16 | pub type SAMP_R = crate::R; 17 | #[doc = "Reader of field `RXM`"] 18 | pub type RXM_R = crate::R; 19 | #[doc = "Reader of field `TXM`"] 20 | pub type TXM_R = crate::R; 21 | #[doc = "Reader of field `SLAKI`"] 22 | pub type SLAKI_R = crate::R; 23 | #[doc = "Write proxy for field `SLAKI`"] 24 | pub struct SLAKI_W<'a> { 25 | w: &'a mut W, 26 | } 27 | impl<'a> SLAKI_W<'a> { 28 | #[doc = r"Sets the field bit"] 29 | #[inline(always)] 30 | pub fn set_bit(self) -> &'a mut W { 31 | self.bit(true) 32 | } 33 | #[doc = r"Clears the field bit"] 34 | #[inline(always)] 35 | pub fn clear_bit(self) -> &'a mut W { 36 | self.bit(false) 37 | } 38 | #[doc = r"Writes raw bits to the field"] 39 | #[inline(always)] 40 | pub fn bit(self, value: bool) -> &'a mut W { 41 | self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); 42 | self.w 43 | } 44 | } 45 | #[doc = "Reader of field `WKUI`"] 46 | pub type WKUI_R = crate::R; 47 | #[doc = "Write proxy for field `WKUI`"] 48 | pub struct WKUI_W<'a> { 49 | w: &'a mut W, 50 | } 51 | impl<'a> WKUI_W<'a> { 52 | #[doc = r"Sets the field bit"] 53 | #[inline(always)] 54 | pub fn set_bit(self) -> &'a mut W { 55 | self.bit(true) 56 | } 57 | #[doc = r"Clears the field bit"] 58 | #[inline(always)] 59 | pub fn clear_bit(self) -> &'a mut W { 60 | self.bit(false) 61 | } 62 | #[doc = r"Writes raw bits to the field"] 63 | #[inline(always)] 64 | pub fn bit(self, value: bool) -> &'a mut W { 65 | self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); 66 | self.w 67 | } 68 | } 69 | #[doc = "Reader of field `ERRI`"] 70 | pub type ERRI_R = crate::R; 71 | #[doc = "Write proxy for field `ERRI`"] 72 | pub struct ERRI_W<'a> { 73 | w: &'a mut W, 74 | } 75 | impl<'a> ERRI_W<'a> { 76 | #[doc = r"Sets the field bit"] 77 | #[inline(always)] 78 | pub fn set_bit(self) -> &'a mut W { 79 | self.bit(true) 80 | } 81 | #[doc = r"Clears the field bit"] 82 | #[inline(always)] 83 | pub fn clear_bit(self) -> &'a mut W { 84 | self.bit(false) 85 | } 86 | #[doc = r"Writes raw bits to the field"] 87 | #[inline(always)] 88 | pub fn bit(self, value: bool) -> &'a mut W { 89 | self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); 90 | self.w 91 | } 92 | } 93 | #[doc = "Reader of field `SLAK`"] 94 | pub type SLAK_R = crate::R; 95 | #[doc = "Reader of field `INAK`"] 96 | pub type INAK_R = crate::R; 97 | impl R { 98 | #[doc = "Bit 11 - RX"] 99 | #[inline(always)] 100 | pub fn rx(&self) -> RX_R { 101 | RX_R::new(((self.bits >> 11) & 0x01) != 0) 102 | } 103 | #[doc = "Bit 10 - SAMP"] 104 | #[inline(always)] 105 | pub fn samp(&self) -> SAMP_R { 106 | SAMP_R::new(((self.bits >> 10) & 0x01) != 0) 107 | } 108 | #[doc = "Bit 9 - RXM"] 109 | #[inline(always)] 110 | pub fn rxm(&self) -> RXM_R { 111 | RXM_R::new(((self.bits >> 9) & 0x01) != 0) 112 | } 113 | #[doc = "Bit 8 - TXM"] 114 | #[inline(always)] 115 | pub fn txm(&self) -> TXM_R { 116 | TXM_R::new(((self.bits >> 8) & 0x01) != 0) 117 | } 118 | #[doc = "Bit 4 - SLAKI"] 119 | #[inline(always)] 120 | pub fn slaki(&self) -> SLAKI_R { 121 | SLAKI_R::new(((self.bits >> 4) & 0x01) != 0) 122 | } 123 | #[doc = "Bit 3 - WKUI"] 124 | #[inline(always)] 125 | pub fn wkui(&self) -> WKUI_R { 126 | WKUI_R::new(((self.bits >> 3) & 0x01) != 0) 127 | } 128 | #[doc = "Bit 2 - ERRI"] 129 | #[inline(always)] 130 | pub fn erri(&self) -> ERRI_R { 131 | ERRI_R::new(((self.bits >> 2) & 0x01) != 0) 132 | } 133 | #[doc = "Bit 1 - SLAK"] 134 | #[inline(always)] 135 | pub fn slak(&self) -> SLAK_R { 136 | SLAK_R::new(((self.bits >> 1) & 0x01) != 0) 137 | } 138 | #[doc = "Bit 0 - INAK"] 139 | #[inline(always)] 140 | pub fn inak(&self) -> INAK_R { 141 | INAK_R::new((self.bits & 0x01) != 0) 142 | } 143 | } 144 | impl W { 145 | #[doc = "Bit 4 - SLAKI"] 146 | #[inline(always)] 147 | pub fn slaki(&mut self) -> SLAKI_W { 148 | SLAKI_W { w: self } 149 | } 150 | #[doc = "Bit 3 - WKUI"] 151 | #[inline(always)] 152 | pub fn wkui(&mut self) -> WKUI_W { 153 | WKUI_W { w: self } 154 | } 155 | #[doc = "Bit 2 - ERRI"] 156 | #[inline(always)] 157 | pub fn erri(&mut self) -> ERRI_W { 158 | ERRI_W { w: self } 159 | } 160 | } 161 | -------------------------------------------------------------------------------- /src/pac/can/rfr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register RF%sR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register RF%sR"] 4 | pub type W = crate::W; 5 | #[doc = "Register RF%sR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::RFR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "RFOM0\n\nValue on reset: 0"] 14 | #[derive(Clone, Copy, Debug, PartialEq)] 15 | pub enum RFOM_A { 16 | #[doc = "1: Set by software to release the output mailbox of the FIFO"] 17 | RELEASE = 1, 18 | } 19 | impl From for bool { 20 | #[inline(always)] 21 | fn from(variant: RFOM_A) -> Self { 22 | variant as u8 != 0 23 | } 24 | } 25 | #[doc = "Reader of field `RFOM`"] 26 | pub type RFOM_R = crate::R; 27 | impl RFOM_R { 28 | #[doc = r"Get enumerated values variant"] 29 | #[inline(always)] 30 | pub fn variant(&self) -> crate::Variant { 31 | use crate::Variant::*; 32 | match self.bits { 33 | true => Val(RFOM_A::RELEASE), 34 | i => Res(i), 35 | } 36 | } 37 | #[doc = "Checks if the value of the field is `RELEASE`"] 38 | #[inline(always)] 39 | pub fn is_release(&self) -> bool { 40 | *self == RFOM_A::RELEASE 41 | } 42 | } 43 | #[doc = "Write proxy for field `RFOM`"] 44 | pub struct RFOM_W<'a> { 45 | w: &'a mut W, 46 | } 47 | impl<'a> RFOM_W<'a> { 48 | #[doc = r"Writes `variant` to the field"] 49 | #[inline(always)] 50 | pub fn variant(self, variant: RFOM_A) -> &'a mut W { 51 | { 52 | self.bit(variant.into()) 53 | } 54 | } 55 | #[doc = "Set by software to release the output mailbox of the FIFO"] 56 | #[inline(always)] 57 | pub fn release(self) -> &'a mut W { 58 | self.variant(RFOM_A::RELEASE) 59 | } 60 | #[doc = r"Sets the field bit"] 61 | #[inline(always)] 62 | pub fn set_bit(self) -> &'a mut W { 63 | self.bit(true) 64 | } 65 | #[doc = r"Clears the field bit"] 66 | #[inline(always)] 67 | pub fn clear_bit(self) -> &'a mut W { 68 | self.bit(false) 69 | } 70 | #[doc = r"Writes raw bits to the field"] 71 | #[inline(always)] 72 | pub fn bit(self, value: bool) -> &'a mut W { 73 | self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); 74 | self.w 75 | } 76 | } 77 | #[doc = "FOVR0\n\nValue on reset: 0"] 78 | #[derive(Clone, Copy, Debug, PartialEq)] 79 | pub enum FOVR_A { 80 | #[doc = "0: No FIFO x overrun"] 81 | NOOVERRUN = 0, 82 | #[doc = "1: FIFO x overrun"] 83 | OVERRUN = 1, 84 | } 85 | impl From for bool { 86 | #[inline(always)] 87 | fn from(variant: FOVR_A) -> Self { 88 | variant as u8 != 0 89 | } 90 | } 91 | #[doc = "Reader of field `FOVR`"] 92 | pub type FOVR_R = crate::R; 93 | impl FOVR_R { 94 | #[doc = r"Get enumerated values variant"] 95 | #[inline(always)] 96 | pub fn variant(&self) -> FOVR_A { 97 | match self.bits { 98 | false => FOVR_A::NOOVERRUN, 99 | true => FOVR_A::OVERRUN, 100 | } 101 | } 102 | #[doc = "Checks if the value of the field is `NOOVERRUN`"] 103 | #[inline(always)] 104 | pub fn is_no_overrun(&self) -> bool { 105 | *self == FOVR_A::NOOVERRUN 106 | } 107 | #[doc = "Checks if the value of the field is `OVERRUN`"] 108 | #[inline(always)] 109 | pub fn is_overrun(&self) -> bool { 110 | *self == FOVR_A::OVERRUN 111 | } 112 | } 113 | #[doc = "FOVR0\n\nValue on reset: 0"] 114 | #[derive(Clone, Copy, Debug, PartialEq)] 115 | pub enum FOVR_AW { 116 | #[doc = "1: Clear flag"] 117 | CLEAR = 1, 118 | } 119 | impl From for bool { 120 | #[inline(always)] 121 | fn from(variant: FOVR_AW) -> Self { 122 | variant as u8 != 0 123 | } 124 | } 125 | #[doc = "Write proxy for field `FOVR`"] 126 | pub struct FOVR_W<'a> { 127 | w: &'a mut W, 128 | } 129 | impl<'a> FOVR_W<'a> { 130 | #[doc = r"Writes `variant` to the field"] 131 | #[inline(always)] 132 | pub fn variant(self, variant: FOVR_AW) -> &'a mut W { 133 | { 134 | self.bit(variant.into()) 135 | } 136 | } 137 | #[doc = "Clear flag"] 138 | #[inline(always)] 139 | pub fn clear(self) -> &'a mut W { 140 | self.variant(FOVR_AW::CLEAR) 141 | } 142 | #[doc = r"Sets the field bit"] 143 | #[inline(always)] 144 | pub fn set_bit(self) -> &'a mut W { 145 | self.bit(true) 146 | } 147 | #[doc = r"Clears the field bit"] 148 | #[inline(always)] 149 | pub fn clear_bit(self) -> &'a mut W { 150 | self.bit(false) 151 | } 152 | #[doc = r"Writes raw bits to the field"] 153 | #[inline(always)] 154 | pub fn bit(self, value: bool) -> &'a mut W { 155 | self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); 156 | self.w 157 | } 158 | } 159 | #[doc = "FULL0\n\nValue on reset: 0"] 160 | #[derive(Clone, Copy, Debug, PartialEq)] 161 | pub enum FULL_A { 162 | #[doc = "0: FIFO x is not full"] 163 | NOTFULL = 0, 164 | #[doc = "1: FIFO x is full"] 165 | FULL = 1, 166 | } 167 | impl From for bool { 168 | #[inline(always)] 169 | fn from(variant: FULL_A) -> Self { 170 | variant as u8 != 0 171 | } 172 | } 173 | #[doc = "Reader of field `FULL`"] 174 | pub type FULL_R = crate::R; 175 | impl FULL_R { 176 | #[doc = r"Get enumerated values variant"] 177 | #[inline(always)] 178 | pub fn variant(&self) -> FULL_A { 179 | match self.bits { 180 | false => FULL_A::NOTFULL, 181 | true => FULL_A::FULL, 182 | } 183 | } 184 | #[doc = "Checks if the value of the field is `NOTFULL`"] 185 | #[inline(always)] 186 | pub fn is_not_full(&self) -> bool { 187 | *self == FULL_A::NOTFULL 188 | } 189 | #[doc = "Checks if the value of the field is `FULL`"] 190 | #[inline(always)] 191 | pub fn is_full(&self) -> bool { 192 | *self == FULL_A::FULL 193 | } 194 | } 195 | #[doc = "FULL0\n\nValue on reset: 0"] 196 | #[derive(Clone, Copy, Debug, PartialEq)] 197 | pub enum FULL_AW { 198 | #[doc = "1: Clear flag"] 199 | CLEAR = 1, 200 | } 201 | impl From for bool { 202 | #[inline(always)] 203 | fn from(variant: FULL_AW) -> Self { 204 | variant as u8 != 0 205 | } 206 | } 207 | #[doc = "Write proxy for field `FULL`"] 208 | pub struct FULL_W<'a> { 209 | w: &'a mut W, 210 | } 211 | impl<'a> FULL_W<'a> { 212 | #[doc = r"Writes `variant` to the field"] 213 | #[inline(always)] 214 | pub fn variant(self, variant: FULL_AW) -> &'a mut W { 215 | { 216 | self.bit(variant.into()) 217 | } 218 | } 219 | #[doc = "Clear flag"] 220 | #[inline(always)] 221 | pub fn clear(self) -> &'a mut W { 222 | self.variant(FULL_AW::CLEAR) 223 | } 224 | #[doc = r"Sets the field bit"] 225 | #[inline(always)] 226 | pub fn set_bit(self) -> &'a mut W { 227 | self.bit(true) 228 | } 229 | #[doc = r"Clears the field bit"] 230 | #[inline(always)] 231 | pub fn clear_bit(self) -> &'a mut W { 232 | self.bit(false) 233 | } 234 | #[doc = r"Writes raw bits to the field"] 235 | #[inline(always)] 236 | pub fn bit(self, value: bool) -> &'a mut W { 237 | self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); 238 | self.w 239 | } 240 | } 241 | #[doc = "Reader of field `FMP`"] 242 | pub type FMP_R = crate::R; 243 | impl R { 244 | #[doc = "Bit 5 - RFOM0"] 245 | #[inline(always)] 246 | pub fn rfom(&self) -> RFOM_R { 247 | RFOM_R::new(((self.bits >> 5) & 0x01) != 0) 248 | } 249 | #[doc = "Bit 4 - FOVR0"] 250 | #[inline(always)] 251 | pub fn fovr(&self) -> FOVR_R { 252 | FOVR_R::new(((self.bits >> 4) & 0x01) != 0) 253 | } 254 | #[doc = "Bit 3 - FULL0"] 255 | #[inline(always)] 256 | pub fn full(&self) -> FULL_R { 257 | FULL_R::new(((self.bits >> 3) & 0x01) != 0) 258 | } 259 | #[doc = "Bits 0:1 - FMP0"] 260 | #[inline(always)] 261 | pub fn fmp(&self) -> FMP_R { 262 | FMP_R::new((self.bits & 0x03) as u8) 263 | } 264 | } 265 | impl W { 266 | #[doc = "Bit 5 - RFOM0"] 267 | #[inline(always)] 268 | pub fn rfom(&mut self) -> RFOM_W { 269 | RFOM_W { w: self } 270 | } 271 | #[doc = "Bit 4 - FOVR0"] 272 | #[inline(always)] 273 | pub fn fovr(&mut self) -> FOVR_W { 274 | FOVR_W { w: self } 275 | } 276 | #[doc = "Bit 3 - FULL0"] 277 | #[inline(always)] 278 | pub fn full(&mut self) -> FULL_W { 279 | FULL_W { w: self } 280 | } 281 | } 282 | -------------------------------------------------------------------------------- /src/pac/can/rx.rs: -------------------------------------------------------------------------------- 1 | #[doc = "CAN_RI0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rir](rir) module"] 2 | pub type RIR = crate::Reg; 3 | #[allow(missing_docs)] 4 | #[doc(hidden)] 5 | pub struct _RIR; 6 | #[doc = "`read()` method returns [rir::R](rir::R) reader structure"] 7 | impl crate::Readable for RIR {} 8 | #[doc = "CAN_RI0R"] 9 | pub mod rir; 10 | #[doc = "CAN_RDT0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdtr](rdtr) module"] 11 | pub type RDTR = crate::Reg; 12 | #[allow(missing_docs)] 13 | #[doc(hidden)] 14 | pub struct _RDTR; 15 | #[doc = "`read()` method returns [rdtr::R](rdtr::R) reader structure"] 16 | impl crate::Readable for RDTR {} 17 | #[doc = "CAN_RDT0R"] 18 | pub mod rdtr; 19 | #[doc = "CAN_RDL0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdlr](rdlr) module"] 20 | pub type RDLR = crate::Reg; 21 | #[allow(missing_docs)] 22 | #[doc(hidden)] 23 | pub struct _RDLR; 24 | #[doc = "`read()` method returns [rdlr::R](rdlr::R) reader structure"] 25 | impl crate::Readable for RDLR {} 26 | #[doc = "CAN_RDL0R"] 27 | pub mod rdlr; 28 | #[doc = "CAN_RDH0R\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdhr](rdhr) module"] 29 | pub type RDHR = crate::Reg; 30 | #[allow(missing_docs)] 31 | #[doc(hidden)] 32 | pub struct _RDHR; 33 | #[doc = "`read()` method returns [rdhr::R](rdhr::R) reader structure"] 34 | impl crate::Readable for RDHR {} 35 | #[doc = "CAN_RDH0R"] 36 | pub mod rdhr; 37 | -------------------------------------------------------------------------------- /src/pac/can/rx/rdhr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register RDHR"] 2 | pub type R = crate::R; 3 | #[doc = "Reader of field `DATA7`"] 4 | pub type DATA7_R = crate::R; 5 | #[doc = "Reader of field `DATA6`"] 6 | pub type DATA6_R = crate::R; 7 | #[doc = "Reader of field `DATA5`"] 8 | pub type DATA5_R = crate::R; 9 | #[doc = "Reader of field `DATA4`"] 10 | pub type DATA4_R = crate::R; 11 | impl R { 12 | #[doc = "Bits 24:31 - DATA7"] 13 | #[inline(always)] 14 | pub fn data7(&self) -> DATA7_R { 15 | DATA7_R::new(((self.bits >> 24) & 0xff) as u8) 16 | } 17 | #[doc = "Bits 16:23 - DATA6"] 18 | #[inline(always)] 19 | pub fn data6(&self) -> DATA6_R { 20 | DATA6_R::new(((self.bits >> 16) & 0xff) as u8) 21 | } 22 | #[doc = "Bits 8:15 - DATA5"] 23 | #[inline(always)] 24 | pub fn data5(&self) -> DATA5_R { 25 | DATA5_R::new(((self.bits >> 8) & 0xff) as u8) 26 | } 27 | #[doc = "Bits 0:7 - DATA4"] 28 | #[inline(always)] 29 | pub fn data4(&self) -> DATA4_R { 30 | DATA4_R::new((self.bits & 0xff) as u8) 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /src/pac/can/rx/rdlr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register RDLR"] 2 | pub type R = crate::R; 3 | #[doc = "Reader of field `DATA3`"] 4 | pub type DATA3_R = crate::R; 5 | #[doc = "Reader of field `DATA2`"] 6 | pub type DATA2_R = crate::R; 7 | #[doc = "Reader of field `DATA1`"] 8 | pub type DATA1_R = crate::R; 9 | #[doc = "Reader of field `DATA0`"] 10 | pub type DATA0_R = crate::R; 11 | impl R { 12 | #[doc = "Bits 24:31 - DATA3"] 13 | #[inline(always)] 14 | pub fn data3(&self) -> DATA3_R { 15 | DATA3_R::new(((self.bits >> 24) & 0xff) as u8) 16 | } 17 | #[doc = "Bits 16:23 - DATA2"] 18 | #[inline(always)] 19 | pub fn data2(&self) -> DATA2_R { 20 | DATA2_R::new(((self.bits >> 16) & 0xff) as u8) 21 | } 22 | #[doc = "Bits 8:15 - DATA1"] 23 | #[inline(always)] 24 | pub fn data1(&self) -> DATA1_R { 25 | DATA1_R::new(((self.bits >> 8) & 0xff) as u8) 26 | } 27 | #[doc = "Bits 0:7 - DATA0"] 28 | #[inline(always)] 29 | pub fn data0(&self) -> DATA0_R { 30 | DATA0_R::new((self.bits & 0xff) as u8) 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /src/pac/can/rx/rdtr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register RDTR"] 2 | pub type R = crate::R; 3 | #[doc = "Reader of field `TIME`"] 4 | pub type TIME_R = crate::R; 5 | #[doc = "Reader of field `FMI`"] 6 | pub type FMI_R = crate::R; 7 | #[doc = "Reader of field `DLC`"] 8 | pub type DLC_R = crate::R; 9 | impl R { 10 | #[doc = "Bits 16:31 - TIME"] 11 | #[inline(always)] 12 | pub fn time(&self) -> TIME_R { 13 | TIME_R::new(((self.bits >> 16) & 0xffff) as u16) 14 | } 15 | #[doc = "Bits 8:15 - FMI"] 16 | #[inline(always)] 17 | pub fn fmi(&self) -> FMI_R { 18 | FMI_R::new(((self.bits >> 8) & 0xff) as u8) 19 | } 20 | #[doc = "Bits 0:3 - DLC"] 21 | #[inline(always)] 22 | pub fn dlc(&self) -> DLC_R { 23 | DLC_R::new((self.bits & 0x0f) as u8) 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /src/pac/can/rx/rir.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register RIR"] 2 | pub type R = crate::R; 3 | #[doc = "Reader of field `STID`"] 4 | pub type STID_R = crate::R; 5 | #[doc = "Reader of field `EXID`"] 6 | pub type EXID_R = crate::R; 7 | #[doc = "IDE\n\nValue on reset: 0"] 8 | #[derive(Clone, Copy, Debug, PartialEq)] 9 | pub enum IDE_A { 10 | #[doc = "0: Standard identifier"] 11 | STANDARD = 0, 12 | #[doc = "1: Extended identifier"] 13 | EXTENDED = 1, 14 | } 15 | impl From for bool { 16 | #[inline(always)] 17 | fn from(variant: IDE_A) -> Self { 18 | variant as u8 != 0 19 | } 20 | } 21 | #[doc = "Reader of field `IDE`"] 22 | pub type IDE_R = crate::R; 23 | impl IDE_R { 24 | #[doc = r"Get enumerated values variant"] 25 | #[inline(always)] 26 | pub fn variant(&self) -> IDE_A { 27 | match self.bits { 28 | false => IDE_A::STANDARD, 29 | true => IDE_A::EXTENDED, 30 | } 31 | } 32 | #[doc = "Checks if the value of the field is `STANDARD`"] 33 | #[inline(always)] 34 | pub fn is_standard(&self) -> bool { 35 | *self == IDE_A::STANDARD 36 | } 37 | #[doc = "Checks if the value of the field is `EXTENDED`"] 38 | #[inline(always)] 39 | pub fn is_extended(&self) -> bool { 40 | *self == IDE_A::EXTENDED 41 | } 42 | } 43 | #[doc = "RTR\n\nValue on reset: 0"] 44 | #[derive(Clone, Copy, Debug, PartialEq)] 45 | pub enum RTR_A { 46 | #[doc = "0: Data frame"] 47 | DATA = 0, 48 | #[doc = "1: Remote frame"] 49 | REMOTE = 1, 50 | } 51 | impl From for bool { 52 | #[inline(always)] 53 | fn from(variant: RTR_A) -> Self { 54 | variant as u8 != 0 55 | } 56 | } 57 | #[doc = "Reader of field `RTR`"] 58 | pub type RTR_R = crate::R; 59 | impl RTR_R { 60 | #[doc = r"Get enumerated values variant"] 61 | #[inline(always)] 62 | pub fn variant(&self) -> RTR_A { 63 | match self.bits { 64 | false => RTR_A::DATA, 65 | true => RTR_A::REMOTE, 66 | } 67 | } 68 | #[doc = "Checks if the value of the field is `DATA`"] 69 | #[inline(always)] 70 | pub fn is_data(&self) -> bool { 71 | *self == RTR_A::DATA 72 | } 73 | #[doc = "Checks if the value of the field is `REMOTE`"] 74 | #[inline(always)] 75 | pub fn is_remote(&self) -> bool { 76 | *self == RTR_A::REMOTE 77 | } 78 | } 79 | impl R { 80 | #[doc = "Bits 21:31 - STID"] 81 | #[inline(always)] 82 | pub fn stid(&self) -> STID_R { 83 | STID_R::new(((self.bits >> 21) & 0x07ff) as u16) 84 | } 85 | #[doc = "Bits 3:20 - EXID"] 86 | #[inline(always)] 87 | pub fn exid(&self) -> EXID_R { 88 | EXID_R::new(((self.bits >> 3) & 0x0003_ffff) as u32) 89 | } 90 | #[doc = "Bit 2 - IDE"] 91 | #[inline(always)] 92 | pub fn ide(&self) -> IDE_R { 93 | IDE_R::new(((self.bits >> 2) & 0x01) != 0) 94 | } 95 | #[doc = "Bit 1 - RTR"] 96 | #[inline(always)] 97 | pub fn rtr(&self) -> RTR_R { 98 | RTR_R::new(((self.bits >> 1) & 0x01) != 0) 99 | } 100 | } 101 | -------------------------------------------------------------------------------- /src/pac/can/tx.rs: -------------------------------------------------------------------------------- 1 | #[doc = "CAN_TI0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tir](tir) module"] 2 | pub type TIR = crate::Reg; 3 | #[allow(missing_docs)] 4 | #[doc(hidden)] 5 | pub struct _TIR; 6 | #[doc = "`read()` method returns [tir::R](tir::R) reader structure"] 7 | impl crate::Readable for TIR {} 8 | #[doc = "`write(|w| ..)` method takes [tir::W](tir::W) writer structure"] 9 | impl crate::Writable for TIR {} 10 | #[doc = "CAN_TI0R"] 11 | pub mod tir; 12 | #[doc = "CAN_TDT0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdtr](tdtr) module"] 13 | pub type TDTR = crate::Reg; 14 | #[allow(missing_docs)] 15 | #[doc(hidden)] 16 | pub struct _TDTR; 17 | #[doc = "`read()` method returns [tdtr::R](tdtr::R) reader structure"] 18 | impl crate::Readable for TDTR {} 19 | #[doc = "`write(|w| ..)` method takes [tdtr::W](tdtr::W) writer structure"] 20 | impl crate::Writable for TDTR {} 21 | #[doc = "CAN_TDT0R"] 22 | pub mod tdtr; 23 | #[doc = "CAN_TDL0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdlr](tdlr) module"] 24 | pub type TDLR = crate::Reg; 25 | #[allow(missing_docs)] 26 | #[doc(hidden)] 27 | pub struct _TDLR; 28 | #[doc = "`read()` method returns [tdlr::R](tdlr::R) reader structure"] 29 | impl crate::Readable for TDLR {} 30 | #[doc = "`write(|w| ..)` method takes [tdlr::W](tdlr::W) writer structure"] 31 | impl crate::Writable for TDLR {} 32 | #[doc = "CAN_TDL0R"] 33 | pub mod tdlr; 34 | #[doc = "CAN_TDH0R\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdhr](tdhr) module"] 35 | pub type TDHR = crate::Reg; 36 | #[allow(missing_docs)] 37 | #[doc(hidden)] 38 | pub struct _TDHR; 39 | #[doc = "`read()` method returns [tdhr::R](tdhr::R) reader structure"] 40 | impl crate::Readable for TDHR {} 41 | #[doc = "`write(|w| ..)` method takes [tdhr::W](tdhr::W) writer structure"] 42 | impl crate::Writable for TDHR {} 43 | #[doc = "CAN_TDH0R"] 44 | pub mod tdhr; 45 | -------------------------------------------------------------------------------- /src/pac/can/tx/tdhr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register TDHR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register TDHR"] 4 | pub type W = crate::W; 5 | #[doc = "Register TDHR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::TDHR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `DATA7`"] 14 | pub type DATA7_R = crate::R; 15 | #[doc = "Write proxy for field `DATA7`"] 16 | pub struct DATA7_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> DATA7_W<'a> { 20 | #[doc = r"Writes raw bits to the field"] 21 | #[inline(always)] 22 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 23 | self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); 24 | self.w 25 | } 26 | } 27 | #[doc = "Reader of field `DATA6`"] 28 | pub type DATA6_R = crate::R; 29 | #[doc = "Write proxy for field `DATA6`"] 30 | pub struct DATA6_W<'a> { 31 | w: &'a mut W, 32 | } 33 | impl<'a> DATA6_W<'a> { 34 | #[doc = r"Writes raw bits to the field"] 35 | #[inline(always)] 36 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 37 | self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); 38 | self.w 39 | } 40 | } 41 | #[doc = "Reader of field `DATA5`"] 42 | pub type DATA5_R = crate::R; 43 | #[doc = "Write proxy for field `DATA5`"] 44 | pub struct DATA5_W<'a> { 45 | w: &'a mut W, 46 | } 47 | impl<'a> DATA5_W<'a> { 48 | #[doc = r"Writes raw bits to the field"] 49 | #[inline(always)] 50 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 51 | self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); 52 | self.w 53 | } 54 | } 55 | #[doc = "Reader of field `DATA4`"] 56 | pub type DATA4_R = crate::R; 57 | #[doc = "Write proxy for field `DATA4`"] 58 | pub struct DATA4_W<'a> { 59 | w: &'a mut W, 60 | } 61 | impl<'a> DATA4_W<'a> { 62 | #[doc = r"Writes raw bits to the field"] 63 | #[inline(always)] 64 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 65 | self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); 66 | self.w 67 | } 68 | } 69 | impl R { 70 | #[doc = "Bits 24:31 - DATA7"] 71 | #[inline(always)] 72 | pub fn data7(&self) -> DATA7_R { 73 | DATA7_R::new(((self.bits >> 24) & 0xff) as u8) 74 | } 75 | #[doc = "Bits 16:23 - DATA6"] 76 | #[inline(always)] 77 | pub fn data6(&self) -> DATA6_R { 78 | DATA6_R::new(((self.bits >> 16) & 0xff) as u8) 79 | } 80 | #[doc = "Bits 8:15 - DATA5"] 81 | #[inline(always)] 82 | pub fn data5(&self) -> DATA5_R { 83 | DATA5_R::new(((self.bits >> 8) & 0xff) as u8) 84 | } 85 | #[doc = "Bits 0:7 - DATA4"] 86 | #[inline(always)] 87 | pub fn data4(&self) -> DATA4_R { 88 | DATA4_R::new((self.bits & 0xff) as u8) 89 | } 90 | } 91 | impl W { 92 | #[doc = "Bits 24:31 - DATA7"] 93 | #[inline(always)] 94 | pub fn data7(&mut self) -> DATA7_W { 95 | DATA7_W { w: self } 96 | } 97 | #[doc = "Bits 16:23 - DATA6"] 98 | #[inline(always)] 99 | pub fn data6(&mut self) -> DATA6_W { 100 | DATA6_W { w: self } 101 | } 102 | #[doc = "Bits 8:15 - DATA5"] 103 | #[inline(always)] 104 | pub fn data5(&mut self) -> DATA5_W { 105 | DATA5_W { w: self } 106 | } 107 | #[doc = "Bits 0:7 - DATA4"] 108 | #[inline(always)] 109 | pub fn data4(&mut self) -> DATA4_W { 110 | DATA4_W { w: self } 111 | } 112 | } 113 | -------------------------------------------------------------------------------- /src/pac/can/tx/tdlr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register TDLR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register TDLR"] 4 | pub type W = crate::W; 5 | #[doc = "Register TDLR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::TDLR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `DATA3`"] 14 | pub type DATA3_R = crate::R; 15 | #[doc = "Write proxy for field `DATA3`"] 16 | pub struct DATA3_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> DATA3_W<'a> { 20 | #[doc = r"Writes raw bits to the field"] 21 | #[inline(always)] 22 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 23 | self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24); 24 | self.w 25 | } 26 | } 27 | #[doc = "Reader of field `DATA2`"] 28 | pub type DATA2_R = crate::R; 29 | #[doc = "Write proxy for field `DATA2`"] 30 | pub struct DATA2_W<'a> { 31 | w: &'a mut W, 32 | } 33 | impl<'a> DATA2_W<'a> { 34 | #[doc = r"Writes raw bits to the field"] 35 | #[inline(always)] 36 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 37 | self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); 38 | self.w 39 | } 40 | } 41 | #[doc = "Reader of field `DATA1`"] 42 | pub type DATA1_R = crate::R; 43 | #[doc = "Write proxy for field `DATA1`"] 44 | pub struct DATA1_W<'a> { 45 | w: &'a mut W, 46 | } 47 | impl<'a> DATA1_W<'a> { 48 | #[doc = r"Writes raw bits to the field"] 49 | #[inline(always)] 50 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 51 | self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); 52 | self.w 53 | } 54 | } 55 | #[doc = "Reader of field `DATA0`"] 56 | pub type DATA0_R = crate::R; 57 | #[doc = "Write proxy for field `DATA0`"] 58 | pub struct DATA0_W<'a> { 59 | w: &'a mut W, 60 | } 61 | impl<'a> DATA0_W<'a> { 62 | #[doc = r"Writes raw bits to the field"] 63 | #[inline(always)] 64 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 65 | self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); 66 | self.w 67 | } 68 | } 69 | impl R { 70 | #[doc = "Bits 24:31 - DATA3"] 71 | #[inline(always)] 72 | pub fn data3(&self) -> DATA3_R { 73 | DATA3_R::new(((self.bits >> 24) & 0xff) as u8) 74 | } 75 | #[doc = "Bits 16:23 - DATA2"] 76 | #[inline(always)] 77 | pub fn data2(&self) -> DATA2_R { 78 | DATA2_R::new(((self.bits >> 16) & 0xff) as u8) 79 | } 80 | #[doc = "Bits 8:15 - DATA1"] 81 | #[inline(always)] 82 | pub fn data1(&self) -> DATA1_R { 83 | DATA1_R::new(((self.bits >> 8) & 0xff) as u8) 84 | } 85 | #[doc = "Bits 0:7 - DATA0"] 86 | #[inline(always)] 87 | pub fn data0(&self) -> DATA0_R { 88 | DATA0_R::new((self.bits & 0xff) as u8) 89 | } 90 | } 91 | impl W { 92 | #[doc = "Bits 24:31 - DATA3"] 93 | #[inline(always)] 94 | pub fn data3(&mut self) -> DATA3_W { 95 | DATA3_W { w: self } 96 | } 97 | #[doc = "Bits 16:23 - DATA2"] 98 | #[inline(always)] 99 | pub fn data2(&mut self) -> DATA2_W { 100 | DATA2_W { w: self } 101 | } 102 | #[doc = "Bits 8:15 - DATA1"] 103 | #[inline(always)] 104 | pub fn data1(&mut self) -> DATA1_W { 105 | DATA1_W { w: self } 106 | } 107 | #[doc = "Bits 0:7 - DATA0"] 108 | #[inline(always)] 109 | pub fn data0(&mut self) -> DATA0_W { 110 | DATA0_W { w: self } 111 | } 112 | } 113 | -------------------------------------------------------------------------------- /src/pac/can/tx/tdtr.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register TDTR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register TDTR"] 4 | pub type W = crate::W; 5 | #[doc = "Register TDTR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::TDTR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `TIME`"] 14 | pub type TIME_R = crate::R; 15 | #[doc = "Write proxy for field `TIME`"] 16 | pub struct TIME_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> TIME_W<'a> { 20 | #[doc = r"Writes raw bits to the field"] 21 | #[inline(always)] 22 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 23 | self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16); 24 | self.w 25 | } 26 | } 27 | #[doc = "Reader of field `TGT`"] 28 | pub type TGT_R = crate::R; 29 | #[doc = "Write proxy for field `TGT`"] 30 | pub struct TGT_W<'a> { 31 | w: &'a mut W, 32 | } 33 | impl<'a> TGT_W<'a> { 34 | #[doc = r"Sets the field bit"] 35 | #[inline(always)] 36 | pub fn set_bit(self) -> &'a mut W { 37 | self.bit(true) 38 | } 39 | #[doc = r"Clears the field bit"] 40 | #[inline(always)] 41 | pub fn clear_bit(self) -> &'a mut W { 42 | self.bit(false) 43 | } 44 | #[doc = r"Writes raw bits to the field"] 45 | #[inline(always)] 46 | pub fn bit(self, value: bool) -> &'a mut W { 47 | self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); 48 | self.w 49 | } 50 | } 51 | #[doc = "Reader of field `DLC`"] 52 | pub type DLC_R = crate::R; 53 | #[doc = "Write proxy for field `DLC`"] 54 | pub struct DLC_W<'a> { 55 | w: &'a mut W, 56 | } 57 | impl<'a> DLC_W<'a> { 58 | #[doc = r"Writes raw bits to the field"] 59 | #[inline(always)] 60 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 61 | self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); 62 | self.w 63 | } 64 | } 65 | impl R { 66 | #[doc = "Bits 16:31 - TIME"] 67 | #[inline(always)] 68 | pub fn time(&self) -> TIME_R { 69 | TIME_R::new(((self.bits >> 16) & 0xffff) as u16) 70 | } 71 | #[doc = "Bit 8 - TGT"] 72 | #[inline(always)] 73 | pub fn tgt(&self) -> TGT_R { 74 | TGT_R::new(((self.bits >> 8) & 0x01) != 0) 75 | } 76 | #[doc = "Bits 0:3 - DLC"] 77 | #[inline(always)] 78 | pub fn dlc(&self) -> DLC_R { 79 | DLC_R::new((self.bits & 0x0f) as u8) 80 | } 81 | } 82 | impl W { 83 | #[doc = "Bits 16:31 - TIME"] 84 | #[inline(always)] 85 | pub fn time(&mut self) -> TIME_W { 86 | TIME_W { w: self } 87 | } 88 | #[doc = "Bit 8 - TGT"] 89 | #[inline(always)] 90 | pub fn tgt(&mut self) -> TGT_W { 91 | TGT_W { w: self } 92 | } 93 | #[doc = "Bits 0:3 - DLC"] 94 | #[inline(always)] 95 | pub fn dlc(&mut self) -> DLC_W { 96 | DLC_W { w: self } 97 | } 98 | } 99 | -------------------------------------------------------------------------------- /src/pac/can/tx/tir.rs: -------------------------------------------------------------------------------- 1 | #[doc = "Reader of register TIR"] 2 | pub type R = crate::R; 3 | #[doc = "Writer for register TIR"] 4 | pub type W = crate::W; 5 | #[doc = "Register TIR `reset()`'s with value 0"] 6 | impl crate::ResetValue for super::TIR { 7 | type Type = u32; 8 | #[inline(always)] 9 | fn reset_value() -> Self::Type { 10 | 0 11 | } 12 | } 13 | #[doc = "Reader of field `STID`"] 14 | pub type STID_R = crate::R; 15 | #[doc = "Write proxy for field `STID`"] 16 | pub struct STID_W<'a> { 17 | w: &'a mut W, 18 | } 19 | impl<'a> STID_W<'a> { 20 | #[doc = r"Writes raw bits to the field"] 21 | #[inline(always)] 22 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 23 | self.w.bits = (self.w.bits & !(0x07ff << 21)) | (((value as u32) & 0x07ff) << 21); 24 | self.w 25 | } 26 | } 27 | #[doc = "Reader of field `EXID`"] 28 | pub type EXID_R = crate::R; 29 | #[doc = "Write proxy for field `EXID`"] 30 | pub struct EXID_W<'a> { 31 | w: &'a mut W, 32 | } 33 | impl<'a> EXID_W<'a> { 34 | #[doc = r"Writes raw bits to the field"] 35 | #[inline(always)] 36 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 37 | self.w.bits = (self.w.bits & !(0x0003_ffff << 3)) | (((value as u32) & 0x0003_ffff) << 3); 38 | self.w 39 | } 40 | } 41 | #[doc = "IDE\n\nValue on reset: 0"] 42 | #[derive(Clone, Copy, Debug, PartialEq)] 43 | pub enum IDE_A { 44 | #[doc = "0: Standard identifier"] 45 | STANDARD = 0, 46 | #[doc = "1: Extended identifier"] 47 | EXTENDED = 1, 48 | } 49 | impl From for bool { 50 | #[inline(always)] 51 | fn from(variant: IDE_A) -> Self { 52 | variant as u8 != 0 53 | } 54 | } 55 | #[doc = "Reader of field `IDE`"] 56 | pub type IDE_R = crate::R; 57 | impl IDE_R { 58 | #[doc = r"Get enumerated values variant"] 59 | #[inline(always)] 60 | pub fn variant(&self) -> IDE_A { 61 | match self.bits { 62 | false => IDE_A::STANDARD, 63 | true => IDE_A::EXTENDED, 64 | } 65 | } 66 | #[doc = "Checks if the value of the field is `STANDARD`"] 67 | #[inline(always)] 68 | pub fn is_standard(&self) -> bool { 69 | *self == IDE_A::STANDARD 70 | } 71 | #[doc = "Checks if the value of the field is `EXTENDED`"] 72 | #[inline(always)] 73 | pub fn is_extended(&self) -> bool { 74 | *self == IDE_A::EXTENDED 75 | } 76 | } 77 | #[doc = "Write proxy for field `IDE`"] 78 | pub struct IDE_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> IDE_W<'a> { 82 | #[doc = r"Writes `variant` to the field"] 83 | #[inline(always)] 84 | pub fn variant(self, variant: IDE_A) -> &'a mut W { 85 | { 86 | self.bit(variant.into()) 87 | } 88 | } 89 | #[doc = "Standard identifier"] 90 | #[inline(always)] 91 | pub fn standard(self) -> &'a mut W { 92 | self.variant(IDE_A::STANDARD) 93 | } 94 | #[doc = "Extended identifier"] 95 | #[inline(always)] 96 | pub fn extended(self) -> &'a mut W { 97 | self.variant(IDE_A::EXTENDED) 98 | } 99 | #[doc = r"Sets the field bit"] 100 | #[inline(always)] 101 | pub fn set_bit(self) -> &'a mut W { 102 | self.bit(true) 103 | } 104 | #[doc = r"Clears the field bit"] 105 | #[inline(always)] 106 | pub fn clear_bit(self) -> &'a mut W { 107 | self.bit(false) 108 | } 109 | #[doc = r"Writes raw bits to the field"] 110 | #[inline(always)] 111 | pub fn bit(self, value: bool) -> &'a mut W { 112 | self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); 113 | self.w 114 | } 115 | } 116 | #[doc = "RTR\n\nValue on reset: 0"] 117 | #[derive(Clone, Copy, Debug, PartialEq)] 118 | pub enum RTR_A { 119 | #[doc = "0: Data frame"] 120 | DATA = 0, 121 | #[doc = "1: Remote frame"] 122 | REMOTE = 1, 123 | } 124 | impl From for bool { 125 | #[inline(always)] 126 | fn from(variant: RTR_A) -> Self { 127 | variant as u8 != 0 128 | } 129 | } 130 | #[doc = "Reader of field `RTR`"] 131 | pub type RTR_R = crate::R; 132 | impl RTR_R { 133 | #[doc = r"Get enumerated values variant"] 134 | #[inline(always)] 135 | pub fn variant(&self) -> RTR_A { 136 | match self.bits { 137 | false => RTR_A::DATA, 138 | true => RTR_A::REMOTE, 139 | } 140 | } 141 | #[doc = "Checks if the value of the field is `DATA`"] 142 | #[inline(always)] 143 | pub fn is_data(&self) -> bool { 144 | *self == RTR_A::DATA 145 | } 146 | #[doc = "Checks if the value of the field is `REMOTE`"] 147 | #[inline(always)] 148 | pub fn is_remote(&self) -> bool { 149 | *self == RTR_A::REMOTE 150 | } 151 | } 152 | #[doc = "Write proxy for field `RTR`"] 153 | pub struct RTR_W<'a> { 154 | w: &'a mut W, 155 | } 156 | impl<'a> RTR_W<'a> { 157 | #[doc = r"Writes `variant` to the field"] 158 | #[inline(always)] 159 | pub fn variant(self, variant: RTR_A) -> &'a mut W { 160 | { 161 | self.bit(variant.into()) 162 | } 163 | } 164 | #[doc = "Data frame"] 165 | #[inline(always)] 166 | pub fn data(self) -> &'a mut W { 167 | self.variant(RTR_A::DATA) 168 | } 169 | #[doc = "Remote frame"] 170 | #[inline(always)] 171 | pub fn remote(self) -> &'a mut W { 172 | self.variant(RTR_A::REMOTE) 173 | } 174 | #[doc = r"Sets the field bit"] 175 | #[inline(always)] 176 | pub fn set_bit(self) -> &'a mut W { 177 | self.bit(true) 178 | } 179 | #[doc = r"Clears the field bit"] 180 | #[inline(always)] 181 | pub fn clear_bit(self) -> &'a mut W { 182 | self.bit(false) 183 | } 184 | #[doc = r"Writes raw bits to the field"] 185 | #[inline(always)] 186 | pub fn bit(self, value: bool) -> &'a mut W { 187 | self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); 188 | self.w 189 | } 190 | } 191 | #[doc = "Reader of field `TXRQ`"] 192 | pub type TXRQ_R = crate::R; 193 | #[doc = "Write proxy for field `TXRQ`"] 194 | pub struct TXRQ_W<'a> { 195 | w: &'a mut W, 196 | } 197 | impl<'a> TXRQ_W<'a> { 198 | #[doc = r"Sets the field bit"] 199 | #[inline(always)] 200 | pub fn set_bit(self) -> &'a mut W { 201 | self.bit(true) 202 | } 203 | #[doc = r"Clears the field bit"] 204 | #[inline(always)] 205 | pub fn clear_bit(self) -> &'a mut W { 206 | self.bit(false) 207 | } 208 | #[doc = r"Writes raw bits to the field"] 209 | #[inline(always)] 210 | pub fn bit(self, value: bool) -> &'a mut W { 211 | self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); 212 | self.w 213 | } 214 | } 215 | impl R { 216 | #[doc = "Bits 21:31 - STID"] 217 | #[inline(always)] 218 | pub fn stid(&self) -> STID_R { 219 | STID_R::new(((self.bits >> 21) & 0x07ff) as u16) 220 | } 221 | #[doc = "Bits 3:20 - EXID"] 222 | #[inline(always)] 223 | pub fn exid(&self) -> EXID_R { 224 | EXID_R::new(((self.bits >> 3) & 0x0003_ffff) as u32) 225 | } 226 | #[doc = "Bit 2 - IDE"] 227 | #[inline(always)] 228 | pub fn ide(&self) -> IDE_R { 229 | IDE_R::new(((self.bits >> 2) & 0x01) != 0) 230 | } 231 | #[doc = "Bit 1 - RTR"] 232 | #[inline(always)] 233 | pub fn rtr(&self) -> RTR_R { 234 | RTR_R::new(((self.bits >> 1) & 0x01) != 0) 235 | } 236 | #[doc = "Bit 0 - TXRQ"] 237 | #[inline(always)] 238 | pub fn txrq(&self) -> TXRQ_R { 239 | TXRQ_R::new((self.bits & 0x01) != 0) 240 | } 241 | } 242 | impl W { 243 | #[doc = "Bits 21:31 - STID"] 244 | #[inline(always)] 245 | pub fn stid(&mut self) -> STID_W { 246 | STID_W { w: self } 247 | } 248 | #[doc = "Bits 3:20 - EXID"] 249 | #[inline(always)] 250 | pub fn exid(&mut self) -> EXID_W { 251 | EXID_W { w: self } 252 | } 253 | #[doc = "Bit 2 - IDE"] 254 | #[inline(always)] 255 | pub fn ide(&mut self) -> IDE_W { 256 | IDE_W { w: self } 257 | } 258 | #[doc = "Bit 1 - RTR"] 259 | #[inline(always)] 260 | pub fn rtr(&mut self) -> RTR_W { 261 | RTR_W { w: self } 262 | } 263 | #[doc = "Bit 0 - TXRQ"] 264 | #[inline(always)] 265 | pub fn txrq(&mut self) -> TXRQ_W { 266 | TXRQ_W { w: self } 267 | } 268 | } 269 | -------------------------------------------------------------------------------- /src/pac/generic.rs: -------------------------------------------------------------------------------- 1 | use core::marker; 2 | 3 | ///This trait shows that register has `read` method 4 | /// 5 | ///Registers marked with `Writable` can be also `modify`'ed 6 | pub trait Readable {} 7 | 8 | ///This trait shows that register has `write`, `write_with_zero` and `reset` method 9 | /// 10 | ///Registers marked with `Readable` can be also `modify`'ed 11 | pub trait Writable {} 12 | 13 | ///Reset value of the register 14 | /// 15 | ///This value is initial value for `write` method. 16 | ///It can be also directly writed to register by `reset` method. 17 | pub trait ResetValue { 18 | ///Register size 19 | type Type; 20 | ///Reset value of the register 21 | fn reset_value() -> Self::Type; 22 | } 23 | 24 | ///This structure provides volatile access to register 25 | pub struct Reg { 26 | register: vcell::VolatileCell, 27 | _marker: marker::PhantomData, 28 | } 29 | 30 | unsafe impl Send for Reg {} 31 | 32 | impl Reg 33 | where 34 | Self: Readable, 35 | U: Copy, 36 | { 37 | ///Reads the contents of `Readable` register 38 | /// 39 | ///You can read the contents of a register in such way: 40 | ///```ignore 41 | ///let bits = periph.reg.read().bits(); 42 | ///``` 43 | ///or get the content of a particular field of a register. 44 | ///```ignore 45 | ///let reader = periph.reg.read(); 46 | ///let bits = reader.field1().bits(); 47 | ///let flag = reader.field2().bit_is_set(); 48 | ///``` 49 | #[inline(always)] 50 | pub fn read(&self) -> R { 51 | R { 52 | bits: self.register.get(), 53 | _reg: marker::PhantomData, 54 | } 55 | } 56 | } 57 | 58 | impl Reg 59 | where 60 | Self: ResetValue + Writable, 61 | U: Copy, 62 | { 63 | ///Writes the reset value to `Writable` register 64 | /// 65 | ///Resets the register to its initial state 66 | #[inline(always)] 67 | pub fn reset(&self) { 68 | self.register.set(Self::reset_value()) 69 | } 70 | } 71 | 72 | impl Reg 73 | where 74 | Self: ResetValue + Writable, 75 | U: Copy, 76 | { 77 | ///Writes bits to `Writable` register 78 | /// 79 | ///You can write raw bits into a register: 80 | ///```ignore 81 | ///periph.reg.write(|w| unsafe { w.bits(rawbits) }); 82 | ///``` 83 | ///or write only the fields you need: 84 | ///```ignore 85 | ///periph.reg.write(|w| w 86 | /// .field1().bits(newfield1bits) 87 | /// .field2().set_bit() 88 | /// .field3().variant(VARIANT) 89 | ///); 90 | ///``` 91 | ///Other fields will have reset value. 92 | #[inline(always)] 93 | pub fn write(&self, f: F) 94 | where 95 | F: FnOnce(&mut W) -> &mut W, 96 | { 97 | self.register.set( 98 | f(&mut W { 99 | bits: Self::reset_value(), 100 | _reg: marker::PhantomData, 101 | }) 102 | .bits, 103 | ); 104 | } 105 | } 106 | 107 | impl Reg 108 | where 109 | Self: Writable, 110 | U: Copy + Default, 111 | { 112 | ///Writes Zero to `Writable` register 113 | /// 114 | ///Similar to `write`, but unused bits will contain 0. 115 | #[inline(always)] 116 | pub fn write_with_zero(&self, f: F) 117 | where 118 | F: FnOnce(&mut W) -> &mut W, 119 | { 120 | self.register.set( 121 | f(&mut W { 122 | bits: U::default(), 123 | _reg: marker::PhantomData, 124 | }) 125 | .bits, 126 | ); 127 | } 128 | } 129 | 130 | impl Reg 131 | where 132 | Self: Readable + Writable, 133 | U: Copy, 134 | { 135 | ///Modifies the contents of the register 136 | /// 137 | ///E.g. to do a read-modify-write sequence to change parts of a register: 138 | ///```ignore 139 | ///periph.reg.modify(|r, w| unsafe { w.bits( 140 | /// r.bits() | 3 141 | ///) }); 142 | ///``` 143 | ///or 144 | ///```ignore 145 | ///periph.reg.modify(|_, w| w 146 | /// .field1().bits(newfield1bits) 147 | /// .field2().set_bit() 148 | /// .field3().variant(VARIANT) 149 | ///); 150 | ///``` 151 | ///Other fields will have value they had before call `modify`. 152 | #[inline(always)] 153 | pub fn modify(&self, f: F) 154 | where 155 | for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, 156 | { 157 | let bits = self.register.get(); 158 | self.register.set( 159 | f( 160 | &R { 161 | bits, 162 | _reg: marker::PhantomData, 163 | }, 164 | &mut W { 165 | bits, 166 | _reg: marker::PhantomData, 167 | }, 168 | ) 169 | .bits, 170 | ); 171 | } 172 | } 173 | 174 | ///Register/field reader 175 | /// 176 | ///Result of the [`read`](Reg::read) method of a register. 177 | ///Also it can be used in the [`modify`](Reg::read) method 178 | pub struct R { 179 | pub(crate) bits: U, 180 | _reg: marker::PhantomData, 181 | } 182 | 183 | impl R 184 | where 185 | U: Copy, 186 | { 187 | ///Create new instance of reader 188 | #[inline(always)] 189 | pub(crate) fn new(bits: U) -> Self { 190 | Self { 191 | bits, 192 | _reg: marker::PhantomData, 193 | } 194 | } 195 | ///Read raw bits from register/field 196 | #[inline(always)] 197 | pub fn bits(&self) -> U { 198 | self.bits 199 | } 200 | } 201 | 202 | impl PartialEq for R 203 | where 204 | U: PartialEq, 205 | FI: Copy + Into, 206 | { 207 | #[inline(always)] 208 | fn eq(&self, other: &FI) -> bool { 209 | self.bits.eq(&(*other).into()) 210 | } 211 | } 212 | 213 | impl R { 214 | ///Value of the field as raw bits 215 | #[inline(always)] 216 | pub fn bit(&self) -> bool { 217 | self.bits 218 | } 219 | ///Returns `true` if the bit is clear (0) 220 | #[inline(always)] 221 | pub fn bit_is_clear(&self) -> bool { 222 | !self.bit() 223 | } 224 | ///Returns `true` if the bit is set (1) 225 | #[inline(always)] 226 | pub fn bit_is_set(&self) -> bool { 227 | self.bit() 228 | } 229 | } 230 | 231 | ///Register writer 232 | /// 233 | ///Used as an argument to the closures in the [`write`](Reg::write) and [`modify`](Reg::modify) methods of the register 234 | pub struct W { 235 | ///Writable bits 236 | pub(crate) bits: U, 237 | _reg: marker::PhantomData, 238 | } 239 | 240 | impl W { 241 | ///Writes raw bits to the register 242 | #[inline(always)] 243 | pub unsafe fn bits(&mut self, bits: U) -> &mut Self { 244 | self.bits = bits; 245 | self 246 | } 247 | } 248 | 249 | ///Used if enumerated values cover not the whole range 250 | #[derive(Clone, Copy, PartialEq)] 251 | pub enum Variant { 252 | ///Expected variant 253 | Val(T), 254 | ///Raw bits 255 | Res(U), 256 | } 257 | -------------------------------------------------------------------------------- /src/pac/mod.rs: -------------------------------------------------------------------------------- 1 | #![allow(non_camel_case_types)] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | use core::marker::PhantomData; 5 | use core::ops::Deref; 6 | 7 | #[doc = "Controller area network"] 8 | pub mod can; 9 | pub mod generic; 10 | -------------------------------------------------------------------------------- /testsuite/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 2 | runner = "probe-run --chip STM32F105RB" 3 | rustflags = [ 4 | "-C", "linker=flip-link", 5 | "-C", "link-arg=-Tlink.x", 6 | "-C", "link-arg=-Tdefmt.x", 7 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 8 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 9 | "-C", "link-arg=--nmagic", 10 | ] 11 | 12 | [build] 13 | # (`thumbv6m-*` is compatible with all ARM Cortex-M chips but using the right 14 | # target improves performance) 15 | # target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ 16 | target = "thumbv7m-none-eabi" # Cortex-M3 17 | # target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) 18 | # target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) 19 | 20 | [alias] 21 | rb = "run --bin" 22 | rrb = "run --release --bin" 23 | -------------------------------------------------------------------------------- /testsuite/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | authors = ["Jonas Schievink "] 3 | name = "testsuite" 4 | publish = false 5 | edition = "2021" 6 | version = "0.0.0" 7 | 8 | [lib] 9 | name = "testsuite" 10 | test = false 11 | 12 | [[test]] 13 | name = "integration" 14 | harness = false 15 | 16 | [[test]] 17 | name = "interrupts" 18 | harness = false 19 | 20 | [dependencies] 21 | cortex-m = { version = "0.7.3", features = ["critical-section-single-core"] } 22 | cortex-m-rt = "0.7.0" 23 | defmt = "0.3.0" 24 | defmt-rtt = "0.4.0" 25 | defmt-test = "0.3.0" 26 | panic-probe = { version = "0.3.0", features = ["print-defmt"] } 27 | # NB: We use F107 here, which seems to share its SVD file with the F105. The difference is that the 28 | # 107 has Ethernet, but we don't use that. 29 | stm32f1 = { version = "0.14.0", features = ["stm32f107", "rt"] } 30 | nb = "1.0.0" 31 | irq = "0.2.3" 32 | 33 | [dependencies.bxcan] 34 | path = ".." 35 | features = ["unstable-defmt"] 36 | -------------------------------------------------------------------------------- /testsuite/README.md: -------------------------------------------------------------------------------- 1 | # On-Device bxCAN Testsuite 2 | 3 | This is a small hardware-in-the-loop testsuite powered by [`defmt-test`]. It was 4 | made for STM32F105 MCUs with 2 CAN peripherals. 5 | 6 | Specifically, the testsuite was written to work with the "CAN filter" boards 7 | described in [this article][can-filter-article], and it makes the following 8 | assumptions: 9 | 10 | * Both CAN1 and CAN2 are connected to the same CAN bus, with no interfering 11 | devices on the bus. 12 | * CAN1 is connected to pins PA11 and PA12. 13 | * CAN2 is connected to pins PB5 and PB6 (a non-default remapping). 14 | 15 | [`defmt-test`]: https://crates.io/crates/defmt-test 16 | [can-filter-article]: https://dangerouspayload.com/2020/03/10/hacking-a-mileage-manipulator-can-bus-filter-device/ 17 | -------------------------------------------------------------------------------- /testsuite/build.rs: -------------------------------------------------------------------------------- 1 | fn main() { 2 | let out_dir = std::env::var("OUT_DIR").unwrap(); 3 | std::fs::copy("memory.x", format!("{}/memory.x", out_dir)).unwrap(); 4 | println!("cargo:rustc-link-search={}", out_dir); 5 | } 6 | -------------------------------------------------------------------------------- /testsuite/memory.x: -------------------------------------------------------------------------------- 1 | /* Memory layout of STM32F105RBT6 */ 2 | MEMORY 3 | { 4 | FLASH : ORIGIN = 0x08000000, LENGTH = 128K 5 | RAM : ORIGIN = 0x20000000, LENGTH = 20K 6 | } 7 | -------------------------------------------------------------------------------- /testsuite/src/interrupt.rs: -------------------------------------------------------------------------------- 1 | use core::cell::RefCell; 2 | 3 | use crate::pac::interrupt; 4 | 5 | irq::scoped_interrupts! { 6 | #[allow(non_camel_case_types)] 7 | pub enum Interrupt { 8 | USB_HP_CAN_TX, 9 | USB_LP_CAN_RX0, 10 | CAN_RX1, 11 | CAN_SCE, 12 | CAN2_TX, 13 | CAN2_RX0, 14 | CAN2_RX1, 15 | CAN2_SCE, 16 | } 17 | 18 | use #[interrupt]; 19 | } 20 | 21 | pub use Interrupt::CAN_RX1 as CAN1_RX1; 22 | pub use Interrupt::CAN_SCE as CAN1_SCE; 23 | pub use Interrupt::USB_HP_CAN_TX as CAN1_TX; 24 | pub use Interrupt::USB_LP_CAN_RX0 as CAN1_RX0; 25 | pub use Interrupt::{CAN2_RX0, CAN2_RX1, CAN2_SCE, CAN2_TX}; 26 | 27 | pub struct Mutex { 28 | object: cortex_m::interrupt::Mutex>, 29 | } 30 | 31 | impl Mutex { 32 | pub const fn new(object: T) -> Self { 33 | Self { 34 | object: cortex_m::interrupt::Mutex::new(RefCell::new(object)), 35 | } 36 | } 37 | 38 | pub fn lock(&self, f: impl FnOnce(&mut T) -> R) -> R { 39 | cortex_m::interrupt::free(|cs| f(&mut *self.object.borrow(cs).borrow_mut())) 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /testsuite/src/lib.rs: -------------------------------------------------------------------------------- 1 | //! bxCAN on-device testsuite definitions. 2 | //! 3 | //! This is meant to run on an STM32F105, and will probably break on other chips. 4 | //! 5 | //! We deliberately avoid depending on any STM32 HAL here, since that can cause weird cyclic 6 | //! dependencies once bxcan is used by them. 7 | 8 | #![no_std] 9 | 10 | pub mod interrupt; 11 | 12 | use cortex_m::peripheral::NVIC; 13 | use defmt_rtt as _; 14 | use panic_probe as _; 15 | 16 | use bxcan::{Can, FilterOwner, Frame, Instance, MasterInstance}; 17 | 18 | pub use stm32f1::stm32f107 as pac; 19 | 20 | pub struct CAN1 { 21 | _private: (), 22 | } 23 | 24 | pub struct CAN2 { 25 | _private: (), 26 | } 27 | 28 | unsafe impl Instance for CAN1 { 29 | const REGISTERS: *mut bxcan::RegisterBlock = 0x4000_6400 as *mut _; 30 | } 31 | 32 | unsafe impl MasterInstance for CAN1 {} 33 | 34 | unsafe impl FilterOwner for CAN1 { 35 | /// F105 is a connectivity-line device, which have 28 total filter banks. 36 | const NUM_FILTER_BANKS: u8 = 28; 37 | } 38 | 39 | unsafe impl Instance for CAN2 { 40 | const REGISTERS: *mut bxcan::RegisterBlock = 0x4000_6800 as *mut _; 41 | } 42 | 43 | fn init(p: pac::Peripherals) -> (CAN1, CAN2) { 44 | // Enable CAN interrupts 45 | // Safety: `irq` is safe when all interrupts it manages are enabled. 46 | unsafe { 47 | NVIC::unmask(pac::Interrupt::USB_HP_CAN_TX); 48 | NVIC::unmask(pac::Interrupt::USB_LP_CAN_RX0); 49 | NVIC::unmask(pac::Interrupt::CAN_RX1); 50 | NVIC::unmask(pac::Interrupt::CAN_SCE); 51 | NVIC::unmask(pac::Interrupt::CAN2_TX); 52 | NVIC::unmask(pac::Interrupt::CAN2_RX0); 53 | NVIC::unmask(pac::Interrupt::CAN2_RX1); 54 | NVIC::unmask(pac::Interrupt::CAN2_SCE); 55 | } 56 | 57 | // Initialize CAN peripherals 58 | p.RCC 59 | .apb1enr 60 | .modify(|_, w| w.can1en().enabled().can2en().enabled()); 61 | p.RCC 62 | .apb2enr 63 | .modify(|_, w| w.iopaen().enabled().iopben().enabled().afioen().enabled()); 64 | 65 | p.RCC 66 | .apb1rstr 67 | .modify(|_, w| w.can1rst().reset().can2rst().reset()); 68 | p.RCC 69 | .apb1rstr 70 | .modify(|_, w| w.can1rst().clear_bit().can2rst().clear_bit()); 71 | 72 | // CAN1: PA11 + PA12 73 | // CAN2: PB5 + PB6 74 | p.AFIO 75 | .mapr 76 | .modify(|_, w| unsafe { w.can1_remap().bits(0).can2_remap().set_bit() }); 77 | p.GPIOA 78 | .crh 79 | .modify(|_, w| w.mode12().output().cnf12().alt_push_pull()); 80 | p.GPIOB 81 | .crl 82 | .modify(|_, w| w.mode6().output().cnf6().alt_push_pull()); 83 | 84 | let _ = (p.CAN1, p.CAN2); 85 | 86 | (CAN1 { _private: () }, CAN2 { _private: () }) 87 | } 88 | 89 | pub struct State { 90 | pub can1: Can, 91 | pub can2: Can, 92 | } 93 | 94 | const BTR_FAST: u32 = 0x00050000; 95 | const BTR_SLOW: u32 = 0x007f_03ff; 96 | 97 | impl State { 98 | pub fn init() -> Self { 99 | let periph = defmt::unwrap!(pac::Peripherals::take()); 100 | let (can1, can2) = init(periph); 101 | let mut can1 = Can::builder(can1) 102 | .set_loopback(true) 103 | .set_silent(true) 104 | .set_bit_timing(BTR_FAST) 105 | .enable(); 106 | let can2 = Can::builder(can2) 107 | .set_loopback(true) 108 | .set_silent(true) 109 | .set_bit_timing(BTR_FAST) 110 | .enable(); 111 | can1.modify_filters().clear(); 112 | 113 | let mut state = Self { can1, can2 }; 114 | state.go_fast(); 115 | state 116 | } 117 | 118 | /// Configures the slowest possible speed. 119 | /// 120 | /// This is useful for testing recovery when the mailboxes are full. 121 | pub fn go_slow(&mut self) { 122 | self.can1 123 | .modify_config() 124 | .set_loopback(true) 125 | .set_silent(true) 126 | .set_bit_timing(BTR_SLOW) 127 | .enable(); 128 | self.can2 129 | .modify_config() 130 | .set_loopback(true) 131 | .set_silent(true) 132 | .set_bit_timing(BTR_SLOW) 133 | .enable(); 134 | } 135 | 136 | /// Configures the default (fast) speed. 137 | pub fn go_fast(&mut self) { 138 | self.can1 139 | .modify_config() 140 | .set_loopback(true) 141 | .set_silent(true) 142 | .set_bit_timing(BTR_FAST) 143 | .enable(); 144 | self.can2 145 | .modify_config() 146 | .set_loopback(true) 147 | .set_silent(true) 148 | .set_bit_timing(BTR_FAST) 149 | .enable(); 150 | } 151 | 152 | pub fn roundtrip_frame_fifo0(&mut self, frame: &Frame) -> bool { 153 | nb::block!(self.can1.transmit(frame)).unwrap(); 154 | defmt::assert!(!self.can1.is_transmitter_idle()); 155 | 156 | // Wait until the transmission has completed. 157 | while !self.can1.is_transmitter_idle() {} 158 | 159 | match self.can1.rx0().receive() { 160 | Ok(received) => { 161 | defmt::assert_eq!(received, *frame); 162 | true 163 | } 164 | Err(nb::Error::WouldBlock) => false, 165 | Err(nb::Error::Other(e)) => defmt::panic!("{:?}", e), 166 | } 167 | } 168 | 169 | pub fn roundtrip_frame_fifo1(&mut self, frame: &Frame) -> bool { 170 | nb::block!(self.can1.transmit(frame)).unwrap(); 171 | defmt::assert!(!self.can1.is_transmitter_idle()); 172 | 173 | // Wait until the transmission has completed. 174 | while !self.can1.is_transmitter_idle() {} 175 | 176 | match self.can1.rx1().receive() { 177 | Ok(received) => { 178 | defmt::assert_eq!(received, *frame); 179 | true 180 | } 181 | Err(nb::Error::WouldBlock) => false, 182 | Err(nb::Error::Other(e)) => defmt::panic!("{:?}", e), 183 | } 184 | } 185 | } 186 | -------------------------------------------------------------------------------- /testsuite/tests/interrupts.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | #[defmt_test::tests] 5 | mod tests { 6 | use core::sync::atomic::{AtomicBool, Ordering}; 7 | 8 | use bxcan::{filter::Mask32, Interrupts, Mailbox, StandardId}; 9 | use bxcan::{Fifo, Frame, Interrupt}; 10 | 11 | use irq::handler; 12 | use nb::block; 13 | use testsuite::{ 14 | interrupt::{self, Mutex}, 15 | State, 16 | }; 17 | 18 | #[init] 19 | fn init() -> State { 20 | let mut state = State::init(); 21 | 22 | // Accept all messages. 23 | state 24 | .can1 25 | .modify_filters() 26 | .set_split(1) 27 | .clear() 28 | .enable_bank(0, Fifo::Fifo0, Mask32::accept_all()) 29 | .slave_filters() 30 | .clear() 31 | .enable_bank(1, Fifo::Fifo0, Mask32::accept_all()); 32 | 33 | state 34 | } 35 | 36 | #[test] 37 | fn tx_interrupt(state: &mut State) { 38 | state.can1.enable_interrupt(Interrupt::TransmitMailboxEmpty); 39 | 40 | let m = Mutex::new(&mut *state); 41 | let tx_fired = AtomicBool::new(false); 42 | handler!( 43 | can1_tx = || { 44 | defmt::debug!("CAN1 TX interrupt"); 45 | defmt::assert_eq!( 46 | m.lock(|state| state.can1.clear_request_completed_flag()), 47 | Some(Mailbox::Mailbox0) 48 | ); 49 | defmt::assert_eq!( 50 | m.lock(|state| state.can1.clear_request_completed_flag()), 51 | None 52 | ); 53 | tx_fired.store(true, Ordering::Relaxed); 54 | } 55 | ); 56 | irq::scope(|scope| { 57 | scope.register(interrupt::CAN1_TX, can1_tx); 58 | 59 | defmt::assert!(!tx_fired.load(Ordering::Relaxed)); 60 | let frame = Frame::new_data(StandardId::new(0).unwrap(), []); 61 | defmt::assert!(m.lock(|state| state.roundtrip_frame_fifo0(&frame))); 62 | defmt::assert!(tx_fired.load(Ordering::Relaxed)); 63 | }); 64 | 65 | state 66 | .can1 67 | .disable_interrupt(Interrupt::TransmitMailboxEmpty); 68 | } 69 | 70 | #[test] 71 | fn rx_interrupt_message_pending(state: &mut State) { 72 | state.can1.enable_interrupt(Interrupt::Fifo0MessagePending); 73 | 74 | let m = Mutex::new(&mut *state); 75 | let interrupt_fired = AtomicBool::new(false); 76 | handler!( 77 | can1_rx = || { 78 | defmt::debug!("interrupt: FIFO 0 message pending"); 79 | let frame = m.lock(|state| state.can1.receive().unwrap()); 80 | defmt::debug!("received {:?}", frame); 81 | 82 | interrupt_fired.store(true, Ordering::Relaxed); 83 | } 84 | ); 85 | irq::scope(|scope| { 86 | scope.register(interrupt::CAN1_RX0, can1_rx); 87 | 88 | let frame = Frame::new_data(StandardId::new(0).unwrap(), []); 89 | defmt::debug!("transmitting {:?}", frame); 90 | defmt::assert!(!interrupt_fired.load(Ordering::Relaxed)); 91 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 92 | 93 | m.lock(|state| 94 | // Wait until the transmission has completed. 95 | while !state.can1.is_transmitter_idle() {} 96 | ); 97 | 98 | defmt::assert!(interrupt_fired.load(Ordering::Relaxed)); 99 | }); 100 | 101 | state.can1.disable_interrupt(Interrupt::Fifo0MessagePending); 102 | } 103 | 104 | #[test] 105 | fn rx_interrupt_fifo_full(state: &mut State) { 106 | state.can1.enable_interrupt(Interrupt::Fifo0Full); 107 | 108 | let m = Mutex::new(&mut *state); 109 | let interrupt_fired = AtomicBool::new(false); 110 | handler!( 111 | can1_rx0 = || { 112 | defmt::debug!("interrupt: FIFO 0 is full"); 113 | let frame = m.lock(|state| state.can1.receive().unwrap()); 114 | defmt::debug!("received {:?}", frame); 115 | let frame = m.lock(|state| state.can1.receive().unwrap()); 116 | defmt::debug!("received {:?}", frame); 117 | let frame = m.lock(|state| state.can1.receive().unwrap()); 118 | defmt::debug!("received {:?}", frame); 119 | 120 | interrupt_fired.store(true, Ordering::Relaxed); 121 | } 122 | ); 123 | irq::scope(|scope| { 124 | scope.register(interrupt::CAN1_RX0, can1_rx0); 125 | 126 | let frame = Frame::new_data(StandardId::new(0).unwrap(), []); 127 | defmt::debug!("transmitting {:?} 3 times", frame); 128 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 129 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 130 | defmt::assert!(!interrupt_fired.load(Ordering::Relaxed)); 131 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 132 | 133 | m.lock(|state| 134 | // Wait until all transmissions have completed. 135 | while !state.can1.is_transmitter_idle() {} 136 | ); 137 | 138 | defmt::assert!(interrupt_fired.load(Ordering::Relaxed)); 139 | }); 140 | 141 | state.can1.disable_interrupt(Interrupt::Fifo0Full); 142 | } 143 | 144 | #[test] 145 | fn rx_interrupt_fifo_overrun(state: &mut State) { 146 | state.can1.enable_interrupt(Interrupt::Fifo0Overrun); 147 | 148 | let m = Mutex::new(&mut *state); 149 | let interrupt_fired = AtomicBool::new(false); 150 | handler!( 151 | can1_rx0 = || { 152 | defmt::debug!("interrupt: FIFO 0 overrun"); 153 | m.lock(|state| state.can1.receive().unwrap_err()); 154 | 155 | interrupt_fired.store(true, Ordering::Relaxed); 156 | } 157 | ); 158 | irq::scope(|scope| { 159 | scope.register(interrupt::CAN1_RX0, can1_rx0); 160 | 161 | let frame = Frame::new_data(StandardId::new(0).unwrap(), []); 162 | defmt::debug!("transmitting {:?} 4 times", frame); 163 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 164 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 165 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 166 | 167 | m.lock(|state| 168 | // Wait until all transmissions have completed. 169 | while !state.can1.is_transmitter_idle() {} 170 | ); 171 | 172 | // FIFO should be full, but not have overrun. 173 | defmt::assert!(!interrupt_fired.load(Ordering::Relaxed)); 174 | 175 | defmt::unwrap!(block!(m.lock(|state| state.can1.transmit(&frame)))); 176 | 177 | m.lock(|state| 178 | // Wait until all transmissions have completed. 179 | while !state.can1.is_transmitter_idle() {} 180 | ); 181 | 182 | // Reception of the 4th message should have caused an overrun interrupt. 183 | defmt::assert!(interrupt_fired.load(Ordering::Relaxed)); 184 | 185 | // Drain the receive FIFO for subsequent tests. 186 | defmt::unwrap!(block!(m.lock(|state| state.can1.receive()))); 187 | defmt::unwrap!(block!(m.lock(|state| state.can1.receive()))); 188 | defmt::unwrap!(block!(m.lock(|state| state.can1.receive()))); 189 | }); 190 | 191 | state.can1.disable_interrupt(Interrupt::Fifo0Overrun); 192 | } 193 | 194 | #[test] 195 | fn sce_interrupt_sleep(state: &mut State) { 196 | state.can1.enable_interrupts(Interrupts::SLEEP); 197 | 198 | let m = Mutex::new(&mut *state); 199 | let sleep_interrupt_fired = AtomicBool::new(false); 200 | handler!( 201 | on_sleep = || { 202 | defmt::debug!("interrupt: entered sleep mode"); 203 | m.lock(|state| state.can1.clear_sleep_interrupt()); 204 | sleep_interrupt_fired.store(true, Ordering::Relaxed); 205 | } 206 | ); 207 | irq::scope(|scope| { 208 | scope.register(interrupt::CAN1_SCE, on_sleep); 209 | 210 | defmt::assert!(!sleep_interrupt_fired.load(Ordering::Relaxed)); 211 | m.lock(|state| state.can1.sleep()); 212 | defmt::assert!(sleep_interrupt_fired.load(Ordering::Relaxed)); 213 | }); 214 | 215 | state.can1.disable_interrupts(Interrupts::SLEEP); 216 | } 217 | 218 | #[test] 219 | fn sce_interrupt_wakeup(state: &mut State) { 220 | // The wakeup interrupt does not fire when calling `can.wakeup()`, it requires an incoming 221 | // message. This test uses CAN2 to send that message. 222 | 223 | state.can1.enable_interrupt(Interrupt::Wakeup); 224 | 225 | // Turn off the loopback modes. 226 | state 227 | .can1 228 | .modify_config() 229 | .set_loopback(false) 230 | .set_silent(false) 231 | .set_bit_timing(0x00050000) 232 | .enable(); 233 | state 234 | .can2 235 | .modify_config() 236 | .set_loopback(false) 237 | .set_silent(false) 238 | .set_bit_timing(0x00050000) 239 | .enable(); 240 | 241 | let m = Mutex::new(&mut *state); 242 | let wakeup_interrupt_fired = AtomicBool::new(false); 243 | handler!( 244 | on_wakeup = || { 245 | defmt::debug!("interrupt: left sleep mode"); 246 | m.lock(|state| state.can1.clear_wakeup_interrupt()); 247 | wakeup_interrupt_fired.store(true, Ordering::Relaxed); 248 | } 249 | ); 250 | irq::scope(|scope| { 251 | scope.register(interrupt::CAN1_SCE, on_wakeup); 252 | 253 | m.lock(|state| { 254 | state.can1.set_automatic_wakeup(true); 255 | state.can1.sleep(); 256 | }); 257 | let frame = Frame::new_data(StandardId::new(0).unwrap(), []); 258 | defmt::unwrap!(block!(m.lock(|state| state.can2.transmit(&frame)))); 259 | m.lock(|state| 260 | // Wait until all transmissions have completed. 261 | while !state.can2.is_transmitter_idle() {} 262 | ); 263 | defmt::assert!(wakeup_interrupt_fired.load(Ordering::Relaxed)); 264 | 265 | // Frame should still be received correctly. 266 | let recvd = defmt::unwrap!(block!(m.lock(|state| state.can1.receive()))); 267 | defmt::assert_eq!(recvd, frame); 268 | }); 269 | 270 | state.can1.disable_interrupt(Interrupt::Wakeup); 271 | state.go_fast(); 272 | } 273 | } 274 | --------------------------------------------------------------------------------