├── .github └── workflows │ └── ci.yml ├── .gitignore ├── CHANGELOG.md ├── Cargo.toml ├── LICENSE-APACHE ├── LICENSE-MIT ├── README.md ├── RELEASE_PROCESS.md ├── rustfmt.toml └── src ├── config.rs ├── filter.rs ├── frame.rs ├── id.rs ├── interrupt.rs ├── lib.rs ├── message_ram.rs ├── message_ram ├── common.rs ├── enums.rs ├── extended_filter.rs ├── generic.rs ├── rxfifo_element.rs ├── standard_filter.rs ├── txbuffer_element.rs └── txevent_element.rs └── pac ├── fdcan.rs ├── fdcan ├── cccr.rs ├── crel.rs ├── dbtp.rs ├── ecr.rs ├── endn.rs ├── hpms.rs ├── ie_g0_g4_l5.rs ├── ie_h7.rs ├── ile_g0_g4_l5.rs ├── ile_h7.rs ├── ils_g0_g4_l5.rs ├── ils_h7.rs ├── ir_g0_g4_l5.rs ├── ir_h7.rs ├── nbtp.rs ├── ndat1.rs ├── ndat2.rs ├── psr.rs ├── rwd.rs ├── rxbc.rs ├── rxesc.rs ├── rxf0a.rs ├── rxf0c.rs ├── rxf0s.rs ├── rxf1a.rs ├── rxf1c.rs ├── rxf1s.rs ├── rxgfc_g0_g4_l5.rs ├── rxgfc_h7.rs ├── sidfc.rs ├── tdcr.rs ├── test.rs ├── tocc.rs ├── tocv.rs ├── tscc.rs ├── tscv.rs ├── ttcpt.rs ├── ttcsm.rs ├── ttctc.rs ├── ttgtp.rs ├── ttie.rs ├── ttils.rs ├── ttir.rs ├── ttlgt.rs ├── ttmlm.rs ├── ttocf.rs ├── ttocn.rs ├── ttost.rs ├── ttrmc.rs ├── tttmc.rs ├── tttmk.rs ├── ttts.rs ├── turcf.rs ├── turna.rs ├── txbar.rs ├── txbc_g0_g4_l5.rs ├── txbc_h7.rs ├── txbcf.rs ├── txbcie.rs ├── txbcr.rs ├── txbrp.rs ├── txbtie.rs ├── txbto.rs ├── txefa.rs ├── txefc.rs ├── txefs.rs ├── txesc.rs ├── txfqs.rs ├── xidam.rs └── xidfc.rs ├── generic.rs └── mod.rs /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | on: 2 | push: 3 | branches: master 4 | pull_request: 5 | merge_group: 6 | 7 | name: Continuous integration 8 | 9 | env: 10 | CARGO_TERM_COLOR: always 11 | TARGET: thumbv7em-none-eabihf 12 | 13 | jobs: 14 | ci: 15 | name: CI 16 | runs-on: ubuntu-latest 17 | needs: [test, lint] 18 | if: always() 19 | steps: 20 | - name: Done 21 | run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}' 22 | 23 | test: 24 | runs-on: ubuntu-latest 25 | strategy: 26 | matrix: 27 | rust: 28 | - 1.60.0 # MSRV 29 | - stable 30 | device_feature: 31 | - fdcan_g0_g4_l5 32 | - fdcan_h7 33 | steps: 34 | - uses: actions/checkout@v2 35 | - name: Cache cargo registry and index 36 | uses: actions/cache@v2 37 | with: 38 | path: | 39 | ~/.cargo/registry 40 | ~/.cargo/git 41 | key: ${{ runner.os }}-cargo-${{ hashFiles('**/Cargo.toml') }} 42 | - name: Cache cargo build 43 | uses: actions/cache@v2 44 | with: 45 | path: target 46 | key: ${{ runner.os }}-target-${{ matrix.rust }}-${{ hashFiles('**/Cargo.toml') }} 47 | - uses: actions-rs/toolchain@v1 48 | with: 49 | profile: minimal 50 | toolchain: ${{ matrix.rust }} 51 | target: ${{ env.TARGET }} 52 | override: true 53 | - uses: actions-rs/cargo@v1 54 | with: 55 | use-cross: true 56 | command: build 57 | args: --verbose --release --target ${{ env.TARGET }} --features ${{ matrix.device_feature }} 58 | - uses: actions-rs/cargo@v1 59 | with: 60 | use-cross: true 61 | command: test 62 | args: --verbose --features ${{ matrix.device_feature }} 63 | 64 | lint: 65 | runs-on: ubuntu-latest 66 | steps: 67 | - uses: actions/checkout@v2 68 | - uses: actions-rs/toolchain@v1 69 | with: 70 | profile: minimal 71 | toolchain: stable 72 | override: true 73 | components: rustfmt 74 | - name: Check code formatting 75 | run: cargo fmt -- --check 76 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | **/*.rs.bk 3 | Cargo.lock 4 | *.hex 5 | *.bin 6 | .gdb_history 7 | Embed.toml 8 | **/*.vscode -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Changelog 2 | 3 | ## [Unreleased] 4 | 5 | * Update MSRV to 1.60 6 | * Allow timestamp to be accessed in all modes 7 | 8 | ## [v0.2.1] 2024-09-04 9 | 10 | * Bugfix: Fix transmit pause configuration [#41] 11 | * Update depreciated method `set_interrupt_line_config` to `select_interrupt_line_1` [#46] 12 | 13 | ## [v0.2.0] 2023-07-09 14 | 15 | * **Breaking:** Rename method `set_interrupt_line_config` to `select_interrupt_line_1` [#27] 16 | * bors bot replaced with GH merge queue 17 | * Update txbuffer element.rs : to data length [#23] 18 | * Expose protocol status and error properties [#25] 19 | * Fix undefined behaviour in write_mailbox. [#32] 20 | * Use volatile reads and writes for rx and tx buffers [#34] 21 | * message_ram: fix SFIDx read/write mask [#36] 22 | 23 | ## [v0.1.2] 2022-09-13 24 | 25 | * Fix DLC field (frame length) for FDCAN frames [#21] 26 | 27 | ## [v0.1.1] 2022-07-27 28 | 29 | * Fix mask for STANDARD ID, was applied incorrectly 30 | 31 | ## [v0.1.0] 2022-03-18 32 | 33 | Initial release. 34 | 35 | Callbacks replaced with parameter buffer #10 36 | 37 | [Unreleased]: https://github.com/stm32-rs/fdcan/compare/v0.2.1...HEAD 38 | [v0.2.1]: https://github.com/stm32-rs/fdcan/compare/v0.2.0...v0.2.1 39 | [v0.2.0]: https://github.com/stm32-rs/fdcan/compare/v0.1.2...v0.2.0 40 | [v0.1.2]: https://github.com/stm32-rs/fdcan/compare/v0.1.1...v0.1.2 41 | [v0.1.1]: https://github.com/stm32-rs/fdcan/compare/v0.1.0...v0.1.1 42 | 43 | [#18]: https://github.com/stm32-rs/fdcan/pull/18 44 | [#21]: https://github.com/stm32-rs/fdcan/pull/21 45 | [#23]: https://github.com/stm32-rs/fdcan/pull/23 46 | [#25]: https://github.com/stm32-rs/fdcan/pull/25 47 | [#27]: https://github.com/stm32-rs/fdcan/pull/27 48 | [#32]: https://github.com/stm32-rs/fdcan/pull/32 49 | [#34]: https://github.com/stm32-rs/fdcan/pull/34 50 | [#36]: https://github.com/stm32-rs/fdcan/pull/36 51 | [#41]: https://github.com/stm32-rs/fdcan/pull/41 52 | [#46]: https://github.com/stm32-rs/fdcan/pull/46 53 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "fdcan" 3 | version = "0.2.1" 4 | authors = [ 5 | "Richard Meadows ", 6 | "Cor Peters " 7 | ] 8 | edition = "2018" 9 | description = "STM32 FDCAN peripheral driver" 10 | documentation = "https://docs.rs/fdcan/" 11 | repository = "https://github.com/stm32-rs/fdcan.git" 12 | keywords = ["can", "hal", "bus"] 13 | categories = ["no-std", "embedded"] 14 | license = "MIT/Apache-2.0" 15 | readme = "README.md" 16 | 17 | [package.metadata.docs.rs] 18 | features = ["fdcan_g0_g4_l5"] 19 | targets = ["thumbv7em-none-eabihf"] 20 | 21 | [features] 22 | fdcan_g0_g4_l5 = [] # Peripheral map found on G0 G4 L5 23 | fdcan_h7 = [] # Peripheral map found on H7 24 | 25 | defmt-03 = ["dep:defmt"] 26 | 27 | [dependencies] 28 | bitflags = "1.3.2" 29 | paste = "1.0" 30 | vcell = "0.1.3" 31 | nb = "1.0.0" 32 | static_assertions = "1.1" 33 | volatile-register = "0.2.1" 34 | defmt = { version = "0.3.6", optional = true } 35 | 36 | [dependencies.embedded-can-03] 37 | version = "0.3" 38 | optional = true 39 | package = "embedded-can" 40 | 41 | 42 | [profile.test] 43 | opt-level = "s" 44 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | MIT LICENSE 2 | 3 | Copyright (c) 2021 4 | 5 | Permission is hereby granted, free of charge, to any 6 | person obtaining a copy of this software and associated 7 | documentation files (the "Software"), to deal in the 8 | Software without restriction, including without 9 | limitation the rights to use, copy, modify, merge, 10 | publish, distribute, sublicense, and/or sell copies of 11 | the Software, and to permit persons to whom the Software 12 | is furnished to do so, subject to the following 13 | conditions: 14 | 15 | The above copyright notice and this permission notice 16 | shall be included in all copies or substantial portions 17 | of the Software. 18 | 19 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF 20 | ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 21 | TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 22 | PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT 23 | SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR 26 | IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 27 | DEALINGS IN THE SOFTWARE. 28 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FDCAN peripheral driver 2 | 3 | [![crates.io](https://img.shields.io/crates/v/fdcan.svg)](https://crates.io/crates/fdcan) 4 | [![docs.rs](https://docs.rs/fdcan/badge.svg)](https://docs.rs/fdcan/) 5 | ![CI](https://github.com/stm32-rs/fdcan/actions/workflows/ci.yml/badge.svg) 6 | 7 | This crate implements a driver for the FDCAN peripheral found in high-end STM32 8 | microcontrollers (G0, G4, H7, L5 series). The other CAN peripheral found on 9 | STM32 microcontrollers is [bxCAN](https://github.com/stm32-rs/bxcan). 10 | 11 | ## Usage 12 | 13 | Add an entry to your `Cargo.toml`: 14 | 15 | ```toml 16 | [dependencies] 17 | fdcan = "0.2.1" 18 | ``` 19 | 20 | # Minimum supported Rust version 21 | 22 | The Minimum Supported Rust Version (MSRV) at the moment is **1.60.0**. Older 23 | versions **may** compile, especially when some features are not used 24 | in your application. 25 | 26 | # Changelog 27 | 28 | See [CHANGELOG.md](CHANGELOG.md). 29 | -------------------------------------------------------------------------------- /RELEASE_PROCESS.md: -------------------------------------------------------------------------------- 1 | # What to do to publish a new release 2 | 3 | * Update Cargo.toml 4 | * Update CHANGELOG.md 5 | * Update version in README.md 6 | 7 | ``` 8 | git commit -am 'v0.2.0' 9 | git push upstream 10 | 11 | # Merge this commit onto the master branch 12 | 13 | git fetch upstream 14 | git checkout upstream/master 15 | git tag -a 'v0.2.0' -m 'v0.2.0' 16 | git push upstream v0.2.0 17 | cargo publish --features fdcan_g0_g4_l5 18 | ``` 19 | -------------------------------------------------------------------------------- /rustfmt.toml: -------------------------------------------------------------------------------- 1 | # ------------------------------------------------------------------------ 2 | # r u s t f m t - C O N F I G 3 | # ======================================================================== 4 | # Maximum width of each line. 5 | max_width = 88 6 | # Number of spaces per tab. 7 | tab_spaces = 4 8 | 9 | newline_style = "Unix" -------------------------------------------------------------------------------- /src/message_ram.rs: -------------------------------------------------------------------------------- 1 | use volatile_register::RW; 2 | 3 | pub(crate) mod common; 4 | pub(crate) mod enums; 5 | pub(crate) mod generic; 6 | 7 | /// Number of Receive Fifos configured by this module 8 | pub const RX_FIFOS_MAX: u8 = 2; 9 | /// Number of Receive Messages per RxFifo configured by this module 10 | pub const RX_FIFO_MAX: u8 = 3; 11 | /// Number of Transmit Messages configured by this module 12 | pub const TX_FIFO_MAX: u8 = 3; 13 | /// Number of Transmit Events configured by this module 14 | pub const TX_EVENT_MAX: u8 = 3; 15 | /// Number of Standard Filters configured by this module 16 | pub const STANDARD_FILTER_MAX: u8 = 28; 17 | /// Number of Extended Filters configured by this module 18 | pub const EXTENDED_FILTER_MAX: u8 = 8; 19 | 20 | /// MessageRam Overlay 21 | #[repr(C)] 22 | pub struct RegisterBlock { 23 | pub(crate) filters: Filters, 24 | pub(crate) receive: [Receive; RX_FIFOS_MAX as usize], 25 | pub(crate) transmit: Transmit, 26 | } 27 | impl RegisterBlock { 28 | pub fn reset(&mut self) { 29 | self.filters.reset(); 30 | self.receive[0].reset(); 31 | self.receive[1].reset(); 32 | self.transmit.reset(); 33 | } 34 | } 35 | 36 | #[repr(C)] 37 | pub(crate) struct Filters { 38 | pub(crate) flssa: [StandardFilter; STANDARD_FILTER_MAX as usize], 39 | pub(crate) flesa: [ExtendedFilter; EXTENDED_FILTER_MAX as usize], 40 | } 41 | impl Filters { 42 | pub fn reset(&mut self) { 43 | for sf in &mut self.flssa { 44 | sf.reset(); 45 | } 46 | for ef in &mut self.flesa { 47 | ef.reset(); 48 | } 49 | } 50 | } 51 | 52 | #[repr(C)] 53 | pub(crate) struct Receive { 54 | pub(crate) fxsa: [RxFifoElement; RX_FIFO_MAX as usize], 55 | } 56 | impl Receive { 57 | pub fn reset(&mut self) { 58 | for fe in &mut self.fxsa { 59 | fe.reset(); 60 | } 61 | } 62 | } 63 | 64 | #[repr(C)] 65 | pub(crate) struct Transmit { 66 | pub(crate) efsa: [TxEventElement; TX_EVENT_MAX as usize], 67 | pub(crate) tbsa: [TxBufferElement; TX_FIFO_MAX as usize], 68 | } 69 | impl Transmit { 70 | pub fn reset(&mut self) { 71 | for ee in &mut self.efsa { 72 | ee.reset(); 73 | } 74 | for be in &mut self.tbsa { 75 | be.reset(); 76 | } 77 | } 78 | } 79 | 80 | pub(crate) mod standard_filter; 81 | pub(crate) type StandardFilterType = u32; 82 | pub(crate) type StandardFilter = generic::Reg; 83 | pub(crate) struct _StandardFilter; 84 | impl generic::Readable for StandardFilter {} 85 | impl generic::Writable for StandardFilter {} 86 | 87 | pub(crate) mod extended_filter; 88 | pub(crate) type ExtendedFilterType = [u32; 2]; 89 | pub(crate) type ExtendedFilter = generic::Reg; 90 | pub(crate) struct _ExtendedFilter; 91 | impl generic::Readable for ExtendedFilter {} 92 | impl generic::Writable for ExtendedFilter {} 93 | 94 | pub(crate) mod txevent_element; 95 | pub(crate) type TxEventElementType = [u32; 2]; 96 | pub(crate) type TxEventElement = generic::Reg; 97 | pub(crate) struct _TxEventElement; 98 | impl generic::Readable for TxEventElement {} 99 | impl generic::Writable for TxEventElement {} 100 | 101 | pub(crate) mod rxfifo_element; 102 | #[repr(C)] 103 | pub(crate) struct RxFifoElement { 104 | pub(crate) header: RxFifoElementHeader, 105 | pub(crate) data: [RW; 16], 106 | } 107 | impl RxFifoElement { 108 | pub(crate) fn reset(&mut self) { 109 | self.header.reset(); 110 | for byte in self.data.iter_mut() { 111 | unsafe { byte.write(0) }; 112 | } 113 | } 114 | } 115 | pub(crate) type RxFifoElementHeaderType = [u32; 2]; 116 | pub(crate) type RxFifoElementHeader = 117 | generic::Reg; 118 | pub(crate) struct _RxFifoElement; 119 | impl generic::Readable for RxFifoElementHeader {} 120 | impl generic::Writable for RxFifoElementHeader {} 121 | 122 | pub(crate) mod txbuffer_element; 123 | #[repr(C)] 124 | pub(crate) struct TxBufferElement { 125 | pub(crate) header: TxBufferElementHeader, 126 | pub(crate) data: [RW; 16], 127 | } 128 | impl TxBufferElement { 129 | pub(crate) fn reset(&mut self) { 130 | self.header.reset(); 131 | for byte in self.data.iter_mut() { 132 | unsafe { byte.write(0) }; 133 | } 134 | } 135 | } 136 | pub(crate) type TxBufferElementHeader = 137 | generic::Reg; 138 | pub(crate) type TxBufferElementHeaderType = [u32; 2]; 139 | pub(crate) struct _TxBufferElement; 140 | impl generic::Readable for TxBufferElementHeader {} 141 | impl generic::Writable for TxBufferElementHeader {} 142 | 143 | /// FdCan Message RAM instance. 144 | /// 145 | /// # Safety 146 | /// 147 | /// It is only safe to implement this trait, when: 148 | /// 149 | /// * The implementing type has ownership of the Message RAM, preventing any 150 | /// other accesses to the register block. 151 | /// * `MSG_RAM` is a pointer to the Message RAM block and can be safely accessed 152 | /// for as long as ownership or a borrow of the implementing type is present. 153 | pub unsafe trait Instance { 154 | const MSG_RAM: *mut RegisterBlock; 155 | fn msg_ram(&self) -> &RegisterBlock { 156 | unsafe { &*Self::MSG_RAM } 157 | } 158 | fn msg_ram_mut(&mut self) -> &mut RegisterBlock { 159 | unsafe { &mut *Self::MSG_RAM } 160 | } 161 | } 162 | 163 | // Ensure the RegisterBlock is the same size as on pg 1957 of RM0440. 164 | static_assertions::assert_eq_size!(Filters, [u32; 28 + 16]); 165 | static_assertions::assert_eq_size!(Receive, [u32; 54]); 166 | static_assertions::assert_eq_size!(Transmit, [u32; 6 + 54]); 167 | static_assertions::assert_eq_size!( 168 | RegisterBlock, 169 | [u32; 28 /*Standard Filters*/ +16 /*Extended Filters*/ +54 /*RxFifo0*/ +54 /*RxFifo1*/ +6 /*TxEvent*/ +54 /*TxFifo */] 170 | ); 171 | -------------------------------------------------------------------------------- /src/message_ram/common.rs: -------------------------------------------------------------------------------- 1 | #![allow(non_camel_case_types)] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | 5 | use super::enums::{ 6 | BitRateSwitching, ErrorStateIndicator, FilterElementConfig, FilterType, 7 | FrameFormat, IdType, RemoteTransmissionRequest, 8 | }; 9 | use super::generic; 10 | 11 | #[doc = "Reader of field `ID`"] 12 | pub type ID_R = generic::R; 13 | 14 | #[doc = "Reader of field `RTR`"] 15 | pub type RTR_R = generic::R; 16 | impl RTR_R { 17 | pub fn rtr(&self) -> RemoteTransmissionRequest { 18 | match self.bits { 19 | false => RemoteTransmissionRequest::TransmitDataFrame, 20 | true => RemoteTransmissionRequest::TransmitRemoteFrame, 21 | } 22 | } 23 | pub fn is_transmit_remote_frame(&self) -> bool { 24 | *self == RemoteTransmissionRequest::TransmitRemoteFrame 25 | } 26 | pub fn is_transmit_data_frame(&self) -> bool { 27 | *self == RemoteTransmissionRequest::TransmitDataFrame 28 | } 29 | } 30 | 31 | #[doc = "Reader of field `XTD`"] 32 | pub type XTD_R = generic::R; 33 | impl XTD_R { 34 | pub fn id_type(&self) -> IdType { 35 | match self.bits() { 36 | false => IdType::StandardId, 37 | true => IdType::ExtendedId, 38 | } 39 | } 40 | pub fn is_standard_id(&self) -> bool { 41 | *self == IdType::StandardId 42 | } 43 | pub fn is_exteded_id(&self) -> bool { 44 | *self == IdType::ExtendedId 45 | } 46 | } 47 | 48 | #[doc = "Reader of field `ESI`"] 49 | pub type ESI_R = generic::R; 50 | impl ESI_R { 51 | pub fn error_state(&self) -> ErrorStateIndicator { 52 | match self.bits() { 53 | false => ErrorStateIndicator::ErrorActive, 54 | true => ErrorStateIndicator::ErrorPassive, 55 | } 56 | } 57 | pub fn is_error_active(&self) -> bool { 58 | *self == ErrorStateIndicator::ErrorActive 59 | } 60 | pub fn is_error_passive(&self) -> bool { 61 | *self == ErrorStateIndicator::ErrorPassive 62 | } 63 | } 64 | 65 | #[doc = "Reader of field `DLC`"] 66 | pub type DLC_R = generic::R; 67 | 68 | #[doc = "Reader of field `BRS`"] 69 | pub type BRS_R = generic::R; 70 | impl BRS_R { 71 | pub fn bit_rate_switching(&self) -> BitRateSwitching { 72 | match self.bits() { 73 | true => BitRateSwitching::WithBRS, 74 | false => BitRateSwitching::WithoutBRS, 75 | } 76 | } 77 | pub fn is_with_brs(&self) -> bool { 78 | *self == BitRateSwitching::WithBRS 79 | } 80 | pub fn is_without_brs(&self) -> bool { 81 | *self == BitRateSwitching::WithoutBRS 82 | } 83 | } 84 | 85 | #[doc = "Reader of field `FDF`"] 86 | pub type FDF_R = generic::R; 87 | impl FDF_R { 88 | pub fn frame_format(&self) -> FrameFormat { 89 | match self.bits() { 90 | false => FrameFormat::Standard, 91 | true => FrameFormat::Fdcan, 92 | } 93 | } 94 | pub fn is_standard_format(&self) -> bool { 95 | *self == FrameFormat::Standard 96 | } 97 | pub fn is_fdcan_format(&self) -> bool { 98 | *self == FrameFormat::Fdcan 99 | } 100 | } 101 | 102 | #[doc = "Reader of field `(X|S)FT`"] 103 | pub type ESFT_R = generic::R; 104 | impl ESFT_R { 105 | #[doc = r"Gets the Filtertype"] 106 | #[inline(always)] 107 | pub fn to_filter_type(&self) -> FilterType { 108 | match self.bits() { 109 | 0b00 => FilterType::RangeFilter, 110 | 0b01 => FilterType::DualIdFilter, 111 | 0b10 => FilterType::ClassicFilter, 112 | 0b11 => FilterType::FilterDisabled, 113 | _ => unreachable!(), 114 | } 115 | } 116 | } 117 | 118 | #[doc = "Reader of field `(E|S)FEC`"] 119 | pub type ESFEC_R = generic::R; 120 | impl ESFEC_R { 121 | pub fn to_filter_element_config(&self) -> FilterElementConfig { 122 | match self.bits() { 123 | 0b000 => FilterElementConfig::DisableFilterElement, 124 | 0b001 => FilterElementConfig::StoreInFifo0, 125 | 0b010 => FilterElementConfig::StoreInFifo1, 126 | 0b011 => FilterElementConfig::Reject, 127 | 0b100 => FilterElementConfig::SetPriority, 128 | 0b101 => FilterElementConfig::SetPriorityAndStoreInFifo0, 129 | 0b110 => FilterElementConfig::SetPriorityAndStoreInFifo1, 130 | _ => unimplemented!(), 131 | } 132 | } 133 | } 134 | -------------------------------------------------------------------------------- /src/message_ram/enums.rs: -------------------------------------------------------------------------------- 1 | /// Datalength is the message length generalised over 2 | /// the Standard (Classic) and FDCAN message types 3 | 4 | #[derive(Clone, Copy, Debug, PartialEq)] 5 | pub enum DataLength { 6 | Standard(u8), 7 | Fdcan(u8), 8 | } 9 | impl DataLength { 10 | /// Creates a DataLength type 11 | /// 12 | /// Uses the byte length and Type of frame as input 13 | pub fn new(len: u8, ff: FrameFormat) -> DataLength { 14 | match ff { 15 | FrameFormat::Standard => match len { 16 | 0..=8 => DataLength::Standard(len), 17 | _ => panic!("DataLength > 8"), 18 | }, 19 | FrameFormat::Fdcan => match len { 20 | 0..=64 => DataLength::Fdcan(len), 21 | _ => panic!("DataLength > 64"), 22 | }, 23 | } 24 | } 25 | /// Specialised function to create standard frames 26 | pub fn new_standard(len: u8) -> DataLength { 27 | Self::new(len, FrameFormat::Standard) 28 | } 29 | /// Specialised function to create FDCAN frames 30 | pub fn new_fdcan(len: u8) -> DataLength { 31 | Self::new(len, FrameFormat::Fdcan) 32 | } 33 | 34 | /// returns the length in bytes 35 | pub fn len(&self) -> u8 { 36 | match self { 37 | DataLength::Standard(l) | DataLength::Fdcan(l) => *l, 38 | } 39 | } 40 | 41 | pub(crate) fn dlc(&self) -> u8 { 42 | match self { 43 | DataLength::Standard(l) => *l, 44 | // See RM0433 Rev 7 Table 475. DLC coding 45 | DataLength::Fdcan(l) => match l { 46 | 0..=8 => *l, 47 | 9..=12 => 9, 48 | 13..=16 => 10, 49 | 17..=20 => 11, 50 | 21..=24 => 12, 51 | 25..=32 => 13, 52 | 33..=48 => 14, 53 | 49..=64 => 15, 54 | _ => panic!("DataLength > 64"), 55 | }, 56 | } 57 | } 58 | } 59 | impl From for FrameFormat { 60 | fn from(dl: DataLength) -> FrameFormat { 61 | match dl { 62 | DataLength::Standard(_) => FrameFormat::Standard, 63 | DataLength::Fdcan(_) => FrameFormat::Fdcan, 64 | } 65 | } 66 | } 67 | 68 | /// Wheter or not to generate an Tx Event 69 | #[derive(Clone, Copy, Debug, PartialEq)] 70 | pub enum Event { 71 | /// Do not generate an Tx Event 72 | NoEvent, 73 | /// Generate an Tx Event with a specified ID 74 | Event(u8), 75 | } 76 | 77 | impl From for EventControl { 78 | fn from(e: Event) -> Self { 79 | match e { 80 | Event::NoEvent => EventControl::DoNotStore, 81 | Event::Event(_) => EventControl::Store, 82 | } 83 | } 84 | } 85 | 86 | impl From> for Event { 87 | fn from(mm: Option) -> Self { 88 | match mm { 89 | None => Event::NoEvent, 90 | Some(mm) => Event::Event(mm), 91 | } 92 | } 93 | } 94 | 95 | impl From for Option { 96 | fn from(e: Event) -> Option { 97 | match e { 98 | Event::NoEvent => None, 99 | Event::Event(mm) => Some(mm), 100 | } 101 | } 102 | } 103 | 104 | /// TODO 105 | #[derive(Clone, Copy, Debug, PartialEq)] 106 | pub enum ErrorStateIndicator { 107 | /// TODO 108 | ErrorActive = 0, 109 | /// TODO 110 | ErrorPassive = 1, 111 | } 112 | impl From for bool { 113 | #[inline(always)] 114 | fn from(e: ErrorStateIndicator) -> Self { 115 | e as u8 != 0 116 | } 117 | } 118 | 119 | /// Type of frame, standard (classic) or FdCAN 120 | #[derive(Clone, Copy, Debug, PartialEq)] 121 | pub enum FrameFormat { 122 | Standard = 0, 123 | Fdcan = 1, 124 | } 125 | impl From for bool { 126 | #[inline(always)] 127 | fn from(e: FrameFormat) -> Self { 128 | e as u8 != 0 129 | } 130 | } 131 | 132 | /// Type of Id, Standard or Extended 133 | #[derive(Clone, Copy, Debug, PartialEq)] 134 | pub enum IdType { 135 | /// Standard ID 136 | StandardId = 0, 137 | /// Extended ID 138 | ExtendedId = 1, 139 | } 140 | impl From for bool { 141 | #[inline(always)] 142 | fn from(e: IdType) -> Self { 143 | e as u8 != 0 144 | } 145 | } 146 | 147 | /// Whether the frame contains data or requests data 148 | #[derive(Clone, Copy, Debug, PartialEq)] 149 | pub enum RemoteTransmissionRequest { 150 | /// Frame contains data 151 | TransmitDataFrame = 0, 152 | /// frame does not contain data 153 | TransmitRemoteFrame = 1, 154 | } 155 | impl From for bool { 156 | #[inline(always)] 157 | fn from(e: RemoteTransmissionRequest) -> Self { 158 | e as u8 != 0 159 | } 160 | } 161 | 162 | /// Whether BitRateSwitching should be or was enabled 163 | #[derive(Clone, Copy, Debug, PartialEq)] 164 | pub enum BitRateSwitching { 165 | /// disable bit rate switching 166 | WithoutBRS = 0, 167 | /// enable bit rate switching 168 | WithBRS = 1, 169 | } 170 | impl From for bool { 171 | #[inline(always)] 172 | fn from(e: BitRateSwitching) -> Self { 173 | e as u8 != 0 174 | } 175 | } 176 | 177 | /// Whether to store transmit Events 178 | #[derive(Clone, Copy, Debug, PartialEq)] 179 | pub enum EventControl { 180 | /// do not store an tx event 181 | DoNotStore, 182 | /// store transmit events 183 | Store, 184 | } 185 | impl From for bool { 186 | #[inline(always)] 187 | fn from(e: EventControl) -> Self { 188 | e as u8 != 0 189 | } 190 | } 191 | 192 | /// If an received message matched any filters 193 | #[derive(Clone, Copy, Debug, PartialEq)] 194 | pub enum FilterFrameMatch { 195 | /// This did match filter 196 | DidMatch(u8), 197 | /// This received frame did not match any specific filters 198 | DidNotMatch, 199 | } 200 | 201 | /// Type of filter to be used 202 | #[derive(Clone, Copy, Debug, PartialEq)] 203 | pub enum FilterType { 204 | /// Filter uses the range between two id's 205 | RangeFilter = 0b00, 206 | /// The filter matches on two specific id's (or one ID checked twice) 207 | DualIdFilter = 0b01, 208 | /// Filter is using a bitmask 209 | ClassicFilter = 0b10, 210 | /// Filter is disabled 211 | FilterDisabled = 0b11, 212 | } 213 | 214 | #[derive(Clone, Copy, Debug, PartialEq)] 215 | pub enum FilterElementConfig { 216 | /// Filter is disabled 217 | DisableFilterElement = 0b000, 218 | /// Store a matching message in FIFO 0 219 | StoreInFifo0 = 0b001, 220 | /// Store a matching message in FIFO 1 221 | StoreInFifo1 = 0b010, 222 | /// Reject a matching message 223 | Reject = 0b011, 224 | /// Flag that a priority message has been received, *But do note store!*?? 225 | SetPriority = 0b100, 226 | /// Flag and store message in FIFO 0 227 | SetPriorityAndStoreInFifo0 = 0b101, 228 | /// Flag and store message in FIFO 1 229 | SetPriorityAndStoreInFifo1 = 0b110, 230 | //_Unused = 0b111, 231 | } 232 | -------------------------------------------------------------------------------- /src/message_ram/extended_filter.rs: -------------------------------------------------------------------------------- 1 | #![allow(non_camel_case_types)] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | 5 | use super::common::{ESFEC_R, ESFT_R}; 6 | use super::enums::{FilterElementConfig, FilterType}; 7 | use super::generic; 8 | 9 | #[doc = "Reader of register ExtendedFilter"] 10 | pub(crate) type R = generic::R; 11 | #[doc = "Writer for register ExtendedFilter"] 12 | pub(crate) type W = generic::W; 13 | #[doc = "Register ExtendedFilter `reset()`'s"] 14 | impl generic::ResetValue for super::ExtendedFilter { 15 | type Type = super::ExtendedFilterType; 16 | #[inline(always)] 17 | fn reset_value() -> Self::Type { 18 | // Sets filter element to Disabled 19 | [0x0, 0x0] 20 | } 21 | } 22 | 23 | #[doc = "Reader of field `EFID2`"] 24 | pub(crate) type EFID2_R = generic::R; 25 | #[doc = "Write proxy for field `EFID2`"] 26 | pub(crate) struct EFID2_W<'a> { 27 | w: &'a mut W, 28 | } 29 | impl<'a> EFID2_W<'a> { 30 | #[doc = r"Writes raw bits to the field"] 31 | #[inline(always)] 32 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 33 | self.w.bits[1] = 34 | (self.w.bits[1] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF); 35 | self.w 36 | } 37 | } 38 | 39 | #[doc = "Reader of field `EFID1`"] 40 | pub(crate) type EFID1_R = generic::R; 41 | #[doc = "Write proxy for field `EFID1`"] 42 | pub(crate) struct EFID1_W<'a> { 43 | w: &'a mut W, 44 | } 45 | impl<'a> EFID1_W<'a> { 46 | #[doc = r"Writes raw bits to the field"] 47 | #[inline(always)] 48 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 49 | self.w.bits[0] = 50 | (self.w.bits[0] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF); 51 | self.w 52 | } 53 | } 54 | 55 | #[doc = "Write proxy for field `EFEC`"] 56 | pub(crate) struct EFEC_W<'a> { 57 | w: &'a mut W, 58 | } 59 | impl<'a> EFEC_W<'a> { 60 | #[doc = r"Writes raw bits to the field"] 61 | #[inline(always)] 62 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 63 | self.w.bits[0] = 64 | (self.w.bits[0] & !(0x07 << 29)) | (((value as u32) & 0x07) << 29); 65 | self.w 66 | } 67 | #[doc = r"Sets the field according to FilterElementConfig"] 68 | #[inline(always)] 69 | pub fn set_filter_element_config(self, fec: FilterElementConfig) -> &'a mut W { 70 | //SAFETY: FilterElementConfig only be valid options 71 | unsafe { self.bits(fec as u8) } 72 | } 73 | } 74 | 75 | #[doc = "Write proxy for field `EFT`"] 76 | pub(crate) struct EFT_W<'a> { 77 | w: &'a mut W, 78 | } 79 | impl<'a> EFT_W<'a> { 80 | #[doc = r"Sets the field according the FilterType"] 81 | #[inline(always)] 82 | pub fn set_filter_type(self, filter: FilterType) -> &'a mut W { 83 | //SAFETY: FilterType only be valid options 84 | unsafe { self.bits(filter as u8) } 85 | } 86 | #[doc = r"Writes raw bits to the field"] 87 | #[inline(always)] 88 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 89 | self.w.bits[1] = 90 | (self.w.bits[1] & !(0x03 << 30)) | (((value as u32) & 0x03) << 30); 91 | self.w 92 | } 93 | } 94 | 95 | impl R { 96 | #[doc = "Byte 0 - Bits 0:28 - EFID1"] 97 | #[inline(always)] 98 | pub fn sfid1(&self) -> EFID1_R { 99 | EFID1_R::new(((self.bits[0]) & 0x1FFFFFFF) as u32) 100 | } 101 | #[doc = "Byte 0 - Bits 29:31 - EFEC"] 102 | #[inline(always)] 103 | pub fn efec(&self) -> ESFEC_R { 104 | ESFEC_R::new(((self.bits[0] >> 29) & 0x07) as u8) 105 | } 106 | #[doc = "Byte 1 - Bits 0:28 - EFID2"] 107 | #[inline(always)] 108 | pub fn sfid2(&self) -> EFID2_R { 109 | EFID2_R::new(((self.bits[1]) & 0x1FFFFFFF) as u32) 110 | } 111 | #[doc = "Byte 1 - Bits 30:31 - EFT"] 112 | #[inline(always)] 113 | pub fn eft(&self) -> ESFT_R { 114 | ESFT_R::new(((self.bits[1] >> 30) & 0x03) as u8) 115 | } 116 | } 117 | impl W { 118 | #[doc = "Byte 0 - Bits 0:28 - EFID1"] 119 | #[inline(always)] 120 | pub fn efid1(&mut self) -> EFID1_W { 121 | EFID1_W { w: self } 122 | } 123 | #[doc = "Byte 0 - Bits 29:31 - EFEC"] 124 | #[inline(always)] 125 | pub fn efec(&mut self) -> EFEC_W { 126 | EFEC_W { w: self } 127 | } 128 | #[doc = "Byte 1 - Bits 0:28 - EFID2"] 129 | #[inline(always)] 130 | pub fn efid2(&mut self) -> EFID2_W { 131 | EFID2_W { w: self } 132 | } 133 | #[doc = "Byte 1 - Bits 30:31 - EFT"] 134 | #[inline(always)] 135 | pub fn eft(&mut self) -> EFT_W { 136 | EFT_W { w: self } 137 | } 138 | } 139 | -------------------------------------------------------------------------------- /src/message_ram/generic.rs: -------------------------------------------------------------------------------- 1 | use core::marker; 2 | 3 | ///This trait shows that register has `read` method 4 | /// 5 | ///Registers marked with `Writable` can be also `modify`'ed 6 | pub trait Readable {} 7 | 8 | ///This trait shows that register has `write`, `write_with_zero` and `reset` method 9 | /// 10 | ///Registers marked with `Readable` can be also `modify`'ed 11 | pub trait Writable {} 12 | 13 | ///Reset value of the register 14 | /// 15 | ///This value is initial value for `write` method. 16 | ///It can be also directly writed to register by `reset` method. 17 | pub trait ResetValue { 18 | ///Register size 19 | type Type; 20 | ///Reset value of the register 21 | fn reset_value() -> Self::Type; 22 | } 23 | 24 | ///This structure provides volatile access to register 25 | pub struct Reg { 26 | register: vcell::VolatileCell, 27 | _marker: marker::PhantomData, 28 | } 29 | 30 | unsafe impl Send for Reg {} 31 | 32 | impl Reg 33 | where 34 | Self: Readable, 35 | U: Copy, 36 | { 37 | ///Reads the contents of `Readable` register 38 | /// 39 | ///You can read the contents of a register in such way: 40 | ///```ignore 41 | ///let bits = periph.reg.read().bits(); 42 | ///``` 43 | ///or get the content of a particular field of a register. 44 | ///```ignore 45 | ///let reader = periph.reg.read(); 46 | ///let bits = reader.field1().bits(); 47 | ///let flag = reader.field2().bit_is_set(); 48 | ///``` 49 | #[inline(always)] 50 | pub fn read(&self) -> R { 51 | R { 52 | bits: self.register.get(), 53 | _reg: marker::PhantomData, 54 | } 55 | } 56 | } 57 | 58 | impl Reg 59 | where 60 | Self: ResetValue + Writable, 61 | U: Copy, 62 | { 63 | ///Writes the reset value to `Writable` register 64 | /// 65 | ///Resets the register to its initial state 66 | #[inline(always)] 67 | pub fn reset(&self) { 68 | self.register.set(Self::reset_value()) 69 | } 70 | } 71 | 72 | impl Reg 73 | where 74 | Self: ResetValue + Writable, 75 | U: Copy, 76 | { 77 | ///Writes bits to `Writable` register 78 | /// 79 | ///You can write raw bits into a register: 80 | ///```ignore 81 | ///periph.reg.write(|w| unsafe { w.bits(rawbits) }); 82 | ///``` 83 | ///or write only the fields you need: 84 | ///```ignore 85 | ///periph.reg.write(|w| w 86 | /// .field1().bits(newfield1bits) 87 | /// .field2().set_bit() 88 | /// .field3().variant(VARIANT) 89 | ///); 90 | ///``` 91 | ///Other fields will have reset value. 92 | #[inline(always)] 93 | pub fn write(&self, f: F) 94 | where 95 | F: FnOnce(&mut W) -> &mut W, 96 | { 97 | self.register.set( 98 | f(&mut W { 99 | bits: Self::reset_value(), 100 | _reg: marker::PhantomData, 101 | }) 102 | .bits, 103 | ); 104 | } 105 | } 106 | 107 | impl Reg 108 | where 109 | Self: Writable, 110 | U: Copy + Default, 111 | { 112 | ///Writes Zero to `Writable` register 113 | /// 114 | ///Similar to `write`, but unused bits will contain 0. 115 | #[inline(always)] 116 | pub fn write_with_zero(&self, f: F) 117 | where 118 | F: FnOnce(&mut W) -> &mut W, 119 | { 120 | self.register.set( 121 | f(&mut W { 122 | bits: U::default(), 123 | _reg: marker::PhantomData, 124 | }) 125 | .bits, 126 | ); 127 | } 128 | } 129 | 130 | impl Reg 131 | where 132 | Self: Readable + Writable, 133 | U: Copy, 134 | { 135 | ///Modifies the contents of the register 136 | /// 137 | ///E.g. to do a read-modify-write sequence to change parts of a register: 138 | ///```ignore 139 | ///periph.reg.modify(|r, w| unsafe { w.bits( 140 | /// r.bits() | 3 141 | ///) }); 142 | ///``` 143 | ///or 144 | ///```ignore 145 | ///periph.reg.modify(|_, w| w 146 | /// .field1().bits(newfield1bits) 147 | /// .field2().set_bit() 148 | /// .field3().variant(VARIANT) 149 | ///); 150 | ///``` 151 | ///Other fields will have value they had before call `modify`. 152 | #[inline(always)] 153 | pub fn modify(&self, f: F) 154 | where 155 | for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, 156 | { 157 | let bits = self.register.get(); 158 | self.register.set( 159 | f( 160 | &R { 161 | bits, 162 | _reg: marker::PhantomData, 163 | }, 164 | &mut W { 165 | bits, 166 | _reg: marker::PhantomData, 167 | }, 168 | ) 169 | .bits, 170 | ); 171 | } 172 | } 173 | 174 | ///Register/field reader 175 | /// 176 | ///Result of the [`read`](Reg::read) method of a register. 177 | ///Also it can be used in the [`modify`](Reg::read) method 178 | pub struct R { 179 | pub(crate) bits: U, 180 | _reg: marker::PhantomData, 181 | } 182 | 183 | impl R 184 | where 185 | U: Copy, 186 | { 187 | ///Create new instance of reader 188 | #[inline(always)] 189 | pub(crate) fn new(bits: U) -> Self { 190 | Self { 191 | bits, 192 | _reg: marker::PhantomData, 193 | } 194 | } 195 | ///Read raw bits from register/field 196 | #[inline(always)] 197 | pub fn bits(&self) -> U { 198 | self.bits 199 | } 200 | } 201 | 202 | impl PartialEq for R 203 | where 204 | U: PartialEq, 205 | FI: Copy + Into, 206 | { 207 | #[inline(always)] 208 | fn eq(&self, other: &FI) -> bool { 209 | self.bits.eq(&(*other).into()) 210 | } 211 | } 212 | 213 | impl R { 214 | ///Value of the field as raw bits 215 | #[inline(always)] 216 | pub fn bit(&self) -> bool { 217 | self.bits 218 | } 219 | ///Returns `true` if the bit is clear (0) 220 | #[inline(always)] 221 | pub fn bit_is_clear(&self) -> bool { 222 | !self.bit() 223 | } 224 | ///Returns `true` if the bit is set (1) 225 | #[inline(always)] 226 | pub fn bit_is_set(&self) -> bool { 227 | self.bit() 228 | } 229 | } 230 | 231 | ///Register writer 232 | /// 233 | ///Used as an argument to the closures in the [`write`](Reg::write) and [`modify`](Reg::modify) methods of the register 234 | pub struct W { 235 | ///Writable bits 236 | pub(crate) bits: U, 237 | _reg: marker::PhantomData, 238 | } 239 | 240 | impl W { 241 | ///Writes raw bits to the register 242 | #[inline(always)] 243 | pub unsafe fn bits(&mut self, bits: U) -> &mut Self { 244 | self.bits = bits; 245 | self 246 | } 247 | } 248 | -------------------------------------------------------------------------------- /src/message_ram/rxfifo_element.rs: -------------------------------------------------------------------------------- 1 | #![allow(non_camel_case_types)] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | 5 | use super::common::{BRS_R, DLC_R, ESI_R, FDF_R, ID_R, RTR_R, XTD_R}; 6 | use super::enums::{DataLength, FilterFrameMatch, FrameFormat}; 7 | use super::generic; 8 | 9 | #[doc = "Reader of register RxFifoElement"] 10 | pub(crate) type R = 11 | generic::R; 12 | // #[doc = "Writer for register ExtendedFilter"] 13 | // pub(crate) type W = generic::W; 14 | #[doc = "Register ExtendedFilter `reset()`'s"] 15 | impl generic::ResetValue for super::RxFifoElementHeader { 16 | type Type = super::RxFifoElementHeaderType; 17 | #[inline(always)] 18 | fn reset_value() -> Self::Type { 19 | [0x0, 0x0] 20 | } 21 | } 22 | 23 | #[doc = "Reader of field `RXTS`"] 24 | pub(crate) type RXTS_R = generic::R; 25 | 26 | #[doc = "Reader of field `FIDX`"] 27 | pub(crate) type FIDX_R = generic::R; 28 | 29 | pub(crate) struct _ANMF; 30 | #[doc = "Reader of field `ANMF`"] 31 | pub(crate) type ANMF_R = generic::R; 32 | impl ANMF_R { 33 | pub fn is_matching_frame(&self) -> bool { 34 | self.bit_is_clear() 35 | } 36 | } 37 | 38 | impl R { 39 | #[doc = "Byte 0 - Bits 0:28 - ID"] 40 | #[inline(always)] 41 | pub fn id(&self) -> ID_R { 42 | ID_R::new(((self.bits[0]) & 0x1FFFFFFF) as u32) 43 | } 44 | #[doc = "Byte 0 - Bit 29 - RTR"] 45 | #[inline(always)] 46 | pub fn rtr(&self) -> RTR_R { 47 | RTR_R::new(((self.bits[0] >> 29) & 0x01) != 0) 48 | } 49 | #[doc = "Byte 0 - Bit 30 - XTD"] 50 | #[inline(always)] 51 | pub fn xtd(&self) -> XTD_R { 52 | XTD_R::new(((self.bits[0] >> 30) & 0x01) != 0) 53 | } 54 | #[doc = "Byte 0 - Bit 30 - ESI"] 55 | #[inline(always)] 56 | pub fn esi(&self) -> ESI_R { 57 | ESI_R::new(((self.bits[0] >> 31) & 0x01) != 0) 58 | } 59 | #[doc = "Byte 1 - Bits 0:15 - RXTS"] 60 | #[inline(always)] 61 | pub fn txts(&self) -> RXTS_R { 62 | RXTS_R::new(((self.bits[1]) & 0xFFFF) as u16) 63 | } 64 | #[doc = "Byte 1 - Bits 16:19 - DLC"] 65 | #[inline(always)] 66 | pub fn dlc(&self) -> DLC_R { 67 | DLC_R::new(((self.bits[1] >> 16) & 0x0F) as u8) 68 | } 69 | #[doc = "Byte 1 - Bits 20 - BRS"] 70 | #[inline(always)] 71 | pub fn brs(&self) -> BRS_R { 72 | BRS_R::new(((self.bits[1] >> 20) & 0x01) != 0) 73 | } 74 | #[doc = "Byte 1 - Bits 20 - FDF"] 75 | #[inline(always)] 76 | pub fn fdf(&self) -> FDF_R { 77 | FDF_R::new(((self.bits[1] >> 21) & 0x01) != 0) 78 | } 79 | #[doc = "Byte 1 - Bits 24:30 - FIDX"] 80 | #[inline(always)] 81 | pub fn fidx(&self) -> FIDX_R { 82 | FIDX_R::new(((self.bits[1] >> 24) & 0xFF) as u8) 83 | } 84 | #[doc = "Byte 1 - Bits 31 - ANMF"] 85 | #[inline(always)] 86 | pub fn anmf(&self) -> ANMF_R { 87 | ANMF_R::new(((self.bits[1] >> 31) & 0x01) != 0) 88 | } 89 | pub fn to_data_length(&self) -> DataLength { 90 | let dlc = self.dlc().bits(); 91 | let ff = self.fdf().frame_format(); 92 | let len = if ff == FrameFormat::Fdcan { 93 | // See RM0433 Rev 7 Table 475. DLC coding 94 | match dlc { 95 | 0..=8 => dlc, 96 | 9 => 12, 97 | 10 => 16, 98 | 11 => 20, 99 | 12 => 24, 100 | 13 => 32, 101 | 14 => 48, 102 | 15 => 64, 103 | _ => panic!("DLC > 15"), 104 | } 105 | } else { 106 | match dlc { 107 | 0..=8 => dlc, 108 | 9..=15 => 8, 109 | _ => panic!("DLC > 15"), 110 | } 111 | }; 112 | DataLength::new(len, ff) 113 | } 114 | pub fn to_filter_match(&self) -> FilterFrameMatch { 115 | if self.anmf().is_matching_frame() { 116 | FilterFrameMatch::DidMatch(self.fidx().bits()) 117 | } else { 118 | FilterFrameMatch::DidNotMatch 119 | } 120 | } 121 | } 122 | -------------------------------------------------------------------------------- /src/message_ram/standard_filter.rs: -------------------------------------------------------------------------------- 1 | #![allow(non_camel_case_types)] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | 5 | use super::common::{ESFEC_R, ESFT_R}; 6 | use super::enums::{FilterElementConfig, FilterType}; 7 | use super::generic; 8 | 9 | #[doc = "Reader of register StandardFilter"] 10 | pub(crate) type R = generic::R; 11 | #[doc = "Writer for register StandardFilter"] 12 | pub(crate) type W = generic::W; 13 | #[doc = "Register StandardFilter `reset()`'s with value 0xC0000"] 14 | impl generic::ResetValue for super::StandardFilter { 15 | type Type = super::StandardFilterType; 16 | #[inline(always)] 17 | fn reset_value() -> Self::Type { 18 | // Sets filter element to Disabled 19 | 0xC000 20 | } 21 | } 22 | 23 | #[doc = "Reader of field `SFID2`"] 24 | pub(crate) type SFID2_R = generic::R; 25 | #[doc = "Write proxy for field `SFID2`"] 26 | pub(crate) struct SFID2_W<'a> { 27 | w: &'a mut W, 28 | } 29 | impl<'a> SFID2_W<'a> { 30 | #[doc = r"Writes raw bits to the field"] 31 | #[inline(always)] 32 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 33 | self.w.bits = (self.w.bits & !(0x07ff)) | ((value as u32) & 0x07ff); 34 | self.w 35 | } 36 | } 37 | 38 | #[doc = "Reader of field `SFID1`"] 39 | pub(crate) type SFID1_R = generic::R; 40 | #[doc = "Write proxy for field `SFID1`"] 41 | pub(crate) struct SFID1_W<'a> { 42 | w: &'a mut W, 43 | } 44 | impl<'a> SFID1_W<'a> { 45 | #[doc = r"Writes raw bits to the field"] 46 | #[inline(always)] 47 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 48 | self.w.bits = 49 | (self.w.bits & !(0x07ff << 16)) | (((value as u32) & 0x07ff) << 16); 50 | self.w 51 | } 52 | } 53 | 54 | #[doc = "Write proxy for field `SFEC`"] 55 | pub(crate) struct SFEC_W<'a> { 56 | w: &'a mut W, 57 | } 58 | impl<'a> SFEC_W<'a> { 59 | #[doc = r"Writes raw bits to the field"] 60 | #[inline(always)] 61 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 62 | self.w.bits = (self.w.bits & !(0x07 << 27)) | (((value as u32) & 0x07) << 27); 63 | self.w 64 | } 65 | #[doc = r"Sets the field according to FilterElementConfig"] 66 | #[inline(always)] 67 | pub fn set_filter_element_config(self, fec: FilterElementConfig) -> &'a mut W { 68 | //SAFETY: FilterElementConfig only be valid options 69 | unsafe { self.bits(fec as u8) } 70 | } 71 | } 72 | 73 | #[doc = "Write proxy for field `SFT`"] 74 | pub(crate) struct SFT_W<'a> { 75 | w: &'a mut W, 76 | } 77 | impl<'a> SFT_W<'a> { 78 | #[doc = r"Sets the field according the FilterType"] 79 | #[inline(always)] 80 | pub fn set_filter_type(self, filter: FilterType) -> &'a mut W { 81 | //SAFETY: FilterType only be valid options 82 | unsafe { self.bits(filter as u8) } 83 | } 84 | #[doc = r"Writes raw bits to the field"] 85 | #[inline(always)] 86 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 87 | self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30); 88 | self.w 89 | } 90 | } 91 | 92 | impl R { 93 | #[doc = "Bits 0:10 - SFID2"] 94 | #[inline(always)] 95 | pub fn sfid2(&self) -> SFID2_R { 96 | SFID2_R::new((self.bits & 0x07ff) as u16) 97 | } 98 | #[doc = "Bits 16:26 - SFID1"] 99 | #[inline(always)] 100 | pub fn sfid1(&self) -> SFID1_R { 101 | SFID1_R::new(((self.bits >> 16) & 0x07ff) as u16) 102 | } 103 | #[doc = "Bits 27:29 - SFEC"] 104 | #[inline(always)] 105 | pub fn sfec(&self) -> ESFEC_R { 106 | ESFEC_R::new(((self.bits >> 27) & 0x07) as u8) 107 | } 108 | #[doc = "Bits 30:31 - SFT"] 109 | #[inline(always)] 110 | pub fn sft(&self) -> ESFT_R { 111 | ESFT_R::new(((self.bits >> 30) & 0x03) as u8) 112 | } 113 | } 114 | impl W { 115 | #[doc = "Bits 0:10 - SFID2"] 116 | #[inline(always)] 117 | pub fn sfid2(&mut self) -> SFID2_W { 118 | SFID2_W { w: self } 119 | } 120 | #[doc = "Bits 16:26 - SFID1"] 121 | #[inline(always)] 122 | pub fn sfid1(&mut self) -> SFID1_W { 123 | SFID1_W { w: self } 124 | } 125 | #[doc = "Bits 27:29 - SFEC"] 126 | #[inline(always)] 127 | pub fn sfec(&mut self) -> SFEC_W { 128 | SFEC_W { w: self } 129 | } 130 | #[doc = "Bits 30:31 - SFT"] 131 | #[inline(always)] 132 | pub fn sft(&mut self) -> SFT_W { 133 | SFT_W { w: self } 134 | } 135 | } 136 | -------------------------------------------------------------------------------- /src/message_ram/txevent_element.rs: -------------------------------------------------------------------------------- 1 | #![allow(non_camel_case_types)] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | 5 | use super::common::{BRS_R, DLC_R, ESI_R, RTR_R, XTD_R}; 6 | use super::generic; 7 | 8 | #[doc = "Reader of register TxEventElement"] 9 | pub(crate) type R = generic::R; 10 | // #[doc = "Writer for register TxEventElement"] 11 | // pub(crate) type W = generic::W; 12 | #[doc = "Register TxEventElement `reset()`'s"] 13 | impl generic::ResetValue for super::TxEventElement { 14 | type Type = super::TxEventElementType; 15 | #[inline(always)] 16 | fn reset_value() -> Self::Type { 17 | [0, 0] 18 | } 19 | } 20 | 21 | #[doc = "Reader of field `ID`"] 22 | pub(crate) type ID_R = generic::R; 23 | 24 | #[doc = "Reader of field `TXTS`"] 25 | pub(crate) type TXTS_R = generic::R; 26 | 27 | #[derive(Clone, Copy, Debug, PartialEq)] 28 | pub(crate) enum DataLengthFormat { 29 | StandardLength = 0, 30 | FDCANLength = 1, 31 | } 32 | impl From for bool { 33 | #[inline(always)] 34 | fn from(dlf: DataLengthFormat) -> Self { 35 | dlf as u8 != 0 36 | } 37 | } 38 | 39 | #[doc = "Reader of field `EDL`"] 40 | pub(crate) type EDL_R = generic::R; 41 | impl EDL_R { 42 | pub fn data_length_format(&self) -> DataLengthFormat { 43 | match self.bits() { 44 | false => DataLengthFormat::StandardLength, 45 | true => DataLengthFormat::FDCANLength, 46 | } 47 | } 48 | pub fn is_standard_length(&self) -> bool { 49 | *self == DataLengthFormat::StandardLength 50 | } 51 | pub fn is_fdcan_length(&self) -> bool { 52 | *self == DataLengthFormat::FDCANLength 53 | } 54 | } 55 | 56 | #[derive(Clone, Copy, Debug, PartialEq)] 57 | pub(crate) enum EventType { 58 | //_Reserved = 0b00, 59 | TxEvent = 0b01, 60 | TxDespiteAbort = 0b10, 61 | //_Reserved = 0b10, 62 | } 63 | 64 | #[doc = "Reader of field `EFC`"] 65 | pub(crate) type EFC_R = generic::R; 66 | impl EFC_R { 67 | pub fn event_type(&self) -> EventType { 68 | match self.bits() { 69 | 0b01 => EventType::TxEvent, 70 | 0b10 => EventType::TxDespiteAbort, 71 | _ => unimplemented!(), 72 | } 73 | } 74 | pub fn is_tx_event(&self) -> bool { 75 | self.event_type() == EventType::TxEvent 76 | } 77 | pub fn is_despite_abort(&self) -> bool { 78 | self.event_type() == EventType::TxDespiteAbort 79 | } 80 | } 81 | 82 | #[doc = "Reader of field `MM`"] 83 | pub(crate) type MM_R = generic::R; 84 | 85 | impl R { 86 | #[doc = "Byte 0 - Bits 0:28 - ID"] 87 | #[inline(always)] 88 | pub fn id(&self) -> ID_R { 89 | ID_R::new(((self.bits[0]) & 0x1FFFFFFF) as u32) 90 | } 91 | #[doc = "Byte 0 - Bit 29 - RTR"] 92 | #[inline(always)] 93 | pub fn rtr(&self) -> RTR_R { 94 | RTR_R::new(((self.bits[0] >> 29) & 0x01) != 0) 95 | } 96 | #[doc = "Byte 0 - Bit 30 - XTD"] 97 | #[inline(always)] 98 | pub fn xtd(&self) -> XTD_R { 99 | XTD_R::new(((self.bits[0] >> 30) & 0x01) != 0) 100 | } 101 | #[doc = "Byte 0 - Bit 30 - ESI"] 102 | #[inline(always)] 103 | pub fn esi(&self) -> ESI_R { 104 | ESI_R::new(((self.bits[0] >> 31) & 0x01) != 0) 105 | } 106 | #[doc = "Byte 1 - Bits 0:15 - TXTS"] 107 | #[inline(always)] 108 | pub fn txts(&self) -> TXTS_R { 109 | TXTS_R::new(((self.bits[1]) & 0xFFFF) as u16) 110 | } 111 | #[doc = "Byte 1 - Bits 16:19 - DLC"] 112 | #[inline(always)] 113 | pub fn dlc(&self) -> DLC_R { 114 | DLC_R::new(((self.bits[1] >> 16) & 0x0F) as u8) 115 | } 116 | #[doc = "Byte 1 - Bits 20 - BRS"] 117 | #[inline(always)] 118 | pub fn brs(&self) -> BRS_R { 119 | BRS_R::new(((self.bits[1] >> 20) & 0x01) != 0) 120 | } 121 | #[doc = "Byte 1 - Bits 21 - EDL"] 122 | #[inline(always)] 123 | pub fn edl(&self) -> EDL_R { 124 | EDL_R::new(((self.bits[1] >> 21) & 0x01) != 0) 125 | } 126 | #[doc = "Byte 1 - Bits 22:23 - EFC"] 127 | #[inline(always)] 128 | pub fn efc(&self) -> EFC_R { 129 | EFC_R::new(((self.bits[1] >> 22) & 0x03) as u8) 130 | } 131 | #[doc = "Byte 1 - Bits 24:31 - MM"] 132 | #[inline(always)] 133 | pub fn mm(&self) -> MM_R { 134 | MM_R::new(((self.bits[1] >> 24) & 0xFF) as u8) 135 | } 136 | } 137 | -------------------------------------------------------------------------------- /src/pac/fdcan/crel.rs: -------------------------------------------------------------------------------- 1 | ///Register `CREL` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `REL` reader - Core release 17 | pub struct REL_R(crate::FieldReader); 18 | impl REL_R { 19 | pub(crate) fn new(bits: u8) -> Self { 20 | REL_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for REL_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | ///Field `STEP` reader - Step of Core release 31 | pub struct STEP_R(crate::FieldReader); 32 | impl STEP_R { 33 | pub(crate) fn new(bits: u8) -> Self { 34 | STEP_R(crate::FieldReader::new(bits)) 35 | } 36 | } 37 | impl core::ops::Deref for STEP_R { 38 | type Target = crate::FieldReader; 39 | #[inline(always)] 40 | fn deref(&self) -> &Self::Target { 41 | &self.0 42 | } 43 | } 44 | ///Field `SUBSTEP` reader - Sub-step of Core release 45 | pub struct SUBSTEP_R(crate::FieldReader); 46 | impl SUBSTEP_R { 47 | pub(crate) fn new(bits: u8) -> Self { 48 | SUBSTEP_R(crate::FieldReader::new(bits)) 49 | } 50 | } 51 | impl core::ops::Deref for SUBSTEP_R { 52 | type Target = crate::FieldReader; 53 | #[inline(always)] 54 | fn deref(&self) -> &Self::Target { 55 | &self.0 56 | } 57 | } 58 | ///Field `YEAR` reader - Timestamp Year 59 | pub struct YEAR_R(crate::FieldReader); 60 | impl YEAR_R { 61 | pub(crate) fn new(bits: u8) -> Self { 62 | YEAR_R(crate::FieldReader::new(bits)) 63 | } 64 | } 65 | impl core::ops::Deref for YEAR_R { 66 | type Target = crate::FieldReader; 67 | #[inline(always)] 68 | fn deref(&self) -> &Self::Target { 69 | &self.0 70 | } 71 | } 72 | ///Field `MON` reader - Timestamp Month 73 | pub struct MON_R(crate::FieldReader); 74 | impl MON_R { 75 | pub(crate) fn new(bits: u8) -> Self { 76 | MON_R(crate::FieldReader::new(bits)) 77 | } 78 | } 79 | impl core::ops::Deref for MON_R { 80 | type Target = crate::FieldReader; 81 | #[inline(always)] 82 | fn deref(&self) -> &Self::Target { 83 | &self.0 84 | } 85 | } 86 | ///Field `DAY` reader - Timestamp Day 87 | pub struct DAY_R(crate::FieldReader); 88 | impl DAY_R { 89 | pub(crate) fn new(bits: u8) -> Self { 90 | DAY_R(crate::FieldReader::new(bits)) 91 | } 92 | } 93 | impl core::ops::Deref for DAY_R { 94 | type Target = crate::FieldReader; 95 | #[inline(always)] 96 | fn deref(&self) -> &Self::Target { 97 | &self.0 98 | } 99 | } 100 | impl R { 101 | ///Bits 28:31 - Core release 102 | #[inline(always)] 103 | pub fn rel(&self) -> REL_R { 104 | REL_R::new(((self.bits >> 28) & 0x0f) as u8) 105 | } 106 | ///Bits 24:27 - Step of Core release 107 | #[inline(always)] 108 | pub fn step(&self) -> STEP_R { 109 | STEP_R::new(((self.bits >> 24) & 0x0f) as u8) 110 | } 111 | ///Bits 20:23 - Sub-step of Core release 112 | #[inline(always)] 113 | pub fn substep(&self) -> SUBSTEP_R { 114 | SUBSTEP_R::new(((self.bits >> 20) & 0x0f) as u8) 115 | } 116 | ///Bits 16:19 - Timestamp Year 117 | #[inline(always)] 118 | pub fn year(&self) -> YEAR_R { 119 | YEAR_R::new(((self.bits >> 16) & 0x0f) as u8) 120 | } 121 | ///Bits 8:15 - Timestamp Month 122 | #[inline(always)] 123 | pub fn mon(&self) -> MON_R { 124 | MON_R::new(((self.bits >> 8) & 0xff) as u8) 125 | } 126 | ///Bits 0:7 - Timestamp Day 127 | #[inline(always)] 128 | pub fn day(&self) -> DAY_R { 129 | DAY_R::new((self.bits & 0xff) as u8) 130 | } 131 | } 132 | ///FDCAN Core Release Register 133 | /// 134 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 135 | /// 136 | ///For information about available fields see [crel](index.html) module 137 | pub struct CREL_SPEC; 138 | impl crate::RegisterSpec for CREL_SPEC { 139 | type Ux = u32; 140 | } 141 | ///`read()` method returns [crel::R](R) reader structure 142 | impl crate::Readable for CREL_SPEC { 143 | type Reader = R; 144 | } 145 | ///`reset()` method sets CREL to value 0 146 | impl crate::Resettable for CREL_SPEC { 147 | #[inline(always)] 148 | fn reset_value() -> Self::Ux { 149 | 0 150 | } 151 | } 152 | -------------------------------------------------------------------------------- /src/pac/fdcan/ecr.rs: -------------------------------------------------------------------------------- 1 | ///Register `ECR` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `ECR` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `CEL` reader - AN Error Logging 38 | pub struct CEL_R(crate::FieldReader); 39 | impl CEL_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | CEL_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for CEL_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `CEL` writer - AN Error Logging 52 | pub struct CEL_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> CEL_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); 60 | self.w 61 | } 62 | } 63 | ///Field `RP` reader - Receive Error Passive 64 | pub struct RP_R(crate::FieldReader); 65 | impl RP_R { 66 | pub(crate) fn new(bits: bool) -> Self { 67 | RP_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for RP_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `RP` writer - Receive Error Passive 78 | pub struct RP_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> RP_W<'a> { 82 | ///Sets the field bit 83 | #[inline(always)] 84 | pub fn set_bit(self) -> &'a mut W { 85 | self.bit(true) 86 | } 87 | ///Clears the field bit 88 | #[inline(always)] 89 | pub fn clear_bit(self) -> &'a mut W { 90 | self.bit(false) 91 | } 92 | ///Writes raw bits to the field 93 | #[inline(always)] 94 | pub fn bit(self, value: bool) -> &'a mut W { 95 | self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); 96 | self.w 97 | } 98 | } 99 | ///Field `REC` reader - Receive Error Counter 100 | pub struct REC_R(crate::FieldReader); 101 | impl REC_R { 102 | pub(crate) fn new(bits: u8) -> Self { 103 | REC_R(crate::FieldReader::new(bits)) 104 | } 105 | } 106 | impl core::ops::Deref for REC_R { 107 | type Target = crate::FieldReader; 108 | #[inline(always)] 109 | fn deref(&self) -> &Self::Target { 110 | &self.0 111 | } 112 | } 113 | ///Field `REC` writer - Receive Error Counter 114 | pub struct REC_W<'a> { 115 | w: &'a mut W, 116 | } 117 | impl<'a> REC_W<'a> { 118 | ///Writes raw bits to the field 119 | #[inline(always)] 120 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 121 | self.w.bits = (self.w.bits & !(0x7f << 8)) | ((value as u32 & 0x7f) << 8); 122 | self.w 123 | } 124 | } 125 | ///Field `TEC` reader - Transmit Error Counter 126 | pub struct TEC_R(crate::FieldReader); 127 | impl TEC_R { 128 | pub(crate) fn new(bits: u8) -> Self { 129 | TEC_R(crate::FieldReader::new(bits)) 130 | } 131 | } 132 | impl core::ops::Deref for TEC_R { 133 | type Target = crate::FieldReader; 134 | #[inline(always)] 135 | fn deref(&self) -> &Self::Target { 136 | &self.0 137 | } 138 | } 139 | ///Field `TEC` writer - Transmit Error Counter 140 | pub struct TEC_W<'a> { 141 | w: &'a mut W, 142 | } 143 | impl<'a> TEC_W<'a> { 144 | ///Writes raw bits to the field 145 | #[inline(always)] 146 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 147 | self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); 148 | self.w 149 | } 150 | } 151 | impl R { 152 | ///Bits 16:23 - AN Error Logging 153 | #[inline(always)] 154 | pub fn cel(&self) -> CEL_R { 155 | CEL_R::new(((self.bits >> 16) & 0xff) as u8) 156 | } 157 | ///Bit 15 - Receive Error Passive 158 | #[inline(always)] 159 | pub fn rp(&self) -> RP_R { 160 | RP_R::new(((self.bits >> 15) & 0x01) != 0) 161 | } 162 | ///Bits 8:14 - Receive Error Counter 163 | #[inline(always)] 164 | pub fn rec(&self) -> REC_R { 165 | REC_R::new(((self.bits >> 8) & 0x7f) as u8) 166 | } 167 | ///Bits 0:7 - Transmit Error Counter 168 | #[inline(always)] 169 | pub fn tec(&self) -> TEC_R { 170 | TEC_R::new((self.bits & 0xff) as u8) 171 | } 172 | } 173 | impl W { 174 | ///Bits 16:23 - AN Error Logging 175 | #[inline(always)] 176 | pub fn cel(&mut self) -> CEL_W { 177 | CEL_W { w: self } 178 | } 179 | ///Bit 15 - Receive Error Passive 180 | #[inline(always)] 181 | pub fn rp(&mut self) -> RP_W { 182 | RP_W { w: self } 183 | } 184 | ///Bits 8:14 - Receive Error Counter 185 | #[inline(always)] 186 | pub fn rec(&mut self) -> REC_W { 187 | REC_W { w: self } 188 | } 189 | ///Bits 0:7 - Transmit Error Counter 190 | #[inline(always)] 191 | pub fn tec(&mut self) -> TEC_W { 192 | TEC_W { w: self } 193 | } 194 | ///Writes raw bits to the register. 195 | #[inline(always)] 196 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 197 | self.0.bits(bits); 198 | self 199 | } 200 | } 201 | ///FDCAN Error Counter Register 202 | /// 203 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 204 | /// 205 | ///For information about available fields see [ecr](index.html) module 206 | pub struct ECR_SPEC; 207 | impl crate::RegisterSpec for ECR_SPEC { 208 | type Ux = u32; 209 | } 210 | ///`read()` method returns [ecr::R](R) reader structure 211 | impl crate::Readable for ECR_SPEC { 212 | type Reader = R; 213 | } 214 | ///`write(|w| ..)` method takes [ecr::W](W) writer structure 215 | impl crate::Writable for ECR_SPEC { 216 | type Writer = W; 217 | } 218 | ///`reset()` method sets ECR to value 0 219 | impl crate::Resettable for ECR_SPEC { 220 | #[inline(always)] 221 | fn reset_value() -> Self::Ux { 222 | 0 223 | } 224 | } 225 | -------------------------------------------------------------------------------- /src/pac/fdcan/endn.rs: -------------------------------------------------------------------------------- 1 | ///Register `ENDN` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `ETV` reader - Endiannes Test Value 17 | pub struct ETV_R(crate::FieldReader); 18 | impl ETV_R { 19 | pub(crate) fn new(bits: u32) -> Self { 20 | ETV_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for ETV_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | impl R { 31 | ///Bits 0:31 - Endiannes Test Value 32 | #[inline(always)] 33 | pub fn etv(&self) -> ETV_R { 34 | ETV_R::new((self.bits & 0xffff_ffff) as u32) 35 | } 36 | } 37 | ///FDCAN Core Release Register 38 | /// 39 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 40 | /// 41 | ///For information about available fields see [endn](index.html) module 42 | pub struct ENDN_SPEC; 43 | impl crate::RegisterSpec for ENDN_SPEC { 44 | type Ux = u32; 45 | } 46 | ///`read()` method returns [endn::R](R) reader structure 47 | impl crate::Readable for ENDN_SPEC { 48 | type Reader = R; 49 | } 50 | ///`reset()` method sets ENDN to value 0 51 | impl crate::Resettable for ENDN_SPEC { 52 | #[inline(always)] 53 | fn reset_value() -> Self::Ux { 54 | 0 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /src/pac/fdcan/hpms.rs: -------------------------------------------------------------------------------- 1 | ///Register `HPMS` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `BIDX` reader - Buffer Index 17 | pub struct BIDX_R(crate::FieldReader); 18 | impl BIDX_R { 19 | pub(crate) fn new(bits: u8) -> Self { 20 | BIDX_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for BIDX_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | ///Field `MSI` reader - Message Storage Indicator 31 | pub struct MSI_R(crate::FieldReader); 32 | impl MSI_R { 33 | pub(crate) fn new(bits: u8) -> Self { 34 | MSI_R(crate::FieldReader::new(bits)) 35 | } 36 | } 37 | impl core::ops::Deref for MSI_R { 38 | type Target = crate::FieldReader; 39 | #[inline(always)] 40 | fn deref(&self) -> &Self::Target { 41 | &self.0 42 | } 43 | } 44 | ///Field `FIDX` reader - Filter Index 45 | pub struct FIDX_R(crate::FieldReader); 46 | impl FIDX_R { 47 | pub(crate) fn new(bits: u8) -> Self { 48 | FIDX_R(crate::FieldReader::new(bits)) 49 | } 50 | } 51 | impl core::ops::Deref for FIDX_R { 52 | type Target = crate::FieldReader; 53 | #[inline(always)] 54 | fn deref(&self) -> &Self::Target { 55 | &self.0 56 | } 57 | } 58 | ///Field `FLST` reader - Filter List 59 | pub struct FLST_R(crate::FieldReader); 60 | impl FLST_R { 61 | pub(crate) fn new(bits: bool) -> Self { 62 | FLST_R(crate::FieldReader::new(bits)) 63 | } 64 | } 65 | impl core::ops::Deref for FLST_R { 66 | type Target = crate::FieldReader; 67 | #[inline(always)] 68 | fn deref(&self) -> &Self::Target { 69 | &self.0 70 | } 71 | } 72 | impl R { 73 | ///Bits 0:5 - Buffer Index 74 | #[inline(always)] 75 | pub fn bidx(&self) -> BIDX_R { 76 | BIDX_R::new((self.bits & 0x3f) as u8) 77 | } 78 | ///Bits 6:7 - Message Storage Indicator 79 | #[inline(always)] 80 | pub fn msi(&self) -> MSI_R { 81 | MSI_R::new(((self.bits >> 6) & 0x03) as u8) 82 | } 83 | ///Bits 8:14 - Filter Index 84 | #[inline(always)] 85 | pub fn fidx(&self) -> FIDX_R { 86 | FIDX_R::new(((self.bits >> 8) & 0x7f) as u8) 87 | } 88 | ///Bit 15 - Filter List 89 | #[inline(always)] 90 | pub fn flst(&self) -> FLST_R { 91 | FLST_R::new(((self.bits >> 15) & 0x01) != 0) 92 | } 93 | } 94 | ///FDCAN High Priority Message Status Register 95 | /// 96 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 97 | /// 98 | ///For information about available fields see [hpms](index.html) module 99 | pub struct HPMS_SPEC; 100 | impl crate::RegisterSpec for HPMS_SPEC { 101 | type Ux = u32; 102 | } 103 | ///`read()` method returns [hpms::R](R) reader structure 104 | impl crate::Readable for HPMS_SPEC { 105 | type Reader = R; 106 | } 107 | ///`reset()` method sets HPMS to value 0 108 | impl crate::Resettable for HPMS_SPEC { 109 | #[inline(always)] 110 | fn reset_value() -> Self::Ux { 111 | 0 112 | } 113 | } 114 | -------------------------------------------------------------------------------- /src/pac/fdcan/ile_g0_g4_l5.rs: -------------------------------------------------------------------------------- 1 | // The field names differ from the field names in G0/G4/L5 reference manual, but 2 | // match the field descriptions. The field descriptions appear to be 3 | // correct. See https://github.com/stm32-rs/fdcan/issues/4 4 | 5 | ///Register `ILE` reader 6 | pub struct R(crate::R); 7 | impl core::ops::Deref for R { 8 | type Target = crate::R; 9 | #[inline(always)] 10 | fn deref(&self) -> &Self::Target { 11 | &self.0 12 | } 13 | } 14 | impl From> for R { 15 | #[inline(always)] 16 | fn from(reader: crate::R) -> Self { 17 | R(reader) 18 | } 19 | } 20 | ///Register `ILE` writer 21 | pub struct W(crate::W); 22 | impl core::ops::Deref for W { 23 | type Target = crate::W; 24 | #[inline(always)] 25 | fn deref(&self) -> &Self::Target { 26 | &self.0 27 | } 28 | } 29 | impl core::ops::DerefMut for W { 30 | #[inline(always)] 31 | fn deref_mut(&mut self) -> &mut Self::Target { 32 | &mut self.0 33 | } 34 | } 35 | impl From> for W { 36 | #[inline(always)] 37 | fn from(writer: crate::W) -> Self { 38 | W(writer) 39 | } 40 | } 41 | ///Field `EINT1` reader - Enable Interrupt Line 1 42 | pub struct EINT1_R(crate::FieldReader); 43 | impl EINT1_R { 44 | pub(crate) fn new(bits: bool) -> Self { 45 | EINT1_R(crate::FieldReader::new(bits)) 46 | } 47 | } 48 | impl core::ops::Deref for EINT1_R { 49 | type Target = crate::FieldReader; 50 | #[inline(always)] 51 | fn deref(&self) -> &Self::Target { 52 | &self.0 53 | } 54 | } 55 | ///Field `EINT1` writer - Enable Interrupt Line 1 56 | pub struct EINT1_W<'a> { 57 | w: &'a mut W, 58 | } 59 | impl<'a> EINT1_W<'a> { 60 | ///Sets the field bit 61 | #[inline(always)] 62 | pub fn set_bit(self) -> &'a mut W { 63 | self.bit(true) 64 | } 65 | ///Clears the field bit 66 | #[inline(always)] 67 | pub fn clear_bit(self) -> &'a mut W { 68 | self.bit(false) 69 | } 70 | ///Writes raw bits to the field 71 | #[inline(always)] 72 | pub fn bit(self, value: bool) -> &'a mut W { 73 | self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); 74 | self.w 75 | } 76 | } 77 | ///Field `EINT0` reader - Enable Interrupt Line 0 78 | pub struct EINT0_R(crate::FieldReader); 79 | impl EINT0_R { 80 | pub(crate) fn new(bits: bool) -> Self { 81 | EINT0_R(crate::FieldReader::new(bits)) 82 | } 83 | } 84 | impl core::ops::Deref for EINT0_R { 85 | type Target = crate::FieldReader; 86 | #[inline(always)] 87 | fn deref(&self) -> &Self::Target { 88 | &self.0 89 | } 90 | } 91 | ///Field `EINT0` writer - Enable Interrupt Line 0 92 | pub struct EINT0_W<'a> { 93 | w: &'a mut W, 94 | } 95 | impl<'a> EINT0_W<'a> { 96 | ///Sets the field bit 97 | #[inline(always)] 98 | pub fn set_bit(self) -> &'a mut W { 99 | self.bit(true) 100 | } 101 | ///Clears the field bit 102 | #[inline(always)] 103 | pub fn clear_bit(self) -> &'a mut W { 104 | self.bit(false) 105 | } 106 | ///Writes raw bits to the field 107 | #[inline(always)] 108 | pub fn bit(self, value: bool) -> &'a mut W { 109 | self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); 110 | self.w 111 | } 112 | } 113 | impl R { 114 | ///Bit 0 - Enable Interrupt Line 1 115 | #[inline(always)] 116 | pub fn eint1(&self) -> EINT1_R { 117 | EINT1_R::new((self.bits & 0x01) != 0) 118 | } 119 | ///Bit 1 - Enable Interrupt Line 0 120 | #[inline(always)] 121 | pub fn eint0(&self) -> EINT0_R { 122 | EINT0_R::new(((self.bits >> 1) & 0x01) != 0) 123 | } 124 | } 125 | impl W { 126 | ///Bit 0 - Enable Interrupt Line 1 127 | #[inline(always)] 128 | pub fn eint1(&mut self) -> EINT1_W { 129 | EINT1_W { w: self } 130 | } 131 | ///Bit 1 - Enable Interrupt Line 0 132 | #[inline(always)] 133 | pub fn eint0(&mut self) -> EINT0_W { 134 | EINT0_W { w: self } 135 | } 136 | ///Writes raw bits to the register. 137 | #[inline(always)] 138 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 139 | self.0.bits(bits); 140 | self 141 | } 142 | } 143 | ///FDCAN Interrupt Line Enable Register 144 | /// 145 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 146 | /// 147 | ///For information about available fields see [ile](index.html) module 148 | pub struct ILE_SPEC; 149 | impl crate::RegisterSpec for ILE_SPEC { 150 | type Ux = u32; 151 | } 152 | ///`read()` method returns [ile::R](R) reader structure 153 | impl crate::Readable for ILE_SPEC { 154 | type Reader = R; 155 | } 156 | ///`write(|w| ..)` method takes [ile::W](W) writer structure 157 | impl crate::Writable for ILE_SPEC { 158 | type Writer = W; 159 | } 160 | ///`reset()` method sets ILE to value 0 161 | impl crate::Resettable for ILE_SPEC { 162 | #[inline(always)] 163 | fn reset_value() -> Self::Ux { 164 | 0 165 | } 166 | } 167 | -------------------------------------------------------------------------------- /src/pac/fdcan/ile_h7.rs: -------------------------------------------------------------------------------- 1 | ///Register `ILE` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `ILE` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `EINT0` reader - Enable Interrupt Line 0 38 | pub struct EINT0_R(crate::FieldReader); 39 | impl EINT0_R { 40 | pub(crate) fn new(bits: bool) -> Self { 41 | EINT0_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for EINT0_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `EINT0` writer - Enable Interrupt Line 0 52 | pub struct EINT0_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> EINT0_W<'a> { 56 | ///Sets the field bit 57 | #[inline(always)] 58 | pub fn set_bit(self) -> &'a mut W { 59 | self.bit(true) 60 | } 61 | ///Clears the field bit 62 | #[inline(always)] 63 | pub fn clear_bit(self) -> &'a mut W { 64 | self.bit(false) 65 | } 66 | ///Writes raw bits to the field 67 | #[inline(always)] 68 | pub fn bit(self, value: bool) -> &'a mut W { 69 | self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); 70 | self.w 71 | } 72 | } 73 | ///Field `EINT1` reader - Enable Interrupt Line 1 74 | pub struct EINT1_R(crate::FieldReader); 75 | impl EINT1_R { 76 | pub(crate) fn new(bits: bool) -> Self { 77 | EINT1_R(crate::FieldReader::new(bits)) 78 | } 79 | } 80 | impl core::ops::Deref for EINT1_R { 81 | type Target = crate::FieldReader; 82 | #[inline(always)] 83 | fn deref(&self) -> &Self::Target { 84 | &self.0 85 | } 86 | } 87 | ///Field `EINT1` writer - Enable Interrupt Line 1 88 | pub struct EINT1_W<'a> { 89 | w: &'a mut W, 90 | } 91 | impl<'a> EINT1_W<'a> { 92 | ///Sets the field bit 93 | #[inline(always)] 94 | pub fn set_bit(self) -> &'a mut W { 95 | self.bit(true) 96 | } 97 | ///Clears the field bit 98 | #[inline(always)] 99 | pub fn clear_bit(self) -> &'a mut W { 100 | self.bit(false) 101 | } 102 | ///Writes raw bits to the field 103 | #[inline(always)] 104 | pub fn bit(self, value: bool) -> &'a mut W { 105 | self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); 106 | self.w 107 | } 108 | } 109 | impl R { 110 | ///Bit 0 - Enable Interrupt Line 0 111 | #[inline(always)] 112 | pub fn eint0(&self) -> EINT0_R { 113 | EINT0_R::new((self.bits & 0x01) != 0) 114 | } 115 | ///Bit 1 - Enable Interrupt Line 1 116 | #[inline(always)] 117 | pub fn eint1(&self) -> EINT1_R { 118 | EINT1_R::new(((self.bits >> 1) & 0x01) != 0) 119 | } 120 | } 121 | impl W { 122 | ///Bit 0 - Enable Interrupt Line 0 123 | #[inline(always)] 124 | pub fn eint0(&mut self) -> EINT0_W { 125 | EINT0_W { w: self } 126 | } 127 | ///Bit 1 - Enable Interrupt Line 1 128 | #[inline(always)] 129 | pub fn eint1(&mut self) -> EINT1_W { 130 | EINT1_W { w: self } 131 | } 132 | ///Writes raw bits to the register. 133 | #[inline(always)] 134 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 135 | self.0.bits(bits); 136 | self 137 | } 138 | } 139 | ///FDCAN Interrupt Line Enable Register 140 | /// 141 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 142 | /// 143 | ///For information about available fields see [ile](index.html) module 144 | pub struct ILE_SPEC; 145 | impl crate::RegisterSpec for ILE_SPEC { 146 | type Ux = u32; 147 | } 148 | ///`read()` method returns [ile::R](R) reader structure 149 | impl crate::Readable for ILE_SPEC { 150 | type Reader = R; 151 | } 152 | ///`write(|w| ..)` method takes [ile::W](W) writer structure 153 | impl crate::Writable for ILE_SPEC { 154 | type Writer = W; 155 | } 156 | ///`reset()` method sets ILE to value 0 157 | impl crate::Resettable for ILE_SPEC { 158 | #[inline(always)] 159 | fn reset_value() -> Self::Ux { 160 | 0 161 | } 162 | } 163 | -------------------------------------------------------------------------------- /src/pac/fdcan/rwd.rs: -------------------------------------------------------------------------------- 1 | ///Register `RWD` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `WDV` reader - Watchdog value 17 | pub struct WDV_R(crate::FieldReader); 18 | impl WDV_R { 19 | pub(crate) fn new(bits: u8) -> Self { 20 | WDV_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for WDV_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | ///Field `WDC` reader - Watchdog configuration 31 | pub struct WDC_R(crate::FieldReader); 32 | impl WDC_R { 33 | pub(crate) fn new(bits: u8) -> Self { 34 | WDC_R(crate::FieldReader::new(bits)) 35 | } 36 | } 37 | impl core::ops::Deref for WDC_R { 38 | type Target = crate::FieldReader; 39 | #[inline(always)] 40 | fn deref(&self) -> &Self::Target { 41 | &self.0 42 | } 43 | } 44 | impl R { 45 | ///Bits 8:15 - Watchdog value 46 | #[inline(always)] 47 | pub fn wdv(&self) -> WDV_R { 48 | WDV_R::new(((self.bits >> 8) & 0xff) as u8) 49 | } 50 | ///Bits 0:7 - Watchdog configuration 51 | #[inline(always)] 52 | pub fn wdc(&self) -> WDC_R { 53 | WDC_R::new((self.bits & 0xff) as u8) 54 | } 55 | } 56 | ///FDCAN RAM Watchdog Register 57 | /// 58 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 59 | /// 60 | ///For information about available fields see [rwd](index.html) module 61 | pub struct RWD_SPEC; 62 | impl crate::RegisterSpec for RWD_SPEC { 63 | type Ux = u32; 64 | } 65 | ///`read()` method returns [rwd::R](R) reader structure 66 | impl crate::Readable for RWD_SPEC { 67 | type Reader = R; 68 | } 69 | ///`reset()` method sets RWD to value 0 70 | impl crate::Resettable for RWD_SPEC { 71 | #[inline(always)] 72 | fn reset_value() -> Self::Ux { 73 | 0 74 | } 75 | } 76 | -------------------------------------------------------------------------------- /src/pac/fdcan/rxbc.rs: -------------------------------------------------------------------------------- 1 | ///Register `RXBC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `RXBC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `RBSA` reader - Rx Buffer Start Address 38 | pub struct RBSA_R(crate::FieldReader); 39 | impl RBSA_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | RBSA_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for RBSA_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `RBSA` writer - Rx Buffer Start Address 52 | pub struct RBSA_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> RBSA_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !(0x3fff << 2)) | ((value as u32 & 0x3fff) << 2); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 2:15 - Rx Buffer Start Address 65 | #[inline(always)] 66 | pub fn rbsa(&self) -> RBSA_R { 67 | RBSA_R::new(((self.bits >> 2) & 0x3fff) as u16) 68 | } 69 | } 70 | impl W { 71 | ///Bits 2:15 - Rx Buffer Start Address 72 | #[inline(always)] 73 | pub fn rbsa(&mut self) -> RBSA_W { 74 | RBSA_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Rx Buffer Configuration Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [rxbc](index.html) module 88 | pub struct RXBC_SPEC; 89 | impl crate::RegisterSpec for RXBC_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [rxbc::R](R) reader structure 93 | impl crate::Readable for RXBC_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [rxbc::W](W) writer structure 97 | impl crate::Writable for RXBC_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets RXBC to value 0 101 | impl crate::Resettable for RXBC_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/rxesc.rs: -------------------------------------------------------------------------------- 1 | ///Register `RXESC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `RXESC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `F0DS` reader - Rx FIFO 1 Data Field Size: 38 | pub struct F0DS_R(crate::FieldReader); 39 | impl F0DS_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | F0DS_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for F0DS_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `F0DS` writer - Rx FIFO 1 Data Field Size: 52 | pub struct F0DS_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> F0DS_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); 60 | self.w 61 | } 62 | } 63 | ///Field `F1DS` reader - Rx FIFO 0 Data Field Size: 64 | pub struct F1DS_R(crate::FieldReader); 65 | impl F1DS_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | F1DS_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for F1DS_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `F1DS` writer - Rx FIFO 0 Data Field Size: 78 | pub struct F1DS_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> F1DS_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); 86 | self.w 87 | } 88 | } 89 | ///Field `RBDS` reader - Rx Buffer Data Field Size: 90 | pub struct RBDS_R(crate::FieldReader); 91 | impl RBDS_R { 92 | pub(crate) fn new(bits: u8) -> Self { 93 | RBDS_R(crate::FieldReader::new(bits)) 94 | } 95 | } 96 | impl core::ops::Deref for RBDS_R { 97 | type Target = crate::FieldReader; 98 | #[inline(always)] 99 | fn deref(&self) -> &Self::Target { 100 | &self.0 101 | } 102 | } 103 | ///Field `RBDS` writer - Rx Buffer Data Field Size: 104 | pub struct RBDS_W<'a> { 105 | w: &'a mut W, 106 | } 107 | impl<'a> RBDS_W<'a> { 108 | ///Writes raw bits to the field 109 | #[inline(always)] 110 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 111 | self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); 112 | self.w 113 | } 114 | } 115 | impl R { 116 | ///Bits 0:2 - Rx FIFO 1 Data Field Size: 117 | #[inline(always)] 118 | pub fn f0ds(&self) -> F0DS_R { 119 | F0DS_R::new((self.bits & 0x07) as u8) 120 | } 121 | ///Bits 4:6 - Rx FIFO 0 Data Field Size: 122 | #[inline(always)] 123 | pub fn f1ds(&self) -> F1DS_R { 124 | F1DS_R::new(((self.bits >> 4) & 0x07) as u8) 125 | } 126 | ///Bits 8:10 - Rx Buffer Data Field Size: 127 | #[inline(always)] 128 | pub fn rbds(&self) -> RBDS_R { 129 | RBDS_R::new(((self.bits >> 8) & 0x07) as u8) 130 | } 131 | } 132 | impl W { 133 | ///Bits 0:2 - Rx FIFO 1 Data Field Size: 134 | #[inline(always)] 135 | pub fn f0ds(&mut self) -> F0DS_W { 136 | F0DS_W { w: self } 137 | } 138 | ///Bits 4:6 - Rx FIFO 0 Data Field Size: 139 | #[inline(always)] 140 | pub fn f1ds(&mut self) -> F1DS_W { 141 | F1DS_W { w: self } 142 | } 143 | ///Bits 8:10 - Rx Buffer Data Field Size: 144 | #[inline(always)] 145 | pub fn rbds(&mut self) -> RBDS_W { 146 | RBDS_W { w: self } 147 | } 148 | ///Writes raw bits to the register. 149 | #[inline(always)] 150 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 151 | self.0.bits(bits); 152 | self 153 | } 154 | } 155 | ///FDCAN Rx Buffer Element Size Configuration Register 156 | /// 157 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 158 | /// 159 | ///For information about available fields see [rxesc](index.html) module 160 | pub struct RXESC_SPEC; 161 | impl crate::RegisterSpec for RXESC_SPEC { 162 | type Ux = u32; 163 | } 164 | ///`read()` method returns [rxesc::R](R) reader structure 165 | impl crate::Readable for RXESC_SPEC { 166 | type Reader = R; 167 | } 168 | ///`write(|w| ..)` method takes [rxesc::W](W) writer structure 169 | impl crate::Writable for RXESC_SPEC { 170 | type Writer = W; 171 | } 172 | ///`reset()` method sets RXESC to value 0 173 | impl crate::Resettable for RXESC_SPEC { 174 | #[inline(always)] 175 | fn reset_value() -> Self::Ux { 176 | 0 177 | } 178 | } 179 | -------------------------------------------------------------------------------- /src/pac/fdcan/rxf0a.rs: -------------------------------------------------------------------------------- 1 | ///Register `RXF0A` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `RXF0A` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `F0AI` reader - Rx FIFO 0 Acknowledge Index 38 | pub struct F0AI_R(crate::FieldReader); 39 | impl F0AI_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | F0AI_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for F0AI_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `F0AI` writer - Rx FIFO 0 Acknowledge Index 52 | pub struct F0AI_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> F0AI_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:5 - Rx FIFO 0 Acknowledge Index 65 | #[inline(always)] 66 | pub fn f0ai(&self) -> F0AI_R { 67 | F0AI_R::new((self.bits & 0x3f) as u8) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:5 - Rx FIFO 0 Acknowledge Index 72 | #[inline(always)] 73 | pub fn f0ai(&mut self) -> F0AI_W { 74 | F0AI_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///CAN Rx FIFO 0 Acknowledge Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [rxf0a](index.html) module 88 | pub struct RXF0A_SPEC; 89 | impl crate::RegisterSpec for RXF0A_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [rxf0a::R](R) reader structure 93 | impl crate::Readable for RXF0A_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [rxf0a::W](W) writer structure 97 | impl crate::Writable for RXF0A_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets RXF0A to value 0 101 | impl crate::Resettable for RXF0A_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/rxf1a.rs: -------------------------------------------------------------------------------- 1 | ///Register `RXF1A` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `RXF1A` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `F1AI` reader - Rx FIFO 1 Acknowledge Index 38 | pub struct F1AI_R(crate::FieldReader); 39 | impl F1AI_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | F1AI_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for F1AI_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `F1AI` writer - Rx FIFO 1 Acknowledge Index 52 | pub struct F1AI_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> F1AI_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:5 - Rx FIFO 1 Acknowledge Index 65 | #[inline(always)] 66 | pub fn f1ai(&self) -> F1AI_R { 67 | F1AI_R::new((self.bits & 0x3f) as u8) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:5 - Rx FIFO 1 Acknowledge Index 72 | #[inline(always)] 73 | pub fn f1ai(&mut self) -> F1AI_W { 74 | F1AI_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Rx FIFO 1 Acknowledge Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [rxf1a](index.html) module 88 | pub struct RXF1A_SPEC; 89 | impl crate::RegisterSpec for RXF1A_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [rxf1a::R](R) reader structure 93 | impl crate::Readable for RXF1A_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [rxf1a::W](W) writer structure 97 | impl crate::Writable for RXF1A_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets RXF1A to value 0 101 | impl crate::Resettable for RXF1A_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/sidfc.rs: -------------------------------------------------------------------------------- 1 | ///Register `SIDFC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `SIDFC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `FLSSA` reader - Filter List Standard Start Address 38 | pub struct FLSSA_R(crate::FieldReader); 39 | impl FLSSA_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | FLSSA_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for FLSSA_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `FLSSA` writer - Filter List Standard Start Address 52 | pub struct FLSSA_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> FLSSA_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !(0x3fff << 2)) | ((value as u32 & 0x3fff) << 2); 60 | self.w 61 | } 62 | } 63 | ///Field `LSS` reader - List Size Standard 64 | pub struct LSS_R(crate::FieldReader); 65 | impl LSS_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | LSS_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for LSS_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `LSS` writer - List Size Standard 78 | pub struct LSS_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> LSS_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); 86 | self.w 87 | } 88 | } 89 | impl R { 90 | ///Bits 2:15 - Filter List Standard Start Address 91 | #[inline(always)] 92 | pub fn flssa(&self) -> FLSSA_R { 93 | FLSSA_R::new(((self.bits >> 2) & 0x3fff) as u16) 94 | } 95 | ///Bits 16:23 - List Size Standard 96 | #[inline(always)] 97 | pub fn lss(&self) -> LSS_R { 98 | LSS_R::new(((self.bits >> 16) & 0xff) as u8) 99 | } 100 | } 101 | impl W { 102 | ///Bits 2:15 - Filter List Standard Start Address 103 | #[inline(always)] 104 | pub fn flssa(&mut self) -> FLSSA_W { 105 | FLSSA_W { w: self } 106 | } 107 | ///Bits 16:23 - List Size Standard 108 | #[inline(always)] 109 | pub fn lss(&mut self) -> LSS_W { 110 | LSS_W { w: self } 111 | } 112 | ///Writes raw bits to the register. 113 | #[inline(always)] 114 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 115 | self.0.bits(bits); 116 | self 117 | } 118 | } 119 | ///FDCAN Standard ID Filter Configuration Register 120 | /// 121 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 122 | /// 123 | ///For information about available fields see [sidfc](index.html) module 124 | pub struct SIDFC_SPEC; 125 | impl crate::RegisterSpec for SIDFC_SPEC { 126 | type Ux = u32; 127 | } 128 | ///`read()` method returns [sidfc::R](R) reader structure 129 | impl crate::Readable for SIDFC_SPEC { 130 | type Reader = R; 131 | } 132 | ///`write(|w| ..)` method takes [sidfc::W](W) writer structure 133 | impl crate::Writable for SIDFC_SPEC { 134 | type Writer = W; 135 | } 136 | ///`reset()` method sets SIDFC to value 0 137 | impl crate::Resettable for SIDFC_SPEC { 138 | #[inline(always)] 139 | fn reset_value() -> Self::Ux { 140 | 0 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/pac/fdcan/tdcr.rs: -------------------------------------------------------------------------------- 1 | ///Register `TDCR` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TDCR` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TDCF` reader - Transmitter Delay Compensation Filter Window Length 38 | pub struct TDCF_R(crate::FieldReader); 39 | impl TDCF_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | TDCF_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TDCF_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TDCF` writer - Transmitter Delay Compensation Filter Window Length 52 | pub struct TDCF_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TDCF_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); 60 | self.w 61 | } 62 | } 63 | ///Field `TDCO` reader - Transmitter Delay Compensation Offset 64 | pub struct TDCO_R(crate::FieldReader); 65 | impl TDCO_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | TDCO_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for TDCO_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `TDCO` writer - Transmitter Delay Compensation Offset 78 | pub struct TDCO_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> TDCO_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x7f << 8)) | ((value as u32 & 0x7f) << 8); 86 | self.w 87 | } 88 | } 89 | impl R { 90 | ///Bits 0:6 - Transmitter Delay Compensation Filter Window Length 91 | #[inline(always)] 92 | pub fn tdcf(&self) -> TDCF_R { 93 | TDCF_R::new((self.bits & 0x7f) as u8) 94 | } 95 | ///Bits 8:14 - Transmitter Delay Compensation Offset 96 | #[inline(always)] 97 | pub fn tdco(&self) -> TDCO_R { 98 | TDCO_R::new(((self.bits >> 8) & 0x7f) as u8) 99 | } 100 | } 101 | impl W { 102 | ///Bits 0:6 - Transmitter Delay Compensation Filter Window Length 103 | #[inline(always)] 104 | pub fn tdcf(&mut self) -> TDCF_W { 105 | TDCF_W { w: self } 106 | } 107 | ///Bits 8:14 - Transmitter Delay Compensation Offset 108 | #[inline(always)] 109 | pub fn tdco(&mut self) -> TDCO_W { 110 | TDCO_W { w: self } 111 | } 112 | ///Writes raw bits to the register. 113 | #[inline(always)] 114 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 115 | self.0.bits(bits); 116 | self 117 | } 118 | } 119 | ///FDCAN Transmitter Delay Compensation Register 120 | /// 121 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 122 | /// 123 | ///For information about available fields see [tdcr](index.html) module 124 | pub struct TDCR_SPEC; 125 | impl crate::RegisterSpec for TDCR_SPEC { 126 | type Ux = u32; 127 | } 128 | ///`read()` method returns [tdcr::R](R) reader structure 129 | impl crate::Readable for TDCR_SPEC { 130 | type Reader = R; 131 | } 132 | ///`write(|w| ..)` method takes [tdcr::W](W) writer structure 133 | impl crate::Writable for TDCR_SPEC { 134 | type Writer = W; 135 | } 136 | ///`reset()` method sets TDCR to value 0 137 | impl crate::Resettable for TDCR_SPEC { 138 | #[inline(always)] 139 | fn reset_value() -> Self::Ux { 140 | 0 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/pac/fdcan/test.rs: -------------------------------------------------------------------------------- 1 | ///Register `TEST` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TEST` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `LBCK` reader - Loop Back mode 38 | pub struct LBCK_R(crate::FieldReader); 39 | impl LBCK_R { 40 | pub(crate) fn new(bits: bool) -> Self { 41 | LBCK_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for LBCK_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `LBCK` writer - Loop Back mode 52 | pub struct LBCK_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> LBCK_W<'a> { 56 | ///Sets the field bit 57 | #[inline(always)] 58 | pub fn set_bit(self) -> &'a mut W { 59 | self.bit(true) 60 | } 61 | ///Clears the field bit 62 | #[inline(always)] 63 | pub fn clear_bit(self) -> &'a mut W { 64 | self.bit(false) 65 | } 66 | ///Writes raw bits to the field 67 | #[inline(always)] 68 | pub fn bit(self, value: bool) -> &'a mut W { 69 | self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); 70 | self.w 71 | } 72 | } 73 | ///Field `TX` reader - Loop Back mode 74 | pub struct TX_R(crate::FieldReader); 75 | impl TX_R { 76 | pub(crate) fn new(bits: u8) -> Self { 77 | TX_R(crate::FieldReader::new(bits)) 78 | } 79 | } 80 | impl core::ops::Deref for TX_R { 81 | type Target = crate::FieldReader; 82 | #[inline(always)] 83 | fn deref(&self) -> &Self::Target { 84 | &self.0 85 | } 86 | } 87 | ///Field `TX` writer - Loop Back mode 88 | pub struct TX_W<'a> { 89 | w: &'a mut W, 90 | } 91 | impl<'a> TX_W<'a> { 92 | ///Writes raw bits to the field 93 | #[inline(always)] 94 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 95 | self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); 96 | self.w 97 | } 98 | } 99 | ///Field `RX` reader - Control of Transmit Pin 100 | pub struct RX_R(crate::FieldReader); 101 | impl RX_R { 102 | pub(crate) fn new(bits: bool) -> Self { 103 | RX_R(crate::FieldReader::new(bits)) 104 | } 105 | } 106 | impl core::ops::Deref for RX_R { 107 | type Target = crate::FieldReader; 108 | #[inline(always)] 109 | fn deref(&self) -> &Self::Target { 110 | &self.0 111 | } 112 | } 113 | ///Field `RX` writer - Control of Transmit Pin 114 | pub struct RX_W<'a> { 115 | w: &'a mut W, 116 | } 117 | impl<'a> RX_W<'a> { 118 | ///Sets the field bit 119 | #[inline(always)] 120 | pub fn set_bit(self) -> &'a mut W { 121 | self.bit(true) 122 | } 123 | ///Clears the field bit 124 | #[inline(always)] 125 | pub fn clear_bit(self) -> &'a mut W { 126 | self.bit(false) 127 | } 128 | ///Writes raw bits to the field 129 | #[inline(always)] 130 | pub fn bit(self, value: bool) -> &'a mut W { 131 | self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); 132 | self.w 133 | } 134 | } 135 | impl R { 136 | ///Bit 4 - Loop Back mode 137 | #[inline(always)] 138 | pub fn lbck(&self) -> LBCK_R { 139 | LBCK_R::new(((self.bits >> 4) & 0x01) != 0) 140 | } 141 | ///Bits 5:6 - Loop Back mode 142 | #[inline(always)] 143 | pub fn tx(&self) -> TX_R { 144 | TX_R::new(((self.bits >> 5) & 0x03) as u8) 145 | } 146 | ///Bit 7 - Control of Transmit Pin 147 | #[inline(always)] 148 | pub fn rx(&self) -> RX_R { 149 | RX_R::new(((self.bits >> 7) & 0x01) != 0) 150 | } 151 | } 152 | impl W { 153 | ///Bit 4 - Loop Back mode 154 | #[inline(always)] 155 | pub fn lbck(&mut self) -> LBCK_W { 156 | LBCK_W { w: self } 157 | } 158 | ///Bits 5:6 - Loop Back mode 159 | #[inline(always)] 160 | pub fn tx(&mut self) -> TX_W { 161 | TX_W { w: self } 162 | } 163 | ///Bit 7 - Control of Transmit Pin 164 | #[inline(always)] 165 | pub fn rx(&mut self) -> RX_W { 166 | RX_W { w: self } 167 | } 168 | ///Writes raw bits to the register. 169 | #[inline(always)] 170 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 171 | self.0.bits(bits); 172 | self 173 | } 174 | } 175 | ///FDCAN Test Register 176 | /// 177 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 178 | /// 179 | ///For information about available fields see [test](index.html) module 180 | pub struct TEST_SPEC; 181 | impl crate::RegisterSpec for TEST_SPEC { 182 | type Ux = u32; 183 | } 184 | ///`read()` method returns [test::R](R) reader structure 185 | impl crate::Readable for TEST_SPEC { 186 | type Reader = R; 187 | } 188 | ///`write(|w| ..)` method takes [test::W](W) writer structure 189 | impl crate::Writable for TEST_SPEC { 190 | type Writer = W; 191 | } 192 | ///`reset()` method sets TEST to value 0 193 | impl crate::Resettable for TEST_SPEC { 194 | #[inline(always)] 195 | fn reset_value() -> Self::Ux { 196 | 0 197 | } 198 | } 199 | -------------------------------------------------------------------------------- /src/pac/fdcan/tocc.rs: -------------------------------------------------------------------------------- 1 | ///Register `TOCC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TOCC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `ETOC` reader - Enable Timeout Counter 38 | pub struct ETOC_R(crate::FieldReader); 39 | impl ETOC_R { 40 | pub(crate) fn new(bits: bool) -> Self { 41 | ETOC_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for ETOC_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `ETOC` writer - Enable Timeout Counter 52 | pub struct ETOC_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> ETOC_W<'a> { 56 | ///Sets the field bit 57 | #[inline(always)] 58 | pub fn set_bit(self) -> &'a mut W { 59 | self.bit(true) 60 | } 61 | ///Clears the field bit 62 | #[inline(always)] 63 | pub fn clear_bit(self) -> &'a mut W { 64 | self.bit(false) 65 | } 66 | ///Writes raw bits to the field 67 | #[inline(always)] 68 | pub fn bit(self, value: bool) -> &'a mut W { 69 | self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); 70 | self.w 71 | } 72 | } 73 | ///Field `TOS` reader - Timeout Select 74 | pub struct TOS_R(crate::FieldReader); 75 | impl TOS_R { 76 | pub(crate) fn new(bits: u8) -> Self { 77 | TOS_R(crate::FieldReader::new(bits)) 78 | } 79 | } 80 | impl core::ops::Deref for TOS_R { 81 | type Target = crate::FieldReader; 82 | #[inline(always)] 83 | fn deref(&self) -> &Self::Target { 84 | &self.0 85 | } 86 | } 87 | ///Field `TOS` writer - Timeout Select 88 | pub struct TOS_W<'a> { 89 | w: &'a mut W, 90 | } 91 | impl<'a> TOS_W<'a> { 92 | ///Writes raw bits to the field 93 | #[inline(always)] 94 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 95 | self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u32 & 0x03) << 1); 96 | self.w 97 | } 98 | } 99 | ///Field `TOP` reader - Timeout Period 100 | pub struct TOP_R(crate::FieldReader); 101 | impl TOP_R { 102 | pub(crate) fn new(bits: u16) -> Self { 103 | TOP_R(crate::FieldReader::new(bits)) 104 | } 105 | } 106 | impl core::ops::Deref for TOP_R { 107 | type Target = crate::FieldReader; 108 | #[inline(always)] 109 | fn deref(&self) -> &Self::Target { 110 | &self.0 111 | } 112 | } 113 | ///Field `TOP` writer - Timeout Period 114 | pub struct TOP_W<'a> { 115 | w: &'a mut W, 116 | } 117 | impl<'a> TOP_W<'a> { 118 | ///Writes raw bits to the field 119 | #[inline(always)] 120 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 121 | self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); 122 | self.w 123 | } 124 | } 125 | impl R { 126 | ///Bit 0 - Enable Timeout Counter 127 | #[inline(always)] 128 | pub fn etoc(&self) -> ETOC_R { 129 | ETOC_R::new((self.bits & 0x01) != 0) 130 | } 131 | ///Bits 1:2 - Timeout Select 132 | #[inline(always)] 133 | pub fn tos(&self) -> TOS_R { 134 | TOS_R::new(((self.bits >> 1) & 0x03) as u8) 135 | } 136 | ///Bits 16:31 - Timeout Period 137 | #[inline(always)] 138 | pub fn top(&self) -> TOP_R { 139 | TOP_R::new(((self.bits >> 16) & 0xffff) as u16) 140 | } 141 | } 142 | impl W { 143 | ///Bit 0 - Enable Timeout Counter 144 | #[inline(always)] 145 | pub fn etoc(&mut self) -> ETOC_W { 146 | ETOC_W { w: self } 147 | } 148 | ///Bits 1:2 - Timeout Select 149 | #[inline(always)] 150 | pub fn tos(&mut self) -> TOS_W { 151 | TOS_W { w: self } 152 | } 153 | ///Bits 16:31 - Timeout Period 154 | #[inline(always)] 155 | pub fn top(&mut self) -> TOP_W { 156 | TOP_W { w: self } 157 | } 158 | ///Writes raw bits to the register. 159 | #[inline(always)] 160 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 161 | self.0.bits(bits); 162 | self 163 | } 164 | } 165 | ///FDCAN Timeout Counter Configuration Register 166 | /// 167 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 168 | /// 169 | ///For information about available fields see [tocc](index.html) module 170 | pub struct TOCC_SPEC; 171 | impl crate::RegisterSpec for TOCC_SPEC { 172 | type Ux = u32; 173 | } 174 | ///`read()` method returns [tocc::R](R) reader structure 175 | impl crate::Readable for TOCC_SPEC { 176 | type Reader = R; 177 | } 178 | ///`write(|w| ..)` method takes [tocc::W](W) writer structure 179 | impl crate::Writable for TOCC_SPEC { 180 | type Writer = W; 181 | } 182 | ///`reset()` method sets TOCC to value 0 183 | impl crate::Resettable for TOCC_SPEC { 184 | #[inline(always)] 185 | fn reset_value() -> Self::Ux { 186 | 0 187 | } 188 | } 189 | -------------------------------------------------------------------------------- /src/pac/fdcan/tocv.rs: -------------------------------------------------------------------------------- 1 | ///Register `TOCV` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TOCV` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TOC` reader - Timeout Counter 38 | pub struct TOC_R(crate::FieldReader); 39 | impl TOC_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | TOC_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TOC_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TOC` writer - Timeout Counter 52 | pub struct TOC_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TOC_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:15 - Timeout Counter 65 | #[inline(always)] 66 | pub fn toc(&self) -> TOC_R { 67 | TOC_R::new((self.bits & 0xffff) as u16) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:15 - Timeout Counter 72 | #[inline(always)] 73 | pub fn toc(&mut self) -> TOC_W { 74 | TOC_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Timeout Counter Value Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [tocv](index.html) module 88 | pub struct TOCV_SPEC; 89 | impl crate::RegisterSpec for TOCV_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [tocv::R](R) reader structure 93 | impl crate::Readable for TOCV_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [tocv::W](W) writer structure 97 | impl crate::Writable for TOCV_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TOCV to value 0 101 | impl crate::Resettable for TOCV_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/tscc.rs: -------------------------------------------------------------------------------- 1 | ///Register `TSCC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TSCC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TCP` reader - Timestamp Counter Prescaler 38 | pub struct TCP_R(crate::FieldReader); 39 | impl TCP_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | TCP_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TCP_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TCP` writer - Timestamp Counter Prescaler 52 | pub struct TCP_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TCP_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); 60 | self.w 61 | } 62 | } 63 | ///Field `TSS` reader - Timestamp Select 64 | pub struct TSS_R(crate::FieldReader); 65 | impl TSS_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | TSS_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for TSS_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `TSS` writer - Timestamp Select 78 | pub struct TSS_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> TSS_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); 86 | self.w 87 | } 88 | } 89 | impl R { 90 | ///Bits 16:19 - Timestamp Counter Prescaler 91 | #[inline(always)] 92 | pub fn tcp(&self) -> TCP_R { 93 | TCP_R::new(((self.bits >> 16) & 0x0f) as u8) 94 | } 95 | ///Bits 0:1 - Timestamp Select 96 | #[inline(always)] 97 | pub fn tss(&self) -> TSS_R { 98 | TSS_R::new((self.bits & 0x03) as u8) 99 | } 100 | } 101 | impl W { 102 | ///Bits 16:19 - Timestamp Counter Prescaler 103 | #[inline(always)] 104 | pub fn tcp(&mut self) -> TCP_W { 105 | TCP_W { w: self } 106 | } 107 | ///Bits 0:1 - Timestamp Select 108 | #[inline(always)] 109 | pub fn tss(&mut self) -> TSS_W { 110 | TSS_W { w: self } 111 | } 112 | ///Writes raw bits to the register. 113 | #[inline(always)] 114 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 115 | self.0.bits(bits); 116 | self 117 | } 118 | } 119 | ///FDCAN Timestamp Counter Configuration Register 120 | /// 121 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 122 | /// 123 | ///For information about available fields see [tscc](index.html) module 124 | pub struct TSCC_SPEC; 125 | impl crate::RegisterSpec for TSCC_SPEC { 126 | type Ux = u32; 127 | } 128 | ///`read()` method returns [tscc::R](R) reader structure 129 | impl crate::Readable for TSCC_SPEC { 130 | type Reader = R; 131 | } 132 | ///`write(|w| ..)` method takes [tscc::W](W) writer structure 133 | impl crate::Writable for TSCC_SPEC { 134 | type Writer = W; 135 | } 136 | ///`reset()` method sets TSCC to value 0 137 | impl crate::Resettable for TSCC_SPEC { 138 | #[inline(always)] 139 | fn reset_value() -> Self::Ux { 140 | 0 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/pac/fdcan/tscv.rs: -------------------------------------------------------------------------------- 1 | ///Register `TSCV` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TSCV` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TSC` reader - Timestamp Counter 38 | pub struct TSC_R(crate::FieldReader); 39 | impl TSC_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | TSC_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TSC_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TSC` writer - Timestamp Counter 52 | pub struct TSC_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TSC_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:15 - Timestamp Counter 65 | #[inline(always)] 66 | pub fn tsc(&self) -> TSC_R { 67 | TSC_R::new((self.bits & 0xffff) as u16) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:15 - Timestamp Counter 72 | #[inline(always)] 73 | pub fn tsc(&mut self) -> TSC_W { 74 | TSC_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Timestamp Counter Value Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [tscv](index.html) module 88 | pub struct TSCV_SPEC; 89 | impl crate::RegisterSpec for TSCV_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [tscv::R](R) reader structure 93 | impl crate::Readable for TSCV_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [tscv::W](W) writer structure 97 | impl crate::Writable for TSCV_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TSCV to value 0 101 | impl crate::Resettable for TSCV_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttcpt.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTCPT` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `CCV` reader - Cycle Count Value 17 | pub struct CCV_R(crate::FieldReader); 18 | impl CCV_R { 19 | pub(crate) fn new(bits: u8) -> Self { 20 | CCV_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for CCV_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | ///Field `SWV` reader - Stop Watch Value 31 | pub struct SWV_R(crate::FieldReader); 32 | impl SWV_R { 33 | pub(crate) fn new(bits: u16) -> Self { 34 | SWV_R(crate::FieldReader::new(bits)) 35 | } 36 | } 37 | impl core::ops::Deref for SWV_R { 38 | type Target = crate::FieldReader; 39 | #[inline(always)] 40 | fn deref(&self) -> &Self::Target { 41 | &self.0 42 | } 43 | } 44 | impl R { 45 | ///Bits 0:5 - Cycle Count Value 46 | #[inline(always)] 47 | pub fn ccv(&self) -> CCV_R { 48 | CCV_R::new((self.bits & 0x3f) as u8) 49 | } 50 | ///Bits 16:31 - Stop Watch Value 51 | #[inline(always)] 52 | pub fn swv(&self) -> SWV_R { 53 | SWV_R::new(((self.bits >> 16) & 0xffff) as u16) 54 | } 55 | } 56 | ///FDCAN TT Capture Time Register 57 | /// 58 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 59 | /// 60 | ///For information about available fields see [ttcpt](index.html) module 61 | pub struct TTCPT_SPEC; 62 | impl crate::RegisterSpec for TTCPT_SPEC { 63 | type Ux = u32; 64 | } 65 | ///`read()` method returns [ttcpt::R](R) reader structure 66 | impl crate::Readable for TTCPT_SPEC { 67 | type Reader = R; 68 | } 69 | ///`reset()` method sets TTCPT to value 0 70 | impl crate::Resettable for TTCPT_SPEC { 71 | #[inline(always)] 72 | fn reset_value() -> Self::Ux { 73 | 0 74 | } 75 | } 76 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttcsm.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTCSM` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `CSM` reader - Cycle Sync Mark 17 | pub struct CSM_R(crate::FieldReader); 18 | impl CSM_R { 19 | pub(crate) fn new(bits: u16) -> Self { 20 | CSM_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for CSM_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | impl R { 31 | ///Bits 0:15 - Cycle Sync Mark 32 | #[inline(always)] 33 | pub fn csm(&self) -> CSM_R { 34 | CSM_R::new((self.bits & 0xffff) as u16) 35 | } 36 | } 37 | ///FDCAN TT Cycle Sync Mark Register 38 | /// 39 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 40 | /// 41 | ///For information about available fields see [ttcsm](index.html) module 42 | pub struct TTCSM_SPEC; 43 | impl crate::RegisterSpec for TTCSM_SPEC { 44 | type Ux = u32; 45 | } 46 | ///`read()` method returns [ttcsm::R](R) reader structure 47 | impl crate::Readable for TTCSM_SPEC { 48 | type Reader = R; 49 | } 50 | ///`reset()` method sets TTCSM to value 0 51 | impl crate::Resettable for TTCSM_SPEC { 52 | #[inline(always)] 53 | fn reset_value() -> Self::Ux { 54 | 0 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttctc.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTCTC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `CT` reader - Cycle Time 17 | pub struct CT_R(crate::FieldReader); 18 | impl CT_R { 19 | pub(crate) fn new(bits: u16) -> Self { 20 | CT_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for CT_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | ///Field `CC` reader - Cycle Count 31 | pub struct CC_R(crate::FieldReader); 32 | impl CC_R { 33 | pub(crate) fn new(bits: u8) -> Self { 34 | CC_R(crate::FieldReader::new(bits)) 35 | } 36 | } 37 | impl core::ops::Deref for CC_R { 38 | type Target = crate::FieldReader; 39 | #[inline(always)] 40 | fn deref(&self) -> &Self::Target { 41 | &self.0 42 | } 43 | } 44 | impl R { 45 | ///Bits 0:15 - Cycle Time 46 | #[inline(always)] 47 | pub fn ct(&self) -> CT_R { 48 | CT_R::new((self.bits & 0xffff) as u16) 49 | } 50 | ///Bits 16:21 - Cycle Count 51 | #[inline(always)] 52 | pub fn cc(&self) -> CC_R { 53 | CC_R::new(((self.bits >> 16) & 0x3f) as u8) 54 | } 55 | } 56 | ///FDCAN TT Cycle Time and Count Register 57 | /// 58 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 59 | /// 60 | ///For information about available fields see [ttctc](index.html) module 61 | pub struct TTCTC_SPEC; 62 | impl crate::RegisterSpec for TTCTC_SPEC { 63 | type Ux = u32; 64 | } 65 | ///`read()` method returns [ttctc::R](R) reader structure 66 | impl crate::Readable for TTCTC_SPEC { 67 | type Reader = R; 68 | } 69 | ///`reset()` method sets TTCTC to value 0 70 | impl crate::Resettable for TTCTC_SPEC { 71 | #[inline(always)] 72 | fn reset_value() -> Self::Ux { 73 | 0 74 | } 75 | } 76 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttgtp.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTGTP` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TTGTP` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `NCL` reader - Time Preset 38 | pub struct NCL_R(crate::FieldReader); 39 | impl NCL_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | NCL_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for NCL_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `NCL` writer - Time Preset 52 | pub struct NCL_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> NCL_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); 60 | self.w 61 | } 62 | } 63 | ///Field `CTP` reader - Cycle Time Target Phase 64 | pub struct CTP_R(crate::FieldReader); 65 | impl CTP_R { 66 | pub(crate) fn new(bits: u16) -> Self { 67 | CTP_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for CTP_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `CTP` writer - Cycle Time Target Phase 78 | pub struct CTP_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> CTP_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); 86 | self.w 87 | } 88 | } 89 | impl R { 90 | ///Bits 0:15 - Time Preset 91 | #[inline(always)] 92 | pub fn ncl(&self) -> NCL_R { 93 | NCL_R::new((self.bits & 0xffff) as u16) 94 | } 95 | ///Bits 16:31 - Cycle Time Target Phase 96 | #[inline(always)] 97 | pub fn ctp(&self) -> CTP_R { 98 | CTP_R::new(((self.bits >> 16) & 0xffff) as u16) 99 | } 100 | } 101 | impl W { 102 | ///Bits 0:15 - Time Preset 103 | #[inline(always)] 104 | pub fn ncl(&mut self) -> NCL_W { 105 | NCL_W { w: self } 106 | } 107 | ///Bits 16:31 - Cycle Time Target Phase 108 | #[inline(always)] 109 | pub fn ctp(&mut self) -> CTP_W { 110 | CTP_W { w: self } 111 | } 112 | ///Writes raw bits to the register. 113 | #[inline(always)] 114 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 115 | self.0.bits(bits); 116 | self 117 | } 118 | } 119 | ///FDCAN TT Global Time Preset Register 120 | /// 121 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 122 | /// 123 | ///For information about available fields see [ttgtp](index.html) module 124 | pub struct TTGTP_SPEC; 125 | impl crate::RegisterSpec for TTGTP_SPEC { 126 | type Ux = u32; 127 | } 128 | ///`read()` method returns [ttgtp::R](R) reader structure 129 | impl crate::Readable for TTGTP_SPEC { 130 | type Reader = R; 131 | } 132 | ///`write(|w| ..)` method takes [ttgtp::W](W) writer structure 133 | impl crate::Writable for TTGTP_SPEC { 134 | type Writer = W; 135 | } 136 | ///`reset()` method sets TTGTP to value 0 137 | impl crate::Resettable for TTGTP_SPEC { 138 | #[inline(always)] 139 | fn reset_value() -> Self::Ux { 140 | 0 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttlgt.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTLGT` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `LT` reader - Local Time 17 | pub struct LT_R(crate::FieldReader); 18 | impl LT_R { 19 | pub(crate) fn new(bits: u16) -> Self { 20 | LT_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for LT_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | ///Field `GT` reader - Global Time 31 | pub struct GT_R(crate::FieldReader); 32 | impl GT_R { 33 | pub(crate) fn new(bits: u16) -> Self { 34 | GT_R(crate::FieldReader::new(bits)) 35 | } 36 | } 37 | impl core::ops::Deref for GT_R { 38 | type Target = crate::FieldReader; 39 | #[inline(always)] 40 | fn deref(&self) -> &Self::Target { 41 | &self.0 42 | } 43 | } 44 | impl R { 45 | ///Bits 0:15 - Local Time 46 | #[inline(always)] 47 | pub fn lt(&self) -> LT_R { 48 | LT_R::new((self.bits & 0xffff) as u16) 49 | } 50 | ///Bits 16:31 - Global Time 51 | #[inline(always)] 52 | pub fn gt(&self) -> GT_R { 53 | GT_R::new(((self.bits >> 16) & 0xffff) as u16) 54 | } 55 | } 56 | ///FDCAN TT Local and Global Time Register 57 | /// 58 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 59 | /// 60 | ///For information about available fields see [ttlgt](index.html) module 61 | pub struct TTLGT_SPEC; 62 | impl crate::RegisterSpec for TTLGT_SPEC { 63 | type Ux = u32; 64 | } 65 | ///`read()` method returns [ttlgt::R](R) reader structure 66 | impl crate::Readable for TTLGT_SPEC { 67 | type Reader = R; 68 | } 69 | ///`reset()` method sets TTLGT to value 0 70 | impl crate::Resettable for TTLGT_SPEC { 71 | #[inline(always)] 72 | fn reset_value() -> Self::Ux { 73 | 0 74 | } 75 | } 76 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttmlm.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTMLM` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TTMLM` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `CCM` reader - Cycle Count Max 38 | pub struct CCM_R(crate::FieldReader); 39 | impl CCM_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | CCM_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for CCM_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `CCM` writer - Cycle Count Max 52 | pub struct CCM_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> CCM_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); 60 | self.w 61 | } 62 | } 63 | ///Field `CSS` reader - Cycle Start Synchronization 64 | pub struct CSS_R(crate::FieldReader); 65 | impl CSS_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | CSS_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for CSS_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `CSS` writer - Cycle Start Synchronization 78 | pub struct CSS_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> CSS_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); 86 | self.w 87 | } 88 | } 89 | ///Field `TXEW` reader - Tx Enable Window 90 | pub struct TXEW_R(crate::FieldReader); 91 | impl TXEW_R { 92 | pub(crate) fn new(bits: u8) -> Self { 93 | TXEW_R(crate::FieldReader::new(bits)) 94 | } 95 | } 96 | impl core::ops::Deref for TXEW_R { 97 | type Target = crate::FieldReader; 98 | #[inline(always)] 99 | fn deref(&self) -> &Self::Target { 100 | &self.0 101 | } 102 | } 103 | ///Field `TXEW` writer - Tx Enable Window 104 | pub struct TXEW_W<'a> { 105 | w: &'a mut W, 106 | } 107 | impl<'a> TXEW_W<'a> { 108 | ///Writes raw bits to the field 109 | #[inline(always)] 110 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 111 | self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); 112 | self.w 113 | } 114 | } 115 | ///Field `ENTT` reader - Expected Number of Tx Triggers 116 | pub struct ENTT_R(crate::FieldReader); 117 | impl ENTT_R { 118 | pub(crate) fn new(bits: u16) -> Self { 119 | ENTT_R(crate::FieldReader::new(bits)) 120 | } 121 | } 122 | impl core::ops::Deref for ENTT_R { 123 | type Target = crate::FieldReader; 124 | #[inline(always)] 125 | fn deref(&self) -> &Self::Target { 126 | &self.0 127 | } 128 | } 129 | ///Field `ENTT` writer - Expected Number of Tx Triggers 130 | pub struct ENTT_W<'a> { 131 | w: &'a mut W, 132 | } 133 | impl<'a> ENTT_W<'a> { 134 | ///Writes raw bits to the field 135 | #[inline(always)] 136 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 137 | self.w.bits = (self.w.bits & !(0x0fff << 16)) | ((value as u32 & 0x0fff) << 16); 138 | self.w 139 | } 140 | } 141 | impl R { 142 | ///Bits 0:5 - Cycle Count Max 143 | #[inline(always)] 144 | pub fn ccm(&self) -> CCM_R { 145 | CCM_R::new((self.bits & 0x3f) as u8) 146 | } 147 | ///Bits 6:7 - Cycle Start Synchronization 148 | #[inline(always)] 149 | pub fn css(&self) -> CSS_R { 150 | CSS_R::new(((self.bits >> 6) & 0x03) as u8) 151 | } 152 | ///Bits 8:11 - Tx Enable Window 153 | #[inline(always)] 154 | pub fn txew(&self) -> TXEW_R { 155 | TXEW_R::new(((self.bits >> 8) & 0x0f) as u8) 156 | } 157 | ///Bits 16:27 - Expected Number of Tx Triggers 158 | #[inline(always)] 159 | pub fn entt(&self) -> ENTT_R { 160 | ENTT_R::new(((self.bits >> 16) & 0x0fff) as u16) 161 | } 162 | } 163 | impl W { 164 | ///Bits 0:5 - Cycle Count Max 165 | #[inline(always)] 166 | pub fn ccm(&mut self) -> CCM_W { 167 | CCM_W { w: self } 168 | } 169 | ///Bits 6:7 - Cycle Start Synchronization 170 | #[inline(always)] 171 | pub fn css(&mut self) -> CSS_W { 172 | CSS_W { w: self } 173 | } 174 | ///Bits 8:11 - Tx Enable Window 175 | #[inline(always)] 176 | pub fn txew(&mut self) -> TXEW_W { 177 | TXEW_W { w: self } 178 | } 179 | ///Bits 16:27 - Expected Number of Tx Triggers 180 | #[inline(always)] 181 | pub fn entt(&mut self) -> ENTT_W { 182 | ENTT_W { w: self } 183 | } 184 | ///Writes raw bits to the register. 185 | #[inline(always)] 186 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 187 | self.0.bits(bits); 188 | self 189 | } 190 | } 191 | ///FDCAN TT Matrix Limits Register 192 | /// 193 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 194 | /// 195 | ///For information about available fields see [ttmlm](index.html) module 196 | pub struct TTMLM_SPEC; 197 | impl crate::RegisterSpec for TTMLM_SPEC { 198 | type Ux = u32; 199 | } 200 | ///`read()` method returns [ttmlm::R](R) reader structure 201 | impl crate::Readable for TTMLM_SPEC { 202 | type Reader = R; 203 | } 204 | ///`write(|w| ..)` method takes [ttmlm::W](W) writer structure 205 | impl crate::Writable for TTMLM_SPEC { 206 | type Writer = W; 207 | } 208 | ///`reset()` method sets TTMLM to value 0 209 | impl crate::Resettable for TTMLM_SPEC { 210 | #[inline(always)] 211 | fn reset_value() -> Self::Ux { 212 | 0 213 | } 214 | } 215 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttrmc.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTRMC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TTRMC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `RID` reader - Reference Identifier. 38 | pub struct RID_R(crate::FieldReader); 39 | impl RID_R { 40 | pub(crate) fn new(bits: u32) -> Self { 41 | RID_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for RID_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `RID` writer - Reference Identifier. 52 | pub struct RID_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> RID_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x1fff_ffff) | (value as u32 & 0x1fff_ffff); 60 | self.w 61 | } 62 | } 63 | ///Field `XTD` reader - Extended Identifier 64 | pub struct XTD_R(crate::FieldReader); 65 | impl XTD_R { 66 | pub(crate) fn new(bits: bool) -> Self { 67 | XTD_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for XTD_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `XTD` writer - Extended Identifier 78 | pub struct XTD_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> XTD_W<'a> { 82 | ///Sets the field bit 83 | #[inline(always)] 84 | pub fn set_bit(self) -> &'a mut W { 85 | self.bit(true) 86 | } 87 | ///Clears the field bit 88 | #[inline(always)] 89 | pub fn clear_bit(self) -> &'a mut W { 90 | self.bit(false) 91 | } 92 | ///Writes raw bits to the field 93 | #[inline(always)] 94 | pub fn bit(self, value: bool) -> &'a mut W { 95 | self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); 96 | self.w 97 | } 98 | } 99 | ///Field `RMPS` reader - Reference Message Payload Select 100 | pub struct RMPS_R(crate::FieldReader); 101 | impl RMPS_R { 102 | pub(crate) fn new(bits: bool) -> Self { 103 | RMPS_R(crate::FieldReader::new(bits)) 104 | } 105 | } 106 | impl core::ops::Deref for RMPS_R { 107 | type Target = crate::FieldReader; 108 | #[inline(always)] 109 | fn deref(&self) -> &Self::Target { 110 | &self.0 111 | } 112 | } 113 | ///Field `RMPS` writer - Reference Message Payload Select 114 | pub struct RMPS_W<'a> { 115 | w: &'a mut W, 116 | } 117 | impl<'a> RMPS_W<'a> { 118 | ///Sets the field bit 119 | #[inline(always)] 120 | pub fn set_bit(self) -> &'a mut W { 121 | self.bit(true) 122 | } 123 | ///Clears the field bit 124 | #[inline(always)] 125 | pub fn clear_bit(self) -> &'a mut W { 126 | self.bit(false) 127 | } 128 | ///Writes raw bits to the field 129 | #[inline(always)] 130 | pub fn bit(self, value: bool) -> &'a mut W { 131 | self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); 132 | self.w 133 | } 134 | } 135 | impl R { 136 | ///Bits 0:28 - Reference Identifier. 137 | #[inline(always)] 138 | pub fn rid(&self) -> RID_R { 139 | RID_R::new((self.bits & 0x1fff_ffff) as u32) 140 | } 141 | ///Bit 30 - Extended Identifier 142 | #[inline(always)] 143 | pub fn xtd(&self) -> XTD_R { 144 | XTD_R::new(((self.bits >> 30) & 0x01) != 0) 145 | } 146 | ///Bit 31 - Reference Message Payload Select 147 | #[inline(always)] 148 | pub fn rmps(&self) -> RMPS_R { 149 | RMPS_R::new(((self.bits >> 31) & 0x01) != 0) 150 | } 151 | } 152 | impl W { 153 | ///Bits 0:28 - Reference Identifier. 154 | #[inline(always)] 155 | pub fn rid(&mut self) -> RID_W { 156 | RID_W { w: self } 157 | } 158 | ///Bit 30 - Extended Identifier 159 | #[inline(always)] 160 | pub fn xtd(&mut self) -> XTD_W { 161 | XTD_W { w: self } 162 | } 163 | ///Bit 31 - Reference Message Payload Select 164 | #[inline(always)] 165 | pub fn rmps(&mut self) -> RMPS_W { 166 | RMPS_W { w: self } 167 | } 168 | ///Writes raw bits to the register. 169 | #[inline(always)] 170 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 171 | self.0.bits(bits); 172 | self 173 | } 174 | } 175 | ///FDCAN TT Reference Message Configuration Register 176 | /// 177 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 178 | /// 179 | ///For information about available fields see [ttrmc](index.html) module 180 | pub struct TTRMC_SPEC; 181 | impl crate::RegisterSpec for TTRMC_SPEC { 182 | type Ux = u32; 183 | } 184 | ///`read()` method returns [ttrmc::R](R) reader structure 185 | impl crate::Readable for TTRMC_SPEC { 186 | type Reader = R; 187 | } 188 | ///`write(|w| ..)` method takes [ttrmc::W](W) writer structure 189 | impl crate::Writable for TTRMC_SPEC { 190 | type Writer = W; 191 | } 192 | ///`reset()` method sets TTRMC to value 0 193 | impl crate::Resettable for TTRMC_SPEC { 194 | #[inline(always)] 195 | fn reset_value() -> Self::Ux { 196 | 0 197 | } 198 | } 199 | -------------------------------------------------------------------------------- /src/pac/fdcan/tttmc.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTTMC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TTTMC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TMSA` reader - Trigger Memory Start Address 38 | pub struct TMSA_R(crate::FieldReader); 39 | impl TMSA_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | TMSA_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TMSA_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TMSA` writer - Trigger Memory Start Address 52 | pub struct TMSA_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TMSA_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !(0x3fff << 2)) | ((value as u32 & 0x3fff) << 2); 60 | self.w 61 | } 62 | } 63 | ///Field `TME` reader - Trigger Memory Elements 64 | pub struct TME_R(crate::FieldReader); 65 | impl TME_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | TME_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for TME_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `TME` writer - Trigger Memory Elements 78 | pub struct TME_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> TME_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); 86 | self.w 87 | } 88 | } 89 | impl R { 90 | ///Bits 2:15 - Trigger Memory Start Address 91 | #[inline(always)] 92 | pub fn tmsa(&self) -> TMSA_R { 93 | TMSA_R::new(((self.bits >> 2) & 0x3fff) as u16) 94 | } 95 | ///Bits 16:22 - Trigger Memory Elements 96 | #[inline(always)] 97 | pub fn tme(&self) -> TME_R { 98 | TME_R::new(((self.bits >> 16) & 0x7f) as u8) 99 | } 100 | } 101 | impl W { 102 | ///Bits 2:15 - Trigger Memory Start Address 103 | #[inline(always)] 104 | pub fn tmsa(&mut self) -> TMSA_W { 105 | TMSA_W { w: self } 106 | } 107 | ///Bits 16:22 - Trigger Memory Elements 108 | #[inline(always)] 109 | pub fn tme(&mut self) -> TME_W { 110 | TME_W { w: self } 111 | } 112 | ///Writes raw bits to the register. 113 | #[inline(always)] 114 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 115 | self.0.bits(bits); 116 | self 117 | } 118 | } 119 | ///FDCAN TT Trigger Memory Configuration Register 120 | /// 121 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 122 | /// 123 | ///For information about available fields see [tttmc](index.html) module 124 | pub struct TTTMC_SPEC; 125 | impl crate::RegisterSpec for TTTMC_SPEC { 126 | type Ux = u32; 127 | } 128 | ///`read()` method returns [tttmc::R](R) reader structure 129 | impl crate::Readable for TTTMC_SPEC { 130 | type Reader = R; 131 | } 132 | ///`write(|w| ..)` method takes [tttmc::W](W) writer structure 133 | impl crate::Writable for TTTMC_SPEC { 134 | type Writer = W; 135 | } 136 | ///`reset()` method sets TTTMC to value 0 137 | impl crate::Resettable for TTTMC_SPEC { 138 | #[inline(always)] 139 | fn reset_value() -> Self::Ux { 140 | 0 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/pac/fdcan/tttmk.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTTMK` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TTTMK` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TM` reader - Time Mark 38 | pub struct TM_R(crate::FieldReader); 39 | impl TM_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | TM_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TM_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TM` writer - Time Mark 52 | pub struct TM_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TM_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); 60 | self.w 61 | } 62 | } 63 | ///Field `TICC` reader - Time Mark Cycle Code 64 | pub struct TICC_R(crate::FieldReader); 65 | impl TICC_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | TICC_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for TICC_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `TICC` writer - Time Mark Cycle Code 78 | pub struct TICC_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> TICC_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16); 86 | self.w 87 | } 88 | } 89 | ///Field `LCKM` reader - TT Time Mark Register Locked 90 | pub struct LCKM_R(crate::FieldReader); 91 | impl LCKM_R { 92 | pub(crate) fn new(bits: bool) -> Self { 93 | LCKM_R(crate::FieldReader::new(bits)) 94 | } 95 | } 96 | impl core::ops::Deref for LCKM_R { 97 | type Target = crate::FieldReader; 98 | #[inline(always)] 99 | fn deref(&self) -> &Self::Target { 100 | &self.0 101 | } 102 | } 103 | ///Field `LCKM` writer - TT Time Mark Register Locked 104 | pub struct LCKM_W<'a> { 105 | w: &'a mut W, 106 | } 107 | impl<'a> LCKM_W<'a> { 108 | ///Sets the field bit 109 | #[inline(always)] 110 | pub fn set_bit(self) -> &'a mut W { 111 | self.bit(true) 112 | } 113 | ///Clears the field bit 114 | #[inline(always)] 115 | pub fn clear_bit(self) -> &'a mut W { 116 | self.bit(false) 117 | } 118 | ///Writes raw bits to the field 119 | #[inline(always)] 120 | pub fn bit(self, value: bool) -> &'a mut W { 121 | self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); 122 | self.w 123 | } 124 | } 125 | impl R { 126 | ///Bits 0:15 - Time Mark 127 | #[inline(always)] 128 | pub fn tm(&self) -> TM_R { 129 | TM_R::new((self.bits & 0xffff) as u16) 130 | } 131 | ///Bits 16:22 - Time Mark Cycle Code 132 | #[inline(always)] 133 | pub fn ticc(&self) -> TICC_R { 134 | TICC_R::new(((self.bits >> 16) & 0x7f) as u8) 135 | } 136 | ///Bit 31 - TT Time Mark Register Locked 137 | #[inline(always)] 138 | pub fn lckm(&self) -> LCKM_R { 139 | LCKM_R::new(((self.bits >> 31) & 0x01) != 0) 140 | } 141 | } 142 | impl W { 143 | ///Bits 0:15 - Time Mark 144 | #[inline(always)] 145 | pub fn tm(&mut self) -> TM_W { 146 | TM_W { w: self } 147 | } 148 | ///Bits 16:22 - Time Mark Cycle Code 149 | #[inline(always)] 150 | pub fn ticc(&mut self) -> TICC_W { 151 | TICC_W { w: self } 152 | } 153 | ///Bit 31 - TT Time Mark Register Locked 154 | #[inline(always)] 155 | pub fn lckm(&mut self) -> LCKM_W { 156 | LCKM_W { w: self } 157 | } 158 | ///Writes raw bits to the register. 159 | #[inline(always)] 160 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 161 | self.0.bits(bits); 162 | self 163 | } 164 | } 165 | ///FDCAN TT Time Mark Register 166 | /// 167 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 168 | /// 169 | ///For information about available fields see [tttmk](index.html) module 170 | pub struct TTTMK_SPEC; 171 | impl crate::RegisterSpec for TTTMK_SPEC { 172 | type Ux = u32; 173 | } 174 | ///`read()` method returns [tttmk::R](R) reader structure 175 | impl crate::Readable for TTTMK_SPEC { 176 | type Reader = R; 177 | } 178 | ///`write(|w| ..)` method takes [tttmk::W](W) writer structure 179 | impl crate::Writable for TTTMK_SPEC { 180 | type Writer = W; 181 | } 182 | ///`reset()` method sets TTTMK to value 0 183 | impl crate::Resettable for TTTMK_SPEC { 184 | #[inline(always)] 185 | fn reset_value() -> Self::Ux { 186 | 0 187 | } 188 | } 189 | -------------------------------------------------------------------------------- /src/pac/fdcan/ttts.rs: -------------------------------------------------------------------------------- 1 | ///Register `TTTS` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TTTS` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `SWTDEL` reader - Stop watch trigger input selection 38 | pub struct SWTDEL_R(crate::FieldReader); 39 | impl SWTDEL_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | SWTDEL_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for SWTDEL_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `SWTDEL` writer - Stop watch trigger input selection 52 | pub struct SWTDEL_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> SWTDEL_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); 60 | self.w 61 | } 62 | } 63 | ///Field `EVTSEL` reader - Event trigger input selection 64 | pub struct EVTSEL_R(crate::FieldReader); 65 | impl EVTSEL_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | EVTSEL_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for EVTSEL_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `EVTSEL` writer - Event trigger input selection 78 | pub struct EVTSEL_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> EVTSEL_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); 86 | self.w 87 | } 88 | } 89 | impl R { 90 | ///Bits 0:1 - Stop watch trigger input selection 91 | #[inline(always)] 92 | pub fn swtdel(&self) -> SWTDEL_R { 93 | SWTDEL_R::new((self.bits & 0x03) as u8) 94 | } 95 | ///Bits 4:5 - Event trigger input selection 96 | #[inline(always)] 97 | pub fn evtsel(&self) -> EVTSEL_R { 98 | EVTSEL_R::new(((self.bits >> 4) & 0x03) as u8) 99 | } 100 | } 101 | impl W { 102 | ///Bits 0:1 - Stop watch trigger input selection 103 | #[inline(always)] 104 | pub fn swtdel(&mut self) -> SWTDEL_W { 105 | SWTDEL_W { w: self } 106 | } 107 | ///Bits 4:5 - Event trigger input selection 108 | #[inline(always)] 109 | pub fn evtsel(&mut self) -> EVTSEL_W { 110 | EVTSEL_W { w: self } 111 | } 112 | ///Writes raw bits to the register. 113 | #[inline(always)] 114 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 115 | self.0.bits(bits); 116 | self 117 | } 118 | } 119 | ///FDCAN TT Trigger Select Register 120 | /// 121 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 122 | /// 123 | ///For information about available fields see [ttts](index.html) module 124 | pub struct TTTS_SPEC; 125 | impl crate::RegisterSpec for TTTS_SPEC { 126 | type Ux = u32; 127 | } 128 | ///`read()` method returns [ttts::R](R) reader structure 129 | impl crate::Readable for TTTS_SPEC { 130 | type Reader = R; 131 | } 132 | ///`write(|w| ..)` method takes [ttts::W](W) writer structure 133 | impl crate::Writable for TTTS_SPEC { 134 | type Writer = W; 135 | } 136 | ///`reset()` method sets TTTS to value 0 137 | impl crate::Resettable for TTTS_SPEC { 138 | #[inline(always)] 139 | fn reset_value() -> Self::Ux { 140 | 0 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/pac/fdcan/turcf.rs: -------------------------------------------------------------------------------- 1 | ///Register `TURCF` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TURCF` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `NCL` reader - Numerator Configuration Low. 38 | pub struct NCL_R(crate::FieldReader); 39 | impl NCL_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | NCL_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for NCL_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `NCL` writer - Numerator Configuration Low. 52 | pub struct NCL_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> NCL_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); 60 | self.w 61 | } 62 | } 63 | ///Field `DC` reader - Denominator Configuration. 64 | pub struct DC_R(crate::FieldReader); 65 | impl DC_R { 66 | pub(crate) fn new(bits: u16) -> Self { 67 | DC_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for DC_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `DC` writer - Denominator Configuration. 78 | pub struct DC_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> DC_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x3fff << 16)) | ((value as u32 & 0x3fff) << 16); 86 | self.w 87 | } 88 | } 89 | ///Field `ELT` reader - Enable Local Time 90 | pub struct ELT_R(crate::FieldReader); 91 | impl ELT_R { 92 | pub(crate) fn new(bits: bool) -> Self { 93 | ELT_R(crate::FieldReader::new(bits)) 94 | } 95 | } 96 | impl core::ops::Deref for ELT_R { 97 | type Target = crate::FieldReader; 98 | #[inline(always)] 99 | fn deref(&self) -> &Self::Target { 100 | &self.0 101 | } 102 | } 103 | ///Field `ELT` writer - Enable Local Time 104 | pub struct ELT_W<'a> { 105 | w: &'a mut W, 106 | } 107 | impl<'a> ELT_W<'a> { 108 | ///Sets the field bit 109 | #[inline(always)] 110 | pub fn set_bit(self) -> &'a mut W { 111 | self.bit(true) 112 | } 113 | ///Clears the field bit 114 | #[inline(always)] 115 | pub fn clear_bit(self) -> &'a mut W { 116 | self.bit(false) 117 | } 118 | ///Writes raw bits to the field 119 | #[inline(always)] 120 | pub fn bit(self, value: bool) -> &'a mut W { 121 | self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); 122 | self.w 123 | } 124 | } 125 | impl R { 126 | ///Bits 0:15 - Numerator Configuration Low. 127 | #[inline(always)] 128 | pub fn ncl(&self) -> NCL_R { 129 | NCL_R::new((self.bits & 0xffff) as u16) 130 | } 131 | ///Bits 16:29 - Denominator Configuration. 132 | #[inline(always)] 133 | pub fn dc(&self) -> DC_R { 134 | DC_R::new(((self.bits >> 16) & 0x3fff) as u16) 135 | } 136 | ///Bit 31 - Enable Local Time 137 | #[inline(always)] 138 | pub fn elt(&self) -> ELT_R { 139 | ELT_R::new(((self.bits >> 31) & 0x01) != 0) 140 | } 141 | } 142 | impl W { 143 | ///Bits 0:15 - Numerator Configuration Low. 144 | #[inline(always)] 145 | pub fn ncl(&mut self) -> NCL_W { 146 | NCL_W { w: self } 147 | } 148 | ///Bits 16:29 - Denominator Configuration. 149 | #[inline(always)] 150 | pub fn dc(&mut self) -> DC_W { 151 | DC_W { w: self } 152 | } 153 | ///Bit 31 - Enable Local Time 154 | #[inline(always)] 155 | pub fn elt(&mut self) -> ELT_W { 156 | ELT_W { w: self } 157 | } 158 | ///Writes raw bits to the register. 159 | #[inline(always)] 160 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 161 | self.0.bits(bits); 162 | self 163 | } 164 | } 165 | ///FDCAN TUR Configuration Register 166 | /// 167 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 168 | /// 169 | ///For information about available fields see [turcf](index.html) module 170 | pub struct TURCF_SPEC; 171 | impl crate::RegisterSpec for TURCF_SPEC { 172 | type Ux = u32; 173 | } 174 | ///`read()` method returns [turcf::R](R) reader structure 175 | impl crate::Readable for TURCF_SPEC { 176 | type Reader = R; 177 | } 178 | ///`write(|w| ..)` method takes [turcf::W](W) writer structure 179 | impl crate::Writable for TURCF_SPEC { 180 | type Writer = W; 181 | } 182 | ///`reset()` method sets TURCF to value 0 183 | impl crate::Resettable for TURCF_SPEC { 184 | #[inline(always)] 185 | fn reset_value() -> Self::Ux { 186 | 0 187 | } 188 | } 189 | -------------------------------------------------------------------------------- /src/pac/fdcan/turna.rs: -------------------------------------------------------------------------------- 1 | ///Register `TURNA` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `NAV` reader - Numerator Actual Value 17 | pub struct NAV_R(crate::FieldReader); 18 | impl NAV_R { 19 | pub(crate) fn new(bits: u32) -> Self { 20 | NAV_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for NAV_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | impl R { 31 | ///Bits 0:17 - Numerator Actual Value 32 | #[inline(always)] 33 | pub fn nav(&self) -> NAV_R { 34 | NAV_R::new((self.bits & 0x0003_ffff) as u32) 35 | } 36 | } 37 | ///FDCAN TUR Numerator Actual Register 38 | /// 39 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 40 | /// 41 | ///For information about available fields see [turna](index.html) module 42 | pub struct TURNA_SPEC; 43 | impl crate::RegisterSpec for TURNA_SPEC { 44 | type Ux = u32; 45 | } 46 | ///`read()` method returns [turna::R](R) reader structure 47 | impl crate::Readable for TURNA_SPEC { 48 | type Reader = R; 49 | } 50 | ///`reset()` method sets TURNA to value 0 51 | impl crate::Resettable for TURNA_SPEC { 52 | #[inline(always)] 53 | fn reset_value() -> Self::Ux { 54 | 0 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbar.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBAR` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXBAR` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `AR` reader - Add Request 38 | pub struct AR_R(crate::FieldReader); 39 | impl AR_R { 40 | pub(crate) fn new(bits: u32) -> Self { 41 | AR_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for AR_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `AR` writer - Add Request 52 | pub struct AR_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> AR_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:31 - Add Request 65 | #[inline(always)] 66 | pub fn ar(&self) -> AR_R { 67 | AR_R::new((self.bits & 0xffff_ffff) as u32) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:31 - Add Request 72 | #[inline(always)] 73 | pub fn ar(&mut self) -> AR_W { 74 | AR_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Tx Buffer Add Request Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [txbar](index.html) module 88 | pub struct TXBAR_SPEC; 89 | impl crate::RegisterSpec for TXBAR_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [txbar::R](R) reader structure 93 | impl crate::Readable for TXBAR_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [txbar::W](W) writer structure 97 | impl crate::Writable for TXBAR_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TXBAR to value 0 101 | impl crate::Resettable for TXBAR_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbc_g0_g4_l5.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXBC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | 38 | ///Field `TFQM` reader - Tx FIFO/Queue Mode 39 | pub struct TFQM_R(crate::FieldReader); 40 | impl TFQM_R { 41 | pub(crate) fn new(bits: bool) -> Self { 42 | TFQM_R(crate::FieldReader::new(bits)) 43 | } 44 | } 45 | impl core::ops::Deref for TFQM_R { 46 | type Target = crate::FieldReader; 47 | #[inline(always)] 48 | fn deref(&self) -> &Self::Target { 49 | &self.0 50 | } 51 | } 52 | ///Field `TFQM` writer - Tx FIFO/Queue Mode 53 | pub struct TFQM_W<'a> { 54 | w: &'a mut W, 55 | } 56 | impl<'a> TFQM_W<'a> { 57 | ///Sets the field bit 58 | #[inline(always)] 59 | pub fn set_bit(self) -> &'a mut W { 60 | self.bit(true) 61 | } 62 | ///Clears the field bit 63 | #[inline(always)] 64 | pub fn clear_bit(self) -> &'a mut W { 65 | self.bit(false) 66 | } 67 | ///Writes raw bits to the field 68 | #[inline(always)] 69 | pub fn bit(self, value: bool) -> &'a mut W { 70 | self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); 71 | self.w 72 | } 73 | } 74 | impl R { 75 | ///Bit 24 - Tx FIFO/Queue Mode 76 | #[inline(always)] 77 | pub fn tfqm(&self) -> TFQM_R { 78 | TFQM_R::new(((self.bits >> 24) & 0x01) != 0) 79 | } 80 | } 81 | impl W { 82 | ///Bit 24 - Tx FIFO/Queue Mode 83 | #[inline(always)] 84 | pub fn tfqm(&mut self) -> TFQM_W { 85 | TFQM_W { w: self } 86 | } 87 | ///Writes raw bits to the register. 88 | #[inline(always)] 89 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 90 | self.0.bits(bits); 91 | self 92 | } 93 | } 94 | ///FDCAN Tx Buffer Configuration Register 95 | /// 96 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 97 | /// 98 | ///For information about available fields see [txbc](index.html) module 99 | pub struct TXBC_SPEC; 100 | impl crate::RegisterSpec for TXBC_SPEC { 101 | type Ux = u32; 102 | } 103 | ///`read()` method returns [txbc::R](R) reader structure 104 | impl crate::Readable for TXBC_SPEC { 105 | type Reader = R; 106 | } 107 | ///`write(|w| ..)` method takes [txbc::W](W) writer structure 108 | impl crate::Writable for TXBC_SPEC { 109 | type Writer = W; 110 | } 111 | ///`reset()` method sets TXBC to value 0 112 | impl crate::Resettable for TXBC_SPEC { 113 | #[inline(always)] 114 | fn reset_value() -> Self::Ux { 115 | 0 116 | } 117 | } 118 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbcf.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBCF` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `CF` reader - Cancellation Finished 17 | pub struct CF_R(crate::FieldReader); 18 | impl CF_R { 19 | pub(crate) fn new(bits: u32) -> Self { 20 | CF_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for CF_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | impl R { 31 | ///Bits 0:31 - Cancellation Finished 32 | #[inline(always)] 33 | pub fn cf(&self) -> CF_R { 34 | CF_R::new((self.bits & 0xffff_ffff) as u32) 35 | } 36 | } 37 | ///FDCAN Tx Buffer Cancellation Finished Register 38 | /// 39 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 40 | /// 41 | ///For information about available fields see [txbcf](index.html) module 42 | pub struct TXBCF_SPEC; 43 | impl crate::RegisterSpec for TXBCF_SPEC { 44 | type Ux = u32; 45 | } 46 | ///`read()` method returns [txbcf::R](R) reader structure 47 | impl crate::Readable for TXBCF_SPEC { 48 | type Reader = R; 49 | } 50 | ///`reset()` method sets TXBCF to value 0 51 | impl crate::Resettable for TXBCF_SPEC { 52 | #[inline(always)] 53 | fn reset_value() -> Self::Ux { 54 | 0 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbcie.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBCIE` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXBCIE` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `CF` reader - Cancellation Finished Interrupt Enable 38 | pub struct CF_R(crate::FieldReader); 39 | impl CF_R { 40 | pub(crate) fn new(bits: u32) -> Self { 41 | CF_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for CF_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `CF` writer - Cancellation Finished Interrupt Enable 52 | pub struct CF_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> CF_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:31 - Cancellation Finished Interrupt Enable 65 | #[inline(always)] 66 | pub fn cf(&self) -> CF_R { 67 | CF_R::new((self.bits & 0xffff_ffff) as u32) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:31 - Cancellation Finished Interrupt Enable 72 | #[inline(always)] 73 | pub fn cf(&mut self) -> CF_W { 74 | CF_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [txbcie](index.html) module 88 | pub struct TXBCIE_SPEC; 89 | impl crate::RegisterSpec for TXBCIE_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [txbcie::R](R) reader structure 93 | impl crate::Readable for TXBCIE_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [txbcie::W](W) writer structure 97 | impl crate::Writable for TXBCIE_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TXBCIE to value 0 101 | impl crate::Resettable for TXBCIE_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbcr.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBCR` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXBCR` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `CR` reader - Cancellation Request 38 | pub struct CR_R(crate::FieldReader); 39 | impl CR_R { 40 | pub(crate) fn new(bits: u32) -> Self { 41 | CR_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for CR_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `CR` writer - Cancellation Request 52 | pub struct CR_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> CR_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:31 - Cancellation Request 65 | #[inline(always)] 66 | pub fn cr(&self) -> CR_R { 67 | CR_R::new((self.bits & 0xffff_ffff) as u32) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:31 - Cancellation Request 72 | #[inline(always)] 73 | pub fn cr(&mut self) -> CR_W { 74 | CR_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Tx Buffer Cancellation Request Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [txbcr](index.html) module 88 | pub struct TXBCR_SPEC; 89 | impl crate::RegisterSpec for TXBCR_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [txbcr::R](R) reader structure 93 | impl crate::Readable for TXBCR_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [txbcr::W](W) writer structure 97 | impl crate::Writable for TXBCR_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TXBCR to value 0 101 | impl crate::Resettable for TXBCR_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbrp.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBRP` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `TRP` reader - Transmission Request Pending 17 | pub struct TRP_R(crate::FieldReader); 18 | impl TRP_R { 19 | pub(crate) fn new(bits: u32) -> Self { 20 | TRP_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for TRP_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | impl R { 31 | ///Bits 0:31 - Transmission Request Pending 32 | #[inline(always)] 33 | pub fn trp(&self) -> TRP_R { 34 | TRP_R::new((self.bits & 0xffff_ffff) as u32) 35 | } 36 | } 37 | ///FDCAN Tx Buffer Request Pending Register 38 | /// 39 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 40 | /// 41 | ///For information about available fields see [txbrp](index.html) module 42 | pub struct TXBRP_SPEC; 43 | impl crate::RegisterSpec for TXBRP_SPEC { 44 | type Ux = u32; 45 | } 46 | ///`read()` method returns [txbrp::R](R) reader structure 47 | impl crate::Readable for TXBRP_SPEC { 48 | type Reader = R; 49 | } 50 | ///`reset()` method sets TXBRP to value 0 51 | impl crate::Resettable for TXBRP_SPEC { 52 | #[inline(always)] 53 | fn reset_value() -> Self::Ux { 54 | 0 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbtie.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBTIE` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXBTIE` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TIE` reader - Transmission Interrupt Enable 38 | pub struct TIE_R(crate::FieldReader); 39 | impl TIE_R { 40 | pub(crate) fn new(bits: u32) -> Self { 41 | TIE_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TIE_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TIE` writer - Transmission Interrupt Enable 52 | pub struct TIE_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TIE_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:31 - Transmission Interrupt Enable 65 | #[inline(always)] 66 | pub fn tie(&self) -> TIE_R { 67 | TIE_R::new((self.bits & 0xffff_ffff) as u32) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:31 - Transmission Interrupt Enable 72 | #[inline(always)] 73 | pub fn tie(&mut self) -> TIE_W { 74 | TIE_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Tx Buffer Transmission Interrupt Enable Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [txbtie](index.html) module 88 | pub struct TXBTIE_SPEC; 89 | impl crate::RegisterSpec for TXBTIE_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [txbtie::R](R) reader structure 93 | impl crate::Readable for TXBTIE_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [txbtie::W](W) writer structure 97 | impl crate::Writable for TXBTIE_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TXBTIE to value 0 101 | impl crate::Resettable for TXBTIE_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/txbto.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXBTO` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXBTO` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TO` reader - Transmission Occurred. 38 | pub struct TO_R(crate::FieldReader); 39 | impl TO_R { 40 | pub(crate) fn new(bits: u32) -> Self { 41 | TO_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TO_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TO` writer - Transmission Occurred. 52 | pub struct TO_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TO_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:31 - Transmission Occurred. 65 | #[inline(always)] 66 | pub fn to(&self) -> TO_R { 67 | TO_R::new((self.bits & 0xffff_ffff) as u32) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:31 - Transmission Occurred. 72 | #[inline(always)] 73 | pub fn to(&mut self) -> TO_W { 74 | TO_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Tx Buffer Transmission Occurred Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [txbto](index.html) module 88 | pub struct TXBTO_SPEC; 89 | impl crate::RegisterSpec for TXBTO_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [txbto::R](R) reader structure 93 | impl crate::Readable for TXBTO_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [txbto::W](W) writer structure 97 | impl crate::Writable for TXBTO_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TXBTO to value 0 101 | impl crate::Resettable for TXBTO_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/txefa.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXEFA` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXEFA` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `EFAI` reader - Event FIFO Acknowledge Index 38 | pub struct EFAI_R(crate::FieldReader); 39 | impl EFAI_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | EFAI_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for EFAI_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `EFAI` writer - Event FIFO Acknowledge Index 52 | pub struct EFAI_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> EFAI_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:4 - Event FIFO Acknowledge Index 65 | #[inline(always)] 66 | pub fn efai(&self) -> EFAI_R { 67 | EFAI_R::new((self.bits & 0x1f) as u8) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:4 - Event FIFO Acknowledge Index 72 | #[inline(always)] 73 | pub fn efai(&mut self) -> EFAI_W { 74 | EFAI_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Tx Event FIFO Acknowledge Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [txefa](index.html) module 88 | pub struct TXEFA_SPEC; 89 | impl crate::RegisterSpec for TXEFA_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [txefa::R](R) reader structure 93 | impl crate::Readable for TXEFA_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [txefa::W](W) writer structure 97 | impl crate::Writable for TXEFA_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TXEFA to value 0 101 | impl crate::Resettable for TXEFA_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/txefc.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXEFC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXEFC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `EFSA` reader - Event FIFO Start Address 38 | pub struct EFSA_R(crate::FieldReader); 39 | impl EFSA_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | EFSA_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for EFSA_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `EFSA` writer - Event FIFO Start Address 52 | pub struct EFSA_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> EFSA_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !(0x3fff << 2)) | ((value as u32 & 0x3fff) << 2); 60 | self.w 61 | } 62 | } 63 | ///Field `EFS` reader - Event FIFO Size 64 | pub struct EFS_R(crate::FieldReader); 65 | impl EFS_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | EFS_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for EFS_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `EFS` writer - Event FIFO Size 78 | pub struct EFS_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> EFS_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); 86 | self.w 87 | } 88 | } 89 | ///Field `EFWM` reader - Event FIFO Watermark 90 | pub struct EFWM_R(crate::FieldReader); 91 | impl EFWM_R { 92 | pub(crate) fn new(bits: u8) -> Self { 93 | EFWM_R(crate::FieldReader::new(bits)) 94 | } 95 | } 96 | impl core::ops::Deref for EFWM_R { 97 | type Target = crate::FieldReader; 98 | #[inline(always)] 99 | fn deref(&self) -> &Self::Target { 100 | &self.0 101 | } 102 | } 103 | ///Field `EFWM` writer - Event FIFO Watermark 104 | pub struct EFWM_W<'a> { 105 | w: &'a mut W, 106 | } 107 | impl<'a> EFWM_W<'a> { 108 | ///Writes raw bits to the field 109 | #[inline(always)] 110 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 111 | self.w.bits = (self.w.bits & !(0x3f << 24)) | ((value as u32 & 0x3f) << 24); 112 | self.w 113 | } 114 | } 115 | impl R { 116 | ///Bits 2:15 - Event FIFO Start Address 117 | #[inline(always)] 118 | pub fn efsa(&self) -> EFSA_R { 119 | EFSA_R::new(((self.bits >> 2) & 0x3fff) as u16) 120 | } 121 | ///Bits 16:21 - Event FIFO Size 122 | #[inline(always)] 123 | pub fn efs(&self) -> EFS_R { 124 | EFS_R::new(((self.bits >> 16) & 0x3f) as u8) 125 | } 126 | ///Bits 24:29 - Event FIFO Watermark 127 | #[inline(always)] 128 | pub fn efwm(&self) -> EFWM_R { 129 | EFWM_R::new(((self.bits >> 24) & 0x3f) as u8) 130 | } 131 | } 132 | impl W { 133 | ///Bits 2:15 - Event FIFO Start Address 134 | #[inline(always)] 135 | pub fn efsa(&mut self) -> EFSA_W { 136 | EFSA_W { w: self } 137 | } 138 | ///Bits 16:21 - Event FIFO Size 139 | #[inline(always)] 140 | pub fn efs(&mut self) -> EFS_W { 141 | EFS_W { w: self } 142 | } 143 | ///Bits 24:29 - Event FIFO Watermark 144 | #[inline(always)] 145 | pub fn efwm(&mut self) -> EFWM_W { 146 | EFWM_W { w: self } 147 | } 148 | ///Writes raw bits to the register. 149 | #[inline(always)] 150 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 151 | self.0.bits(bits); 152 | self 153 | } 154 | } 155 | ///FDCAN Tx Event FIFO Configuration Register 156 | /// 157 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 158 | /// 159 | ///For information about available fields see [txefc](index.html) module 160 | pub struct TXEFC_SPEC; 161 | impl crate::RegisterSpec for TXEFC_SPEC { 162 | type Ux = u32; 163 | } 164 | ///`read()` method returns [txefc::R](R) reader structure 165 | impl crate::Readable for TXEFC_SPEC { 166 | type Reader = R; 167 | } 168 | ///`write(|w| ..)` method takes [txefc::W](W) writer structure 169 | impl crate::Writable for TXEFC_SPEC { 170 | type Writer = W; 171 | } 172 | ///`reset()` method sets TXEFC to value 0 173 | impl crate::Resettable for TXEFC_SPEC { 174 | #[inline(always)] 175 | fn reset_value() -> Self::Ux { 176 | 0 177 | } 178 | } 179 | -------------------------------------------------------------------------------- /src/pac/fdcan/txesc.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXESC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `TXESC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `TBDS` reader - Tx Buffer Data Field Size: 38 | pub struct TBDS_R(crate::FieldReader); 39 | impl TBDS_R { 40 | pub(crate) fn new(bits: u8) -> Self { 41 | TBDS_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for TBDS_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `TBDS` writer - Tx Buffer Data Field Size: 52 | pub struct TBDS_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> TBDS_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:2 - Tx Buffer Data Field Size: 65 | #[inline(always)] 66 | pub fn tbds(&self) -> TBDS_R { 67 | TBDS_R::new((self.bits & 0x07) as u8) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:2 - Tx Buffer Data Field Size: 72 | #[inline(always)] 73 | pub fn tbds(&mut self) -> TBDS_W { 74 | TBDS_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Tx Buffer Element Size Configuration Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [txesc](index.html) module 88 | pub struct TXESC_SPEC; 89 | impl crate::RegisterSpec for TXESC_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [txesc::R](R) reader structure 93 | impl crate::Readable for TXESC_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [txesc::W](W) writer structure 97 | impl crate::Writable for TXESC_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets TXESC to value 0 101 | impl crate::Resettable for TXESC_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/txfqs.rs: -------------------------------------------------------------------------------- 1 | ///Register `TXFQS` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Field `TFFL` reader - Tx FIFO Free Level 17 | pub struct TFFL_R(crate::FieldReader); 18 | impl TFFL_R { 19 | pub(crate) fn new(bits: u8) -> Self { 20 | TFFL_R(crate::FieldReader::new(bits)) 21 | } 22 | } 23 | impl core::ops::Deref for TFFL_R { 24 | type Target = crate::FieldReader; 25 | #[inline(always)] 26 | fn deref(&self) -> &Self::Target { 27 | &self.0 28 | } 29 | } 30 | ///Field `TFGI` reader - TFGI 31 | pub struct TFGI_R(crate::FieldReader); 32 | impl TFGI_R { 33 | pub(crate) fn new(bits: u8) -> Self { 34 | TFGI_R(crate::FieldReader::new(bits)) 35 | } 36 | } 37 | impl core::ops::Deref for TFGI_R { 38 | type Target = crate::FieldReader; 39 | #[inline(always)] 40 | fn deref(&self) -> &Self::Target { 41 | &self.0 42 | } 43 | } 44 | ///Field `TFQPI` reader - Tx FIFO/Queue Put Index 45 | pub struct TFQPI_R(crate::FieldReader); 46 | impl TFQPI_R { 47 | pub(crate) fn new(bits: u8) -> Self { 48 | TFQPI_R(crate::FieldReader::new(bits)) 49 | } 50 | } 51 | impl core::ops::Deref for TFQPI_R { 52 | type Target = crate::FieldReader; 53 | #[inline(always)] 54 | fn deref(&self) -> &Self::Target { 55 | &self.0 56 | } 57 | } 58 | ///Field `TFQF` reader - Tx FIFO/Queue Full 59 | pub struct TFQF_R(crate::FieldReader); 60 | impl TFQF_R { 61 | pub(crate) fn new(bits: bool) -> Self { 62 | TFQF_R(crate::FieldReader::new(bits)) 63 | } 64 | } 65 | impl core::ops::Deref for TFQF_R { 66 | type Target = crate::FieldReader; 67 | #[inline(always)] 68 | fn deref(&self) -> &Self::Target { 69 | &self.0 70 | } 71 | } 72 | impl R { 73 | ///Bits 0:5 - Tx FIFO Free Level 74 | #[inline(always)] 75 | pub fn tffl(&self) -> TFFL_R { 76 | TFFL_R::new((self.bits & 0x3f) as u8) 77 | } 78 | ///Bits 8:12 - TFGI 79 | #[inline(always)] 80 | pub fn tfgi(&self) -> TFGI_R { 81 | TFGI_R::new(((self.bits >> 8) & 0x1f) as u8) 82 | } 83 | ///Bits 16:20 - Tx FIFO/Queue Put Index 84 | #[inline(always)] 85 | pub fn tfqpi(&self) -> TFQPI_R { 86 | TFQPI_R::new(((self.bits >> 16) & 0x1f) as u8) 87 | } 88 | ///Bit 21 - Tx FIFO/Queue Full 89 | #[inline(always)] 90 | pub fn tfqf(&self) -> TFQF_R { 91 | TFQF_R::new(((self.bits >> 21) & 0x01) != 0) 92 | } 93 | } 94 | ///FDCAN Tx FIFO/Queue Status Register 95 | /// 96 | ///This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 97 | /// 98 | ///For information about available fields see [txfqs](index.html) module 99 | pub struct TXFQS_SPEC; 100 | impl crate::RegisterSpec for TXFQS_SPEC { 101 | type Ux = u32; 102 | } 103 | ///`read()` method returns [txfqs::R](R) reader structure 104 | impl crate::Readable for TXFQS_SPEC { 105 | type Reader = R; 106 | } 107 | ///`reset()` method sets TXFQS to value 0 108 | impl crate::Resettable for TXFQS_SPEC { 109 | #[inline(always)] 110 | fn reset_value() -> Self::Ux { 111 | 0 112 | } 113 | } 114 | -------------------------------------------------------------------------------- /src/pac/fdcan/xidam.rs: -------------------------------------------------------------------------------- 1 | ///Register `XIDAM` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `XIDAM` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `EIDM` reader - Extended ID Mask 38 | pub struct EIDM_R(crate::FieldReader); 39 | impl EIDM_R { 40 | pub(crate) fn new(bits: u32) -> Self { 41 | EIDM_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for EIDM_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `EIDM` writer - Extended ID Mask 52 | pub struct EIDM_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> EIDM_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u32) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !0x1fff_ffff) | (value as u32 & 0x1fff_ffff); 60 | self.w 61 | } 62 | } 63 | impl R { 64 | ///Bits 0:28 - Extended ID Mask 65 | #[inline(always)] 66 | pub fn eidm(&self) -> EIDM_R { 67 | EIDM_R::new((self.bits & 0x1fff_ffff) as u32) 68 | } 69 | } 70 | impl W { 71 | ///Bits 0:28 - Extended ID Mask 72 | #[inline(always)] 73 | pub fn eidm(&mut self) -> EIDM_W { 74 | EIDM_W { w: self } 75 | } 76 | ///Writes raw bits to the register. 77 | #[inline(always)] 78 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 79 | self.0.bits(bits); 80 | self 81 | } 82 | } 83 | ///FDCAN Extended ID and Mask Register 84 | /// 85 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 86 | /// 87 | ///For information about available fields see [xidam](index.html) module 88 | pub struct XIDAM_SPEC; 89 | impl crate::RegisterSpec for XIDAM_SPEC { 90 | type Ux = u32; 91 | } 92 | ///`read()` method returns [xidam::R](R) reader structure 93 | impl crate::Readable for XIDAM_SPEC { 94 | type Reader = R; 95 | } 96 | ///`write(|w| ..)` method takes [xidam::W](W) writer structure 97 | impl crate::Writable for XIDAM_SPEC { 98 | type Writer = W; 99 | } 100 | ///`reset()` method sets XIDAM to value 0 101 | impl crate::Resettable for XIDAM_SPEC { 102 | #[inline(always)] 103 | fn reset_value() -> Self::Ux { 104 | 0 105 | } 106 | } 107 | -------------------------------------------------------------------------------- /src/pac/fdcan/xidfc.rs: -------------------------------------------------------------------------------- 1 | ///Register `XIDFC` reader 2 | pub struct R(crate::R); 3 | impl core::ops::Deref for R { 4 | type Target = crate::R; 5 | #[inline(always)] 6 | fn deref(&self) -> &Self::Target { 7 | &self.0 8 | } 9 | } 10 | impl From> for R { 11 | #[inline(always)] 12 | fn from(reader: crate::R) -> Self { 13 | R(reader) 14 | } 15 | } 16 | ///Register `XIDFC` writer 17 | pub struct W(crate::W); 18 | impl core::ops::Deref for W { 19 | type Target = crate::W; 20 | #[inline(always)] 21 | fn deref(&self) -> &Self::Target { 22 | &self.0 23 | } 24 | } 25 | impl core::ops::DerefMut for W { 26 | #[inline(always)] 27 | fn deref_mut(&mut self) -> &mut Self::Target { 28 | &mut self.0 29 | } 30 | } 31 | impl From> for W { 32 | #[inline(always)] 33 | fn from(writer: crate::W) -> Self { 34 | W(writer) 35 | } 36 | } 37 | ///Field `FLESA` reader - Filter List Standard Start Address 38 | pub struct FLESA_R(crate::FieldReader); 39 | impl FLESA_R { 40 | pub(crate) fn new(bits: u16) -> Self { 41 | FLESA_R(crate::FieldReader::new(bits)) 42 | } 43 | } 44 | impl core::ops::Deref for FLESA_R { 45 | type Target = crate::FieldReader; 46 | #[inline(always)] 47 | fn deref(&self) -> &Self::Target { 48 | &self.0 49 | } 50 | } 51 | ///Field `FLESA` writer - Filter List Standard Start Address 52 | pub struct FLESA_W<'a> { 53 | w: &'a mut W, 54 | } 55 | impl<'a> FLESA_W<'a> { 56 | ///Writes raw bits to the field 57 | #[inline(always)] 58 | pub unsafe fn bits(self, value: u16) -> &'a mut W { 59 | self.w.bits = (self.w.bits & !(0x3fff << 2)) | ((value as u32 & 0x3fff) << 2); 60 | self.w 61 | } 62 | } 63 | ///Field `LSE` reader - List Size Extended 64 | pub struct LSE_R(crate::FieldReader); 65 | impl LSE_R { 66 | pub(crate) fn new(bits: u8) -> Self { 67 | LSE_R(crate::FieldReader::new(bits)) 68 | } 69 | } 70 | impl core::ops::Deref for LSE_R { 71 | type Target = crate::FieldReader; 72 | #[inline(always)] 73 | fn deref(&self) -> &Self::Target { 74 | &self.0 75 | } 76 | } 77 | ///Field `LSE` writer - List Size Extended 78 | pub struct LSE_W<'a> { 79 | w: &'a mut W, 80 | } 81 | impl<'a> LSE_W<'a> { 82 | ///Writes raw bits to the field 83 | #[inline(always)] 84 | pub unsafe fn bits(self, value: u8) -> &'a mut W { 85 | self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); 86 | self.w 87 | } 88 | } 89 | impl R { 90 | ///Bits 2:15 - Filter List Standard Start Address 91 | #[inline(always)] 92 | pub fn flesa(&self) -> FLESA_R { 93 | FLESA_R::new(((self.bits >> 2) & 0x3fff) as u16) 94 | } 95 | ///Bits 16:23 - List Size Extended 96 | #[inline(always)] 97 | pub fn lse(&self) -> LSE_R { 98 | LSE_R::new(((self.bits >> 16) & 0xff) as u8) 99 | } 100 | } 101 | impl W { 102 | ///Bits 2:15 - Filter List Standard Start Address 103 | #[inline(always)] 104 | pub fn flesa(&mut self) -> FLESA_W { 105 | FLESA_W { w: self } 106 | } 107 | ///Bits 16:23 - List Size Extended 108 | #[inline(always)] 109 | pub fn lse(&mut self) -> LSE_W { 110 | LSE_W { w: self } 111 | } 112 | ///Writes raw bits to the register. 113 | #[inline(always)] 114 | pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { 115 | self.0.bits(bits); 116 | self 117 | } 118 | } 119 | ///FDCAN Extended ID Filter Configuration Register 120 | /// 121 | ///This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 122 | /// 123 | ///For information about available fields see [xidfc](index.html) module 124 | pub struct XIDFC_SPEC; 125 | impl crate::RegisterSpec for XIDFC_SPEC { 126 | type Ux = u32; 127 | } 128 | ///`read()` method returns [xidfc::R](R) reader structure 129 | impl crate::Readable for XIDFC_SPEC { 130 | type Reader = R; 131 | } 132 | ///`write(|w| ..)` method takes [xidfc::W](W) writer structure 133 | impl crate::Writable for XIDFC_SPEC { 134 | type Writer = W; 135 | } 136 | ///`reset()` method sets XIDFC to value 0 137 | impl crate::Resettable for XIDFC_SPEC { 138 | #[inline(always)] 139 | fn reset_value() -> Self::Ux { 140 | 0 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/pac/mod.rs: -------------------------------------------------------------------------------- 1 | #![allow(non_camel_case_types)] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | use core::marker::PhantomData; 5 | use core::ops::Deref; 6 | 7 | #[doc = "Controller area network"] 8 | pub mod fdcan; 9 | pub mod generic; 10 | --------------------------------------------------------------------------------