├── .github ├── dependabot.yml └── workflows │ └── main.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── sim ├── testbench.v └── uart_sim_receiver.v └── src ├── convert.sh └── neorv32_verilog_wrapper.vhd /.github/dependabot.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/.github/dependabot.yml -------------------------------------------------------------------------------- /.github/workflows/main.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/.github/workflows/main.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/.gitignore -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/.gitmodules -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/LICENSE -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/README.md -------------------------------------------------------------------------------- /sim/testbench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/sim/testbench.v -------------------------------------------------------------------------------- /sim/uart_sim_receiver.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/sim/uart_sim_receiver.v -------------------------------------------------------------------------------- /src/convert.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/src/convert.sh -------------------------------------------------------------------------------- /src/neorv32_verilog_wrapper.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/stnolting/neorv32-verilog/HEAD/src/neorv32_verilog_wrapper.vhd --------------------------------------------------------------------------------