├── pystrath_rfsoc └── __init__.py ├── nb_rf_spectrum.png ├── strathsdr_banner.png ├── nb_rf_data_converters.png ├── open_jupyter_launcher.jpg ├── open_terminal_window.jpg ├── common ├── images │ ├── dsp_slice.eps │ ├── rfsoc_fpga.eps │ ├── clb_overview.eps │ ├── ZCU111_Master.png │ ├── RFSoC_2x2_Master.png │ ├── rf_adc_hierarchy.eps │ ├── rf_adc_interface.eps │ ├── rf_dac_hierarchy.eps │ ├── rf_dac_interface.eps │ ├── strathsdr_banner.png │ ├── super_sample_rate.eps │ ├── real_time_processor.eps │ ├── application_processor.eps │ ├── rfsoc_architecture_overview.eps │ ├── real_time_processor.svg │ ├── application_processor.svg │ ├── rf_dac_interface.svg │ ├── rf_adc_interface.svg │ ├── super_sample_rate.svg │ ├── dsp_slice.svg │ ├── rfsoc_architecture_overview.svg │ ├── clb_overview.svg │ ├── rf_adc_hierarchy.svg │ ├── rf_dac_hierarchy.svg │ └── rfsoc_fpga.svg ├── 03_zynq_rfsoc_development.ipynb ├── 02_exploring_the_rf_dataconverters.ipynb └── 01_rfsoc_architecture_overview.ipynb ├── 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/common/images/rfsoc_architecture_overview.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/strath-sdr/rfsoc_notebooks/HEAD/common/images/rfsoc_architecture_overview.eps -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore Logs 2 | *.log 3 | 4 | # Ignore Simulink Files 5 | *.autosave 6 | *.slxc 7 | *\.hbs 8 | *\.Xil 9 | *\hdl_prj 10 | *\slprj 11 | *\wavedata 12 | 13 | # Ignore Vivado Files 14 | *.jou 15 | *vivado.txt 16 | 17 | # Ignore ./rfstrath/rfstrath/ 18 | **/rfstrath/rfstrath 19 | **/pystrath_rfsoc/pystrath_rfsoc 20 | -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | import os 2 | import shutil 3 | from distutils.dir_util import copy_tree 4 | 5 | from setuptools import find_packages, setup 6 | 7 | # global variables 8 | nb_dir = os.environ['PYNQ_JUPYTER_NOTEBOOKS'] 9 | package_name = 'pystrath_rfsoc' 10 | pip_name = 'pystrath-rfsoc' 11 | data_files = [] 12 | 13 | # copy common notebooks to jupyter home 14 | def copy_common_notebooks(): 15 | src_dir = os.path.join(f'common') 16 | dst_dir = os.path.join(nb_dir, 'rfsoc-notebooks') 17 | if os.path.exists(dst_dir): 18 | shutil.rmtree(dst_dir) 19 | copy_tree(src_dir, dst_dir) 20 | 21 | copy_common_notebooks() 22 | 23 | setup( 24 | name=package_name, 25 | version='0.2.0', 26 | install_requires=[ 27 | 'plotly==5.1.0', 28 | 'pynq==2.7' 29 | ], 30 | author="David Northcote", 31 | packages=find_packages(), 32 | package_data={ 33 | '': data_files, 34 | }, 35 | description="A collection of RFSoC introductory notebooks for PYNQ.") 36 | -------------------------------------------------------------------------------- /common/03_zynq_rfsoc_development.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": {}, 6 | "source": [ 7 | "" 8 | ] 9 | }, 10 | { 11 | "cell_type": "markdown", 12 | "metadata": {}, 13 | "source": [ 14 | "# Zynq RFSoC Platforms and Development\n", 15 | "\n", 16 | "----" 17 | ] 18 | }, 19 | { 20 | "cell_type": "markdown", 21 | "metadata": {}, 22 | "source": [ 23 | "Thank you for using the RFSoC introductory notebooks. These notebooks are still a work in progress. Please come back later when they are updated.\n", 24 | "\n", 25 | "You can check for updates at the [GitHub repository](https://github.com/strath-sdr/rfsoc_notebooks)." 26 | ] 27 | } 28 | ], 29 | "metadata": { 30 | "kernelspec": { 31 | "display_name": "Python 3", 32 | "language": "python", 33 | "name": "python3" 34 | }, 35 | "language_info": { 36 | "codemirror_mode": { 37 | "name": "ipython", 38 | "version": 3 39 | }, 40 | "file_extension": ".py", 41 | "mimetype": "text/x-python", 42 | "name": "python", 43 | "nbconvert_exporter": "python", 44 | "pygments_lexer": "ipython3", 45 | "version": "3.6.5" 46 | } 47 | }, 48 | "nbformat": 4, 49 | "nbformat_minor": 4 50 | } -------------------------------------------------------------------------------- /common/02_exploring_the_rf_dataconverters.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": {}, 6 | "source": [ 7 | "" 8 | ] 9 | }, 10 | { 11 | "cell_type": "markdown", 12 | "metadata": {}, 13 | "source": [ 14 | "# Exploring the RF Data Converters\n", 15 | "\n", 16 | "----" 17 | ] 18 | }, 19 | { 20 | "cell_type": "markdown", 21 | "metadata": {}, 22 | "source": [ 23 | "Thank you for using the RFSoC introductory notebooks. These notebooks are still a work in progress. Please come back later when they are updated.\n", 24 | "\n", 25 | "You can check for updates at the [GitHub repository](https://github.com/strath-sdr/rfsoc_notebooks)." 26 | ] 27 | } 28 | ], 29 | "metadata": { 30 | "kernelspec": { 31 | "display_name": "Python 3", 32 | "language": "python", 33 | "name": "python3" 34 | }, 35 | "language_info": { 36 | "codemirror_mode": { 37 | "name": "ipython", 38 | "version": 3 39 | }, 40 | "file_extension": ".py", 41 | "mimetype": "text/x-python", 42 | "name": "python", 43 | "nbconvert_exporter": "python", 44 | "pygments_lexer": "ipython3", 45 | "version": "3.6.5" 46 | } 47 | }, 48 | "nbformat": 4, 49 | "nbformat_minor": 4 50 | } -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2021, University of Strathclyde - Software Defined Radio Research Laboratory 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | # RFSoC Introductory Notebooks 4 | A collection of RFSoC introductory notebooks. This repository is only compatible with [PYNQ images v2.7](https://github.com/Xilinx/PYNQ/releases) for the [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html) and [RFSoC2x2](http://rfsoc-pynq.io/). 5 | 6 | 7 | 8 | 9 | 10 | ## PYNQ Quick Start 11 | The RFSoC notebooks can be installed on to your development board by running a simple line of code in a command terminal. **However, you will need to connect your board to the internet.** Follow the instructions below to install the notebooks now. 12 | * Power on your RFSoC2x2 or ZCU111 development board with an SD Card containing a fresh PYNQ v2.7 image. 13 | * Navigate to Jupyter Labs by opening a browser (preferably Chrome) and connecting to `http://:9090/lab`. 14 | * We need to open a terminal in Jupyter Lab. Firstly, open a launcher window as shown in the figure below: 15 | 16 |

17 | 18 |

19 | 20 | * Now open a terminal in Jupyter as illustrated below: 21 | 22 |

23 | 24 |

25 | 26 | * Now simply run the code below that will install the package to your system. 27 | 28 | ```sh 29 | pip3 install git+https://github.com/strath-sdr/rfsoc_notebooks 30 | ``` 31 | 32 | Once installation has complete you will find the RFSoC notebooks in the Jupyter workspace directory. The folder will be named 'rfsoc-notebooks'. 33 | -------------------------------------------------------------------------------- /common/images/real_time_processor.svg: -------------------------------------------------------------------------------- 1 | Real-TimeProcessing UnitLow Power SwitchCortex-R5ProcessorTCM RAMs / MPUCortex-R5 Core 0Generic Interrupt Controller (GIC)Low LatencyPeripheral PortLevel 1 Instruction &Data Cache -------------------------------------------------------------------------------- /common/images/application_processor.svg: -------------------------------------------------------------------------------- 1 | ApplicationProcessing UnitSnoop Control Unit (SCU)Cortex-A53ProcessorFPU / NEON / CryptoDebug / Timers / MMULevel 1 Instruction &Data CacheCortex-A53 Core 0Level 2 CacheSnoop Control Unit (SCU) -------------------------------------------------------------------------------- /common/images/rf_dac_interface.svg: -------------------------------------------------------------------------------- 1 | Programmable LogicGenerate / TransferData to RF DACRF DAC BlockNCORealImagFurther ProcessingRF DAC TileFollowerLeaderRF DAC -------------------------------------------------------------------------------- /common/images/rf_adc_interface.svg: -------------------------------------------------------------------------------- 1 | Programmable LogicReceive samplesfrom RF ADCRF ADC BlockNCORealImagPre-ProcessingRF ADC TileLeaderFollowerRF ADCPre-Processing -------------------------------------------------------------------------------- /common/images/super_sample_rate.svg: -------------------------------------------------------------------------------- 1 | Each sample is 16 bits wide.One Sample Per Clock CycleRequired Clock Frequency is 4096 MHzDeserialiseEight Samples Per Clock CycleRequired Clock Frequency is 512 MHzEach sample is 16 bits wide.Each SSR sample is 128 bits wide. -------------------------------------------------------------------------------- /common/images/dsp_slice.svg: -------------------------------------------------------------------------------- 1 | Pre-adder27 x 18MultiplierPatternDetectorBDSP48E2 SliceADCXORPPatternDetect18302748454827Arithmetic LogicUnit (ALU)48 -------------------------------------------------------------------------------- /common/images/rfsoc_architecture_overview.svg: -------------------------------------------------------------------------------- 1 | RPUXilinx Zynq UltraScale+ RFSoC (Gen-1 ZU28DR Device)Cortex-R5CPU 0Low-Power SwitchCortex-R5CPU 1General PeripheralsMultiplexedInput/OutputInterconnect and SwitchesCortex-A53CPU 0Cortex-A53CPU 1Cortex-A53CPU 2Cortex-A53CPU 3APUProgrammable Logic (PL)DDRControllerPS-GTRHigh SpeedPeripheralsProcessing System (PS)PlatformManagementUnitConfigurationSecurityUnitRF Data ConvertersRF DAC 3RF DAC TilesRF DAC 2RF DAC 1RF DAC 0RF ADCTilesRF ADC 1RF ADC 0SD-FEC -------------------------------------------------------------------------------- /common/images/clb_overview.svg: -------------------------------------------------------------------------------- 1 | FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCarry Chain(Vertical Connection)LUTLUTLUTLUTLUTLUTLUTLUTLogic FabricConfigurable Logic Block (CLB) -------------------------------------------------------------------------------- /common/images/rf_adc_hierarchy.svg: -------------------------------------------------------------------------------- 1 | RF ADC Block 0Dual Block RF ADC TileRF-ADCChannelRF-ADCChannelPLLBUFBUFVIN_PVIN_NVIN_PVIN_NADC_CLK_PADC_CLK_NAXI-StreamImagAXI-StreamRealAXI-StreamImagAXI-StreamRealTile ClocksZU28DR RFSoC DeviceRF ADC Block 1NCOPre-ProcessingLeaderRF ADC Block 0NCOLeaderPre-ProcessingPre-ProcessingPre-Processing -------------------------------------------------------------------------------- /common/01_rfsoc_architecture_overview.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": {}, 6 | "source": [ 7 | "" 8 | ] 9 | }, 10 | { 11 | "cell_type": "markdown", 12 | "metadata": {}, 13 | "source": [ 14 | "# Overview of the RFSoC Architecture\n", 15 | "\n", 16 | "----\n", 17 | "\n", 18 | "Throughout this notebook and beyond, we will explore the Xilinx Zynq RFSoC architecture, RF Data Converters (RF DCs), and development tools. There are a wide variety of RFSoC devices available. Therefore, we will pay particular attention to the ZU28DR RFSoC device, as this is used widely on several RFSoC development platforms. By the end of this notebook series you will have thoroughly explored many of the RFSoC's capabilities and be more 'in-tune' with its processing features. These notebooks will enable you to start your RFSoC developement adventure.\n", 19 | "\n", 20 | "## Table of Contents\n", 21 | "* [Overview of the RFSoC Architecture](#overview_of_the_rfsoc_architecture)\n", 22 | " * [Generations of RFSoC](#generations_of_rfsoc)\n", 23 | " * [The First in a Generation](#the_first_in_a_generation)\n", 24 | " * [The RFSoC Device Family](#the_rfsoc_device_family)\n", 25 | " * [The Processing System](#the_processing_system)\n", 26 | " * [The Application Processor](#the_application_processor)\n", 27 | " * [The Real-Time Processor](#the_real_time_processor)\n", 28 | " * [Platform Management and Security](#platform_management_and_security)\n", 29 | " * [The Programmable Logic](#the_programmable_logic)\n", 30 | " * [The Logic Fabric](#the_logic_fabric)\n", 31 | " * [Special Processing Resources](#special_processing_resources)\n", 32 | " * [The RF Interface](#the_rf_interface)\n", 33 | " * [Super Sample Rate](#super_sample_rate)\n", 34 | " * [The RF Data Converters](#the_rf_data_converters)\n", 35 | " * [The RF ADC Hierarchy](#the_rf_adc_hierarchy)\n", 36 | " * [The RF DAC Hierarchy](#the_rf_dac_hierarchy)\n", 37 | " * [Conclusion](#conclusion)\n", 38 | " * [References](#references)\n", 39 | " \n", 40 | "## Revision History\n", 41 | "* **v1.0** | 27/02/2021 | First RFSoC overview notebook\n", 42 | " " 43 | ] 44 | }, 45 | { 46 | "cell_type": "markdown", 47 | "metadata": {}, 48 | "source": [ 49 | "----" 50 | ] 51 | }, 52 | { 53 | "cell_type": "markdown", 54 | "metadata": {}, 55 | "source": [ 56 | "## Generations of RFSoC \n", 57 | "The Zynq System-on-Chip (SoC) [[1]](#ref-1) and the Zynq Multiprocessor System-on-Chip (MPSoC) [[2]](#ref-2), each have several chip variations consisting of different families and features. The Zynq RFSoC is similar to its predecessors. In particular, it has 'device generations', offering progression of functionality and capabilities through the generations. For the purpose of keeping things simple, this notebook series will only describe generation one (commonly referred to as Gen-1) RFSoC devices throughout examples and illustrations. Keep this in mind as you are progressing through this material.\n", 58 | "\n", 59 | "### The First in a Generation \n", 60 | "The Xilinx RFSoC is a single-chip solution for applications demanding high sample rate processing. The Gen-1 RFSoC devices can be considered as a combination of the Zynq MPSoC and several channels of GHz RF samplers. A diagram illustrating the architecture of a typical RFSoC device [[5]](#ref-5) can be seen in [Figure 1](#fig-1).\n", 61 | "\n", 62 | "\n", 63 | "

\n", 64 | "\n", 65 | "
Figure 1: High-level overview of the RFSoC ZU28DR device architecture.
\n", 66 | "
\n", 67 | "\n", 68 | "Below is a list of major RFSoC components that are housed entirely on one RFSoC chip:\n", 69 | "\n", 70 | "* A Processing System (PS).\n", 71 | "* Programmable Logic (PL) containing Field Programmable Gate Array (FPGA) logic fabric.\n", 72 | "* 8 or 16 Channels of RF Samplers.\n", 73 | "* Soft Decision Forward Error Correction (SD-FEC) Blocks.\n", 74 | "\n", 75 | "The RFSoC's PS, contains an Application Processing Unit (APU), a Real-Time Processing Unit (RPU), and a set of Platform Management and Security Configuration processors. The RFSoC's PL is host to FPGA logic fabric that can provide hardware acceleration for computationally intensive arithmetic. The FPGA fabric is conveniently interfaced to the RFSoC's RF DCs, which are the primary communication path to the analogue world. There are two types of RF DCs, the first is the RF Analogue-to-Digital Converter (RF ADC) and the second is the RF Digital-to-Analogue Converter (RF DAC). In this series of notebooks, we will collectively refer to the RF ADCs and RF DACs, as RF DCs.\n", 76 | "\n", 77 | "### The RFSoC Device Family \n", 78 | "Before we further explore the architecture of Gen-1 RFSoC devices, let's take a moment to investigate [Table 1](#tab-1), which presents some useful information about the Gen-1 RFSoC device family [[3]](#ref-3). From here, you will have a better understanding of the different components implemented in each device." 79 | ] 80 | }, 81 | { 82 | "cell_type": "markdown", 83 | "metadata": {}, 84 | "source": [ 85 | "\n", 86 | "
\n", 87 | "
Table 1: The Gen-1 RFSoC device family.
\n", 88 | "
\n", 89 | " \n", 90 | " \n", 91 | " \n", 92 | " \n", 93 | " \n", 94 | " \n", 95 | " \n", 96 | " \n", 97 | " \n", 98 | " \n", 99 | " \n", 100 | " \n", 101 | " \n", 102 | " \n", 103 | " \n", 104 | " \n", 105 | " \n", 106 | " \n", 107 | " \n", 108 | " \n", 109 | " \n", 110 | " \n", 111 | " \n", 112 | " \n", 113 | " \n", 114 | " \n", 115 | " \n", 116 | " \n", 117 | " \n", 118 | " \n", 119 | " \n", 120 | " \n", 121 | " \n", 122 | " \n", 123 | " \n", 124 | " \n", 125 | " \n", 126 | " \n", 127 | " \n", 128 | " \n", 129 | " \n", 130 | " \n", 131 | " \n", 132 | " \n", 133 | " \n", 134 | " \n", 135 | " \n", 136 | " \n", 137 | " \n", 138 | " \n", 139 | " \n", 140 | " \n", 141 | " \n", 142 | " \n", 143 | " \n", 144 | " \n", 145 | " \n", 146 | " \n", 147 | " \n", 148 | " \n", 149 | " \n", 150 | " \n", 151 | " \n", 152 | " \n", 153 | " \n", 154 | " \n", 155 | " \n", 156 | " \n", 157 | " \n", 158 | " \n", 159 | " \n", 160 | " \n", 161 | " \n", 162 | " \n", 163 | " \n", 164 | " \n", 165 | " \n", 166 | " \n", 167 | " \n", 168 | " \n", 169 | " \n", 170 | " \n", 171 | "
Generation 1
ZU21DRZU25DRZU27DRZU28DRZU29DR
ADC Blocks
Max Rate (Gsps)		0
0		8
4.096		8
4.096		8
4.096		16
2.048
DAC Blocks
Max Rate (Gsps)		0
0		8
6.554		8
6.554		8
6.554		16
6.554
SD-FEC Blocks80080
System Logic Cells (K)930678930930930
CLB LUTs (K)425310425425425
Max Dist. RAM (Mb)13.09.613.013.013.0
Total Block RAM (Mb)38.027.838.038.038.0
UltraRAM (Mb)22.513.522.522.522.5
DSP Slices42723145427242724272
\n", 172 | "
" 173 | ] 174 | }, 175 | { 176 | "cell_type": "markdown", 177 | "metadata": {}, 178 | "source": [ 179 | "Pay particular attention to the number of RF ADCs and RF DACs each device contains. Note that the ZU21DR device does not contain any RF DCs, and instead only contains SD-FEC blocks for accelerated forward error correction. The sample frequency of the RF ADCs also change between RFSoC devices depending on the number of available channels." 180 | ] 181 | }, 182 | { 183 | "cell_type": "markdown", 184 | "metadata": {}, 185 | "source": [ 186 | "----" 187 | ] 188 | }, 189 | { 190 | "cell_type": "markdown", 191 | "metadata": {}, 192 | "source": [ 193 | "## The Processing System \n", 194 | "Let's now investigate the RFSoC's PS. From [Figure 1](#fig-1) we can see that the PS contains an APU, RPU, Platform Management Unit (PMU), Configuration Security Unit (CSU) and external memory controller. There are also a variety of hardware drivers for general and high-speed peripheral communication. Each of these components are described thoroughly in the Exploring Zynq MPSoC book [[2]](#ref-2). We will briefly review the APU, RPU, PMU and CSU in this section.\n", 195 | "\n", 196 | "### The Application Processor \n", 197 | "The APU contains an Arm Cortex-A53 Multi-Processor Core (MPCore). The Cortex-A53 MPCore is host to four processing cores, each with their own dedicated computational units. These include a Floating Point Unit (FPU), NEON Media Processing Engine (MPE), Cryptography Extension (Crypto), Memory Management Unit (MMU), and dedicated Level 1 cache memory per core. The entire APU has access to a Snoop Control Unit (SCU) and Level 2 cache memory. An overview of the APU can be seen in [Figure 2](#fig-2).\n", 198 | "\n", 199 | "\n", 200 | "
\n", 201 | "\n", 202 | "
Figure 2: Simplified diagram of the Application Processing Unit.
\n", 203 | "
\n", 204 | "\n", 205 | "A motivation for using the APU is to host an operating system. For example, if you are accessing this notebook on your RFSoC development board, then you are probably using the PYNQ software framework (a Linux based operating system) on the APU. An operating system provides driver support and application control for your RFSoC system design.\n", 206 | "\n", 207 | "### The Real-Time Processor \n", 208 | "The RPU contains two Arm Cortex-R5 cores and should be considered for real-time applications and deterministic system control, as it provides low latency performance. The RPU contains a number of computational units and memories, which include an FPU, Tightly Coupled Memories (TCMs), two local caches, and a Memory Protection Unit (MPU). See [Figure 3](#fig-3) for a simplified overview of the RPU architecture.\n", 209 | "\n", 210 | "\n", 211 | "
\n", 212 | "\n", 213 | "
Figure 3: Overview of the Real-Time Processing System.
\n", 214 | "
\n", 215 | "\n", 216 | "The RPU can be selected to run the FreeRTOS operating system, to support system development and design.\n", 217 | "\n", 218 | "### Platform Management and Security \n", 219 | "The PMU consists of a triplicated MicroBlaze processing unit, which contains hardened processors. Using three MicroBlaze processors rather than one improves the reliability of data handling with a majority voting system. The PMU contains several memories, and Xilinx firmware, which allow it to effectively manage the RFSoC device.\n", 220 | "\n", 221 | "Lastly, the CSU consists of a Secure Processor Block (SPB) and crypto interface block (CIB). Similar to the PMU, the SPB contains three triplicated MicroBlaze processing units. These manage the secure boot of the Arm processors and several other security related features, such as Physically Unclonable Functions (PUFs) and tamper detection. The CIB contains several crypto blocks for secure applications: AES-GCM, SHA-3, and RSA 4096." 222 | ] 223 | }, 224 | { 225 | "cell_type": "markdown", 226 | "metadata": {}, 227 | "source": [ 228 | "----" 229 | ] 230 | }, 231 | { 232 | "cell_type": "markdown", 233 | "metadata": {}, 234 | "source": [ 235 | "## The Programmable Logic \n", 236 | "The PL is an essential part of the RFSoC device, as it directly interfaces to the high sample rate RF ADCs and RF DACs. As we have previously explored, there are several RF DC channels, each can be processed simultaneously by exploiting the parallel processing capabilities of FPGAs. Before we begin exploring the RF DCs, let's review the fundamental building blocks of an FPGA, and investigate its special processing resources for undertaking computationally intensive arithemtic. See [Figure 4](#fig-4) for an architecture overview of the RFSoC's FPGA logic fabric.\n", 237 | "\n", 238 | "\n", 239 | "
\n", 240 | " \n", 241 | "
\n", 242 | "
\n", 243 | "
Figure 4: The Zynq RFSoC's Programmable Logic with FPGA, RF Data Converters, and AXI ports.
\n", 244 | "
\n", 245 | "\n", 246 | "Also shown in [Figure 4](#fig-4) are the Advanced eXtensible Interface (AXI) ports, which enable data transfer between the RFSoC's PL and PS. If you would like to learn more about the AXI ports, see Chapter 3 and Chapter 11 in [[2]](#ref-2).\n", 247 | "\n", 248 | "This section will review the FPGA logic fabric and special processing resources such as Block RAMs, Ultra RAMs, and DSP48E2 slices. Finally, the interface to the RF ADC and RF DAC channels will be investigated.\n", 249 | "\n", 250 | "### The Logic Fabric \n", 251 | "Previously in [Table 1](#tab-1) it was shown that each RFSoC device contains logic cells and Configurable Logic Blocks (CLBs). These resources are fundamental for many Digital Signal Processing (DSP) architectures and implementations. CLBs are arranged in columns in the FPGA logic fabric, and are closely aligned with switch matrices to support signal routing between neighbouring resources. Each CLB in Gen-1 RFSoC devices contain 8 Lookup Tables (LUTs), 16 Flip-Flops (FFs), and other critical routing logic for communicating between CLBs. The routing logic is composed of multiplexers and other special arithmetic carry logic, which are useful for routing signals between adjacent CLBs. See [Figure 5](#fig-5) for an overview of a CLB.\n", 252 | "\n", 253 | "\n", 254 | "
\n", 255 | "\n", 256 | "
Figure 5: Configurable Logic Block (CLB) connections and components overview.
\n", 257 | "
\n", 258 | "\n", 259 | "The FPGA logic fabric has a variety of applications, including constructing various distributed arithmetic circuits such as addition and multiplication, and also hosting distributed RAM using LUTs (see [Table 1](#tab-1) for the maximum distributed RAM per device).\n", 260 | "\n", 261 | "### Special Processing Resources \n", 262 | "The RFSoC is packed full of unique processing resources. The FPGA contains special components to accelerate arithmetic and algorithm computation. The special processing resources are separated into two categories; storage and arithmetic.\n", 263 | "\n", 264 | "#### Block RAM and UltraRAM\n", 265 | "Other than distributed memory, the PL also contains Block RAMs and UltraRAMs for memory storage. Each storage element has their own features and capabilities.\n", 266 | "\n", 267 | "Block RAMs can be configured to operate as a RAM, ROM and First In First Out (FIFO) buffer. When configured as one storage element, a Block RAM can store up to 36Kb of data. Alternatively, the Block RAM can be separated into two individual memories capable of storing 18Kb of data each. Block RAMs are unique because they can be reshaped. For example, a Block RAM can be configured to store 4096 elements x 9 bits, or 8192 elements x 4 bits, and other configurations.\n", 268 | "\n", 269 | "UltraRAM is a larger storage element than Block RAM as it can store up to 100Mb of data in one tile. Unlike Block RAM, an UltraRAM tile cannot be reshaped, as it only supports an address configuration of 4096 elements x 72 bits.\n", 270 | "\n", 271 | "#### DSP48E2 Slices\n", 272 | "Many FPGA architectures benefit from dedicated DSP resources for large arithmetic computations. The RFSoC's PL offers several columns of DSP48E2 slices, which can provide high-speed and wide wordlength arithmetic support. DSP slices can be cascaded with others to increase arithmetic wordlength. [Figure 6](#fig-6) shows the architecture of a DSP slice and the input/output wordlengths of each stage.\n", 273 | "\n", 274 | "\n", 275 | "
\n", 276 | "\n", 277 | "
Figure 6: Simplified block diagram of the DSP48E2 slice.
\n", 278 | "
\n", 279 | "\n", 280 | "Notice that the maximum input to the multiplier is 27x18 bits. The pre-adder (suitable for systolic Finite Impulse Response, FIR, filters) can accept 30x27 bits, and the post-adder can accept 48x45 bits. The DSP48E2 slice is very suitable for implementing FIR filter designs. FIRs can be deployed on the FPGA and perform signal filtering operations such as decimation and interpolation for RFSoC applications.\n", 281 | "\n", 282 | "### The RF Interface \n", 283 | "Finally, the RFSoC's FPGA is our gateway to the RF ADC and RF DAC channels. As previously shown in [Figure 1](#fig-1), there are several RF DC channels that each require their own interface to the FPGA logic fabric. For the purpose of exploring the RF interface, we will focus on one channel only. Signal data is transferred between the RFSoC's FPGA and the RF DCs using the AXI-Stream interface. AXI-Stream is a straightforward data transfer standard that only requires three signals to operate correctly.\n", 284 | "\n", 285 | "* Data — Also known as tdata, this signal is used to transfer data between the FPGA and RF interface.\n", 286 | "* Valid — Also known as tvalid, this signal is used to indicate the presence of valid data on the tdata signal.\n", 287 | "* Ready — Also known as tready, this signal is used to handle backpressure in the AXI-Stream transfer.\n", 288 | "\n", 289 | "Further information on the AXI-Stream interface can be found in [[4]](#ref-4).\n", 290 | "\n", 291 | "The RF interface follows a relatively straightforward design topology. A component is responsible for creating data and the other consumes the data. In the past, this has been referred to as a master and slave topology. We will refer to these terms as the leader and follower respectively.\n", 292 | "\n", 293 | "The leader is responsible for retrieving or generating data so that it can be transferred to the follower. If we first consider an RF DAC channel, we can see that the FPGA is responsible for transferring data onto the RF interface. In this setup, the FPGA is the leader and the RF DAC is the follower, as shown in [Figure 7](#fig-7).\n", 294 | "\n", 295 | "\n", 296 | "
\n", 297 | "\n", 298 | "
Figure 7: The leader/follower interface between the FPGA and RF DAC. Real and imaginary components are concatenated onto a single AXI-Stream interface on ZU28DR devices. Configuration shown is complex-to-real mode.
\n", 299 | "
\n", 300 | "\n", 301 | "In constrast, an RF ADC channel will transfer data onto the RF interface for the FPGA to consume. The RF ADC is the leader in this situation, and the FPGA is the follower. An illustration of this setup is shown in [Figure 8](#fig-8).\n", 302 | "\n", 303 | "\n", 304 | "
\n", 305 | "\n", 306 | "
Figure 8: The follower/leader interface between the RF ADC and FPGA. Real and imaginary components are on separate AXI-Stream interfaces on ZU28DR devices.
\n", 307 | "
\n", 308 | "\n", 309 | "The data interface for the RF ADC and RF DAC channels use 16 bits to represent one sample. The AXI-Stream interface operates using a handshaking protocol, where the follower must set the tready signal high to initiate a transfer from the leader.\n", 310 | "\n", 311 | "### Super Sample Rate \n", 312 | "Take a moment to consider the high sample rate of the RFSoC's ADC and DAC channels. Their maximum sample rate is 4096Msps and 6554Msps respectively. If you are familiar with FPGAs, you will realise that these digital signals cannot be clocked sequentially on the FPGA logic fabric, as the required clock frequency is too high. In order to represent these signals, they must be converted to a Super Sample Rate (SSR) representation.\n", 313 | "\n", 314 | "An SSR interface contains several time contiguous samples per AXI-Stream clock cycle. To explain this concept, consider the conceptual diagram presented in [Figure 9](#fig-9). To acquire a signal sampled at 4096Msps, the samples must first be deserialised. Deserialisation increases the signal wordlength, but also has the effect of decreasing the required AXI-Stream clock frequency.\n", 315 | "\n", 316 | "\n", 317 | "
\n", 318 | "\n", 319 | "
Figure 9: Conceptual diagram of converting from a serial interface, to an SSR interface. The RF DCs do not strictly use this technique to create their SSR interface. This diagram attempts to only explain the concept of SSR interfaces.
\n", 320 | "
\n", 321 | "\n", 322 | "SSR interfaces are used regularly to transfer data between the RF DC channels and the RFSoC's FPGA. They are primarily required when the sample rate requirements of the RF interface is too high for single rate implementation.\n", 323 | "\n", 324 | "For all Gen-1 RFSoC devices, an SSR interface uses 16 bits to represent a sample. Therefore, an SSR of 1 will be 16 bits wide, an SSR of 2 will be 32 bits wide, and an SSR of 4 will be 64 bits wide." 325 | ] 326 | }, 327 | { 328 | "cell_type": "markdown", 329 | "metadata": {}, 330 | "source": [ 331 | "----" 332 | ] 333 | }, 334 | { 335 | "cell_type": "markdown", 336 | "metadata": {}, 337 | "source": [ 338 | "## The RF Data Converters \n", 339 | "We've finally arrived at our main topic of discussion. The RFSoC's Data Converter technology, which is one of the significant differences between a Zynq MPSoC and Zynq RFSoC device. When selecting a Zynq device, the RF DCs should be a motivating reason to use an RFSoC for your target application (other than the SD-FEC blocks). Let's quickly review the facts of the RF DCs on the ZU28DR RFSoC device.\n", 340 | "\n", 341 | "* There are 8 RF ADC channels.\n", 342 | " * The maximum sample rate is 4096 Msps.\n", 343 | " * The sampler uses a wordlength of 12 bits.\n", 344 | "* There are 8 RF DAC channels.\n", 345 | " * The maximum sample rate is 6554 Msps.\n", 346 | " * The sampler uses a wordlength of 14 bits.\n", 347 | " \n", 348 | "Although there are 8 RF ADC and RF DAC channels, we should pay particular attention to how they are physically configured. The RFSoC data converters are laid out in tiles, which are host to a group of blocks that implement the core functionality of the associated data converter. This hierarchy of tiles and blocks simplifies the data converter design and implementation. Let's explore the hierarchy of each RF DC in this section to obtain a better understanding of its overall layout.\n", 349 | "\n", 350 | "### The RF ADC Hierarchy \n", 351 | "The RF ADC can be configured as four blocks per tile, or two blocks per tile depending on the selected device. In particular, the ZU28DR device uses a layout of two blocks per tile, meaning a total of 4 tiles are required to host all 8 ADC blocks. A tile can generate all its own clocking requirements using its own Phase Locked Loop (PLL). The PLL requires an external, low-jitter, off-chip clock to operate effectively. An overview of the RF ADC is presented in [Figure 10](#fig-10).\n", 352 | "\n", 353 | "\n", 354 | "
\n", 355 | "\n", 356 | "
Figure 10: RF ADC hierarchy for the ZU28DR RFSoC device.
\n", 357 | "
\n", 358 | "\n", 359 | "Each RF ADC tile uses differential signaling. Therefore, the off-chip analogue signal needs to be differential. As on the ZCU111 + XM500 and RFSoC2x2 development boards, the differential signals are converted to single-ended using an RF Balun.\n", 360 | "\n", 361 | "Each RF ADC block above contains several core processing blocks for a Digital Down Converter (DDC). The RF ADC processing pipeline samples an analogue signal, effectively converting it to the digital domain. The ADC block then applies DSP techniques such as threshold detection and Quadrature Modulation Correction (QMC). The signal is subsequently down converted using a complex mixer and programmable decimator [[5]](#ref-5).\n", 362 | "\n", 363 | "### The RF DAC Hierarchy \n", 364 | "The RF DAC is configured as four blocks per tile, which requires a total of 2 tiles to host all 8 DAC blocks on the ZU28DR device. Similar to the ADC, there is an internal PLL for generating the DAC's clocking requirements. As before, an external, low-jitter clock is required to drive the PLL. [Figure 11](#fig-11) presents an overview of the RF DAC hierarchy.\n", 365 | "\n", 366 | "\n", 367 | "
\n", 368 | "\n", 369 | "
Figure 11: RF DAC hierarchy for the ZU28DR RFSoC device.
\n", 370 | "
\n", 371 | "\n", 372 | "Differential signaling is used again to interface RF DAC data to the outside world. Baluns can be used to convert between differential signals and single-ended signals. \n", 373 | "\n", 374 | "Each RF DAC block contains many functional processing blocks to implement a Digital Up Converter (DUC). The RF DAC contains several stages including a programmable interpolator, complex mixer, QMC processing, and an anti-sinc filter to correct Nyquist Zone 1 droop. Finally, a sampler converts the processed digital signal to the analogue domain for transmission [[5]](#ref-5)." 375 | ] 376 | }, 377 | { 378 | "cell_type": "markdown", 379 | "metadata": {}, 380 | "source": [ 381 | "----" 382 | ] 383 | }, 384 | { 385 | "cell_type": "markdown", 386 | "metadata": {}, 387 | "source": [ 388 | "## Conclusion\n", 389 | "In this notebook we have explored the Xilinx Zynq UltraScale+ RFSoC device architecture. An investigation of the RFSoC's constituent components were reviewed, and the RF DC hierarchy presented. It was found that the RFSoC's FPGA logic fabric interfaces directly with the RF ADC and RF DAC tiles. SSR interfaces are regularly used to transfer high data rates between the FPGA and RF DCs.\n", 390 | "\n", 391 | "The next notebook in this series will explore the RFSoC's data converters in more detail, by investigating the core functionality of RF DC tiles and blocks.\n", 392 | "\n", 393 | "| | [Next Notebook ➡️](02_exploring_the_rf_dataconverters.ipynb)\n", 394 | "\n", 395 | "## References\n", 396 | "\n", 397 | "[1] - [L. H. Crockett, R. A. Elliot, M. A. Enderwitz and R. W. Stewart, The Zynq Book: Embedded Processing with the ARM CortexA9 on the Xilinx Zynq-7000 All Programmable SoC, First Edition, Strathclyde Academic Media, 2014.](http://www.zynqbook.com/)\n", 398 | "\n", 399 | "\n", 400 | "[2] - [Crockett, L., Northcote, D., Ramsay, C., Robinson, F., & Stewart, R. (2019). Exploring Zynq MPSoC: With PYNQ and Machine Learning Applications.](https://www.zynq-mpsoc-book.com/)\n", 401 | "\n", 402 | "\n", 403 | "[3] - [Xilinx, Inc. \"Zynq UltraScale+ RFSoC Product Tables and Product Selection Guide\", xmp105, v1.9, 2020](https://www.xilinx.com/support/documentation/selection-guides/zynq-usp-rfsoc-product-selection-guide.pdf)\n", 404 | "\n", 405 | "\n", 406 | "[4] - [Arm, Ltd. \"AMBA 4 AXI4-Stream Protocol Specification\", Issue A, Version 1.0, March 2010.](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0051a/index.html)\n", 407 | "\n", 408 | "\n", 409 | "[5] - [Xilinx, Inc, \"USP RF Data Converter: LogiCORE IP Product Guide\", PG269, v2.3, June 2020](https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_3/pg269-rf-data-converter.pdf)" 410 | ] 411 | } 412 | ], 413 | "metadata": { 414 | "kernelspec": { 415 | "display_name": "Python 3", 416 | "language": "python", 417 | "name": "python3" 418 | }, 419 | "language_info": { 420 | "codemirror_mode": { 421 | "name": "ipython", 422 | "version": 3 423 | }, 424 | "file_extension": ".py", 425 | "mimetype": "text/x-python", 426 | "name": "python", 427 | "nbconvert_exporter": "python", 428 | "pygments_lexer": "ipython3", 429 | "version": "3.6.5" 430 | } 431 | }, 432 | "nbformat": 4, 433 | "nbformat_minor": 4 434 | } 435 | -------------------------------------------------------------------------------- /common/images/rf_dac_hierarchy.svg: -------------------------------------------------------------------------------- 1 | RF DAC Block 1NCOFurther ProcessingFollowerQuad Block RF DAC TileAXI-StreamReal / ImagRF DAC Block 0NCOFurther ProcessingFollowerRF-DACChannelPLLVOUT_PVOUT_NDAC_CLK_PDAC_CLK_NRF-DACChannelRF-DACChannelRF-DACChannelVOUT_PVOUT_NVOUT_PVOUT_NVOUT_PVOUT_NDAC_AVTTDAC_AVTTRF DAC Block 3NCOFurther ProcessingFollowerRF DAC Block 2NCOFurther ProcessingFollowerTileClocksAXI-StreamReal / ImagAXI-StreamReal / ImagAXI-StreamReal / ImagZU28DR RFSoC Device -------------------------------------------------------------------------------- /common/images/rfsoc_fpga.svg: -------------------------------------------------------------------------------- 1 | Block RAMUltraRAMDSP48E2sInput / OutputPinsLogicFabricConfigurableLogic Block (CLB)RF DAC 0RF DAC 1RF DAC 2RF DAC 3RF DACTileRF ADC 0RF ADC 1RF ADCTileAXI HighPerformancePortsTo PS --------------------------------------------------------------------------------