├── LDPC Decoding for FPGA Implementation Report.pdf
├── LDPC Decoding for FPGA Implementation ppt.pdf
├── README.md
├── ldpc rtl schematic.pdf
├── ldpc rtl.jpg
├── ldpc_for_DESim_Implementation
└── ldpc_decoder.v
├── ldpc_matlab
├── Hard Decision BER.ps
├── Min-Sum Alogorithm BER.ps
├── cmmb_ldpc_encode.m
├── data_in.dat
├── decode_ldpc_new.cpp
├── demapper.m
├── genH.m
├── ldpc_decode.m
├── ldpc_decode_fix.m
├── ldpc_decode_sim.m
├── ldpc_demo.m
├── ldpc_encode.m
├── ldpc_gmatrix.m
├── ldpc_lu.m
├── ldpc_lu2.m
├── ldpc_lu_example.m
├── llr.mat
├── mapper.m
└── sim.mat
└── ldpc_rtl
├── addr_gen.v
├── comp_cell.v
├── data
├── G.mat
├── G34.mat
├── col_order.mat
├── col_order34.mat
├── readme.md
├── readme.txt
├── symbol.mat
└── symbol1.mat
├── data_cell.v
├── data_cell1.v
├── data_cell2.v
├── data_comp.v
├── debug.v
├── fig
├── qpsk12.fig
└── readme.md
├── ldpc.v
├── ldpc_ctrl.v
├── ldpc_dec.v
├── ldpc_vtc.v
├── lr_cell.v
├── out_table.v
├── qpsk12
├── Eb_N0_dB.mat
├── nBitErr.mat
├── readme.md
└── simBer.mat
├── rd_cell.v
├── rd_seq.v
├── readme.md
├── ref
├── QPSK_TX.m
└── script_16qam_gray_mapping_bit_error_rate.m
├── sram256x8.v
├── sram2p256x8.v
├── sram2p768x52.v
├── vtc_cell.v
└── wr_cell.v
/LDPC Decoding for FPGA Implementation Report.pdf:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/LDPC Decoding for FPGA Implementation Report.pdf
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/LDPC Decoding for FPGA Implementation ppt.pdf:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/LDPC Decoding for FPGA Implementation ppt.pdf
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/README.md:
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1 | Download the report [here](https://github.com/sudhamshu091/ldpc-encoder-decoder/raw/main/LDPC%20Decoding%20for%20FPGA%20Implementation%20Report.pdf)
2 | [LDPC RTL](ldpc%20rtl.jpg)
3 | 
4 |
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/ldpc rtl.jpg:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc rtl.jpg
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/ldpc_matlab/decode_ldpc_new.cpp:
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1 |
2 | /*LDPC Decoder*/
3 |
4 | #include "mex.h"
5 | #include "matrix.h"
6 | #include "math.h"
7 | #include
8 | #include "decodeutil_new.h"
9 |
10 | #define INF 1000
11 |
12 | // for fixed point
13 | #define wordLen_din_frag 2
14 | #define wordLen_tanh_frag 6
15 | #define wordLen_tanh_mul 6
16 | #define wordLen_atanh_frag 4
17 | #define wordLen_atanh_real 3
18 |
19 |
20 | double atanh(double x);
21 |
22 |
23 | void decode(double max_iter, double *vhat, int mrows, int ncols, double *iter_out, double *gamma_n,
24 | double *check_node_ones,double max_check_degree, double BIGVALUE_COLS,
25 | double *variable_node_ones,double max_variable_degree,double BIGVALUE_ROWS)
26 |
27 | {//function braces
28 |
29 | int i=0, j=0;
30 |
31 | double **sg_array,**sa_array, **bitmessage_temp ;
32 | double **H, **check_node_ones_matrix,**variable_node_ones_matrix;
33 |
34 | sg_array = matrix(0,mrows-1,0,ncols-1);
35 | sa_array = matrix(0,mrows-1,0,ncols-1);
36 | H = matrix(0,mrows-1,0,ncols-1);
37 |
38 | check_node_ones_matrix=matrix(0,mrows-1,0,max_check_degree-1);
39 | variable_node_ones_matrix=matrix(0,max_variable_degree-1,0,ncols-1);
40 |
41 |
42 |
43 | for (i=0;ipow(2,wordLen_atanh_real))
161 | {
162 | tt2 = pow(2,wordLen_atanh_real);
163 | }
164 |
165 | sa_array[u][(int)element]=tt2;
166 | temp=1;
167 |
168 |
169 | }//across columns
170 |
171 | }//accross mrows
172 |
173 | for ( i=0;i=0)
206 | *(vhat+i)=0;
207 | else
208 | *(vhat+i)=1;
209 | }
210 |
211 | int parity=0,cumsum=0;
212 |
213 | for ( j=0;j(1-epsilon)) return INF;
253 | if(x<(-1+epsilon)) return -INF;
254 | return 0.5*log((1+x)/(1-x));
255 | }
256 |
257 |
258 | void mexFunction( int nlhs, mxArray *plhs[],
259 | int nrhs, const mxArray*prhs[] )
260 | {
261 | double *vhat, *iter_out,*gamma_n, *check_node_ones, *variable_node_ones; /*pointer variables for input Matrices*/
262 | double max_iter,max_check_degree,max_variable_degree, BIGVALUE_COLS,BIGVALUE_ROWS;
263 | int mrows,ncols;
264 |
265 |
266 | gamma_n = mxGetPr(prhs[1]);
267 | check_node_ones=mxGetPr(prhs[2]);
268 | max_check_degree=mxGetScalar(prhs[3]);
269 | BIGVALUE_COLS=mxGetScalar(prhs[4]);
270 |
271 | variable_node_ones=mxGetPr(prhs[5]);
272 | max_variable_degree=mxGetScalar(prhs[6]);
273 | BIGVALUE_ROWS=mxGetScalar(prhs[7]);
274 |
275 |
276 | max_iter = mxGetScalar(prhs[0]);
277 |
278 | mrows = mxGetScalar(prhs[8]);
279 | ncols = mxGetScalar(prhs[9]);
280 |
281 | plhs[0] = mxCreateDoubleMatrix(1,ncols, mxREAL);
282 | vhat = mxGetPr(plhs[0]);
283 | plhs[1] = mxCreateDoubleScalar(0);
284 | iter_out = mxGetPr(plhs[1]);
285 |
286 | decode(max_iter,vhat,mrows,ncols,iter_out,gamma_n,check_node_ones,max_check_degree,BIGVALUE_COLS,variable_node_ones,max_variable_degree,BIGVALUE_ROWS);
287 |
288 |
289 | }
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/ldpc_matlab/demapper.m:
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1 | function [bitseq]=demapper(waveform,mode);
2 | %function [bitseq] = demapper(waveform, mode);
3 | %mode: 'bpsk','qpsk','16qam'
4 | %waveform: output data stream
5 | % amplitude normalize to 1
6 | %bitseq input bit sequence (0, 1)
7 | k_bpsk = 1/sqrt(2);
8 | k_16qam = 1/sqrt(10);
9 |
10 | if (mode == 'bpsk')
11 | for i=1:length(waveform)
12 | bitseq(i) = real(waveform(i))+imag(waveform(i));
13 | end
14 | end
15 |
16 | if (mode == 'qpsk')
17 | for i=1:length(waveform)
18 | bitseq(2*i-1) = real(waveform(i));
19 | bitseq(2*i) = imag(waveform(i));
20 | end
21 | end
22 |
23 | if (mode == '16qm')
24 | rx=waveform/k_16qam;
25 | for i=1:length(rx)
26 | if(abs(real(rx(i)))<=2)
27 | bitseq(4*i-3) = real(rx(i));
28 | elseif(real(rx(i)>2))
29 | bitseq(4*i-3) = 2*(real(rx(i))-1);
30 | else
31 | bitseq(4*i-3) = 2*(real(rx(i))+1);
32 | end
33 | bitseq(4*i-1) = abs(real(rx(i))) - 2;
34 | if(abs(imag(rx(i)))<=2)
35 | bitseq(4*i-2) = imag(rx(i));
36 | elseif(imag(rx(i)>2))
37 | bitseq(4*i-2) = 2*(imag(rx(i))-1);
38 | else
39 | bitseq(4*i-2) = 2*(imag(rx(i))+1);
40 | end
41 | bitseq(4*i) = abs(imag(rx(i))) - 2;
42 | end
43 | end
44 |
45 |
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/ldpc_matlab/genH.m:
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1 | function [H]=genH(coderate);
2 | %function [H]=genH(coderate);
3 | %coderate can be set 1/2 (0.5) or 3/4 (0.75)
4 | %when coderate equals 0.5
5 | % H would be a matrix 4608x9216
6 | %when coderate equlas 0.75
7 | % H must be a matrix 2304x9216
8 | %
9 | % Editor Chenzy on Dec-15-2009
10 |
11 | if(coderate == 0.5)
12 | rows = 4608;
13 | cols = 9216;
14 | %row_flag(1:rows)=0;
15 | HT=zeros(rows,cols);
16 |
17 | %initialization
18 | aij = zeros(18,9216);
19 | r = zeros(18,6);
20 | %look up table from protocol
21 | r(1,:)= [0 6 12 18 25 30];
22 | r(2,:)= [0 7 19 26 31 5664];
23 | r(3,:)= [0 8 13 20 32 8270];
24 | r(4,:)= [1 6 14 21 3085 8959];
25 | r(5,:)= [1 15 27 33 9128 9188];
26 | r(6,:)= [1 9 16 34 8485 9093];
27 | r(7,:)= [2 6 28 35 4156 7760];
28 | r(8,:)= [2 10 17 7335 7545 9138];
29 | r(9,:)= [2 11 22 5278 8728 8962];
30 | r(10,:)= [3 7 2510 4765 8637 8875];
31 | r(11,:)=[3 4653 4744 7541 9175 9198];
32 | r(12,:)=[3 23 2349 9012 9107 9168];
33 | r(13,:)=[4 7 29 5921 7774 8946];
34 | r(14,:)=[4 7224 8074 8339 8725 9212];
35 | r(15,:)=[4 4169 8650 8780 9023 9159];
36 | r(16,:)=[5 8 6638 8986 9064 9210];
37 | r(17,:)=[5 2107 7787 8655 9141 9171];
38 | r(18,:)=[5 24 5939 8507 8906 9173];
39 | %child-matrix gen 18x9216
40 | j = 1;
41 | for k=1:18
42 | for i=1:cols
43 | if (i-1) == r(k,j)
44 | aij(k,i) = 1;
45 | if j<6
46 | j = j + 1;
47 | end
48 | end
49 | end
50 | j = 1;
51 | end
52 | %QC-shift generate full matrix
53 | % A1 A2 A3 ... A256
54 | % A256 A1 A2 A255
55 | % A2 A3 A4 A1
56 | for i = 0:255
57 | for j = 0:255
58 | HT( (i*18+1):(i*18+18), (j*36+1):(j*36+36))= aij( :,( mod(j+256-i,256)*36+1):( mod(j+256-i,256)*36+36) );
59 | end
60 | end
61 | H=HT;
62 | end
63 |
64 | if(coderate == 0.75)
65 | rows = 2304;
66 | cols = 9216;
67 | %row_flag(1:rows)=0;
68 | HT=zeros(rows,cols);
69 |
70 | %initialization
71 | aij = zeros(18,9216);
72 | r = zeros(9,12);
73 | %look up table from protocol
74 | r(1,:)= [0 3 6 12 16 18 21 24 27 31 34 7494];
75 | r(2,:)= [0 4 10 13 25 28 5233 6498 7018 8358 8805 9211];
76 | r(3,:)= [0 7 11 19 22 6729 6831 7913 8944 9013 9133 9184];
77 | r(4,:)= [1 3 8 14 17 20 29 32 5000 5985 7189 7906];
78 | r(5,:)= [1 9 4612 5523 6456 7879 8487 8952 9081 9129 9164 9214];
79 | r(6,:)= [1 5 23 26 33 35 7135 8525 8983 9015 9048 9154];
80 | r(7,:)= [2 3 30 3652 4067 5123 7808 7838 8231 8474 8791 9162];
81 | r(8,:)= [2 35 3774 4310 6827 6917 8264 8416 8542 8834 9044 9089];
82 | r(9,:)= [2 15 631 1077 6256 7859 8069 8160 8657 8958 9094 9116];
83 | %child-matrix gen 9x9216
84 | j = 1;
85 | for k=1:9
86 | for i=1:cols
87 | if (i-1) == r(k,j)
88 | aij(k,i) = 1;
89 | if j<12
90 | j = j + 1;
91 | end
92 | end
93 | end
94 | j = 1;
95 | end
96 | %QC-shift generate full matrix
97 | % A1 A2 A3 ... A256
98 | % A256 A1 A2 A255
99 | % A2 A3 A4 A1
100 | for i = 0:255
101 | for j = 0:255
102 | HT( (i*9+1):(i*9+9), (j*36+1):(j*36+36))= aij(1:9,( mod(j+256-i,256)*36+1):( mod(j+256-i,256)*36+36) );
103 | end
104 | end
105 | H=HT;
106 | end
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/ldpc_matlab/ldpc_decode.m:
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1 | function [R iter]=ldpc_decode(llr,SNR,H,coderate,col_order)
2 | %function [R iter]=ldpc_decode(llr,SNR,H,coderate,col_order);
3 | %llr : log-like ratio
4 | %SNR : SNR value estimation
5 | %H : Check Matrix
6 | %col_order : Reranged Column Order
7 | %R : decoder result
8 | %ber : bit error rate
9 |
10 | iter_num = 20;
11 | alpha = 0.6;
12 | ber = 0;
13 | if coderate == 0.5
14 | row_weight = 6;
15 | row_num = 18;
16 | elseif coderate == 0.75
17 | row_weight = 12;
18 | row_num = 9;
19 | end
20 |
21 | % store first 18 row only for 0.5 coderate
22 | % store first 9 row for 0.75 coderate
23 |
24 | % initilize ram index and offset value
25 | % 18x6 store index and offset
26 | if coderate == 0.5
27 | t=zeros(18,6);
28 | for i=1:18
29 | t(i,:)=find(H(i,:))';
30 | end
31 | index=mod(t,36);
32 | offset=fix(t/36)+1;
33 | % change 0 to 36
34 | n=find(index==0);
35 | index(n)=36;
36 | offset(n)=offset(n)-1;
37 | % 9x12 store index and offset
38 | elseif coderate == 0.75
39 | t=zeros(9,12);
40 | for i=1:9;
41 | t(i,:)=find(H(i,:))';
42 | end
43 | index=mod(t,36);
44 | offset=fix(t/36)+1;
45 | % change 0 to 36
46 | n=find(index==0);
47 | index(n)=36;
48 | offset(n)=offset(n)-1;
49 | end
50 |
51 | % initilize seq_ram
52 | for i =1:256
53 | for j =1:36
54 | seq_ram(j,i) = llr(36*(i-1)+j);
55 | end
56 | end
57 |
58 | % H matrix store, t(i,j) non-zero t_group no-zero m group
59 | % for i = 1:256
60 | % for j =1:256
61 | % temp = H((18*i-17):(18*i),(36*j-35):(36*j));
62 | % t(i,j)=nnz(temp);
63 | % end
64 | % end
65 | % t_group = find(t~=0);
66 |
67 | compresslr=zeros(row_num,256,row_weight+4);
68 |
69 | for iter = 1:iter_num
70 | % Horizontal step: collect lq information
71 | for i = 1:256
72 | for j = 1:row_num
73 | for k = 1:row_weight
74 | x = index(j,k);
75 | y = mod(offset(j,k)+i-1,256);
76 | if y == 0
77 | y = 256;
78 | end
79 | lqij(k) = seq_ram(x,y);
80 | % if x == 36 & y == 6
81 | % x
82 | % y
83 | % seq_ram(x,y)
84 | % end
85 | end
86 |
87 | % Decompress : generate lr information
88 | for k = 1:row_weight
89 | if k == compresslr(j,i,3)
90 | temp_min = compresslr(j,i,2);
91 | else
92 | temp_min = compresslr(j,i,1);
93 | end
94 | sign_temp = mod( compresslr(j,i,k+4)+compresslr(j,i,4), 2);
95 | if sign_temp == 1
96 | lrij(k) = -1 * temp_min;
97 | else
98 | lrij(k) = temp_min;
99 | end
100 | end
101 |
102 | % Retrive lqij' information
103 | if iter == 1
104 | lqij = lqij;
105 | else
106 | lqij = lqij -lrij;
107 | end
108 |
109 | % Min-sum function
110 | % Sign of lqij
111 | sign_xor = 0;
112 | for k = 1:row_weight
113 | if lqij(k) < 0;
114 | sign_xor = mod (sign_xor + 1,2);
115 | sign_lq(k) = 1;
116 | else
117 | sign_lq(k) = 0;
118 | end
119 | end
120 |
121 | % Minimum value
122 | if abs(lqij(1)) < abs(lqij(2))
123 | min_lq = abs(lqij(1));
124 | less_lq = abs(lqij(2));
125 | loc_lq = 1;
126 | else
127 | min_lq = abs(lqij(2));
128 | less_lq = abs(lqij(1));
129 | loc_lq = 2;
130 | end
131 | for k = 3:row_weight
132 | if abs(lqij(k)) < min_lq
133 | less_lq = min_lq;
134 | min_lq = abs(lqij(k));
135 | loc_lq = k;
136 | elseif abs(lqij(k)) < less_lq
137 | less_lq = abs(lqij(k));
138 | end
139 | end
140 | min_lq = alpha * min_lq;
141 | less_lq = alpha * less_lq;
142 | compresslr(j,i,1) = min_lq;
143 | compresslr(j,i,2) = less_lq;
144 | compresslr(j,i,3) = loc_lq;
145 | compresslr(j,i,4) = sign_xor;
146 | compresslr(j,i,5:end) = sign_lq(1:row_weight);
147 |
148 | % Decompress : generate lr information
149 | for k = 1:row_weight
150 | if k == compresslr(j,i,3)
151 | temp_min = compresslr(j,i,2);
152 | else
153 | temp_min = compresslr(j,i,1);
154 | end
155 | sign_temp = mod( compresslr(j,i,k+4)+compresslr(j,i,4), 2);
156 | if sign_temp == 1
157 | lrij(k) = -1 * temp_min;
158 | else
159 | lrij(k) = temp_min;
160 | end
161 | end
162 |
163 | %add new lr back to lq, then write lq back to ram_seq
164 | lqij = lqij + lrij;
165 |
166 | for k = 1:row_weight
167 | x = index(j,k);
168 | y = mod(offset(j,k)+i-1,256);
169 | if y == 0
170 | y = 256;
171 | end
172 | seq_ram(x,y) = lqij(k);
173 | end
174 | end
175 | end
176 | for i =1:256
177 | for j =1:36
178 | llr(36*(i-1)+j) = seq_ram(j,i) ;
179 | end
180 | end
181 | % Hard decision output data
182 | for i =1:length(llr)
183 | R(i) = (llr(i) < 0);
184 | end
185 | PC = mod((H*R'),2);
186 | if nnz(PC) == 0
187 | break;
188 | end
189 | end
190 |
191 |
192 |
193 |
194 |
195 |
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/ldpc_matlab/ldpc_decode_fix.m:
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1 | function [R iter]=ldpc_decode_fix(llr,SNR,H,coderate,col_order)
2 | %function [R iter]=ldpc_decode(llr,SNR,H,coderate,col_order);
3 | %llr : log-like ratio
4 | %SNR : SNR value estimation
5 | %H : Check Matrix
6 | %col_order : Reranged Column Order
7 | %R : decoder result
8 | %ber : bit error rate
9 |
10 | % llr width
11 | llr_width = 5;
12 |
13 | iter_num = 20;
14 | alpha = 0.6;
15 | ber = 0;
16 | if coderate == 0.5
17 | row_weight = 6;
18 | row_num = 18;
19 | elseif coderate == 0.75
20 | row_weight = 12;
21 | row_num = 9;
22 | end
23 |
24 | % store first 18 row only for 0.5 coderate
25 | % store first 9 row for 0.75 coderate
26 |
27 | % initilize ram index and offset value
28 | % 18x6 store index and offset
29 | if coderate == 0.5
30 | t=zeros(18,6);
31 | for i=1:18
32 | t(i,:)=find(H(i,:))';
33 | end
34 | index=mod(t,36);
35 | offset=fix(t/36)+1;
36 | % change 0 to 36
37 | n=find(index==0);
38 | index(n)=36;
39 | offset(n)=offset(n)-1;
40 | % 9x12 store index and offset
41 | elseif coderate == 0.75
42 | t=zeros(9,12);
43 | for i=1:9;
44 | t(i,:)=find(H(i,:))';
45 | end
46 | index=mod(t,36);
47 | offset=fix(t/36)+1;
48 | % change 0 to 36
49 | n=find(index==0);
50 | index(n)=36;
51 | offset(n)=offset(n)-1;
52 | end
53 |
54 | % initilize seq_ram
55 | for i =1:256
56 | for j =1:36
57 | % seq_ram(j,i) = llr(36*(i-1)+j);
58 | temp = floor(llr(36*(i-1)+j)*2^llr_width;
59 | seq_ram(j,i) = temp;
60 | end
61 | end
62 |
63 | % H matrix store, t(i,j) non-zero t_group no-zero m group
64 | % for i = 1:256
65 | % for j =1:256
66 | % temp = H((18*i-17):(18*i),(36*j-35):(36*j));
67 | % t(i,j)=nnz(temp);
68 | % end
69 | % end
70 | % t_group = find(t~=0);
71 |
72 | compresslr=zeros(row_num,256,row_weight+4);
73 |
74 | for iter = 1:iter_num
75 | % Horizontal step: collect lq information
76 | for i = 1:256
77 | for j = 1:row_num
78 | for k = 1:row_weight
79 | x = index(j,k);
80 | y = mod(offset(j,k)+i-1,256);
81 | if y == 0
82 | y = 256;
83 | end
84 | lqij(k) = seq_ram(x,y);
85 | % if x == 36 & y == 6
86 | % x
87 | % y
88 | % seq_ram(x,y)
89 | % end
90 | end
91 |
92 | % Decompress : generate lr information
93 | for k = 1:row_weight
94 | if k == compresslr(j,i,3)
95 | temp_min = compresslr(j,i,2);
96 | else
97 | temp_min = compresslr(j,i,1);
98 | end
99 | sign_temp = mod( compresslr(j,i,k+4)+compresslr(j,i,4), 2);
100 | if sign_temp == 1
101 | lrij(k) = -1 * temp_min;
102 | else
103 | lrij(k) = temp_min;
104 | end
105 | end
106 |
107 | % Retrive lqij' information
108 | if iter == 1
109 | lqij = lqij;
110 | else
111 | lqij = lqij -lrij;
112 | end
113 |
114 | % Min-sum function
115 | % Sign of lqij
116 | sign_xor = 0;
117 | for k = 1:row_weight
118 | if lqij(k) < 0;
119 | sign_xor = mod (sign_xor + 1,2);
120 | sign_lq(k) = 1;
121 | else
122 | sign_lq(k) = 0;
123 | end
124 | end
125 |
126 | % Minimum value
127 | if abs(lqij(1)) < abs(lqij(2))
128 | min_lq = abs(lqij(1));
129 | less_lq = abs(lqij(2));
130 | loc_lq = 1;
131 | else
132 | min_lq = abs(lqij(2));
133 | less_lq = abs(lqij(1));
134 | loc_lq = 2;
135 | end
136 | for k = 3:row_weight
137 | if abs(lqij(k)) < min_lq
138 | less_lq = min_lq;
139 | min_lq = abs(lqij(k));
140 | loc_lq = k;
141 | elseif abs(lqij(k)) < less_lq
142 | less_lq = abs(lqij(k));
143 | end
144 | end
145 | min_lq = alpha * min_lq;
146 | less_lq = alpha * less_lq;
147 | compresslr(j,i,1) = min_lq;
148 | compresslr(j,i,2) = less_lq;
149 | compresslr(j,i,3) = loc_lq;
150 | compresslr(j,i,4) = sign_xor;
151 | compresslr(j,i,5:end) = sign_lq(1:row_weight);
152 |
153 | % Decompress : generate lr information
154 | for k = 1:row_weight
155 | if k == compresslr(j,i,3)
156 | temp_min = compresslr(j,i,2);
157 | else
158 | temp_min = compresslr(j,i,1);
159 | end
160 | sign_temp = mod( compresslr(j,i,k+4)+compresslr(j,i,4), 2);
161 | if sign_temp == 1
162 | lrij(k) = -1 * temp_min;
163 | else
164 | lrij(k) = temp_min;
165 | end
166 | end
167 |
168 | %add new lr back to lq, then write lq back to ram_seq
169 | lqij = lqij + lrij;
170 |
171 | for k = 1:row_weight
172 | x = index(j,k);
173 | y = mod(offset(j,k)+i-1,256);
174 | if y == 0
175 | y = 256;
176 | end
177 | seq_ram(x,y) = lqij(k);
178 | end
179 | end
180 | end
181 | for i =1:256
182 | for j =1:36
183 | llr(36*(i-1)+j) = seq_ram(j,i) ;
184 | end
185 | end
186 | % Hard decision output data
187 | for i =1:length(llr)
188 | R(i) = (llr(i) < 0);
189 | end
190 | PC = mod((H*R'),2);
191 | if nnz(PC) == 0
192 | break;
193 | end
194 | end
195 |
196 |
197 |
198 |
199 |
200 |
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/ldpc_matlab/ldpc_decode_sim.m:
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1 | %function [R iter]=ldpc_decode_fix(llr,SNR,H,coderate,col_order)
2 | %function [R iter]=ldpc_decode(llr,SNR,H,coderate,col_order);
3 | %llr : log-like ratio
4 | %SNR : SNR value estimation
5 | %H : Check Matrix
6 | %col_order : Reranged Column Order
7 | %R : decoder result
8 | %ber : bit error rate
9 |
10 | % llr width
11 | % llr_width = 5;
12 | load sim.mat
13 | load llr.mat
14 |
15 | iter_num = 20;
16 | alpha = 0.625;
17 | ber = 0;
18 | if coderate == 0.5
19 | row_weight = 6;
20 | row_num = 18;
21 | elseif coderate == 0.75
22 | row_weight = 12;
23 | row_num = 9;
24 | end
25 |
26 | % store first 18 row only for 0.5 coderate
27 | % store first 9 row for 0.75 coderate
28 |
29 | % initilize ram index and offset value
30 | % 18x6 store index and offset
31 | if coderate == 0.5
32 | t=zeros(18,6);
33 | for i=1:18
34 | t(i,:)=find(H(i,:))';
35 | end
36 | index=mod(t,36);
37 | offset=fix(t/36)+1;
38 | % change 0 to 36
39 | n=find(index==0);
40 | index(n)=36;
41 | offset(n)=offset(n)-1;
42 | % 9x12 store index and offset
43 | elseif coderate == 0.75
44 | t=zeros(9,12);
45 | for i=1:9;
46 | t(i,:)=find(H(i,:))';
47 | end
48 | index=mod(t,36);
49 | offset=fix(t/36)+1;
50 | % change 0 to 36
51 | n=find(index==0);
52 | index(n)=36;
53 | offset(n)=offset(n)-1;
54 | end
55 |
56 | % initilize seq_ram
57 | for i =1:256
58 | for j =1:36
59 | seq_ram(j,i) = llr(36*(i-1)+j);
60 | % temp = floor(llr(36*(i-1)+j)*2^llr_width;
61 | % seq_ram(j,i) = temp;
62 | end
63 | end
64 |
65 | % H matrix store, t(i,j) non-zero t_group no-zero m group
66 | % for i = 1:256
67 | % for j =1:256
68 | % temp = H((18*i-17):(18*i),(36*j-35):(36*j));
69 | % t(i,j)=nnz(temp);
70 | % end
71 | % end
72 | % t_group = find(t~=0);
73 |
74 | compresslr=zeros(row_num,256,row_weight+4);
75 |
76 | for iter = 1:iter_num
77 | % Horizontal step: collect lq information
78 | for i = 1:256
79 | for j = 1:row_num
80 | for k = 1:row_weight
81 | x = index(j,k);
82 | y = mod(offset(j,k)+i-1,256);
83 | if y == 0
84 | y = 256;
85 | end
86 | lqij(k) = seq_ram(x,y);
87 | % if x == 36 & y == 6
88 | % x
89 | % y
90 | % seq_ram(x,y)
91 | % end
92 | end
93 |
94 | % Decompress : generate lr information
95 | for k = 1:row_weight
96 | if k == compresslr(j,i,3)
97 | temp_min = compresslr(j,i,2);
98 | else
99 | temp_min = compresslr(j,i,1);
100 | end
101 | sign_temp = mod( compresslr(j,i,k+4)+compresslr(j,i,4), 2);
102 | if sign_temp == 1
103 | lrij(k) = -1 * temp_min;
104 | else
105 | lrij(k) = temp_min;
106 | end
107 | end
108 |
109 | % Retrive lqij' information
110 | if iter == 1
111 | lqij = lqij;
112 | else
113 | lqij = lqij -lrij;
114 | end
115 |
116 | % Min-sum function
117 | % Sign of lqij
118 | sign_xor = 0;
119 | for k = 1:row_weight
120 | if lqij(k) < 0;
121 | sign_xor = mod (sign_xor + 1,2);
122 | sign_lq(k) = 1;
123 | else
124 | sign_lq(k) = 0;
125 | end
126 | end
127 |
128 | % Minimum value
129 | if abs(lqij(1)) < abs(lqij(2))
130 | min_lq = abs(lqij(1));
131 | less_lq = abs(lqij(2));
132 | loc_lq = 1;
133 | else
134 | min_lq = abs(lqij(2));
135 | less_lq = abs(lqij(1));
136 | loc_lq = 2;
137 | end
138 | for k = 3:row_weight
139 | if abs(lqij(k)) < min_lq
140 | less_lq = min_lq;
141 | min_lq = abs(lqij(k));
142 | loc_lq = k;
143 | elseif abs(lqij(k)) < less_lq
144 | less_lq = abs(lqij(k));
145 | end
146 | end
147 | min_lq = round(alpha * min_lq);
148 | less_lq = round(alpha * less_lq);
149 | compresslr(j,i,1) = min_lq;
150 | compresslr(j,i,2) = less_lq;
151 | compresslr(j,i,3) = loc_lq;
152 | compresslr(j,i,4) = sign_xor;
153 | compresslr(j,i,5:end) = sign_lq(1:row_weight);
154 |
155 | % Decompress : generate lr information
156 | for k = 1:row_weight
157 | if k == compresslr(j,i,3)
158 | temp_min = compresslr(j,i,2);
159 | else
160 | temp_min = compresslr(j,i,1);
161 | end
162 | sign_temp = mod( compresslr(j,i,k+4)+compresslr(j,i,4), 2);
163 | if sign_temp == 1
164 | lrij(k) = -1 * temp_min;
165 | else
166 | lrij(k) = temp_min;
167 | end
168 | end
169 |
170 | %add new lr back to lq, then write lq back to ram_seq
171 | lqij = lqij + lrij;
172 |
173 | for k = 1:row_weight
174 | x = index(j,k);
175 | y = mod(offset(j,k)+i-1,256);
176 | if y == 0
177 | y = 256;
178 | end
179 | seq_ram(x,y) = lqij(k);
180 | end
181 | end
182 | end
183 | for i =1:256
184 | for j =1:36
185 | llr(36*(i-1)+j) = seq_ram(j,i) ;
186 | end
187 | end
188 | % Hard decision output data
189 | for i =1:length(llr)
190 | R(i) = (llr(i) < 0);
191 | end
192 | PC = mod((H*R'),2);
193 | if nnz(PC) == 0
194 | break;
195 | end
196 | end
197 |
198 |
199 |
200 |
201 |
202 |
--------------------------------------------------------------------------------
/ldpc_matlab/ldpc_demo.m:
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1 | % All rights reserved by Chenzy
2 | % The file simulate CMMB-Stimi LDPC simulation model
3 | % Author : Chen Zhengyi
4 | % Email : czhengyi@126.com
5 | % Version : 1.0
6 | % Data : 25 Dec 2009
7 | %
8 | clc;
9 | clear all;
10 | %modulation = ['bpsk' 'qpsk' '16qm'];
11 | constellation = [ 1 2 4];
12 |
13 | % Parameter Definition here
14 | coderate = 0.5; % 0.75
15 | mode = 'qpsk'; % 'bpsk' 'qpsk' '16qm'
16 | % snr = ; % Signal-Noise ratio
17 | k = constellation(2); % 1 2 4
18 | N = 1; % 500 frame 10^6
19 |
20 | %Eb_N0_dB = [1.2:0.1:2]; % multiple Es/N0 values
21 | Eb_N0_dB = [1.2];
22 | Es_N0_dB = Eb_N0_dB + 10*log10(k);
23 |
24 | for ii = 1:length(Eb_N0_dB)
25 | % symbol generation
26 | % -----------------
27 | inbit = randint(1,N*9216*coderate);
28 | if( coderate == 0.5)
29 | load data\G.mat
30 | load data\col_order.mat
31 | elseif( coderate == 0.75)
32 | load data\G34.mat
33 | load data\col_order34.mat
34 | end
35 | for nframe = 1 : N
36 | symbol = inbit((nframe-1)*9216*coderate+1:nframe*9216*coderate);
37 | pc = mod((G*symbol'),2);
38 | msg(1:9216*(1-coderate)) = pc';
39 | msg(9216*(1-coderate)+1:9216) = symbol;
40 | for i=1:9216
41 | code(col_order(i)+1)=msg(i);
42 | end
43 | tx(1,(nframe-1)*9216+1:nframe*9216)=code;
44 | end
45 | % clear inbit;
46 | clear msg;
47 | clear symbol;
48 | clear pc;
49 | clear code;
50 | clear G;
51 | % Complex constellation
52 | tx_waveform = mapper(tx,mode);
53 | clear tx;
54 |
55 | % noise
56 | % -----
57 | noise = 1/sqrt(2)*[randn(1,length(tx_waveform))+sqrt(-1)*randn(1,length(tx_waveform))];
58 | rx = tx_waveform + 10^(-Es_N0_dB(ii)/20)*noise; % additive white gauss noise
59 | clear noise;
60 | clear tx_waveform;
61 |
62 | % soft demapper
63 | % plot(rx,'.');
64 | llr = demapper(rx,mode);
65 | clear rx;
66 |
67 | % ldpc decode
68 | H=genH(coderate);
69 | for nframe = 1:N
70 | symbol = llr((nframe-1)*9216+1:nframe*9216);
71 | [recode, iter] = ldpc_decode(symbol,0,H,coderate,col_order);
72 | for i = 1:9216*coderate
73 | % outbit(i)=recode(col_order(9216*(1-coderate)+i)+1);
74 | outbit((nframe-1)*9216*coderate+i)=recode(col_order(9216*(1-coderate)+i)+1);
75 | end
76 | clear symbol;
77 | clear recode;
78 | end
79 | nBitErr(ii) = length(find(inbit ~= outbit));
80 | clear H;
81 | clear llr;
82 | end
83 |
84 | simBer = nBitErr/(N*9216);
85 |
86 | semilogy(Eb_N0_dB,simBer,'mx-','LineWidth',2);
87 | axis([0 2 10^-5 1])
88 | grid on
89 | xlabel('Eb/No, dB')
90 | ylabel('Bit Error Rate')
91 | title('Bit error probability curve for QPSK 1/2 coderate')
--------------------------------------------------------------------------------
/ldpc_matlab/ldpc_lu.m:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_matlab/ldpc_lu.m
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/ldpc_matlab/ldpc_lu2.m:
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1 | function [L,U,P] = ldpc_lu2(A)
2 | % clear all;
3 | % clc;
4 | % A=[ 1 1 1 0 0
5 | % 1 0 1 1 0
6 | % 0 0 1 0 1
7 | % 1 0 0 1 0
8 | % 0 0 1 1 1];
9 |
10 | [n,n]=size(A);
11 | L=zeros(n,n);
12 | U=zeros(n,n);
13 | P=eye(n);
14 | %piv=zeros(1,n);
15 | AP = A;
16 |
17 | for i=1:n
18 | % AP
19 | t=find(AP(i:n,i)); % find 1 in column i
20 | max_col = length(t);
21 | min_weight = n + 1; % give a initial value for weight
22 | for k = 1:max_col,
23 | weight = sum(AP(t(k)+i-1,i:n));
24 | if weight < min_weight
25 | index = t(k)+i-1;
26 | min_weight = weight;
27 | end
28 | end
29 |
30 | if( index ~= i)
31 | AP( [i index],:) = AP( [index i],: );
32 | P([i index],:) = P([index i],: );
33 | L( [i index],:) = L ( [index i],:);
34 | end
35 | % AP
36 | U(i,i:n) = AP(i,i:n);
37 | L(i:n,i) = AP(i:n,i);
38 |
39 | % GAUSS elimination
40 | c = find(AP(i+1:n,i));
41 | for k = 1 : length(c)
42 | c1 = c(k) +i;
43 | AP(c1,i:n) = abs ( AP(c1, i:n) - AP(i, i:n));
44 | end
45 |
46 | % for i=1:n
47 | % AP
48 | % t=find(AP(i,i:n)); % find 1 in row i
49 | % max_col = length(t);
50 | % min_weight = max_col + 1; % give a initial value for weight
51 | % for k = 1:max_col,
52 | % weight = sum(AP(i:n, t(k)+i-1));
53 | % if weight < min_weight
54 | % index = t(k)+i-1;
55 | % min_weight = weight;
56 | % end
57 | % end
58 | %
59 | % if( index ~= i)
60 | % AP( :,[i index]) = AP( :,[index i] );
61 | % P(:,[i index]) = P(:,[index i] );
62 | % end
63 | %
64 | % U(i,i:n) = AP(i,i:n);
65 | % L(i:n,i) = AP(i:n,i);
66 | %
67 | % % GAUSS elimination
68 | % c = find(AP(i,i+1:n));
69 | % for k = 1 : length(c)
70 | % c1 = c(k) +i;
71 | % AP(i:n,c1) = abs ( AP(i:n,c1) - AP(i:n,i));
72 | % end
73 |
74 | end
75 |
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/ldpc_matlab/ldpc_lu_example.m:
--------------------------------------------------------------------------------
1 | %function [L,U,P] = ldpc_lu(A)
2 | clear all;
3 | clc;
4 | A=[ 1 1 1 0 0
5 | 1 0 1 1 0
6 | 0 0 1 0 1
7 | 1 0 0 1 0
8 | 0 0 1 1 1];
9 |
10 | %initialization
11 | % [n,n]=size(A);
12 | % L=zeros(n,n);
13 | % U=zeros(n,n);
14 | % P=eye(n);
15 | % %piv=zeros(1,n);
16 | % AP = A;
17 |
18 | %lu decompose
19 | % for i=1:n
20 | % % AP
21 | % t=find(AP(i:n,i)); % find 1 in column i
22 | % max_col = length(t);
23 | % min_weight = n + 1; % give a initial value for weight
24 | % for k = 1:max_col,
25 | % weight = sum(AP(t(k)+i-1,i:n));
26 | % if weight < min_weight
27 | % index = t(k)+i-1;
28 | % min_weight = weight;
29 | % end
30 | % end
31 | %
32 | % if( index ~= i)
33 | % AP( [i index],:) = AP( [index i],: );
34 | % P([i index],:) = P([index i],: );
35 | % L( [i index],:) = L ( [index i],:);
36 | % end
37 | % % AP
38 | % U(i,i:n) = AP(i,i:n);
39 | % L(i:n,i) = AP(i:n,i);
40 |
41 | % % GAUSS elimination
42 | % c = find(AP(i+1:n,i));
43 | % for k = 1 : length(c)
44 | % c1 = c(k) +i;
45 | % AP(c1,i:n) = abs ( AP(c1, i:n) - AP(i, i:n));
46 | % end
47 |
48 | [m,n]=size(A);
49 |
50 | U=A;
51 | L=eye(m);
52 | P=eye(m);
53 |
54 | for i=1:m
55 | i
56 | L
57 | U
58 | P
59 | %find main cell
60 | t =(find(U(i:end,i)==1));
61 | max_col = length(t);
62 | min_row_weight1 = n+1;
63 | for k =1:max_col
64 | row_weight = sum( U(t(k)+i-1,i:end),2);
65 | if row_weight < min_row_weight1
66 | row_index = t(k)+i-1;
67 | min_row_weight1 = row_weight;
68 | end
69 | end
70 |
71 | if(row_index ~= i)
72 | U([i row_index],:) = U([row_index i],:);
73 | P([i,row_index],:) = P([row_index i],:);
74 | if(i>1)
75 | L([i row_index],1:i-1)=L([row_index i],1:i-1);
76 | end
77 | end
78 |
79 | %Gauss elimination
80 | y2=(find(U(i+1:end,i)==1));
81 | k2 = length(y2);
82 | if k2>0
83 | for k3=1:k2
84 | k4=y2(k3)+i;
85 | U(k4,i:end)=abs( U(k4,i:end) - U(i,i:end));
86 | L(k4,i) = abs(L(k4,i) -1);
87 | end
88 | end
89 | end
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/ldpc_matlab/llr.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_matlab/llr.mat
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/ldpc_matlab/mapper.m:
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1 | function [waveform] = mapper(bitseq, mode)
2 | %function [waveform] = mapper(bitseq, mode);
3 | %bitseq input bit sequence [ 0, 1]
4 | %mode: 'bpsk','qpsk','16qam'
5 | %waveform: output data stream
6 | % amplitude normalize to 1
7 | k_bpsk = 1/sqrt(2);
8 | k_16qam = 1/sqrt(10);
9 |
10 | % y = -2 * x + 1;
11 | % x = 0 => y = 1;
12 | % x = 1 => y = -1;
13 | if (mode == 'bpsk')
14 | for i=1:length(bitseq)
15 | mod = (-2*bitseq(i)+1)*(1+sqrt(-1));
16 | waveform(i)=k_bpsk*mod;
17 | end
18 | end
19 |
20 | % y = -2 * x + 1;
21 | if (mode == 'qpsk')
22 | for i=1:length(bitseq)/2
23 | Re_symbol = -2*bitseq(2*i-1)+1;
24 | Im_symbol = -2*bitseq(2*i)+1;
25 | mod = Re_symbol + sqrt(-1)*Im_symbol;
26 | waveform(i)=k_bpsk*mod;
27 | end
28 | end
29 |
30 | % z = ( - 2 * x + 1) * ( -2 * y + 3);
31 | % x = 0, y = 0 => z = 3;
32 | % x = 0, y = 1 => z = 1;
33 | % x = 1, y = 0 => z = -3
34 | % x = 1, y = 1 => z = -1;
35 | if (mode == '16qm')
36 | for i=1:length(bitseq)/4
37 | Re_symbol = (-2*bitseq(4*i-3)+1)*(-2*bitseq(4*i-1)+3);
38 | Im_symbol = (-2*bitseq(4*i-2)+1)*(-2*bitseq(4*i)+3);
39 | mod = Re_symbol + sqrt(-1)*Im_symbol;
40 | waveform(i)=k_16qam*mod;
41 | end
42 | end
43 |
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/ldpc_matlab/sim.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_matlab/sim.mat
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/ldpc_rtl/addr_gen.v:
--------------------------------------------------------------------------------
1 | module addr_gen(
2 | clk,
3 | reset_n,
4 | fsm,
5 | cycle,
6 | rate,
7 | sync_in,
8 | wr_lq,
9 | wr_lr,
10 | rd_lq,
11 | rd_lr,
12 | out_sel,
13 | out_en,
14 | rd_addr00,
15 | rd_addr01,
16 | rd_addr02,
17 | rd_addr03,
18 | rd_addr04,
19 | rd_addr05,
20 | rd_addr06,
21 | rd_addr07,
22 | rd_addr08,
23 | rd_addr09,
24 | rd_addr10,
25 | rd_addr11,
26 | rd_addr12,
27 | rd_addr13,
28 | rd_addr14,
29 | rd_addr15,
30 | rd_addr16,
31 | rd_addr17,
32 | rd_addr18,
33 | rd_addr19,
34 | rd_addr20,
35 | rd_addr21,
36 | rd_addr22,
37 | rd_addr23,
38 | rd_addr24,
39 | rd_addr25,
40 | rd_addr26,
41 | rd_addr27,
42 | rd_addr28,
43 | rd_addr29,
44 | rd_addr30,
45 | rd_addr31,
46 | rd_addr32,
47 | rd_addr33,
48 | rd_addr34,
49 | rd_addr35,
50 | wr_addr00,
51 | wr_addr01,
52 | wr_addr02,
53 | wr_addr03,
54 | wr_addr04,
55 | wr_addr05,
56 | wr_addr06,
57 | wr_addr07,
58 | wr_addr08,
59 | wr_addr09,
60 | wr_addr10,
61 | wr_addr11,
62 | wr_addr12,
63 | wr_addr13,
64 | wr_addr14,
65 | wr_addr15,
66 | wr_addr16,
67 | wr_addr17,
68 | wr_addr18,
69 | wr_addr19,
70 | wr_addr20,
71 | wr_addr21,
72 | wr_addr22,
73 | wr_addr23,
74 | wr_addr24,
75 | wr_addr25,
76 | wr_addr26,
77 | wr_addr27,
78 | wr_addr28,
79 | wr_addr29,
80 | wr_addr30,
81 | wr_addr31,
82 | wr_addr32,
83 | wr_addr33,
84 | wr_addr34,
85 | wr_addr35,
86 | wr00 ,
87 | wr01 ,
88 | wr02 ,
89 | wr03 ,
90 | wr04 ,
91 | wr05 ,
92 | wr06 ,
93 | wr07 ,
94 | wr08 ,
95 | wr09 ,
96 | wr10 ,
97 | wr11 ,
98 | wr12 ,
99 | wr13 ,
100 | wr14 ,
101 | wr15 ,
102 | wr16 ,
103 | wr17 ,
104 | wr18 ,
105 | wr19 ,
106 | wr20 ,
107 | wr21 ,
108 | wr22 ,
109 | wr23 ,
110 | wr24 ,
111 | wr25 ,
112 | wr26 ,
113 | wr27 ,
114 | wr28 ,
115 | wr29 ,
116 | wr30 ,
117 | wr31 ,
118 | wr32 ,
119 | wr33 ,
120 | wr34 ,
121 | wr35 ,
122 | rd_addr ,
123 | wr_addr ,
124 | wr0
125 | );
126 |
127 | parameter A_WID = 8;
128 |
129 | //Input ports
130 | input clk ;
131 | input reset_n ;
132 | input rate ;
133 | input [3:0] fsm ;
134 | input [3:0] cycle ;
135 | input [35:0] sync_in ;
136 | input wr_lq ;
137 | input wr_lr ;
138 | input rd_lq ;
139 | input rd_lr ;
140 |
141 | //Output ports
142 | output [A_WID-1:0] rd_addr00 ;
143 | output [A_WID-1:0] rd_addr01 ;
144 | output [A_WID-1:0] rd_addr02 ;
145 | output [A_WID-1:0] rd_addr03 ;
146 | output [A_WID-1:0] rd_addr04 ;
147 | output [A_WID-1:0] rd_addr05 ;
148 | output [A_WID-1:0] rd_addr06 ;
149 | output [A_WID-1:0] rd_addr07 ;
150 | output [A_WID-1:0] rd_addr08 ;
151 | output [A_WID-1:0] rd_addr09 ;
152 | output [A_WID-1:0] rd_addr10 ;
153 | output [A_WID-1:0] rd_addr11 ;
154 | output [A_WID-1:0] rd_addr12 ;
155 | output [A_WID-1:0] rd_addr13 ;
156 | output [A_WID-1:0] rd_addr14 ;
157 | output [A_WID-1:0] rd_addr15 ;
158 | output [A_WID-1:0] rd_addr16 ;
159 | output [A_WID-1:0] rd_addr17 ;
160 | output [A_WID-1:0] rd_addr18 ;
161 | output [A_WID-1:0] rd_addr19 ;
162 | output [A_WID-1:0] rd_addr20 ;
163 | output [A_WID-1:0] rd_addr21 ;
164 | output [A_WID-1:0] rd_addr22 ;
165 | output [A_WID-1:0] rd_addr23 ;
166 | output [A_WID-1:0] rd_addr24 ;
167 | output [A_WID-1:0] rd_addr25 ;
168 | output [A_WID-1:0] rd_addr26 ;
169 | output [A_WID-1:0] rd_addr27 ;
170 | output [A_WID-1:0] rd_addr28 ;
171 | output [A_WID-1:0] rd_addr29 ;
172 | output [A_WID-1:0] rd_addr30 ;
173 | output [A_WID-1:0] rd_addr31 ;
174 | output [A_WID-1:0] rd_addr32 ;
175 | output [A_WID-1:0] rd_addr33 ;
176 | output [A_WID-1:0] rd_addr34 ;
177 | output [A_WID-1:0] rd_addr35 ;
178 | output [A_WID-1:0] wr_addr00 ;
179 | output [A_WID-1:0] wr_addr01 ;
180 | output [A_WID-1:0] wr_addr02 ;
181 | output [A_WID-1:0] wr_addr03 ;
182 | output [A_WID-1:0] wr_addr04 ;
183 | output [A_WID-1:0] wr_addr05 ;
184 | output [A_WID-1:0] wr_addr06 ;
185 | output [A_WID-1:0] wr_addr07 ;
186 | output [A_WID-1:0] wr_addr08 ;
187 | output [A_WID-1:0] wr_addr09 ;
188 | output [A_WID-1:0] wr_addr10 ;
189 | output [A_WID-1:0] wr_addr11 ;
190 | output [A_WID-1:0] wr_addr12 ;
191 | output [A_WID-1:0] wr_addr13 ;
192 | output [A_WID-1:0] wr_addr14 ;
193 | output [A_WID-1:0] wr_addr15 ;
194 | output [A_WID-1:0] wr_addr16 ;
195 | output [A_WID-1:0] wr_addr17 ;
196 | output [A_WID-1:0] wr_addr18 ;
197 | output [A_WID-1:0] wr_addr19 ;
198 | output [A_WID-1:0] wr_addr20 ;
199 | output [A_WID-1:0] wr_addr21 ;
200 | output [A_WID-1:0] wr_addr22 ;
201 | output [A_WID-1:0] wr_addr23 ;
202 | output [A_WID-1:0] wr_addr24 ;
203 | output [A_WID-1:0] wr_addr25 ;
204 | output [A_WID-1:0] wr_addr26 ;
205 | output [A_WID-1:0] wr_addr27 ;
206 | output [A_WID-1:0] wr_addr28 ;
207 | output [A_WID-1:0] wr_addr29 ;
208 | output [A_WID-1:0] wr_addr30 ;
209 | output [A_WID-1:0] wr_addr31 ;
210 | output [A_WID-1:0] wr_addr32 ;
211 | output [A_WID-1:0] wr_addr33 ;
212 | output [A_WID-1:0] wr_addr34 ;
213 | output [A_WID-1:0] wr_addr35 ;
214 | output wr00 ;
215 | output wr01 ;
216 | output wr02 ;
217 | output wr03 ;
218 | output wr04 ;
219 | output wr05 ;
220 | output wr06 ;
221 | output wr07 ;
222 | output wr08 ;
223 | output wr09 ;
224 | output wr10 ;
225 | output wr11 ;
226 | output wr12 ;
227 | output wr13 ;
228 | output wr14 ;
229 | output wr15 ;
230 | output wr16 ;
231 | output wr17 ;
232 | output wr18 ;
233 | output wr19 ;
234 | output wr20 ;
235 | output wr21 ;
236 | output wr22 ;
237 | output wr23 ;
238 | output wr24 ;
239 | output wr25 ;
240 | output wr26 ;
241 | output wr27 ;
242 | output wr28 ;
243 | output wr29 ;
244 | output wr30 ;
245 | output wr31 ;
246 | output wr32 ;
247 | output wr33 ;
248 | output wr34 ;
249 | output wr35 ;
250 | output [A_WID+1:0] rd_addr ;
251 | output [A_WID+1:0] wr_addr ;
252 | output wr0 ;
253 | output [35:0] out_sel ;
254 | output out_en ;
255 |
256 | wire [A_WID-1:0] rd_addr00 ;
257 | wire [A_WID-1:0] rd_addr01 ;
258 | wire [A_WID-1:0] rd_addr02 ;
259 | wire [A_WID-1:0] rd_addr03 ;
260 | wire [A_WID-1:0] rd_addr04 ;
261 | wire [A_WID-1:0] rd_addr05 ;
262 | wire [A_WID-1:0] rd_addr06 ;
263 | wire [A_WID-1:0] rd_addr07 ;
264 | wire [A_WID-1:0] rd_addr08 ;
265 | wire [A_WID-1:0] rd_addr09 ;
266 | wire [A_WID-1:0] rd_addr10 ;
267 | wire [A_WID-1:0] rd_addr11 ;
268 | wire [A_WID-1:0] rd_addr12 ;
269 | wire [A_WID-1:0] rd_addr13 ;
270 | wire [A_WID-1:0] rd_addr14 ;
271 | wire [A_WID-1:0] rd_addr15 ;
272 | wire [A_WID-1:0] rd_addr16 ;
273 | wire [A_WID-1:0] rd_addr17 ;
274 | wire [A_WID-1:0] rd_addr18 ;
275 | wire [A_WID-1:0] rd_addr19 ;
276 | wire [A_WID-1:0] rd_addr20 ;
277 | wire [A_WID-1:0] rd_addr21 ;
278 | wire [A_WID-1:0] rd_addr22 ;
279 | wire [A_WID-1:0] rd_addr23 ;
280 | wire [A_WID-1:0] rd_addr24 ;
281 | wire [A_WID-1:0] rd_addr25 ;
282 | wire [A_WID-1:0] rd_addr26 ;
283 | wire [A_WID-1:0] rd_addr27 ;
284 | wire [A_WID-1:0] rd_addr28 ;
285 | wire [A_WID-1:0] rd_addr29 ;
286 | wire [A_WID-1:0] rd_addr30 ;
287 | wire [A_WID-1:0] rd_addr31 ;
288 | wire [A_WID-1:0] rd_addr32 ;
289 | wire [A_WID-1:0] rd_addr33 ;
290 | wire [A_WID-1:0] rd_addr34 ;
291 | wire [A_WID-1:0] rd_addr35 ;
292 | wire wr00 ;
293 | wire wr01 ;
294 | wire wr02 ;
295 | wire wr03 ;
296 | wire wr04 ;
297 | wire wr05 ;
298 | wire wr06 ;
299 | wire wr07 ;
300 | wire wr08 ;
301 | wire wr09 ;
302 | wire wr10 ;
303 | wire wr11 ;
304 | wire wr12 ;
305 | wire wr13 ;
306 | wire wr14 ;
307 | wire wr15 ;
308 | wire wr16 ;
309 | wire wr17 ;
310 | wire wr18 ;
311 | wire wr19 ;
312 | wire wr20 ;
313 | wire wr21 ;
314 | wire wr22 ;
315 | wire wr23 ;
316 | wire wr24 ;
317 | wire wr25 ;
318 | wire wr26 ;
319 | wire wr27 ;
320 | wire wr28 ;
321 | wire wr29 ;
322 | wire wr30 ;
323 | wire wr31 ;
324 | wire wr32 ;
325 | wire wr33 ;
326 | wire wr34 ;
327 | wire wr35 ;
328 | wire [A_WID-1:0] wr_addr00 ;
329 | wire [A_WID-1:0] wr_addr01 ;
330 | wire [A_WID-1:0] wr_addr02 ;
331 | wire [A_WID-1:0] wr_addr03 ;
332 | wire [A_WID-1:0] wr_addr04 ;
333 | wire [A_WID-1:0] wr_addr05 ;
334 | wire [A_WID-1:0] wr_addr06 ;
335 | wire [A_WID-1:0] wr_addr07 ;
336 | wire [A_WID-1:0] wr_addr08 ;
337 | wire [A_WID-1:0] wr_addr09 ;
338 | wire [A_WID-1:0] wr_addr10 ;
339 | wire [A_WID-1:0] wr_addr11 ;
340 | wire [A_WID-1:0] wr_addr12 ;
341 | wire [A_WID-1:0] wr_addr13 ;
342 | wire [A_WID-1:0] wr_addr14 ;
343 | wire [A_WID-1:0] wr_addr15 ;
344 | wire [A_WID-1:0] wr_addr16 ;
345 | wire [A_WID-1:0] wr_addr17 ;
346 | wire [A_WID-1:0] wr_addr18 ;
347 | wire [A_WID-1:0] wr_addr19 ;
348 | wire [A_WID-1:0] wr_addr20 ;
349 | wire [A_WID-1:0] wr_addr21 ;
350 | wire [A_WID-1:0] wr_addr22 ;
351 | wire [A_WID-1:0] wr_addr23 ;
352 | wire [A_WID-1:0] wr_addr24 ;
353 | wire [A_WID-1:0] wr_addr25 ;
354 | wire [A_WID-1:0] wr_addr26 ;
355 | wire [A_WID-1:0] wr_addr27 ;
356 | wire [A_WID-1:0] wr_addr28 ;
357 | wire [A_WID-1:0] wr_addr29 ;
358 | wire [A_WID-1:0] wr_addr30 ;
359 | wire [A_WID-1:0] wr_addr31 ;
360 | wire [A_WID-1:0] wr_addr32 ;
361 | wire [A_WID-1:0] wr_addr33 ;
362 | wire [A_WID-1:0] wr_addr34 ;
363 | wire [A_WID-1:0] wr_addr35 ;
364 | wire [3*A_WID-1:0] offset00 ;
365 | wire [3*A_WID-1:0] offset01 ;
366 | wire [3*A_WID-1:0] offset02 ;
367 | wire [3*A_WID-1:0] offset03 ;
368 | wire [3*A_WID-1:0] offset04 ;
369 | wire [3*A_WID-1:0] offset05 ;
370 | wire [3*A_WID-1:0] offset06 ;
371 | wire [3*A_WID-1:0] offset07 ;
372 | wire [3*A_WID-1:0] offset08 ;
373 | wire [3*A_WID-1:0] offset09 ;
374 | wire [3*A_WID-1:0] offset10 ;
375 | wire [3*A_WID-1:0] offset11 ;
376 | wire [3*A_WID-1:0] offset12 ;
377 | wire [3*A_WID-1:0] offset13 ;
378 | wire [3*A_WID-1:0] offset14 ;
379 | wire [3*A_WID-1:0] offset15 ;
380 | wire [3*A_WID-1:0] offset16 ;
381 | wire [3*A_WID-1:0] offset17 ;
382 | wire [3*A_WID-1:0] offset18 ;
383 | wire [3*A_WID-1:0] offset19 ;
384 | wire [3*A_WID-1:0] offset20 ;
385 | wire [3*A_WID-1:0] offset21 ;
386 | wire [3*A_WID-1:0] offset22 ;
387 | wire [3*A_WID-1:0] offset23 ;
388 | wire [3*A_WID-1:0] offset24 ;
389 | wire [3*A_WID-1:0] offset25 ;
390 | wire [3*A_WID-1:0] offset26 ;
391 | wire [3*A_WID-1:0] offset27 ;
392 | wire [3*A_WID-1:0] offset28 ;
393 | wire [3*A_WID-1:0] offset29 ;
394 | wire [3*A_WID-1:0] offset30 ;
395 | wire [3*A_WID-1:0] offset31 ;
396 | wire [3*A_WID-1:0] offset32 ;
397 | wire [3*A_WID-1:0] offset33 ;
398 | wire [3*A_WID-1:0] offset34 ;
399 | wire [3*A_WID-1:0] offset35 ;
400 | wire [A_WID-1:0] out_addr ;
401 | wire [35:0] out_rd_sel ;
402 | wire out_rd_en ;
403 |
404 | reg [A_WID-1:0] rd_counter ;
405 | reg [A_WID-1:0] wr_counter ;
406 | reg [A_WID+1:0] rd_addr ;
407 | reg [A_WID+1:0] wr_addr ;
408 | reg [35:0] out_sel ;
409 | reg out_en ;
410 |
411 | wire wr0 ;
412 | wire rd_en ;
413 |
414 | assign rd_en = fsm[2] & (cycle[3:2] != 2'h0);
415 | assign wr_en = fsm[2] & (cycle[1:0] != 2'h0);
416 | assign offset00 = {8'd0,8'd0,8'd0};
417 | assign offset01 = {8'd0,8'd0,8'd0};
418 | assign offset02 = {8'd0,8'd0,8'd0};
419 | assign offset03 = {8'd0,8'd0,8'd0};
420 | assign offset04 = {8'd0,8'd0,8'd0};
421 | assign offset05 = {8'd0,8'd0,8'd0};
422 | assign offset06 = {8'd0,8'd0,8'd0};
423 | assign offset07 = {8'd0,8'd0,8'd0};
424 | assign offset08 = {8'd0,8'd255,8'd0};
425 | assign offset09 = {8'd0,8'd129,8'd65};
426 | assign offset10 = {8'd0,8'd224,8'd240};
427 | assign offset11 = {8'd0,8'd216,8'd236};
428 | assign offset12 = {8'd0,8'd157,8'd250};
429 | assign offset13 = {8'd0,8'd132,8'd242};
430 | assign offset14 = {8'd0,8'd184,8'd247};
431 | assign offset15 = {8'd0,8'd254,8'd240};
432 | assign offset16 = {8'd0,8'd115,8'd242};
433 | assign offset17 = {8'd0,8'd209,8'd164};
434 | assign offset18 = {8'd0,8'd255,8'd248};
435 | assign offset19 = {8'd0,8'd246,8'd58};
436 | assign offset20 = {8'd0,8'd253,8'd215};
437 | assign offset21 = {8'd0,8'd252,8'd209};
438 | assign offset22 = {8'd0,8'd146,8'd249};
439 | assign offset23 = {8'd0,8'd231,8'd250};
440 | assign offset24 = {8'd254,8'd200,8'd0};
441 | assign offset25 = {8'd0,8'd85,8'd235};
442 | assign offset26 = {8'd0,8'd229,8'd69};
443 | assign offset27 = {8'd0,8'd203,8'd254};
444 | assign offset28 = {8'd0,8'd131,8'd251};
445 | assign offset29 = {8'd0,8'd115,8'd254};
446 | assign offset30 = {8'd0,8'd253,8'd255};
447 | assign offset31 = {8'd0,8'd248,8'd254};
448 | assign offset32 = {8'd0,8'd255,8'd243};
449 | assign offset33 = {8'd0,8'd239,8'd253};
450 | assign offset34 = {8'd0,8'd248,8'd215};
451 | assign offset35 = {8'd0,8'd252,8'd164};
452 |
453 | always @ (posedge clk or negedge reset_n)
454 | begin : rd_counter_r
455 | if(!reset_n)
456 | rd_counter <= #1 8'h0;
457 | else if(fsm[2]) begin
458 | if ( rd_lq )
459 | rd_counter <= #1 rd_counter + 8'd37;
460 | else
461 | rd_counter <= #1 rd_counter;
462 | end
463 | // else if(out_rd_en)
464 | // rd_counter <= #1 out_addr;
465 | else
466 | rd_counter <= #1 8'h0;
467 | end
468 |
469 | always @ (posedge clk or negedge reset_n)
470 | begin : out_sel_r
471 | if(!reset_n)
472 | out_sel <= #1 36'h0;
473 | else
474 | out_sel <= #1 out_rd_sel;
475 | end
476 |
477 | always @ (posedge clk or negedge reset_n)
478 | begin : out_en_r
479 | if(!reset_n)
480 | out_en <= #1 1'b0;
481 | else
482 | out_en <= #1 out_rd_en;
483 | end
484 |
485 | always @ (posedge clk or negedge reset_n)
486 | begin : wr_counter_r
487 | if(!reset_n)
488 | wr_counter <= #1 8'h0;
489 | else if(fsm[2]) begin
490 | if ( wr_lq )
491 | wr_counter <= #1 wr_counter + 8'd37;
492 | else
493 | wr_counter <= #1 wr_counter;
494 | end
495 | else
496 | wr_counter <= #1 8'h0;
497 | end
498 |
499 | always @ (posedge clk or negedge reset_n)
500 | begin : wr_addr_r
501 | if(!reset_n)
502 | wr_addr <= #1 10'h0;
503 | else if(wr_lr) begin
504 | if( wr_addr == 'd767)
505 | wr_addr <= #1 10'h0;
506 | else
507 | wr_addr <= #1 wr_addr + 1'b1;
508 | end
509 | end
510 |
511 | assign wr0 = wr_lr;
512 |
513 | always @ (posedge clk or negedge reset_n)
514 | begin : rd_addr_r
515 | if(!reset_n)
516 | rd_addr <= #1 10'h0;
517 | else if(rd_lr) begin
518 | if(rd_addr == 'd767)
519 | rd_addr <= #1 10'h0;
520 | else
521 | rd_addr <= #1 rd_addr + 1'b1;
522 | end
523 | end
524 |
525 | rd_cell rd_cell00(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset00),.out_addr(out_addr),.out_en(out_rd_sel[ 0]),.rd_addr(rd_addr00));
526 | rd_cell rd_cell01(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset01),.out_addr(out_addr),.out_en(out_rd_sel[ 1]),.rd_addr(rd_addr01));
527 | rd_cell rd_cell02(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset02),.out_addr(out_addr),.out_en(out_rd_sel[ 2]),.rd_addr(rd_addr02));
528 | rd_cell rd_cell03(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset03),.out_addr(out_addr),.out_en(out_rd_sel[ 3]),.rd_addr(rd_addr03));
529 | rd_cell rd_cell04(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset04),.out_addr(out_addr),.out_en(out_rd_sel[ 4]),.rd_addr(rd_addr04));
530 | rd_cell rd_cell05(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset05),.out_addr(out_addr),.out_en(out_rd_sel[ 5]),.rd_addr(rd_addr05));
531 | rd_cell rd_cell06(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset06),.out_addr(out_addr),.out_en(out_rd_sel[ 6]),.rd_addr(rd_addr06));
532 | rd_cell rd_cell07(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset07),.out_addr(out_addr),.out_en(out_rd_sel[ 7]),.rd_addr(rd_addr07));
533 | rd_cell rd_cell08(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset08),.out_addr(out_addr),.out_en(out_rd_sel[ 8]),.rd_addr(rd_addr08));
534 | rd_cell rd_cell09(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset09),.out_addr(out_addr),.out_en(out_rd_sel[ 9]),.rd_addr(rd_addr09));
535 | rd_cell rd_cell10(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset10),.out_addr(out_addr),.out_en(out_rd_sel[10]),.rd_addr(rd_addr10));
536 | rd_cell rd_cell11(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset11),.out_addr(out_addr),.out_en(out_rd_sel[11]),.rd_addr(rd_addr11));
537 | rd_cell rd_cell12(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset12),.out_addr(out_addr),.out_en(out_rd_sel[12]),.rd_addr(rd_addr12));
538 | rd_cell rd_cell13(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset13),.out_addr(out_addr),.out_en(out_rd_sel[13]),.rd_addr(rd_addr13));
539 | rd_cell rd_cell14(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset14),.out_addr(out_addr),.out_en(out_rd_sel[14]),.rd_addr(rd_addr14));
540 | rd_cell rd_cell15(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset15),.out_addr(out_addr),.out_en(out_rd_sel[15]),.rd_addr(rd_addr15));
541 | rd_cell rd_cell16(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset16),.out_addr(out_addr),.out_en(out_rd_sel[16]),.rd_addr(rd_addr16));
542 | rd_cell rd_cell17(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset17),.out_addr(out_addr),.out_en(out_rd_sel[17]),.rd_addr(rd_addr17));
543 | rd_cell rd_cell18(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset18),.out_addr(out_addr),.out_en(out_rd_sel[18]),.rd_addr(rd_addr18));
544 | rd_cell rd_cell19(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset19),.out_addr(out_addr),.out_en(out_rd_sel[19]),.rd_addr(rd_addr19));
545 | rd_cell rd_cell20(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset20),.out_addr(out_addr),.out_en(out_rd_sel[20]),.rd_addr(rd_addr20));
546 | rd_cell rd_cell21(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset21),.out_addr(out_addr),.out_en(out_rd_sel[21]),.rd_addr(rd_addr21));
547 | rd_cell rd_cell22(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset22),.out_addr(out_addr),.out_en(out_rd_sel[22]),.rd_addr(rd_addr22));
548 | rd_cell rd_cell23(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset23),.out_addr(out_addr),.out_en(out_rd_sel[23]),.rd_addr(rd_addr23));
549 | rd_cell rd_cell24(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset24),.out_addr(out_addr),.out_en(out_rd_sel[24]),.rd_addr(rd_addr24));
550 | rd_cell rd_cell25(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset25),.out_addr(out_addr),.out_en(out_rd_sel[25]),.rd_addr(rd_addr25));
551 | rd_cell rd_cell26(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset26),.out_addr(out_addr),.out_en(out_rd_sel[26]),.rd_addr(rd_addr26));
552 | rd_cell rd_cell27(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset27),.out_addr(out_addr),.out_en(out_rd_sel[27]),.rd_addr(rd_addr27));
553 | rd_cell rd_cell28(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset28),.out_addr(out_addr),.out_en(out_rd_sel[28]),.rd_addr(rd_addr28));
554 | rd_cell rd_cell29(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset29),.out_addr(out_addr),.out_en(out_rd_sel[29]),.rd_addr(rd_addr29));
555 | rd_cell rd_cell30(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset30),.out_addr(out_addr),.out_en(out_rd_sel[30]),.rd_addr(rd_addr30));
556 | rd_cell rd_cell31(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset31),.out_addr(out_addr),.out_en(out_rd_sel[31]),.rd_addr(rd_addr31));
557 | rd_cell rd_cell32(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset32),.out_addr(out_addr),.out_en(out_rd_sel[32]),.rd_addr(rd_addr32));
558 | rd_cell rd_cell33(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset33),.out_addr(out_addr),.out_en(out_rd_sel[33]),.rd_addr(rd_addr33));
559 | rd_cell rd_cell34(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset34),.out_addr(out_addr),.out_en(out_rd_sel[34]),.rd_addr(rd_addr34));
560 | rd_cell rd_cell35(.clk(clk),.reset_n(reset_n),.rd_en(rd_en),.cycle(cycle[3:2]),.base_addr(rd_counter),.addr_offset(offset35),.out_addr(out_addr),.out_en(out_rd_sel[35]),.rd_addr(rd_addr35));
561 |
562 | wr_cell wr_cell00(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 0]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset00),.wr_addr(wr_addr00),.ram_wr(wr00));
563 | wr_cell wr_cell01(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 1]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset01),.wr_addr(wr_addr01),.ram_wr(wr01));
564 | wr_cell wr_cell02(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 2]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset02),.wr_addr(wr_addr02),.ram_wr(wr02));
565 | wr_cell wr_cell03(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 3]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset03),.wr_addr(wr_addr03),.ram_wr(wr03));
566 | wr_cell wr_cell04(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 4]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset04),.wr_addr(wr_addr04),.ram_wr(wr04));
567 | wr_cell wr_cell05(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 5]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset05),.wr_addr(wr_addr05),.ram_wr(wr05));
568 | wr_cell wr_cell06(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 6]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset06),.wr_addr(wr_addr06),.ram_wr(wr06));
569 | wr_cell wr_cell07(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 7]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset07),.wr_addr(wr_addr07),.ram_wr(wr07));
570 | wr_cell wr_cell08(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 8]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset08),.wr_addr(wr_addr08),.ram_wr(wr08));
571 | wr_cell wr_cell09(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[ 9]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset09),.wr_addr(wr_addr09),.ram_wr(wr09));
572 | wr_cell wr_cell10(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[10]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset10),.wr_addr(wr_addr10),.ram_wr(wr10));
573 | wr_cell wr_cell11(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[11]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset11),.wr_addr(wr_addr11),.ram_wr(wr11));
574 | wr_cell wr_cell12(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[12]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset12),.wr_addr(wr_addr12),.ram_wr(wr12));
575 | wr_cell wr_cell13(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[13]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset13),.wr_addr(wr_addr13),.ram_wr(wr13));
576 | wr_cell wr_cell14(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[14]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset14),.wr_addr(wr_addr14),.ram_wr(wr14));
577 | wr_cell wr_cell15(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[15]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset15),.wr_addr(wr_addr15),.ram_wr(wr15));
578 | wr_cell wr_cell16(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[16]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset16),.wr_addr(wr_addr16),.ram_wr(wr16));
579 | wr_cell wr_cell17(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[17]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset17),.wr_addr(wr_addr17),.ram_wr(wr17));
580 | wr_cell wr_cell18(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[18]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset18),.wr_addr(wr_addr18),.ram_wr(wr18));
581 | wr_cell wr_cell19(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[19]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset19),.wr_addr(wr_addr19),.ram_wr(wr19));
582 | wr_cell wr_cell20(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[20]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset20),.wr_addr(wr_addr20),.ram_wr(wr20));
583 | wr_cell wr_cell21(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[21]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset21),.wr_addr(wr_addr21),.ram_wr(wr21));
584 | wr_cell wr_cell22(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[22]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset22),.wr_addr(wr_addr22),.ram_wr(wr22));
585 | wr_cell wr_cell23(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[23]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset23),.wr_addr(wr_addr23),.ram_wr(wr23));
586 | wr_cell wr_cell24(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[24]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset24),.wr_addr(wr_addr24),.ram_wr(wr24));
587 | wr_cell wr_cell25(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[25]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset25),.wr_addr(wr_addr25),.ram_wr(wr25));
588 | wr_cell wr_cell26(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[26]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset26),.wr_addr(wr_addr26),.ram_wr(wr26));
589 | wr_cell wr_cell27(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[27]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset27),.wr_addr(wr_addr27),.ram_wr(wr27));
590 | wr_cell wr_cell28(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[28]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset28),.wr_addr(wr_addr28),.ram_wr(wr28));
591 | wr_cell wr_cell29(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[29]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset29),.wr_addr(wr_addr29),.ram_wr(wr29));
592 | wr_cell wr_cell30(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[30]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset30),.wr_addr(wr_addr30),.ram_wr(wr30));
593 | wr_cell wr_cell31(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[31]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset31),.wr_addr(wr_addr31),.ram_wr(wr31));
594 | wr_cell wr_cell32(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[32]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset32),.wr_addr(wr_addr32),.ram_wr(wr32));
595 | wr_cell wr_cell33(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[33]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset33),.wr_addr(wr_addr33),.ram_wr(wr33));
596 | wr_cell wr_cell34(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[34]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset34),.wr_addr(wr_addr34),.ram_wr(wr34));
597 | wr_cell wr_cell35(.clk(clk),.reset_n(reset_n),.wr_en(wr_en),.sin(sync_in[35]),.fsm(fsm),.cycle(cycle[1:0]),.base_addr(wr_counter),.addr_offset(offset35),.wr_addr(wr_addr35),.ram_wr(wr35));
598 |
599 | rd_seq rd_seq(.clk(clk),.reset_n(reset_n),.rate(rate),.fsm(fsm),.out_addr(out_addr),.out_rd_en(out_rd_en),.out_rd_sel(out_rd_sel));
600 |
601 | endmodule
602 |
--------------------------------------------------------------------------------
/ldpc_rtl/comp_cell.v:
--------------------------------------------------------------------------------
1 | module comp_cell(
2 | clk,
3 | reset_n,
4 | iter_0,
5 | lq6_in,
6 | lr_in,
7 | cnu_in,
8 | lq6_out,
9 | lr_out
10 | );
11 |
12 | //Parameter
13 | parameter D_WID = 8;
14 |
15 | //Input ports
16 | input clk ;
17 | input reset_n ;
18 | input iter_0 ;
19 | input [6*D_WID-1:0] lq6_in ;
20 | input [2*D_WID+9:0] lr_in ;
21 | input [6:0] cnu_in ;
22 |
23 | //Output ports
24 | output [6*D_WID-1:0] lq6_out ;
25 | output [2*D_WID+9:0] lr_out ;
26 |
27 | reg [D_WID-1:0] lq0 ;
28 | reg [D_WID-1:0] lq1 ;
29 | reg [D_WID-1:0] lq2 ;
30 | reg [D_WID-1:0] lq3 ;
31 | reg [D_WID-1:0] lq4 ;
32 | reg [D_WID-1:0] lq5 ;
33 | reg [D_WID-1:0] lq0_dly ;
34 | reg [D_WID-1:0] lq1_dly ;
35 | reg [D_WID-1:0] lq2_dly ;
36 | reg [D_WID-1:0] lq3_dly ;
37 | reg [D_WID-1:0] lq4_dly ;
38 | reg [D_WID-1:0] lq5_dly ;
39 | reg sign_xor ;
40 | reg [D_WID-1:0] abs_less_lq ;
41 | reg [D_WID-1:0] abs_least_lq;
42 | reg [2:0] least_loc ;
43 | reg [2*D_WID+9:0] compress_lr;
44 |
45 | wire in_dly ;
46 | wire in_dly2 ;
47 | wire in_dly3 ;
48 | wire in_dly4 ;
49 | wire in_dly5 ;
50 | wire [D_WID-1:0] lq0_diff ;
51 | wire [D_WID-1:0] lq1_diff ;
52 | wire [D_WID-1:0] lq2_diff ;
53 | wire [D_WID-1:0] lq3_diff ;
54 | wire [D_WID-1:0] lq4_diff ;
55 | wire [D_WID-1:0] lq5_diff ;
56 | wire [D_WID-1:0] lq0_sum ;
57 | wire [D_WID-1:0] lq1_sum ;
58 | wire [D_WID-1:0] lq2_sum ;
59 | wire [D_WID-1:0] lq3_sum ;
60 | wire [D_WID-1:0] lq4_sum ;
61 | wire [D_WID-1:0] lq5_sum ;
62 | wire [D_WID-1:0] new_lr0 ;
63 | wire [D_WID-1:0] new_lr1 ;
64 | wire [D_WID-1:0] new_lr2 ;
65 | wire [D_WID-1:0] new_lr3 ;
66 | wire [D_WID-1:0] new_lr4 ;
67 | wire [D_WID-1:0] new_lr5 ;
68 | wire [D_WID-1:0] abs_lq0 ;
69 | wire [D_WID-1:0] abs_lq1 ;
70 | wire [D_WID-1:0] abs_lq2 ;
71 | wire [D_WID-1:0] abs_lq3 ;
72 | wire [D_WID-1:0] abs_lq4 ;
73 | wire [D_WID-1:0] abs_lq5 ;
74 | wire com0_1 ;
75 | wire com2_3 ;
76 | wire com4_5 ;
77 | wire [D_WID-1:0] less01 ;
78 | wire [D_WID-1:0] less23 ;
79 | wire [D_WID-1:0] less45 ;
80 | wire [D_WID-1:0] more01 ;
81 | wire [D_WID-1:0] more23 ;
82 | wire [D_WID-1:0] more45 ;
83 | wire [2:0] ind_less01 ;
84 | wire [2:0] ind_less23 ;
85 | wire [2:0] ind_less45 ;
86 | wire [2:0] ind_more01 ;
87 | wire [2:0] ind_more23 ;
88 | wire [2:0] ind_more45 ;
89 | wire com01_23 ;
90 | wire [D_WID-1:0] more0123 ;
91 | wire [D_WID-1:0] least0123 ;
92 | wire [2:0] ind_least0123 ;
93 | wire com01_0123 ;
94 | wire com23_0123 ;
95 | wire [D_WID-1:0] less0123 ;
96 | wire [2:0] ind_less0123 ;
97 | wire com0123_45 ;
98 | wire [D_WID-1:0] least012345 ;
99 | wire [D_WID-1:0] more012345 ;
100 | wire [2:0] ind_least012345 ;
101 | wire com0123_012345 ;
102 | wire com45_012345 ;
103 | wire [D_WID-1:0] less012345 ;
104 | wire [2:0] ind_less012345 ;
105 | wire [D_WID:0] less_lq_w ;
106 | wire [D_WID:0] least_lq_w ;
107 | wire [D_WID-1:0] inv_less_lq;
108 | wire [D_WID-1:0] inv_least_lq;
109 | wire sign_xor_w ;
110 | wire [D_WID-1:0] lr0 ;
111 | wire [D_WID-1:0] lr1 ;
112 | wire [D_WID-1:0] lr2 ;
113 | wire [D_WID-1:0] lr3 ;
114 | wire [D_WID-1:0] lr4 ;
115 | wire [D_WID-1:0] lr5 ;
116 | wire [D_WID-1:0] inv_less_lr;
117 | wire [D_WID-1:0] inv_least_lr;
118 | wire [D_WID-1:0] abs_less_lr;
119 | wire [D_WID-1:0] abs_least_lr;
120 | wire lr0_sign ;
121 | wire lr1_sign ;
122 | wire lr2_sign ;
123 | wire lr3_sign ;
124 | wire lr4_sign ;
125 | wire lr5_sign ;
126 | wire sign_lr ;
127 | wire [2:0] lr_least_loc;
128 |
129 | assign lq6_out = {lq0_dly,lq1_dly,lq2_dly,lq3_dly,lq4_dly,lq5_dly};
130 | assign lr_out = {abs_least_lq, abs_less_lq, least_loc, sign_xor, lq0_dly[D_WID-1], lq1_dly[D_WID-1], lq2_dly[D_WID-1], lq3_dly[D_WID-1], lq4_dly[D_WID-1], lq5_dly[D_WID-1]};
131 |
132 | assign lq0_diff = iter_0 ? lq0 : (lq0 - lr0);
133 | assign lq1_diff = iter_0 ? lq1 : (lq1 - lr1);
134 | assign lq2_diff = iter_0 ? lq2 : (lq2 - lr2);
135 | assign lq3_diff = iter_0 ? lq3 : (lq3 - lr3);
136 | assign lq4_diff = iter_0 ? lq4 : (lq4 - lr4);
137 | assign lq5_diff = iter_0 ? lq5 : (lq5 - lr5);
138 |
139 | assign {abs_least_lr, abs_less_lr, lr_least_loc, sign_lr, lr0_sign, lr1_sign, lr2_sign, lr3_sign, lr4_sign, lr5_sign} = compress_lr;
140 | assign inv_less_lr = ~abs_less_lr + 1'b1;
141 | assign inv_least_lr = ~abs_least_lr + 1'b1;
142 | assign lr0 = (lr_least_loc==3'h0) ? ((lr0_sign ^ sign_lr)? inv_less_lr : abs_less_lr ) : ((lr0_sign ^ sign_lr)? inv_least_lr : abs_least_lr );
143 | assign lr1 = (lr_least_loc==3'h1) ? ((lr1_sign ^ sign_lr)? inv_less_lr : abs_less_lr ) : ((lr1_sign ^ sign_lr)? inv_least_lr : abs_least_lr );
144 | assign lr2 = (lr_least_loc==3'h2) ? ((lr2_sign ^ sign_lr)? inv_less_lr : abs_less_lr ) : ((lr2_sign ^ sign_lr)? inv_least_lr : abs_least_lr );
145 | assign lr3 = (lr_least_loc==3'h3) ? ((lr3_sign ^ sign_lr)? inv_less_lr : abs_less_lr ) : ((lr3_sign ^ sign_lr)? inv_least_lr : abs_least_lr );
146 | assign lr4 = (lr_least_loc==3'h4) ? ((lr4_sign ^ sign_lr)? inv_less_lr : abs_less_lr ) : ((lr4_sign ^ sign_lr)? inv_least_lr : abs_least_lr );
147 | assign lr5 = (lr_least_loc==3'h5) ? ((lr5_sign ^ sign_lr)? inv_less_lr : abs_less_lr ) : ((lr5_sign ^ sign_lr)? inv_least_lr : abs_least_lr );
148 |
149 |
150 | assign in_dly = cnu_in[2] ;
151 | assign in_dly2 = cnu_in[3] ;
152 | assign in_dly3 = cnu_in[4] ;
153 | assign in_dly4 = cnu_in[5] ;
154 | assign in_dly5 = cnu_in[6] ;
155 |
156 | always @ (posedge clk or negedge reset_n)
157 | begin : lr_r
158 | if(!reset_n)
159 | compress_lr <= #1 {(2*D_WID+10){1'b0}};
160 | else if(cnu_in[1])
161 | compress_lr <= #1 lr_in;
162 | end
163 |
164 | always @ (posedge clk or negedge reset_n)
165 | begin : lq_r
166 | if(!reset_n) begin
167 | lq0 <= #1 {D_WID{1'b0}};
168 | lq1 <= #1 {D_WID{1'b0}};
169 | lq2 <= #1 {D_WID{1'b0}};
170 | lq3 <= #1 {D_WID{1'b0}};
171 | lq4 <= #1 {D_WID{1'b0}};
172 | lq5 <= #1 {D_WID{1'b0}};
173 | end
174 | else if(cnu_in[1]) begin
175 | lq0 <= #1 lq6_in[6*D_WID-1:5*D_WID];
176 | lq1 <= #1 lq6_in[5*D_WID-1:4*D_WID];
177 | lq2 <= #1 lq6_in[4*D_WID-1:3*D_WID];
178 | lq3 <= #1 lq6_in[3*D_WID-1:2*D_WID];
179 | lq4 <= #1 lq6_in[2*D_WID-1: D_WID];
180 | lq5 <= #1 lq6_in[ D_WID-1:0];
181 | end
182 | else if(in_dly) begin
183 | lq0 <= #1 lq0_diff;
184 | lq1 <= #1 lq1_diff;
185 | lq2 <= #1 lq2_diff;
186 | lq3 <= #1 lq3_diff;
187 | lq4 <= #1 lq4_diff;
188 | lq5 <= #1 lq5_diff;
189 | end
190 | // else if(in_dly2) begin
191 | //
192 | // end
193 | else ;
194 | end
195 |
196 | // Lrij Sign (Lq) and Minimum Value
197 | // Sign bit
198 | assign sign_xor_w = lq0[D_WID-1] ^ lq1[D_WID-1] ^ lq2[D_WID-1] ^ lq3[D_WID-1] ^ lq4[D_WID-1] ^ lq5[D_WID-1];
199 |
200 | // Absolute value
201 | assign abs_lq0 = lq0[D_WID-1] ? (~lq0 + 1'b1) : lq0;
202 | assign abs_lq1 = lq1[D_WID-1] ? (~lq1 + 1'b1) : lq1;
203 | assign abs_lq2 = lq2[D_WID-1] ? (~lq2 + 1'b1) : lq2;
204 | assign abs_lq3 = lq3[D_WID-1] ? (~lq3 + 1'b1) : lq3;
205 | assign abs_lq4 = lq4[D_WID-1] ? (~lq4 + 1'b1) : lq4;
206 | assign abs_lq5 = lq5[D_WID-1] ? (~lq5 + 1'b1) : lq5;
207 |
208 | // L1,L2 finder current leave 2 cycles for L1,L2 finder
209 | // Compare 2 group
210 | assign com0_1 = abs_lq0 > abs_lq1;
211 | assign com2_3 = abs_lq2 > abs_lq3;
212 | assign com4_5 = abs_lq4 > abs_lq5;
213 |
214 | // Keep more, less, index value
215 | assign less01 = com0_1 ? abs_lq1 : abs_lq0 ;
216 | assign less23 = com2_3 ? abs_lq3 : abs_lq2 ;
217 | assign less45 = com4_5 ? abs_lq5 : abs_lq4 ;
218 | assign more01 = com0_1 ? abs_lq0 : abs_lq1 ;
219 | assign more23 = com2_3 ? abs_lq2 : abs_lq3 ;
220 | assign more45 = com4_5 ? abs_lq4 : abs_lq5 ;
221 | assign ind_less01 = com0_1 ? 3'h1 : 3'h0 ;
222 | assign ind_less23 = com2_3 ? 3'h3 : 3'h2 ;
223 | assign ind_less45 = com4_5 ? 3'h5 : 3'h4 ;
224 | assign ind_more01 = com0_1 ? 3'h0 : 3'h1 ;
225 | assign ind_more23 = com2_3 ? 3'h2 : 3'h3 ;
226 | assign ind_more45 = com4_5 ? 3'h4 : 3'h5 ;
227 |
228 | // 01 vs 23 comparsion
229 | assign com01_23 = less01 > less23;
230 | assign more0123 = com01_23 ? less01 : less23;
231 | assign least0123 = com01_23 ? less23 : less01;
232 | assign ind_least0123 = com01_23 ? ind_less23 : ind_less01 ;
233 |
234 | assign com01_0123 = less01 > more23;
235 | assign com23_0123 = less23 > more01;
236 | assign less0123 = com01_23 ? (com01_0123 ? more23 : less01) : (com23_0123 ? more01 : less23);
237 | assign ind_less0123 = com23_0123 ? (com01_0123 ? ind_more23 : ind_less01 ) : (com23_0123 ? ind_more01 : ind_less23 );
238 |
239 | // 0123 vs 45 comparsion
240 | assign com0123_45 = least0123 > less45 ;
241 | assign least012345 = com0123_45 ? less45 : least0123;
242 | assign more012345 = com0123_45 ? least0123 : less45;
243 | assign ind_least012345 = com0123_45 ? ind_less45 : ind_least0123;
244 |
245 | assign com0123_012345 = least0123 > more45;
246 | assign com45_012345 = less45 > less0123;
247 | assign less012345 = com0123_45 ? ( com0123_012345 ? more45 : least0123 ) : ( com45_012345 ? less0123 : less45 );
248 | assign ind_less012345 = com0123_45 ? ( com0123_012345 ? ind_more45 : ind_least0123) : (com45_012345 ? ind_less0123 : ind_less45 );
249 |
250 | // compress lr information
251 | assign less_lq_w = {1'b0, abs_less_lq[D_WID-2:0]} + {3'b0, abs_less_lq[D_WID-4:2]} + 1'b1;
252 | assign least_lq_w = {1'b0,abs_least_lq[D_WID-2:0]} + {3'b0,abs_least_lq[D_WID-4:2]} + 1'b1;
253 |
254 | always @ (posedge clk or negedge reset_n)
255 | begin : lq_less_r
256 | if(!reset_n) begin
257 | abs_less_lq <= #1 {D_WID{1'b0}};
258 | abs_least_lq <= #1 {D_WID{1'b0}};
259 | least_loc <= #1 3'h0;
260 | sign_xor <= #1 1'b0;
261 | end
262 | else if(in_dly2) begin
263 | abs_less_lq <= #1 less012345;
264 | abs_least_lq <= #1 least012345;
265 | least_loc <= #1 ind_least012345;
266 | sign_xor <= #1 sign_xor_w;
267 | end
268 | else if(in_dly3) begin
269 | abs_less_lq <= #1 less_lq_w[D_WID:1];
270 | abs_least_lq <= #1 least_lq_w[D_WID:1];
271 | end
272 | end
273 |
274 | assign inv_less_lq = ~abs_less_lq + 1'b1;
275 | assign inv_least_lq = ~abs_least_lq + 1'b1;
276 |
277 | assign new_lr0 = (least_loc==3'h0) ? ((lq0_dly[D_WID-1]^sign_xor) ? inv_less_lq : abs_less_lq ) : ((lq0_dly[D_WID-1]^sign_xor) ? inv_least_lq : abs_least_lq );
278 | assign new_lr1 = (least_loc==3'h1) ? ((lq1_dly[D_WID-1]^sign_xor) ? inv_less_lq : abs_less_lq ) : ((lq1_dly[D_WID-1]^sign_xor) ? inv_least_lq : abs_least_lq );
279 | assign new_lr2 = (least_loc==3'h2) ? ((lq2_dly[D_WID-1]^sign_xor) ? inv_less_lq : abs_less_lq ) : ((lq2_dly[D_WID-1]^sign_xor) ? inv_least_lq : abs_least_lq );
280 | assign new_lr3 = (least_loc==3'h3) ? ((lq3_dly[D_WID-1]^sign_xor) ? inv_less_lq : abs_less_lq ) : ((lq3_dly[D_WID-1]^sign_xor) ? inv_least_lq : abs_least_lq );
281 | assign new_lr4 = (least_loc==3'h4) ? ((lq4_dly[D_WID-1]^sign_xor) ? inv_less_lq : abs_less_lq ) : ((lq4_dly[D_WID-1]^sign_xor) ? inv_least_lq : abs_least_lq );
282 | assign new_lr5 = (least_loc==3'h5) ? ((lq5_dly[D_WID-1]^sign_xor) ? inv_less_lq : abs_less_lq ) : ((lq5_dly[D_WID-1]^sign_xor) ? inv_least_lq : abs_least_lq );
283 | assign lq0_sum = lq0_dly + new_lr0;
284 | assign lq1_sum = lq1_dly + new_lr1;
285 | assign lq2_sum = lq2_dly + new_lr2;
286 | assign lq3_sum = lq3_dly + new_lr3;
287 | assign lq4_sum = lq4_dly + new_lr4;
288 | assign lq5_sum = lq5_dly + new_lr5;
289 |
290 | always @ (posedge clk or negedge reset_n)
291 | begin : lq_dly_r
292 | if(!reset_n) begin
293 | lq0_dly <= #1 {D_WID{1'b0}};
294 | lq1_dly <= #1 {D_WID{1'b0}};
295 | lq2_dly <= #1 {D_WID{1'b0}};
296 | lq3_dly <= #1 {D_WID{1'b0}};
297 | lq4_dly <= #1 {D_WID{1'b0}};
298 | lq5_dly <= #1 {D_WID{1'b0}};
299 | end
300 | else if(in_dly3) begin
301 | lq0_dly <= #1 lq0;
302 | lq1_dly <= #1 lq1;
303 | lq2_dly <= #1 lq2;
304 | lq3_dly <= #1 lq3;
305 | lq4_dly <= #1 lq4;
306 | lq5_dly <= #1 lq5;
307 | end
308 | else if(in_dly4) begin
309 | lq0_dly <= #1 lq0_sum;
310 | lq1_dly <= #1 lq1_sum;
311 | lq2_dly <= #1 lq2_sum;
312 | lq3_dly <= #1 lq3_sum;
313 | lq4_dly <= #1 lq4_sum;
314 | lq5_dly <= #1 lq5_sum;
315 | end
316 | end
317 |
318 |
319 | endmodule
320 |
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/ldpc_rtl/data/G.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/data/G.mat
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/ldpc_rtl/data/G34.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/data/G34.mat
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/ldpc_rtl/data/col_order.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/data/col_order.mat
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/ldpc_rtl/data/col_order34.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/data/col_order34.mat
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/ldpc_rtl/data/readme.md:
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1 |
2 |
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/ldpc_rtl/data/readme.txt:
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1 | B.mat mean A * Hp + B * Hs = 0;
2 | col_order mean Column Order
3 | H1.mat mean H1 =
4 | HN.mat mean HN = P * B
5 | H.mat mean Generate Check Matrix
6 | HG.mat mean Hp = G * Hs
7 | L1.mat mean L1 = L ^ -1
8 | U1.mat mean U1 = U ^ -1
9 | L.mat mean L * U * Hp = P * B * Hs
10 | U.mat mean L * U * Hp = P * B * Hs
11 | P.mat mean L * U * Hp = P * B * Hs
12 |
13 |
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/ldpc_rtl/data/symbol.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/data/symbol.mat
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/ldpc_rtl/data/symbol1.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/data/symbol1.mat
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/ldpc_rtl/data_cell.v:
--------------------------------------------------------------------------------
1 | module data_cell(
2 | clk,
3 | reset_n,
4 | fsm,
5 | sin,
6 | din,
7 | vtc_en,
8 | dvtc_a,
9 | dvtc_b,
10 | dvtc_c,
11 |
12 | ram_d
13 | );
14 |
15 | parameter D_WID = 8;
16 |
17 | input clk ;
18 | input reset_n ;
19 | input [D_WID-1:0] din ; // LLR input
20 | input sin ;
21 | input [3:0] fsm ;
22 | input [2:0] vtc_en ;
23 | input [D_WID-1:0] dvtc_a ;
24 | input [D_WID-1:0] dvtc_b ;
25 | input [D_WID-1:0] dvtc_c ;
26 |
27 | output [D_WID-1:0] ram_d ;
28 | reg [D_WID-1:0] ram_d ;
29 |
30 | always @ (posedge clk or negedge reset_n)
31 | begin : ram_d_r
32 | if(!reset_n)
33 | ram_d <= #1 {D_WID{1'b0}};
34 | else if(fsm[1] & sin)
35 | ram_d <= #1 din;
36 | else if(fsm[2]) begin
37 | if(vtc_en[0])
38 | ram_d <= #1 dvtc_a;
39 | if(vtc_en[1])
40 | ram_d <= #1 dvtc_b;
41 | if(vtc_en[2])
42 | ram_d <= #1 dvtc_c;
43 | end
44 | end
45 |
46 | endmodule
47 |
--------------------------------------------------------------------------------
/ldpc_rtl/data_cell1.v:
--------------------------------------------------------------------------------
1 | module data_cell1(
2 | clk,
3 | reset_n,
4 | fsm,
5 | sin,
6 | din,
7 | vtc_en,
8 | dvtc_a,
9 | dvtc_b,
10 | dvtc_c,
11 | d_last,
12 |
13 | ram_d
14 | );
15 |
16 | parameter D_WID = 8;
17 |
18 | input clk ;
19 | input reset_n ;
20 | input [D_WID-1:0] din ; // LLR input
21 | input sin ;
22 | input [3:0] fsm ;
23 | input [2:0] vtc_en ;
24 | input [D_WID-1:0] dvtc_a ;
25 | input [D_WID-1:0] dvtc_b ;
26 | input [D_WID-1:0] dvtc_c ;
27 | input [D_WID-1:0] d_last ;
28 |
29 | output [D_WID-1:0] ram_d ;
30 | reg [D_WID-1:0] ram_d ;
31 |
32 | wire [D_WID-1:0] temp1 ;
33 | //wire [D_WID-1:0] temp2 ;
34 | wire [D_WID-1:0] temp3 ;
35 |
36 | assign temp1 = dvtc_a - d_last ;
37 | //assign temp2 = dvtc_b - d_last ;
38 | assign temp3 = dvtc_c + temp1 ;
39 |
40 | always @ (posedge clk or negedge reset_n)
41 | begin : ram_d_r
42 | if(!reset_n)
43 | ram_d <= #1 {D_WID{1'b0}};
44 | else if(fsm[1] & sin)
45 | ram_d <= #1 din;
46 | else if(fsm[2]) begin
47 | // if(vtc_en[0])
48 | // ram_d <= #1 dvtc_a;
49 | if(vtc_en[1])
50 | ram_d <= #1 dvtc_b;
51 | if(vtc_en[2])
52 | ram_d <= #1 temp3;
53 | end
54 | end
55 |
56 | endmodule
57 |
--------------------------------------------------------------------------------
/ldpc_rtl/data_cell2.v:
--------------------------------------------------------------------------------
1 | module data_cell2(
2 | clk,
3 | reset_n,
4 | fsm,
5 | sin,
6 | din,
7 | vtc_en,
8 | dvtc_a,
9 | dvtc_b,
10 | dvtc_c,
11 | d_last,
12 |
13 | ram_d
14 | );
15 |
16 | parameter D_WID = 8;
17 |
18 | input clk ;
19 | input reset_n ;
20 | input [D_WID-1:0] din ; // LLR input
21 | input sin ;
22 | input [3:0] fsm ;
23 | input [2:0] vtc_en ;
24 | input [D_WID-1:0] dvtc_a ;
25 | input [D_WID-1:0] dvtc_b ;
26 | input [D_WID-1:0] dvtc_c ;
27 | input [D_WID-1:0] d_last ;
28 |
29 | output [D_WID-1:0] ram_d ;
30 | reg [D_WID-1:0] ram_d ;
31 |
32 | wire [D_WID-1:0] temp1 ;
33 | wire [D_WID-1:0] temp2 ;
34 | wire [D_WID-1:0] temp3 ;
35 |
36 | assign temp1 = dvtc_a - d_last ;
37 | assign temp2 = dvtc_b - d_last ;
38 | assign temp3 = dvtc_c + temp1 + temp2;
39 |
40 | always @ (posedge clk or negedge reset_n)
41 | begin : ram_d_r
42 | if(!reset_n)
43 | ram_d <= #1 {D_WID{1'b0}};
44 | else if(fsm[1] & sin)
45 | ram_d <= #1 din;
46 | else if(fsm[2]) begin
47 | // if(vtc_en[0])
48 | // ram_d <= #1 dvtc_a;
49 | // if(vtc_en[1])
50 | // ram_d <= #1 dvtc_b;
51 | if(vtc_en[0])
52 | ram_d <= #1 temp3;
53 | end
54 | end
55 |
56 | endmodule
--------------------------------------------------------------------------------
/ldpc_rtl/debug.v:
--------------------------------------------------------------------------------
1 | `ifdef DEBUG
2 | integer file;
3 | integer file1,file2;
4 |
5 | initial
6 | begin
7 | file = $fopen("../debussy/lq.csv");
8 | file1 = $fopen("./hpu.dat");
9 | file2 = $fopen("./vpu.dat");
10 | DEBUG;
11 | end
12 |
13 | task DEBUG;
14 | integer k;
15 | begin
16 | #100000
17 | wait(u_ldpc_dec.u_ram00.ADDRB == 8'hf5) begin
18 | $display("OK,%dns",$time);
19 | for(k=0;k<256;k=k+1) begin
20 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram00 .mem[k]));
21 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram01 .mem[k]));
22 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram02 .mem[k]));
23 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram03 .mem[k]));
24 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram04 .mem[k]));
25 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram05 .mem[k]));
26 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram06 .mem[k]));
27 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram07 .mem[k]));
28 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram08 .mem[k]));
29 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram09 .mem[k]));
30 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram10 .mem[k]));
31 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram11 .mem[k]));
32 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram12 .mem[k]));
33 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram13 .mem[k]));
34 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram14 .mem[k]));
35 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram15 .mem[k]));
36 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram16 .mem[k]));
37 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram17 .mem[k]));
38 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram18 .mem[k]));
39 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram19 .mem[k]));
40 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram20 .mem[k]));
41 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram21 .mem[k]));
42 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram22 .mem[k]));
43 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram23 .mem[k]));
44 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram24 .mem[k]));
45 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram25 .mem[k]));
46 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram26 .mem[k]));
47 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram27 .mem[k]));
48 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram28 .mem[k]));
49 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram29 .mem[k]));
50 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram30 .mem[k]));
51 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram31 .mem[k]));
52 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram32 .mem[k]));
53 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram33 .mem[k]));
54 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram34 .mem[k]));
55 | $fdisplay(file,"%d",$signed(u_ldpc_dec.u_ram35 .mem[k]));
56 | end
57 | #90000 $finish;
58 | end
59 | end
60 | endtask
61 |
62 |
63 | always @ (posedge clk)
64 | if (u_ldpc_dec.u_data_comp.cnu_in[2] == 1'b1) begin
65 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp0.lq0),$signed(u_ldpc_dec.u_data_comp.comp0.lq1),$signed(u_ldpc_dec.u_data_comp.comp0.lq2),$signed(u_ldpc_dec.u_data_comp.comp0.lq3),$signed(u_ldpc_dec.u_data_comp.comp0.lq4),$signed(u_ldpc_dec.u_data_comp.comp0.lq5));
66 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp1.lq0),$signed(u_ldpc_dec.u_data_comp.comp1.lq1),$signed(u_ldpc_dec.u_data_comp.comp1.lq2),$signed(u_ldpc_dec.u_data_comp.comp1.lq3),$signed(u_ldpc_dec.u_data_comp.comp1.lq4),$signed(u_ldpc_dec.u_data_comp.comp1.lq5));
67 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp2.lq0),$signed(u_ldpc_dec.u_data_comp.comp2.lq1),$signed(u_ldpc_dec.u_data_comp.comp2.lq2),$signed(u_ldpc_dec.u_data_comp.comp2.lq3),$signed(u_ldpc_dec.u_data_comp.comp2.lq4),$signed(u_ldpc_dec.u_data_comp.comp2.lq5));
68 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp3.lq0),$signed(u_ldpc_dec.u_data_comp.comp3.lq1),$signed(u_ldpc_dec.u_data_comp.comp3.lq2),$signed(u_ldpc_dec.u_data_comp.comp3.lq3),$signed(u_ldpc_dec.u_data_comp.comp3.lq4),$signed(u_ldpc_dec.u_data_comp.comp3.lq5));
69 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp4.lq0),$signed(u_ldpc_dec.u_data_comp.comp4.lq1),$signed(u_ldpc_dec.u_data_comp.comp4.lq2),$signed(u_ldpc_dec.u_data_comp.comp4.lq3),$signed(u_ldpc_dec.u_data_comp.comp4.lq4),$signed(u_ldpc_dec.u_data_comp.comp4.lq5));
70 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp5.lq0),$signed(u_ldpc_dec.u_data_comp.comp5.lq1),$signed(u_ldpc_dec.u_data_comp.comp5.lq2),$signed(u_ldpc_dec.u_data_comp.comp5.lq3),$signed(u_ldpc_dec.u_data_comp.comp5.lq4),$signed(u_ldpc_dec.u_data_comp.comp5.lq5));
71 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp6.lq0),$signed(u_ldpc_dec.u_data_comp.comp6.lq1),$signed(u_ldpc_dec.u_data_comp.comp6.lq2),$signed(u_ldpc_dec.u_data_comp.comp6.lq3),$signed(u_ldpc_dec.u_data_comp.comp6.lq4),$signed(u_ldpc_dec.u_data_comp.comp6.lq5));
72 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp7.lq0),$signed(u_ldpc_dec.u_data_comp.comp7.lq1),$signed(u_ldpc_dec.u_data_comp.comp7.lq2),$signed(u_ldpc_dec.u_data_comp.comp7.lq3),$signed(u_ldpc_dec.u_data_comp.comp7.lq4),$signed(u_ldpc_dec.u_data_comp.comp7.lq5));
73 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp8.lq0),$signed(u_ldpc_dec.u_data_comp.comp8.lq1),$signed(u_ldpc_dec.u_data_comp.comp8.lq2),$signed(u_ldpc_dec.u_data_comp.comp8.lq3),$signed(u_ldpc_dec.u_data_comp.comp8.lq4),$signed(u_ldpc_dec.u_data_comp.comp8.lq5));
74 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp9.lq0),$signed(u_ldpc_dec.u_data_comp.comp9.lq1),$signed(u_ldpc_dec.u_data_comp.comp9.lq2),$signed(u_ldpc_dec.u_data_comp.comp9.lq3),$signed(u_ldpc_dec.u_data_comp.comp9.lq4),$signed(u_ldpc_dec.u_data_comp.comp9.lq5));
75 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compa.lq0),$signed(u_ldpc_dec.u_data_comp.compa.lq1),$signed(u_ldpc_dec.u_data_comp.compa.lq2),$signed(u_ldpc_dec.u_data_comp.compa.lq3),$signed(u_ldpc_dec.u_data_comp.compa.lq4),$signed(u_ldpc_dec.u_data_comp.compa.lq5));
76 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compb.lq0),$signed(u_ldpc_dec.u_data_comp.compb.lq1),$signed(u_ldpc_dec.u_data_comp.compb.lq2),$signed(u_ldpc_dec.u_data_comp.compb.lq3),$signed(u_ldpc_dec.u_data_comp.compb.lq4),$signed(u_ldpc_dec.u_data_comp.compb.lq5));
77 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compc.lq0),$signed(u_ldpc_dec.u_data_comp.compc.lq1),$signed(u_ldpc_dec.u_data_comp.compc.lq2),$signed(u_ldpc_dec.u_data_comp.compc.lq3),$signed(u_ldpc_dec.u_data_comp.compc.lq4),$signed(u_ldpc_dec.u_data_comp.compc.lq5));
78 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compd.lq0),$signed(u_ldpc_dec.u_data_comp.compd.lq1),$signed(u_ldpc_dec.u_data_comp.compd.lq2),$signed(u_ldpc_dec.u_data_comp.compd.lq3),$signed(u_ldpc_dec.u_data_comp.compd.lq4),$signed(u_ldpc_dec.u_data_comp.compd.lq5));
79 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compe.lq0),$signed(u_ldpc_dec.u_data_comp.compe.lq1),$signed(u_ldpc_dec.u_data_comp.compe.lq2),$signed(u_ldpc_dec.u_data_comp.compe.lq3),$signed(u_ldpc_dec.u_data_comp.compe.lq4),$signed(u_ldpc_dec.u_data_comp.compe.lq5));
80 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compf.lq0),$signed(u_ldpc_dec.u_data_comp.compf.lq1),$signed(u_ldpc_dec.u_data_comp.compf.lq2),$signed(u_ldpc_dec.u_data_comp.compf.lq3),$signed(u_ldpc_dec.u_data_comp.compf.lq4),$signed(u_ldpc_dec.u_data_comp.compf.lq5));
81 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compg.lq0),$signed(u_ldpc_dec.u_data_comp.compg.lq1),$signed(u_ldpc_dec.u_data_comp.compg.lq2),$signed(u_ldpc_dec.u_data_comp.compg.lq3),$signed(u_ldpc_dec.u_data_comp.compg.lq4),$signed(u_ldpc_dec.u_data_comp.compg.lq5));
82 | $fdisplay(file1,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comph.lq0),$signed(u_ldpc_dec.u_data_comp.comph.lq1),$signed(u_ldpc_dec.u_data_comp.comph.lq2),$signed(u_ldpc_dec.u_data_comp.comph.lq3),$signed(u_ldpc_dec.u_data_comp.comph.lq4),$signed(u_ldpc_dec.u_data_comp.comph.lq5));
83 | end
84 |
85 | always @ (posedge clk)
86 | if (u_ldpc_dec.u_data_comp.cnu_in[6] == 1'b1) begin
87 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp0.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp0.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp0.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp0.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp0.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp0.lq5_dly));
88 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp1.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp1.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp1.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp1.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp1.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp1.lq5_dly));
89 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp2.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp2.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp2.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp2.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp2.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp2.lq5_dly));
90 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp3.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp3.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp3.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp3.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp3.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp3.lq5_dly));
91 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp4.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp4.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp4.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp4.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp4.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp4.lq5_dly));
92 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp5.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp5.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp5.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp5.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp5.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp5.lq5_dly));
93 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp6.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp6.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp6.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp6.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp6.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp6.lq5_dly));
94 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp7.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp7.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp7.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp7.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp7.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp7.lq5_dly));
95 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp8.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp8.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp8.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp8.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp8.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp8.lq5_dly));
96 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comp9.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comp9.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comp9.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comp9.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comp9.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comp9.lq5_dly));
97 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compa.lq0_dly),$signed(u_ldpc_dec.u_data_comp.compa.lq1_dly),$signed(u_ldpc_dec.u_data_comp.compa.lq2_dly),$signed(u_ldpc_dec.u_data_comp.compa.lq3_dly),$signed(u_ldpc_dec.u_data_comp.compa.lq4_dly),$signed(u_ldpc_dec.u_data_comp.compa.lq5_dly));
98 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compb.lq0_dly),$signed(u_ldpc_dec.u_data_comp.compb.lq1_dly),$signed(u_ldpc_dec.u_data_comp.compb.lq2_dly),$signed(u_ldpc_dec.u_data_comp.compb.lq3_dly),$signed(u_ldpc_dec.u_data_comp.compb.lq4_dly),$signed(u_ldpc_dec.u_data_comp.compb.lq5_dly));
99 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compc.lq0_dly),$signed(u_ldpc_dec.u_data_comp.compc.lq1_dly),$signed(u_ldpc_dec.u_data_comp.compc.lq2_dly),$signed(u_ldpc_dec.u_data_comp.compc.lq3_dly),$signed(u_ldpc_dec.u_data_comp.compc.lq4_dly),$signed(u_ldpc_dec.u_data_comp.compc.lq5_dly));
100 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compd.lq0_dly),$signed(u_ldpc_dec.u_data_comp.compd.lq1_dly),$signed(u_ldpc_dec.u_data_comp.compd.lq2_dly),$signed(u_ldpc_dec.u_data_comp.compd.lq3_dly),$signed(u_ldpc_dec.u_data_comp.compd.lq4_dly),$signed(u_ldpc_dec.u_data_comp.compd.lq5_dly));
101 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compe.lq0_dly),$signed(u_ldpc_dec.u_data_comp.compe.lq1_dly),$signed(u_ldpc_dec.u_data_comp.compe.lq2_dly),$signed(u_ldpc_dec.u_data_comp.compe.lq3_dly),$signed(u_ldpc_dec.u_data_comp.compe.lq4_dly),$signed(u_ldpc_dec.u_data_comp.compe.lq5_dly));
102 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compf.lq0_dly),$signed(u_ldpc_dec.u_data_comp.compf.lq1_dly),$signed(u_ldpc_dec.u_data_comp.compf.lq2_dly),$signed(u_ldpc_dec.u_data_comp.compf.lq3_dly),$signed(u_ldpc_dec.u_data_comp.compf.lq4_dly),$signed(u_ldpc_dec.u_data_comp.compf.lq5_dly));
103 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.compg.lq0_dly),$signed(u_ldpc_dec.u_data_comp.compg.lq1_dly),$signed(u_ldpc_dec.u_data_comp.compg.lq2_dly),$signed(u_ldpc_dec.u_data_comp.compg.lq3_dly),$signed(u_ldpc_dec.u_data_comp.compg.lq4_dly),$signed(u_ldpc_dec.u_data_comp.compg.lq5_dly));
104 | $fdisplay(file2,"%d, %d, %d, %d, %d ,%d,",$signed(u_ldpc_dec.u_data_comp.comph.lq0_dly),$signed(u_ldpc_dec.u_data_comp.comph.lq1_dly),$signed(u_ldpc_dec.u_data_comp.comph.lq2_dly),$signed(u_ldpc_dec.u_data_comp.comph.lq3_dly),$signed(u_ldpc_dec.u_data_comp.comph.lq4_dly),$signed(u_ldpc_dec.u_data_comp.comph.lq5_dly));
105 | end
106 |
107 | `endif
108 |
--------------------------------------------------------------------------------
/ldpc_rtl/fig/qpsk12.fig:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/fig/qpsk12.fig
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/ldpc_rtl/fig/readme.md:
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1 |
2 |
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/ldpc_rtl/ldpc.v:
--------------------------------------------------------------------------------
1 | module ldpc(clk,reset_n,data_in,sync_in,rate,max_iter,data_out,sync_out,busy,num_iter);
2 |
3 |
4 | parameter D_WID = 8;
5 | parameter A_WID = 8;
6 |
7 | input clk ;
8 | input reset_n ;
9 | input rate ; // 0, 1/2 1, 3/4
10 | input [D_WID-3:0] data_in ; // LLR input
11 | input sync_in ;
12 | input [4:0] max_iter ;
13 |
14 | //Output ports
15 | output data_out ;
16 | output sync_out ;
17 | output busy ; // ldpc is running
18 | //output finish ; // ldpc decoder finish, can read new data
19 | output [4:0] num_iter ; // iteration number
20 |
21 | //Internal Register and Wire definition
22 |
23 | wire [A_WID-1:0] wr_addr00 ;
24 | wire [A_WID-1:0] wr_addr01 ;
25 | wire [A_WID-1:0] wr_addr02 ;
26 | wire [A_WID-1:0] wr_addr03 ;
27 | wire [A_WID-1:0] wr_addr04 ;
28 | wire [A_WID-1:0] wr_addr05 ;
29 | wire [A_WID-1:0] wr_addr06 ;
30 | wire [A_WID-1:0] wr_addr07 ;
31 | wire [A_WID-1:0] wr_addr08 ;
32 | wire [A_WID-1:0] wr_addr09 ;
33 | wire [A_WID-1:0] wr_addr10 ;
34 | wire [A_WID-1:0] wr_addr11 ;
35 | wire [A_WID-1:0] wr_addr12 ;
36 | wire [A_WID-1:0] wr_addr13 ;
37 | wire [A_WID-1:0] wr_addr14 ;
38 | wire [A_WID-1:0] wr_addr15 ;
39 | wire [A_WID-1:0] wr_addr16 ;
40 | wire [A_WID-1:0] wr_addr17 ;
41 | wire [A_WID-1:0] wr_addr18 ;
42 | wire [A_WID-1:0] wr_addr19 ;
43 | wire [A_WID-1:0] wr_addr20 ;
44 | wire [A_WID-1:0] wr_addr21 ;
45 | wire [A_WID-1:0] wr_addr22 ;
46 | wire [A_WID-1:0] wr_addr23 ;
47 | wire [A_WID-1:0] wr_addr24 ;
48 | wire [A_WID-1:0] wr_addr25 ;
49 | wire [A_WID-1:0] wr_addr26 ;
50 | wire [A_WID-1:0] wr_addr27 ;
51 | wire [A_WID-1:0] wr_addr28 ;
52 | wire [A_WID-1:0] wr_addr29 ;
53 | wire [A_WID-1:0] wr_addr30 ;
54 | wire [A_WID-1:0] wr_addr31 ;
55 | wire [A_WID-1:0] wr_addr32 ;
56 | wire [A_WID-1:0] wr_addr33 ;
57 | wire [A_WID-1:0] wr_addr34 ;
58 | wire [A_WID-1:0] wr_addr35 ;
59 | wire [A_WID-1:0] rd_addr00 ;
60 | wire [A_WID-1:0] rd_addr01 ;
61 | wire [A_WID-1:0] rd_addr02 ;
62 | wire [A_WID-1:0] rd_addr03 ;
63 | wire [A_WID-1:0] rd_addr04 ;
64 | wire [A_WID-1:0] rd_addr05 ;
65 | wire [A_WID-1:0] rd_addr06 ;
66 | wire [A_WID-1:0] rd_addr07 ;
67 | wire [A_WID-1:0] rd_addr08 ;
68 | wire [A_WID-1:0] rd_addr09 ;
69 | wire [A_WID-1:0] rd_addr10 ;
70 | wire [A_WID-1:0] rd_addr11 ;
71 | wire [A_WID-1:0] rd_addr12 ;
72 | wire [A_WID-1:0] rd_addr13 ;
73 | wire [A_WID-1:0] rd_addr14 ;
74 | wire [A_WID-1:0] rd_addr15 ;
75 | wire [A_WID-1:0] rd_addr16 ;
76 | wire [A_WID-1:0] rd_addr17 ;
77 | wire [A_WID-1:0] rd_addr18 ;
78 | wire [A_WID-1:0] rd_addr19 ;
79 | wire [A_WID-1:0] rd_addr20 ;
80 | wire [A_WID-1:0] rd_addr21 ;
81 | wire [A_WID-1:0] rd_addr22 ;
82 | wire [A_WID-1:0] rd_addr23 ;
83 | wire [A_WID-1:0] rd_addr24 ;
84 | wire [A_WID-1:0] rd_addr25 ;
85 | wire [A_WID-1:0] rd_addr26 ;
86 | wire [A_WID-1:0] rd_addr27 ;
87 | wire [A_WID-1:0] rd_addr28 ;
88 | wire [A_WID-1:0] rd_addr29 ;
89 | wire [A_WID-1:0] rd_addr30 ;
90 | wire [A_WID-1:0] rd_addr31 ;
91 | wire [A_WID-1:0] rd_addr32 ;
92 | wire [A_WID-1:0] rd_addr33 ;
93 | wire [A_WID-1:0] rd_addr34 ;
94 | wire [A_WID-1:0] rd_addr35 ;
95 | wire wr00 ;
96 | wire wr01 ;
97 | wire wr02 ;
98 | wire wr03 ;
99 | wire wr04 ;
100 | wire wr05 ;
101 | wire wr06 ;
102 | wire wr07 ;
103 | wire wr08 ;
104 | wire wr09 ;
105 | wire wr10 ;
106 | wire wr11 ;
107 | wire wr12 ;
108 | wire wr13 ;
109 | wire wr14 ;
110 | wire wr15 ;
111 | wire wr16 ;
112 | wire wr17 ;
113 | wire wr18 ;
114 | wire wr19 ;
115 | wire wr20 ;
116 | wire wr21 ;
117 | wire wr22 ;
118 | wire wr23 ;
119 | wire wr24 ;
120 | wire wr25 ;
121 | wire wr26 ;
122 | wire wr27 ;
123 | wire wr28 ;
124 | wire wr29 ;
125 | wire wr30 ;
126 | wire wr31 ;
127 | wire wr32 ;
128 | wire wr33 ;
129 | wire wr34 ;
130 | wire wr35 ;
131 | wire [D_WID-1:0] din00 ;
132 | wire [D_WID-1:0] din01 ;
133 | wire [D_WID-1:0] din02 ;
134 | wire [D_WID-1:0] din03 ;
135 | wire [D_WID-1:0] din04 ;
136 | wire [D_WID-1:0] din05 ;
137 | wire [D_WID-1:0] din06 ;
138 | wire [D_WID-1:0] din07 ;
139 | wire [D_WID-1:0] din08 ;
140 | wire [D_WID-1:0] din09 ;
141 | wire [D_WID-1:0] din10 ;
142 | wire [D_WID-1:0] din11 ;
143 | wire [D_WID-1:0] din12 ;
144 | wire [D_WID-1:0] din13 ;
145 | wire [D_WID-1:0] din14 ;
146 | wire [D_WID-1:0] din15 ;
147 | wire [D_WID-1:0] din16 ;
148 | wire [D_WID-1:0] din17 ;
149 | wire [D_WID-1:0] din18 ;
150 | wire [D_WID-1:0] din19 ;
151 | wire [D_WID-1:0] din20 ;
152 | wire [D_WID-1:0] din21 ;
153 | wire [D_WID-1:0] din22 ;
154 | wire [D_WID-1:0] din23 ;
155 | wire [D_WID-1:0] din24 ;
156 | wire [D_WID-1:0] din25 ;
157 | wire [D_WID-1:0] din26 ;
158 | wire [D_WID-1:0] din27 ;
159 | wire [D_WID-1:0] din28 ;
160 | wire [D_WID-1:0] din29 ;
161 | wire [D_WID-1:0] din30 ;
162 | wire [D_WID-1:0] din31 ;
163 | wire [D_WID-1:0] din32 ;
164 | wire [D_WID-1:0] din33 ;
165 | wire [D_WID-1:0] din34 ;
166 | wire [D_WID-1:0] din35 ;
167 | wire [D_WID-1:0] dout00 ;
168 | wire [D_WID-1:0] dout01 ;
169 | wire [D_WID-1:0] dout02 ;
170 | wire [D_WID-1:0] dout03 ;
171 | wire [D_WID-1:0] dout04 ;
172 | wire [D_WID-1:0] dout05 ;
173 | wire [D_WID-1:0] dout06 ;
174 | wire [D_WID-1:0] dout07 ;
175 | wire [D_WID-1:0] dout08 ;
176 | wire [D_WID-1:0] dout09 ;
177 | wire [D_WID-1:0] dout10 ;
178 | wire [D_WID-1:0] dout11 ;
179 | wire [D_WID-1:0] dout12 ;
180 | wire [D_WID-1:0] dout13 ;
181 | wire [D_WID-1:0] dout14 ;
182 | wire [D_WID-1:0] dout15 ;
183 | wire [D_WID-1:0] dout16 ;
184 | wire [D_WID-1:0] dout17 ;
185 | wire [D_WID-1:0] dout18 ;
186 | wire [D_WID-1:0] dout19 ;
187 | wire [D_WID-1:0] dout20 ;
188 | wire [D_WID-1:0] dout21 ;
189 | wire [D_WID-1:0] dout22 ;
190 | wire [D_WID-1:0] dout23 ;
191 | wire [D_WID-1:0] dout24 ;
192 | wire [D_WID-1:0] dout25 ;
193 | wire [D_WID-1:0] dout26 ;
194 | wire [D_WID-1:0] dout27 ;
195 | wire [D_WID-1:0] dout28 ;
196 | wire [D_WID-1:0] dout29 ;
197 | wire [D_WID-1:0] dout30 ;
198 | wire [D_WID-1:0] dout31 ;
199 | wire [D_WID-1:0] dout32 ;
200 | wire [D_WID-1:0] dout33 ;
201 | wire [D_WID-1:0] dout34 ;
202 | wire [D_WID-1:0] dout35 ;
203 | //wire [D_WID-1:0] dctv00 ;
204 | //wire [D_WID-1:0] dctv01 ;
205 | //wire [D_WID-1:0] dctv02 ;
206 | //wire [D_WID-1:0] dctv03 ;
207 | //wire [D_WID-1:0] dctv04 ;
208 | //wire [D_WID-1:0] dctv05 ;
209 | //wire [D_WID-1:0] dctv06 ;
210 | //wire [D_WID-1:0] dctv07 ;
211 | //wire [D_WID-1:0] dctv08 ;
212 | //wire [D_WID-1:0] dctv09 ;
213 | //wire [D_WID-1:0] dctv10 ;
214 | //wire [D_WID-1:0] dctv11 ;
215 | //wire [D_WID-1:0] dctv12 ;
216 | //wire [D_WID-1:0] dctv13 ;
217 | //wire [D_WID-1:0] dctv14 ;
218 | //wire [D_WID-1:0] dctv15 ;
219 | //wire [D_WID-1:0] dctv16 ;
220 | //wire [D_WID-1:0] dctv17 ;
221 | //wire [D_WID-1:0] dctv18 ;
222 | //wire [D_WID-1:0] dctv19 ;
223 | //wire [D_WID-1:0] dctv20 ;
224 | //wire [D_WID-1:0] dctv21 ;
225 | //wire [D_WID-1:0] dctv22 ;
226 | //wire [D_WID-1:0] dctv23 ;
227 | //wire [D_WID-1:0] dctv24 ;
228 | //wire [D_WID-1:0] dctv25 ;
229 | //wire [D_WID-1:0] dctv26 ;
230 | //wire [D_WID-1:0] dctv27 ;
231 | //wire [D_WID-1:0] dctv28 ;
232 | //wire [D_WID-1:0] dctv29 ;
233 | //wire [D_WID-1:0] dctv30 ;
234 | //wire [D_WID-1:0] dctv31 ;
235 | //wire [D_WID-1:0] dctv32 ;
236 | //wire [D_WID-1:0] dctv33 ;
237 | //wire [D_WID-1:0] dctv34 ;
238 | //wire [D_WID-1:0] dctv35 ;
239 | wire [A_WID+1:0] rd_addr ;
240 | wire [A_WID+1:0] wr_addr ;
241 | wire wr0 ;
242 | wire [3:0] cycle ;
243 | wire ctv_out ;
244 | wire [4*D_WID+19:0] mem0_in ;
245 | wire [4*D_WID+19:0] mem1_in ;
246 | wire [4*D_WID+19:0] mem2_in ;
247 | wire [4*D_WID+19:0] mem0_out ;
248 | wire [4*D_WID+19:0] mem1_out ;
249 | wire [4*D_WID+19:0] mem2_out ;
250 | wire sigma_vnu ;
251 | wire [35:0] out_sel ;
252 | wire out_en ;
253 |
254 | reg [35:0] sync_dly ;
255 | reg [D_WID-1:0] data_dly ;
256 | reg [5:0] sync_count ;
257 | reg data_out ;
258 | reg sync_out ;
259 | reg dec_out ;
260 | reg [35:0] out_sel_dly;
261 | reg out_en_dly ;
262 |
263 | wire [3:0] fsm ;
264 | wire sync_in6 ;
265 |
266 | assign sync_in6 = (sync_count == 6'h0) & sync_in;
267 |
268 | always @ (posedge clk or negedge reset_n)
269 | begin : sync_count_r
270 | if(!reset_n)
271 | sync_count <= #1 6'h0;
272 | else if(sync_in)
273 | begin if(sync_count == 6'd35)
274 | sync_count <= #1 6'h0;
275 | else
276 | sync_count <= #1 sync_count + 1'b1;
277 | end
278 | end
279 |
280 | always @ (posedge clk or negedge reset_n)
281 | begin : sync_dly_r
282 | if(!reset_n)
283 | sync_dly <= #1 36'h0;
284 | else if(sync_in)
285 | sync_dly <= #1 { sync_dly[34:0],sync_in6 };
286 | else
287 | sync_dly <= #1 36'h0;
288 | end
289 |
290 | always @ (posedge clk or negedge reset_n)
291 | begin : data_dly_r
292 | if(!reset_n)
293 | data_dly <= #1 {D_WID{1'b0}};
294 | else
295 | data_dly <= #1 {{2{data_in[D_WID-3]}},data_in};
296 | end
297 |
298 | always @ (posedge clk or negedge reset_n)
299 | begin : out_sel_d
300 | if(!reset_n)
301 | out_sel_dly <= #1 36'h0;
302 | else
303 | out_sel_dly <= #1 out_sel;
304 | end
305 |
306 | always @ (posedge clk or negedge reset_n)
307 | begin : out_en_d
308 | if(!reset_n)
309 | out_en_dly <= #1 1'b0;
310 | else
311 | out_en_dly <= #1 out_en;
312 | end
313 |
314 | always @ (posedge clk or negedge reset_n)
315 | begin : sync_r
316 | if(!reset_n)
317 | sync_out <= #1 1'b0;
318 | else
319 | sync_out <= #1 out_en_dly;
320 | end
321 |
322 | always @ (posedge clk or negedge reset_n)
323 | begin : data_r
324 | if(!reset_n)
325 | data_out <= #1 1'b0;
326 | else if(out_en_dly)
327 | data_out <= #1 dec_out;
328 | end
329 |
330 | always @ (*)
331 | case(out_sel_dly)
332 | 36'h0_0000_0001: dec_out = dout00[D_WID-1];
333 | 36'h0_0000_0002: dec_out = dout01[D_WID-1];
334 | 36'h0_0000_0004: dec_out = dout02[D_WID-1];
335 | 36'h0_0000_0008: dec_out = dout03[D_WID-1];
336 | 36'h0_0000_0010: dec_out = dout04[D_WID-1];
337 | 36'h0_0000_0020: dec_out = dout05[D_WID-1];
338 | 36'h0_0000_0040: dec_out = dout06[D_WID-1];
339 | 36'h0_0000_0080: dec_out = dout07[D_WID-1];
340 | 36'h0_0000_0100: dec_out = dout08[D_WID-1];
341 | 36'h0_0000_0200: dec_out = dout09[D_WID-1];
342 | 36'h0_0000_0400: dec_out = dout10[D_WID-1];
343 | 36'h0_0000_0800: dec_out = dout11[D_WID-1];
344 | 36'h0_0000_1000: dec_out = dout12[D_WID-1];
345 | 36'h0_0000_2000: dec_out = dout13[D_WID-1];
346 | 36'h0_0000_4000: dec_out = dout14[D_WID-1];
347 | 36'h0_0000_8000: dec_out = dout15[D_WID-1];
348 | 36'h0_0001_0000: dec_out = dout16[D_WID-1];
349 | 36'h0_0002_0000: dec_out = dout17[D_WID-1];
350 | 36'h0_0004_0000: dec_out = dout18[D_WID-1];
351 | 36'h0_0008_0000: dec_out = dout19[D_WID-1];
352 | 36'h0_0010_0000: dec_out = dout20[D_WID-1];
353 | 36'h0_0020_0000: dec_out = dout21[D_WID-1];
354 | 36'h0_0040_0000: dec_out = dout22[D_WID-1];
355 | 36'h0_0080_0000: dec_out = dout23[D_WID-1];
356 | 36'h0_0100_0000: dec_out = dout24[D_WID-1];
357 | 36'h0_0200_0000: dec_out = dout25[D_WID-1];
358 | 36'h0_0400_0000: dec_out = dout26[D_WID-1];
359 | 36'h0_0800_0000: dec_out = dout27[D_WID-1];
360 | 36'h0_1000_0000: dec_out = dout28[D_WID-1];
361 | 36'h0_2000_0000: dec_out = dout29[D_WID-1];
362 | 36'h0_4000_0000: dec_out = dout30[D_WID-1];
363 | 36'h0_8000_0000: dec_out = dout31[D_WID-1];
364 | 36'h1_0000_0000: dec_out = dout32[D_WID-1];
365 | 36'h2_0000_0000: dec_out = dout33[D_WID-1];
366 | 36'h4_0000_0000: dec_out = dout34[D_WID-1];
367 | 36'h8_0000_0000: dec_out = dout35[D_WID-1];
368 | default: dec_out = 1'b0;
369 | endcase
370 |
371 | //vtc_cell cel_00(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 0]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr00),.rd_addr(),.ram_wr(wr00),.ram_d(),.dctv(dctv00));
372 | //vtc_cell cel_01(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 1]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr01),.rd_addr(),.ram_wr(wr01),.ram_d(),.dctv(dctv01));
373 | //vtc_cell cel_02(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 2]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr02),.rd_addr(),.ram_wr(wr02),.ram_d(),.dctv(dctv02));
374 | //vtc_cell cel_03(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 3]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr03),.rd_addr(),.ram_wr(wr03),.ram_d(),.dctv(dctv03));
375 | //vtc_cell cel_04(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 4]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr04),.rd_addr(),.ram_wr(wr04),.ram_d(),.dctv(dctv04));
376 | //vtc_cell cel_05(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 5]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr05),.rd_addr(),.ram_wr(wr05),.ram_d(),.dctv(dctv05));
377 | //vtc_cell cel_06(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 6]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr06),.rd_addr(),.ram_wr(wr06),.ram_d(),.dctv(dctv06));
378 | //vtc_cell cel_07(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 7]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr07),.rd_addr(),.ram_wr(wr07),.ram_d(),.dctv(dctv07));
379 | //vtc_cell cel_08(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 8]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr08),.rd_addr(),.ram_wr(wr08),.ram_d(),.dctv(dctv08));
380 | //vtc_cell cel_09(.clk(clk),.reset_n(reset_n),.sin(sync_dly[ 9]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr09),.rd_addr(),.ram_wr(wr09),.ram_d(),.dctv(dctv09));
381 | //vtc_cell cel_10(.clk(clk),.reset_n(reset_n),.sin(sync_dly[10]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr10),.rd_addr(),.ram_wr(wr10),.ram_d(),.dctv(dctv10));
382 | //vtc_cell cel_11(.clk(clk),.reset_n(reset_n),.sin(sync_dly[11]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr11),.rd_addr(),.ram_wr(wr11),.ram_d(),.dctv(dctv11));
383 | //vtc_cell cel_12(.clk(clk),.reset_n(reset_n),.sin(sync_dly[12]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr12),.rd_addr(),.ram_wr(wr12),.ram_d(),.dctv(dctv12));
384 | //vtc_cell cel_13(.clk(clk),.reset_n(reset_n),.sin(sync_dly[13]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr13),.rd_addr(),.ram_wr(wr13),.ram_d(),.dctv(dctv13));
385 | //vtc_cell cel_14(.clk(clk),.reset_n(reset_n),.sin(sync_dly[14]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr14),.rd_addr(),.ram_wr(wr14),.ram_d(),.dctv(dctv14));
386 | //vtc_cell cel_15(.clk(clk),.reset_n(reset_n),.sin(sync_dly[15]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr15),.rd_addr(),.ram_wr(wr15),.ram_d(),.dctv(dctv15));
387 | //vtc_cell cel_16(.clk(clk),.reset_n(reset_n),.sin(sync_dly[16]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr16),.rd_addr(),.ram_wr(wr16),.ram_d(),.dctv(dctv16));
388 | //vtc_cell cel_17(.clk(clk),.reset_n(reset_n),.sin(sync_dly[17]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr17),.rd_addr(),.ram_wr(wr17),.ram_d(),.dctv(dctv17));
389 | //vtc_cell cel_18(.clk(clk),.reset_n(reset_n),.sin(sync_dly[18]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr18),.rd_addr(),.ram_wr(wr18),.ram_d(),.dctv(dctv18));
390 | //vtc_cell cel_19(.clk(clk),.reset_n(reset_n),.sin(sync_dly[19]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr19),.rd_addr(),.ram_wr(wr19),.ram_d(),.dctv(dctv19));
391 | //vtc_cell cel_20(.clk(clk),.reset_n(reset_n),.sin(sync_dly[20]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr20),.rd_addr(),.ram_wr(wr20),.ram_d(),.dctv(dctv20));
392 | //vtc_cell cel_21(.clk(clk),.reset_n(reset_n),.sin(sync_dly[21]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr21),.rd_addr(),.ram_wr(wr21),.ram_d(),.dctv(dctv21));
393 | //vtc_cell cel_22(.clk(clk),.reset_n(reset_n),.sin(sync_dly[22]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr22),.rd_addr(),.ram_wr(wr22),.ram_d(),.dctv(dctv22));
394 | //vtc_cell cel_23(.clk(clk),.reset_n(reset_n),.sin(sync_dly[23]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr23),.rd_addr(),.ram_wr(wr23),.ram_d(),.dctv(dctv23));
395 | //vtc_cell cel_24(.clk(clk),.reset_n(reset_n),.sin(sync_dly[24]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr24),.rd_addr(),.ram_wr(wr24),.ram_d(),.dctv(dctv24));
396 | //vtc_cell cel_25(.clk(clk),.reset_n(reset_n),.sin(sync_dly[25]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr25),.rd_addr(),.ram_wr(wr25),.ram_d(),.dctv(dctv25));
397 | //vtc_cell cel_26(.clk(clk),.reset_n(reset_n),.sin(sync_dly[26]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr26),.rd_addr(),.ram_wr(wr26),.ram_d(),.dctv(dctv26));
398 | //vtc_cell cel_27(.clk(clk),.reset_n(reset_n),.sin(sync_dly[27]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr27),.rd_addr(),.ram_wr(wr27),.ram_d(),.dctv(dctv27));
399 | //vtc_cell cel_28(.clk(clk),.reset_n(reset_n),.sin(sync_dly[28]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr28),.rd_addr(),.ram_wr(wr28),.ram_d(),.dctv(dctv28));
400 | //vtc_cell cel_29(.clk(clk),.reset_n(reset_n),.sin(sync_dly[29]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr29),.rd_addr(),.ram_wr(wr29),.ram_d(),.dctv(dctv29));
401 | //vtc_cell cel_30(.clk(clk),.reset_n(reset_n),.sin(sync_dly[30]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr30),.rd_addr(),.ram_wr(wr30),.ram_d(),.dctv(dctv30));
402 | //vtc_cell cel_31(.clk(clk),.reset_n(reset_n),.sin(sync_dly[31]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr31),.rd_addr(),.ram_wr(wr31),.ram_d(),.dctv(dctv31));
403 | //vtc_cell cel_32(.clk(clk),.reset_n(reset_n),.sin(sync_dly[32]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr32),.rd_addr(),.ram_wr(wr32),.ram_d(),.dctv(dctv32));
404 | //vtc_cell cel_33(.clk(clk),.reset_n(reset_n),.sin(sync_dly[33]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr33),.rd_addr(),.ram_wr(wr33),.ram_d(),.dctv(dctv33));
405 | //vtc_cell cel_34(.clk(clk),.reset_n(reset_n),.sin(sync_dly[34]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr34),.rd_addr(),.ram_wr(wr34),.ram_d(),.dctv(dctv34));
406 | //vtc_cell cel_35(.clk(clk),.reset_n(reset_n),.sin(sync_dly[35]),.din(data_dly),.fsm(fsm),.rate(rate),.cycle(cycle),.wr_addr(wr_addr35),.rd_addr(),.ram_wr(wr35),.ram_d(),.dctv(dctv35));
407 |
408 |
409 | sram2p256x8 u_ram00(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr00),.ADDRB(wr_addr00),.ENA(1'b0),.ENB(1'b0),.WEB(wr00),.DINB(din00),.DOUTA(dout00));
410 | sram2p256x8 u_ram01(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr01),.ADDRB(wr_addr01),.ENA(1'b0),.ENB(1'b0),.WEB(wr01),.DINB(din01),.DOUTA(dout01));
411 | sram2p256x8 u_ram02(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr02),.ADDRB(wr_addr02),.ENA(1'b0),.ENB(1'b0),.WEB(wr02),.DINB(din02),.DOUTA(dout02));
412 | sram2p256x8 u_ram03(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr03),.ADDRB(wr_addr03),.ENA(1'b0),.ENB(1'b0),.WEB(wr03),.DINB(din03),.DOUTA(dout03));
413 | sram2p256x8 u_ram04(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr04),.ADDRB(wr_addr04),.ENA(1'b0),.ENB(1'b0),.WEB(wr04),.DINB(din04),.DOUTA(dout04));
414 | sram2p256x8 u_ram05(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr05),.ADDRB(wr_addr05),.ENA(1'b0),.ENB(1'b0),.WEB(wr05),.DINB(din05),.DOUTA(dout05));
415 | sram2p256x8 u_ram06(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr06),.ADDRB(wr_addr06),.ENA(1'b0),.ENB(1'b0),.WEB(wr06),.DINB(din06),.DOUTA(dout06));
416 | sram2p256x8 u_ram07(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr07),.ADDRB(wr_addr07),.ENA(1'b0),.ENB(1'b0),.WEB(wr07),.DINB(din07),.DOUTA(dout07));
417 | sram2p256x8 u_ram08(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr08),.ADDRB(wr_addr08),.ENA(1'b0),.ENB(1'b0),.WEB(wr08),.DINB(din08),.DOUTA(dout08));
418 | sram2p256x8 u_ram09(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr09),.ADDRB(wr_addr09),.ENA(1'b0),.ENB(1'b0),.WEB(wr09),.DINB(din09),.DOUTA(dout09));
419 | sram2p256x8 u_ram10(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr10),.ADDRB(wr_addr10),.ENA(1'b0),.ENB(1'b0),.WEB(wr10),.DINB(din10),.DOUTA(dout10));
420 | sram2p256x8 u_ram11(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr11),.ADDRB(wr_addr11),.ENA(1'b0),.ENB(1'b0),.WEB(wr11),.DINB(din11),.DOUTA(dout11));
421 | sram2p256x8 u_ram12(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr12),.ADDRB(wr_addr12),.ENA(1'b0),.ENB(1'b0),.WEB(wr12),.DINB(din12),.DOUTA(dout12));
422 | sram2p256x8 u_ram13(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr13),.ADDRB(wr_addr13),.ENA(1'b0),.ENB(1'b0),.WEB(wr13),.DINB(din13),.DOUTA(dout13));
423 | sram2p256x8 u_ram14(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr14),.ADDRB(wr_addr14),.ENA(1'b0),.ENB(1'b0),.WEB(wr14),.DINB(din14),.DOUTA(dout14));
424 | sram2p256x8 u_ram15(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr15),.ADDRB(wr_addr15),.ENA(1'b0),.ENB(1'b0),.WEB(wr15),.DINB(din15),.DOUTA(dout15));
425 | sram2p256x8 u_ram16(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr16),.ADDRB(wr_addr16),.ENA(1'b0),.ENB(1'b0),.WEB(wr16),.DINB(din16),.DOUTA(dout16));
426 | sram2p256x8 u_ram17(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr17),.ADDRB(wr_addr17),.ENA(1'b0),.ENB(1'b0),.WEB(wr17),.DINB(din17),.DOUTA(dout17));
427 | sram2p256x8 u_ram18(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr18),.ADDRB(wr_addr18),.ENA(1'b0),.ENB(1'b0),.WEB(wr18),.DINB(din18),.DOUTA(dout18));
428 | sram2p256x8 u_ram19(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr19),.ADDRB(wr_addr19),.ENA(1'b0),.ENB(1'b0),.WEB(wr19),.DINB(din19),.DOUTA(dout19));
429 | sram2p256x8 u_ram20(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr20),.ADDRB(wr_addr20),.ENA(1'b0),.ENB(1'b0),.WEB(wr20),.DINB(din20),.DOUTA(dout20));
430 | sram2p256x8 u_ram21(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr21),.ADDRB(wr_addr21),.ENA(1'b0),.ENB(1'b0),.WEB(wr21),.DINB(din21),.DOUTA(dout21));
431 | sram2p256x8 u_ram22(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr22),.ADDRB(wr_addr22),.ENA(1'b0),.ENB(1'b0),.WEB(wr22),.DINB(din22),.DOUTA(dout22));
432 | sram2p256x8 u_ram23(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr23),.ADDRB(wr_addr23),.ENA(1'b0),.ENB(1'b0),.WEB(wr23),.DINB(din23),.DOUTA(dout23));
433 | sram2p256x8 u_ram24(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr24),.ADDRB(wr_addr24),.ENA(1'b0),.ENB(1'b0),.WEB(wr24),.DINB(din24),.DOUTA(dout24));
434 | sram2p256x8 u_ram25(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr25),.ADDRB(wr_addr25),.ENA(1'b0),.ENB(1'b0),.WEB(wr25),.DINB(din25),.DOUTA(dout25));
435 | sram2p256x8 u_ram26(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr26),.ADDRB(wr_addr26),.ENA(1'b0),.ENB(1'b0),.WEB(wr26),.DINB(din26),.DOUTA(dout26));
436 | sram2p256x8 u_ram27(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr27),.ADDRB(wr_addr27),.ENA(1'b0),.ENB(1'b0),.WEB(wr27),.DINB(din27),.DOUTA(dout27));
437 | sram2p256x8 u_ram28(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr28),.ADDRB(wr_addr28),.ENA(1'b0),.ENB(1'b0),.WEB(wr28),.DINB(din28),.DOUTA(dout28));
438 | sram2p256x8 u_ram29(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr29),.ADDRB(wr_addr29),.ENA(1'b0),.ENB(1'b0),.WEB(wr29),.DINB(din29),.DOUTA(dout29));
439 | sram2p256x8 u_ram30(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr30),.ADDRB(wr_addr30),.ENA(1'b0),.ENB(1'b0),.WEB(wr30),.DINB(din30),.DOUTA(dout30));
440 | sram2p256x8 u_ram31(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr31),.ADDRB(wr_addr31),.ENA(1'b0),.ENB(1'b0),.WEB(wr31),.DINB(din31),.DOUTA(dout31));
441 | sram2p256x8 u_ram32(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr32),.ADDRB(wr_addr32),.ENA(1'b0),.ENB(1'b0),.WEB(wr32),.DINB(din32),.DOUTA(dout32));
442 | sram2p256x8 u_ram33(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr33),.ADDRB(wr_addr33),.ENA(1'b0),.ENB(1'b0),.WEB(wr33),.DINB(din33),.DOUTA(dout33));
443 | sram2p256x8 u_ram34(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr34),.ADDRB(wr_addr34),.ENA(1'b0),.ENB(1'b0),.WEB(wr34),.DINB(din34),.DOUTA(dout34));
444 | sram2p256x8 u_ram35(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr35),.ADDRB(wr_addr35),.ENA(1'b0),.ENB(1'b0),.WEB(wr35),.DINB(din35),.DOUTA(dout35));
445 |
446 | sram2p768x52 lr_ram00(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr),.ADDRB(wr_addr),.ENA(1'b0),.ENB(1'b0),.WEB(wr0),.DINB(mem0_in),.DOUTA(mem0_out));
447 | sram2p768x52 lr_ram01(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr),.ADDRB(wr_addr),.ENA(1'b0),.ENB(1'b0),.WEB(wr0),.DINB(mem1_in),.DOUTA(mem1_out));
448 | sram2p768x52 lr_ram02(.CLKA(clk),.CLKB(clk),.ADDRA(rd_addr),.ADDRB(wr_addr),.ENA(1'b0),.ENB(1'b0),.WEB(wr0),.DINB(mem2_in),.DOUTA(mem2_out));
449 |
450 | ldpc_ctrl u_ldpc_ctrl(
451 | .clk ( clk ),
452 | .reset_n ( reset_n ),
453 | .sync_in ( sync_in ),
454 | .rate ( rate ),
455 | .max_iter ( max_iter ),
456 | .ctv_out ( ctv_out ),
457 | .sigma_vnu ( sigma_vnu ),
458 |
459 | .fsm_state ( fsm ),
460 | .cycle ( cycle ),
461 | .finish ( ),
462 | .busy ( busy ),
463 | .iter_0 ( iter_0 ),
464 | .wr_lq ( wr_lq ),
465 | .wr_lr ( wr_lr ),
466 | .rd_lq ( rd_lq ),
467 | .rd_lr ( rd_lr ),
468 | .num_iter ( num_iter )
469 |
470 | );
471 |
472 | addr_gen u_addr_gen(
473 | .clk (clk ),
474 | .reset_n (reset_n ),
475 | .fsm (fsm ),
476 | .cycle (cycle ),
477 | .rate (rate ),
478 | .sync_in (sync_dly ),
479 | .wr_lq ( wr_lq ),
480 | .wr_lr ( wr_lr ),
481 | .rd_lq ( rd_lq ),
482 | .rd_lr ( rd_lr ),
483 | .out_sel (out_sel ),
484 | .out_en (out_en ),
485 | .rd_addr00 (rd_addr00),
486 | .rd_addr01 (rd_addr01),
487 | .rd_addr02 (rd_addr02),
488 | .rd_addr03 (rd_addr03),
489 | .rd_addr04 (rd_addr04),
490 | .rd_addr05 (rd_addr05),
491 | .rd_addr06 (rd_addr06),
492 | .rd_addr07 (rd_addr07),
493 | .rd_addr08 (rd_addr08),
494 | .rd_addr09 (rd_addr09),
495 | .rd_addr10 (rd_addr10),
496 | .rd_addr11 (rd_addr11),
497 | .rd_addr12 (rd_addr12),
498 | .rd_addr13 (rd_addr13),
499 | .rd_addr14 (rd_addr14),
500 | .rd_addr15 (rd_addr15),
501 | .rd_addr16 (rd_addr16),
502 | .rd_addr17 (rd_addr17),
503 | .rd_addr18 (rd_addr18),
504 | .rd_addr19 (rd_addr19),
505 | .rd_addr20 (rd_addr20),
506 | .rd_addr21 (rd_addr21),
507 | .rd_addr22 (rd_addr22),
508 | .rd_addr23 (rd_addr23),
509 | .rd_addr24 (rd_addr24),
510 | .rd_addr25 (rd_addr25),
511 | .rd_addr26 (rd_addr26),
512 | .rd_addr27 (rd_addr27),
513 | .rd_addr28 (rd_addr28),
514 | .rd_addr29 (rd_addr29),
515 | .rd_addr30 (rd_addr30),
516 | .rd_addr31 (rd_addr31),
517 | .rd_addr32 (rd_addr32),
518 | .rd_addr33 (rd_addr33),
519 | .rd_addr34 (rd_addr34),
520 | .rd_addr35 (rd_addr35),
521 | .wr_addr00 (wr_addr00),
522 | .wr_addr01 (wr_addr01),
523 | .wr_addr02 (wr_addr02),
524 | .wr_addr03 (wr_addr03),
525 | .wr_addr04 (wr_addr04),
526 | .wr_addr05 (wr_addr05),
527 | .wr_addr06 (wr_addr06),
528 | .wr_addr07 (wr_addr07),
529 | .wr_addr08 (wr_addr08),
530 | .wr_addr09 (wr_addr09),
531 | .wr_addr10 (wr_addr10),
532 | .wr_addr11 (wr_addr11),
533 | .wr_addr12 (wr_addr12),
534 | .wr_addr13 (wr_addr13),
535 | .wr_addr14 (wr_addr14),
536 | .wr_addr15 (wr_addr15),
537 | .wr_addr16 (wr_addr16),
538 | .wr_addr17 (wr_addr17),
539 | .wr_addr18 (wr_addr18),
540 | .wr_addr19 (wr_addr19),
541 | .wr_addr20 (wr_addr20),
542 | .wr_addr21 (wr_addr21),
543 | .wr_addr22 (wr_addr22),
544 | .wr_addr23 (wr_addr23),
545 | .wr_addr24 (wr_addr24),
546 | .wr_addr25 (wr_addr25),
547 | .wr_addr26 (wr_addr26),
548 | .wr_addr27 (wr_addr27),
549 | .wr_addr28 (wr_addr28),
550 | .wr_addr29 (wr_addr29),
551 | .wr_addr30 (wr_addr30),
552 | .wr_addr31 (wr_addr31),
553 | .wr_addr32 (wr_addr32),
554 | .wr_addr33 (wr_addr33),
555 | .wr_addr34 (wr_addr34),
556 | .wr_addr35 (wr_addr35),
557 | .wr00 (wr00 ),
558 | .wr01 (wr01 ),
559 | .wr02 (wr02 ),
560 | .wr03 (wr03 ),
561 | .wr04 (wr04 ),
562 | .wr05 (wr05 ),
563 | .wr06 (wr06 ),
564 | .wr07 (wr07 ),
565 | .wr08 (wr08 ),
566 | .wr09 (wr09 ),
567 | .wr10 (wr10 ),
568 | .wr11 (wr11 ),
569 | .wr12 (wr12 ),
570 | .wr13 (wr13 ),
571 | .wr14 (wr14 ),
572 | .wr15 (wr15 ),
573 | .wr16 (wr16 ),
574 | .wr17 (wr17 ),
575 | .wr18 (wr18 ),
576 | .wr19 (wr19 ),
577 | .wr20 (wr20 ),
578 | .wr21 (wr21 ),
579 | .wr22 (wr22 ),
580 | .wr23 (wr23 ),
581 | .wr24 (wr24 ),
582 | .wr25 (wr25 ),
583 | .wr26 (wr26 ),
584 | .wr27 (wr27 ),
585 | .wr28 (wr28 ),
586 | .wr29 (wr29 ),
587 | .wr30 (wr30 ),
588 | .wr31 (wr31 ),
589 | .wr32 (wr32 ),
590 | .wr33 (wr33 ),
591 | .wr34 (wr34 ),
592 | .wr35 (wr35 ),
593 | .rd_addr (rd_addr ),
594 | .wr_addr (wr_addr ),
595 | .wr0 (wr0 )
596 | );
597 |
598 |
599 | data_comp u_data_comp(
600 | .clk ( clk ),
601 | .reset_n ( reset_n ),
602 | .fsm ( fsm ),
603 | .cycle ( cycle[3:2] ),
604 | .rate ( rate ),
605 | .iter_0 ( iter_0 ),
606 | .sync_in ( sync_dly ),
607 | .data_in ( data_dly ),
608 | .ctv_out ( ctv_out ),
609 | .sigma_vnu ( sigma_vnu ),
610 | .dout00 ( dout00 ),
611 | .dout01 ( dout01 ),
612 | .dout02 ( dout02 ),
613 | .dout03 ( dout03 ),
614 | .dout04 ( dout04 ),
615 | .dout05 ( dout05 ),
616 | .dout06 ( dout06 ),
617 | .dout07 ( dout07 ),
618 | .dout08 ( dout08 ),
619 | .dout09 ( dout09 ),
620 | .dout10 ( dout10 ),
621 | .dout11 ( dout11 ),
622 | .dout12 ( dout12 ),
623 | .dout13 ( dout13 ),
624 | .dout14 ( dout14 ),
625 | .dout15 ( dout15 ),
626 | .dout16 ( dout16 ),
627 | .dout17 ( dout17 ),
628 | .dout18 ( dout18 ),
629 | .dout19 ( dout19 ),
630 | .dout20 ( dout20 ),
631 | .dout21 ( dout21 ),
632 | .dout22 ( dout22 ),
633 | .dout23 ( dout23 ),
634 | .dout24 ( dout24 ),
635 | .dout25 ( dout25 ),
636 | .dout26 ( dout26 ),
637 | .dout27 ( dout27 ),
638 | .dout28 ( dout28 ),
639 | .dout29 ( dout29 ),
640 | .dout30 ( dout30 ),
641 | .dout31 ( dout31 ),
642 | .dout32 ( dout32 ),
643 | .dout33 ( dout33 ),
644 | .dout34 ( dout34 ),
645 | .dout35 ( dout35 ),
646 | .din00 ( din00 ),
647 | .din01 ( din01 ),
648 | .din02 ( din02 ),
649 | .din03 ( din03 ),
650 | .din04 ( din04 ),
651 | .din05 ( din05 ),
652 | .din06 ( din06 ),
653 | .din07 ( din07 ),
654 | .din08 ( din08 ),
655 | .din09 ( din09 ),
656 | .din10 ( din10 ),
657 | .din11 ( din11 ),
658 | .din12 ( din12 ),
659 | .din13 ( din13 ),
660 | .din14 ( din14 ),
661 | .din15 ( din15 ),
662 | .din16 ( din16 ),
663 | .din17 ( din17 ),
664 | .din18 ( din18 ),
665 | .din19 ( din19 ),
666 | .din20 ( din20 ),
667 | .din21 ( din21 ),
668 | .din22 ( din22 ),
669 | .din23 ( din23 ),
670 | .din24 ( din24 ),
671 | .din25 ( din25 ),
672 | .din26 ( din26 ),
673 | .din27 ( din27 ),
674 | .din28 ( din28 ),
675 | .din29 ( din29 ),
676 | .din30 ( din30 ),
677 | .din31 ( din31 ),
678 | .din32 ( din32 ),
679 | .din33 ( din33 ),
680 | .din34 ( din34 ),
681 | .din35 ( din35 ),
682 | .mem0_in ( mem0_in ),
683 | .mem0_out ( mem0_out ),
684 | .mem1_in ( mem1_in ),
685 | .mem1_out ( mem1_out ),
686 | .mem2_in ( mem2_in ),
687 | .mem2_out ( mem2_out )
688 | );
689 |
690 | endmodule
691 |
--------------------------------------------------------------------------------
/ldpc_rtl/ldpc_ctrl.v:
--------------------------------------------------------------------------------
1 | //Module
2 | module ldpc_ctrl(
3 | clk,
4 | reset_n,
5 | sync_in,
6 | rate,
7 | max_iter,
8 | ctv_out,
9 | sigma_vnu,
10 |
11 | fsm_state,
12 | cycle,
13 | finish,
14 | busy,
15 | iter_0,
16 | wr_lq,
17 | wr_lr,
18 | rd_lq,
19 | rd_lr,
20 | num_iter
21 | );
22 |
23 | //Input ports
24 | input clk ;
25 | input reset_n ;
26 | input rate ; // 0, 1/2 1, 3/4
27 | input sync_in ;
28 | input [4:0] max_iter ;
29 | input ctv_out ;
30 | input sigma_vnu ;
31 |
32 | //Output ports
33 | output [3:0] fsm_state ;
34 | output [3:0] cycle ;
35 | output finish ;
36 | output busy ;
37 | output [4:0] num_iter ;
38 | output iter_0 ;
39 | output wr_lq ;
40 | output wr_lr ;
41 | output rd_lq ;
42 | output rd_lr ;
43 |
44 | //Paramter
45 | parameter IDLE = 5'b00001,
46 | DATA_I = 5'b00010,
47 | CNU_U = 5'b00100,
48 | VNU_U = 5'b01000,
49 | DATA_O = 5'b10000;
50 | // WAIT = 5'b00001;
51 |
52 | //Intenal Reg and Wires Definition
53 | //reg [3:0] fsm_state ;
54 | reg finish ;
55 | reg busy ;
56 | reg [4:0] num_iter ;
57 | //reg [3:0] cycle ;
58 |
59 | reg sync_dly ;
60 | reg sync_dly2 ;
61 | reg sync_out_d ;
62 | //reg [3:0] next_state ;
63 | reg [12:0] counter ;
64 | //reg wr_ena ;
65 | reg wr_lq ;
66 | //reg wr_lr ;
67 | reg rd_lq ;
68 | reg rd_lr ;
69 | //reg [7:0] rd_lq_cnt ;
70 | //reg [7:0] wr_lq_cnt ;
71 | reg [6:0] step ;
72 | reg iter_0 ;
73 | reg rd_lq_ena ;
74 | reg wr_lq_ena ;
75 | reg wr_lr_ena ;
76 | reg error_det ;
77 | reg [1:0] rd_cycle ;
78 | reg [1:0] wr_cycle ;
79 | //////////////////////////////////
80 | reg [4:0] fsm ;
81 | reg [4:0] next_fsm ;
82 |
83 | wire [3:0] cycle ;
84 | wire sync_end ;
85 | wire iter_end ;
86 | //wire vnu_end ;
87 | wire sync_out_end;
88 | wire [12:0] counter_max;
89 | //wire rd_ena ;
90 | wire fsm_cnu ;
91 | wire rd_lq_end ;
92 | wire wr_lq_end ;
93 | wire wr_lq_pre ;
94 |
95 | assign cycle = {rd_cycle, wr_cycle};
96 | assign wr_lr = wr_lr_ena;
97 | assign fsm_state = {fsm[4],fsm[3]|fsm[2],fsm[1],fsm[0]};
98 | //assign rd_lr = rd_lq_ena & ( num_iter != 'd1);
99 | assign counter_max = rate ? 'd6911 : 'd4607;
100 | assign sync_end = sync_dly2 & (!sync_dly);
101 | assign iter_end = (num_iter == max_iter);
102 | //assign vnu_end = (rd_lq_cnt == 8'hff) & fsm[2];
103 | assign sync_out_end = (counter == counter_max) & fsm[4];
104 | //assign rd_ena = next_state == CNU;
105 | //assign iter_0 = ( num_iter == 0);
106 |
107 | // sync in delay register
108 | always @ (posedge clk or negedge reset_n)
109 | begin : sync_d1
110 | if(!reset_n)
111 | sync_dly <= #1 1'b0;
112 | else
113 | sync_dly <= #1 sync_in;
114 | end
115 |
116 | always @ (posedge clk or negedge reset_n)
117 | begin : sync_d2
118 | if(!reset_n)
119 | sync_dly2 <= #1 1'b0;
120 | else
121 | sync_dly2 <= #1 sync_dly;
122 | end
123 |
124 | // ldpc_busy status
125 | always @ (posedge clk or negedge reset_n)
126 | begin : busy_r
127 | if(!reset_n)
128 | busy <= #1 1'b0;
129 | else if(finish)
130 | busy <= #1 1'b0;
131 | else if(sync_end)
132 | busy <= #1 1'b1;
133 | end
134 |
135 | always @ (posedge clk or negedge reset_n)
136 | begin : finish_r
137 | if(!reset_n)
138 | finish <= #1 1'b0;
139 | else
140 | finish <= #1 sync_out_d;
141 | end
142 |
143 | always @ (posedge clk or negedge reset_n)
144 | begin : sync_out_d1
145 | if(!reset_n)
146 | sync_out_d <= #1 1'b0;
147 | else
148 | sync_out_d <= sync_out_end;
149 | end
150 | // FSM
151 | /*
152 | always @ (posedge clk or negedge reset_n)
153 | begin : fsm_state_r
154 | if(!reset_n)
155 | fsm_state <= #1 IDLE;
156 | else
157 | fsm_state <= #1 next_state;
158 | end
159 |
160 | always @ (*)
161 | begin : fsm_next_state_r
162 | case(fsm_state)
163 | IDLE: if(sync_in)
164 | next_state = DATA_IN;
165 | DATA_IN: if(sync_end)
166 | next_state = CNU;
167 | CNU: if(vnu_end)
168 | begin
169 | if(iter_end)
170 | next_state = DATA_OUT;
171 | else
172 | next_state = CNU;
173 | end
174 | DATA_OUT: if(sync_out_end)
175 | next_state = IDLE;
176 | default:
177 | next_state = IDLE;
178 | endcase
179 | end
180 |
181 | //(*)
182 | // Cycle 01->10->11
183 | always @ (posedge clk or negedge reset_n)
184 | begin : cycle0_r
185 | if(!reset_n)
186 | cycle[3:2] <= #1 2'b0;
187 | else if((next_state == CNU) & rd_ena ) begin
188 | if(cycle[3:2] == 2'b11)
189 | cycle[3:2] <= #1 2'b01;
190 | else
191 | cycle[3:2] <= #1 cycle[3:2] + 1'b1;
192 | end
193 | else
194 | cycle[3:2] <= #1 2'b0;
195 | end
196 |
197 | always @ (posedge clk or negedge reset_n)
198 | begin : cycle1_r
199 | if(!reset_n)
200 | cycle[1:0] <= #1 2'b0;
201 | else if((next_state == CNU) & wr_ena) begin
202 | if(cycle[1:0] == 2'b11)
203 | cycle[1:0] <= #1 2'b01;
204 | else
205 | cycle[1:0] <= #1 cycle[1:0] + 1'b1;
206 | end
207 | else
208 | cycle[1:0] <= #1 2'b0;
209 | end
210 | */
211 | // Number of iteration
212 | always @ (posedge clk or negedge reset_n)
213 | begin: num_iter_r
214 | if(!reset_n)
215 | num_iter <= #1 5'h0;
216 | else if(sync_in)
217 | num_iter <= #1 5'h0;
218 | else if(fsm_cnu)
219 | num_iter <=#1 num_iter + 1'b1;
220 | end
221 |
222 | // This section is not implment in the end
223 | //
224 | always @ (posedge clk or negedge reset_n)
225 | begin: counter_r
226 | if(!reset_n)
227 | counter <= #1 13'h0;
228 | else if(fsm[2] | fsm[3]) begin
229 | if(wr_lq_end)
230 | counter <= #1 13'h0;
231 | else
232 | counter <= #1 counter + 1'b1;
233 | end
234 | else if(fsm[4]) begin
235 | if(counter == counter_max)
236 | counter <= #1 13'h0;
237 | else
238 | counter <= #1 counter + 1'b1;
239 | end
240 | end
241 | /*
242 | always @ (posedge clk or negedge reset_n)
243 | begin : wr_ena_r
244 | if(!reset_n)
245 | wr_ena <= #1 1'b0;
246 | else if(step[6])
247 | wr_ena <= #1 1'b1;
248 | else if(iter_end)
249 | wr_ena <= #1 1'b0;
250 | end
251 | */
252 | always @ (posedge clk or negedge reset_n)
253 | begin : wr_lq_r
254 | if(!reset_n)
255 | wr_lq <= #1 1'b0;
256 | else if(cycle[1:0] == 2'b10)
257 | wr_lq <= #1 1'b1;
258 | else
259 | wr_lq <= #1 1'b0;
260 | end
261 |
262 | always @ (posedge clk or negedge reset_n)
263 | begin : rd_lq_r
264 | if(!reset_n)
265 | rd_lq <= #1 1'b0;
266 | else if(cycle[3:2] == 2'b10)
267 | rd_lq <= #1 1'b1;
268 | else
269 | rd_lq <= #1 1'b0;
270 | end
271 | /*
272 | always @ (posedge clk or negedge reset_n)
273 | begin : wr_lr_r
274 | if(!reset_n)
275 | wr_lr<= #1 1'b0;
276 | else if(step[6])
277 | wr_lr <= #1 1'b1;
278 | end
279 | */
280 | always @ (posedge clk or negedge reset_n)
281 | begin : rd_lr_r
282 | if(!reset_n)
283 | rd_lr <= #1 1'b0;
284 | else
285 | rd_lr <= #1 rd_lq_ena & (num_iter != 'd1);
286 | end
287 | /*
288 | always @ (posedge clk or negedge reset_n)
289 | begin : rd_lq_cnt_r
290 | if(!reset_n)
291 | rd_lq_cnt <= #1 8'h0;
292 | else if(step[3])
293 | rd_lq_cnt <= #1 rd_lq_cnt + 1'b1;
294 | end
295 |
296 | always @ (posedge clk or negedge reset_n)
297 | begin : wr_lq_cnt_r
298 | if(!reset_n)
299 | wr_lq_cnt <= #1 8'h0;
300 | else if(step[10])
301 | wr_lq_cnt <= #1 wr_lq_cnt + 1'b1;
302 | end
303 | */
304 | always @ (posedge clk or negedge reset_n)
305 | begin : step_r
306 | if(!reset_n)
307 | step <= #1 7'h0;
308 | else
309 | step <= #1 { step[5:0],rd_lq };
310 | end
311 |
312 | always @ (posedge clk or negedge reset_n)
313 | begin : iter_0r
314 | if(!reset_n)
315 | iter_0 <= #1 1'b0;
316 | else
317 | iter_0 <= #1 (num_iter == 'd1);
318 | end
319 |
320 | assign fsm_cnu = (( fsm == DATA_I ) | fsm == VNU_U) & ( next_fsm == CNU_U );
321 | assign rd_lq_end = (counter == 'd767);
322 | assign wr_lq_end = (counter == 'd778);
323 | assign wr_lq_pre = (counter == 'd777);
324 |
325 | always @ (posedge clk or negedge reset_n)
326 | begin : rd_lq_ena_r
327 | if(!reset_n)
328 | rd_lq_ena <= #1 1'b0;
329 | else if(fsm_cnu)
330 | rd_lq_ena <= #1 1'b1;
331 | else if(rd_lq_end)
332 | rd_lq_ena <= #1 1'b0;
333 | end
334 |
335 | always @ (posedge clk or negedge reset_n)
336 | begin : wr_lq_ena_r
337 | if(!reset_n)
338 | wr_lq_ena <= #1 1'b0;
339 | else if(wr_lq_pre)
340 | wr_lq_ena <= #1 1'b0;
341 | else if(step[6] & rd_lq_ena)
342 | wr_lq_ena <= #1 1'b1;
343 | end
344 |
345 | always @ (posedge clk or negedge reset_n)
346 | begin : wr_lr_ena_r
347 | if(!reset_n)
348 | wr_lr_ena <= #1 1'b0;
349 | else if(counter == 'd777)
350 | wr_lr_ena <= #1 1'b0;
351 | else if(step[6] & rd_lq_ena)
352 | wr_lr_ena <= #1 1'b1;
353 | end
354 |
355 | always @ (posedge clk or negedge reset_n)
356 | begin : error_det_r
357 | if(!reset_n)
358 | error_det <= #1 1'b0;
359 | else if(fsm_cnu)
360 | error_det <= #1 1'b0;
361 | else if(sigma_vnu)
362 | error_det <= #1 1'b1;
363 | end
364 |
365 | always @ (posedge clk or negedge reset_n)
366 | begin : fsm_r
367 | if(!reset_n)
368 | fsm <= #1 IDLE;
369 | else
370 | fsm <= #1 next_fsm;
371 | end
372 |
373 | always @ (*)
374 | begin
375 | case(fsm)
376 | IDLE: if(sync_in)
377 | next_fsm = DATA_I;
378 | else
379 | next_fsm = IDLE;
380 | DATA_I: if(sync_end)
381 | next_fsm = CNU_U;
382 | else
383 | next_fsm = DATA_I;
384 | CNU_U: if(rd_lq_end)
385 | next_fsm = VNU_U;
386 | else
387 | next_fsm = CNU_U;
388 | VNU_U: if(wr_lq_end) begin
389 | if(!error_det | iter_end)
390 | next_fsm = DATA_O;
391 | else
392 | next_fsm = CNU_U;
393 | end
394 | else
395 | next_fsm = VNU_U;
396 | DATA_O: if(sync_out_end)
397 | next_fsm = IDLE;
398 | else
399 | next_fsm = DATA_O;
400 | // WAIT:
401 | // next_fsm = IDLE;
402 | default:
403 | next_fsm = IDLE;
404 | endcase
405 | end
406 |
407 | always @ (posedge clk or negedge reset_n)
408 | begin : rd_cycle_r
409 | if(!reset_n)
410 | rd_cycle <= #1 2'b0;
411 | else if((fsm_cnu | rd_lq_ena) & (!rd_lq_end) ) begin
412 | if(rd_cycle == 2'b11)
413 | rd_cycle <= #1 2'b01;
414 | else
415 | rd_cycle <= #1 rd_cycle + 1'b1;
416 | end
417 | else
418 | rd_cycle <= #1 2'b0;
419 | end
420 |
421 | always @ (posedge clk or negedge reset_n)
422 | begin : wr_cycle_r
423 | if(!reset_n)
424 | wr_cycle <= #1 2'h0;
425 | else if(wr_lq_ena) begin
426 | if(wr_cycle == 2'b11)
427 | wr_cycle <= #1 2'b01;
428 | else
429 | wr_cycle <= #1 wr_cycle + 1'b1;
430 | end
431 | else
432 | wr_cycle <= #1 2'b0;
433 | end
434 |
435 | endmodule
436 |
--------------------------------------------------------------------------------
/ldpc_rtl/ldpc_dec.v:
--------------------------------------------------------------------------------
1 | //Defines
2 | //
3 | //Module
4 | module ldpc_dec(
5 | clk,
6 | reset_n,
7 | code_rate,
8 | data_in,
9 | sync_in,
10 | max_iter,
11 |
12 | data_out,
13 | sync_out,
14 | busy,
15 | num_iter,
16 | );
17 |
18 | parameter D_WID = 6;
19 |
20 | //Input ports
21 | input clk ;
22 | input reset_n ;
23 | input code_rate ; // 0, 1/2 1, 3/4
24 | input [D_WID-1:0] data_in ; // LLR input
25 | input sync_in ;
26 | input [4:0] max_iter ;
27 |
28 | //Output ports
29 | output data_out ;
30 | output sync_out ;
31 | output busy ; // ldpc is running
32 | //output finish ; // ldpc decoder finish, can read new data
33 | output [4:0] num_iter ; // iteration number
34 |
35 | //Internal wires definition
36 | wire [3:0] fsm_state ;
37 |
38 | //Sub module body
39 | //ldpc_ctv u_ldpc_ctv( );
40 |
41 | ldpc_ctrl u_ldpc_ctrl(
42 | .clk ( clk ),
43 | .reset_n ( reset_n ),
44 | .sync_in ( sync_in ),
45 | .code_rate ( code_rate ),
46 | .max_iter ( max_iter ),
47 |
48 | .fsm_state ( fsm_state ),
49 | .finish ( ),
50 | .busy ( busy ),
51 | .num_iter ( num_iter )
52 |
53 | );
54 |
55 | //lr_decom u_lr_decom();
56 |
57 | ldpc_vtc u_ldpc_vtc(
58 | .clk ( clk ),
59 | .reset_n ( reset_n ),
60 | .data_in ( data_in ),
61 | .sync_in ( sync_in ),
62 | .fsm_state ( fsm_state ),
63 | .code_rate ( code_rate ),
64 |
65 | .lq_dat_i ( la_dat_i ),
66 | .lq_dat_o ( lq_dat_o )
67 |
68 | );
69 |
70 | //ldpc_cnu u_ldpc_cnu();
71 |
72 | endmodule
73 |
--------------------------------------------------------------------------------
/ldpc_rtl/ldpc_vtc.v:
--------------------------------------------------------------------------------
1 | //Module
2 | module ldpc_vtc(
3 | clk,
4 | reset_n,
5 | data_in,
6 | sync_in,
7 | fsm_state,
8 | code_rate,
9 |
10 | lq_dat_i,
11 | lq_dat_o
12 | );
13 |
14 | //Parameter
15 | parameter D_WID = 6;
16 | parameter A_WID = 8;
17 |
18 | //Input ports
19 | input clk ;
20 | input reset_n ;
21 | input code_rate ; // 0, 1/2 1, 3/4
22 | input [D_WID-1:0] data_in ; // LLR input
23 | input sync_in ;
24 | input [3:0] fsm_state ;
25 | input [12*D_WID-1:0] lq_dat_i ;
26 |
27 | //Output ports
28 | output [12*D_WID-1:0] lq_dat_o ;
29 |
30 | //Internal Register and Wire definition
31 |
32 | wire [A_WID-1:0] addr00 ;
33 | wire [A_WID-1:0] addr01 ;
34 | wire [A_WID-1:0] addr02 ;
35 | wire [A_WID-1:0] addr03 ;
36 | wire [A_WID-1:0] addr04 ;
37 | wire [A_WID-1:0] addr05 ;
38 | wire [A_WID-1:0] addr06 ;
39 | wire [A_WID-1:0] addr07 ;
40 | wire [A_WID-1:0] addr08 ;
41 | wire [A_WID-1:0] addr09 ;
42 | wire [A_WID-1:0] addr10 ;
43 | wire [A_WID-1:0] addr11 ;
44 | wire [A_WID-1:0] addr12 ;
45 | wire [A_WID-1:0] addr13 ;
46 | wire [A_WID-1:0] addr14 ;
47 | wire [A_WID-1:0] addr15 ;
48 | wire [A_WID-1:0] addr16 ;
49 | wire [A_WID-1:0] addr17 ;
50 | wire [A_WID-1:0] addr18 ;
51 | wire [A_WID-1:0] addr19 ;
52 | wire [A_WID-1:0] addr20 ;
53 | wire [A_WID-1:0] addr21 ;
54 | wire [A_WID-1:0] addr22 ;
55 | wire [A_WID-1:0] addr23 ;
56 | wire [A_WID-1:0] addr24 ;
57 | wire [A_WID-1:0] addr25 ;
58 | wire [A_WID-1:0] addr26 ;
59 | wire [A_WID-1:0] addr27 ;
60 | wire [A_WID-1:0] addr28 ;
61 | wire [A_WID-1:0] addr29 ;
62 | wire [A_WID-1:0] addr30 ;
63 | wire [A_WID-1:0] addr31 ;
64 | wire [A_WID-1:0] addr32 ;
65 | wire [A_WID-1:0] addr33 ;
66 | wire [A_WID-1:0] addr34 ;
67 | wire [A_WID-1:0] addr35 ;
68 |
69 | wire wr00 ;
70 | wire wr01 ;
71 | wire wr02 ;
72 | wire wr03 ;
73 | wire wr04 ;
74 | wire wr05 ;
75 | wire wr06 ;
76 | wire wr07 ;
77 | wire wr08 ;
78 | wire wr09 ;
79 | wire wr10 ;
80 | wire wr11 ;
81 | wire wr12 ;
82 | wire wr13 ;
83 | wire wr14 ;
84 | wire wr15 ;
85 | wire wr16 ;
86 | wire wr17 ;
87 | wire wr18 ;
88 | wire wr19 ;
89 | wire wr20 ;
90 | wire wr21 ;
91 | wire wr22 ;
92 | wire wr23 ;
93 | wire wr24 ;
94 | wire wr25 ;
95 | wire wr26 ;
96 | wire wr27 ;
97 | wire wr28 ;
98 | wire wr29 ;
99 | wire wr30 ;
100 | wire wr31 ;
101 | wire wr32 ;
102 | wire wr33 ;
103 | wire wr34 ;
104 | wire wr35 ;
105 |
106 | wire [D_WID-1:0] din00 ;
107 | wire [D_WID-1:0] din01 ;
108 | wire [D_WID-1:0] din02 ;
109 | wire [D_WID-1:0] din03 ;
110 | wire [D_WID-1:0] din04 ;
111 | wire [D_WID-1:0] din05 ;
112 | wire [D_WID-1:0] din06 ;
113 | wire [D_WID-1:0] din07 ;
114 | wire [D_WID-1:0] din08 ;
115 | wire [D_WID-1:0] din09 ;
116 | wire [D_WID-1:0] din10 ;
117 | wire [D_WID-1:0] din11 ;
118 | wire [D_WID-1:0] din12 ;
119 | wire [D_WID-1:0] din13 ;
120 | wire [D_WID-1:0] din14 ;
121 | wire [D_WID-1:0] din15 ;
122 | wire [D_WID-1:0] din16 ;
123 | wire [D_WID-1:0] din17 ;
124 | wire [D_WID-1:0] din18 ;
125 | wire [D_WID-1:0] din19 ;
126 | wire [D_WID-1:0] din20 ;
127 | wire [D_WID-1:0] din21 ;
128 | wire [D_WID-1:0] din22 ;
129 | wire [D_WID-1:0] din23 ;
130 | wire [D_WID-1:0] din24 ;
131 | wire [D_WID-1:0] din25 ;
132 | wire [D_WID-1:0] din26 ;
133 | wire [D_WID-1:0] din27 ;
134 | wire [D_WID-1:0] din28 ;
135 | wire [D_WID-1:0] din29 ;
136 | wire [D_WID-1:0] din30 ;
137 | wire [D_WID-1:0] din31 ;
138 | wire [D_WID-1:0] din32 ;
139 | wire [D_WID-1:0] din33 ;
140 | wire [D_WID-1:0] din34 ;
141 | wire [D_WID-1:0] din35 ;
142 | wire [D_WID-1:0] dout00 ;
143 | wire [D_WID-1:0] dout01 ;
144 | wire [D_WID-1:0] dout02 ;
145 | wire [D_WID-1:0] dout03 ;
146 | wire [D_WID-1:0] dout04 ;
147 | wire [D_WID-1:0] dout05 ;
148 | wire [D_WID-1:0] dout06 ;
149 | wire [D_WID-1:0] dout07 ;
150 | wire [D_WID-1:0] dout08 ;
151 | wire [D_WID-1:0] dout09 ;
152 | wire [D_WID-1:0] dout10 ;
153 | wire [D_WID-1:0] dout11 ;
154 | wire [D_WID-1:0] dout12 ;
155 | wire [D_WID-1:0] dout13 ;
156 | wire [D_WID-1:0] dout14 ;
157 | wire [D_WID-1:0] dout15 ;
158 | wire [D_WID-1:0] dout16 ;
159 | wire [D_WID-1:0] dout17 ;
160 | wire [D_WID-1:0] dout18 ;
161 | wire [D_WID-1:0] dout19 ;
162 | wire [D_WID-1:0] dout20 ;
163 | wire [D_WID-1:0] dout21 ;
164 | wire [D_WID-1:0] dout22 ;
165 | wire [D_WID-1:0] dout23 ;
166 | wire [D_WID-1:0] dout24 ;
167 | wire [D_WID-1:0] dout25 ;
168 | wire [D_WID-1:0] dout26 ;
169 | wire [D_WID-1:0] dout27 ;
170 | wire [D_WID-1:0] dout28 ;
171 | wire [D_WID-1:0] dout29 ;
172 | wire [D_WID-1:0] dout30 ;
173 | wire [D_WID-1:0] dout31 ;
174 | wire [D_WID-1:0] dout32 ;
175 | wire [D_WID-1:0] dout33 ;
176 | wire [D_WID-1:0] dout34 ;
177 | wire [D_WID-1:0] dout35 ;
178 |
179 | reg [35:0] sync_dly ;
180 | reg [D_WID-1:0] data_dly ;
181 | reg [5:0] sync_count ;
182 |
183 | wire [3:0] fsm ;
184 | wire sync_in6 ;
185 |
186 | assign fsm = fsm_state ;
187 | assign sync_in6 = (sync_count == 6'h0) & sync_in;
188 |
189 | always @ (posedge clk or negedge reset_n)
190 | begin : sync_count_r
191 | if(!reset_n)
192 | sync_count <= #1 6'h0;
193 | else if(sync_in)
194 | begin if(sync_count == 6'd35)
195 | sync_count <= #1 6'h0;
196 | else
197 | sync_count <= #1 sync_count + 1'b1;
198 | end
199 | end
200 |
201 | always @ (posedge clk or negedge reset_n)
202 | begin : sync_dly_r
203 | if(!reset_n)
204 | sync_dly <= #1 36'h0;
205 | else if(sync_in)
206 | sync_dly <= #1 { sync_dly[34:0],sync_in6 };
207 | else
208 | sync_dly <= #1 36'h0;
209 | end
210 |
211 | always @ (posedge clk or negedge reset_n)
212 | begin : data_dly_r
213 | if(!reset_n)
214 | data_dly <= #1 {D_WID{1'b0}};
215 | else
216 | data_dly <= #1 data_in;
217 | end
218 |
219 | vtc_cell cel_00(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 0]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr00),.ram_wr(wr00),.ram_d(din00));
220 | vtc_cell cel_01(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 1]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr01),.ram_wr(wr01),.ram_d(din01));
221 | vtc_cell cel_02(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 2]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr02),.ram_wr(wr02),.ram_d(din02));
222 | vtc_cell cel_03(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 3]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr03),.ram_wr(wr03),.ram_d(din03));
223 | vtc_cell cel_04(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 4]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr04),.ram_wr(wr04),.ram_d(din04));
224 | vtc_cell cel_05(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 5]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr05),.ram_wr(wr05),.ram_d(din05));
225 | vtc_cell cel_06(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 6]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr06),.ram_wr(wr06),.ram_d(din06));
226 | vtc_cell cel_07(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 7]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr07),.ram_wr(wr07),.ram_d(din07));
227 | vtc_cell cel_08(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 8]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr08),.ram_wr(wr08),.ram_d(din08));
228 | vtc_cell cel_09(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[ 9]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr09),.ram_wr(wr09),.ram_d(din09));
229 | vtc_cell cel_10(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[10]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr10),.ram_wr(wr10),.ram_d(din10));
230 | vtc_cell cel_11(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[11]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr11),.ram_wr(wr11),.ram_d(din11));
231 | vtc_cell cel_12(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[12]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr12),.ram_wr(wr12),.ram_d(din12));
232 | vtc_cell cel_13(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[13]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr13),.ram_wr(wr13),.ram_d(din13));
233 | vtc_cell cel_14(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[14]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr14),.ram_wr(wr14),.ram_d(din14));
234 | vtc_cell cel_15(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[15]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr15),.ram_wr(wr15),.ram_d(din15));
235 | vtc_cell cel_16(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[16]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr16),.ram_wr(wr16),.ram_d(din16));
236 | vtc_cell cel_17(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[17]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr17),.ram_wr(wr17),.ram_d(din17));
237 | vtc_cell cel_18(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[18]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr18),.ram_wr(wr18),.ram_d(din18));
238 | vtc_cell cel_19(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[19]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr19),.ram_wr(wr19),.ram_d(din19));
239 | vtc_cell cel_20(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[20]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr20),.ram_wr(wr20),.ram_d(din20));
240 | vtc_cell cel_21(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[21]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr21),.ram_wr(wr21),.ram_d(din21));
241 | vtc_cell cel_22(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[22]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr22),.ram_wr(wr22),.ram_d(din22));
242 | vtc_cell cel_23(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[23]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr23),.ram_wr(wr23),.ram_d(din23));
243 | vtc_cell cel_24(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[24]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr24),.ram_wr(wr24),.ram_d(din24));
244 | vtc_cell cel_25(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[25]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr25),.ram_wr(wr25),.ram_d(din25));
245 | vtc_cell cel_26(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[26]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr26),.ram_wr(wr26),.ram_d(din26));
246 | vtc_cell cel_27(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[27]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr27),.ram_wr(wr27),.ram_d(din27));
247 | vtc_cell cel_28(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[28]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr28),.ram_wr(wr28),.ram_d(din28));
248 | vtc_cell cel_29(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[29]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr29),.ram_wr(wr29),.ram_d(din29));
249 | vtc_cell cel_30(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[30]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr30),.ram_wr(wr30),.ram_d(din30));
250 | vtc_cell cel_31(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[31]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr31),.ram_wr(wr31),.ram_d(din31));
251 | vtc_cell cel_32(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[32]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr32),.ram_wr(wr32),.ram_d(din32));
252 | vtc_cell cel_33(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[33]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr33),.ram_wr(wr33),.ram_d(din33));
253 | vtc_cell cel_34(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[34]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr34),.ram_wr(wr34),.ram_d(din34));
254 | vtc_cell cel_35(.clk(clk),.reset_n(reset_n),.sync_in(sync_dly[35]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr35),.ram_wr(wr35),.ram_d(din35));
255 | //vtc_cell cel_06(.clk(clk),reset_n(reset_n),.sync_in(sync_dly[ 6]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr06),.ram_wr(wr06),.ram_d(din06));
256 | //vtc_cell cel_07(.clk(clk),reset_n(reset_n),.sync_in(sync_dly[ 7]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr07),.ram_wr(wr07),.ram_d(din07));
257 | //vtc_cell cel_08(.clk(clk),reset_n(reset_n),.sync_in(sync_dly[ 8]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr08),.ram_wr(wr08),.ram_d(din08));
258 | //vtc_cell cel_09(.clk(clk),reset_n(reset_n),.sync_in(sync_dly[ 9]),.data_in(data_dly),.fsm(fsm),.ram_addr(addr09),.ram_wr(wr09),.ram_d(din09));
259 |
260 | sram256x8 u_ram00(.CLK(clk),.A(addr00),.CEN(1'b0),.WEN(wr00),.D(din00),.Q(dout00));
261 | sram256x8 u_ram01(.CLK(clk),.A(addr01),.CEN(1'b0),.WEN(wr01),.D(din01),.Q(dout01));
262 | sram256x8 u_ram02(.CLK(clk),.A(addr02),.CEN(1'b0),.WEN(wr02),.D(din02),.Q(dout02));
263 | sram256x8 u_ram03(.CLK(clk),.A(addr03),.CEN(1'b0),.WEN(wr03),.D(din03),.Q(dout03));
264 | sram256x8 u_ram04(.CLK(clk),.A(addr04),.CEN(1'b0),.WEN(wr04),.D(din04),.Q(dout04));
265 | sram256x8 u_ram05(.CLK(clk),.A(addr05),.CEN(1'b0),.WEN(wr05),.D(din05),.Q(dout05));
266 | sram256x8 u_ram06(.CLK(clk),.A(addr06),.CEN(1'b0),.WEN(wr06),.D(din06),.Q(dout06));
267 | sram256x8 u_ram07(.CLK(clk),.A(addr07),.CEN(1'b0),.WEN(wr07),.D(din07),.Q(dout07));
268 | sram256x8 u_ram08(.CLK(clk),.A(addr08),.CEN(1'b0),.WEN(wr08),.D(din08),.Q(dout08));
269 | sram256x8 u_ram09(.CLK(clk),.A(addr09),.CEN(1'b0),.WEN(wr09),.D(din09),.Q(dout09));
270 | sram256x8 u_ram10(.CLK(clk),.A(addr10),.CEN(1'b0),.WEN(wr10),.D(din00),.Q(dout10));
271 | sram256x8 u_ram11(.CLK(clk),.A(addr11),.CEN(1'b0),.WEN(wr11),.D(din01),.Q(dout11));
272 | sram256x8 u_ram12(.CLK(clk),.A(addr12),.CEN(1'b0),.WEN(wr12),.D(din02),.Q(dout12));
273 | sram256x8 u_ram13(.CLK(clk),.A(addr13),.CEN(1'b0),.WEN(wr13),.D(din03),.Q(dout13));
274 | sram256x8 u_ram14(.CLK(clk),.A(addr14),.CEN(1'b0),.WEN(wr14),.D(din04),.Q(dout14));
275 | sram256x8 u_ram15(.CLK(clk),.A(addr15),.CEN(1'b0),.WEN(wr15),.D(din05),.Q(dout15));
276 | sram256x8 u_ram16(.CLK(clk),.A(addr16),.CEN(1'b0),.WEN(wr16),.D(din06),.Q(dout16));
277 | sram256x8 u_ram17(.CLK(clk),.A(addr17),.CEN(1'b0),.WEN(wr17),.D(din07),.Q(dout17));
278 | sram256x8 u_ram18(.CLK(clk),.A(addr18),.CEN(1'b0),.WEN(wr18),.D(din08),.Q(dout18));
279 | sram256x8 u_ram19(.CLK(clk),.A(addr19),.CEN(1'b0),.WEN(wr19),.D(din09),.Q(dout19));
280 | sram256x8 u_ram20(.CLK(clk),.A(addr20),.CEN(1'b0),.WEN(wr20),.D(din00),.Q(dout20));
281 | sram256x8 u_ram21(.CLK(clk),.A(addr21),.CEN(1'b0),.WEN(wr21),.D(din01),.Q(dout21));
282 | sram256x8 u_ram22(.CLK(clk),.A(addr22),.CEN(1'b0),.WEN(wr22),.D(din02),.Q(dout22));
283 | sram256x8 u_ram23(.CLK(clk),.A(addr23),.CEN(1'b0),.WEN(wr23),.D(din03),.Q(dout23));
284 | sram256x8 u_ram24(.CLK(clk),.A(addr24),.CEN(1'b0),.WEN(wr24),.D(din04),.Q(dout24));
285 | sram256x8 u_ram25(.CLK(clk),.A(addr25),.CEN(1'b0),.WEN(wr25),.D(din05),.Q(dout25));
286 | sram256x8 u_ram26(.CLK(clk),.A(addr26),.CEN(1'b0),.WEN(wr26),.D(din06),.Q(dout26));
287 | sram256x8 u_ram27(.CLK(clk),.A(addr27),.CEN(1'b0),.WEN(wr27),.D(din07),.Q(dout27));
288 | sram256x8 u_ram28(.CLK(clk),.A(addr28),.CEN(1'b0),.WEN(wr28),.D(din08),.Q(dout28));
289 | sram256x8 u_ram29(.CLK(clk),.A(addr29),.CEN(1'b0),.WEN(wr29),.D(din09),.Q(dout29));
290 | sram256x8 u_ram30(.CLK(clk),.A(addr30),.CEN(1'b0),.WEN(wr30),.D(din30),.Q(dout30));
291 | sram256x8 u_ram31(.CLK(clk),.A(addr31),.CEN(1'b0),.WEN(wr31),.D(din31),.Q(dout31));
292 | sram256x8 u_ram32(.CLK(clk),.A(addr32),.CEN(1'b0),.WEN(wr32),.D(din32),.Q(dout32));
293 | sram256x8 u_ram33(.CLK(clk),.A(addr33),.CEN(1'b0),.WEN(wr33),.D(din33),.Q(dout33));
294 | sram256x8 u_ram34(.CLK(clk),.A(addr34),.CEN(1'b0),.WEN(wr34),.D(din34),.Q(dout34));
295 | sram256x8 u_ram35(.CLK(clk),.A(addr35),.CEN(1'b0),.WEN(wr35),.D(din35),.Q(dout35));
296 |
297 | endmodule
298 |
--------------------------------------------------------------------------------
/ldpc_rtl/lr_cell.v:
--------------------------------------------------------------------------------
1 | module lr_cell(
2 | clk,
3 | reset_n,
4 | iter_0,
5 | cnu_in,
6 | cycle ,
7 | cnu0_q,
8 | cnu1_q,
9 | cnu2_q,
10 | cnu3_q,
11 | cnu4_q,
12 | cnu5_q,
13 | mem_in,
14 | mem_out,
15 | cnu0_d,
16 | cnu1_d,
17 | cnu2_d,
18 | cnu3_d,
19 | cnu4_d,
20 | cnu5_d
21 | );
22 |
23 | //Parameter
24 | parameter D_WID = 8;
25 |
26 | //Input ports
27 | input clk ;
28 | input reset_n ;
29 | input iter_0 ;
30 | input [6:0] cnu_in ;
31 | input [1:0] cycle ;
32 | input [2*D_WID+9:0] cnu0_q ;
33 | input [2*D_WID+9:0] cnu1_q ;
34 | input [2*D_WID+9:0] cnu2_q ;
35 | input [2*D_WID+9:0] cnu3_q ;
36 | input [2*D_WID+9:0] cnu4_q ;
37 | input [2*D_WID+9:0] cnu5_q ;
38 | input [4*D_WID+19:0] mem_out ;
39 |
40 | output [2*D_WID+9:0] cnu0_d ;
41 | output [2*D_WID+9:0] cnu1_d ;
42 | output [2*D_WID+9:0] cnu2_d ;
43 | output [2*D_WID+9:0] cnu3_d ;
44 | output [2*D_WID+9:0] cnu4_d ;
45 | output [2*D_WID+9:0] cnu5_d ;
46 | output [4*D_WID+19:0] mem_in ;
47 |
48 | reg [4*D_WID+19:0] mem_in ;
49 | reg [4*D_WID+19:0] cnu_tmp0 ;
50 | reg [4*D_WID+19:0] cnu_tmp1 ;
51 | reg [2*D_WID+9:0] cnu0_d ;
52 | reg [2*D_WID+9:0] cnu1_d ;
53 | reg [2*D_WID+9:0] cnu2_d ;
54 | reg [2*D_WID+9:0] cnu3_d ;
55 | reg [2*D_WID+9:0] cnu4_d ;
56 | reg [2*D_WID+9:0] cnu5_d ;
57 | reg cnu_dly ;
58 |
59 | always @ (posedge clk or negedge reset_n)
60 | begin : cnu_dly_r
61 | if(!reset_n)
62 | cnu_dly <= 1'b0;
63 | else
64 | cnu_dly <= #1 cnu_in[6];
65 | end
66 |
67 | always @ (posedge clk or negedge reset_n)
68 | begin : mem_in_r
69 | if(!reset_n)
70 | mem_in <= #1 52'h0;
71 | else if(cnu_in[5])
72 | mem_in <= #1 {cnu0_q, cnu1_q};
73 | else if(cnu_in[6])
74 | mem_in <= #1 cnu_tmp0;
75 | else if(cnu_dly)
76 | mem_in <= #1 cnu_tmp1;
77 | end
78 |
79 | always @ (posedge clk or negedge reset_n)
80 | begin : cnu_tmp0_r
81 | if(!reset_n)
82 | cnu_tmp0 <= #1 52'h0;
83 | else if(cnu_in[5])
84 | cnu_tmp0 <= #1 {cnu2_q, cnu3_q};
85 | end
86 |
87 | always @ (posedge clk or negedge reset_n)
88 | begin : cnu_tmp1_r
89 | if(!reset_n)
90 | cnu_tmp1 <= #1 52'h0;
91 | else if(cnu_in[5])
92 | cnu_tmp1 <= #1 {cnu4_q, cnu5_q};
93 | end
94 |
95 | always @ (posedge clk or negedge reset_n)
96 | begin : cnu0_d_r
97 | if(!reset_n)
98 | cnu0_d <= #1 26'h0;
99 | else if((cycle == 2'b01) & !iter_0)
100 | cnu0_d <= #1 mem_out[4*D_WID+19:2*D_WID+10];
101 | end
102 |
103 | always @ (posedge clk or negedge reset_n)
104 | begin : cnu1_d_r
105 | if(!reset_n)
106 | cnu1_d <= #1 26'h0;
107 | else if((cycle == 2'b01) & !iter_0)
108 | cnu1_d <= #1 mem_out[2*D_WID+9:0];
109 | end
110 |
111 | always @ (posedge clk or negedge reset_n)
112 | begin : cnu2_d_r
113 | if(!reset_n)
114 | cnu2_d <= #1 26'h0;
115 | else if((cycle == 2'b10) & !iter_0)
116 | cnu2_d <= #1 mem_out[4*D_WID+19:2*D_WID+10];
117 | end
118 |
119 | always @ (posedge clk or negedge reset_n)
120 | begin : cnu3_d_r
121 | if(!reset_n)
122 | cnu3_d <= #1 26'h0;
123 | else if((cycle == 2'b10) & !iter_0)
124 | cnu3_d <= #1 mem_out[2*D_WID+9:0];
125 | end
126 |
127 |
128 | always @ (posedge clk or negedge reset_n)
129 | begin : cnu4_d_r
130 | if(!reset_n)
131 | cnu4_d <= #1 26'h0;
132 | else if((cycle == 2'b11) & !iter_0)
133 | cnu4_d <= #1 mem_out[4*D_WID+19:2*D_WID+10];
134 | end
135 |
136 | always @ (posedge clk or negedge reset_n)
137 | begin : cnu5_d_r
138 | if(!reset_n)
139 | cnu5_d <= #1 26'h0;
140 | else if((cycle == 2'b11) & !iter_0)
141 | cnu5_d <= #1 mem_out[2*D_WID+9:0];
142 | end
143 |
144 | endmodule
145 |
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/ldpc_rtl/qpsk12/Eb_N0_dB.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/qpsk12/Eb_N0_dB.mat
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/ldpc_rtl/qpsk12/nBitErr.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/qpsk12/nBitErr.mat
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/ldpc_rtl/qpsk12/readme.md:
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1 |
2 |
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/ldpc_rtl/qpsk12/simBer.mat:
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https://raw.githubusercontent.com/sudhamshu091/ldpc-encoder-decoder/677decbff246b96c25923ab51f1dc08d2ac512be/ldpc_rtl/qpsk12/simBer.mat
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/ldpc_rtl/rd_cell.v:
--------------------------------------------------------------------------------
1 | module rd_cell(
2 | clk,
3 | reset_n,
4 | rd_en,
5 | cycle,
6 | base_addr,
7 | addr_offset,
8 | out_addr,
9 | out_en,
10 | rd_addr
11 | );
12 |
13 | parameter A_WID = 8;
14 |
15 | //Input ports
16 | input clk ;
17 | input reset_n ;
18 | input rd_en ;
19 | input [1:0] cycle ;
20 | input [A_WID-1:0] base_addr ;
21 | input [3*A_WID-1:0] addr_offset;
22 | input [A_WID-1:0] out_addr ;
23 | input out_en ;
24 |
25 | output [A_WID-1:0] rd_addr ;
26 |
27 | reg [A_WID-1:0] rd_addr ;
28 | reg [A_WID-1:0] addr_offset1;
29 |
30 | always @ (posedge clk or negedge reset_n)
31 | begin : rd_addr_r
32 | if(!reset_n)
33 | rd_addr <= #1 8'h0;
34 | else if(rd_en)
35 | rd_addr <= #1 base_addr + addr_offset1;
36 | else if(out_en)
37 | rd_addr <= #1 out_addr;
38 | else
39 | rd_addr <= #1 8'h0;
40 | end
41 |
42 | always @ (addr_offset or cycle)
43 | begin : addr_offset_r
44 | case(cycle)
45 | 2'b01: addr_offset1 = addr_offset[3*A_WID-1:2*A_WID];
46 | 2'b10: addr_offset1 = addr_offset[2*A_WID-1:A_WID];
47 | 2'b11: addr_offset1 = addr_offset[A_WID-1:0];
48 | default: addr_offset1 = 8'h0;
49 | endcase
50 | end
51 |
52 | endmodule
--------------------------------------------------------------------------------
/ldpc_rtl/rd_seq.v:
--------------------------------------------------------------------------------
1 | module rd_seq(
2 | clk,
3 | reset_n,
4 | rate,
5 | fsm,
6 | out_addr,
7 | out_rd_en,
8 | out_rd_sel
9 | );
10 |
11 | parameter A_WID = 8;
12 |
13 | //Input ports
14 | input clk ;
15 | input reset_n ;
16 | input rate ;
17 | input [3:0] fsm ;
18 |
19 | output [A_WID-1:0] out_addr ;
20 | output out_rd_en ;
21 | output [35:0] out_rd_sel ;
22 |
23 | reg [12:0] out_counter;
24 | reg [35:0] out_rd_sel ;
25 | reg out_rd_en ;
26 | reg [35:0] data_out_r ;
27 | reg [A_WID-1:0] out_addr ;
28 |
29 | wire [12:0] out_max ;
30 | wire out_end ;
31 | wire [13:0] data_out ;
32 |
33 | assign out_max = rate ? 'd6911: 'd4607;
34 | assign out_end = out_counter == out_max;
35 |
36 | always @ (posedge clk or negedge reset_n)
37 | begin : out_counter_r
38 | if(!reset_n)
39 | out_counter <= #1 13'h0;
40 | else if(fsm[3]) begin
41 | if(out_end)
42 | out_counter <= #1 13'h0;
43 | else
44 | out_counter <= #1 out_counter + 1'b1;
45 | end
46 | end
47 |
48 | out_table u_out_table(
49 | .clk (clk),
50 | .addr (out_counter),
51 | .q (data_out)
52 | );
53 |
54 | always @ (posedge clk or negedge reset_n)
55 | begin : out_addr_r
56 | if(!reset_n)
57 | out_addr <= #1 {A_WID{1'b0}};
58 | else
59 | out_addr <= #1 data_out[A_WID+5:6];
60 | end
61 |
62 | always @ (posedge clk or negedge reset_n)
63 | begin : out_rd_r
64 | if(!reset_n)
65 | out_rd_sel <= #1 36'h0;
66 | else if(fsm[3])
67 | out_rd_sel <= #1 data_out_r;
68 | else
69 | out_rd_sel <= #1 36'h0;
70 | end
71 |
72 | always @ (posedge clk or negedge reset_n)
73 | begin : out_rd_en_r
74 | if(!reset_n)
75 | out_rd_en <= #1 1'b0;
76 | else
77 | out_rd_en <= #1 fsm[3];
78 | end
79 |
80 | always @ (data_out[5:0])
81 | case(data_out[5:0])
82 | 6'd0 : data_out_r = 36'h0_0000_0001;
83 | 6'd1 : data_out_r = 36'h0_0000_0002;
84 | 6'd2 : data_out_r = 36'h0_0000_0004;
85 | 6'd3 : data_out_r = 36'h0_0000_0008;
86 | 6'd4 : data_out_r = 36'h0_0000_0010;
87 | 6'd5 : data_out_r = 36'h0_0000_0020;
88 | 6'd6 : data_out_r = 36'h0_0000_0040;
89 | 6'd7 : data_out_r = 36'h0_0000_0080;
90 | 6'd8 : data_out_r = 36'h0_0000_0100;
91 | 6'd9 : data_out_r = 36'h0_0000_0200;
92 | 6'd10 : data_out_r = 36'h0_0000_0400;
93 | 6'd11 : data_out_r = 36'h0_0000_0800;
94 | 6'd12 : data_out_r = 36'h0_0000_1000;
95 | 6'd13 : data_out_r = 36'h0_0000_2000;
96 | 6'd14 : data_out_r = 36'h0_0000_4000;
97 | 6'd15 : data_out_r = 36'h0_0000_8000;
98 | 6'd16 : data_out_r = 36'h0_0001_0000;
99 | 6'd17 : data_out_r = 36'h0_0002_0000;
100 | 6'd18 : data_out_r = 36'h0_0004_0000;
101 | 6'd19 : data_out_r = 36'h0_0008_0000;
102 | 6'd20 : data_out_r = 36'h0_0010_0000;
103 | 6'd21 : data_out_r = 36'h0_0020_0000;
104 | 6'd22 : data_out_r = 36'h0_0040_0000;
105 | 6'd23 : data_out_r = 36'h0_0080_0000;
106 | 6'd24 : data_out_r = 36'h0_0100_0000;
107 | 6'd25 : data_out_r = 36'h0_0200_0000;
108 | 6'd26 : data_out_r = 36'h0_0400_0000;
109 | 6'd27 : data_out_r = 36'h0_0800_0000;
110 | 6'd28 : data_out_r = 36'h0_1000_0000;
111 | 6'd29 : data_out_r = 36'h0_2000_0000;
112 | 6'd30 : data_out_r = 36'h0_4000_0000;
113 | 6'd31 : data_out_r = 36'h0_8000_0000;
114 | 6'd32 : data_out_r = 36'h1_0000_0000;
115 | 6'd33 : data_out_r = 36'h2_0000_0000;
116 | 6'd34 : data_out_r = 36'h4_0000_0000;
117 | 6'd35 : data_out_r = 36'h8_0000_0000;
118 | default: data_out_r =36'h0;
119 | endcase
120 | endmodule
121 |
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/ldpc_rtl/readme.md:
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1 |
2 |
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/ldpc_rtl/ref/QPSK_TX.m:
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1 | %QPSK Transmitter(QPSK_TX.m)
2 | %JC 6/5/05
3 | %Run from editor debug(F5)
4 | %m-file for simulating a QPSK transmitter by modulating with a pseudo
5 | %random bit stream. A serial to parallel conversion of the pseudo random
6 | %bit stream is performed with mapping of two bits per symbol. A cosine and
7 | %sine carrier is configured and the I and Q symbols modulate these
8 | %carriers. The I and Q carriers are combined and time and frequency domain
9 | %plots are provided showing key waveforms at various positions in the QPSK
10 | %transmitter. The simulation uses a serial "passband" approach. Notes and
11 | %a reference are provided at the end of the m-file.
12 | %===================================================================
13 | clear;
14 | fcarr=2e3; % Carrier frequency(Hz)
15 | N=10; % Number of data bits(bit rate)
16 | fs=16*1e3; % Sampling frequency
17 | Fn=fs/2; % Nyquist frequency
18 | Ts=1/fs; % Sampling time = 1/fs
19 | T=1/N; % Bit time
20 | randn('state',0); % Keeps PRBS from changing on reruns
21 | td=[0:Ts:(N*T)-Ts]';% Time vector(data)(transpose)
22 | %===================================================================
23 | % The Transmitter.
24 | %===================================================================
25 | data=sign(randn(N,1))';%transpose
26 | data1=ones(T/Ts,1)*data;
27 | data2=data1(:);
28 |
29 | %Serial To Parallel (alternating)
30 | tiq = [0:Ts*2:(N*T)-Ts]';% Time vector for I and Q symbols(transpose)
31 |
32 | bs1=data(1:2:length(data));%odd
33 | symbols=ones(T/Ts,1)*bs1;
34 | Isymbols=symbols(:);%I_waveform
35 |
36 | bs2=data(2:2:length(data));%even
37 | symbols1=ones(T/Ts,1)*bs2;
38 | Qsymbols=symbols1(:);%Q_waveform
39 |
40 | %generate carrier waves
41 | %cosine and sine wave
42 | %2 pi fc t is written as below
43 | twopi_fc_t=(1:fs/2)*2*pi*fcarr/fs;
44 | a=1;
45 | %phi=45*pi/180
46 | phi=0;
47 | cs_t = a * cos(twopi_fc_t + phi);
48 | sn_t = a * sin(twopi_fc_t + phi);
49 |
50 | cs_t=cs_t';%transpose
51 | sn_t=sn_t';
52 | si=cs_t.*Isymbols;
53 | sq=sn_t.*Qsymbols;
54 | sumiq=si+sq;
55 | sumiq=.7*sumiq;%reduce gain to keep output at +/- one
56 | %======================================================================
57 | %Plots
58 | %======================================================================
59 | figure(1)
60 | subplot(3,2,1)
61 | plot(td,data2)
62 | axis([0 1 -2 2]);
63 | grid
64 | xlabel(' Time')
65 | ylabel('Amplitude')
66 | title('Input Data')
67 |
68 | subplot(3,2,3)
69 | plot(tiq,Isymbols)
70 | axis([0 1 -2 2]);
71 | grid
72 | xlabel(' Time')
73 | ylabel('Amplitude')
74 | title('I Channel(two bits/symbol) Data')
75 |
76 | subplot(3,2,5)
77 | plot(tiq,Qsymbols)
78 | axis([0 1 -2 2]);
79 | grid
80 | xlabel(' Time')
81 | ylabel('Amplitude')
82 | title('Q Channel(two bits/symbol) Data')
83 |
84 | subplot(3,2,2)
85 | plot(tiq,si)
86 | axis([.595 .605 -2 2]);
87 | grid
88 | xlabel(' Time')
89 | ylabel('Amplitude')
90 | title('I Channel Modulated Waveform')
91 |
92 | subplot(3,2,4)
93 | plot(tiq,sq)
94 | axis([.595 .605 -2 2]);
95 | grid
96 | xlabel(' Time')
97 | ylabel('Amplitude')
98 | title('Q Channel Modulated Waveform')
99 |
100 | subplot(3,2,6)
101 | plot(tiq,sumiq)
102 | axis([.595 .605 -2 2]);
103 | grid
104 | xlabel(' Time')
105 | ylabel('Amplitude')
106 | title('QPSK Output Waveform')
107 | %========================================================================
108 | %Take FFT of modulated carrier
109 | %========================================================================
110 | y=sumiq;
111 | NFFY=2.^(ceil(log(length(y))/log(2)));
112 | FFTY=fft(y,NFFY);%pad with zeros
113 | NumUniquePts=ceil((NFFY+1)/2);
114 | FFTY=FFTY(1:NumUniquePts);
115 | MY=abs(FFTY);
116 | MY=MY*2;
117 | MY(1)=MY(1)/2;
118 | MY(length(MY))=MY(length(MY))/2;
119 | MY=MY/length(y);
120 | f1=(0:NumUniquePts-1)*2*Fn/NFFY;
121 | %=========================================================================
122 | %Plot frequency domain
123 | %=========================================================================
124 | figure(2)
125 | subplot(3,1,1); plot(f1,MY);xlabel('');ylabel('AMPLITUDE');
126 | axis([1500 2500 -.5 2]);%zoom in/out
127 | title('Frequency domain plots');
128 | grid
129 |
130 | subplot(3,1,2); plot(f1,20*log10(abs(MY).^2));xlabel('FREQUENCY(Hz)');ylabel('DB');
131 | axis([1500 2500 -100 10]);
132 | grid
133 | title('Modulated QPSK carrier')
134 |
135 | %NOTE
136 | %Serial to parallel conversion of a serial bit stream and mapping of
137 | %two bits to a symbol can sometimes be confusing. I will try and explain
138 | %with an example.
139 | %Suppose you have a serial bit stream of ten 0 0 1 1 0 1 1 0 1 1 even # of bits
140 | %odd bits 0 1 0 1 1
141 | %even bits 0 1 1 0 1
142 |
143 | %The odd bits are the I Channel Data at one half the original serial bit stream
144 | %bit rate. Notice that the amplitudes are +/- one as shown in figure 1.
145 | %The possible combinations are -1 -1, 1 1, -1 1, 1 -1. The amplitudes, in
146 | %theory, should be held at +/- 0.707 to keep the summed output of the
147 | %QPSK transmitter at a constant amplitude of +/- one.
148 | %The even bits are the Q Channel Data at one half the original serial bit
149 | %stream bit rate. Same info as above.
150 |
151 | %A good reference discussing a QPSK Transmitter and look up tables and Gray
152 | %coding can be found at http://cnx.rice.edu/content/m10042/latest/
153 |
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/ldpc_rtl/ref/script_16qam_gray_mapping_bit_error_rate.m:
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1 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2 | % All rights reserved by Krishna Pillai, http://www.dsplog.com
3 | % The file may not be re-distributed without explicit authorization
4 | % from Krishna Pillai.
5 | % Checked for proper operation with Octave Version 3.0.0
6 | % Author : Krishna Pillai
7 | % Email : krishna@dsplog.com
8 | % Version : 1.0
9 | % Date : 05 June 2008
10 | % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
11 |
12 | % Bit Error Rate for 16-QAM modulation using Gray modulation mapping
13 |
14 | clear
15 | N = 10^5; % number of symbols
16 | M = 16; % constellation size
17 | k = log2(M); % bits per symbol
18 |
19 | % defining the real and imaginary PAM constellation
20 | % for 16-QAM
21 | alphaRe = [-(2*sqrt(M)/2-1):2:-1 1:2:2*sqrt(M)/2-1];
22 | alphaIm = [-(2*sqrt(M)/2-1):2:-1 1:2:2*sqrt(M)/2-1];
23 | k_16QAM = 1/sqrt(10);
24 |
25 | Eb_N0_dB = [0:15]; % multiple Es/N0 values
26 | Es_N0_dB = Eb_N0_dB + 10*log10(k);
27 |
28 | % Mapping for binary <--> Gray code conversion
29 | ref = [0:k-1];
30 | map = bitxor(ref,floor(ref/2));
31 | [tt ind] = sort(map);
32 |
33 | for ii = 1:length(Eb_N0_dB)
34 |
35 | % symbol generation
36 | % ------------------
37 | ipBit = rand(1,N*k,1)>0.5; % random 1's and 0's
38 | ipBitReshape = reshape(ipBit,k,N).';
39 | bin2DecMatrix = ones(N,1)*(2.^[(k/2-1):-1:0]) ; % conversion from binary to decimal
40 | % real
41 | ipBitRe = ipBitReshape(:,[1:k/2]);
42 | ipDecRe = sum(ipBitRe.*bin2DecMatrix,2);
43 | ipGrayDecRe = bitxor(ipDecRe,floor(ipDecRe/2));
44 | % imaginary
45 | ipBitIm = ipBitReshape(:,[k/2+1:k]);
46 | ipDecIm = sum(ipBitIm.*bin2DecMatrix,2);
47 | ipGrayDecIm = bitxor(ipDecIm,floor(ipDecIm/2));
48 | % mapping the Gray coded symbols into constellation
49 | modRe = alphaRe(ipGrayDecRe+1);
50 | modIm = alphaIm(ipGrayDecIm+1);
51 | % complex constellation
52 | mod = modRe + j*modIm;
53 | s = k_16QAM*mod; % normalization of transmit power to one
54 |
55 | % noise
56 | % -----
57 | n = 1/sqrt(2)*[randn(1,N) + j*randn(1,N)]; % white guassian noise, 0dB variance
58 |
59 | y = s + 10^(-Es_N0_dB(ii)/20)*n; % additive white gaussian noise
60 |
61 | % demodulation
62 | % ------------
63 | y_re = real(y)/k_16QAM; % real part
64 | y_im = imag(y)/k_16QAM; % imaginary part
65 |
66 | % rounding to the nearest alphabet
67 | ipHatRe = 2*floor(y_re/2)+1;
68 | ipHatRe(find(ipHatRe>max(alphaRe))) = max(alphaRe);
69 | ipHatRe(find(ipHatRemax(alphaIm))) = max(alphaIm);
72 | ipHatIm(find(ipHatIm