├── 1:2 mux ├── 2mux ├── 2mux.v ├── 2mux.vcd └── 2mux_tb.v ├── 2:4 demux ├── demux ├── demux.v ├── demux.vcd └── demux_tb.v ├── 2:4 mux ├── 4mux ├── 4mux.v ├── 4mux.vcd └── 4mux_tb.v ├── 4:2 decoder ├── decoder ├── decoder.v ├── decoder.vcd └── decoder_tb.v ├── 8-bit Booth Multiplier ├── Booth_Multiplier.vcd ├── GTK Output snaps │ ├── Negative, Negative.png │ ├── Negative, Positive.png │ ├── Positive, Negative.png │ └── Positive, Positive.png ├── bit ├── bit.v └── bit_tb.v ├── Control Logic ├── alu.v ├── lib.v ├── mproc.v ├── mproc_mem.v └── pc.v ├── README.md ├── week-1 ├── and_gate │ ├── and.v │ ├── and_tb.v │ └── and_tb.vcd ├── nand_gate │ ├── nand.v │ ├── nand_tb.v │ └── nand_tb.vcd ├── nor_gate │ ├── nor.v │ ├── nor_tb.v │ └── nor_tb.vcd ├── not_gate │ ├── not.v │ ├── not_tb.v │ └── not_tb.vcd ├── or_gate │ ├── or.v │ ├── or_tb.v │ └── or_tb.vcd ├── xnor_gate │ ├── xnor.v │ ├── xnor_tb.v │ └── xnor_tb.vcd └── xor_gate │ ├── xor.v │ ├── xor_tb.v │ └── xor_tb.vcd ├── week-2 ├── circuit-1 │ ├── circuit │ ├── circuit-1.png │ ├── circuit1.v │ ├── circuit1.vcd │ └── tb_circuit1.v ├── circuit-2 │ ├── circuit-2.png │ ├── circuit1 │ ├── circuit2.v │ ├── circuit2.vcd │ └── tb_circuit2.v ├── full_adder │ ├── full_adder │ ├── full_adder.v │ ├── full_adder_tb.v │ └── full_adder_tb.vcd ├── half_adder │ ├── half_adder │ ├── half_adder.v │ ├── half_adder_tb.v │ └── half_adder_tb.vcd └── simple_circuit │ ├── circuit.png │ ├── simple.vcd │ ├── simple_circuit.v │ └── tb_simple_circuit.v ├── week-3 ├── ALU.jpg ├── alu ├── alu.v ├── lib.v ├── tb_alu.v └── tb_alu.vcd ├── week-4 ├── alu.v ├── lib.v ├── reg_alu.v ├── tb_reg_alu.v └── tb_reg_alu.vcd ├── week-5 ├── lib.v ├── pc ├── pc.v ├── tb_pc.v ├── tb_pc.vcd └── vvp_output.png ├── week-6 ├── PC.pdf ├── lib.v ├── pc ├── pc.v ├── tb_pc.v └── tb_pc.vcd └── week-7 ├── Diagram.docx ├── alu.v ├── lib.v ├── mproc.v ├── mproc_mem.v ├── pc.v ├── reg_alu.v └── tb_mproc_mem.v /1:2 mux/2mux: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x55b81f567f90 .scope module, "mux_tb" "mux_tb" 2 1; 11 | .timescale 0 0; 12 | v0x55b81f57e1a0_0 .var "t_a", 0 0; 13 | v0x55b81f57e260_0 .var "t_b", 0 0; 14 | v0x55b81f57e330_0 .net "t_o", 0 0, L_0x55b81f58e820; 1 drivers 15 | v0x55b81f57e430_0 .var "t_s", 0 0; 16 | S_0x55b81f568120 .scope module, "mux" "mux2" 2 5, 3 1 0, S_0x55b81f567f90; 17 | .timescale 0 0; 18 | .port_info 0 /INPUT 1 "i0"; 19 | .port_info 1 /INPUT 1 "i1"; 20 | .port_info 2 /INPUT 1 "j"; 21 | .port_info 3 /OUTPUT 1 "o"; 22 | v0x55b81f557a40_0 .net *"_ivl_0", 31 0, L_0x55b81f57e500; 1 drivers 23 | L_0x7fb53e86f018 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 24 | v0x55b81f57db40_0 .net *"_ivl_3", 30 0, L_0x7fb53e86f018; 1 drivers 25 | L_0x7fb53e86f060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 26 | v0x55b81f57dc20_0 .net/2u *"_ivl_4", 31 0, L_0x7fb53e86f060; 1 drivers 27 | v0x55b81f57dd10_0 .net *"_ivl_6", 0 0, L_0x55b81f58e6b0; 1 drivers 28 | v0x55b81f57ddd0_0 .net "i0", 0 0, v0x55b81f57e1a0_0; 1 drivers 29 | v0x55b81f57dee0_0 .net "i1", 0 0, v0x55b81f57e260_0; 1 drivers 30 | v0x55b81f57dfa0_0 .net "j", 0 0, v0x55b81f57e430_0; 1 drivers 31 | v0x55b81f57e060_0 .net "o", 0 0, L_0x55b81f58e820; alias, 1 drivers 32 | L_0x55b81f57e500 .concat [ 1 31 0 0], v0x55b81f57e430_0, L_0x7fb53e86f018; 33 | L_0x55b81f58e6b0 .cmp/eq 32, L_0x55b81f57e500, L_0x7fb53e86f060; 34 | L_0x55b81f58e820 .functor MUXZ 1, v0x55b81f57e260_0, v0x55b81f57e1a0_0, L_0x55b81f58e6b0, C4<>; 35 | .scope S_0x55b81f567f90; 36 | T_0 ; 37 | %vpi_call 2 7 "$dumpfile", "2mux.vcd" {0 0 0}; 38 | %vpi_call 2 8 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55b81f567f90 {0 0 0}; 39 | %end; 40 | .thread T_0; 41 | .scope S_0x55b81f567f90; 42 | T_1 ; 43 | %vpi_call 2 11 "$monitor", v0x55b81f57e1a0_0, v0x55b81f57e260_0, v0x55b81f57e430_0, v0x55b81f57e330_0 {0 0 0}; 44 | %pushi/vec4 1, 0, 1; 45 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 46 | %pushi/vec4 0, 0, 1; 47 | %store/vec4 v0x55b81f57e260_0, 0, 1; 48 | %pushi/vec4 0, 0, 1; 49 | %store/vec4 v0x55b81f57e430_0, 0, 1; 50 | %delay 10, 0; 51 | %pushi/vec4 0, 0, 1; 52 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 53 | %pushi/vec4 1, 0, 1; 54 | %store/vec4 v0x55b81f57e260_0, 0, 1; 55 | %pushi/vec4 0, 0, 1; 56 | %store/vec4 v0x55b81f57e430_0, 0, 1; 57 | %delay 10, 0; 58 | %pushi/vec4 1, 0, 1; 59 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 60 | %pushi/vec4 0, 0, 1; 61 | %store/vec4 v0x55b81f57e260_0, 0, 1; 62 | %pushi/vec4 1, 0, 1; 63 | %store/vec4 v0x55b81f57e430_0, 0, 1; 64 | %delay 10, 0; 65 | %pushi/vec4 1, 0, 1; 66 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 67 | %pushi/vec4 1, 0, 1; 68 | %store/vec4 v0x55b81f57e260_0, 0, 1; 69 | %pushi/vec4 0, 0, 1; 70 | %store/vec4 v0x55b81f57e430_0, 0, 1; 71 | %delay 10, 0; 72 | %pushi/vec4 0, 0, 1; 73 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 74 | %pushi/vec4 0, 0, 1; 75 | %store/vec4 v0x55b81f57e260_0, 0, 1; 76 | %pushi/vec4 1, 0, 1; 77 | %store/vec4 v0x55b81f57e430_0, 0, 1; 78 | %delay 10, 0; 79 | %pushi/vec4 0, 0, 1; 80 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 81 | %pushi/vec4 1, 0, 1; 82 | %store/vec4 v0x55b81f57e260_0, 0, 1; 83 | %pushi/vec4 1, 0, 1; 84 | %store/vec4 v0x55b81f57e430_0, 0, 1; 85 | %delay 10, 0; 86 | %pushi/vec4 1, 0, 1; 87 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 88 | %pushi/vec4 0, 0, 1; 89 | %store/vec4 v0x55b81f57e260_0, 0, 1; 90 | %pushi/vec4 1, 0, 1; 91 | %store/vec4 v0x55b81f57e430_0, 0, 1; 92 | %delay 10, 0; 93 | %pushi/vec4 1, 0, 1; 94 | %store/vec4 v0x55b81f57e1a0_0, 0, 1; 95 | %pushi/vec4 1, 0, 1; 96 | %store/vec4 v0x55b81f57e260_0, 0, 1; 97 | %pushi/vec4 1, 0, 1; 98 | %store/vec4 v0x55b81f57e430_0, 0, 1; 99 | %end; 100 | .thread T_1; 101 | # The file index is used to find the file name in the following table. 102 | :file_names 4; 103 | "N/A"; 104 | ""; 105 | "2mux_tb.v"; 106 | "2mux.v"; 107 | -------------------------------------------------------------------------------- /1:2 mux/2mux.v: -------------------------------------------------------------------------------- 1 | module mux2(input wire i0, i1, j, output wire o); 2 | assign o = (j==0)?i0:i1; 3 | endmodule 4 | -------------------------------------------------------------------------------- /1:2 mux/2mux.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Sep 18 19:16:40 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module mux_tb $end 11 | $var wire 1 ! t_o $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $var reg 1 $ t_s $end 15 | $scope module mux $end 16 | $var wire 1 " i0 $end 17 | $var wire 1 # i1 $end 18 | $var wire 1 $ j $end 19 | $var wire 1 ! o $end 20 | $upscope $end 21 | $upscope $end 22 | $enddefinitions $end 23 | #0 24 | $dumpvars 25 | 0$ 26 | 0# 27 | 1" 28 | 1! 29 | $end 30 | #10 31 | 0! 32 | 1# 33 | 0" 34 | #20 35 | 1$ 36 | 0# 37 | 1" 38 | #30 39 | 1! 40 | 0$ 41 | 1# 42 | #40 43 | 0! 44 | 1$ 45 | 0# 46 | 0" 47 | #50 48 | 1! 49 | 1# 50 | #60 51 | 0! 52 | 0# 53 | 1" 54 | #70 55 | 1! 56 | 1# 57 | -------------------------------------------------------------------------------- /1:2 mux/2mux_tb.v: -------------------------------------------------------------------------------- 1 | module mux_tb; 2 | reg t_a,t_b,t_s; 3 | wire t_o; 4 | 5 | mux2 mux(.i0(t_a),.i1(t_b),.j(t_s),.o(t_o)); 6 | 7 | initial begin $dumpfile("2mux.vcd"); 8 | $dumpvars(0,mux_tb); 9 | end 10 | 11 | initial begin $monitor(t_a,t_b,t_s,t_o); 12 | 13 | t_a=1'b1; 14 | t_b=1'b0; 15 | t_s=1'b0; 16 | #10 17 | t_a=1'b0; 18 | t_b=1'b1; 19 | t_s=1'b0; 20 | #10 21 | t_a=1'b1; 22 | t_b=1'b0; 23 | t_s=1'b1; 24 | #10 25 | t_a=1'b1; 26 | t_b=1'b1; 27 | t_s=1'b0; 28 | #10 29 | t_a=1'b0; 30 | t_b=1'b0; 31 | t_s=1'b1; 32 | #10 33 | t_a=1'b0; 34 | t_b=1'b1; 35 | t_s=1'b1; 36 | #10 37 | t_a=1'b1; 38 | t_b=1'b0; 39 | t_s=1'b1; 40 | #10 41 | t_a=1'b1; 42 | t_b=1'b1; 43 | t_s=1'b1; 44 | 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /2:4 demux/demux: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x55f8bf5ea870 .scope module, "Demultiplexer_1_to_4_case_tb" "Demultiplexer_1_to_4_case_tb" 2 1; 11 | .timescale 0 0; 12 | v0x55f8bf5ffc00_0 .var "A", 1 0; 13 | v0x55f8bf5ffcf0_0 .net "Y", 3 0, v0x55f8bf5d6750_0; 1 drivers 14 | v0x55f8bf5ffdc0_0 .var "din", 0 0; 15 | S_0x55f8bf5eaa00 .scope module, "I0" "Demultiplexer_1_to_4_case" 2 5, 3 1 0, S_0x55f8bf5ea870; 16 | .timescale 0 0; 17 | .port_info 0 /OUTPUT 4 "Y"; 18 | .port_info 1 /INPUT 2 "A"; 19 | .port_info 2 /INPUT 1 "din"; 20 | v0x55f8bf5b0ba0_0 .net "A", 1 0, v0x55f8bf5ffc00_0; 1 drivers 21 | v0x55f8bf5d6750_0 .var "Y", 3 0; 22 | v0x55f8bf5ffae0_0 .net "din", 0 0, v0x55f8bf5ffdc0_0; 1 drivers 23 | E_0x55f8bf5e7b80 .event edge, v0x55f8bf5b0ba0_0, v0x55f8bf5d6750_0; 24 | .scope S_0x55f8bf5eaa00; 25 | T_0 ; 26 | %wait E_0x55f8bf5e7b80; 27 | %load/vec4 v0x55f8bf5b0ba0_0; 28 | %dup/vec4; 29 | %pushi/vec4 0, 0, 2; 30 | %cmp/u; 31 | %jmp/1 T_0.0, 6; 32 | %dup/vec4; 33 | %pushi/vec4 1, 0, 2; 34 | %cmp/u; 35 | %jmp/1 T_0.1, 6; 36 | %dup/vec4; 37 | %pushi/vec4 2, 0, 2; 38 | %cmp/u; 39 | %jmp/1 T_0.2, 6; 40 | %dup/vec4; 41 | %pushi/vec4 3, 0, 2; 42 | %cmp/u; 43 | %jmp/1 T_0.3, 6; 44 | %jmp T_0.4; 45 | T_0.0 ; 46 | %load/vec4 v0x55f8bf5ffae0_0; 47 | %ix/load 4, 0, 0; 48 | %flag_set/imm 4, 0; 49 | %store/vec4 v0x55f8bf5d6750_0, 4, 1; 50 | %pushi/vec4 0, 0, 3; 51 | %ix/load 4, 1, 0; 52 | %flag_set/imm 4, 0; 53 | %store/vec4 v0x55f8bf5d6750_0, 4, 3; 54 | %jmp T_0.4; 55 | T_0.1 ; 56 | %load/vec4 v0x55f8bf5ffae0_0; 57 | %ix/load 4, 1, 0; 58 | %flag_set/imm 4, 0; 59 | %store/vec4 v0x55f8bf5d6750_0, 4, 1; 60 | %pushi/vec4 0, 0, 1; 61 | %ix/load 4, 0, 0; 62 | %flag_set/imm 4, 0; 63 | %store/vec4 v0x55f8bf5d6750_0, 4, 1; 64 | %jmp T_0.4; 65 | T_0.2 ; 66 | %load/vec4 v0x55f8bf5ffae0_0; 67 | %ix/load 4, 2, 0; 68 | %flag_set/imm 4, 0; 69 | %store/vec4 v0x55f8bf5d6750_0, 4, 1; 70 | %pushi/vec4 0, 0, 2; 71 | %ix/load 4, 0, 0; 72 | %flag_set/imm 4, 0; 73 | %store/vec4 v0x55f8bf5d6750_0, 4, 2; 74 | %jmp T_0.4; 75 | T_0.3 ; 76 | %load/vec4 v0x55f8bf5ffae0_0; 77 | %ix/load 4, 3, 0; 78 | %flag_set/imm 4, 0; 79 | %store/vec4 v0x55f8bf5d6750_0, 4, 1; 80 | %pushi/vec4 0, 0, 3; 81 | %ix/load 4, 0, 0; 82 | %flag_set/imm 4, 0; 83 | %store/vec4 v0x55f8bf5d6750_0, 4, 3; 84 | %jmp T_0.4; 85 | T_0.4 ; 86 | %pop/vec4 1; 87 | %jmp T_0; 88 | .thread T_0, $push; 89 | .scope S_0x55f8bf5ea870; 90 | T_1 ; 91 | %vpi_call 2 6 "$dumpfile", "demux.vcd" {0 0 0}; 92 | %vpi_call 2 7 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55f8bf5ea870 {0 0 0}; 93 | %end; 94 | .thread T_1; 95 | .scope S_0x55f8bf5ea870; 96 | T_2 ; 97 | %pushi/vec4 1, 0, 1; 98 | %store/vec4 v0x55f8bf5ffdc0_0, 0, 1; 99 | %pushi/vec4 0, 0, 2; 100 | %store/vec4 v0x55f8bf5ffc00_0, 0, 2; 101 | %delay 1, 0; 102 | %pushi/vec4 1, 0, 2; 103 | %store/vec4 v0x55f8bf5ffc00_0, 0, 2; 104 | %delay 1, 0; 105 | %pushi/vec4 2, 0, 2; 106 | %store/vec4 v0x55f8bf5ffc00_0, 0, 2; 107 | %delay 1, 0; 108 | %pushi/vec4 3, 0, 2; 109 | %store/vec4 v0x55f8bf5ffc00_0, 0, 2; 110 | %end; 111 | .thread T_2; 112 | .scope S_0x55f8bf5ea870; 113 | T_3 ; 114 | %vpi_call 2 17 "$monitor", "%t| Din = %d| A[1] = %d| A[0] = %d| Y[0] = %d| Y[1] = %d| Y[2] = %d| Y[3] = %d", $time, v0x55f8bf5ffdc0_0, &PV, &PV, &PV, &PV, &PV, &PV {0 0 0}; 115 | %end; 116 | .thread T_3; 117 | # The file index is used to find the file name in the following table. 118 | :file_names 4; 119 | "N/A"; 120 | ""; 121 | "demux_tb.v"; 122 | "demux.v"; 123 | -------------------------------------------------------------------------------- /2:4 demux/demux.v: -------------------------------------------------------------------------------- 1 | module Demultiplexer_1_to_4_case (output reg [3:0] Y, input [1:0] A, input din); 2 | always @(Y, A) begin 3 | case (A) 4 | 2'b00 : begin Y[0] = din; Y[3:1] = 0; end 5 | 2'b01 : begin Y[1] = din; Y[0] = 0; end 6 | 2'b10 : begin Y[2] = din; Y[1:0] = 0; end 7 | 2'b11 : begin Y[3] = din; Y[2:0] = 0; end 8 | endcase 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /2:4 demux/demux.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Sep 18 19:27:26 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module Demultiplexer_1_to_4_case_tb $end 11 | $var wire 4 ! Y [3:0] $end 12 | $var reg 2 " A [1:0] $end 13 | $var reg 1 # din $end 14 | $scope module I0 $end 15 | $var wire 2 $ A [1:0] $end 16 | $var wire 1 # din $end 17 | $var reg 4 % Y [3:0] $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | b1 % 24 | b0 $ 25 | 1# 26 | b0 " 27 | b1 ! 28 | $end 29 | #1 30 | b10 ! 31 | b10 % 32 | b1 " 33 | b1 $ 34 | #2 35 | b100 ! 36 | b100 % 37 | b10 " 38 | b10 $ 39 | #3 40 | b1000 ! 41 | b1000 % 42 | b11 " 43 | b11 $ 44 | -------------------------------------------------------------------------------- /2:4 demux/demux_tb.v: -------------------------------------------------------------------------------- 1 | module Demultiplexer_1_to_4_case_tb; 2 | wire [3:0] Y; 3 | reg [1:0] A; 4 | reg din; 5 | Demultiplexer_1_to_4_case I0 (Y, A, din); 6 | initial begin $dumpfile("demux.vcd"); 7 | $dumpvars(0, Demultiplexer_1_to_4_case_tb); 8 | end 9 | initial begin 10 | din = 1; 11 | A = 2'b00; 12 | #1 A = 2'b01; 13 | #1 A = 2'b10; 14 | #1 A = 2'b11; 15 | end 16 | initial begin 17 | $monitor("%t| Din = %d| A[1] = %d| A[0] = %d| Y[0] = %d| Y[1] = %d| Y[2] = %d| Y[3] = %d", 18 | $time, din, A[1], A[0], Y[0], Y[1], Y[2], Y[3]); 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /2:4 mux/4mux: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x556227df25e0 .scope module, "mux4_tb" "mux4_tb" 2 1; 11 | .timescale 0 0; 12 | v0x556227e109f0_0 .var "t_a", 0 0; 13 | v0x556227e10b00_0 .var "t_b", 0 0; 14 | v0x556227e10bc0_0 .var "t_c", 0 0; 15 | v0x556227e10cb0_0 .var "t_d", 0 0; 16 | v0x556227e10d50_0 .net "t_o", 0 0, L_0x556227e218e0; 1 drivers 17 | v0x556227e10e90_0 .var "t_p", 0 0; 18 | v0x556227e10f30_0 .var "t_q", 0 0; 19 | S_0x556227df2770 .scope module, "mux" "mux4" 2 6, 3 4 0, S_0x556227df25e0; 20 | .timescale 0 0; 21 | .port_info 0 /INPUT 1 "a"; 22 | .port_info 1 /INPUT 1 "b"; 23 | .port_info 2 /INPUT 1 "c"; 24 | .port_info 3 /INPUT 1 "d"; 25 | .port_info 4 /INPUT 1 "j"; 26 | .port_info 5 /INPUT 1 "k"; 27 | .port_info 6 /OUTPUT 1 "o"; 28 | v0x556227e10260_0 .net "a", 0 0, v0x556227e109f0_0; 1 drivers 29 | v0x556227e10320_0 .net "b", 0 0, v0x556227e10b00_0; 1 drivers 30 | v0x556227e10410_0 .net "c", 0 0, v0x556227e10bc0_0; 1 drivers 31 | v0x556227e104e0_0 .net "d", 0 0, v0x556227e10cb0_0; 1 drivers 32 | v0x556227e10580_0 .net "j", 0 0, v0x556227e10e90_0; 1 drivers 33 | v0x556227e106c0_0 .net "k", 0 0, v0x556227e10f30_0; 1 drivers 34 | v0x556227e10760_0 .net "o", 0 0, L_0x556227e218e0; alias, 1 drivers 35 | v0x556227e10800_0 .net "p", 0 0, L_0x556227e21210; 1 drivers 36 | v0x556227e108f0_0 .net "q", 0 0, L_0x556227e21570; 1 drivers 37 | S_0x556227defeb0 .scope module, "i0" "mux2" 3 6, 3 1 0, S_0x556227df2770; 38 | .timescale 0 0; 39 | .port_info 0 /INPUT 1 "a"; 40 | .port_info 1 /INPUT 1 "b"; 41 | .port_info 2 /INPUT 1 "j"; 42 | .port_info 3 /OUTPUT 1 "o"; 43 | v0x556227df2a00_0 .net *"_ivl_0", 31 0, L_0x556227e11020; 1 drivers 44 | L_0x7f8ead536018 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 45 | v0x556227e0e900_0 .net *"_ivl_3", 30 0, L_0x7f8ead536018; 1 drivers 46 | L_0x7f8ead536060 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 47 | v0x556227e0e9e0_0 .net/2u *"_ivl_4", 31 0, L_0x7f8ead536060; 1 drivers 48 | v0x556227e0eaa0_0 .net *"_ivl_6", 0 0, L_0x556227e210d0; 1 drivers 49 | v0x556227e0eb60_0 .net "a", 0 0, v0x556227e109f0_0; alias, 1 drivers 50 | v0x556227e0ec70_0 .net "b", 0 0, v0x556227e10b00_0; alias, 1 drivers 51 | v0x556227e0ed30_0 .net "j", 0 0, v0x556227e10e90_0; alias, 1 drivers 52 | v0x556227e0edf0_0 .net "o", 0 0, L_0x556227e21210; alias, 1 drivers 53 | L_0x556227e11020 .concat [ 1 31 0 0], v0x556227e10e90_0, L_0x7f8ead536018; 54 | L_0x556227e210d0 .cmp/eq 32, L_0x556227e11020, L_0x7f8ead536060; 55 | L_0x556227e21210 .functor MUXZ 1, v0x556227e10b00_0, v0x556227e109f0_0, L_0x556227e210d0, C4<>; 56 | S_0x556227e0ef30 .scope module, "i1" "mux2" 3 7, 3 1 0, S_0x556227df2770; 57 | .timescale 0 0; 58 | .port_info 0 /INPUT 1 "a"; 59 | .port_info 1 /INPUT 1 "b"; 60 | .port_info 2 /INPUT 1 "j"; 61 | .port_info 3 /OUTPUT 1 "o"; 62 | v0x556227e0f1a0_0 .net *"_ivl_0", 31 0, L_0x556227e21390; 1 drivers 63 | L_0x7f8ead5360a8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 64 | v0x556227e0f280_0 .net *"_ivl_3", 30 0, L_0x7f8ead5360a8; 1 drivers 65 | L_0x7f8ead5360f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 66 | v0x556227e0f360_0 .net/2u *"_ivl_4", 31 0, L_0x7f8ead5360f0; 1 drivers 67 | v0x556227e0f450_0 .net *"_ivl_6", 0 0, L_0x556227e21430; 1 drivers 68 | v0x556227e0f510_0 .net "a", 0 0, v0x556227e10b00_0; alias, 1 drivers 69 | v0x556227e0f600_0 .net "b", 0 0, v0x556227e10bc0_0; alias, 1 drivers 70 | v0x556227e0f6a0_0 .net "j", 0 0, v0x556227e10e90_0; alias, 1 drivers 71 | v0x556227e0f770_0 .net "o", 0 0, L_0x556227e21570; alias, 1 drivers 72 | L_0x556227e21390 .concat [ 1 31 0 0], v0x556227e10e90_0, L_0x7f8ead5360a8; 73 | L_0x556227e21430 .cmp/eq 32, L_0x556227e21390, L_0x7f8ead5360f0; 74 | L_0x556227e21570 .functor MUXZ 1, v0x556227e10bc0_0, v0x556227e10b00_0, L_0x556227e21430, C4<>; 75 | S_0x556227e0f8c0 .scope module, "i2" "mux2" 3 8, 3 1 0, S_0x556227df2770; 76 | .timescale 0 0; 77 | .port_info 0 /INPUT 1 "a"; 78 | .port_info 1 /INPUT 1 "b"; 79 | .port_info 2 /INPUT 1 "j"; 80 | .port_info 3 /OUTPUT 1 "o"; 81 | v0x556227e0fb40_0 .net *"_ivl_0", 31 0, L_0x556227e21660; 1 drivers 82 | L_0x7f8ead536138 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 83 | v0x556227e0fc20_0 .net *"_ivl_3", 30 0, L_0x7f8ead536138; 1 drivers 84 | L_0x7f8ead536180 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 85 | v0x556227e0fd00_0 .net/2u *"_ivl_4", 31 0, L_0x7f8ead536180; 1 drivers 86 | v0x556227e0fdf0_0 .net *"_ivl_6", 0 0, L_0x556227e217a0; 1 drivers 87 | v0x556227e0feb0_0 .net "a", 0 0, L_0x556227e21210; alias, 1 drivers 88 | v0x556227e0ffa0_0 .net "b", 0 0, L_0x556227e21570; alias, 1 drivers 89 | v0x556227e10070_0 .net "j", 0 0, v0x556227e10f30_0; alias, 1 drivers 90 | v0x556227e10110_0 .net "o", 0 0, L_0x556227e218e0; alias, 1 drivers 91 | L_0x556227e21660 .concat [ 1 31 0 0], v0x556227e10f30_0, L_0x7f8ead536138; 92 | L_0x556227e217a0 .cmp/eq 32, L_0x556227e21660, L_0x7f8ead536180; 93 | L_0x556227e218e0 .functor MUXZ 1, L_0x556227e21570, L_0x556227e21210, L_0x556227e217a0, C4<>; 94 | .scope S_0x556227df25e0; 95 | T_0 ; 96 | %vpi_call 2 8 "$dumpfile", "4mux.vcd" {0 0 0}; 97 | %vpi_call 2 9 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x556227df25e0 {0 0 0}; 98 | %end; 99 | .thread T_0; 100 | .scope S_0x556227df25e0; 101 | T_1 ; 102 | %vpi_call 2 12 "$monitor", v0x556227e109f0_0, v0x556227e10b00_0, v0x556227e10bc0_0, v0x556227e10cb0_0, v0x556227e10e90_0, v0x556227e10f30_0, v0x556227e10d50_0 {0 0 0}; 103 | %pushi/vec4 1, 0, 1; 104 | %store/vec4 v0x556227e109f0_0, 0, 1; 105 | %pushi/vec4 0, 0, 1; 106 | %store/vec4 v0x556227e10b00_0, 0, 1; 107 | %pushi/vec4 0, 0, 1; 108 | %store/vec4 v0x556227e10bc0_0, 0, 1; 109 | %pushi/vec4 0, 0, 1; 110 | %store/vec4 v0x556227e10cb0_0, 0, 1; 111 | %pushi/vec4 0, 0, 1; 112 | %store/vec4 v0x556227e10e90_0, 0, 1; 113 | %pushi/vec4 0, 0, 1; 114 | %store/vec4 v0x556227e10f30_0, 0, 1; 115 | %delay 10, 0; 116 | %pushi/vec4 0, 0, 1; 117 | %store/vec4 v0x556227e109f0_0, 0, 1; 118 | %pushi/vec4 0, 0, 1; 119 | %store/vec4 v0x556227e10b00_0, 0, 1; 120 | %pushi/vec4 1, 0, 1; 121 | %store/vec4 v0x556227e10bc0_0, 0, 1; 122 | %pushi/vec4 1, 0, 1; 123 | %store/vec4 v0x556227e10cb0_0, 0, 1; 124 | %pushi/vec4 0, 0, 1; 125 | %store/vec4 v0x556227e10e90_0, 0, 1; 126 | %pushi/vec4 0, 0, 1; 127 | %store/vec4 v0x556227e10f30_0, 0, 1; 128 | %delay 10, 0; 129 | %pushi/vec4 1, 0, 1; 130 | %store/vec4 v0x556227e109f0_0, 0, 1; 131 | %pushi/vec4 0, 0, 1; 132 | %store/vec4 v0x556227e10b00_0, 0, 1; 133 | %pushi/vec4 1, 0, 1; 134 | %store/vec4 v0x556227e10bc0_0, 0, 1; 135 | %pushi/vec4 0, 0, 1; 136 | %store/vec4 v0x556227e10cb0_0, 0, 1; 137 | %pushi/vec4 1, 0, 1; 138 | %store/vec4 v0x556227e10e90_0, 0, 1; 139 | %pushi/vec4 0, 0, 1; 140 | %store/vec4 v0x556227e10f30_0, 0, 1; 141 | %delay 10, 0; 142 | %pushi/vec4 1, 0, 1; 143 | %store/vec4 v0x556227e109f0_0, 0, 1; 144 | %pushi/vec4 0, 0, 1; 145 | %store/vec4 v0x556227e10b00_0, 0, 1; 146 | %pushi/vec4 0, 0, 1; 147 | %store/vec4 v0x556227e10bc0_0, 0, 1; 148 | %pushi/vec4 1, 0, 1; 149 | %store/vec4 v0x556227e10cb0_0, 0, 1; 150 | %pushi/vec4 1, 0, 1; 151 | %store/vec4 v0x556227e10e90_0, 0, 1; 152 | %pushi/vec4 1, 0, 1; 153 | %store/vec4 v0x556227e10f30_0, 0, 1; 154 | %delay 10, 0; 155 | %pushi/vec4 1, 0, 1; 156 | %store/vec4 v0x556227e109f0_0, 0, 1; 157 | %pushi/vec4 1, 0, 1; 158 | %store/vec4 v0x556227e10b00_0, 0, 1; 159 | %pushi/vec4 1, 0, 1; 160 | %store/vec4 v0x556227e10bc0_0, 0, 1; 161 | %pushi/vec4 1, 0, 1; 162 | %store/vec4 v0x556227e10cb0_0, 0, 1; 163 | %pushi/vec4 1, 0, 1; 164 | %store/vec4 v0x556227e10e90_0, 0, 1; 165 | %pushi/vec4 1, 0, 1; 166 | %store/vec4 v0x556227e10f30_0, 0, 1; 167 | %end; 168 | .thread T_1; 169 | # The file index is used to find the file name in the following table. 170 | :file_names 4; 171 | "N/A"; 172 | ""; 173 | "4mux_tb.v"; 174 | "4mux.v"; 175 | -------------------------------------------------------------------------------- /2:4 mux/4mux.v: -------------------------------------------------------------------------------- 1 | module mux2 (input wire a,b, input wire j, output wire o); 2 | assign o = (j == 0)? a : b; 3 | endmodule 4 | module mux4( input wire a, b , c , d , input wire j, k, output o); 5 | wire p, q; 6 | mux2 i0(a, b, j, p); 7 | mux2 i1(b, c, j, q); 8 | mux2 i2(p, q, k, o); 9 | endmodule 10 | -------------------------------------------------------------------------------- /2:4 mux/4mux.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Sep 18 19:20:23 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module mux4_tb $end 11 | $var wire 1 ! t_o $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $var reg 1 $ t_c $end 15 | $var reg 1 % t_d $end 16 | $var reg 1 & t_p $end 17 | $var reg 1 ' t_q $end 18 | $scope module mux $end 19 | $var wire 1 " a $end 20 | $var wire 1 # b $end 21 | $var wire 1 $ c $end 22 | $var wire 1 % d $end 23 | $var wire 1 & j $end 24 | $var wire 1 ' k $end 25 | $var wire 1 ( q $end 26 | $var wire 1 ) p $end 27 | $var wire 1 ! o $end 28 | $scope module i0 $end 29 | $var wire 1 " a $end 30 | $var wire 1 # b $end 31 | $var wire 1 & j $end 32 | $var wire 1 ) o $end 33 | $upscope $end 34 | $scope module i1 $end 35 | $var wire 1 # a $end 36 | $var wire 1 $ b $end 37 | $var wire 1 & j $end 38 | $var wire 1 ( o $end 39 | $upscope $end 40 | $scope module i2 $end 41 | $var wire 1 ) a $end 42 | $var wire 1 ( b $end 43 | $var wire 1 ' j $end 44 | $var wire 1 ! o $end 45 | $upscope $end 46 | $upscope $end 47 | $upscope $end 48 | $enddefinitions $end 49 | #0 50 | $dumpvars 51 | 1) 52 | 0( 53 | 0' 54 | 0& 55 | 0% 56 | 0$ 57 | 0# 58 | 1" 59 | 1! 60 | $end 61 | #10 62 | 0! 63 | 0) 64 | 1% 65 | 1$ 66 | 0" 67 | #20 68 | 1( 69 | 1& 70 | 0% 71 | 1" 72 | #30 73 | 0( 74 | 1' 75 | 1% 76 | 0$ 77 | #40 78 | 1! 79 | 1( 80 | 1) 81 | 1$ 82 | 1# 83 | -------------------------------------------------------------------------------- /2:4 mux/4mux_tb.v: -------------------------------------------------------------------------------- 1 | module mux4_tb; 2 | 3 | reg t_a,t_b, t_c, t_d, t_p, t_q; 4 | wire t_o; 5 | 6 | mux4 mux(.a(t_a),.b(t_b),.c(t_c),.d(t_d), .j(t_p), .k(t_q), .o(t_o)); 7 | 8 | initial begin $dumpfile("4mux.vcd"); 9 | $dumpvars(0,mux4_tb); 10 | end 11 | 12 | initial begin $monitor(t_a,t_b,t_c,t_d,t_p,t_q,t_o); 13 | 14 | t_a=1'b1; 15 | t_b=1'b0; 16 | t_c=1'b0; 17 | t_d=1'b0; 18 | t_p=1'b0; 19 | t_q=1'b0; 20 | #10 21 | t_a=1'b0; 22 | t_b=1'b0; 23 | t_c=1'b1; 24 | t_d=1'b1; 25 | t_p=1'b0; 26 | t_q=1'b0; 27 | 28 | #10 29 | t_a=1'b1; 30 | t_b=1'b0; 31 | t_c=1'b1; 32 | t_d=1'b0; 33 | t_p=1'b1; 34 | t_q=1'b0; 35 | 36 | #10 37 | t_a=1'b1; 38 | t_b=1'b0; 39 | t_c=1'b0; 40 | t_d=1'b1; 41 | t_p=1'b1; 42 | t_q=1'b1; 43 | 44 | #10 45 | t_a=1'b1; 46 | t_b=1'b1; 47 | t_c=1'b1; 48 | t_d=1'b1; 49 | t_p=1'b1; 50 | t_q=1'b1; 51 | 52 | 53 | end 54 | endmodule 55 | -------------------------------------------------------------------------------- /4:2 decoder/decoder: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x55da752171d0 .scope module, "decoder_tb" "decoder_tb" 2 1; 11 | .timescale 0 0; 12 | v0x55da7522f4a0_0 .var "t_a", 0 0; 13 | v0x55da7522f560_0 .var "t_b", 0 0; 14 | v0x55da7522f600_0 .var "t_c", 0 0; 15 | v0x55da7522f700_0 .net "t_p", 0 0, L_0x55da7522fcd0; 1 drivers 16 | v0x55da7522f7d0_0 .net "t_q", 0 0, L_0x55da7522ffd0; 1 drivers 17 | v0x55da7522f870_0 .net "t_r", 0 0, L_0x55da752302a0; 1 drivers 18 | v0x55da7522f940_0 .net "t_s", 0 0, L_0x55da752304c0; 1 drivers 19 | S_0x55da75217360 .scope module, "a2" "and2" 2 5, 3 1 0, S_0x55da752171d0; 20 | .timescale 0 0; 21 | .port_info 0 /INPUT 1 "a"; 22 | .port_info 1 /INPUT 1 "b"; 23 | .port_info 2 /INPUT 1 "c"; 24 | .port_info 3 /OUTPUT 1 "p"; 25 | .port_info 4 /OUTPUT 1 "q"; 26 | .port_info 5 /OUTPUT 1 "r"; 27 | .port_info 6 /OUTPUT 1 "s"; 28 | L_0x55da7522fa10 .functor NOT 1, v0x55da7522f4a0_0, C4<0>, C4<0>, C4<0>; 29 | L_0x55da7522fb00 .functor NOT 1, v0x55da7522f560_0, C4<0>, C4<0>, C4<0>; 30 | L_0x55da7522fbc0 .functor AND 1, L_0x55da7522fa10, L_0x55da7522fb00, C4<1>, C4<1>; 31 | L_0x55da7522fcd0 .functor AND 1, L_0x55da7522fbc0, v0x55da7522f600_0, C4<1>, C4<1>; 32 | L_0x55da7522fe60 .functor NOT 1, v0x55da7522f4a0_0, C4<0>, C4<0>, C4<0>; 33 | L_0x55da7522fed0 .functor AND 1, L_0x55da7522fe60, v0x55da7522f560_0, C4<1>, C4<1>; 34 | L_0x55da7522ffd0 .functor AND 1, L_0x55da7522fed0, v0x55da7522f600_0, C4<1>, C4<1>; 35 | L_0x55da752300e0 .functor NOT 1, v0x55da7522f560_0, C4<0>, C4<0>, C4<0>; 36 | L_0x55da752301a0 .functor AND 1, v0x55da7522f4a0_0, L_0x55da752300e0, C4<1>, C4<1>; 37 | L_0x55da752302a0 .functor AND 1, L_0x55da752301a0, v0x55da7522f600_0, C4<1>, C4<1>; 38 | L_0x55da75230450 .functor AND 1, v0x55da7522f4a0_0, v0x55da7522f560_0, C4<1>, C4<1>; 39 | L_0x55da752304c0 .functor AND 1, L_0x55da75230450, v0x55da7522f600_0, C4<1>, C4<1>; 40 | v0x55da75207ce0_0 .net *"_ivl_0", 0 0, L_0x55da7522fa10; 1 drivers 41 | v0x55da7522e830_0 .net *"_ivl_10", 0 0, L_0x55da7522fed0; 1 drivers 42 | v0x55da7522e910_0 .net *"_ivl_14", 0 0, L_0x55da752300e0; 1 drivers 43 | v0x55da7522e9d0_0 .net *"_ivl_16", 0 0, L_0x55da752301a0; 1 drivers 44 | v0x55da7522eab0_0 .net *"_ivl_2", 0 0, L_0x55da7522fb00; 1 drivers 45 | v0x55da7522ebe0_0 .net *"_ivl_20", 0 0, L_0x55da75230450; 1 drivers 46 | v0x55da7522ecc0_0 .net *"_ivl_4", 0 0, L_0x55da7522fbc0; 1 drivers 47 | v0x55da7522eda0_0 .net *"_ivl_8", 0 0, L_0x55da7522fe60; 1 drivers 48 | v0x55da7522ee80_0 .net "a", 0 0, v0x55da7522f4a0_0; 1 drivers 49 | v0x55da7522ef40_0 .net "b", 0 0, v0x55da7522f560_0; 1 drivers 50 | v0x55da7522f000_0 .net "c", 0 0, v0x55da7522f600_0; 1 drivers 51 | v0x55da7522f0c0_0 .net "p", 0 0, L_0x55da7522fcd0; alias, 1 drivers 52 | v0x55da7522f180_0 .net "q", 0 0, L_0x55da7522ffd0; alias, 1 drivers 53 | v0x55da7522f240_0 .net "r", 0 0, L_0x55da752302a0; alias, 1 drivers 54 | v0x55da7522f300_0 .net "s", 0 0, L_0x55da752304c0; alias, 1 drivers 55 | .scope S_0x55da752171d0; 56 | T_0 ; 57 | %vpi_call 2 6 "$dumpfile", "decoder.vcd" {0 0 0}; 58 | %vpi_call 2 7 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55da752171d0 {0 0 0}; 59 | %end; 60 | .thread T_0; 61 | .scope S_0x55da752171d0; 62 | T_1 ; 63 | %vpi_call 2 9 "$monitor", v0x55da7522f4a0_0, v0x55da7522f560_0, v0x55da7522f600_0, v0x55da7522f700_0, v0x55da7522f7d0_0, v0x55da7522f870_0, v0x55da7522f940_0 {0 0 0}; 64 | %pushi/vec4 0, 0, 1; 65 | %store/vec4 v0x55da7522f4a0_0, 0, 1; 66 | %pushi/vec4 0, 0, 1; 67 | %store/vec4 v0x55da7522f560_0, 0, 1; 68 | %pushi/vec4 1, 0, 1; 69 | %store/vec4 v0x55da7522f600_0, 0, 1; 70 | %delay 10, 0; 71 | %pushi/vec4 0, 0, 1; 72 | %store/vec4 v0x55da7522f4a0_0, 0, 1; 73 | %pushi/vec4 1, 0, 1; 74 | %store/vec4 v0x55da7522f560_0, 0, 1; 75 | %pushi/vec4 1, 0, 1; 76 | %store/vec4 v0x55da7522f600_0, 0, 1; 77 | %delay 10, 0; 78 | %pushi/vec4 1, 0, 1; 79 | %store/vec4 v0x55da7522f4a0_0, 0, 1; 80 | %pushi/vec4 0, 0, 1; 81 | %store/vec4 v0x55da7522f560_0, 0, 1; 82 | %pushi/vec4 1, 0, 1; 83 | %store/vec4 v0x55da7522f600_0, 0, 1; 84 | %delay 10, 0; 85 | %pushi/vec4 1, 0, 1; 86 | %store/vec4 v0x55da7522f4a0_0, 0, 1; 87 | %pushi/vec4 1, 0, 1; 88 | %store/vec4 v0x55da7522f560_0, 0, 1; 89 | %pushi/vec4 1, 0, 1; 90 | %store/vec4 v0x55da7522f600_0, 0, 1; 91 | %delay 10, 0; 92 | %pushi/vec4 1, 0, 1; 93 | %store/vec4 v0x55da7522f4a0_0, 0, 1; 94 | %pushi/vec4 1, 0, 1; 95 | %store/vec4 v0x55da7522f560_0, 0, 1; 96 | %pushi/vec4 1, 0, 1; 97 | %store/vec4 v0x55da7522f600_0, 0, 1; 98 | %delay 10, 0; 99 | %pushi/vec4 1, 0, 1; 100 | %store/vec4 v0x55da7522f4a0_0, 0, 1; 101 | %pushi/vec4 1, 0, 1; 102 | %store/vec4 v0x55da7522f560_0, 0, 1; 103 | %pushi/vec4 0, 0, 1; 104 | %store/vec4 v0x55da7522f600_0, 0, 1; 105 | %end; 106 | .thread T_1; 107 | # The file index is used to find the file name in the following table. 108 | :file_names 4; 109 | "N/A"; 110 | ""; 111 | "decoder_tb.v"; 112 | "decoder.v"; 113 | -------------------------------------------------------------------------------- /4:2 decoder/decoder.v: -------------------------------------------------------------------------------- 1 | module and2(input wire a, b, c, output wire p, q, r, s); 2 | assign p = (~a)&(~b)&(c); 3 | assign q = (~a)&(b)&(c); 4 | assign r = (a)&(~b)&(c); 5 | assign s = (a)&(b)&(c); 6 | endmodule 7 | -------------------------------------------------------------------------------- /4:2 decoder/decoder.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Sep 18 19:23:42 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module decoder_tb $end 11 | $var wire 1 ! t_s $end 12 | $var wire 1 " t_r $end 13 | $var wire 1 # t_q $end 14 | $var wire 1 $ t_p $end 15 | $var reg 1 % t_a $end 16 | $var reg 1 & t_b $end 17 | $var reg 1 ' t_c $end 18 | $scope module a2 $end 19 | $var wire 1 % a $end 20 | $var wire 1 & b $end 21 | $var wire 1 ' c $end 22 | $var wire 1 $ p $end 23 | $var wire 1 # q $end 24 | $var wire 1 " r $end 25 | $var wire 1 ! s $end 26 | $upscope $end 27 | $upscope $end 28 | $enddefinitions $end 29 | #0 30 | $dumpvars 31 | 1' 32 | 0& 33 | 0% 34 | 1$ 35 | 0# 36 | 0" 37 | 0! 38 | $end 39 | #10 40 | 0$ 41 | 1# 42 | 1& 43 | #20 44 | 1" 45 | 0# 46 | 0& 47 | 1% 48 | #30 49 | 0" 50 | 1! 51 | 1& 52 | #50 53 | 0! 54 | 0' 55 | -------------------------------------------------------------------------------- /4:2 decoder/decoder_tb.v: -------------------------------------------------------------------------------- 1 | module decoder_tb; 2 | reg t_a, t_b, t_c; 3 | wire t_p, t_q, t_r, t_s; 4 | 5 | and2 a2(.a(t_a), .b(t_b), .c(t_c), .p(t_p), .q(t_q), .r(t_r), .s(t_s)); 6 | initial begin $dumpfile("decoder.vcd"); 7 | $dumpvars(0, decoder_tb); 8 | end 9 | initial begin $monitor(t_a,t_b, t_c,t_p, t_q, t_r, t_s); 10 | t_a = 1'b0; 11 | t_b = 1'b0; 12 | t_c = 1'b1; 13 | #10 14 | t_a = 1'b0; 15 | t_b = 1'b1; 16 | t_c = 1'b1; 17 | #10 18 | t_a = 1'b1; 19 | t_b = 1'b0; 20 | t_c = 1'b1; 21 | #10 22 | t_a = 1'b1; 23 | t_b = 1'b1; 24 | t_c = 1'b1; 25 | #10 26 | t_a = 1'b1; 27 | t_b = 1'b1; 28 | t_c = 1'b1; 29 | #10 30 | t_a = 1'b1; 31 | t_b = 1'b1; 32 | t_c = 1'b0; 33 | 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /8-bit Booth Multiplier/Booth_Multiplier.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Thu Oct 27 23:05:48 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module booth_tb $end 11 | $var wire 1 ! valid $end 12 | $var wire 16 " Z [15:0] $end 13 | $var reg 8 # X [7:0] $end 14 | $var reg 8 $ Y [7:0] $end 15 | $var reg 1 % clock $end 16 | $var reg 1 & reset $end 17 | $var reg 1 ' start $end 18 | $scope module inst $end 19 | $var wire 8 ( X [7:0] $end 20 | $var wire 8 ) Y [7:0] $end 21 | $var wire 1 % clock $end 22 | $var wire 1 & reset $end 23 | $var wire 1 ' start $end 24 | $var reg 16 * Z [15:0] $end 25 | $var reg 16 + Z_temp [15:0] $end 26 | $var reg 3 , count [2:0] $end 27 | $var reg 16 - next_Z [15:0] $end 28 | $var reg 3 . next_count [2:0] $end 29 | $var reg 1 / next_state $end 30 | $var reg 3 0 next_temp [2:0] $end 31 | $var reg 1 1 next_valid $end 32 | $var reg 1 2 present_state $end 33 | $var reg 3 3 temp [2:0] $end 34 | $var reg 1 ! valid $end 35 | $upscope $end 36 | $upscope $end 37 | $enddefinitions $end 38 | #0 39 | $dumpvars 40 | b0 3 41 | 02 42 | 01 43 | b0 0 44 | 0/ 45 | b0 . 46 | b0 - 47 | b0 , 48 | bx + 49 | b0 * 50 | b10111010 ) 51 | b11001000 ( 52 | 0' 53 | 0& 54 | 1% 55 | b10111010 $ 56 | b11001000 # 57 | b0 " 58 | 0! 59 | $end 60 | #5 61 | 0% 62 | #10 63 | 1% 64 | 1& 65 | #15 66 | 0% 67 | #20 68 | b1 . 69 | b11001000 + 70 | 12 71 | b11001000 " 72 | b11001000 * 73 | b1100100 - 74 | 1/ 75 | 1% 76 | 1' 77 | #25 78 | 0% 79 | #30 80 | b110010 - 81 | b10 . 82 | b1100100 + 83 | b1 , 84 | b1100100 " 85 | b1100100 * 86 | 1% 87 | 0' 88 | #35 89 | 0% 90 | #40 91 | b11001 - 92 | b11 . 93 | b10 0 94 | b110010 + 95 | b10 , 96 | b110010 " 97 | b110010 * 98 | 1% 99 | #45 100 | 0% 101 | #50 102 | b10001100001100 - 103 | b100 . 104 | b1 0 105 | b100011000011001 + 106 | b11 , 107 | b10 3 108 | b11001 " 109 | b11001 * 110 | 1% 111 | #55 112 | 0% 113 | #60 114 | b1110111010000110 - 115 | b101 . 116 | b0 0 117 | b1101110100001100 + 118 | b100 , 119 | b1 3 120 | b10001100001100 " 121 | b10001100001100 * 122 | 1% 123 | #65 124 | 0% 125 | #70 126 | b1111011101000011 - 127 | b110 . 128 | b10 0 129 | b1110111010000110 + 130 | b101 , 131 | b0 3 132 | b1110111010000110 " 133 | b1110111010000110 * 134 | 1% 135 | #75 136 | 0% 137 | #80 138 | b1111010100001 - 139 | b111 . 140 | b11 0 141 | b11110101000011 + 142 | b110 , 143 | b10 3 144 | b1111011101000011 " 145 | b1111011101000011 * 146 | 1% 147 | #85 148 | 0% 149 | #90 150 | 0/ 151 | 11 152 | b111101010000 - 153 | b0 . 154 | b0x1 0 155 | b1111010100001 + 156 | b111 , 157 | b11 3 158 | b1111010100001 " 159 | b1111010100001 * 160 | 1% 161 | #95 162 | 0% 163 | #100 164 | b0 - 165 | b0 0 166 | 01 167 | b0 , 168 | b0x1 3 169 | 02 170 | 1! 171 | b111101010000 " 172 | b111101010000 * 173 | 1% 174 | #105 175 | 0% 176 | #110 177 | b0 3 178 | 0! 179 | b0 " 180 | b0 * 181 | 1% 182 | #115 183 | 0% 184 | #120 185 | 1% 186 | #125 187 | 0% 188 | #130 189 | 1% 190 | #135 191 | 0% 192 | #140 193 | 1% 194 | 0& 195 | #145 196 | 0% 197 | #150 198 | 1% 199 | #155 200 | 0% 201 | #160 202 | 1% 203 | #165 204 | 0% 205 | #170 206 | 1% 207 | #175 208 | 0% 209 | #180 210 | 1% 211 | #185 212 | 0% 213 | #190 214 | 1% 215 | #195 216 | 0% 217 | #200 218 | 1% 219 | #205 220 | 0% 221 | #210 222 | 1% 223 | #215 224 | 0% 225 | #220 226 | 1% 227 | #225 228 | 0% 229 | #230 230 | 1% 231 | #235 232 | 0% 233 | #240 234 | 1% 235 | #245 236 | 0% 237 | #250 238 | 1% 239 | #255 240 | 0% 241 | #260 242 | 1% 243 | -------------------------------------------------------------------------------- /8-bit Booth Multiplier/GTK Output snaps/Negative, Negative.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/8-bit Booth Multiplier/GTK Output snaps/Negative, Negative.png -------------------------------------------------------------------------------- /8-bit Booth Multiplier/GTK Output snaps/Negative, Positive.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/8-bit Booth Multiplier/GTK Output snaps/Negative, Positive.png -------------------------------------------------------------------------------- /8-bit Booth Multiplier/GTK Output snaps/Positive, Negative.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/8-bit Booth Multiplier/GTK Output snaps/Positive, Negative.png -------------------------------------------------------------------------------- /8-bit Booth Multiplier/GTK Output snaps/Positive, Positive.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/8-bit Booth Multiplier/GTK Output snaps/Positive, Positive.png -------------------------------------------------------------------------------- /8-bit Booth Multiplier/bit: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x561f17c39880 .scope module, "booth_tb" "booth_tb" 2 1; 11 | .timescale 0 0; 12 | v0x561f17c541d0_0 .var/s "X", 7 0; 13 | v0x561f17c542b0_0 .var/s "Y", 7 0; 14 | v0x561f17c54350_0 .net/s "Z", 15 0, v0x561f17c53560_0; 1 drivers 15 | v0x561f17c54450_0 .var "clock", 0 0; 16 | v0x561f17c54520_0 .var "reset", 0 0; 17 | v0x561f17c545c0_0 .var "start", 0 0; 18 | v0x561f17c54690_0 .net "valid", 0 0, v0x561f17c54030_0; 1 drivers 19 | S_0x561f17c39a10 .scope module, "inst" "Booth_Multiplier" 2 10, 3 1 0, S_0x561f17c39880; 20 | .timescale 0 0; 21 | .port_info 0 /INPUT 1 "clock"; 22 | .port_info 1 /INPUT 1 "reset"; 23 | .port_info 2 /INPUT 1 "start"; 24 | .port_info 3 /INPUT 8 "X"; 25 | .port_info 4 /INPUT 8 "Y"; 26 | .port_info 5 /OUTPUT 1 "valid"; 27 | .port_info 6 /OUTPUT 16 "Z"; 28 | P_0x561f17c21070 .param/l "IDLE" 0 3 17, C4<0>; 29 | P_0x561f17c210b0 .param/l "START" 0 3 18, C4<1>; 30 | v0x561f17bf7df0_0 .net/s "X", 7 0, v0x561f17c541d0_0; 1 drivers 31 | v0x561f17c53480_0 .net/s "Y", 7 0, v0x561f17c542b0_0; 1 drivers 32 | v0x561f17c53560_0 .var/s "Z", 15 0; 33 | v0x561f17c53620_0 .var/s "Z_temp", 15 0; 34 | v0x561f17c53700_0 .net "clock", 0 0, v0x561f17c54450_0; 1 drivers 35 | v0x561f17c53810_0 .var "count", 2 0; 36 | v0x561f17c538f0_0 .var/s "next_Z", 15 0; 37 | v0x561f17c539d0_0 .var "next_count", 2 0; 38 | v0x561f17c53ab0_0 .var "next_state", 0 0; 39 | v0x561f17c53b70_0 .var "next_temp", 2 0; 40 | v0x561f17c53c50_0 .var "next_valid", 0 0; 41 | v0x561f17c53d10_0 .var "present_state", 0 0; 42 | v0x561f17c53dd0_0 .net "reset", 0 0, v0x561f17c54520_0; 1 drivers 43 | v0x561f17c53e90_0 .net "start", 0 0, v0x561f17c545c0_0; 1 drivers 44 | v0x561f17c53f50_0 .var "temp", 2 0; 45 | v0x561f17c54030_0 .var "valid", 0 0; 46 | E_0x561f17c314f0/0 .event edge, v0x561f17c53d10_0, v0x561f17c53e90_0, v0x561f17bf7df0_0, v0x561f17c53f50_0; 47 | E_0x561f17c314f0/1 .event edge, v0x561f17c53560_0, v0x561f17c53480_0, v0x561f17c53810_0, v0x561f17c53620_0; 48 | E_0x561f17c314f0 .event/or E_0x561f17c314f0/0, E_0x561f17c314f0/1; 49 | E_0x561f17bf86f0/0 .event negedge, v0x561f17c53dd0_0; 50 | E_0x561f17bf86f0/1 .event posedge, v0x561f17c53700_0; 51 | E_0x561f17bf86f0 .event/or E_0x561f17bf86f0/0, E_0x561f17bf86f0/1; 52 | .scope S_0x561f17c39a10; 53 | T_0 ; 54 | %wait E_0x561f17bf86f0; 55 | %load/vec4 v0x561f17c53dd0_0; 56 | %nor/r; 57 | %flag_set/vec4 8; 58 | %jmp/0xz T_0.0, 8; 59 | %pushi/vec4 0, 0, 16; 60 | %assign/vec4 v0x561f17c53560_0, 0; 61 | %pushi/vec4 0, 0, 1; 62 | %assign/vec4 v0x561f17c54030_0, 0; 63 | %pushi/vec4 0, 0, 1; 64 | %assign/vec4 v0x561f17c53d10_0, 0; 65 | %pushi/vec4 0, 0, 3; 66 | %assign/vec4 v0x561f17c53f50_0, 0; 67 | %pushi/vec4 0, 0, 3; 68 | %assign/vec4 v0x561f17c53810_0, 0; 69 | %jmp T_0.1; 70 | T_0.0 ; 71 | %load/vec4 v0x561f17c538f0_0; 72 | %assign/vec4 v0x561f17c53560_0, 0; 73 | %load/vec4 v0x561f17c53c50_0; 74 | %assign/vec4 v0x561f17c54030_0, 0; 75 | %load/vec4 v0x561f17c53ab0_0; 76 | %assign/vec4 v0x561f17c53d10_0, 0; 77 | %load/vec4 v0x561f17c53b70_0; 78 | %assign/vec4 v0x561f17c53f50_0, 0; 79 | %load/vec4 v0x561f17c539d0_0; 80 | %assign/vec4 v0x561f17c53810_0, 0; 81 | T_0.1 ; 82 | %jmp T_0; 83 | .thread T_0; 84 | .scope S_0x561f17c39a10; 85 | T_1 ; 86 | %wait E_0x561f17c314f0; 87 | %load/vec4 v0x561f17c53d10_0; 88 | %dup/vec4; 89 | %pushi/vec4 0, 0, 1; 90 | %cmp/u; 91 | %jmp/1 T_1.0, 6; 92 | %dup/vec4; 93 | %pushi/vec4 1, 0, 1; 94 | %cmp/u; 95 | %jmp/1 T_1.1, 6; 96 | %jmp T_1.2; 97 | T_1.0 ; 98 | %pushi/vec4 0, 0, 3; 99 | %store/vec4 v0x561f17c539d0_0, 0, 3; 100 | %pushi/vec4 0, 0, 1; 101 | %store/vec4 v0x561f17c53c50_0, 0, 1; 102 | %load/vec4 v0x561f17c53e90_0; 103 | %flag_set/vec4 8; 104 | %jmp/0xz T_1.3, 8; 105 | %pushi/vec4 1, 0, 1; 106 | %store/vec4 v0x561f17c53ab0_0, 0, 1; 107 | %load/vec4 v0x561f17bf7df0_0; 108 | %parti/s 1, 0, 2; 109 | %concati/vec4 0, 0, 1; 110 | %pad/u 3; 111 | %store/vec4 v0x561f17c53b70_0, 0, 3; 112 | %pushi/vec4 0, 0, 8; 113 | %load/vec4 v0x561f17bf7df0_0; 114 | %concat/vec4; draw_concat_vec4 115 | %store/vec4 v0x561f17c538f0_0, 0, 16; 116 | %jmp T_1.4; 117 | T_1.3 ; 118 | %load/vec4 v0x561f17c53d10_0; 119 | %store/vec4 v0x561f17c53ab0_0, 0, 1; 120 | %pushi/vec4 0, 0, 3; 121 | %store/vec4 v0x561f17c53b70_0, 0, 3; 122 | %pushi/vec4 0, 0, 16; 123 | %store/vec4 v0x561f17c538f0_0, 0, 16; 124 | T_1.4 ; 125 | %jmp T_1.2; 126 | T_1.1 ; 127 | %load/vec4 v0x561f17c53f50_0; 128 | %dup/vec4; 129 | %pushi/vec4 2, 0, 3; 130 | %cmp/u; 131 | %jmp/1 T_1.5, 6; 132 | %dup/vec4; 133 | %pushi/vec4 1, 0, 3; 134 | %cmp/u; 135 | %jmp/1 T_1.6, 6; 136 | %load/vec4 v0x561f17c53560_0; 137 | %parti/s 8, 8, 5; 138 | %load/vec4 v0x561f17c53560_0; 139 | %parti/s 8, 0, 2; 140 | %concat/vec4; draw_concat_vec4 141 | %store/vec4 v0x561f17c53620_0, 0, 16; 142 | %jmp T_1.8; 143 | T_1.5 ; 144 | %load/vec4 v0x561f17c53560_0; 145 | %parti/s 8, 8, 5; 146 | %load/vec4 v0x561f17c53480_0; 147 | %sub; 148 | %load/vec4 v0x561f17c53560_0; 149 | %parti/s 8, 0, 2; 150 | %concat/vec4; draw_concat_vec4 151 | %store/vec4 v0x561f17c53620_0, 0, 16; 152 | %jmp T_1.8; 153 | T_1.6 ; 154 | %load/vec4 v0x561f17c53560_0; 155 | %parti/s 8, 8, 5; 156 | %load/vec4 v0x561f17c53480_0; 157 | %add; 158 | %load/vec4 v0x561f17c53560_0; 159 | %parti/s 8, 0, 2; 160 | %concat/vec4; draw_concat_vec4 161 | %store/vec4 v0x561f17c53620_0, 0, 16; 162 | %jmp T_1.8; 163 | T_1.8 ; 164 | %pop/vec4 1; 165 | %load/vec4 v0x561f17bf7df0_0; 166 | %load/vec4 v0x561f17c53810_0; 167 | %pad/u 32; 168 | %addi 1, 0, 32; 169 | %part/u 1; 170 | %load/vec4 v0x561f17bf7df0_0; 171 | %load/vec4 v0x561f17c53810_0; 172 | %part/u 1; 173 | %concat/vec4; draw_concat_vec4 174 | %pad/u 3; 175 | %store/vec4 v0x561f17c53b70_0, 0, 3; 176 | %load/vec4 v0x561f17c53810_0; 177 | %addi 1, 0, 3; 178 | %store/vec4 v0x561f17c539d0_0, 0, 3; 179 | %load/vec4 v0x561f17c53620_0; 180 | %ix/load 4, 1, 0; 181 | %flag_set/imm 4, 0; 182 | %shiftr/s 4; 183 | %store/vec4 v0x561f17c538f0_0, 0, 16; 184 | %load/vec4 v0x561f17c53810_0; 185 | %and/r; 186 | %flag_set/vec4 8; 187 | %jmp/0 T_1.9, 8; 188 | %pushi/vec4 1, 0, 1; 189 | %jmp/1 T_1.10, 8; 190 | T_1.9 ; End of true expr. 191 | %pushi/vec4 0, 0, 1; 192 | %jmp/0 T_1.10, 8; 193 | ; End of false expr. 194 | %blend; 195 | T_1.10; 196 | %store/vec4 v0x561f17c53c50_0, 0, 1; 197 | %load/vec4 v0x561f17c53810_0; 198 | %and/r; 199 | %flag_set/vec4 8; 200 | %jmp/0 T_1.11, 8; 201 | %pushi/vec4 0, 0, 1; 202 | %jmp/1 T_1.12, 8; 203 | T_1.11 ; End of true expr. 204 | %load/vec4 v0x561f17c53d10_0; 205 | %jmp/0 T_1.12, 8; 206 | ; End of false expr. 207 | %blend; 208 | T_1.12; 209 | %store/vec4 v0x561f17c53ab0_0, 0, 1; 210 | %jmp T_1.2; 211 | T_1.2 ; 212 | %pop/vec4 1; 213 | %jmp T_1; 214 | .thread T_1, $push; 215 | .scope S_0x561f17c39880; 216 | T_2 ; 217 | %delay 5, 0; 218 | %load/vec4 v0x561f17c54450_0; 219 | %inv; 220 | %store/vec4 v0x561f17c54450_0, 0, 1; 221 | %jmp T_2; 222 | .thread T_2; 223 | .scope S_0x561f17c39880; 224 | T_3 ; 225 | %vpi_call 2 13 "$monitor", $time, "X=%d, Y=%d, valid=%d, Z=%d ", v0x561f17c541d0_0, v0x561f17c542b0_0, v0x561f17c54690_0, v0x561f17c54350_0 {0 0 0}; 226 | %end; 227 | .thread T_3; 228 | .scope S_0x561f17c39880; 229 | T_4 ; 230 | %pushi/vec4 200, 0, 8; 231 | %store/vec4 v0x561f17c541d0_0, 0, 8; 232 | %pushi/vec4 186, 0, 8; 233 | %store/vec4 v0x561f17c542b0_0, 0, 8; 234 | %pushi/vec4 1, 0, 1; 235 | %store/vec4 v0x561f17c54450_0, 0, 1; 236 | %pushi/vec4 0, 0, 1; 237 | %store/vec4 v0x561f17c54520_0, 0, 1; 238 | %pushi/vec4 0, 0, 1; 239 | %store/vec4 v0x561f17c545c0_0, 0, 1; 240 | %delay 10, 0; 241 | %pushi/vec4 1, 0, 1; 242 | %store/vec4 v0x561f17c54520_0, 0, 1; 243 | %delay 10, 0; 244 | %pushi/vec4 1, 0, 1; 245 | %store/vec4 v0x561f17c545c0_0, 0, 1; 246 | %delay 10, 0; 247 | %pushi/vec4 0, 0, 1; 248 | %store/vec4 v0x561f17c545c0_0, 0, 1; 249 | %delay 110, 0; 250 | %pushi/vec4 0, 0, 1; 251 | %store/vec4 v0x561f17c54520_0, 0, 1; 252 | %delay 120, 0; 253 | %pushi/vec4 0, 0, 1; 254 | %store/vec4 v0x561f17c54450_0, 0, 1; 255 | %vpi_call 2 25 "$finish" {0 0 0}; 256 | %end; 257 | .thread T_4; 258 | .scope S_0x561f17c39880; 259 | T_5 ; 260 | %vpi_call 2 31 "$dumpfile", "Booth_Multiplier.vcd" {0 0 0}; 261 | %vpi_call 2 32 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x561f17c39880 {0 0 0}; 262 | %end; 263 | .thread T_5; 264 | # The file index is used to find the file name in the following table. 265 | :file_names 4; 266 | "N/A"; 267 | ""; 268 | "bit_tb.v"; 269 | "bit.v"; 270 | -------------------------------------------------------------------------------- /8-bit Booth Multiplier/bit.v: -------------------------------------------------------------------------------- 1 | module Booth_Multiplier(clock,reset,start,X,Y,valid,Z); 2 | 3 | input clock; 4 | input reset; 5 | input start; 6 | 7 | input signed [7:0]X,Y; 8 | output signed [15:0]Z; 9 | output valid; 10 | 11 | reg signed [15:0] Z,next_Z,Z_temp; 12 | reg next_state, present_state; 13 | reg [2:0] temp,next_temp; 14 | reg [2:0] count,next_count; 15 | reg valid, next_valid; 16 | 17 | parameter IDLE = 1'b0; 18 | parameter START = 1'b1; 19 | 20 | always @ (posedge clock or negedge reset) 21 | begin 22 | if(!reset) 23 | begin 24 | Z <= 16'd0; 25 | valid <= 1'b0; 26 | present_state <= 1'b0; 27 | temp <= 2'd0; 28 | count <= 2'd0; 29 | end 30 | 31 | else 32 | begin 33 | Z <= next_Z; 34 | valid <= next_valid; 35 | present_state <= next_state; 36 | temp <= next_temp; 37 | count <= next_count; 38 | end 39 | end 40 | 41 | always @ (*) 42 | begin 43 | case(present_state) 44 | 45 | IDLE: 46 | begin 47 | next_count = 2'b0; 48 | next_valid = 1'b0; 49 | if(start) 50 | begin 51 | next_state = START; 52 | next_temp = {X[0],1'b0}; 53 | next_Z = {8'd0,X}; 54 | end 55 | else 56 | begin 57 | next_state = present_state; 58 | next_temp = 4'd0; 59 | next_Z = 16'd0; 60 | end 61 | end 62 | 63 | START: 64 | begin 65 | case(temp) 66 | 4'b10: Z_temp = {Z[15:8]-Y,Z[7:0]}; 67 | 4'b01: Z_temp = {Z[15:8]+Y,Z[7:0]}; 68 | default: Z_temp = {Z[15:8],Z[7:0]}; 69 | endcase 70 | next_temp = {X[count+1],X[count]}; 71 | next_count = count + 1'b1; 72 | next_Z = Z_temp >>> 1; 73 | next_valid = (&count) ? 1'b1 : 1'b0; 74 | next_state = (&count) ? IDLE : present_state; 75 | end 76 | endcase 77 | end 78 | endmodule 79 | -------------------------------------------------------------------------------- /8-bit Booth Multiplier/bit_tb.v: -------------------------------------------------------------------------------- 1 | module booth_tb; 2 | 3 | reg clock,reset,start; 4 | reg signed [7:0]X,Y; 5 | wire signed [15:0]Z; 6 | wire valid; 7 | 8 | always #5 clock = ~clock; 9 | 10 | Booth_Multiplier inst (clock,reset,start,X,Y,valid,Z); 11 | 12 | initial 13 | $monitor($time,"X=%d, Y=%d, valid=%d, Z=%d ",X,Y,valid,Z); 14 | 15 | initial 16 | begin 17 | 18 | X=-56;Y=-70;clock=1'b1;reset=1'b0;start=1'b0; 19 | #10 reset = 1'b1; 20 | #10 start = 1'b1; 21 | #10 start = 1'b0; 22 | #110 reset = 1'b0; 23 | #120 clock = 1'b0; 24 | 25 | $finish; 26 | end 27 | 28 | initial 29 | begin 30 | 31 | $dumpfile("Booth_Multiplier.vcd"); 32 | $dumpvars(0,booth_tb); 33 | 34 | end 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /Control Logic/alu.v: -------------------------------------------------------------------------------- 1 | 2 | module alu_slice (input wire [1:0] op, input wire i0, i1, cin, output wire o, cout); 3 | wire t_sumdiff, t_and, t_or, t_andor; 4 | addsub _i0 (op[0], i0, i1, cin, t_sumdiff, cout); 5 | and2 _i1 (i0, i1, t_and); 6 | or2 _i2 (i0, i1, t_or); 7 | mux2 _i3 (t_and, t_or, op[0], t_andor); 8 | mux2 _i4 (t_sumdiff, t_andor, op[1], o); 9 | endmodule 10 | 11 | module alu (input wire [1:0] op, input wire [15:0] i0, i1, 12 | output wire [15:0] o, output wire cout); 13 | wire [14:0] c; 14 | alu_slice _i0 (op, i0[0], i1[0], op[0] , o[0], c[0]); 15 | alu_slice _i1 (op, i0[1], i1[1], c[0], o[1], c[1]); 16 | alu_slice _i2 (op, i0[2], i1[2], c[1], o[2], c[2]); 17 | alu_slice _i3 (op, i0[3], i1[3], c[2], o[3], c[3]); 18 | alu_slice _i4 (op, i0[4], i1[4], c[3], o[4], c[4]); 19 | alu_slice _i5 (op, i0[5], i1[5], c[4], o[5], c[5]); 20 | alu_slice _i6 (op, i0[6], i1[6], c[5], o[6], c[6]); 21 | alu_slice _i7 (op, i0[7], i1[7], c[6], o[7], c[7]); 22 | alu_slice _i8 (op, i0[8], i1[8], c[7], o[8], c[8]); 23 | alu_slice _i9 (op, i0[9], i1[9], c[8], o[9], c[9]); 24 | alu_slice _i10 (op, i0[10], i1[10], c[9] , o[10], c[10]); 25 | alu_slice _i11 (op, i0[11], i1[11], c[10], o[11], c[11]); 26 | alu_slice _i12 (op, i0[12], i1[12], c[11], o[12], c[12]); 27 | alu_slice _i13 (op, i0[13], i1[13], c[12], o[13], c[13]); 28 | alu_slice _i14 (op, i0[14], i1[14], c[13], o[14], c[14]); 29 | alu_slice _i15 (op, i0[15], i1[15], c[14], o[15], cout); 30 | endmodule 31 | -------------------------------------------------------------------------------- /Control Logic/lib.v: -------------------------------------------------------------------------------- 1 | module invert (input wire i, output wire o); 2 | assign o = !i; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (t, o); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (t, o); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (t, o); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | module mux2 (input wire i0, i1, j, output wire o); 72 | assign o = (j==0)?i0:i1; 73 | endmodule 74 | 75 | module mux3 (input wire [0:2] i, input wire j1, j0, output wire o); 76 | wire t; 77 | mux2 mux2_0 (i[0], i[1], j0, t); 78 | mux2 mux2_1 (t, i[2], j1, o); 79 | endmodule 80 | 81 | module mux4 (input wire [0:3] i, input wire j1, j0, output wire o); 82 | wire t0, t1; 83 | mux2 mux2_0 (i[0], i[1], j1, t0); 84 | mux2 mux2_1 (i[2], i[3], j1, t1); 85 | mux2 mux2_2 (t0, t1, j0, o); 86 | endmodule 87 | 88 | module mux8 (input wire [0:7] i, input wire j2, j1, j0, output wire o); 89 | wire t0, t1; 90 | mux4 mux4_0 (i[0:3], j2, j1, t0); 91 | mux4 mux4_1 (i[4:7], j2, j1, t1); 92 | mux2 mux2_0 (t0, t1, j0, o); 93 | endmodule 94 | 95 | module demux2 (input wire i, j, output wire o0, o1); 96 | assign o0 = (j==0)?i:1'b0; 97 | assign o1 = (j==1)?i:1'b0; 98 | endmodule 99 | 100 | module demux4 (input wire i, j1, j0, output wire [0:3] o); 101 | wire t0, t1; 102 | demux2 demux2_0 (i, j1, t0, t1); 103 | demux2 demux2_1 (t0, j0, o[0], o[1]); 104 | demux2 demux2_2 (t1, j0, o[2], o[3]); 105 | endmodule 106 | 107 | module demux8 (input wire i, j2, j1, j0, output wire [0:7] o); 108 | wire t0, t1; 109 | demux2 demux2_0 (i, j2, t0, t1); 110 | demux4 demux4_0 (t0, j1, j0, o[0:3]); 111 | demux4 demux4_1 (t1, j1, j0, o[4:7]); 112 | endmodule 113 | 114 | module df (input wire clk, in, output wire out); 115 | reg df_out; 116 | always@(posedge clk) df_out <= in; 117 | assign out = df_out; 118 | endmodule 119 | 120 | module dfr (input wire clk, reset, in, output wire out); 121 | wire reset_, df_in; 122 | invert invert_0 (reset, reset_); 123 | and2 and2_0 (in, reset_, df_in); 124 | df df_0 (clk, df_in, out); 125 | endmodule 126 | 127 | module dfrl (input wire clk, reset, load, in, output wire out); 128 | wire _in; 129 | mux2 mux2_0(out, in, load, _in); 130 | dfr dfr_1(clk, reset, _in, out); 131 | endmodule 132 | 133 | module dfs (input wire clk, set, in, output wire out); 134 | wire dfr_in,dfr_out; 135 | invert invert_0(in, dfr_in); 136 | invert invert_1(dfr_out, out); 137 | dfr dfr_2(clk, set, dfr_in, dfr_out); 138 | endmodule 139 | 140 | module dfsl (input wire clk, set, load, in, output wire out); 141 | wire _in; 142 | mux2 mux2_0(out, in, load, _in); 143 | dfs dfs_1(clk, set, _in, out); 144 | endmodule 145 | 146 | module fa (input wire i0, i1, cin, output wire sum, cout); 147 | wire t0, t1, t2; 148 | xor3 _i0 (i0, i1, cin, sum); 149 | and2 _i1 (i0, i1, t0); 150 | and2 _i2 (i1, cin, t1); 151 | and2 _i3 (cin, i0, t2); 152 | or3 _i4 (t0, t1, t2, cout); 153 | endmodule 154 | 155 | module addsub (input wire addsub, i0, i1, cin, output wire sumdiff, cout); 156 | wire t; 157 | fa _i0 (i0, t, cin, sumdiff, cout); 158 | xor2 _i1 (i1, addsub, t); 159 | endmodule 160 | -------------------------------------------------------------------------------- /Control Logic/mproc.v: -------------------------------------------------------------------------------- 1 | module nor5 (input wire [0:4] i, output wire o); 2 | wire t; 3 | or3 or3_0 (i[0], i[1], i[2], t); 4 | nor3 nor3_0 (t, i[3], i[4], o); 5 | endmodule 6 | 7 | module ir (input wire clk, reset, load, input wire [15:0] din, output wire [15:0] dout); 8 | dfrl dfrl_0 (clk, reset, load, din['h0], dout['h0]); 9 | dfrl dfrl_1 (clk, reset, load, din['h1], dout['h1]); 10 | dfrl dfrl_2 (clk, reset, load, din['h2], dout['h2]); 11 | dfrl dfrl_3 (clk, reset, load, din['h3], dout['h3]); 12 | dfrl dfrl_4 (clk, reset, load, din['h4], dout['h4]); 13 | dfrl dfrl_5 (clk, reset, load, din['h5], dout['h5]); 14 | dfrl dfrl_6 (clk, reset, load, din['h6], dout['h6]); 15 | dfrl dfrl_7 (clk, reset, load, din['h7], dout['h7]); 16 | dfrl dfrl_8 (clk, reset, load, din['h8], dout['h8]); 17 | dfrl dfrl_9 (clk, reset, load, din['h9], dout['h9]); 18 | dfrl dfrl_a (clk, reset, load, din['ha], dout['ha]); 19 | dfrl dfrl_b (clk, reset, load, din['hb], dout['hb]); 20 | dfrl dfrl_c (clk, reset, load, din['hc], dout['hc]); 21 | dfrl dfrl_d (clk, reset, load, din['hd], dout['hd]); 22 | dfrl dfrl_e (clk, reset, load, din['he], dout['he]); 23 | dfrl dfrl_f (clk, reset, load, din['hf], dout['hf]); 24 | endmodule 25 | 26 | module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, 27 | output wire [1:0] op, output wire sel, jump, pc_inc, load_ir, wr_reg); 28 | wire s, t, u, v, w, ld_ins_, ld_ins, pc_inc1, pc_inc2, wr_reg1, wr_reg2; 29 | 30 | assign rd_addr_a[0] = cur_ins[0]; 31 | assign rd_addr_a[1] = cur_ins[1]; 32 | assign rd_addr_a[2] = cur_ins[2]; 33 | assign rd_addr_b[0] = cur_ins[3]; 34 | assign rd_addr_b[1] = cur_ins[4]; 35 | assign rd_addr_b[2] = cur_ins[5]; 36 | assign wr_addr[0] = cur_ins[6]; 37 | assign wr_addr[1] = cur_ins[7]; 38 | assign wr_addr[2] = cur_ins[8]; 39 | assign op[0] = cur_ins[9]; 40 | assign op[1] = cur_ins[10]; 41 | wire t1,t2,t3; 42 | or3 o1(cur_ins[11],cur_ins[12],cur_ins[13],t1); 43 | or3 o2(cur_ins[14],cur_ins[15],t1,t2); 44 | invert o3(t2,t3); 45 | dfsl g1(clk,reset,1'b1,pc_inc,load_ir); 46 | dfrl g2(clk,reset,1'b1,load_ir,pc_inc); 47 | and2 o4(pc_inc, t3,wr_reg); 48 | endmodule 49 | 50 | module mproc (input wire clk, reset, input wire [15:0] d_in, output wire [6:0] addr, 51 | output wire [15:0] d_out); 52 | wire pc_inc, cout, cout_, sub, sel, sel_addr; wire [2:0] rd_addr_a, 53 | rd_addr_b, wr_addr; wire [1:0] op; wire [8:0] _addr; 54 | wire [15:0] cur_ins, d_out_a, d_out_b; 55 | 56 | and2 and2_0 (jump, cout, sub); 57 | pc pc_0 (clk, reset, pc_inc, 1'b0, sub, {8'b0, cur_ins[7:0]}, {_addr, addr}); 58 | ir ir_0 (clk, reset, load_ir, d_in, cur_ins); 59 | control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, sel, jump, pc_inc, load_ir, wr_reg); 60 | reg_alu reg_alu_0 (clk, reset, sel, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, d_in, d_out_a, d_out_b, cout); 61 | assign d_out = d_out_a; 62 | endmodule 63 | -------------------------------------------------------------------------------- /Control Logic/mproc_mem.v: -------------------------------------------------------------------------------- 1 | module ram_128_16 (input wire clk, reset, wr, input wire [6:0] addr, input wire [15:0] din, output wire [15:0] dout); 2 | reg [0:127] ram [15:0]; 3 | 4 | initial begin 5 | ram[0]=16'b10xxxxx000xxxxxx; // load r0, 1 6 | ram[1]=16'h01; 7 | ram[2]=16'b10xxxxx001xxxxxx; // load r1, 21 8 | ram[3]=16'h15; 9 | ram[4]=16'b10xxxxx010xxxxxx; // load r2, 1 10 | ram[5]=16'h01; 11 | ram[6]=16'b10xxxxx011xxxxxx; // load r3, 1 12 | ram[7]=16'h01; 13 | ram[8]=16'b0000000100010011; // add r4, r2, r3 14 | ram[9]=16'b0000010010011011; // move r2, r3 (and r2, r3, r3) 15 | ram[10]=16'b0000010011100100; // move r3, r4 (and r3, r4, r4) 16 | ram[11]=16'b0000001001000001; // sub r1, r0, r1 17 | ram[12]=16'b01xxxxxx00000101; // jbc ram[8] 18 | ram[13]=16'b0000010000100100; // move r0, r4 (and r0, r4, r4) 19 | end 20 | always @(wr) ram[addr]=din; 21 | assign dout=ram[addr]; 22 | endmodule 23 | 24 | module mproc_mem (input wire clk, reset); 25 | wire wr; wire [6:0] addr; wire [15:0] d_in, d_out; 26 | 27 | ram_128_16 ram_128_16_0 (clk, reset, 1'b0, addr, d_out, d_in); 28 | mproc mproc_0 (clk, reset, d_in, addr, d_out); 29 | endmodule 30 | -------------------------------------------------------------------------------- /Control Logic/pc.v: -------------------------------------------------------------------------------- 1 | module pc_slice (input wire clk, reset, cin, load, inc, sub, offset, 2 | output wire cout, pc); 3 | wire in, inc_; 4 | invert invert_0 (inc, inc_); 5 | and2 and2_0 (offset, inc_, t); 6 | addsub addsub_0 (sub, pc, t, cin, in, cout); 7 | dfrl dfrl_0 (clk, reset, load, in, pc); 8 | endmodule 9 | 10 | module pc_slice0 (input wire clk, reset, cin, load, inc, sub, offset, 11 | output wire cout, pc); 12 | wire in; 13 | or2 or2_0 (offset, inc, t); 14 | addsub addsub_0 (sub, pc, t, cin, in, cout); 15 | dfrl dfrl_0 (clk, reset, load, in, pc); 16 | endmodule 17 | 18 | module pc (input wire clk, reset, inc, add, sub, input wire [15:0] offset, 19 | output wire [15:0] pc); 20 | input wire load; input wire [15:0] c; 21 | or3 or3_0 (inc, add, sub, load); 22 | pc_slice0 pc_slice_0 (clk, reset, sub, load, inc, sub, offset[0], c[0], pc[0]); 23 | pc_slice pc_slice_1 (clk, reset, c[0], load, inc, sub, offset[1], c[1], pc[1]); 24 | pc_slice pc_slice_2 (clk, reset, c[1], load, inc, sub, offset[2], c[2], pc[2]); 25 | pc_slice pc_slice_3 (clk, reset, c[2], load, inc, sub, offset[3], c[3], pc[3]); 26 | pc_slice pc_slice_4 (clk, reset, c[3], load, inc, sub, offset[4], c[4], pc[4]); 27 | pc_slice pc_slice_5 (clk, reset, c[4], load, inc, sub, offset[5], c[5], pc[5]); 28 | pc_slice pc_slice_6 (clk, reset, c[5], load, inc, sub, offset[6], c[6], pc[6]); 29 | pc_slice pc_slice_7 (clk, reset, c[6], load, inc, sub, offset[7], c[7], pc[7]); 30 | pc_slice pc_slice_8 (clk, reset, c[7], load, inc, sub, offset[8], c[8], pc[8]); 31 | pc_slice pc_slice_9 (clk, reset, c[8], load, inc, sub, offset[9], c[9], pc[9]); 32 | pc_slice pc_slice_10 (clk, reset, c[9], load, inc, sub, offset[10], c[10], pc[10]); 33 | pc_slice pc_slice_11 (clk, reset, c[10], load, inc, sub, offset[11], c[11], pc[11]); 34 | pc_slice pc_slice_12 (clk, reset, c[11], load, inc, sub, offset[12], c[12], pc[12]); 35 | pc_slice pc_slice_13 (clk, reset, c[12], load, inc, sub, offset[13], c[13], pc[13]); 36 | pc_slice pc_slice_14 (clk, reset, c[13], load, inc, sub, offset[14], c[14], pc[14]); 37 | pc_slice pc_slice_15 (clk, reset, c[14], load, inc, sub, offset[15], c[15], pc[15]); 38 | endmodule 39 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Verilog 2 | 3 | This repo contains basic code snippets of verilog, which is a hardware description language(HDL) used to model electronic systems. 4 | 5 | ## Compile and Run the code 6 | The following command is to compile main file and test bench file. 7 | 8 | ``` 9 | iverilog -o
10 | vvp 11 | ``` 12 | After running the above code you will able to see vvp output 13 | 14 | For GTK wave 15 | ``` 16 | gtkwave 17 | ``` 18 | -------------------------------------------------------------------------------- /week-1/and_gate/and.v: -------------------------------------------------------------------------------- 1 | module andgate (a,b,y); 2 | input a,b; 3 | output y; 4 | assign y= a & b; 5 | endmodule 6 | 7 | 8 | -------------------------------------------------------------------------------- /week-1/and_gate/and_tb.v: -------------------------------------------------------------------------------- 1 | module andgate_tb; 2 | wire t_y; 3 | reg t_a, t_b; 4 | andgate my_gate( .a(t_a), .b(t_b), .y(t_y)); 5 | initial 6 | begin 7 | $dumpfile("and_tb.vcd"); 8 | $dumpvars(0, andgate_tb); 9 | $monitor(t_a, t_b, t_y); 10 | t_a = 1'b0; 11 | t_b = 1'b0; 12 | #5 13 | t_a = 1'b0; 14 | t_b = 1'b1; 15 | #5 16 | t_a = 1'b1; 17 | t_b = 1'b0; 18 | #5 19 | t_a = 1'b1; 20 | t_b = 1'b1; 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /week-1/and_gate/and_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Aug 29 13:26:08 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module andgate_tb $end 11 | $var wire 1 ! t_y $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $scope module my_gate $end 15 | $var wire 1 " a $end 16 | $var wire 1 # b $end 17 | $var wire 1 ! y $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | 0# 24 | 0" 25 | 0! 26 | $end 27 | #5 28 | 1# 29 | #10 30 | 0# 31 | 1" 32 | #15 33 | 1! 34 | 1# 35 | -------------------------------------------------------------------------------- /week-1/nand_gate/nand.v: -------------------------------------------------------------------------------- 1 | module nandgate(a,b,y); 2 | input a,b; 3 | output y; 4 | assign y = !(a&b); 5 | endmodule 6 | -------------------------------------------------------------------------------- /week-1/nand_gate/nand_tb.v: -------------------------------------------------------------------------------- 1 | module nandgate_tb; 2 | wire t_y; 3 | reg t_a, t_b; 4 | 5 | nandgate my_gate( .a(t_a), .b(t_b), .y(t_y)); 6 | 7 | initial 8 | begin 9 | 10 | $dumpfile("nand_tb.vcd"); 11 | $dumpvars(0, nandgate_tb); 12 | 13 | $monitor(t_a,t_b,t_y); 14 | 15 | 16 | t_a = 1'b0; 17 | t_b = 1'b0; 18 | 19 | #5 20 | t_a = 1'b0; 21 | t_b = 1'b1; 22 | 23 | #5 24 | t_a = 1'b1; 25 | t_b = 1'b0; 26 | 27 | #5 28 | t_a = 1'b1; 29 | t_b = 1'b1; 30 | 31 | end 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /week-1/nand_gate/nand_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Aug 29 13:27:33 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module nandgate_tb $end 11 | $var wire 1 ! t_y $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $scope module my_gate $end 15 | $var wire 1 " a $end 16 | $var wire 1 # b $end 17 | $var wire 1 ! y $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | 0# 24 | 0" 25 | 1! 26 | $end 27 | #5 28 | 1# 29 | #10 30 | 0# 31 | 1" 32 | #15 33 | 0! 34 | 1# 35 | -------------------------------------------------------------------------------- /week-1/nor_gate/nor.v: -------------------------------------------------------------------------------- 1 | module norgate(a,b,y); 2 | input a,b; 3 | output y; 4 | assign y = !(a|b); 5 | endmodule 6 | -------------------------------------------------------------------------------- /week-1/nor_gate/nor_tb.v: -------------------------------------------------------------------------------- 1 | module norgate_tb; 2 | wire t_y; 3 | reg t_a, t_b; 4 | 5 | norgate my_gate( .a(t_a), .b(t_b), .y(t_y)); 6 | 7 | initial 8 | begin 9 | 10 | $dumpfile("nor_tb.vcd"); 11 | $dumpvars(0, norgate_tb); 12 | 13 | $monitor(t_a, t_b, t_y); 14 | 15 | t_a = 1'b0; 16 | t_b = 1'b0; 17 | 18 | #5 19 | t_a = 1'b0; 20 | t_b = 1'b1; 21 | 22 | #5 23 | t_a = 1'b1; 24 | t_b = 1'b0; 25 | 26 | #5 27 | t_a = 1'b1; 28 | t_b = 1'b1; 29 | 30 | end 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /week-1/nor_gate/nor_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Aug 29 13:28:33 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module norgate_tb $end 11 | $var wire 1 ! t_y $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $scope module my_gate $end 15 | $var wire 1 " a $end 16 | $var wire 1 # b $end 17 | $var wire 1 ! y $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | 0# 24 | 0" 25 | 1! 26 | $end 27 | #5 28 | 0! 29 | 1# 30 | #10 31 | 0# 32 | 1" 33 | #15 34 | 1# 35 | -------------------------------------------------------------------------------- /week-1/not_gate/not.v: -------------------------------------------------------------------------------- 1 | module notgate (a, y); 2 | input a; 3 | output y; 4 | assign y = !a; 5 | endmodule 6 | -------------------------------------------------------------------------------- /week-1/not_gate/not_tb.v: -------------------------------------------------------------------------------- 1 | module notgate_tb; 2 | wire t_y; 3 | reg t_a; 4 | 5 | notgate my_gate( .a(t_a), .y(t_y)); 6 | 7 | initial 8 | begin 9 | $dumpfile("not_tb.vcd"); 10 | $dumpvars(0, notgate_tb); 11 | 12 | $monitor(t_a, t_y); 13 | 14 | t_a = 1'b0; 15 | 16 | #10 17 | t_a = 1'b1; 18 | 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /week-1/not_gate/not_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Aug 29 13:30:14 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module notgate_tb $end 11 | $var wire 1 ! t_y $end 12 | $var reg 1 " t_a $end 13 | $scope module my_gate $end 14 | $var wire 1 " a $end 15 | $var wire 1 ! y $end 16 | $upscope $end 17 | $upscope $end 18 | $enddefinitions $end 19 | #0 20 | $dumpvars 21 | 0" 22 | 1! 23 | $end 24 | #10 25 | 0! 26 | 1" 27 | -------------------------------------------------------------------------------- /week-1/or_gate/or.v: -------------------------------------------------------------------------------- 1 | module orgate(a, b, y); 2 | input a, b; 3 | output y; 4 | assign y = a|b; 5 | endmodule 6 | -------------------------------------------------------------------------------- /week-1/or_gate/or_tb.v: -------------------------------------------------------------------------------- 1 | module orgate_tb; 2 | wire t_y; 3 | reg t_a, t_b; 4 | 5 | orgate my_gate( .a(t_a), .b(t_b), .y(t_y)); 6 | 7 | initial 8 | begin 9 | $dumpfile("or_tb.vcd"); 10 | $dumpvars(0, orgate_tb); 11 | 12 | 13 | $monitor(t_a,t_b,t_y); 14 | 15 | t_a=1'b0; 16 | t_b=1'b0; 17 | 18 | #5 19 | t_a=1'b0; 20 | t_b=1'b1; 21 | 22 | #5 23 | t_a=1'b1; 24 | t_b=1'b0; 25 | 26 | #5 27 | t_a=1'b1; 28 | t_b=1'b1; 29 | 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /week-1/or_gate/or_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Aug 29 13:31:16 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module orgate_tb $end 11 | $var wire 1 ! t_y $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $scope module my_gate $end 15 | $var wire 1 " a $end 16 | $var wire 1 # b $end 17 | $var wire 1 ! y $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | 0# 24 | 0" 25 | 0! 26 | $end 27 | #5 28 | 1! 29 | 1# 30 | #10 31 | 0# 32 | 1" 33 | #15 34 | 1# 35 | -------------------------------------------------------------------------------- /week-1/xnor_gate/xnor.v: -------------------------------------------------------------------------------- 1 | module xnorgate(a,b,y); 2 | input a, b; 3 | output y; 4 | assign y = (!a&!b)|(a&b); 5 | endmodule 6 | -------------------------------------------------------------------------------- /week-1/xnor_gate/xnor_tb.v: -------------------------------------------------------------------------------- 1 | module xnorgate_tb; 2 | wire t_y; 3 | reg t_a, t_b; 4 | 5 | xnorgate my_gate( .a(t_a), .b(t_b), .y(t_y)); 6 | 7 | initial 8 | begin 9 | $dumpfile("xnor_tb.vcd"); 10 | $dumpvars(0, xnorgate_tb); 11 | 12 | 13 | $monitor(t_a, t_b, t_y); 14 | 15 | t_a = 1'b0; 16 | t_b = 1'b0; 17 | 18 | #5 19 | t_a = 1'b0; 20 | t_b = 1'b1; 21 | 22 | #5 23 | t_a = 1'b1; 24 | t_b = 1'b0; 25 | 26 | #5 27 | t_a = 1'b1; 28 | t_b = 1'b1; 29 | 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /week-1/xnor_gate/xnor_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Aug 29 13:32:49 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module xnorgate_tb $end 11 | $var wire 1 ! t_y $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $scope module my_gate $end 15 | $var wire 1 " a $end 16 | $var wire 1 # b $end 17 | $var wire 1 ! y $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | 0# 24 | 0" 25 | 1! 26 | $end 27 | #5 28 | 0! 29 | 1# 30 | #10 31 | 0# 32 | 1" 33 | #15 34 | 1! 35 | 1# 36 | -------------------------------------------------------------------------------- /week-1/xor_gate/xor.v: -------------------------------------------------------------------------------- 1 | module xorgate(a,b,y); 2 | input a,b; 3 | output y; 4 | assign y = (a&!b)|(!a&b); 5 | endmodule 6 | -------------------------------------------------------------------------------- /week-1/xor_gate/xor_tb.v: -------------------------------------------------------------------------------- 1 | module xorgate_tb; 2 | wire t_y; 3 | reg t_a, t_b; 4 | 5 | xorgate my_gate( .a(t_a), .b(t_b), .y(t_y)); 6 | 7 | initial 8 | begin 9 | 10 | $dumpfile("xor_tb.vcd"); 11 | $dumpvars(0, xorgate_tb); 12 | 13 | $monitor(t_a, t_b, t_y); 14 | 15 | t_a = 1'b0; 16 | t_b = 1'b0; 17 | 18 | #5 19 | t_a = 1'b0; 20 | t_b = 1'b1; 21 | 22 | #5 23 | t_a = 1'b1; 24 | t_b = 1'b0; 25 | 26 | #5 27 | t_a = 1'b1; 28 | t_b = 1'b1; 29 | 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /week-1/xor_gate/xor_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Aug 29 13:33:47 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module xorgate_tb $end 11 | $var wire 1 ! t_y $end 12 | $var reg 1 " t_a $end 13 | $var reg 1 # t_b $end 14 | $scope module my_gate $end 15 | $var wire 1 " a $end 16 | $var wire 1 # b $end 17 | $var wire 1 ! y $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | 0# 24 | 0" 25 | 0! 26 | $end 27 | #5 28 | 1! 29 | 1# 30 | #10 31 | 0# 32 | 1" 33 | #15 34 | 0! 35 | 1# 36 | -------------------------------------------------------------------------------- /week-2/circuit-1/circuit: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x55fd8e3c2190 .scope module, "tb_simple_circuit" "tb_simple_circuit" 2 1; 11 | .timescale 0 0; 12 | v0x55fd8e3e8fc0_0 .var "A", 0 0; 13 | v0x55fd8e3e9080_0 .var "B", 0 0; 14 | v0x55fd8e3e9150_0 .var "C", 0 0; 15 | v0x55fd8e3e9250_0 .net "Y", 0 0, L_0x55fd8e3e9460; 1 drivers 16 | S_0x55fd8e3d32d0 .scope module, "M1" "simple_circuit" 2 5, 3 1 0, S_0x55fd8e3c2190; 17 | .timescale 0 0; 18 | .port_info 0 /INPUT 1 "A"; 19 | .port_info 1 /INPUT 1 "B"; 20 | .port_info 2 /INPUT 1 "C"; 21 | .port_info 3 /OUTPUT 1 "Y"; 22 | L_0x55fd8e3e9320 .functor AND 1, v0x55fd8e3e8fc0_0, v0x55fd8e3e9080_0, C4<1>, C4<1>; 23 | L_0x55fd8e3e9460 .functor OR 1, L_0x55fd8e3e9320, v0x55fd8e3e9150_0, C4<0>, C4<0>; 24 | v0x55fd8e3d3520_0 .net "A", 0 0, v0x55fd8e3e8fc0_0; 1 drivers 25 | v0x55fd8e3e8c10_0 .net "B", 0 0, v0x55fd8e3e9080_0; 1 drivers 26 | v0x55fd8e3e8cd0_0 .net "C", 0 0, v0x55fd8e3e9150_0; 1 drivers 27 | v0x55fd8e3e8d70_0 .net "Y", 0 0, L_0x55fd8e3e9460; alias, 1 drivers 28 | v0x55fd8e3e8e30_0 .net "w1", 0 0, L_0x55fd8e3e9320; 1 drivers 29 | .scope S_0x55fd8e3c2190; 30 | T_0 ; 31 | %pushi/vec4 0, 0, 1; 32 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 33 | %pushi/vec4 0, 0, 1; 34 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 35 | %pushi/vec4 0, 0, 1; 36 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 37 | %delay 20, 0; 38 | %pushi/vec4 0, 0, 1; 39 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 40 | %pushi/vec4 0, 0, 1; 41 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 42 | %pushi/vec4 1, 0, 1; 43 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 44 | %delay 20, 0; 45 | %pushi/vec4 0, 0, 1; 46 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 47 | %pushi/vec4 1, 0, 1; 48 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 49 | %pushi/vec4 0, 0, 1; 50 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 51 | %delay 20, 0; 52 | %pushi/vec4 0, 0, 1; 53 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 54 | %pushi/vec4 1, 0, 1; 55 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 56 | %pushi/vec4 1, 0, 1; 57 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 58 | %delay 20, 0; 59 | %pushi/vec4 1, 0, 1; 60 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 61 | %pushi/vec4 0, 0, 1; 62 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 63 | %pushi/vec4 0, 0, 1; 64 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 65 | %delay 20, 0; 66 | %pushi/vec4 1, 0, 1; 67 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 68 | %pushi/vec4 0, 0, 1; 69 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 70 | %pushi/vec4 1, 0, 1; 71 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 72 | %delay 20, 0; 73 | %pushi/vec4 1, 0, 1; 74 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 75 | %pushi/vec4 1, 0, 1; 76 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 77 | %pushi/vec4 0, 0, 1; 78 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 79 | %delay 20, 0; 80 | %pushi/vec4 1, 0, 1; 81 | %store/vec4 v0x55fd8e3e8fc0_0, 0, 1; 82 | %pushi/vec4 1, 0, 1; 83 | %store/vec4 v0x55fd8e3e9080_0, 0, 1; 84 | %pushi/vec4 1, 0, 1; 85 | %store/vec4 v0x55fd8e3e9150_0, 0, 1; 86 | %end; 87 | .thread T_0; 88 | .scope S_0x55fd8e3c2190; 89 | T_1 ; 90 | %vpi_call 2 32 "$monitor", "A=%b, B=%b, C=%b,Y=%b", v0x55fd8e3e8fc0_0, v0x55fd8e3e9080_0, v0x55fd8e3e9150_0, v0x55fd8e3e9250_0 {0 0 0}; 91 | %end; 92 | .thread T_1; 93 | .scope S_0x55fd8e3c2190; 94 | T_2 ; 95 | %vpi_call 2 36 "$dumpfile", "circuit1.vcd" {0 0 0}; 96 | %vpi_call 2 37 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55fd8e3c2190 {0 0 0}; 97 | %end; 98 | .thread T_2; 99 | # The file index is used to find the file name in the following table. 100 | :file_names 4; 101 | "N/A"; 102 | ""; 103 | "tb_circuit1.v"; 104 | "circuit1.v"; 105 | -------------------------------------------------------------------------------- /week-2/circuit-1/circuit-1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/week-2/circuit-1/circuit-1.png -------------------------------------------------------------------------------- /week-2/circuit-1/circuit1.v: -------------------------------------------------------------------------------- 1 | module simple_circuit(A,B,C,Y); 2 | input A,B,C; 3 | output Y; 4 | wire w1; 5 | assign w1= A&B; 6 | assign Y = w1|C; 7 | endmodule 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /week-2/circuit-1/circuit1.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Tue Aug 30 19:56:27 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module tb_simple_circuit $end 11 | $var wire 1 ! Y $end 12 | $var reg 1 " A $end 13 | $var reg 1 # B $end 14 | $var reg 1 $ C $end 15 | $scope module M1 $end 16 | $var wire 1 " A $end 17 | $var wire 1 # B $end 18 | $var wire 1 $ C $end 19 | $var wire 1 ! Y $end 20 | $var wire 1 % w1 $end 21 | $upscope $end 22 | $upscope $end 23 | $enddefinitions $end 24 | #0 25 | $dumpvars 26 | 0% 27 | 0$ 28 | 0# 29 | 0" 30 | 0! 31 | $end 32 | #20 33 | 1! 34 | 1$ 35 | #40 36 | 0! 37 | 0$ 38 | 1# 39 | #60 40 | 1! 41 | 1$ 42 | #80 43 | 0! 44 | 0$ 45 | 0# 46 | 1" 47 | #100 48 | 1! 49 | 1$ 50 | #120 51 | 1% 52 | 0$ 53 | 1# 54 | #140 55 | 1$ 56 | -------------------------------------------------------------------------------- /week-2/circuit-1/tb_circuit1.v: -------------------------------------------------------------------------------- 1 | module tb_simple_circuit; 2 | 3 | reg A,B,C; 4 | 5 | simple_circuit M1(A,B,C,Y); 6 | 7 | initial 8 | 9 | begin 10 | 11 | A=1'b0 ; B=1'b0 ; C=1'b0; 12 | #20 13 | A=1'b0 ; B=1'b0 ; C=1'b1; 14 | #20 15 | A=1'b0 ; B=1'b1 ; C=1'b0; 16 | #20 17 | A=1'b0 ; B=1'b1 ; C=1'b1; 18 | #20 19 | A=1'b1 ; B=1'b0 ; C=1'b0; 20 | #20 21 | A=1'b1 ; B=1'b0 ; C=1'b1; 22 | #20 23 | A=1'b1 ; B=1'b1 ; C=1'b0; 24 | #20 25 | A=1'b1 ; B=1'b1 ; C=1'b1; 26 | 27 | end 28 | 29 | 30 | initial 31 | begin 32 | $monitor("A=%b, B=%b, C=%b,Y=%b", A,B,C,Y); 33 | end 34 | initial 35 | begin 36 | $dumpfile ("circuit1.vcd"); 37 | $dumpvars (0, tb_simple_circuit); 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /week-2/circuit-2/circuit-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/week-2/circuit-2/circuit-2.png -------------------------------------------------------------------------------- /week-2/circuit-2/circuit1: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x55580dca2f70 .scope module, "tb_simple_circuit" "tb_simple_circuit" 2 1; 11 | .timescale 0 0; 12 | v0x55580dcca540_0 .var "A", 0 0; 13 | v0x55580dcca600_0 .var "B", 0 0; 14 | v0x55580dcca6a0_0 .var "C", 0 0; 15 | v0x55580dcca740_0 .net "Y", 0 0, L_0x55580dccaad0; 1 drivers 16 | S_0x55580dcb3a90 .scope module, "M1" "simple_circuit" 2 5, 3 1 0, S_0x55580dca2f70; 17 | .timescale 0 0; 18 | .port_info 0 /INPUT 1 "A2"; 19 | .port_info 1 /INPUT 1 "B2"; 20 | .port_info 2 /INPUT 1 "C2"; 21 | .port_info 3 /OUTPUT 1 "Y"; 22 | L_0x55580dcca810 .functor AND 1, v0x55580dcca6a0_0, v0x55580dcca600_0, C4<1>, C4<1>; 23 | L_0x55580dcca950 .functor OR 1, v0x55580dcca540_0, L_0x55580dcca810, C4<0>, C4<0>; 24 | L_0x55580dccaa60 .functor AND 1, v0x55580dcca600_0, v0x55580dcca540_0, C4<1>, C4<1>; 25 | L_0x55580dccaad0 .functor OR 1, L_0x55580dcca950, L_0x55580dccaa60, C4<0>, C4<0>; 26 | v0x55580dcb3ce0_0 .net "A2", 0 0, v0x55580dcca540_0; 1 drivers 27 | v0x55580dcca010_0 .net "B2", 0 0, v0x55580dcca600_0; 1 drivers 28 | v0x55580dcca0d0_0 .net "C2", 0 0, v0x55580dcca6a0_0; 1 drivers 29 | v0x55580dcca170_0 .net "Y", 0 0, L_0x55580dccaad0; alias, 1 drivers 30 | v0x55580dcca230_0 .net "w1", 0 0, L_0x55580dcca810; 1 drivers 31 | v0x55580dcca340_0 .net "w2", 0 0, L_0x55580dcca950; 1 drivers 32 | v0x55580dcca400_0 .net "w3", 0 0, L_0x55580dccaa60; 1 drivers 33 | .scope S_0x55580dca2f70; 34 | T_0 ; 35 | %pushi/vec4 0, 0, 1; 36 | %store/vec4 v0x55580dcca540_0, 0, 1; 37 | %pushi/vec4 0, 0, 1; 38 | %store/vec4 v0x55580dcca600_0, 0, 1; 39 | %pushi/vec4 0, 0, 1; 40 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 41 | %delay 20, 0; 42 | %pushi/vec4 0, 0, 1; 43 | %store/vec4 v0x55580dcca540_0, 0, 1; 44 | %pushi/vec4 0, 0, 1; 45 | %store/vec4 v0x55580dcca600_0, 0, 1; 46 | %pushi/vec4 1, 0, 1; 47 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 48 | %delay 20, 0; 49 | %pushi/vec4 0, 0, 1; 50 | %store/vec4 v0x55580dcca540_0, 0, 1; 51 | %pushi/vec4 1, 0, 1; 52 | %store/vec4 v0x55580dcca600_0, 0, 1; 53 | %pushi/vec4 0, 0, 1; 54 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 55 | %delay 20, 0; 56 | %pushi/vec4 0, 0, 1; 57 | %store/vec4 v0x55580dcca540_0, 0, 1; 58 | %pushi/vec4 1, 0, 1; 59 | %store/vec4 v0x55580dcca600_0, 0, 1; 60 | %pushi/vec4 1, 0, 1; 61 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 62 | %delay 20, 0; 63 | %pushi/vec4 1, 0, 1; 64 | %store/vec4 v0x55580dcca540_0, 0, 1; 65 | %pushi/vec4 0, 0, 1; 66 | %store/vec4 v0x55580dcca600_0, 0, 1; 67 | %pushi/vec4 0, 0, 1; 68 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 69 | %delay 20, 0; 70 | %pushi/vec4 1, 0, 1; 71 | %store/vec4 v0x55580dcca540_0, 0, 1; 72 | %pushi/vec4 0, 0, 1; 73 | %store/vec4 v0x55580dcca600_0, 0, 1; 74 | %pushi/vec4 1, 0, 1; 75 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 76 | %delay 20, 0; 77 | %pushi/vec4 1, 0, 1; 78 | %store/vec4 v0x55580dcca540_0, 0, 1; 79 | %pushi/vec4 1, 0, 1; 80 | %store/vec4 v0x55580dcca600_0, 0, 1; 81 | %pushi/vec4 0, 0, 1; 82 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 83 | %delay 20, 0; 84 | %pushi/vec4 1, 0, 1; 85 | %store/vec4 v0x55580dcca540_0, 0, 1; 86 | %pushi/vec4 1, 0, 1; 87 | %store/vec4 v0x55580dcca600_0, 0, 1; 88 | %pushi/vec4 1, 0, 1; 89 | %store/vec4 v0x55580dcca6a0_0, 0, 1; 90 | %end; 91 | .thread T_0; 92 | .scope S_0x55580dca2f70; 93 | T_1 ; 94 | %vpi_call 2 32 "$monitor", "A2=%b, B2=%b, C2=%b,Y=%b", v0x55580dcca540_0, v0x55580dcca600_0, v0x55580dcca6a0_0, v0x55580dcca740_0 {0 0 0}; 95 | %end; 96 | .thread T_1; 97 | .scope S_0x55580dca2f70; 98 | T_2 ; 99 | %vpi_call 2 36 "$dumpfile", "circuit2.vcd" {0 0 0}; 100 | %vpi_call 2 37 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55580dca2f70 {0 0 0}; 101 | %end; 102 | .thread T_2; 103 | # The file index is used to find the file name in the following table. 104 | :file_names 4; 105 | "N/A"; 106 | ""; 107 | "tb_circuit2.v"; 108 | "circuit2.v"; 109 | -------------------------------------------------------------------------------- /week-2/circuit-2/circuit2.v: -------------------------------------------------------------------------------- 1 | module simple_circuit(A2,B2,C2,Y); 2 | output Y; 3 | input A2,B2,C2; 4 | wire w1,w2,w3; 5 | assign w1= C2&B2; 6 | assign w2= A2|w1; 7 | assign w3= B2&A2; 8 | assign Y= w2|w3; 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /week-2/circuit-2/circuit2.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Tue Aug 30 19:54:53 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module tb_simple_circuit $end 11 | $var wire 1 ! Y $end 12 | $var reg 1 " A $end 13 | $var reg 1 # B $end 14 | $var reg 1 $ C $end 15 | $scope module M1 $end 16 | $var wire 1 " A2 $end 17 | $var wire 1 # B2 $end 18 | $var wire 1 $ C2 $end 19 | $var wire 1 ! Y $end 20 | $var wire 1 % w1 $end 21 | $var wire 1 & w2 $end 22 | $var wire 1 ' w3 $end 23 | $upscope $end 24 | $upscope $end 25 | $enddefinitions $end 26 | #0 27 | $dumpvars 28 | 0' 29 | 0& 30 | 0% 31 | 0$ 32 | 0# 33 | 0" 34 | 0! 35 | $end 36 | #20 37 | 1$ 38 | #40 39 | 0$ 40 | 1# 41 | #60 42 | 1! 43 | 1& 44 | 1% 45 | 1$ 46 | #80 47 | 0% 48 | 0$ 49 | 0# 50 | 1" 51 | #100 52 | 1$ 53 | #120 54 | 1' 55 | 0$ 56 | 1# 57 | #140 58 | 1% 59 | 1$ 60 | -------------------------------------------------------------------------------- /week-2/circuit-2/tb_circuit2.v: -------------------------------------------------------------------------------- 1 | module tb_simple_circuit; 2 | 3 | reg A,B,C; 4 | 5 | simple_circuit M1(A,B,C,Y); 6 | 7 | initial 8 | 9 | begin 10 | 11 | A=1'b0 ; B=1'b0 ; C=1'b0; 12 | #20 13 | A=1'b0 ; B=1'b0 ; C=1'b1; 14 | #20 15 | A=1'b0 ; B=1'b1 ; C=1'b0; 16 | #20 17 | A=1'b0 ; B=1'b1 ; C=1'b1; 18 | #20 19 | A=1'b1 ; B=1'b0 ; C=1'b0; 20 | #20 21 | A=1'b1 ; B=1'b0 ; C=1'b1; 22 | #20 23 | A=1'b1 ; B=1'b1 ; C=1'b0; 24 | #20 25 | A=1'b1 ; B=1'b1 ; C=1'b1; 26 | 27 | end 28 | 29 | 30 | initial 31 | begin 32 | $monitor("A2=%b, B2=%b, C2=%b,Y=%b", A,B,C,Y); 33 | end 34 | initial 35 | begin 36 | $dumpfile ("circuit2.vcd"); 37 | $dumpvars (0, tb_simple_circuit); 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /week-2/full_adder/full_adder: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x55abce20bba0 .scope module, "full_adder_tb" "full_adder_tb" 2 1; 11 | .timescale 0 0; 12 | v0x55abce239730_0 .var "t_a", 0 0; 13 | v0x55abce2397f0_0 .var "t_b", 0 0; 14 | v0x55abce2398c0_0 .var "t_c", 0 0; 15 | v0x55abce2399c0_0 .net "t_x", 0 0, L_0x55abce23acc0; 1 drivers 16 | v0x55abce239a90_0 .net "t_y", 0 0, L_0x55abce23a8d0; 1 drivers 17 | S_0x55abce218120 .scope module, "my_gate" "full_adder" 2 4, 3 1 0, S_0x55abce20bba0; 18 | .timescale 0 0; 19 | .port_info 0 /INPUT 1 "a"; 20 | .port_info 1 /INPUT 1 "b"; 21 | .port_info 2 /INPUT 1 "c"; 22 | .port_info 3 /OUTPUT 1 "y"; 23 | .port_info 4 /OUTPUT 1 "x"; 24 | L_0x55abce239d40 .functor AND 1, L_0x55abce239b30, L_0x55abce239c50, C4<1>, C4<1>; 25 | L_0x55abce239e50 .functor AND 1, L_0x55abce239d40, v0x55abce2398c0_0, C4<1>, C4<1>; 26 | L_0x55abce23a000 .functor AND 1, L_0x55abce239f60, v0x55abce2397f0_0, C4<1>, C4<1>; 27 | L_0x55abce23a0c0 .functor AND 1, L_0x55abce23a000, v0x55abce2398c0_0, C4<1>, C4<1>; 28 | L_0x55abce23a1b0 .functor OR 1, L_0x55abce239e50, L_0x55abce23a0c0, C4<0>, C4<0>; 29 | L_0x55abce23a390 .functor AND 1, v0x55abce239730_0, L_0x55abce23a2c0, C4<1>, C4<1>; 30 | L_0x55abce23a570 .functor AND 1, L_0x55abce23a390, L_0x55abce23a440, C4<1>, C4<1>; 31 | L_0x55abce23a5e0 .functor OR 1, L_0x55abce23a1b0, L_0x55abce23a570, C4<0>, C4<0>; 32 | L_0x55abce23a740 .functor AND 1, v0x55abce239730_0, v0x55abce2397f0_0, C4<1>, C4<1>; 33 | L_0x55abce23a7b0 .functor AND 1, L_0x55abce23a740, v0x55abce2398c0_0, C4<1>, C4<1>; 34 | L_0x55abce23a8d0 .functor OR 1, L_0x55abce23a5e0, L_0x55abce23a7b0, C4<0>, C4<0>; 35 | L_0x55abce23a9e0 .functor AND 1, v0x55abce239730_0, v0x55abce2397f0_0, C4<1>, C4<1>; 36 | L_0x55abce23aac0 .functor AND 1, v0x55abce239730_0, v0x55abce2398c0_0, C4<1>, C4<1>; 37 | L_0x55abce23ab30 .functor OR 1, L_0x55abce23a9e0, L_0x55abce23aac0, C4<0>, C4<0>; 38 | L_0x55abce23aa50 .functor AND 1, v0x55abce2397f0_0, v0x55abce2398c0_0, C4<1>, C4<1>; 39 | L_0x55abce23acc0 .functor OR 1, L_0x55abce23ab30, L_0x55abce23aa50, C4<0>, C4<0>; 40 | v0x55abce218300_0 .net *"_ivl_1", 0 0, L_0x55abce239b30; 1 drivers 41 | v0x55abce238360_0 .net *"_ivl_10", 0 0, L_0x55abce23a000; 1 drivers 42 | v0x55abce238440_0 .net *"_ivl_12", 0 0, L_0x55abce23a0c0; 1 drivers 43 | v0x55abce238500_0 .net *"_ivl_14", 0 0, L_0x55abce23a1b0; 1 drivers 44 | v0x55abce2385e0_0 .net *"_ivl_17", 0 0, L_0x55abce23a2c0; 1 drivers 45 | v0x55abce2386f0_0 .net *"_ivl_18", 0 0, L_0x55abce23a390; 1 drivers 46 | v0x55abce2387d0_0 .net *"_ivl_21", 0 0, L_0x55abce23a440; 1 drivers 47 | v0x55abce238890_0 .net *"_ivl_22", 0 0, L_0x55abce23a570; 1 drivers 48 | v0x55abce238970_0 .net *"_ivl_24", 0 0, L_0x55abce23a5e0; 1 drivers 49 | v0x55abce238a50_0 .net *"_ivl_26", 0 0, L_0x55abce23a740; 1 drivers 50 | v0x55abce238b30_0 .net *"_ivl_28", 0 0, L_0x55abce23a7b0; 1 drivers 51 | v0x55abce238c10_0 .net *"_ivl_3", 0 0, L_0x55abce239c50; 1 drivers 52 | v0x55abce238cd0_0 .net *"_ivl_32", 0 0, L_0x55abce23a9e0; 1 drivers 53 | v0x55abce238db0_0 .net *"_ivl_34", 0 0, L_0x55abce23aac0; 1 drivers 54 | v0x55abce238e90_0 .net *"_ivl_36", 0 0, L_0x55abce23ab30; 1 drivers 55 | v0x55abce238f70_0 .net *"_ivl_38", 0 0, L_0x55abce23aa50; 1 drivers 56 | v0x55abce239050_0 .net *"_ivl_4", 0 0, L_0x55abce239d40; 1 drivers 57 | v0x55abce239130_0 .net *"_ivl_6", 0 0, L_0x55abce239e50; 1 drivers 58 | v0x55abce239210_0 .net *"_ivl_9", 0 0, L_0x55abce239f60; 1 drivers 59 | v0x55abce2392d0_0 .net "a", 0 0, v0x55abce239730_0; 1 drivers 60 | v0x55abce239390_0 .net "b", 0 0, v0x55abce2397f0_0; 1 drivers 61 | v0x55abce239450_0 .net "c", 0 0, v0x55abce2398c0_0; 1 drivers 62 | v0x55abce239510_0 .net "x", 0 0, L_0x55abce23acc0; alias, 1 drivers 63 | v0x55abce2395d0_0 .net "y", 0 0, L_0x55abce23a8d0; alias, 1 drivers 64 | L_0x55abce239b30 .reduce/nor v0x55abce239730_0; 65 | L_0x55abce239c50 .reduce/nor v0x55abce2397f0_0; 66 | L_0x55abce239f60 .reduce/nor v0x55abce239730_0; 67 | L_0x55abce23a2c0 .reduce/nor v0x55abce2397f0_0; 68 | L_0x55abce23a440 .reduce/nor v0x55abce2398c0_0; 69 | .scope S_0x55abce20bba0; 70 | T_0 ; 71 | %vpi_call 2 7 "$dumpfile", "full_adder_tb.vcd" {0 0 0}; 72 | %vpi_call 2 8 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55abce20bba0 {0 0 0}; 73 | %vpi_call 2 9 "$monitor", "A=%b, B=%b, C=%b, Y=%b", v0x55abce239730_0, v0x55abce2397f0_0, v0x55abce2398c0_0, v0x55abce239a90_0 {0 0 0}; 74 | %vpi_call 2 10 "$display", "Sum Output" {0 0 0}; 75 | %pushi/vec4 0, 0, 1; 76 | %store/vec4 v0x55abce239730_0, 0, 1; 77 | %pushi/vec4 0, 0, 1; 78 | %store/vec4 v0x55abce2397f0_0, 0, 1; 79 | %pushi/vec4 0, 0, 1; 80 | %store/vec4 v0x55abce2398c0_0, 0, 1; 81 | %delay 5, 0; 82 | %pushi/vec4 0, 0, 1; 83 | %store/vec4 v0x55abce239730_0, 0, 1; 84 | %pushi/vec4 0, 0, 1; 85 | %store/vec4 v0x55abce2397f0_0, 0, 1; 86 | %pushi/vec4 1, 0, 1; 87 | %store/vec4 v0x55abce2398c0_0, 0, 1; 88 | %delay 5, 0; 89 | %pushi/vec4 0, 0, 1; 90 | %store/vec4 v0x55abce239730_0, 0, 1; 91 | %pushi/vec4 1, 0, 1; 92 | %store/vec4 v0x55abce2397f0_0, 0, 1; 93 | %pushi/vec4 0, 0, 1; 94 | %store/vec4 v0x55abce2398c0_0, 0, 1; 95 | %delay 5, 0; 96 | %pushi/vec4 0, 0, 1; 97 | %store/vec4 v0x55abce239730_0, 0, 1; 98 | %pushi/vec4 1, 0, 1; 99 | %store/vec4 v0x55abce2397f0_0, 0, 1; 100 | %pushi/vec4 1, 0, 1; 101 | %store/vec4 v0x55abce2398c0_0, 0, 1; 102 | %delay 5, 0; 103 | %pushi/vec4 1, 0, 1; 104 | %store/vec4 v0x55abce239730_0, 0, 1; 105 | %pushi/vec4 0, 0, 1; 106 | %store/vec4 v0x55abce2397f0_0, 0, 1; 107 | %pushi/vec4 0, 0, 1; 108 | %store/vec4 v0x55abce2398c0_0, 0, 1; 109 | %delay 5, 0; 110 | %pushi/vec4 1, 0, 1; 111 | %store/vec4 v0x55abce239730_0, 0, 1; 112 | %pushi/vec4 0, 0, 1; 113 | %store/vec4 v0x55abce2397f0_0, 0, 1; 114 | %pushi/vec4 1, 0, 1; 115 | %store/vec4 v0x55abce2398c0_0, 0, 1; 116 | %delay 5, 0; 117 | %pushi/vec4 1, 0, 1; 118 | %store/vec4 v0x55abce239730_0, 0, 1; 119 | %pushi/vec4 1, 0, 1; 120 | %store/vec4 v0x55abce2397f0_0, 0, 1; 121 | %pushi/vec4 0, 0, 1; 122 | %store/vec4 v0x55abce2398c0_0, 0, 1; 123 | %delay 5, 0; 124 | %pushi/vec4 1, 0, 1; 125 | %store/vec4 v0x55abce239730_0, 0, 1; 126 | %pushi/vec4 1, 0, 1; 127 | %store/vec4 v0x55abce2397f0_0, 0, 1; 128 | %pushi/vec4 1, 0, 1; 129 | %store/vec4 v0x55abce2398c0_0, 0, 1; 130 | %vpi_call 2 44 "$monitor", "A=%b, B=%b, C=%b, Y=%b", v0x55abce239730_0, v0x55abce2397f0_0, v0x55abce2398c0_0, v0x55abce2399c0_0 {0 0 0}; 131 | %delay 5, 0; 132 | %pushi/vec4 0, 0, 1; 133 | %store/vec4 v0x55abce239730_0, 0, 1; 134 | %pushi/vec4 0, 0, 1; 135 | %store/vec4 v0x55abce2397f0_0, 0, 1; 136 | %pushi/vec4 0, 0, 1; 137 | %store/vec4 v0x55abce2398c0_0, 0, 1; 138 | %vpi_call 2 50 "$display", "Carry Output" {0 0 0}; 139 | %delay 5, 0; 140 | %pushi/vec4 0, 0, 1; 141 | %store/vec4 v0x55abce239730_0, 0, 1; 142 | %pushi/vec4 0, 0, 1; 143 | %store/vec4 v0x55abce2397f0_0, 0, 1; 144 | %pushi/vec4 1, 0, 1; 145 | %store/vec4 v0x55abce2398c0_0, 0, 1; 146 | %delay 5, 0; 147 | %pushi/vec4 0, 0, 1; 148 | %store/vec4 v0x55abce239730_0, 0, 1; 149 | %pushi/vec4 1, 0, 1; 150 | %store/vec4 v0x55abce2397f0_0, 0, 1; 151 | %pushi/vec4 0, 0, 1; 152 | %store/vec4 v0x55abce2398c0_0, 0, 1; 153 | %delay 5, 0; 154 | %pushi/vec4 0, 0, 1; 155 | %store/vec4 v0x55abce239730_0, 0, 1; 156 | %pushi/vec4 1, 0, 1; 157 | %store/vec4 v0x55abce2397f0_0, 0, 1; 158 | %pushi/vec4 1, 0, 1; 159 | %store/vec4 v0x55abce2398c0_0, 0, 1; 160 | %delay 5, 0; 161 | %pushi/vec4 1, 0, 1; 162 | %store/vec4 v0x55abce239730_0, 0, 1; 163 | %pushi/vec4 0, 0, 1; 164 | %store/vec4 v0x55abce2397f0_0, 0, 1; 165 | %pushi/vec4 0, 0, 1; 166 | %store/vec4 v0x55abce2398c0_0, 0, 1; 167 | %delay 5, 0; 168 | %pushi/vec4 1, 0, 1; 169 | %store/vec4 v0x55abce239730_0, 0, 1; 170 | %pushi/vec4 0, 0, 1; 171 | %store/vec4 v0x55abce2397f0_0, 0, 1; 172 | %pushi/vec4 1, 0, 1; 173 | %store/vec4 v0x55abce2398c0_0, 0, 1; 174 | %delay 5, 0; 175 | %pushi/vec4 1, 0, 1; 176 | %store/vec4 v0x55abce239730_0, 0, 1; 177 | %pushi/vec4 1, 0, 1; 178 | %store/vec4 v0x55abce2397f0_0, 0, 1; 179 | %pushi/vec4 0, 0, 1; 180 | %store/vec4 v0x55abce2398c0_0, 0, 1; 181 | %delay 5, 0; 182 | %pushi/vec4 1, 0, 1; 183 | %store/vec4 v0x55abce239730_0, 0, 1; 184 | %pushi/vec4 1, 0, 1; 185 | %store/vec4 v0x55abce2397f0_0, 0, 1; 186 | %pushi/vec4 1, 0, 1; 187 | %store/vec4 v0x55abce2398c0_0, 0, 1; 188 | %end; 189 | .thread T_0; 190 | # The file index is used to find the file name in the following table. 191 | :file_names 4; 192 | "N/A"; 193 | ""; 194 | "full_adder_tb.v"; 195 | "full_adder.v"; 196 | -------------------------------------------------------------------------------- /week-2/full_adder/full_adder.v: -------------------------------------------------------------------------------- 1 | module full_adder(a,b,c,y,x); 2 | input a,b,c; 3 | output y,x; 4 | assign y = ((!a&!b&c)|(!a&b&c)|(a&!b&!c)|(a&b&c)); 5 | assign x = ((a&b)|(a&c)|(b&c)); 6 | endmodule 7 | -------------------------------------------------------------------------------- /week-2/full_adder/full_adder_tb.v: -------------------------------------------------------------------------------- 1 | module full_adder_tb; 2 | wire t_y, t_x; 3 | reg t_a, t_b, t_c; 4 | full_adder my_gate( .a(t_a), .b(t_b), .c(t_c), .y(t_y), .x(t_x)); 5 | initial 6 | begin 7 | $dumpfile("full_adder_tb.vcd"); 8 | $dumpvars(0, full_adder_tb); 9 | $monitor("A=%b, B=%b, C=%b, Y=%b", t_a, t_b, t_c, t_y); 10 | $display("Sum Output"); 11 | t_a = 1'b0; 12 | t_b = 1'b0; 13 | t_c = 1'b0; 14 | #5 15 | t_a = 1'b0; 16 | t_b = 1'b0; 17 | t_c = 1'b1; 18 | #5 19 | t_a = 1'b0; 20 | t_b = 1'b1; 21 | t_c = 1'b0; 22 | #5 23 | t_a = 1'b0; 24 | t_b = 1'b1; 25 | t_c = 1'b1; 26 | #5 27 | t_a = 1'b1; 28 | t_b = 1'b0; 29 | t_c = 1'b0; 30 | #5 31 | t_a = 1'b1; 32 | t_b = 1'b0; 33 | t_c = 1'b1; 34 | #5 35 | t_a = 1'b1; 36 | t_b = 1'b1; 37 | t_c = 1'b0; 38 | #5 39 | t_a = 1'b1; 40 | t_b = 1'b1; 41 | t_c = 1'b1; 42 | 43 | 44 | $monitor("A=%b, B=%b, C=%b, Y=%b",t_a, t_b, t_c, t_x); 45 | 46 | #5 47 | t_a = 1'b0; 48 | t_b = 1'b0; 49 | t_c = 1'b0; 50 | $display("Carry Output"); 51 | #5 52 | t_a = 1'b0; 53 | t_b = 1'b0; 54 | t_c = 1'b1; 55 | #5 56 | t_a = 1'b0; 57 | t_b = 1'b1; 58 | t_c = 1'b0; 59 | #5 60 | t_a = 1'b0; 61 | t_b = 1'b1; 62 | t_c = 1'b1; 63 | #5 64 | t_a = 1'b1; 65 | t_b = 1'b0; 66 | t_c = 1'b0; 67 | #5 68 | t_a = 1'b1; 69 | t_b = 1'b0; 70 | t_c = 1'b1; 71 | #5 72 | t_a = 1'b1; 73 | t_b = 1'b1; 74 | t_c = 1'b0; 75 | #5 76 | t_a = 1'b1; 77 | t_b = 1'b1; 78 | t_c = 1'b1; 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /week-2/full_adder/full_adder_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Aug 28 12:53:36 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module full_adder_tb $end 11 | $var wire 1 ! t_y $end 12 | $var wire 1 " t_x $end 13 | $var reg 1 # t_a $end 14 | $var reg 1 $ t_b $end 15 | $var reg 1 % t_c $end 16 | $scope module my_gate $end 17 | $var wire 1 # a $end 18 | $var wire 1 $ b $end 19 | $var wire 1 % c $end 20 | $var wire 1 " x $end 21 | $var wire 1 ! y $end 22 | $upscope $end 23 | $upscope $end 24 | $enddefinitions $end 25 | #0 26 | $dumpvars 27 | 0% 28 | 0$ 29 | 0# 30 | 0" 31 | 0! 32 | $end 33 | #5 34 | 1! 35 | 1% 36 | #10 37 | 0! 38 | 0% 39 | 1$ 40 | #15 41 | 1! 42 | 1" 43 | 1% 44 | #20 45 | 0" 46 | 0% 47 | 0$ 48 | 1# 49 | #25 50 | 1" 51 | 0! 52 | 1% 53 | #30 54 | 0% 55 | 1$ 56 | #35 57 | 1! 58 | 1% 59 | #40 60 | 0! 61 | 0" 62 | 0% 63 | 0$ 64 | 0# 65 | #45 66 | 1! 67 | 1% 68 | #50 69 | 0! 70 | 0% 71 | 1$ 72 | #55 73 | 1! 74 | 1" 75 | 1% 76 | #60 77 | 0" 78 | 0% 79 | 0$ 80 | 1# 81 | #65 82 | 1" 83 | 0! 84 | 1% 85 | #70 86 | 0% 87 | 1$ 88 | #75 89 | 1! 90 | 1% 91 | -------------------------------------------------------------------------------- /week-2/half_adder/half_adder: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; 6 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; 9 | :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; 10 | S_0x556581414960 .scope module, "half_adder_tb" "half_adder_tb" 2 1; 11 | .timescale 0 0; 12 | v0x55658143b350_0 .var "t_a", 0 0; 13 | v0x55658143b410_0 .var "t_b", 0 0; 14 | v0x55658143b4e0_0 .net "t_x", 0 0, L_0x55658143bba0; 1 drivers 15 | v0x55658143b5e0_0 .net "t_y", 0 0, L_0x55658143ba40; 1 drivers 16 | S_0x556581425320 .scope module, "my_gate" "half_adder" 2 4, 3 1 0, S_0x556581414960; 17 | .timescale 0 0; 18 | .port_info 0 /INPUT 1 "a"; 19 | .port_info 1 /INPUT 1 "b"; 20 | .port_info 2 /OUTPUT 1 "y"; 21 | .port_info 3 /OUTPUT 1 "x"; 22 | L_0x55658143b7d0 .functor AND 1, v0x55658143b350_0, L_0x55658143b6b0, C4<1>, C4<1>; 23 | L_0x55658143b980 .functor AND 1, L_0x55658143b8e0, v0x55658143b410_0, C4<1>, C4<1>; 24 | L_0x55658143ba40 .functor OR 1, L_0x55658143b7d0, L_0x55658143b980, C4<0>, C4<0>; 25 | L_0x55658143bba0 .functor AND 1, v0x55658143b350_0, v0x55658143b410_0, C4<1>, C4<1>; 26 | v0x556581425520_0 .net *"_ivl_1", 0 0, L_0x55658143b6b0; 1 drivers 27 | v0x55658143acf0_0 .net *"_ivl_2", 0 0, L_0x55658143b7d0; 1 drivers 28 | v0x55658143add0_0 .net *"_ivl_5", 0 0, L_0x55658143b8e0; 1 drivers 29 | v0x55658143aea0_0 .net *"_ivl_6", 0 0, L_0x55658143b980; 1 drivers 30 | v0x55658143af80_0 .net "a", 0 0, v0x55658143b350_0; 1 drivers 31 | v0x55658143b090_0 .net "b", 0 0, v0x55658143b410_0; 1 drivers 32 | v0x55658143b150_0 .net "x", 0 0, L_0x55658143bba0; alias, 1 drivers 33 | v0x55658143b210_0 .net "y", 0 0, L_0x55658143ba40; alias, 1 drivers 34 | L_0x55658143b6b0 .reduce/nor v0x55658143b410_0; 35 | L_0x55658143b8e0 .reduce/nor v0x55658143b350_0; 36 | .scope S_0x556581414960; 37 | T_0 ; 38 | %vpi_call 2 7 "$dumpfile", "half_adder_tb.vcd" {0 0 0}; 39 | %vpi_call 2 8 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x556581414960 {0 0 0}; 40 | %vpi_call 2 9 "$monitor", "A=%b, B=%b, Y=%b", v0x55658143b350_0, v0x55658143b410_0, v0x55658143b5e0_0 {0 0 0}; 41 | %vpi_call 2 10 "$display", "Sum Output" {0 0 0}; 42 | %pushi/vec4 0, 0, 1; 43 | %store/vec4 v0x55658143b350_0, 0, 1; 44 | %pushi/vec4 0, 0, 1; 45 | %store/vec4 v0x55658143b410_0, 0, 1; 46 | %delay 5, 0; 47 | %pushi/vec4 0, 0, 1; 48 | %store/vec4 v0x55658143b350_0, 0, 1; 49 | %pushi/vec4 1, 0, 1; 50 | %store/vec4 v0x55658143b410_0, 0, 1; 51 | %delay 5, 0; 52 | %pushi/vec4 1, 0, 1; 53 | %store/vec4 v0x55658143b350_0, 0, 1; 54 | %pushi/vec4 0, 0, 1; 55 | %store/vec4 v0x55658143b410_0, 0, 1; 56 | %delay 5, 0; 57 | %pushi/vec4 1, 0, 1; 58 | %store/vec4 v0x55658143b350_0, 0, 1; 59 | %pushi/vec4 1, 0, 1; 60 | %store/vec4 v0x55658143b410_0, 0, 1; 61 | %vpi_call 2 23 "$monitor", "A=%b, B=%b, Y=%b", v0x55658143b350_0, v0x55658143b410_0, v0x55658143b4e0_0 {0 0 0}; 62 | %delay 5, 0; 63 | %pushi/vec4 0, 0, 1; 64 | %store/vec4 v0x55658143b350_0, 0, 1; 65 | %pushi/vec4 0, 0, 1; 66 | %store/vec4 v0x55658143b410_0, 0, 1; 67 | %vpi_call 2 28 "$display", "Carry Output" {0 0 0}; 68 | %delay 5, 0; 69 | %pushi/vec4 0, 0, 1; 70 | %store/vec4 v0x55658143b350_0, 0, 1; 71 | %pushi/vec4 1, 0, 1; 72 | %store/vec4 v0x55658143b410_0, 0, 1; 73 | %delay 5, 0; 74 | %pushi/vec4 1, 0, 1; 75 | %store/vec4 v0x55658143b350_0, 0, 1; 76 | %pushi/vec4 0, 0, 1; 77 | %store/vec4 v0x55658143b410_0, 0, 1; 78 | %delay 5, 0; 79 | %pushi/vec4 1, 0, 1; 80 | %store/vec4 v0x55658143b350_0, 0, 1; 81 | %pushi/vec4 1, 0, 1; 82 | %store/vec4 v0x55658143b410_0, 0, 1; 83 | %end; 84 | .thread T_0; 85 | # The file index is used to find the file name in the following table. 86 | :file_names 4; 87 | "N/A"; 88 | ""; 89 | "half_adder_tb.v"; 90 | "half_adder.v"; 91 | -------------------------------------------------------------------------------- /week-2/half_adder/half_adder.v: -------------------------------------------------------------------------------- 1 | module half_adder(a,b,y,x); 2 | input a,b; 3 | output y,x; 4 | assign y = (a&!b)|(!a&b); 5 | assign x = a&b; 6 | endmodule 7 | -------------------------------------------------------------------------------- /week-2/half_adder/half_adder_tb.v: -------------------------------------------------------------------------------- 1 | module half_adder_tb; 2 | wire t_y, t_x; 3 | reg t_a, t_b; 4 | half_adder my_gate( .a(t_a), .b(t_b), .y(t_y), .x(t_x)); 5 | initial 6 | begin 7 | $dumpfile("half_adder_tb.vcd"); 8 | $dumpvars(0, half_adder_tb); 9 | $monitor("A=%b, B=%b, Y=%b", t_a, t_b, t_y); 10 | $display("Sum Output"); 11 | t_a = 1'b0; 12 | t_b = 1'b0; 13 | #5 14 | t_a = 1'b0; 15 | t_b = 1'b1; 16 | #5 17 | t_a = 1'b1; 18 | t_b = 1'b0; 19 | #5 20 | t_a = 1'b1; 21 | t_b = 1'b1; 22 | 23 | $monitor( "A=%b, B=%b, Y=%b", t_a, t_b, t_x); 24 | 25 | #5 26 | t_a = 1'b0; 27 | t_b = 1'b0; 28 | $display("Carry Output"); 29 | #5 30 | t_a = 1'b0; 31 | t_b = 1'b1; 32 | #5 33 | t_a = 1'b1; 34 | t_b = 1'b0; 35 | #5 36 | t_a = 1'b1; 37 | t_b = 1'b1; 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /week-2/half_adder/half_adder_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Tue Sep 13 17:04:47 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module half_adder_tb $end 11 | $var wire 1 ! t_y $end 12 | $var wire 1 " t_x $end 13 | $var reg 1 # t_a $end 14 | $var reg 1 $ t_b $end 15 | $scope module my_gate $end 16 | $var wire 1 # a $end 17 | $var wire 1 $ b $end 18 | $var wire 1 " x $end 19 | $var wire 1 ! y $end 20 | $upscope $end 21 | $upscope $end 22 | $enddefinitions $end 23 | #0 24 | $dumpvars 25 | 0$ 26 | 0# 27 | 0" 28 | 0! 29 | $end 30 | #5 31 | 1! 32 | 1$ 33 | #10 34 | 0$ 35 | 1# 36 | #15 37 | 0! 38 | 1" 39 | 1$ 40 | #20 41 | 0" 42 | 0$ 43 | 0# 44 | #25 45 | 1! 46 | 1$ 47 | #30 48 | 0$ 49 | 1# 50 | #35 51 | 0! 52 | 1" 53 | 1$ 54 | -------------------------------------------------------------------------------- /week-2/simple_circuit/circuit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/week-2/simple_circuit/circuit.png -------------------------------------------------------------------------------- /week-2/simple_circuit/simple.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Fri Aug 26 10:17:03 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module tb_simple_circuit $end 11 | $var wire 1 ! E $end 12 | $var wire 1 " D $end 13 | $var reg 1 # A $end 14 | $var reg 1 $ B $end 15 | $var reg 1 % C $end 16 | $scope module M1 $end 17 | $var wire 1 # A $end 18 | $var wire 1 $ B $end 19 | $var wire 1 % C $end 20 | $var wire 1 " D $end 21 | $var wire 1 ! E $end 22 | $var wire 1 & w1 $end 23 | $upscope $end 24 | $upscope $end 25 | $enddefinitions $end 26 | #0 27 | $dumpvars 28 | 0& 29 | 0% 30 | 0$ 31 | 0# 32 | 1" 33 | 1! 34 | $end 35 | #20 36 | 0" 37 | 0! 38 | 1% 39 | #40 40 | 1" 41 | 1! 42 | 0% 43 | 1$ 44 | #60 45 | 0" 46 | 0! 47 | 1% 48 | #80 49 | 1" 50 | 1! 51 | 0% 52 | 0$ 53 | 1# 54 | #100 55 | 0" 56 | 0! 57 | 1% 58 | #120 59 | 1" 60 | 1! 61 | 1& 62 | 0% 63 | 1$ 64 | #140 65 | 0! 66 | 1% 67 | -------------------------------------------------------------------------------- /week-2/simple_circuit/simple_circuit.v: -------------------------------------------------------------------------------- 1 | module simple_circuit(A,B,C,D,E); 2 | output D,E; 3 | input A,B,C; 4 | wire w1; 5 | and G1(w1, A, B); 6 | not G2(E,C); 7 | or G3(D, w1, E); 8 | endmodule 9 | -------------------------------------------------------------------------------- /week-2/simple_circuit/tb_simple_circuit.v: -------------------------------------------------------------------------------- 1 | module tb_simple_circuit; 2 | 3 | reg A,B,C; 4 | 5 | simple_circuit M1(A,B,C,D,E); 6 | 7 | initial 8 | 9 | begin 10 | 11 | A=1'b0 ; B=1'b0 ; C=1'b0; 12 | #20 13 | A=1'b0 ; B=1'b0 ; C=1'b1; 14 | #20 15 | A=1'b0 ; B=1'b1 ; C=1'b0; 16 | #20 17 | A=1'b0 ; B=1'b1 ; C=1'b1; 18 | #20 19 | A=1'b1 ; B=1'b0 ; C=1'b0; 20 | #20 21 | A=1'b1 ; B=1'b0 ; C=1'b1; 22 | #20 23 | A=1'b1 ; B=1'b1 ; C=1'b0; 24 | #20 25 | A=1'b1 ; B=1'b1 ; C=1'b1; 26 | 27 | end 28 | 29 | 30 | initial 31 | begin 32 | $monitor("A=%b, B=%b, C=%b, D=%b, E=%b", A,B,C,D,E); 33 | end 34 | initial 35 | begin 36 | $dumpfile ("simple.vcd"); 37 | $dumpvars (0, tb_simple_circuit); 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /week-3/ALU.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/week-3/ALU.jpg -------------------------------------------------------------------------------- /week-3/alu.v: -------------------------------------------------------------------------------- 1 | module alu (input wire [1:0] op, input wire [15:0] i0, i1, 2 | output wire [15:0] o, output wire cout); 3 | wire c[14:0]; 4 | alu_slice a0(op,i0[0],i1[0],op[0],o[0],c[0]); 5 | alu_slice a1(op,i0[1],i1[1],c[0],o[1],c[1]); 6 | alu_slice a2(op,i0[2],i1[2],c[1],o[2],c[2]); 7 | alu_slice a3(op,i0[3],i1[3],c[2],o[3],c[3]); 8 | alu_slice a4(op,i0[4],i1[4],c[3],o[4],c[4]); 9 | alu_slice a5(op,i0[5],i1[5],c[4],o[5],c[5]); 10 | alu_slice a6(op,i0[6],i1[6],c[5],o[6],c[6]); 11 | alu_slice a7(op,i0[7],i1[7],c[6],o[7],c[7]); 12 | alu_slice a8(op,i0[8],i1[8],c[7],o[8],c[8]); 13 | alu_slice a9(op,i0[9],i1[9],c[8],o[9],c[9]); 14 | alu_slice a10(op,i0[10],i1[10],c[9],o[10],c[10]); 15 | alu_slice a11(op,i0[11],i1[11],c[10],o[11],c[11]); 16 | alu_slice a12(op,i0[12],i1[12],c[11],o[12],c[12]); 17 | alu_slice a13(op,i0[13],i1[13],c[12],o[13],c[13]); 18 | alu_slice a14(op,i0[14],i1[14],c[13],o[14],c[14]); 19 | alu_slice a15(op,i0[15],i1[15],c[14],o[15],cout); 20 | endmodule 21 | module alu_slice(input wire [1:0] op,input wire i0,i1,cin,output wire o,carry); 22 | wire f1; 23 | fa16 b0(i0,i1,cin,f1,carry); 24 | wire t1,t2,t3; 25 | and2 b1(i0,i1,t1); 26 | or2 b2(i0,i1,t2); 27 | mux2 b3(t1,t2,op[0],t3); 28 | mux2 b4(t3,f1,op[1],o); 29 | endmodule 30 | module fa16(input wire i0,i1,cin,output wire o,carry); 31 | wire t4; 32 | xor2 c1(i1,cin,t4); 33 | fa c2(i0,t4,cin,o,carry); 34 | endmodule 35 | module fa(input wire a,b,c,output wire s,output wire coutput); 36 | wire t1; 37 | xor2 x1(a,b,t1); 38 | xor2 x2(t1,c,s); 39 | wire s1; 40 | and2 y1(a,b,s1); 41 | wire s2; 42 | and2 y2(b,c,s2); 43 | wire s3; 44 | and2 y3(a,c,s3); 45 | wire z1; 46 | or2 x3(s1,s2,z1); 47 | or2 x4(z1,s3,coutput); 48 | endmodule 49 | -------------------------------------------------------------------------------- /week-3/lib.v: -------------------------------------------------------------------------------- 1 | module invert (input wire i, output wire o); 2 | assign o = !i; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (t, o); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (t, o); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (t, o); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | module mux2 (input wire i0, i1, j, output wire o); 72 | assign o = (j==0)?i0:i1; 73 | endmodule 74 | 75 | module mux4 (input wire [0:3] i, input wire j1, j0, output wire o); 76 | wire t0, t1; 77 | mux2 mux2_0 (i[0], i[1], j1, t0); 78 | mux2 mux2_1 (i[2], i[3], j1, t1); 79 | mux2 mux2_2 (t0, t1, j0, o); 80 | endmodule 81 | 82 | module mux8 (input wire [0:7] i, input wire j2, j1, j0, output wire o); 83 | wire t0, t1; 84 | mux4 mux4_0 (i[0:3], j2, j1, t0); 85 | mux4 mux4_1 (i[4:7], j2, j1, t1); 86 | mux2 mux2_0 (t0, t1, j0, o); 87 | endmodule 88 | -------------------------------------------------------------------------------- /week-3/tb_alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 100 ps 2 | `define TESTVECS 16 3 | 4 | module tb; 5 | reg clk, reset; 6 | reg [1:0] op; 7 | reg [15:0] i0, i1; 8 | 9 | wire [15:0] o; 10 | wire cout; 11 | reg [33:0] test_vecs [0:(`TESTVECS-1)]; 12 | integer i; 13 | initial begin 14 | $dumpfile("tb_alu.vcd"); 15 | $dumpvars(0,tb); 16 | end 17 | initial begin 18 | reset = 1'b1; #12.5 reset = 1'b0; 19 | end 20 | initial clk = 1'b0; always #5 clk =~ clk; 21 | initial begin 22 | test_vecs[0][33:32] = 2'b00; test_vecs[0][31:16] = 16'h0000; test_vecs[0][15:0] = 16'h0000; 23 | test_vecs[1][33:32] = 2'b00; test_vecs[1][31:16] = 16'haa55;test_vecs[1][15:0] = 16'h55aa; 24 | test_vecs[2][33:32] = 2'b00; test_vecs[2][31:16] = 16'hffff;test_vecs[2][15:0] = 16'h0001; 25 | test_vecs[3][33:32] = 2'b00; test_vecs[3][31:16] = 16'h0001;test_vecs[3][15:0] = 16'h7fff; 26 | test_vecs[4][33:32] = 2'b01; test_vecs[4][31:16] = 16'h0000;test_vecs[4][15:0] = 16'h0000; 27 | test_vecs[5][33:32] = 2'b01; test_vecs[5][31:16] = 16'haa55;test_vecs[5][15:0] = 16'h55aa; 28 | test_vecs[6][33:32] = 2'b01; test_vecs[6][31:16] = 16'hffff;test_vecs[6][15:0] = 16'h0001; 29 | test_vecs[7][33:32] = 2'b01; test_vecs[7][31:16] = 16'h0001;test_vecs[7][15:0] = 16'h7fff; 30 | test_vecs[8][33:32] = 2'b10; test_vecs[8][31:16] = 16'h0000;test_vecs[8][15:0] = 16'h0000; 31 | test_vecs[9][33:32] = 2'b10; test_vecs[9][31:16] = 16'haa55;test_vecs[9][15:0] = 16'h55aa; 32 | test_vecs[10][33:32] = 2'b10; test_vecs[10][31:16] = 16'hffff;test_vecs[10][15:0] = 16'h0001; 33 | test_vecs[11][33:32] = 2'b10; test_vecs[11][31:16] = 16'h0001;test_vecs[11][15:0] = 16'h7fff; 34 | test_vecs[12][33:32] = 2'b11; test_vecs[12][31:16] = 16'h0000;test_vecs[12][15:0] = 16'h0000; 35 | test_vecs[13][33:32] = 2'b11; test_vecs[13][31:16] = 16'haa55;test_vecs[13][15:0] = 16'h55aa; 36 | test_vecs[14][33:32] = 2'b11; test_vecs[14][31:16] = 16'hffff;test_vecs[14][15:0] = 16'h0001; 37 | test_vecs[15][33:32] = 2'b11; test_vecs[15][31:16] = 16'h0001;test_vecs[15][15:0] = 16'h7fff; 38 | end 39 | initial {op, i0, i1} = 0; 40 | alu alu_0 (op, i0, i1, o, cout); 41 | initial begin 42 | #6 for(i=0;i<`TESTVECS;i=i+1) 43 | begin #10 {op, i0, i1}=test_vecs[i]; end 44 | 45 | #100 $finish; 46 | 47 | end 48 | 49 | always@(i0 or i1 ) 50 | $monitor("At time = %t, Operator= %b,i0=%h, i1=%h,Sum = %h,Carry %h", $time,op,i0,i1,o,cout); 51 | 52 | 53 | endmodule 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /week-3/tb_alu.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sat Sep 24 18:37:31 2022 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 100ps 9 | $end 10 | $scope module tb $end 11 | $var wire 16 ! o [15:0] $end 12 | $var wire 1 " cout $end 13 | $var reg 1 # clk $end 14 | $var reg 16 $ i0 [15:0] $end 15 | $var reg 16 % i1 [15:0] $end 16 | $var reg 2 & op [1:0] $end 17 | $var reg 1 ' reset $end 18 | $var integer 32 ( i [31:0] $end 19 | $scope module alu_0 $end 20 | $var wire 16 ) i0 [15:0] $end 21 | $var wire 16 * i1 [15:0] $end 22 | $var wire 2 + op [1:0] $end 23 | $var wire 16 , o [15:0] $end 24 | $var wire 1 " cout $end 25 | $scope module a0 $end 26 | $var wire 1 - cin $end 27 | $var wire 1 . i0 $end 28 | $var wire 1 / i1 $end 29 | $var wire 2 0 op [1:0] $end 30 | $var wire 1 1 t3 $end 31 | $var wire 1 2 t2 $end 32 | $var wire 1 3 t1 $end 33 | $var wire 1 4 o $end 34 | $var wire 1 5 f1 $end 35 | $var wire 1 6 carry $end 36 | $scope module b0 $end 37 | $var wire 1 - cin $end 38 | $var wire 1 . i0 $end 39 | $var wire 1 / i1 $end 40 | $var wire 1 7 t4 $end 41 | $var wire 1 5 o $end 42 | $var wire 1 6 carry $end 43 | $scope module c1 $end 44 | $var wire 1 / i0 $end 45 | $var wire 1 - i1 $end 46 | $var wire 1 7 o $end 47 | $upscope $end 48 | $scope module c2 $end 49 | $var wire 1 . a $end 50 | $var wire 1 7 b $end 51 | $var wire 1 - c $end 52 | $var wire 1 8 z1 $end 53 | $var wire 1 9 t1 $end 54 | $var wire 1 : s3 $end 55 | $var wire 1 ; s2 $end 56 | $var wire 1 < s1 $end 57 | $var wire 1 5 s $end 58 | $var wire 1 6 coutput $end 59 | $scope module x1 $end 60 | $var wire 1 . i0 $end 61 | $var wire 1 7 i1 $end 62 | $var wire 1 9 o $end 63 | $upscope $end 64 | $scope module x2 $end 65 | $var wire 1 9 i0 $end 66 | $var wire 1 - i1 $end 67 | $var wire 1 5 o $end 68 | $upscope $end 69 | $scope module x3 $end 70 | $var wire 1 8 o $end 71 | $var wire 1 ; i1 $end 72 | $var wire 1 < i0 $end 73 | $upscope $end 74 | $scope module x4 $end 75 | $var wire 1 8 i0 $end 76 | $var wire 1 6 o $end 77 | $var wire 1 : i1 $end 78 | $upscope $end 79 | $scope module y1 $end 80 | $var wire 1 . i0 $end 81 | $var wire 1 7 i1 $end 82 | $var wire 1 < o $end 83 | $upscope $end 84 | $scope module y2 $end 85 | $var wire 1 7 i0 $end 86 | $var wire 1 - i1 $end 87 | $var wire 1 ; o $end 88 | $upscope $end 89 | $scope module y3 $end 90 | $var wire 1 . i0 $end 91 | $var wire 1 - i1 $end 92 | $var wire 1 : o $end 93 | $upscope $end 94 | $upscope $end 95 | $upscope $end 96 | $scope module b1 $end 97 | $var wire 1 . i0 $end 98 | $var wire 1 / i1 $end 99 | $var wire 1 3 o $end 100 | $upscope $end 101 | $scope module b2 $end 102 | $var wire 1 . i0 $end 103 | $var wire 1 / i1 $end 104 | $var wire 1 2 o $end 105 | $upscope $end 106 | $scope module b3 $end 107 | $var wire 1 3 i0 $end 108 | $var wire 1 2 i1 $end 109 | $var wire 1 = j $end 110 | $var wire 1 1 o $end 111 | $upscope $end 112 | $scope module b4 $end 113 | $var wire 1 1 i0 $end 114 | $var wire 1 5 i1 $end 115 | $var wire 1 > j $end 116 | $var wire 1 4 o $end 117 | $upscope $end 118 | $upscope $end 119 | $scope module a1 $end 120 | $var wire 1 6 cin $end 121 | $var wire 1 ? i0 $end 122 | $var wire 1 @ i1 $end 123 | $var wire 2 A op [1:0] $end 124 | $var wire 1 B t3 $end 125 | $var wire 1 C t2 $end 126 | $var wire 1 D t1 $end 127 | $var wire 1 E o $end 128 | $var wire 1 F f1 $end 129 | $var wire 1 G carry $end 130 | $scope module b0 $end 131 | $var wire 1 6 cin $end 132 | $var wire 1 ? i0 $end 133 | $var wire 1 @ i1 $end 134 | $var wire 1 H t4 $end 135 | $var wire 1 F o $end 136 | $var wire 1 G carry $end 137 | $scope module c1 $end 138 | $var wire 1 @ i0 $end 139 | $var wire 1 6 i1 $end 140 | $var wire 1 H o $end 141 | $upscope $end 142 | $scope module c2 $end 143 | $var wire 1 ? a $end 144 | $var wire 1 H b $end 145 | $var wire 1 6 c $end 146 | $var wire 1 I z1 $end 147 | $var wire 1 J t1 $end 148 | $var wire 1 K s3 $end 149 | $var wire 1 L s2 $end 150 | $var wire 1 M s1 $end 151 | $var wire 1 F s $end 152 | $var wire 1 G coutput $end 153 | $scope module x1 $end 154 | $var wire 1 ? i0 $end 155 | $var wire 1 H i1 $end 156 | $var wire 1 J o $end 157 | $upscope $end 158 | $scope module x2 $end 159 | $var wire 1 J i0 $end 160 | $var wire 1 6 i1 $end 161 | $var wire 1 F o $end 162 | $upscope $end 163 | $scope module x3 $end 164 | $var wire 1 I o $end 165 | $var wire 1 L i1 $end 166 | $var wire 1 M i0 $end 167 | $upscope $end 168 | $scope module x4 $end 169 | $var wire 1 I i0 $end 170 | $var wire 1 G o $end 171 | $var wire 1 K i1 $end 172 | $upscope $end 173 | $scope module y1 $end 174 | $var wire 1 ? i0 $end 175 | $var wire 1 H i1 $end 176 | $var wire 1 M o $end 177 | $upscope $end 178 | $scope module y2 $end 179 | $var wire 1 H i0 $end 180 | $var wire 1 6 i1 $end 181 | $var wire 1 L o $end 182 | $upscope $end 183 | $scope module y3 $end 184 | $var wire 1 ? i0 $end 185 | $var wire 1 6 i1 $end 186 | $var wire 1 K o $end 187 | $upscope $end 188 | $upscope $end 189 | $upscope $end 190 | $scope module b1 $end 191 | $var wire 1 ? i0 $end 192 | $var wire 1 @ i1 $end 193 | $var wire 1 D o $end 194 | $upscope $end 195 | $scope module b2 $end 196 | $var wire 1 ? i0 $end 197 | $var wire 1 @ i1 $end 198 | $var wire 1 C o $end 199 | $upscope $end 200 | $scope module b3 $end 201 | $var wire 1 D i0 $end 202 | $var wire 1 C i1 $end 203 | $var wire 1 N j $end 204 | $var wire 1 B o $end 205 | $upscope $end 206 | $scope module b4 $end 207 | $var wire 1 B i0 $end 208 | $var wire 1 F i1 $end 209 | $var wire 1 O j $end 210 | $var wire 1 E o $end 211 | $upscope $end 212 | $upscope $end 213 | $scope module a10 $end 214 | $var wire 1 P i0 $end 215 | $var wire 1 Q i1 $end 216 | $var wire 2 R op [1:0] $end 217 | $var wire 1 S t3 $end 218 | $var wire 1 T t2 $end 219 | $var wire 1 U t1 $end 220 | $var wire 1 V o $end 221 | $var wire 1 W f1 $end 222 | $var wire 1 X cin $end 223 | $var wire 1 Y carry $end 224 | $scope module b0 $end 225 | $var wire 1 P i0 $end 226 | $var wire 1 Q i1 $end 227 | $var wire 1 Z t4 $end 228 | $var wire 1 W o $end 229 | $var wire 1 X cin $end 230 | $var wire 1 Y carry $end 231 | $scope module c1 $end 232 | $var wire 1 Q i0 $end 233 | $var wire 1 Z o $end 234 | $var wire 1 X i1 $end 235 | $upscope $end 236 | $scope module c2 $end 237 | $var wire 1 P a $end 238 | $var wire 1 Z b $end 239 | $var wire 1 [ z1 $end 240 | $var wire 1 \ t1 $end 241 | $var wire 1 ] s3 $end 242 | $var wire 1 ^ s2 $end 243 | $var wire 1 _ s1 $end 244 | $var wire 1 W s $end 245 | $var wire 1 Y coutput $end 246 | $var wire 1 X c $end 247 | $scope module x1 $end 248 | $var wire 1 P i0 $end 249 | $var wire 1 Z i1 $end 250 | $var wire 1 \ o $end 251 | $upscope $end 252 | $scope module x2 $end 253 | $var wire 1 \ i0 $end 254 | $var wire 1 W o $end 255 | $var wire 1 X i1 $end 256 | $upscope $end 257 | $scope module x3 $end 258 | $var wire 1 [ o $end 259 | $var wire 1 ^ i1 $end 260 | $var wire 1 _ i0 $end 261 | $upscope $end 262 | $scope module x4 $end 263 | $var wire 1 [ i0 $end 264 | $var wire 1 Y o $end 265 | $var wire 1 ] i1 $end 266 | $upscope $end 267 | $scope module y1 $end 268 | $var wire 1 P i0 $end 269 | $var wire 1 Z i1 $end 270 | $var wire 1 _ o $end 271 | $upscope $end 272 | $scope module y2 $end 273 | $var wire 1 Z i0 $end 274 | $var wire 1 ^ o $end 275 | $var wire 1 X i1 $end 276 | $upscope $end 277 | $scope module y3 $end 278 | $var wire 1 P i0 $end 279 | $var wire 1 ] o $end 280 | $var wire 1 X i1 $end 281 | $upscope $end 282 | $upscope $end 283 | $upscope $end 284 | $scope module b1 $end 285 | $var wire 1 P i0 $end 286 | $var wire 1 Q i1 $end 287 | $var wire 1 U o $end 288 | $upscope $end 289 | $scope module b2 $end 290 | $var wire 1 P i0 $end 291 | $var wire 1 Q i1 $end 292 | $var wire 1 T o $end 293 | $upscope $end 294 | $scope module b3 $end 295 | $var wire 1 U i0 $end 296 | $var wire 1 T i1 $end 297 | $var wire 1 ` j $end 298 | $var wire 1 S o $end 299 | $upscope $end 300 | $scope module b4 $end 301 | $var wire 1 S i0 $end 302 | $var wire 1 W i1 $end 303 | $var wire 1 a j $end 304 | $var wire 1 V o $end 305 | $upscope $end 306 | $upscope $end 307 | $scope module a11 $end 308 | $var wire 1 Y cin $end 309 | $var wire 1 b i0 $end 310 | $var wire 1 c i1 $end 311 | $var wire 2 d op [1:0] $end 312 | $var wire 1 e t3 $end 313 | $var wire 1 f t2 $end 314 | $var wire 1 g t1 $end 315 | $var wire 1 h o $end 316 | $var wire 1 i f1 $end 317 | $var wire 1 j carry $end 318 | $scope module b0 $end 319 | $var wire 1 Y cin $end 320 | $var wire 1 b i0 $end 321 | $var wire 1 c i1 $end 322 | $var wire 1 k t4 $end 323 | $var wire 1 i o $end 324 | $var wire 1 j carry $end 325 | $scope module c1 $end 326 | $var wire 1 c i0 $end 327 | $var wire 1 Y i1 $end 328 | $var wire 1 k o $end 329 | $upscope $end 330 | $scope module c2 $end 331 | $var wire 1 b a $end 332 | $var wire 1 k b $end 333 | $var wire 1 Y c $end 334 | $var wire 1 l z1 $end 335 | $var wire 1 m t1 $end 336 | $var wire 1 n s3 $end 337 | $var wire 1 o s2 $end 338 | $var wire 1 p s1 $end 339 | $var wire 1 i s $end 340 | $var wire 1 j coutput $end 341 | $scope module x1 $end 342 | $var wire 1 b i0 $end 343 | $var wire 1 k i1 $end 344 | $var wire 1 m o $end 345 | $upscope $end 346 | $scope module x2 $end 347 | $var wire 1 m i0 $end 348 | $var wire 1 Y i1 $end 349 | $var wire 1 i o $end 350 | $upscope $end 351 | $scope module x3 $end 352 | $var wire 1 l o $end 353 | $var wire 1 o i1 $end 354 | $var wire 1 p i0 $end 355 | $upscope $end 356 | $scope module x4 $end 357 | $var wire 1 l i0 $end 358 | $var wire 1 j o $end 359 | $var wire 1 n i1 $end 360 | $upscope $end 361 | $scope module y1 $end 362 | $var wire 1 b i0 $end 363 | $var wire 1 k i1 $end 364 | $var wire 1 p o $end 365 | $upscope $end 366 | $scope module y2 $end 367 | $var wire 1 k i0 $end 368 | $var wire 1 Y i1 $end 369 | $var wire 1 o o $end 370 | $upscope $end 371 | $scope module y3 $end 372 | $var wire 1 b i0 $end 373 | $var wire 1 Y i1 $end 374 | $var wire 1 n o $end 375 | $upscope $end 376 | $upscope $end 377 | $upscope $end 378 | $scope module b1 $end 379 | $var wire 1 b i0 $end 380 | $var wire 1 c i1 $end 381 | $var wire 1 g o $end 382 | $upscope $end 383 | $scope module b2 $end 384 | $var wire 1 b i0 $end 385 | $var wire 1 c i1 $end 386 | $var wire 1 f o $end 387 | $upscope $end 388 | $scope module b3 $end 389 | $var wire 1 g i0 $end 390 | $var wire 1 f i1 $end 391 | $var wire 1 q j $end 392 | $var wire 1 e o $end 393 | $upscope $end 394 | $scope module b4 $end 395 | $var wire 1 e i0 $end 396 | $var wire 1 i i1 $end 397 | $var wire 1 r j $end 398 | $var wire 1 h o $end 399 | $upscope $end 400 | $upscope $end 401 | $scope module a12 $end 402 | $var wire 1 j cin $end 403 | $var wire 1 s i0 $end 404 | $var wire 1 t i1 $end 405 | $var wire 2 u op [1:0] $end 406 | $var wire 1 v t3 $end 407 | $var wire 1 w t2 $end 408 | $var wire 1 x t1 $end 409 | $var wire 1 y o $end 410 | $var wire 1 z f1 $end 411 | $var wire 1 { carry $end 412 | $scope module b0 $end 413 | $var wire 1 j cin $end 414 | $var wire 1 s i0 $end 415 | $var wire 1 t i1 $end 416 | $var wire 1 | t4 $end 417 | $var wire 1 z o $end 418 | $var wire 1 { carry $end 419 | $scope module c1 $end 420 | $var wire 1 t i0 $end 421 | $var wire 1 j i1 $end 422 | $var wire 1 | o $end 423 | $upscope $end 424 | $scope module c2 $end 425 | $var wire 1 s a $end 426 | $var wire 1 | b $end 427 | $var wire 1 j c $end 428 | $var wire 1 } z1 $end 429 | $var wire 1 ~ t1 $end 430 | $var wire 1 !" s3 $end 431 | $var wire 1 "" s2 $end 432 | $var wire 1 #" s1 $end 433 | $var wire 1 z s $end 434 | $var wire 1 { coutput $end 435 | $scope module x1 $end 436 | $var wire 1 s i0 $end 437 | $var wire 1 | i1 $end 438 | $var wire 1 ~ o $end 439 | $upscope $end 440 | $scope module x2 $end 441 | $var wire 1 ~ i0 $end 442 | $var wire 1 j i1 $end 443 | $var wire 1 z o $end 444 | $upscope $end 445 | $scope module x3 $end 446 | $var wire 1 } o $end 447 | $var wire 1 "" i1 $end 448 | $var wire 1 #" i0 $end 449 | $upscope $end 450 | $scope module x4 $end 451 | $var wire 1 } i0 $end 452 | $var wire 1 { o $end 453 | $var wire 1 !" i1 $end 454 | $upscope $end 455 | $scope module y1 $end 456 | $var wire 1 s i0 $end 457 | $var wire 1 | i1 $end 458 | $var wire 1 #" o $end 459 | $upscope $end 460 | $scope module y2 $end 461 | $var wire 1 | i0 $end 462 | $var wire 1 j i1 $end 463 | $var wire 1 "" o $end 464 | $upscope $end 465 | $scope module y3 $end 466 | $var wire 1 s i0 $end 467 | $var wire 1 j i1 $end 468 | $var wire 1 !" o $end 469 | $upscope $end 470 | $upscope $end 471 | $upscope $end 472 | $scope module b1 $end 473 | $var wire 1 s i0 $end 474 | $var wire 1 t i1 $end 475 | $var wire 1 x o $end 476 | $upscope $end 477 | $scope module b2 $end 478 | $var wire 1 s i0 $end 479 | $var wire 1 t i1 $end 480 | $var wire 1 w o $end 481 | $upscope $end 482 | $scope module b3 $end 483 | $var wire 1 x i0 $end 484 | $var wire 1 w i1 $end 485 | $var wire 1 $" j $end 486 | $var wire 1 v o $end 487 | $upscope $end 488 | $scope module b4 $end 489 | $var wire 1 v i0 $end 490 | $var wire 1 z i1 $end 491 | $var wire 1 %" j $end 492 | $var wire 1 y o $end 493 | $upscope $end 494 | $upscope $end 495 | $scope module a13 $end 496 | $var wire 1 { cin $end 497 | $var wire 1 &" i0 $end 498 | $var wire 1 '" i1 $end 499 | $var wire 2 (" op [1:0] $end 500 | $var wire 1 )" t3 $end 501 | $var wire 1 *" t2 $end 502 | $var wire 1 +" t1 $end 503 | $var wire 1 ," o $end 504 | $var wire 1 -" f1 $end 505 | $var wire 1 ." carry $end 506 | $scope module b0 $end 507 | $var wire 1 { cin $end 508 | $var wire 1 &" i0 $end 509 | $var wire 1 '" i1 $end 510 | $var wire 1 /" t4 $end 511 | $var wire 1 -" o $end 512 | $var wire 1 ." carry $end 513 | $scope module c1 $end 514 | $var wire 1 '" i0 $end 515 | $var wire 1 { i1 $end 516 | $var wire 1 /" o $end 517 | $upscope $end 518 | $scope module c2 $end 519 | $var wire 1 &" a $end 520 | $var wire 1 /" b $end 521 | $var wire 1 { c $end 522 | $var wire 1 0" z1 $end 523 | $var wire 1 1" t1 $end 524 | $var wire 1 2" s3 $end 525 | $var wire 1 3" s2 $end 526 | $var wire 1 4" s1 $end 527 | $var wire 1 -" s $end 528 | $var wire 1 ." coutput $end 529 | $scope module x1 $end 530 | $var wire 1 &" i0 $end 531 | $var wire 1 /" i1 $end 532 | $var wire 1 1" o $end 533 | $upscope $end 534 | $scope module x2 $end 535 | $var wire 1 1" i0 $end 536 | $var wire 1 { i1 $end 537 | $var wire 1 -" o $end 538 | $upscope $end 539 | $scope module x3 $end 540 | $var wire 1 0" o $end 541 | $var wire 1 3" i1 $end 542 | $var wire 1 4" i0 $end 543 | $upscope $end 544 | $scope module x4 $end 545 | $var wire 1 0" i0 $end 546 | $var wire 1 ." o $end 547 | $var wire 1 2" i1 $end 548 | $upscope $end 549 | $scope module y1 $end 550 | $var wire 1 &" i0 $end 551 | $var wire 1 /" i1 $end 552 | $var wire 1 4" o $end 553 | $upscope $end 554 | $scope module y2 $end 555 | $var wire 1 /" i0 $end 556 | $var wire 1 { i1 $end 557 | $var wire 1 3" o $end 558 | $upscope $end 559 | $scope module y3 $end 560 | $var wire 1 &" i0 $end 561 | $var wire 1 { i1 $end 562 | $var wire 1 2" o $end 563 | $upscope $end 564 | $upscope $end 565 | $upscope $end 566 | $scope module b1 $end 567 | $var wire 1 &" i0 $end 568 | $var wire 1 '" i1 $end 569 | $var wire 1 +" o $end 570 | $upscope $end 571 | $scope module b2 $end 572 | $var wire 1 &" i0 $end 573 | $var wire 1 '" i1 $end 574 | $var wire 1 *" o $end 575 | $upscope $end 576 | $scope module b3 $end 577 | $var wire 1 +" i0 $end 578 | $var wire 1 *" i1 $end 579 | $var wire 1 5" j $end 580 | $var wire 1 )" o $end 581 | $upscope $end 582 | $scope module b4 $end 583 | $var wire 1 )" i0 $end 584 | $var wire 1 -" i1 $end 585 | $var wire 1 6" j $end 586 | $var wire 1 ," o $end 587 | $upscope $end 588 | $upscope $end 589 | $scope module a14 $end 590 | $var wire 1 ." cin $end 591 | $var wire 1 7" i0 $end 592 | $var wire 1 8" i1 $end 593 | $var wire 2 9" op [1:0] $end 594 | $var wire 1 :" t3 $end 595 | $var wire 1 ;" t2 $end 596 | $var wire 1 <" t1 $end 597 | $var wire 1 =" o $end 598 | $var wire 1 >" f1 $end 599 | $var wire 1 ?" carry $end 600 | $scope module b0 $end 601 | $var wire 1 ." cin $end 602 | $var wire 1 7" i0 $end 603 | $var wire 1 8" i1 $end 604 | $var wire 1 @" t4 $end 605 | $var wire 1 >" o $end 606 | $var wire 1 ?" carry $end 607 | $scope module c1 $end 608 | $var wire 1 8" i0 $end 609 | $var wire 1 ." i1 $end 610 | $var wire 1 @" o $end 611 | $upscope $end 612 | $scope module c2 $end 613 | $var wire 1 7" a $end 614 | $var wire 1 @" b $end 615 | $var wire 1 ." c $end 616 | $var wire 1 A" z1 $end 617 | $var wire 1 B" t1 $end 618 | $var wire 1 C" s3 $end 619 | $var wire 1 D" s2 $end 620 | $var wire 1 E" s1 $end 621 | $var wire 1 >" s $end 622 | $var wire 1 ?" coutput $end 623 | $scope module x1 $end 624 | $var wire 1 7" i0 $end 625 | $var wire 1 @" i1 $end 626 | $var wire 1 B" o $end 627 | $upscope $end 628 | $scope module x2 $end 629 | $var wire 1 B" i0 $end 630 | $var wire 1 ." i1 $end 631 | $var wire 1 >" o $end 632 | $upscope $end 633 | $scope module x3 $end 634 | $var wire 1 A" o $end 635 | $var wire 1 D" i1 $end 636 | $var wire 1 E" i0 $end 637 | $upscope $end 638 | $scope module x4 $end 639 | $var wire 1 A" i0 $end 640 | $var wire 1 ?" o $end 641 | $var wire 1 C" i1 $end 642 | $upscope $end 643 | $scope module y1 $end 644 | $var wire 1 7" i0 $end 645 | $var wire 1 @" i1 $end 646 | $var wire 1 E" o $end 647 | $upscope $end 648 | $scope module y2 $end 649 | $var wire 1 @" i0 $end 650 | $var wire 1 ." i1 $end 651 | $var wire 1 D" o $end 652 | $upscope $end 653 | $scope module y3 $end 654 | $var wire 1 7" i0 $end 655 | $var wire 1 ." i1 $end 656 | $var wire 1 C" o $end 657 | $upscope $end 658 | $upscope $end 659 | $upscope $end 660 | $scope module b1 $end 661 | $var wire 1 7" i0 $end 662 | $var wire 1 8" i1 $end 663 | $var wire 1 <" o $end 664 | $upscope $end 665 | $scope module b2 $end 666 | $var wire 1 7" i0 $end 667 | $var wire 1 8" i1 $end 668 | $var wire 1 ;" o $end 669 | $upscope $end 670 | $scope module b3 $end 671 | $var wire 1 <" i0 $end 672 | $var wire 1 ;" i1 $end 673 | $var wire 1 F" j $end 674 | $var wire 1 :" o $end 675 | $upscope $end 676 | $scope module b4 $end 677 | $var wire 1 :" i0 $end 678 | $var wire 1 >" i1 $end 679 | $var wire 1 G" j $end 680 | $var wire 1 =" o $end 681 | $upscope $end 682 | $upscope $end 683 | $scope module a15 $end 684 | $var wire 1 ?" cin $end 685 | $var wire 1 H" i0 $end 686 | $var wire 1 I" i1 $end 687 | $var wire 2 J" op [1:0] $end 688 | $var wire 1 K" t3 $end 689 | $var wire 1 L" t2 $end 690 | $var wire 1 M" t1 $end 691 | $var wire 1 N" o $end 692 | $var wire 1 O" f1 $end 693 | $var wire 1 " carry $end 694 | $scope module b0 $end 695 | $var wire 1 ?" cin $end 696 | $var wire 1 H" i0 $end 697 | $var wire 1 I" i1 $end 698 | $var wire 1 P" t4 $end 699 | $var wire 1 O" o $end 700 | $var wire 1 " carry $end 701 | $scope module c1 $end 702 | $var wire 1 I" i0 $end 703 | $var wire 1 ?" i1 $end 704 | $var wire 1 P" o $end 705 | $upscope $end 706 | $scope module c2 $end 707 | $var wire 1 H" a $end 708 | $var wire 1 P" b $end 709 | $var wire 1 ?" c $end 710 | $var wire 1 Q" z1 $end 711 | $var wire 1 R" t1 $end 712 | $var wire 1 S" s3 $end 713 | $var wire 1 T" s2 $end 714 | $var wire 1 U" s1 $end 715 | $var wire 1 O" s $end 716 | $var wire 1 " coutput $end 717 | $scope module x1 $end 718 | $var wire 1 H" i0 $end 719 | $var wire 1 P" i1 $end 720 | $var wire 1 R" o $end 721 | $upscope $end 722 | $scope module x2 $end 723 | $var wire 1 R" i0 $end 724 | $var wire 1 ?" i1 $end 725 | $var wire 1 O" o $end 726 | $upscope $end 727 | $scope module x3 $end 728 | $var wire 1 Q" o $end 729 | $var wire 1 T" i1 $end 730 | $var wire 1 U" i0 $end 731 | $upscope $end 732 | $scope module x4 $end 733 | $var wire 1 Q" i0 $end 734 | $var wire 1 " o $end 735 | $var wire 1 S" i1 $end 736 | $upscope $end 737 | $scope module y1 $end 738 | $var wire 1 H" i0 $end 739 | $var wire 1 P" i1 $end 740 | $var wire 1 U" o $end 741 | $upscope $end 742 | $scope module y2 $end 743 | $var wire 1 P" i0 $end 744 | $var wire 1 ?" i1 $end 745 | $var wire 1 T" o $end 746 | $upscope $end 747 | $scope module y3 $end 748 | $var wire 1 H" i0 $end 749 | $var wire 1 ?" i1 $end 750 | $var wire 1 S" o $end 751 | $upscope $end 752 | $upscope $end 753 | $upscope $end 754 | $scope module b1 $end 755 | $var wire 1 H" i0 $end 756 | $var wire 1 I" i1 $end 757 | $var wire 1 M" o $end 758 | $upscope $end 759 | $scope module b2 $end 760 | $var wire 1 H" i0 $end 761 | $var wire 1 I" i1 $end 762 | $var wire 1 L" o $end 763 | $upscope $end 764 | $scope module b3 $end 765 | $var wire 1 M" i0 $end 766 | $var wire 1 L" i1 $end 767 | $var wire 1 V" j $end 768 | $var wire 1 K" o $end 769 | $upscope $end 770 | $scope module b4 $end 771 | $var wire 1 K" i0 $end 772 | $var wire 1 O" i1 $end 773 | $var wire 1 W" j $end 774 | $var wire 1 N" o $end 775 | $upscope $end 776 | $upscope $end 777 | $scope module a2 $end 778 | $var wire 1 G cin $end 779 | $var wire 1 X" i0 $end 780 | $var wire 1 Y" i1 $end 781 | $var wire 2 Z" op [1:0] $end 782 | $var wire 1 [" t3 $end 783 | $var wire 1 \" t2 $end 784 | $var wire 1 ]" t1 $end 785 | $var wire 1 ^" o $end 786 | $var wire 1 _" f1 $end 787 | $var wire 1 `" carry $end 788 | $scope module b0 $end 789 | $var wire 1 G cin $end 790 | $var wire 1 X" i0 $end 791 | $var wire 1 Y" i1 $end 792 | $var wire 1 a" t4 $end 793 | $var wire 1 _" o $end 794 | $var wire 1 `" carry $end 795 | $scope module c1 $end 796 | $var wire 1 Y" i0 $end 797 | $var wire 1 G i1 $end 798 | $var wire 1 a" o $end 799 | $upscope $end 800 | $scope module c2 $end 801 | $var wire 1 X" a $end 802 | $var wire 1 a" b $end 803 | $var wire 1 G c $end 804 | $var wire 1 b" z1 $end 805 | $var wire 1 c" t1 $end 806 | $var wire 1 d" s3 $end 807 | $var wire 1 e" s2 $end 808 | $var wire 1 f" s1 $end 809 | $var wire 1 _" s $end 810 | $var wire 1 `" coutput $end 811 | $scope module x1 $end 812 | $var wire 1 X" i0 $end 813 | $var wire 1 a" i1 $end 814 | $var wire 1 c" o $end 815 | $upscope $end 816 | $scope module x2 $end 817 | $var wire 1 c" i0 $end 818 | $var wire 1 G i1 $end 819 | $var wire 1 _" o $end 820 | $upscope $end 821 | $scope module x3 $end 822 | $var wire 1 b" o $end 823 | $var wire 1 e" i1 $end 824 | $var wire 1 f" i0 $end 825 | $upscope $end 826 | $scope module x4 $end 827 | $var wire 1 b" i0 $end 828 | $var wire 1 `" o $end 829 | $var wire 1 d" i1 $end 830 | $upscope $end 831 | $scope module y1 $end 832 | $var wire 1 X" i0 $end 833 | $var wire 1 a" i1 $end 834 | $var wire 1 f" o $end 835 | $upscope $end 836 | $scope module y2 $end 837 | $var wire 1 a" i0 $end 838 | $var wire 1 G i1 $end 839 | $var wire 1 e" o $end 840 | $upscope $end 841 | $scope module y3 $end 842 | $var wire 1 X" i0 $end 843 | $var wire 1 G i1 $end 844 | $var wire 1 d" o $end 845 | $upscope $end 846 | $upscope $end 847 | $upscope $end 848 | $scope module b1 $end 849 | $var wire 1 X" i0 $end 850 | $var wire 1 Y" i1 $end 851 | $var wire 1 ]" o $end 852 | $upscope $end 853 | $scope module b2 $end 854 | $var wire 1 X" i0 $end 855 | $var wire 1 Y" i1 $end 856 | $var wire 1 \" o $end 857 | $upscope $end 858 | $scope module b3 $end 859 | $var wire 1 ]" i0 $end 860 | $var wire 1 \" i1 $end 861 | $var wire 1 g" j $end 862 | $var wire 1 [" o $end 863 | $upscope $end 864 | $scope module b4 $end 865 | $var wire 1 [" i0 $end 866 | $var wire 1 _" i1 $end 867 | $var wire 1 h" j $end 868 | $var wire 1 ^" o $end 869 | $upscope $end 870 | $upscope $end 871 | $scope module a3 $end 872 | $var wire 1 `" cin $end 873 | $var wire 1 i" i0 $end 874 | $var wire 1 j" i1 $end 875 | $var wire 2 k" op [1:0] $end 876 | $var wire 1 l" t3 $end 877 | $var wire 1 m" t2 $end 878 | $var wire 1 n" t1 $end 879 | $var wire 1 o" o $end 880 | $var wire 1 p" f1 $end 881 | $var wire 1 q" carry $end 882 | $scope module b0 $end 883 | $var wire 1 `" cin $end 884 | $var wire 1 i" i0 $end 885 | $var wire 1 j" i1 $end 886 | $var wire 1 r" t4 $end 887 | $var wire 1 p" o $end 888 | $var wire 1 q" carry $end 889 | $scope module c1 $end 890 | $var wire 1 j" i0 $end 891 | $var wire 1 `" i1 $end 892 | $var wire 1 r" o $end 893 | $upscope $end 894 | $scope module c2 $end 895 | $var wire 1 i" a $end 896 | $var wire 1 r" b $end 897 | $var wire 1 `" c $end 898 | $var wire 1 s" z1 $end 899 | $var wire 1 t" t1 $end 900 | $var wire 1 u" s3 $end 901 | $var wire 1 v" s2 $end 902 | $var wire 1 w" s1 $end 903 | $var wire 1 p" s $end 904 | $var wire 1 q" coutput $end 905 | $scope module x1 $end 906 | $var wire 1 i" i0 $end 907 | $var wire 1 r" i1 $end 908 | $var wire 1 t" o $end 909 | $upscope $end 910 | $scope module x2 $end 911 | $var wire 1 t" i0 $end 912 | $var wire 1 `" i1 $end 913 | $var wire 1 p" o $end 914 | $upscope $end 915 | $scope module x3 $end 916 | $var wire 1 s" o $end 917 | $var wire 1 v" i1 $end 918 | $var wire 1 w" i0 $end 919 | $upscope $end 920 | $scope module x4 $end 921 | $var wire 1 s" i0 $end 922 | $var wire 1 q" o $end 923 | $var wire 1 u" i1 $end 924 | $upscope $end 925 | $scope module y1 $end 926 | $var wire 1 i" i0 $end 927 | $var wire 1 r" i1 $end 928 | $var wire 1 w" o $end 929 | $upscope $end 930 | $scope module y2 $end 931 | $var wire 1 r" i0 $end 932 | $var wire 1 `" i1 $end 933 | $var wire 1 v" o $end 934 | $upscope $end 935 | $scope module y3 $end 936 | $var wire 1 i" i0 $end 937 | $var wire 1 `" i1 $end 938 | $var wire 1 u" o $end 939 | $upscope $end 940 | $upscope $end 941 | $upscope $end 942 | $scope module b1 $end 943 | $var wire 1 i" i0 $end 944 | $var wire 1 j" i1 $end 945 | $var wire 1 n" o $end 946 | $upscope $end 947 | $scope module b2 $end 948 | $var wire 1 i" i0 $end 949 | $var wire 1 j" i1 $end 950 | $var wire 1 m" o $end 951 | $upscope $end 952 | $scope module b3 $end 953 | $var wire 1 n" i0 $end 954 | $var wire 1 m" i1 $end 955 | $var wire 1 x" j $end 956 | $var wire 1 l" o $end 957 | $upscope $end 958 | $scope module b4 $end 959 | $var wire 1 l" i0 $end 960 | $var wire 1 p" i1 $end 961 | $var wire 1 y" j $end 962 | $var wire 1 o" o $end 963 | $upscope $end 964 | $upscope $end 965 | $scope module a4 $end 966 | $var wire 1 q" cin $end 967 | $var wire 1 z" i0 $end 968 | $var wire 1 {" i1 $end 969 | $var wire 2 |" op [1:0] $end 970 | $var wire 1 }" t3 $end 971 | $var wire 1 ~" t2 $end 972 | $var wire 1 !# t1 $end 973 | $var wire 1 "# o $end 974 | $var wire 1 ## f1 $end 975 | $var wire 1 $# carry $end 976 | $scope module b0 $end 977 | $var wire 1 q" cin $end 978 | $var wire 1 z" i0 $end 979 | $var wire 1 {" i1 $end 980 | $var wire 1 %# t4 $end 981 | $var wire 1 ## o $end 982 | $var wire 1 $# carry $end 983 | $scope module c1 $end 984 | $var wire 1 {" i0 $end 985 | $var wire 1 q" i1 $end 986 | $var wire 1 %# o $end 987 | $upscope $end 988 | $scope module c2 $end 989 | $var wire 1 z" a $end 990 | $var wire 1 %# b $end 991 | $var wire 1 q" c $end 992 | $var wire 1 &# z1 $end 993 | $var wire 1 '# t1 $end 994 | $var wire 1 (# s3 $end 995 | $var wire 1 )# s2 $end 996 | $var wire 1 *# s1 $end 997 | $var wire 1 ## s $end 998 | $var wire 1 $# coutput $end 999 | $scope module x1 $end 1000 | $var wire 1 z" i0 $end 1001 | $var wire 1 %# i1 $end 1002 | $var wire 1 '# o $end 1003 | $upscope $end 1004 | $scope module x2 $end 1005 | $var wire 1 '# i0 $end 1006 | $var wire 1 q" i1 $end 1007 | $var wire 1 ## o $end 1008 | $upscope $end 1009 | $scope module x3 $end 1010 | $var wire 1 &# o $end 1011 | $var wire 1 )# i1 $end 1012 | $var wire 1 *# i0 $end 1013 | $upscope $end 1014 | $scope module x4 $end 1015 | $var wire 1 &# i0 $end 1016 | $var wire 1 $# o $end 1017 | $var wire 1 (# i1 $end 1018 | $upscope $end 1019 | $scope module y1 $end 1020 | $var wire 1 z" i0 $end 1021 | $var wire 1 %# i1 $end 1022 | $var wire 1 *# o $end 1023 | $upscope $end 1024 | $scope module y2 $end 1025 | $var wire 1 %# i0 $end 1026 | $var wire 1 q" i1 $end 1027 | $var wire 1 )# o $end 1028 | $upscope $end 1029 | $scope module y3 $end 1030 | $var wire 1 z" i0 $end 1031 | $var wire 1 q" i1 $end 1032 | $var wire 1 (# o $end 1033 | $upscope $end 1034 | $upscope $end 1035 | $upscope $end 1036 | $scope module b1 $end 1037 | $var wire 1 z" i0 $end 1038 | $var wire 1 {" i1 $end 1039 | $var wire 1 !# o $end 1040 | $upscope $end 1041 | $scope module b2 $end 1042 | $var wire 1 z" i0 $end 1043 | $var wire 1 {" i1 $end 1044 | $var wire 1 ~" o $end 1045 | $upscope $end 1046 | $scope module b3 $end 1047 | $var wire 1 !# i0 $end 1048 | $var wire 1 ~" i1 $end 1049 | $var wire 1 +# j $end 1050 | $var wire 1 }" o $end 1051 | $upscope $end 1052 | $scope module b4 $end 1053 | $var wire 1 }" i0 $end 1054 | $var wire 1 ## i1 $end 1055 | $var wire 1 ,# j $end 1056 | $var wire 1 "# o $end 1057 | $upscope $end 1058 | $upscope $end 1059 | $scope module a5 $end 1060 | $var wire 1 $# cin $end 1061 | $var wire 1 -# i0 $end 1062 | $var wire 1 .# i1 $end 1063 | $var wire 2 /# op [1:0] $end 1064 | $var wire 1 0# t3 $end 1065 | $var wire 1 1# t2 $end 1066 | $var wire 1 2# t1 $end 1067 | $var wire 1 3# o $end 1068 | $var wire 1 4# f1 $end 1069 | $var wire 1 5# carry $end 1070 | $scope module b0 $end 1071 | $var wire 1 $# cin $end 1072 | $var wire 1 -# i0 $end 1073 | $var wire 1 .# i1 $end 1074 | $var wire 1 6# t4 $end 1075 | $var wire 1 4# o $end 1076 | $var wire 1 5# carry $end 1077 | $scope module c1 $end 1078 | $var wire 1 .# i0 $end 1079 | $var wire 1 $# i1 $end 1080 | $var wire 1 6# o $end 1081 | $upscope $end 1082 | $scope module c2 $end 1083 | $var wire 1 -# a $end 1084 | $var wire 1 6# b $end 1085 | $var wire 1 $# c $end 1086 | $var wire 1 7# z1 $end 1087 | $var wire 1 8# t1 $end 1088 | $var wire 1 9# s3 $end 1089 | $var wire 1 :# s2 $end 1090 | $var wire 1 ;# s1 $end 1091 | $var wire 1 4# s $end 1092 | $var wire 1 5# coutput $end 1093 | $scope module x1 $end 1094 | $var wire 1 -# i0 $end 1095 | $var wire 1 6# i1 $end 1096 | $var wire 1 8# o $end 1097 | $upscope $end 1098 | $scope module x2 $end 1099 | $var wire 1 8# i0 $end 1100 | $var wire 1 $# i1 $end 1101 | $var wire 1 4# o $end 1102 | $upscope $end 1103 | $scope module x3 $end 1104 | $var wire 1 7# o $end 1105 | $var wire 1 :# i1 $end 1106 | $var wire 1 ;# i0 $end 1107 | $upscope $end 1108 | $scope module x4 $end 1109 | $var wire 1 7# i0 $end 1110 | $var wire 1 5# o $end 1111 | $var wire 1 9# i1 $end 1112 | $upscope $end 1113 | $scope module y1 $end 1114 | $var wire 1 -# i0 $end 1115 | $var wire 1 6# i1 $end 1116 | $var wire 1 ;# o $end 1117 | $upscope $end 1118 | $scope module y2 $end 1119 | $var wire 1 6# i0 $end 1120 | $var wire 1 $# i1 $end 1121 | $var wire 1 :# o $end 1122 | $upscope $end 1123 | $scope module y3 $end 1124 | $var wire 1 -# i0 $end 1125 | $var wire 1 $# i1 $end 1126 | $var wire 1 9# o $end 1127 | $upscope $end 1128 | $upscope $end 1129 | $upscope $end 1130 | $scope module b1 $end 1131 | $var wire 1 -# i0 $end 1132 | $var wire 1 .# i1 $end 1133 | $var wire 1 2# o $end 1134 | $upscope $end 1135 | $scope module b2 $end 1136 | $var wire 1 -# i0 $end 1137 | $var wire 1 .# i1 $end 1138 | $var wire 1 1# o $end 1139 | $upscope $end 1140 | $scope module b3 $end 1141 | $var wire 1 2# i0 $end 1142 | $var wire 1 1# i1 $end 1143 | $var wire 1 <# j $end 1144 | $var wire 1 0# o $end 1145 | $upscope $end 1146 | $scope module b4 $end 1147 | $var wire 1 0# i0 $end 1148 | $var wire 1 4# i1 $end 1149 | $var wire 1 =# j $end 1150 | $var wire 1 3# o $end 1151 | $upscope $end 1152 | $upscope $end 1153 | $scope module a6 $end 1154 | $var wire 1 5# cin $end 1155 | $var wire 1 ># i0 $end 1156 | $var wire 1 ?# i1 $end 1157 | $var wire 2 @# op [1:0] $end 1158 | $var wire 1 A# t3 $end 1159 | $var wire 1 B# t2 $end 1160 | $var wire 1 C# t1 $end 1161 | $var wire 1 D# o $end 1162 | $var wire 1 E# f1 $end 1163 | $var wire 1 F# carry $end 1164 | $scope module b0 $end 1165 | $var wire 1 5# cin $end 1166 | $var wire 1 ># i0 $end 1167 | $var wire 1 ?# i1 $end 1168 | $var wire 1 G# t4 $end 1169 | $var wire 1 E# o $end 1170 | $var wire 1 F# carry $end 1171 | $scope module c1 $end 1172 | $var wire 1 ?# i0 $end 1173 | $var wire 1 5# i1 $end 1174 | $var wire 1 G# o $end 1175 | $upscope $end 1176 | $scope module c2 $end 1177 | $var wire 1 ># a $end 1178 | $var wire 1 G# b $end 1179 | $var wire 1 5# c $end 1180 | $var wire 1 H# z1 $end 1181 | $var wire 1 I# t1 $end 1182 | $var wire 1 J# s3 $end 1183 | $var wire 1 K# s2 $end 1184 | $var wire 1 L# s1 $end 1185 | $var wire 1 E# s $end 1186 | $var wire 1 F# coutput $end 1187 | $scope module x1 $end 1188 | $var wire 1 ># i0 $end 1189 | $var wire 1 G# i1 $end 1190 | $var wire 1 I# o $end 1191 | $upscope $end 1192 | $scope module x2 $end 1193 | $var wire 1 I# i0 $end 1194 | $var wire 1 5# i1 $end 1195 | $var wire 1 E# o $end 1196 | $upscope $end 1197 | $scope module x3 $end 1198 | $var wire 1 H# o $end 1199 | $var wire 1 K# i1 $end 1200 | $var wire 1 L# i0 $end 1201 | $upscope $end 1202 | $scope module x4 $end 1203 | $var wire 1 H# i0 $end 1204 | $var wire 1 F# o $end 1205 | $var wire 1 J# i1 $end 1206 | $upscope $end 1207 | $scope module y1 $end 1208 | $var wire 1 ># i0 $end 1209 | $var wire 1 G# i1 $end 1210 | $var wire 1 L# o $end 1211 | $upscope $end 1212 | $scope module y2 $end 1213 | $var wire 1 G# i0 $end 1214 | $var wire 1 5# i1 $end 1215 | $var wire 1 K# o $end 1216 | $upscope $end 1217 | $scope module y3 $end 1218 | $var wire 1 ># i0 $end 1219 | $var wire 1 5# i1 $end 1220 | $var wire 1 J# o $end 1221 | $upscope $end 1222 | $upscope $end 1223 | $upscope $end 1224 | $scope module b1 $end 1225 | $var wire 1 ># i0 $end 1226 | $var wire 1 ?# i1 $end 1227 | $var wire 1 C# o $end 1228 | $upscope $end 1229 | $scope module b2 $end 1230 | $var wire 1 ># i0 $end 1231 | $var wire 1 ?# i1 $end 1232 | $var wire 1 B# o $end 1233 | $upscope $end 1234 | $scope module b3 $end 1235 | $var wire 1 C# i0 $end 1236 | $var wire 1 B# i1 $end 1237 | $var wire 1 M# j $end 1238 | $var wire 1 A# o $end 1239 | $upscope $end 1240 | $scope module b4 $end 1241 | $var wire 1 A# i0 $end 1242 | $var wire 1 E# i1 $end 1243 | $var wire 1 N# j $end 1244 | $var wire 1 D# o $end 1245 | $upscope $end 1246 | $upscope $end 1247 | $scope module a7 $end 1248 | $var wire 1 F# cin $end 1249 | $var wire 1 O# i0 $end 1250 | $var wire 1 P# i1 $end 1251 | $var wire 2 Q# op [1:0] $end 1252 | $var wire 1 R# t3 $end 1253 | $var wire 1 S# t2 $end 1254 | $var wire 1 T# t1 $end 1255 | $var wire 1 U# o $end 1256 | $var wire 1 V# f1 $end 1257 | $var wire 1 W# carry $end 1258 | $scope module b0 $end 1259 | $var wire 1 F# cin $end 1260 | $var wire 1 O# i0 $end 1261 | $var wire 1 P# i1 $end 1262 | $var wire 1 X# t4 $end 1263 | $var wire 1 V# o $end 1264 | $var wire 1 W# carry $end 1265 | $scope module c1 $end 1266 | $var wire 1 P# i0 $end 1267 | $var wire 1 F# i1 $end 1268 | $var wire 1 X# o $end 1269 | $upscope $end 1270 | $scope module c2 $end 1271 | $var wire 1 O# a $end 1272 | $var wire 1 X# b $end 1273 | $var wire 1 F# c $end 1274 | $var wire 1 Y# z1 $end 1275 | $var wire 1 Z# t1 $end 1276 | $var wire 1 [# s3 $end 1277 | $var wire 1 \# s2 $end 1278 | $var wire 1 ]# s1 $end 1279 | $var wire 1 V# s $end 1280 | $var wire 1 W# coutput $end 1281 | $scope module x1 $end 1282 | $var wire 1 O# i0 $end 1283 | $var wire 1 X# i1 $end 1284 | $var wire 1 Z# o $end 1285 | $upscope $end 1286 | $scope module x2 $end 1287 | $var wire 1 Z# i0 $end 1288 | $var wire 1 F# i1 $end 1289 | $var wire 1 V# o $end 1290 | $upscope $end 1291 | $scope module x3 $end 1292 | $var wire 1 Y# o $end 1293 | $var wire 1 \# i1 $end 1294 | $var wire 1 ]# i0 $end 1295 | $upscope $end 1296 | $scope module x4 $end 1297 | $var wire 1 Y# i0 $end 1298 | $var wire 1 W# o $end 1299 | $var wire 1 [# i1 $end 1300 | $upscope $end 1301 | $scope module y1 $end 1302 | $var wire 1 O# i0 $end 1303 | $var wire 1 X# i1 $end 1304 | $var wire 1 ]# o $end 1305 | $upscope $end 1306 | $scope module y2 $end 1307 | $var wire 1 X# i0 $end 1308 | $var wire 1 F# i1 $end 1309 | $var wire 1 \# o $end 1310 | $upscope $end 1311 | $scope module y3 $end 1312 | $var wire 1 O# i0 $end 1313 | $var wire 1 F# i1 $end 1314 | $var wire 1 [# o $end 1315 | $upscope $end 1316 | $upscope $end 1317 | $upscope $end 1318 | $scope module b1 $end 1319 | $var wire 1 O# i0 $end 1320 | $var wire 1 P# i1 $end 1321 | $var wire 1 T# o $end 1322 | $upscope $end 1323 | $scope module b2 $end 1324 | $var wire 1 O# i0 $end 1325 | $var wire 1 P# i1 $end 1326 | $var wire 1 S# o $end 1327 | $upscope $end 1328 | $scope module b3 $end 1329 | $var wire 1 T# i0 $end 1330 | $var wire 1 S# i1 $end 1331 | $var wire 1 ^# j $end 1332 | $var wire 1 R# o $end 1333 | $upscope $end 1334 | $scope module b4 $end 1335 | $var wire 1 R# i0 $end 1336 | $var wire 1 V# i1 $end 1337 | $var wire 1 _# j $end 1338 | $var wire 1 U# o $end 1339 | $upscope $end 1340 | $upscope $end 1341 | $scope module a8 $end 1342 | $var wire 1 W# cin $end 1343 | $var wire 1 `# i0 $end 1344 | $var wire 1 a# i1 $end 1345 | $var wire 2 b# op [1:0] $end 1346 | $var wire 1 c# t3 $end 1347 | $var wire 1 d# t2 $end 1348 | $var wire 1 e# t1 $end 1349 | $var wire 1 f# o $end 1350 | $var wire 1 g# f1 $end 1351 | $var wire 1 h# carry $end 1352 | $scope module b0 $end 1353 | $var wire 1 W# cin $end 1354 | $var wire 1 `# i0 $end 1355 | $var wire 1 a# i1 $end 1356 | $var wire 1 i# t4 $end 1357 | $var wire 1 g# o $end 1358 | $var wire 1 h# carry $end 1359 | $scope module c1 $end 1360 | $var wire 1 a# i0 $end 1361 | $var wire 1 W# i1 $end 1362 | $var wire 1 i# o $end 1363 | $upscope $end 1364 | $scope module c2 $end 1365 | $var wire 1 `# a $end 1366 | $var wire 1 i# b $end 1367 | $var wire 1 W# c $end 1368 | $var wire 1 j# z1 $end 1369 | $var wire 1 k# t1 $end 1370 | $var wire 1 l# s3 $end 1371 | $var wire 1 m# s2 $end 1372 | $var wire 1 n# s1 $end 1373 | $var wire 1 g# s $end 1374 | $var wire 1 h# coutput $end 1375 | $scope module x1 $end 1376 | $var wire 1 `# i0 $end 1377 | $var wire 1 i# i1 $end 1378 | $var wire 1 k# o $end 1379 | $upscope $end 1380 | $scope module x2 $end 1381 | $var wire 1 k# i0 $end 1382 | $var wire 1 W# i1 $end 1383 | $var wire 1 g# o $end 1384 | $upscope $end 1385 | $scope module x3 $end 1386 | $var wire 1 j# o $end 1387 | $var wire 1 m# i1 $end 1388 | $var wire 1 n# i0 $end 1389 | $upscope $end 1390 | $scope module x4 $end 1391 | $var wire 1 j# i0 $end 1392 | $var wire 1 h# o $end 1393 | $var wire 1 l# i1 $end 1394 | $upscope $end 1395 | $scope module y1 $end 1396 | $var wire 1 `# i0 $end 1397 | $var wire 1 i# i1 $end 1398 | $var wire 1 n# o $end 1399 | $upscope $end 1400 | $scope module y2 $end 1401 | $var wire 1 i# i0 $end 1402 | $var wire 1 W# i1 $end 1403 | $var wire 1 m# o $end 1404 | $upscope $end 1405 | $scope module y3 $end 1406 | $var wire 1 `# i0 $end 1407 | $var wire 1 W# i1 $end 1408 | $var wire 1 l# o $end 1409 | $upscope $end 1410 | $upscope $end 1411 | $upscope $end 1412 | $scope module b1 $end 1413 | $var wire 1 `# i0 $end 1414 | $var wire 1 a# i1 $end 1415 | $var wire 1 e# o $end 1416 | $upscope $end 1417 | $scope module b2 $end 1418 | $var wire 1 `# i0 $end 1419 | $var wire 1 a# i1 $end 1420 | $var wire 1 d# o $end 1421 | $upscope $end 1422 | $scope module b3 $end 1423 | $var wire 1 e# i0 $end 1424 | $var wire 1 d# i1 $end 1425 | $var wire 1 o# j $end 1426 | $var wire 1 c# o $end 1427 | $upscope $end 1428 | $scope module b4 $end 1429 | $var wire 1 c# i0 $end 1430 | $var wire 1 g# i1 $end 1431 | $var wire 1 p# j $end 1432 | $var wire 1 f# o $end 1433 | $upscope $end 1434 | $upscope $end 1435 | $scope module a9 $end 1436 | $var wire 1 h# cin $end 1437 | $var wire 1 q# i0 $end 1438 | $var wire 1 r# i1 $end 1439 | $var wire 2 s# op [1:0] $end 1440 | $var wire 1 t# t3 $end 1441 | $var wire 1 u# t2 $end 1442 | $var wire 1 v# t1 $end 1443 | $var wire 1 w# o $end 1444 | $var wire 1 x# f1 $end 1445 | $var wire 1 X carry $end 1446 | $scope module b0 $end 1447 | $var wire 1 h# cin $end 1448 | $var wire 1 q# i0 $end 1449 | $var wire 1 r# i1 $end 1450 | $var wire 1 y# t4 $end 1451 | $var wire 1 x# o $end 1452 | $var wire 1 X carry $end 1453 | $scope module c1 $end 1454 | $var wire 1 r# i0 $end 1455 | $var wire 1 h# i1 $end 1456 | $var wire 1 y# o $end 1457 | $upscope $end 1458 | $scope module c2 $end 1459 | $var wire 1 q# a $end 1460 | $var wire 1 y# b $end 1461 | $var wire 1 h# c $end 1462 | $var wire 1 z# z1 $end 1463 | $var wire 1 {# t1 $end 1464 | $var wire 1 |# s3 $end 1465 | $var wire 1 }# s2 $end 1466 | $var wire 1 ~# s1 $end 1467 | $var wire 1 x# s $end 1468 | $var wire 1 X coutput $end 1469 | $scope module x1 $end 1470 | $var wire 1 q# i0 $end 1471 | $var wire 1 y# i1 $end 1472 | $var wire 1 {# o $end 1473 | $upscope $end 1474 | $scope module x2 $end 1475 | $var wire 1 {# i0 $end 1476 | $var wire 1 h# i1 $end 1477 | $var wire 1 x# o $end 1478 | $upscope $end 1479 | $scope module x3 $end 1480 | $var wire 1 z# o $end 1481 | $var wire 1 }# i1 $end 1482 | $var wire 1 ~# i0 $end 1483 | $upscope $end 1484 | $scope module x4 $end 1485 | $var wire 1 z# i0 $end 1486 | $var wire 1 X o $end 1487 | $var wire 1 |# i1 $end 1488 | $upscope $end 1489 | $scope module y1 $end 1490 | $var wire 1 q# i0 $end 1491 | $var wire 1 y# i1 $end 1492 | $var wire 1 ~# o $end 1493 | $upscope $end 1494 | $scope module y2 $end 1495 | $var wire 1 y# i0 $end 1496 | $var wire 1 h# i1 $end 1497 | $var wire 1 }# o $end 1498 | $upscope $end 1499 | $scope module y3 $end 1500 | $var wire 1 q# i0 $end 1501 | $var wire 1 h# i1 $end 1502 | $var wire 1 |# o $end 1503 | $upscope $end 1504 | $upscope $end 1505 | $upscope $end 1506 | $scope module b1 $end 1507 | $var wire 1 q# i0 $end 1508 | $var wire 1 r# i1 $end 1509 | $var wire 1 v# o $end 1510 | $upscope $end 1511 | $scope module b2 $end 1512 | $var wire 1 q# i0 $end 1513 | $var wire 1 r# i1 $end 1514 | $var wire 1 u# o $end 1515 | $upscope $end 1516 | $scope module b3 $end 1517 | $var wire 1 v# i0 $end 1518 | $var wire 1 u# i1 $end 1519 | $var wire 1 !$ j $end 1520 | $var wire 1 t# o $end 1521 | $upscope $end 1522 | $scope module b4 $end 1523 | $var wire 1 t# i0 $end 1524 | $var wire 1 x# i1 $end 1525 | $var wire 1 "$ j $end 1526 | $var wire 1 w# o $end 1527 | $upscope $end 1528 | $upscope $end 1529 | $upscope $end 1530 | $upscope $end 1531 | $enddefinitions $end 1532 | #0 1533 | $dumpvars 1534 | 0"$ 1535 | 0!$ 1536 | 0~# 1537 | 0}# 1538 | 0|# 1539 | 0{# 1540 | 0z# 1541 | 0y# 1542 | 0x# 1543 | 0w# 1544 | 0v# 1545 | 0u# 1546 | 0t# 1547 | b0 s# 1548 | 0r# 1549 | 0q# 1550 | 0p# 1551 | 0o# 1552 | 0n# 1553 | 0m# 1554 | 0l# 1555 | 0k# 1556 | 0j# 1557 | 0i# 1558 | 0h# 1559 | 0g# 1560 | 0f# 1561 | 0e# 1562 | 0d# 1563 | 0c# 1564 | b0 b# 1565 | 0a# 1566 | 0`# 1567 | 0_# 1568 | 0^# 1569 | 0]# 1570 | 0\# 1571 | 0[# 1572 | 0Z# 1573 | 0Y# 1574 | 0X# 1575 | 0W# 1576 | 0V# 1577 | 0U# 1578 | 0T# 1579 | 0S# 1580 | 0R# 1581 | b0 Q# 1582 | 0P# 1583 | 0O# 1584 | 0N# 1585 | 0M# 1586 | 0L# 1587 | 0K# 1588 | 0J# 1589 | 0I# 1590 | 0H# 1591 | 0G# 1592 | 0F# 1593 | 0E# 1594 | 0D# 1595 | 0C# 1596 | 0B# 1597 | 0A# 1598 | b0 @# 1599 | 0?# 1600 | 0># 1601 | 0=# 1602 | 0<# 1603 | 0;# 1604 | 0:# 1605 | 09# 1606 | 08# 1607 | 07# 1608 | 06# 1609 | 05# 1610 | 04# 1611 | 03# 1612 | 02# 1613 | 01# 1614 | 00# 1615 | b0 /# 1616 | 0.# 1617 | 0-# 1618 | 0,# 1619 | 0+# 1620 | 0*# 1621 | 0)# 1622 | 0(# 1623 | 0'# 1624 | 0&# 1625 | 0%# 1626 | 0$# 1627 | 0## 1628 | 0"# 1629 | 0!# 1630 | 0~" 1631 | 0}" 1632 | b0 |" 1633 | 0{" 1634 | 0z" 1635 | 0y" 1636 | 0x" 1637 | 0w" 1638 | 0v" 1639 | 0u" 1640 | 0t" 1641 | 0s" 1642 | 0r" 1643 | 0q" 1644 | 0p" 1645 | 0o" 1646 | 0n" 1647 | 0m" 1648 | 0l" 1649 | b0 k" 1650 | 0j" 1651 | 0i" 1652 | 0h" 1653 | 0g" 1654 | 0f" 1655 | 0e" 1656 | 0d" 1657 | 0c" 1658 | 0b" 1659 | 0a" 1660 | 0`" 1661 | 0_" 1662 | 0^" 1663 | 0]" 1664 | 0\" 1665 | 0[" 1666 | b0 Z" 1667 | 0Y" 1668 | 0X" 1669 | 0W" 1670 | 0V" 1671 | 0U" 1672 | 0T" 1673 | 0S" 1674 | 0R" 1675 | 0Q" 1676 | 0P" 1677 | 0O" 1678 | 0N" 1679 | 0M" 1680 | 0L" 1681 | 0K" 1682 | b0 J" 1683 | 0I" 1684 | 0H" 1685 | 0G" 1686 | 0F" 1687 | 0E" 1688 | 0D" 1689 | 0C" 1690 | 0B" 1691 | 0A" 1692 | 0@" 1693 | 0?" 1694 | 0>" 1695 | 0=" 1696 | 0<" 1697 | 0;" 1698 | 0:" 1699 | b0 9" 1700 | 08" 1701 | 07" 1702 | 06" 1703 | 05" 1704 | 04" 1705 | 03" 1706 | 02" 1707 | 01" 1708 | 00" 1709 | 0/" 1710 | 0." 1711 | 0-" 1712 | 0," 1713 | 0+" 1714 | 0*" 1715 | 0)" 1716 | b0 (" 1717 | 0'" 1718 | 0&" 1719 | 0%" 1720 | 0$" 1721 | 0#" 1722 | 0"" 1723 | 0!" 1724 | 0~ 1725 | 0} 1726 | 0| 1727 | 0{ 1728 | 0z 1729 | 0y 1730 | 0x 1731 | 0w 1732 | 0v 1733 | b0 u 1734 | 0t 1735 | 0s 1736 | 0r 1737 | 0q 1738 | 0p 1739 | 0o 1740 | 0n 1741 | 0m 1742 | 0l 1743 | 0k 1744 | 0j 1745 | 0i 1746 | 0h 1747 | 0g 1748 | 0f 1749 | 0e 1750 | b0 d 1751 | 0c 1752 | 0b 1753 | 0a 1754 | 0` 1755 | 0_ 1756 | 0^ 1757 | 0] 1758 | 0\ 1759 | 0[ 1760 | 0Z 1761 | 0Y 1762 | 0X 1763 | 0W 1764 | 0V 1765 | 0U 1766 | 0T 1767 | 0S 1768 | b0 R 1769 | 0Q 1770 | 0P 1771 | 0O 1772 | 0N 1773 | 0M 1774 | 0L 1775 | 0K 1776 | 0J 1777 | 0I 1778 | 0H 1779 | 0G 1780 | 0F 1781 | 0E 1782 | 0D 1783 | 0C 1784 | 0B 1785 | b0 A 1786 | 0@ 1787 | 0? 1788 | 0> 1789 | 0= 1790 | 0< 1791 | 0; 1792 | 0: 1793 | 09 1794 | 08 1795 | 07 1796 | 06 1797 | 05 1798 | 04 1799 | 03 1800 | 02 1801 | 01 1802 | b0 0 1803 | 0/ 1804 | 0. 1805 | 0- 1806 | b0 , 1807 | b0 + 1808 | b0 * 1809 | b0 ) 1810 | bx ( 1811 | 1' 1812 | b0 & 1813 | b0 % 1814 | b0 $ 1815 | 0# 1816 | 0" 1817 | b0 ! 1818 | $end 1819 | #50 1820 | 1# 1821 | #60 1822 | b0 ( 1823 | #100 1824 | 0# 1825 | #125 1826 | 0' 1827 | #150 1828 | 1# 1829 | #160 1830 | b1 ( 1831 | #200 1832 | 0# 1833 | #250 1834 | 1# 1835 | #260 1836 | 1F 1837 | 1p" 1838 | 14# 1839 | 1V# 1840 | 1g# 1841 | 1W 1842 | 1z 1843 | 1>" 1844 | 15 1845 | 1_" 1846 | 1## 1847 | 1E# 1848 | 1x# 1849 | 1i 1850 | 1-" 1851 | 1O" 1852 | 1J 1853 | 1t" 1854 | 18# 1855 | 1Z# 1856 | 1k# 1857 | 1\ 1858 | 1~ 1859 | 1B" 1860 | 19 1861 | 12 1862 | 1c" 1863 | 1\" 1864 | 1'# 1865 | 1~" 1866 | 1I# 1867 | 1B# 1868 | 1{# 1869 | 1u# 1870 | 1m 1871 | 1f 1872 | 11" 1873 | 1*" 1874 | 1R" 1875 | 1L" 1876 | 1H 1877 | 1C 1878 | 1r" 1879 | 1m" 1880 | 16# 1881 | 11# 1882 | 1X# 1883 | 1S# 1884 | 1i# 1885 | 1d# 1886 | 1Z 1887 | 1T 1888 | 1| 1889 | 1w 1890 | 1@" 1891 | 1;" 1892 | 1. 1893 | 1X" 1894 | 1z" 1895 | 1># 1896 | 1q# 1897 | 1b 1898 | 1&" 1899 | 1H" 1900 | 1@ 1901 | 1j" 1902 | 1.# 1903 | 1P# 1904 | 1a# 1905 | 1Q 1906 | 1t 1907 | 18" 1908 | b10 ( 1909 | b1010101001010101 $ 1910 | b1010101001010101 ) 1911 | b101010110101010 % 1912 | b101010110101010 * 1913 | #300 1914 | 0# 1915 | #350 1916 | 1# 1917 | #360 1918 | 1Q" 1919 | 0R" 1920 | 1U" 1921 | 1T" 1922 | 1" 1923 | 1A" 1924 | 1P" 1925 | 1O" 1926 | 1S" 1927 | 0B" 1928 | 1E" 1929 | 1D" 1930 | 1?" 1931 | 10" 1932 | 1>" 1933 | 1C" 1934 | 01" 1935 | 14" 1936 | 13" 1937 | 1." 1938 | 1} 1939 | 1/" 1940 | 1-" 1941 | 12" 1942 | 0~ 1943 | 1#" 1944 | 1"" 1945 | 1{ 1946 | 1l 1947 | 1z 1948 | 1!" 1949 | 0m 1950 | 1p 1951 | 1o 1952 | 1j 1953 | 1k 1954 | 1i 1955 | 1n 1956 | 1Y 1957 | 1[ 1958 | 0\ 1959 | 1_ 1960 | 1z# 1961 | 1] 1962 | 1^ 1963 | 1W 1964 | 0{# 1965 | 1~# 1966 | 1}# 1967 | 1X 1968 | 1j# 1969 | 1y# 1970 | 1x# 1971 | 1|# 1972 | 0k# 1973 | 1n# 1974 | 1m# 1975 | 1h# 1976 | 1Y# 1977 | 1g# 1978 | 1l# 1979 | 0Z# 1980 | 1]# 1981 | 1\# 1982 | 1W# 1983 | 1H# 1984 | 1V# 1985 | 1[# 1986 | 0I# 1987 | 1L# 1988 | 1K# 1989 | 1F# 1990 | 17# 1991 | 1G# 1992 | 1E# 1993 | 1J# 1994 | 08# 1995 | 1;# 1996 | 1:# 1997 | 15# 1998 | 1&# 1999 | 14# 2000 | 19# 2001 | 0'# 2002 | 1*# 2003 | 1)# 2004 | 1$# 2005 | 1s" 2006 | 1%# 2007 | 1## 2008 | 1(# 2009 | 0t" 2010 | 1w" 2011 | 1v" 2012 | 1q" 2013 | 1b" 2014 | 1p" 2015 | 1u" 2016 | 0c" 2017 | 1f" 2018 | 1e" 2019 | 1`" 2020 | 1I 2021 | 1a" 2022 | 1_" 2023 | 1d" 2024 | 0J 2025 | 1M 2026 | 1L 2027 | 1G 2028 | 1F 2029 | 1K 2030 | 16 2031 | 05 2032 | 18 2033 | b1 ! 2034 | b1 , 2035 | 14 2036 | 09 2037 | 1< 2038 | 11 2039 | 17 2040 | 13 2041 | 1H 2042 | 1r" 2043 | 16# 2044 | 1X# 2045 | 1i# 2046 | 1Z 2047 | 1| 2048 | 1@" 2049 | 1? 2050 | 1i" 2051 | 1-# 2052 | 1O# 2053 | 1`# 2054 | 1P 2055 | 1s 2056 | 17" 2057 | 1/ 2058 | 0@ 2059 | 0j" 2060 | 0.# 2061 | 0P# 2062 | 0a# 2063 | 0Q 2064 | 0t 2065 | 08" 2066 | b11 ( 2067 | b1111111111111111 $ 2068 | b1111111111111111 ) 2069 | b1 % 2070 | b1 * 2071 | #400 2072 | 0# 2073 | #450 2074 | 1# 2075 | #460 2076 | 0" 2077 | 1c" 2078 | 1t" 2079 | 1'# 2080 | 18# 2081 | 1I# 2082 | 1Z# 2083 | 1k# 2084 | 1{# 2085 | 1\ 2086 | 1m 2087 | 1~ 2088 | 11" 2089 | 1B" 2090 | 0Q" 2091 | 1_" 2092 | 1p" 2093 | 1## 2094 | 14# 2095 | 1E# 2096 | 1V# 2097 | 1g# 2098 | 1x# 2099 | 1W 2100 | 1i 2101 | 1z 2102 | 1-" 2103 | 1>" 2104 | 0P" 2105 | 0T" 2106 | 0G 2107 | 0`" 2108 | 0q" 2109 | 0$# 2110 | 05# 2111 | 0F# 2112 | 0W# 2113 | 0h# 2114 | 0X 2115 | 0Y 2116 | 0j 2117 | 0{ 2118 | 0." 2119 | 0?" 2120 | 0I 2121 | 0b" 2122 | 0s" 2123 | 0&# 2124 | 07# 2125 | 0H# 2126 | 0Y# 2127 | 0j# 2128 | 0z# 2129 | 0[ 2130 | 0l 2131 | 0} 2132 | 00" 2133 | 0A" 2134 | 0O" 2135 | 0L 2136 | 0e" 2137 | 0v" 2138 | 0)# 2139 | 0:# 2140 | 0K# 2141 | 0\# 2142 | 0m# 2143 | 0}# 2144 | 0^ 2145 | 0o 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| 1Q" 2236 | 1R" 2237 | 1T" 2238 | 1P" 2239 | 0O" 2240 | 1?" 2241 | 1A" 2242 | 1D" 2243 | 1." 2244 | 10" 2245 | 13" 2246 | 1{ 2247 | 1} 2248 | 1"" 2249 | 1j 2250 | 1l 2251 | 1o 2252 | 1Y 2253 | 1[ 2254 | 1^ 2255 | 1X 2256 | 1z# 2257 | 1}# 2258 | 1h# 2259 | 1j# 2260 | 1m# 2261 | 1W# 2262 | 1Y# 2263 | 1\# 2264 | 1F# 2265 | 1H# 2266 | 1K# 2267 | 15# 2268 | 17# 2269 | 1:# 2270 | 1$# 2271 | 1&# 2272 | 1)# 2273 | 1q" 2274 | 1s" 2275 | 1v" 2276 | 1`" 2277 | 1b" 2278 | 1e" 2279 | 1G 2280 | 0F 2281 | 1I 2282 | 0_" 2283 | 0p" 2284 | 0## 2285 | 04# 2286 | 0E# 2287 | 0V# 2288 | 0g# 2289 | 0x# 2290 | 0W 2291 | 0i 2292 | 0z 2293 | 0-" 2294 | 0>" 2295 | b0 ! 2296 | b0 , 2297 | 04 2298 | 1J 2299 | 1L 2300 | 1c" 2301 | 1t" 2302 | 1'# 2303 | 18# 2304 | 1I# 2305 | 1Z# 2306 | 1k# 2307 | 1{# 2308 | 1\ 2309 | 1m 2310 | 1~ 2311 | 11" 2312 | 1B" 2313 | 1; 2314 | 01 2315 | 19 2316 | 0< 2317 | 03 2318 | 02 2319 | 1H 2320 | 0C 2321 | 1a" 2322 | 0\" 2323 | 1r" 2324 | 0m" 2325 | 1%# 2326 | 0~" 2327 | 16# 2328 | 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2595 | 1T" 2596 | 1" 2597 | 1A" 2598 | 1P" 2599 | 1O" 2600 | 1S" 2601 | 0B" 2602 | 1E" 2603 | 1D" 2604 | 1?" 2605 | 10" 2606 | 1>" 2607 | 1C" 2608 | 01" 2609 | 14" 2610 | 13" 2611 | 1." 2612 | 1} 2613 | 1/" 2614 | 1-" 2615 | 12" 2616 | 0~ 2617 | 1#" 2618 | 1"" 2619 | 1{ 2620 | 1l 2621 | 1z 2622 | 1!" 2623 | 0m 2624 | 1p 2625 | 1o 2626 | 1j 2627 | 1k 2628 | 1i 2629 | 1n 2630 | 1Y 2631 | 1[ 2632 | 0\ 2633 | 1_ 2634 | 1z# 2635 | 1] 2636 | 1^ 2637 | 1W 2638 | 0{# 2639 | 1~# 2640 | 1}# 2641 | 1X 2642 | 1j# 2643 | 1y# 2644 | 1x# 2645 | 1|# 2646 | 0k# 2647 | 1n# 2648 | 1m# 2649 | 1h# 2650 | 1Y# 2651 | 1g# 2652 | 1l# 2653 | 0Z# 2654 | 1]# 2655 | 1\# 2656 | 1W# 2657 | 1H# 2658 | 1V# 2659 | 1[# 2660 | 0I# 2661 | 1L# 2662 | 1K# 2663 | 1F# 2664 | 17# 2665 | 1G# 2666 | 1E# 2667 | 1J# 2668 | 08# 2669 | 1;# 2670 | 1:# 2671 | 15# 2672 | 1&# 2673 | 14# 2674 | 19# 2675 | 0'# 2676 | 1*# 2677 | 1)# 2678 | 1$# 2679 | 1s" 2680 | 1%# 2681 | 1## 2682 | 1(# 2683 | 0t" 2684 | 1w" 2685 | 1v" 2686 | 1q" 2687 | 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| 0S 2958 | 0e 2959 | 0v 2960 | 0)" 2961 | 0:" 2962 | 0[" 2963 | 0l" 2964 | 0}" 2965 | 00# 2966 | 0A# 2967 | 0R# 2968 | 0c# 2969 | 0t# 2970 | 09 2971 | 0: 2972 | 03 2973 | 02 2974 | 0H 2975 | 0C 2976 | 0a" 2977 | 0\" 2978 | 0r" 2979 | 0m" 2980 | 0%# 2981 | 0~" 2982 | 06# 2983 | 01# 2984 | 0G# 2985 | 0B# 2986 | 0X# 2987 | 0S# 2988 | 0i# 2989 | 0d# 2990 | 0y# 2991 | 0u# 2992 | 0Z 2993 | 0T 2994 | 0k 2995 | 0f 2996 | 0| 2997 | 0w 2998 | 0/" 2999 | 0*" 3000 | 0@" 3001 | 0;" 3002 | 0- 3003 | 0= 3004 | 1> 3005 | 0N 3006 | 1O 3007 | 0` 3008 | 1a 3009 | 0q 3010 | 1r 3011 | 0$" 3012 | 1%" 3013 | 05" 3014 | 16" 3015 | 0F" 3016 | 1G" 3017 | 0V" 3018 | 1W" 3019 | 0g" 3020 | 1h" 3021 | 0x" 3022 | 1y" 3023 | 0+# 3024 | 1,# 3025 | 0<# 3026 | 1=# 3027 | 0M# 3028 | 1N# 3029 | 0^# 3030 | 1_# 3031 | 0o# 3032 | 1p# 3033 | 0!$ 3034 | 1"$ 3035 | 0. 3036 | 0/ 3037 | 0@ 3038 | 0Y" 3039 | 0j" 3040 | 0{" 3041 | 0.# 3042 | 0?# 3043 | 0P# 3044 | 0a# 3045 | 0r# 3046 | 0Q 3047 | 0c 3048 | 0t 3049 | 0'" 3050 | 08" 3051 | b1001 ( 3052 | b10 & 3053 | b10 + 3054 | b10 0 3055 | b10 A 3056 | b10 R 3057 | b10 d 3058 | b10 u 3059 | b10 (" 3060 | b10 9" 3061 | b10 J" 3062 | b10 Z" 3063 | b10 k" 3064 | b10 |" 3065 | b10 /# 3066 | b10 @# 3067 | b10 Q# 3068 | b10 b# 3069 | b10 s# 3070 | b0 $ 3071 | b0 ) 3072 | b0 % 3073 | b0 * 3074 | #1000 3075 | 0# 3076 | #1050 3077 | 1# 3078 | #1060 3079 | 1E 3080 | 1o" 3081 | 13# 3082 | 1U# 3083 | 1f# 3084 | 1V 3085 | 1y 3086 | 1=" 3087 | 14 3088 | 1^" 3089 | 1"# 3090 | 1D# 3091 | 1w# 3092 | 1h 3093 | 1," 3094 | b1111111111111111 ! 3095 | b1111111111111111 , 3096 | 1N" 3097 | 1F 3098 | 1p" 3099 | 14# 3100 | 1V# 3101 | 1g# 3102 | 1W 3103 | 1z 3104 | 1>" 3105 | 15 3106 | 1_" 3107 | 1## 3108 | 1E# 3109 | 1x# 3110 | 1i 3111 | 1-" 3112 | 1O" 3113 | 1J 3114 | 1t" 3115 | 18# 3116 | 1Z# 3117 | 1k# 3118 | 1\ 3119 | 1~ 3120 | 1B" 3121 | 19 3122 | 12 3123 | 1c" 3124 | 1\" 3125 | 1'# 3126 | 1~" 3127 | 1I# 3128 | 1B# 3129 | 1{# 3130 | 1u# 3131 | 1m 3132 | 1f 3133 | 11" 3134 | 1*" 3135 | 1R" 3136 | 1L" 3137 | 1H 3138 | 1C 3139 | 1r" 3140 | 1m" 3141 | 16# 3142 | 11# 3143 | 1X# 3144 | 1S# 3145 | 1i# 3146 | 1d# 3147 | 1Z 3148 | 1T 3149 | 1| 3150 | 1w 3151 | 1@" 3152 | 1;" 3153 | 1. 3154 | 1X" 3155 | 1z" 3156 | 1># 3157 | 1q# 3158 | 1b 3159 | 1&" 3160 | 1H" 3161 | 1@ 3162 | 1j" 3163 | 1.# 3164 | 1P# 3165 | 1a# 3166 | 1Q 3167 | 1t 3168 | 18" 3169 | b1010 ( 3170 | b1010101001010101 $ 3171 | b1010101001010101 ) 3172 | b101010110101010 % 3173 | b101010110101010 * 3174 | #1100 3175 | 0# 3176 | #1150 3177 | 1# 3178 | #1160 3179 | 1Q" 3180 | 0R" 3181 | 1U" 3182 | 1T" 3183 | 1N" 3184 | 1" 3185 | 1A" 3186 | 1P" 3187 | 1O" 3188 | 1S" 3189 | 0B" 3190 | 1E" 3191 | 1D" 3192 | 1=" 3193 | 1?" 3194 | 10" 3195 | 1>" 3196 | 1C" 3197 | 01" 3198 | 14" 3199 | 13" 3200 | 1," 3201 | 1." 3202 | 1} 3203 | 1/" 3204 | 1-" 3205 | 12" 3206 | 0~ 3207 | 1#" 3208 | 1"" 3209 | 1y 3210 | 1{ 3211 | 1l 3212 | 1z 3213 | 1!" 3214 | 0m 3215 | 1p 3216 | 1o 3217 | 1h 3218 | 1j 3219 | 1k 3220 | 1i 3221 | 1n 3222 | 1Y 3223 | 1[ 3224 | 1V 3225 | 0\ 3226 | 1_ 3227 | 1z# 3228 | 1] 3229 | 1^ 3230 | 1W 3231 | 0{# 3232 | 1~# 3233 | 1}# 3234 | 1w# 3235 | 1X 3236 | 1j# 3237 | 1y# 3238 | 1x# 3239 | 1|# 3240 | 0k# 3241 | 1n# 3242 | 1m# 3243 | 1f# 3244 | 1h# 3245 | 1Y# 3246 | 1g# 3247 | 1l# 3248 | 0Z# 3249 | 1]# 3250 | 1\# 3251 | 1U# 3252 | 1W# 3253 | 1H# 3254 | 1V# 3255 | 1[# 3256 | 0I# 3257 | 1L# 3258 | 1K# 3259 | 1D# 3260 | 1F# 3261 | 17# 3262 | 1G# 3263 | 1E# 3264 | 1J# 3265 | 08# 3266 | 1;# 3267 | 1:# 3268 | 13# 3269 | 15# 3270 | 1&# 3271 | 14# 3272 | 19# 3273 | 0'# 3274 | 1*# 3275 | 1)# 3276 | 1"# 3277 | 1$# 3278 | 1s" 3279 | 1%# 3280 | 1## 3281 | 1(# 3282 | 0t" 3283 | 1w" 3284 | 1v" 3285 | 1o" 3286 | 1q" 3287 | 1b" 3288 | 1p" 3289 | 1u" 3290 | 0c" 3291 | 1f" 3292 | 1e" 3293 | 1^" 3294 | 1`" 3295 | 1I 3296 | 1a" 3297 | 1_" 3298 | 1d" 3299 | 0J 3300 | 1M 3301 | 1L 3302 | 1E 3303 | 1G 3304 | 1F 3305 | 1K 3306 | b1111111111111110 ! 3307 | b1111111111111110 , 3308 | 04 3309 | 16 3310 | 05 3311 | 18 3312 | 09 3313 | 1< 3314 | 11 3315 | 17 3316 | 13 3317 | 1H 3318 | 1r" 3319 | 16# 3320 | 1X# 3321 | 1i# 3322 | 1Z 3323 | 1| 3324 | 1@" 3325 | 1? 3326 | 1i" 3327 | 1-# 3328 | 1O# 3329 | 1`# 3330 | 1P 3331 | 1s 3332 | 17" 3333 | 1/ 3334 | 0@ 3335 | 0j" 3336 | 0.# 3337 | 0P# 3338 | 0a# 3339 | 0Q 3340 | 0t 3341 | 08" 3342 | b1011 ( 3343 | b1111111111111111 $ 3344 | b1111111111111111 ) 3345 | b1 % 3346 | b1 * 3347 | #1200 3348 | 0# 3349 | #1250 3350 | 1# 3351 | #1260 3352 | 0" 3353 | 1c" 3354 | 1^" 3355 | 1t" 3356 | 1o" 3357 | 1'# 3358 | 1"# 3359 | 18# 3360 | 13# 3361 | 1I# 3362 | 1D# 3363 | 1Z# 3364 | 1U# 3365 | 1k# 3366 | 1f# 3367 | 1{# 3368 | 1w# 3369 | 1V 3370 | 1\ 3371 | 1m 3372 | 1h 3373 | 1~ 3374 | 1y 3375 | 11" 3376 | 1," 3377 | 1B" 3378 | 1=" 3379 | 0Q" 3380 | 1_" 3381 | 1p" 3382 | 1## 3383 | 14# 3384 | 1E# 3385 | 1V# 3386 | 1g# 3387 | 1x# 3388 | 1W 3389 | 1i 3390 | 1z 3391 | 1-" 3392 | 1>" 3393 | 0P" 3394 | 0T" 3395 | 0G 3396 | 0`" 3397 | 0q" 3398 | 0$# 3399 | 05# 3400 | 0F# 3401 | 0W# 3402 | 0h# 3403 | 0X 3404 | 0Y 3405 | 0j 3406 | 0{ 3407 | 0." 3408 | 0?" 3409 | b111111111111110 ! 3410 | b111111111111110 , 3411 | 0N" 3412 | 0I 3413 | 0b" 3414 | 0s" 3415 | 0&# 3416 | 07# 3417 | 0H# 3418 | 0Y# 3419 | 0j# 3420 | 0z# 3421 | 0[ 3422 | 0l 3423 | 0} 3424 | 00" 3425 | 0A" 3426 | 0O" 3427 | 0L 3428 | 0e" 3429 | 0v" 3430 | 0)# 3431 | 0:# 3432 | 0K# 3433 | 0\# 3434 | 0m# 3435 | 0}# 3436 | 0^ 3437 | 0o 3438 | 0"" 3439 | 03" 3440 | 0D" 3441 | 0M 3442 | 0K 3443 | 0f" 3444 | 0d" 3445 | 0w" 3446 | 0u" 3447 | 0*# 3448 | 0(# 3449 | 0;# 3450 | 09# 3451 | 0L# 3452 | 0J# 3453 | 0]# 3454 | 0[# 3455 | 0n# 3456 | 0l# 3457 | 0~# 3458 | 0|# 3459 | 0_ 3460 | 0] 3461 | 0p 3462 | 0n 3463 | 0#" 3464 | 0!" 3465 | 04" 3466 | 02" 3467 | 0E" 3468 | 0C" 3469 | 0R" 3470 | 0U" 3471 | 0S" 3472 | 0L" 3473 | 0H 3474 | 1a" 3475 | 1r" 3476 | 1%# 3477 | 16# 3478 | 1G# 3479 | 1X# 3480 | 1i# 3481 | 1y# 3482 | 1Z 3483 | 1k 3484 | 1| 3485 | 1/" 3486 | 1@" 3487 | 0? 3488 | 0X" 3489 | 0i" 3490 | 0z" 3491 | 0-# 3492 | 0># 3493 | 0O# 3494 | 0`# 3495 | 0q# 3496 | 0P 3497 | 0b 3498 | 0s 3499 | 0&" 3500 | 07" 3501 | 0H" 3502 | 1@ 3503 | 1Y" 3504 | 1j" 3505 | 1{" 3506 | 1.# 3507 | 1?# 3508 | 1P# 3509 | 1a# 3510 | 1r# 3511 | 1Q 3512 | 1c 3513 | 1t 3514 | 1'" 3515 | 18" 3516 | b1100 ( 3517 | b1 $ 3518 | b1 ) 3519 | b111111111111111 % 3520 | b111111111111111 * 3521 | #1300 3522 | 0# 3523 | #1350 3524 | 1# 3525 | #1360 3526 | 1" 3527 | 1Q" 3528 | 1R" 3529 | 1T" 3530 | 0N" 3531 | 1P" 3532 | 0O" 3533 | 1?" 3534 | 1A" 3535 | 1D" 3536 | 1." 3537 | 10" 3538 | 13" 3539 | 1{ 3540 | 1} 3541 | 1"" 3542 | 1j 3543 | 1l 3544 | 1o 3545 | 1Y 3546 | 1[ 3547 | 1^ 3548 | 1X 3549 | 1z# 3550 | 1}# 3551 | 1h# 3552 | 1j# 3553 | 1m# 3554 | 1W# 3555 | 1Y# 3556 | 1\# 3557 | 1F# 3558 | 1H# 3559 | 1K# 3560 | 15# 3561 | 17# 3562 | 1:# 3563 | 1$# 3564 | 1&# 3565 | 1)# 3566 | 1q" 3567 | 1s" 3568 | 1v" 3569 | 1`" 3570 | 1b" 3571 | 1e" 3572 | 0E 3573 | 1G 3574 | 0^" 3575 | 0o" 3576 | 0"# 3577 | 03# 3578 | 0D# 3579 | 0U# 3580 | 0f# 3581 | 0w# 3582 | 0V 3583 | 0h 3584 | 0y 3585 | 0," 3586 | b0 ! 3587 | b0 , 3588 | 0=" 3589 | 0F 3590 | 1I 3591 | 0_" 3592 | 0p" 3593 | 0## 3594 | 04# 3595 | 0E# 3596 | 0V# 3597 | 0g# 3598 | 0x# 3599 | 0W 3600 | 0i 3601 | 0z 3602 | 0-" 3603 | 0>" 3604 | 1J 3605 | 1L 3606 | 1c" 3607 | 1t" 3608 | 1'# 3609 | 18# 3610 | 1I# 3611 | 1Z# 3612 | 1k# 3613 | 1{# 3614 | 1\ 3615 | 1m 3616 | 1~ 3617 | 11" 3618 | 1B" 3619 | 1; 3620 | 01 3621 | 19 3622 | 0< 3623 | 03 3624 | 02 3625 | 1H 3626 | 0C 3627 | 1a" 3628 | 0\" 3629 | 1r" 3630 | 0m" 3631 | 1%# 3632 | 0~" 3633 | 16# 3634 | 01# 3635 | 1G# 3636 | 0B# 3637 | 1X# 3638 | 0S# 3639 | 1i# 3640 | 0d# 3641 | 1y# 3642 | 0u# 3643 | 1Z 3644 | 0T 3645 | 1k 3646 | 0f 3647 | 1| 3648 | 0w 3649 | 1/" 3650 | 0*" 3651 | 1@" 3652 | 0;" 3653 | 1- 3654 | 1= 3655 | 1N 3656 | 1` 3657 | 1q 3658 | 1$" 3659 | 15" 3660 | 1F" 3661 | 1V" 3662 | 1g" 3663 | 1x" 3664 | 1+# 3665 | 1<# 3666 | 1M# 3667 | 1^# 3668 | 1o# 3669 | 1!$ 3670 | 0. 3671 | 0/ 3672 | 0@ 3673 | 0Y" 3674 | 0j" 3675 | 0{" 3676 | 0.# 3677 | 0?# 3678 | 0P# 3679 | 0a# 3680 | 0r# 3681 | 0Q 3682 | 0c 3683 | 0t 3684 | 0'" 3685 | 08" 3686 | b1101 ( 3687 | b11 & 3688 | b11 + 3689 | b11 0 3690 | b11 A 3691 | b11 R 3692 | b11 d 3693 | b11 u 3694 | b11 (" 3695 | b11 9" 3696 | b11 J" 3697 | b11 Z" 3698 | b11 k" 3699 | b11 |" 3700 | b11 /# 3701 | b11 @# 3702 | b11 Q# 3703 | b11 b# 3704 | b11 s# 3705 | b0 $ 3706 | b0 ) 3707 | b0 % 3708 | b0 * 3709 | #1400 3710 | 0# 3711 | #1450 3712 | 1# 3713 | #1460 3714 | 0`" 3715 | 0$# 3716 | 0F# 3717 | 0X 3718 | 0j 3719 | 0." 3720 | 0" 3721 | 0b" 3722 | 0&# 3723 | 0H# 3724 | 0z# 3725 | 0l 3726 | 00" 3727 | 0Q" 3728 | 0a" 3729 | 0e" 3730 | 0%# 3731 | 0)# 3732 | 0G# 3733 | 0K# 3734 | 0y# 3735 | 0}# 3736 | 0k 3737 | 0o 3738 | 0/" 3739 | 03" 3740 | 0P" 3741 | 0T" 3742 | 1E 3743 | 0G 3744 | 1o" 3745 | 0q" 3746 | 13# 3747 | 05# 3748 | 1U# 3749 | 0W# 3750 | 1f# 3751 | 0h# 3752 | 1V 3753 | 0Y 3754 | 1y 3755 | 0{ 3756 | 1=" 3757 | 0?" 3758 | 14 3759 | 1^" 3760 | 1"# 3761 | 1D# 3762 | 1w# 3763 | 1h 3764 | 1," 3765 | b1111111111111111 ! 3766 | b1111111111111111 , 3767 | 1N" 3768 | 1F 3769 | 0I 3770 | 1p" 3771 | 0s" 3772 | 14# 3773 | 07# 3774 | 1V# 3775 | 0Y# 3776 | 1g# 3777 | 0j# 3778 | 1W 3779 | 0[ 3780 | 1z 3781 | 0} 3782 | 1>" 3783 | 0A" 3784 | 15 3785 | 11 3786 | 1_" 3787 | 1[" 3788 | 1## 3789 | 1}" 3790 | 1E# 3791 | 1A# 3792 | 1x# 3793 | 1t# 3794 | 1i 3795 | 1e 3796 | 1-" 3797 | 1)" 3798 | 1O" 3799 | 1K" 3800 | 0J 3801 | 0L 3802 | 1B 3803 | 1t" 3804 | 0v" 3805 | 1l" 3806 | 18# 3807 | 0:# 3808 | 10# 3809 | 1Z# 3810 | 0\# 3811 | 1R# 3812 | 1k# 3813 | 0m# 3814 | 1c# 3815 | 1\ 3816 | 0^ 3817 | 1S 3818 | 1~ 3819 | 0"" 3820 | 1v 3821 | 1B" 3822 | 0D" 3823 | 1:" 3824 | 09 3825 | 1< 3826 | 1: 3827 | 12 3828 | 1c" 3829 | 0f" 3830 | 0d" 3831 | 1\" 3832 | 1'# 3833 | 0*# 3834 | 0(# 3835 | 1~" 3836 | 1I# 3837 | 0L# 3838 | 0J# 3839 | 1B# 3840 | 1{# 3841 | 0~# 3842 | 0|# 3843 | 1u# 3844 | 1m 3845 | 0p 3846 | 0n 3847 | 1f 3848 | 11" 3849 | 04" 3850 | 02" 3851 | 1*" 3852 | 1R" 3853 | 0U" 3854 | 0S" 3855 | 1L" 3856 | 0H 3857 | 1C 3858 | 1r" 3859 | 1m" 3860 | 16# 3861 | 11# 3862 | 1X# 3863 | 1S# 3864 | 1i# 3865 | 1d# 3866 | 1Z 3867 | 1T 3868 | 1| 3869 | 1w 3870 | 1@" 3871 | 1;" 3872 | 1. 3873 | 1X" 3874 | 1z" 3875 | 1># 3876 | 1q# 3877 | 1b 3878 | 1&" 3879 | 1H" 3880 | 1@ 3881 | 1j" 3882 | 1.# 3883 | 1P# 3884 | 1a# 3885 | 1Q 3886 | 1t 3887 | 18" 3888 | b1110 ( 3889 | b1010101001010101 $ 3890 | b1010101001010101 ) 3891 | b101010110101010 % 3892 | b101010110101010 * 3893 | #1500 3894 | 0# 3895 | #1550 3896 | 1# 3897 | #1560 3898 | 1Q" 3899 | 0R" 3900 | 1U" 3901 | 1T" 3902 | 1N" 3903 | 1" 3904 | 1A" 3905 | 1P" 3906 | 1O" 3907 | 1S" 3908 | 0B" 3909 | 1E" 3910 | 1D" 3911 | 1=" 3912 | 1?" 3913 | 10" 3914 | 1>" 3915 | 1C" 3916 | 01" 3917 | 14" 3918 | 13" 3919 | 1," 3920 | 1." 3921 | 1} 3922 | 1/" 3923 | 1-" 3924 | 12" 3925 | 0~ 3926 | 1#" 3927 | 1"" 3928 | 1y 3929 | 1{ 3930 | 1l 3931 | 1z 3932 | 1!" 3933 | 0m 3934 | 1p 3935 | 1o 3936 | 1h 3937 | 1j 3938 | 1k 3939 | 1i 3940 | 1n 3941 | 1Y 3942 | 1[ 3943 | 1V 3944 | 0\ 3945 | 1_ 3946 | 1z# 3947 | 1] 3948 | 1^ 3949 | 1W 3950 | 0{# 3951 | 1~# 3952 | 1}# 3953 | 1w# 3954 | 1X 3955 | 1j# 3956 | 1y# 3957 | 1x# 3958 | 1|# 3959 | 0k# 3960 | 1n# 3961 | 1m# 3962 | 1f# 3963 | 1h# 3964 | 1Y# 3965 | 1g# 3966 | 1l# 3967 | 0Z# 3968 | 1]# 3969 | 1\# 3970 | 1U# 3971 | 1W# 3972 | 1H# 3973 | 1V# 3974 | 1[# 3975 | 0I# 3976 | 1L# 3977 | 1K# 3978 | 1D# 3979 | 1F# 3980 | 17# 3981 | 1G# 3982 | 1E# 3983 | 1J# 3984 | 08# 3985 | 1;# 3986 | 1:# 3987 | 13# 3988 | 15# 3989 | 1&# 3990 | 14# 3991 | 19# 3992 | 0'# 3993 | 1*# 3994 | 1)# 3995 | 1"# 3996 | 1$# 3997 | 1s" 3998 | 1%# 3999 | 1## 4000 | 1(# 4001 | 0t" 4002 | 1w" 4003 | 1v" 4004 | 1o" 4005 | 1q" 4006 | 1b" 4007 | 1p" 4008 | 1u" 4009 | 0c" 4010 | 1f" 4011 | 1e" 4012 | 1^" 4013 | 1`" 4014 | b1111111111111110 ! 4015 | b1111111111111110 , 4016 | 04 4017 | 1a" 4018 | 1_" 4019 | 1d" 4020 | 05 4021 | 08 4022 | 1I 4023 | 1G 4024 | 19 4025 | 0< 4026 | 0; 4027 | 1L 4028 | 1M 4029 | 1K 4030 | 07 4031 | 13 4032 | 1H 4033 | 1r" 4034 | 16# 4035 | 1X# 4036 | 1i# 4037 | 1Z 4038 | 1| 4039 | 1@" 4040 | 1? 4041 | 1i" 4042 | 1-# 4043 | 1O# 4044 | 1`# 4045 | 1P 4046 | 1s 4047 | 17" 4048 | 1/ 4049 | 0@ 4050 | 0j" 4051 | 0.# 4052 | 0P# 4053 | 0a# 4054 | 0Q 4055 | 0t 4056 | 08" 4057 | b1111 ( 4058 | b1111111111111111 $ 4059 | b1111111111111111 ) 4060 | b1 % 4061 | b1 * 4062 | #1600 4063 | 0# 4064 | #1650 4065 | 1# 4066 | #1660 4067 | 0" 4068 | 1c" 4069 | 1^" 4070 | 1t" 4071 | 1o" 4072 | 1'# 4073 | 1"# 4074 | 18# 4075 | 13# 4076 | 1I# 4077 | 1D# 4078 | 1Z# 4079 | 1U# 4080 | 1k# 4081 | 1f# 4082 | 1{# 4083 | 1w# 4084 | 1V 4085 | 1\ 4086 | 1m 4087 | 1h 4088 | 1~ 4089 | 1y 4090 | 11" 4091 | 1," 4092 | 1B" 4093 | 1=" 4094 | 0Q" 4095 | 1_" 4096 | 1p" 4097 | 1## 4098 | 14# 4099 | 1E# 4100 | 1V# 4101 | 1g# 4102 | 1x# 4103 | 1W 4104 | 1i 4105 | 1z 4106 | 1-" 4107 | 1>" 4108 | 0P" 4109 | 0T" 4110 | 0G 4111 | 0`" 4112 | 0q" 4113 | 0$# 4114 | 05# 4115 | 0F# 4116 | 0W# 4117 | 0h# 4118 | 0X 4119 | 0Y 4120 | 0j 4121 | 0{ 4122 | 0." 4123 | 0?" 4124 | b111111111111110 ! 4125 | b111111111111110 , 4126 | 0N" 4127 | 0I 4128 | 0b" 4129 | 0s" 4130 | 0&# 4131 | 07# 4132 | 0H# 4133 | 0Y# 4134 | 0j# 4135 | 0z# 4136 | 0[ 4137 | 0l 4138 | 0} 4139 | 00" 4140 | 0A" 4141 | 0O" 4142 | 0K" 4143 | 0L 4144 | 0e" 4145 | 0v" 4146 | 0)# 4147 | 0:# 4148 | 0K# 4149 | 0\# 4150 | 0m# 4151 | 0}# 4152 | 0^ 4153 | 0o 4154 | 0"" 4155 | 03" 4156 | 0D" 4157 | 0M 4158 | 0K 4159 | 0f" 4160 | 0d" 4161 | 0w" 4162 | 0u" 4163 | 0*# 4164 | 0(# 4165 | 0;# 4166 | 09# 4167 | 0L# 4168 | 0J# 4169 | 0]# 4170 | 0[# 4171 | 0n# 4172 | 0l# 4173 | 0~# 4174 | 0|# 4175 | 0_ 4176 | 0] 4177 | 0p 4178 | 0n 4179 | 0#" 4180 | 0!" 4181 | 04" 4182 | 02" 4183 | 0E" 4184 | 0C" 4185 | 0R" 4186 | 0U" 4187 | 0S" 4188 | 0L" 4189 | 0H 4190 | 1a" 4191 | 1r" 4192 | 1%# 4193 | 16# 4194 | 1G# 4195 | 1X# 4196 | 1i# 4197 | 1y# 4198 | 1Z 4199 | 1k 4200 | 1| 4201 | 1/" 4202 | 1@" 4203 | 0? 4204 | 0X" 4205 | 0i" 4206 | 0z" 4207 | 0-# 4208 | 0># 4209 | 0O# 4210 | 0`# 4211 | 0q# 4212 | 0P 4213 | 0b 4214 | 0s 4215 | 0&" 4216 | 07" 4217 | 0H" 4218 | 1@ 4219 | 1Y" 4220 | 1j" 4221 | 1{" 4222 | 1.# 4223 | 1?# 4224 | 1P# 4225 | 1a# 4226 | 1r# 4227 | 1Q 4228 | 1c 4229 | 1t 4230 | 1'" 4231 | 18" 4232 | b10000 ( 4233 | b1 $ 4234 | b1 ) 4235 | b111111111111111 % 4236 | b111111111111111 * 4237 | #1700 4238 | 0# 4239 | #1750 4240 | 1# 4241 | #1800 4242 | 0# 4243 | #1850 4244 | 1# 4245 | #1900 4246 | 0# 4247 | #1950 4248 | 1# 4249 | #2000 4250 | 0# 4251 | #2050 4252 | 1# 4253 | #2100 4254 | 0# 4255 | #2150 4256 | 1# 4257 | #2200 4258 | 0# 4259 | #2250 4260 | 1# 4261 | #2300 4262 | 0# 4263 | #2350 4264 | 1# 4265 | #2400 4266 | 0# 4267 | #2450 4268 | 1# 4269 | #2500 4270 | 0# 4271 | #2550 4272 | 1# 4273 | #2600 4274 | 0# 4275 | #2650 4276 | 1# 4277 | #2660 4278 | -------------------------------------------------------------------------------- /week-4/alu.v: -------------------------------------------------------------------------------- 1 | module fa (input wire i0, i1, cin, output wire sum, cout); 2 | wire t0, t1, t2; 3 | xor3 _i0 (i0, i1, cin, sum); 4 | and2 _i1 (i0, i1, t0); 5 | and2 _i2 (i1, cin, t1); 6 | and2 _i3 (cin, i0, t2); 7 | or3 _i4 (t0, t1, t2, cout); 8 | endmodule 9 | 10 | module addsub (input wire addsub, i0, i1, cin, output wire sumdiff, cout); 11 | wire t; 12 | fa _i0 (i0, t, cin, sumdiff, cout); 13 | xor2 _i1 (i1, addsub, t); 14 | endmodule 15 | 16 | module alu_slice (input wire [1:0] op, input wire i0, i1, cin, output wire o, cout); 17 | wire t_sumdiff, t_and, t_or, t_andor; 18 | addsub _i0 (op[0], i0, i1, cin, t_sumdiff, cout); 19 | and2 _i1 (i0, i1, t_and); 20 | or2 _i2 (i0, i1, t_or); 21 | mux2 _i3 (t_and, t_or, op[0], t_andor); 22 | mux2 _i4 (t_sumdiff, t_andor, op[1], o); 23 | endmodule 24 | 25 | module alu (input wire [1:0] op, input wire [15:0] i0, i1, 26 | output wire [15:0] o, output wire cout); 27 | wire [14:0] c; 28 | alu_slice _i0 (op, i0[0], i1[0], op[0] , o[0], c[0]); 29 | alu_slice _i1 (op, i0[1], i1[1], c[0], o[1], c[1]); 30 | alu_slice _i2 (op, i0[2], i1[2], c[1], o[2], c[2]); 31 | alu_slice _i3 (op, i0[3], i1[3], c[2], o[3], c[3]); 32 | alu_slice _i4 (op, i0[4], i1[4], c[3], o[4], c[4]); 33 | alu_slice _i5 (op, i0[5], i1[5], c[4], o[5], c[5]); 34 | alu_slice _i6 (op, i0[6], i1[6], c[5], o[6], c[6]); 35 | alu_slice _i7 (op, i0[7], i1[7], c[6], o[7], c[7]); 36 | alu_slice _i8 (op, i0[8], i1[8], c[7], o[8], c[8]); 37 | alu_slice _i9 (op, i0[9], i1[9], c[8], o[9], c[9]); 38 | alu_slice _i10 (op, i0[10], i1[10], c[9] , o[10], c[10]); 39 | alu_slice _i11 (op, i0[11], i1[11], c[10], o[11], c[11]); 40 | alu_slice _i12 (op, i0[12], i1[12], c[11], o[12], c[12]); 41 | alu_slice _i13 (op, i0[13], i1[13], c[12], o[13], c[13]); 42 | alu_slice _i14 (op, i0[14], i1[14], c[13], o[14], c[14]); 43 | alu_slice _i15 (op, i0[15], i1[15], c[14], o[15], cout); 44 | endmodule 45 | -------------------------------------------------------------------------------- /week-4/lib.v: -------------------------------------------------------------------------------- 1 | module invert (input wire i, output wire o); 2 | assign o = !i; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (t, o); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (t, o); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (t, o); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | module mux2 (input wire i0, i1, j, output wire o); 72 | assign o = (j==0)?i0:i1; 73 | endmodule 74 | 75 | module mux4 (input wire [0:3] i, input wire j1, j0, output wire o); 76 | wire t0, t1; 77 | mux2 mux2_0 (i[0], i[1], j1, t0); 78 | mux2 mux2_1 (i[2], i[3], j1, t1); 79 | mux2 mux2_2 (t0, t1, j0, o); 80 | endmodule 81 | 82 | module mux8 (input wire [0:7] i, input wire j2, j1, j0, output wire o); 83 | wire t0, t1; 84 | mux4 mux4_0 (i[0:3], j2, j1, t0); 85 | mux4 mux4_1 (i[4:7], j2, j1, t1); 86 | mux2 mux2_0 (t0, t1, j0, o); 87 | endmodule 88 | 89 | module demux2 (input wire i, j, output wire o0, o1); 90 | assign o0 = (j==0)?i:1'b0; 91 | assign o1 = (j==1)?i:1'b0; 92 | endmodule 93 | 94 | module demux4 (input wire i, j1, j0, output wire [0:3] o); 95 | wire t0, t1; 96 | demux2 demux2_0 (i, j1, t0, t1); 97 | demux2 demux2_1 (t0, j0, o[0], o[1]); 98 | demux2 demux2_2 (t1, j0, o[2], o[3]); 99 | endmodule 100 | 101 | module demux8 (input wire i, j2, j1, j0, output wire [0:7] o); 102 | wire t0, t1; 103 | demux2 demux2_0 (i, j2, t0, t1); 104 | demux4 demux4_0 (t0, j1, j0, o[0:3]); 105 | demux4 demux4_1 (t1, j1, j0, o[4:7]); 106 | endmodule 107 | 108 | module df (input wire clk, in, output wire out); 109 | reg df_out; 110 | always@(posedge clk) df_out <= in; 111 | assign out = df_out; 112 | endmodule 113 | 114 | module dfr (input wire clk, reset, in, output wire out); 115 | wire reset_, df_in; 116 | invert invert_0 (reset, reset_); 117 | and2 and2_0 (in, reset_, df_in); 118 | df df_0 (clk, df_in, out); 119 | endmodule 120 | 121 | module dfrl (input wire clk, reset, load, in, output wire out); 122 | wire _in; 123 | mux2 mux2_0(out, in, load, _in); 124 | dfr dfr_1(clk, reset, _in, out); 125 | endmodule 126 | -------------------------------------------------------------------------------- /week-4/reg_alu.v: -------------------------------------------------------------------------------- 1 | module reg16(input wire clk,reset,load,input wire [15:0]din,output wire [15:0]r); 2 | dfrl d0(clk,reset,load,din[0],r[0]); 3 | dfrl d1(clk,reset,load,din[1],r[1]); 4 | dfrl d2(clk,reset,load,din[2],r[2]); 5 | dfrl d3(clk,reset,load,din[3],r[3]); 6 | dfrl d4(clk,reset,load,din[4],r[4]); 7 | dfrl d5(clk,reset,load,din[5],r[5]); 8 | dfrl d6(clk,reset,load,din[6],r[6]); 9 | dfrl d7(clk,reset,load,din[7],r[7]); 10 | dfrl d8(clk,reset,load,din[8],r[8]); 11 | dfrl d9(clk,reset,load,din[9],r[9]); 12 | dfrl d10(clk,reset,load,din[10],r[10]); 13 | dfrl d11(clk,reset,load,din[11],r[11]); 14 | dfrl d12(clk,reset,load,din[12],r[12]); 15 | dfrl d13(clk,reset,load,din[13],r[13]); 16 | dfrl d14(clk,reset,load,din[14],r[14]); 17 | dfrl d15(clk,reset,load,din[15],r[15]); 18 | endmodule 19 | 20 | module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b); 21 | wire [0:7]load; 22 | wire [0:15]r0,r1,r2,r3,r4,r5,r6,r7; 23 | demux8 dmx(wr,wr_addr[2],wr_addr[1],wr_addr[0],load); 24 | reg16 reg0(clk,reset,load[0],d_in,r0); 25 | reg16 reg1(clk,reset,load[1],d_in,r1); 26 | reg16 reg2(clk,reset,load[2],d_in,r2); 27 | reg16 reg3(clk,reset,load[3],d_in,r3); 28 | reg16 reg4(clk,reset,load[4],d_in,r4); 29 | reg16 reg5(clk,reset,load[5],d_in,r5); 30 | reg16 reg6(clk,reset,load[6],d_in,r6); 31 | reg16 reg7(clk,reset,load[7],d_in,r7); 32 | mux128_16 mm0(r0,r1,r2,r3,r4,r5,r6,r7,rd_addr_a[0],rd_addr_a[1],rd_addr_a[2],d_out_a); 33 | mux128_16 mm1(r0,r1,r2,r3,r4,r5,r6,r7,rd_addr_b[0],rd_addr_b[1],rd_addr_b[2],d_out_b); 34 | endmodule 35 | 36 | module mux128_16(input wire [15:0]i0,i1,i2,i3,i4,i5,i6,i7,input wire s0,s1,s2,output wire [15:0]o); 37 | mux8 mx0({i0[0],i1[0],i2[0],i3[0],i4[0],i5[0],i6[0],i7[0]},s2,s1,s0,o[0]); 38 | mux8 mx1({i0[1],i1[1],i2[1],i3[1],i4[1],i5[1],i6[1],i7[1]},s2,s1,s0,o[1]); 39 | mux8 mx2({i0[2],i1[2],i2[2],i3[2],i4[2],i5[2],i6[2],i7[2]},s2,s1,s0,o[2]); 40 | mux8 mx3({i0[3],i1[3],i2[3],i3[3],i4[3],i5[3],i6[3],i7[3]},s2,s1,s0,o[3]); 41 | mux8 mx4({i0[4],i1[4],i2[4],i3[4],i4[4],i5[4],i6[4],i7[4]},s2,s1,s0,o[4]); 42 | mux8 mx5({i0[5],i1[5],i2[5],i3[5],i4[5],i5[5],i6[5],i7[5]},s2,s1,s0,o[5]); 43 | mux8 mx6({i0[6],i1[6],i2[6],i3[6],i4[6],i5[6],i6[6],i7[6]},s2,s1,s0,o[6]); 44 | mux8 mx7({i0[7],i1[7],i2[7],i3[7],i4[7],i5[7],i6[7],i7[7]},s2,s1,s0,o[7]); 45 | mux8 mx8({i0[8],i1[8],i2[8],i3[8],i4[8],i5[8],i6[8],i7[8]},s2,s1,s0,o[8]); 46 | mux8 mx9({i0[9],i1[9],i2[9],i3[9],i4[9],i5[9],i6[9],i7[9]},s2,s1,s0,o[9]); 47 | mux8 mx10({i0[10],i1[10],i2[10],i3[10],i4[10],i5[10],i6[10],i7[10]},s2,s1,s0,o[10]); 48 | mux8 mx11({i0[11],i1[11],i2[11],i3[11],i4[11],i5[11],i6[11],i7[11]},s2,s1,s0,o[11]); 49 | mux8 mx12({i0[12],i1[12],i2[12],i3[12],i4[12],i5[12],i6[12],i7[12]},s2,s1,s0,o[12]); 50 | mux8 mx13({i0[13],i1[13],i2[13],i3[13],i4[13],i5[13],i6[13],i7[13]},s2,s1,s0,o[13]); 51 | mux8 mx14({i0[14],i1[14],i2[14],i3[14],i4[14],i5[14],i6[14],i7[14]},s2,s1,s0,o[14]); 52 | mux8 mx15({i0[15],i1[15],i2[15],i3[15],i4[15],i5[15],i6[15],i7[15]},s2,s1,s0,o[15]); 53 | endmodule 54 | 55 | module mux2for16(input wire [15:0] din_regular, alu_out, input wire selector, output wire [15:0]din_final); 56 | mux2 m0(din_regular[0], alu_out[0], selector, din_final[0]); 57 | mux2 m1(din_regular[1], alu_out[1], selector, din_final[1]); 58 | mux2 m2(din_regular[2], alu_out[2], selector, din_final[2]); 59 | mux2 m3(din_regular[3], alu_out[3], selector, din_final[3]); 60 | mux2 m4(din_regular[4], alu_out[4], selector, din_final[4]); 61 | mux2 m5(din_regular[5], alu_out[5], selector, din_final[5]); 62 | mux2 m6(din_regular[6], alu_out[6], selector, din_final[6]); 63 | mux2 m7(din_regular[7], alu_out[7], selector, din_final[7]); 64 | mux2 m8(din_regular[8], alu_out[8], selector, din_final[8]); 65 | mux2 m9(din_regular[9], alu_out[9], selector, din_final[9]); 66 | mux2 m10(din_regular[10], alu_out[10], selector, din_final[10]); 67 | mux2 m11(din_regular[11], alu_out[11], selector, din_final[11]); 68 | mux2 m12(din_regular[12], alu_out[12], selector, din_final[12]); 69 | mux2 m13(din_regular[13], alu_out[13], selector, din_final[13]); 70 | mux2 m14(din_regular[14], alu_out[14], selector, din_final[14]); 71 | mux2 m15(din_regular[15], alu_out[15], selector, din_final[15]); 72 | endmodule 73 | 74 | 75 | module reg_alu (input wire clk, reset, sel, wr, input wire [1:0] op, input wire [2:0] rd_addr_a, 76 | rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b, output wire cout); 77 | wire [15:0] alu_out; 78 | wire [15:0] newdin; 79 | mux2for16 select(d_in, alu_out, sel, newdin); 80 | reg_file new_reg(clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, newdin, d_out_a, d_out_b); 81 | alu calc(op, d_out_a, d_out_b, alu_out, cout); 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /week-4/tb_reg_alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 100 ps 2 | `define TESTVECS 8 3 | 4 | module tb; 5 | reg clk, reset, wr, sel; 6 | reg [1:0] op; 7 | reg [2:0] rd_addr_a, rd_addr_b, wr_addr; reg [15:0] d_in; 8 | wire [15:0] d_out_a, d_out_b; 9 | reg [28:0] test_vecs [0:(`TESTVECS-1)]; 10 | integer i; 11 | initial begin $dumpfile("tb_reg_alu.vcd"); $dumpvars(0,tb); end 12 | initial begin reset = 1'b1; #12.5 reset = 1'b0; end 13 | initial clk = 1'b0; always #5 clk =~ clk; 14 | initial begin 15 | test_vecs[0][28] = 1'b0; test_vecs[0][27] = 1'b1; test_vecs[0][26:25] = 2'bxx; 16 | test_vecs[0][24:22] = 3'ox; test_vecs[0][21:19] = 3'ox; 17 | test_vecs[0][18:16] = 3'h3; test_vecs[0][15:0] = 16'hcdef; 18 | 19 | test_vecs[1][28] = 1'b0; test_vecs[1][27] = 1'b1; test_vecs[1][26:25] = 2'bxx; 20 | test_vecs[1][24:22] = 3'ox; test_vecs[1][21:19] = 3'ox; 21 | test_vecs[1][18:16] = 3'o7; test_vecs[1][15:0] = 16'h3210; 22 | 23 | test_vecs[2][28] = 1'b0; test_vecs[2][27] = 1'b1; test_vecs[2][26:25] = 2'bxx; 24 | test_vecs[2][24:22] = 3'o3; test_vecs[2][21:19] = 3'o7; 25 | test_vecs[2][18:16] = 3'o5; test_vecs[2][15:0] = 16'h4567; 26 | 27 | test_vecs[3][28] = 1'b0; test_vecs[3][27] = 1'b1; test_vecs[3][26:25] = 2'bxx; 28 | test_vecs[3][24:22] = 3'o1; test_vecs[3][21:19] = 3'o5; 29 | test_vecs[3][18:16] = 3'o1; test_vecs[3][15:0] = 16'hba98; 30 | 31 | test_vecs[4][28] = 1'b0; test_vecs[4][27] = 1'b0; test_vecs[4][26:25] = 2'bxx; 32 | test_vecs[4][24:22] = 3'o1; test_vecs[4][21:19] = 3'o5; 33 | test_vecs[4][18:16] = 3'o1; test_vecs[4][15:0] = 16'hxxxx; 34 | 35 | test_vecs[5][28] = 1'b1; test_vecs[5][27] = 1'b1; test_vecs[5][26:25] = 2'b00; 36 | test_vecs[5][24:22] = 3'o1; test_vecs[5][21:19] = 3'o5; 37 | test_vecs[5][18:16] = 3'o2; test_vecs[5][15:0] = 16'hxxxx; 38 | 39 | test_vecs[6][28] = 1'b1; test_vecs[6][27] = 1'b1; test_vecs[6][26:25] = 2'b01; 40 | test_vecs[6][24:22] = 3'o2; test_vecs[6][21:19] = 3'o7; 41 | test_vecs[6][18:16] = 3'o4; test_vecs[6][15:0] = 16'hxxxx; 42 | 43 | test_vecs[7][28] = 1'b1; test_vecs[7][27] = 1'b0; test_vecs[7][26:25] = 2'b01; 44 | test_vecs[7][24:22] = 3'o4; test_vecs[7][21:19] = 3'o4; 45 | test_vecs[7][18:16] = 3'ox; test_vecs[7][15:0] = 16'hxxxx; 46 | end 47 | initial {sel, wr, op, rd_addr_a, rd_addr_b, wr_addr, d_in} = 0; 48 | reg_alu reg_alu_0 (clk, reset, sel, wr, op, rd_addr_a, rd_addr_b, wr_addr, d_in, 49 | d_out_a, d_out_b, cout); 50 | initial begin 51 | #6 for(i=0;i<`TESTVECS;i=i+1) 52 | begin #10 {sel, wr, op, rd_addr_a, rd_addr_b, wr_addr, d_in}=test_vecs[i]; 53 | end 54 | #100 $finish; 55 | end 56 | 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /week-5/lib.v: -------------------------------------------------------------------------------- 1 | module invert (input wire i, output wire o); 2 | assign o = !i; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (t, o); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (t, o); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (t, o); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | module mux2 (input wire i0, i1, j, output wire o); 72 | assign o = (j==0)?i0:i1; 73 | endmodule 74 | 75 | module mux4 (input wire [0:3] i, input wire j1, j0, output wire o); 76 | wire t0, t1; 77 | mux2 mux2_0 (i[0], i[1], j1, t0); 78 | mux2 mux2_1 (i[2], i[3], j1, t1); 79 | mux2 mux2_2 (t0, t1, j0, o); 80 | endmodule 81 | 82 | module mux8 (input wire [0:7] i, input wire j2, j1, j0, output wire o); 83 | wire t0, t1; 84 | mux4 mux4_0 (i[0:3], j2, j1, t0); 85 | mux4 mux4_1 (i[4:7], j2, j1, t1); 86 | mux2 mux2_0 (t0, t1, j0, o); 87 | endmodule 88 | 89 | module demux2 (input wire i, j, output wire o0, o1); 90 | assign o0 = (j==0)?i:1'b0; 91 | assign o1 = (j==1)?i:1'b0; 92 | endmodule 93 | 94 | module demux4 (input wire i, j1, j0, output wire [0:3] o); 95 | wire t0, t1; 96 | demux2 demux2_0 (i, j1, t0, t1); 97 | demux2 demux2_1 (t0, j0, o[0], o[1]); 98 | demux2 demux2_2 (t1, j0, o[2], o[3]); 99 | endmodule 100 | 101 | module demux8 (input wire i, j2, j1, j0, output wire [0:7] o); 102 | wire t0, t1; 103 | demux2 demux2_0 (i, j2, t0, t1); 104 | demux4 demux4_0 (t0, j1, j0, o[0:3]); 105 | demux4 demux4_1 (t1, j1, j0, o[4:7]); 106 | endmodule 107 | 108 | module df (input wire clk, in, output wire out); 109 | reg df_out; 110 | always@(posedge clk) df_out <= in; 111 | assign out = df_out; 112 | endmodule 113 | 114 | module dfr (input wire clk, reset, in, output wire out); 115 | wire reset_, df_in; 116 | invert invert_0 (reset, reset_); 117 | and2 and2_0 (in, reset_, df_in); 118 | df df_0 (clk, df_in, out); 119 | endmodule 120 | 121 | module dfrl (input wire clk, reset, load, in, output wire out); 122 | wire _in; 123 | mux2 mux2_0(out, in, load, _in); 124 | dfr dfr_1(clk, reset, _in, out); 125 | endmodule 126 | -------------------------------------------------------------------------------- /week-5/pc.v: -------------------------------------------------------------------------------- 1 | module fadd(input wire a, b, cin, output wire sum, cout); 2 | wire t0,t1,t2,t3; 3 | xor2 x0(a,b,t0); 4 | xor2 x1(t0,cin,sum); 5 | and2 x2(a,b,t1); 6 | and2 x3(b,cin,t2); 7 | and2 x4(cin,a,t3); 8 | or3 x5(t1,t2,t3,cout); 9 | endmodule 10 | 11 | module addsub(input wire mode,i0,i1,cin,output wire sumdiff,cout); 12 | wire t; 13 | xor2 x0(i1,mode,t); 14 | fadd f(i0,t,cin,sumdiff,cout); 15 | endmodule 16 | 17 | module pc_slice0 (input wire clk,reset,offset,inc,sub,load, output wire pc,cout); 18 | wire t1,t2; 19 | or2 o0(offset,inc,t1); 20 | addsub o2(sub,pc,t1,sub,t2,cout); 21 | dfrl o3(clk,reset,load,t2,pc); 22 | endmodule 23 | 24 | module pc_slice1 (input wire clk,reset,offset,inc,sub,load,cin, output wire pc,cout); 25 | wire t1,t2,t3; 26 | invert i(inc,t1); 27 | and2 o0(offset,t1,t2); 28 | addsub o2(sub,pc,t2,cin,t3,cout); 29 | dfrl o3(clk,reset,load,t3,pc); 30 | endmodule 31 | 32 | module pc (input wire clk, reset, inc, add, sub, input wire [15:0] offset, output wire [15:0] pc); 33 | wire[15:0]cout; 34 | wire load; 35 | or3 o(inc,add,sub,load); 36 | pc_slice0 s0(clk,reset,offset[0],inc,sub,load,pc[0],cout[0]); 37 | pc_slice1 s1(clk,reset,offset[1],inc,sub,load,cout[0],pc[1],cout[1]); 38 | pc_slice1 s2(clk,reset,offset[2],inc,sub,load,cout[1],pc[2],cout[2]); 39 | pc_slice1 s3(clk,reset,offset[3],inc,sub,load,cout[2],pc[3],cout[3]); 40 | pc_slice1 s4(clk,reset,offset[4],inc,sub,load,cout[3],pc[4],cout[4]); 41 | pc_slice1 s5(clk,reset,offset[5],inc,sub,load,cout[4],pc[5],cout[5]); 42 | pc_slice1 s6(clk,reset,offset[6],inc,sub,load,cout[5],pc[6],cout[6]); 43 | pc_slice1 s7(clk,reset,offset[7],inc,sub,load,cout[6],pc[7],cout[7]); 44 | pc_slice1 s8(clk,reset,offset[8],inc,sub,load,cout[7],pc[8],cout[8]); 45 | pc_slice1 s9(clk,reset,offset[9],inc,sub,load,cout[8],pc[9],cout[9]); 46 | pc_slice1 s10(clk,reset,offset[10],inc,sub,load,cout[9],pc[10],cout[10]); 47 | pc_slice1 s11(clk,reset,offset[11],inc,sub,load,cout[10],pc[11],cout[11]); 48 | pc_slice1 s12(clk,reset,offset[12],inc,sub,load,cout[11],pc[12],cout[12]); 49 | pc_slice1 s13(clk,reset,offset[13],inc,sub,load,cout[12],pc[13],cout[13]); 50 | pc_slice1 s14(clk,reset,offset[14],inc,sub,load,cout[13],pc[14],cout[14]); 51 | pc_slice1 s15(clk,reset,offset[15],inc,sub,load,cout[14],pc[15],cout[15]); 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /week-5/tb_pc.v: -------------------------------------------------------------------------------- 1 | // Test bench for PC: 2 | 3 | `timescale 1 ns / 100 ps 4 | `define TESTVECS 5 5 | 6 | module tb; 7 | reg clk, reset, inc, add, sub; 8 | reg [15:0] offset; 9 | wire [15:0] pc; 10 | reg [18:0] test_vecs [0:(`TESTVECS-1)]; 11 | integer i; 12 | initial begin $dumpfile("tb_pc.vcd"); $dumpvars(0,tb); end 13 | initial begin reset = 1'b1; #12.5 reset = 1'b0; end 14 | initial clk = 1'b0; always #5 clk =~ clk; 15 | initial begin 16 | test_vecs[0][18] = 1'b1; test_vecs[0][17] = 1'b0; test_vecs[0][16] = 1'b0; 17 | test_vecs[0][15:0] = 15'hxx; 18 | test_vecs[1][18] = 1'b0; test_vecs[1][17] = 1'b1; test_vecs[1][16] = 1'b0; 19 | test_vecs[1][15:0] = 15'ha5; 20 | test_vecs[2][18] = 1'b0; test_vecs[2][17] = 1'b0; test_vecs[2][16] = 1'b0; 21 | test_vecs[2][15:0] = 15'hxx; 22 | test_vecs[3][18] = 1'b1; test_vecs[3][17] = 1'b0; test_vecs[3][16] = 1'b0; 23 | test_vecs[3][15:0] = 15'hxx; 24 | test_vecs[4][18] = 1'b0; test_vecs[4][17] = 1'b0; test_vecs[4][16] = 1'b1; 25 | test_vecs[4][15:0] = 15'h14; 26 | end 27 | initial {inc, add, sub, offset} = 0; 28 | pc pc_0 (clk, reset, inc, add, sub, offset, pc); 29 | initial begin 30 | #6 for(i=0;i<`TESTVECS;i=i+1) 31 | begin #10 {inc, add, sub, offset}=test_vecs[i]; end 32 | #100 $finish; 33 | end 34 | always@(reset or inc or add or sub ) 35 | $monitor("At time = %t, Reset= %b,inc=%b, add=%b,sub = %b,pc =%h ", $time,reset,inc,add,sub,pc); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /week-5/vvp_output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/week-5/vvp_output.png -------------------------------------------------------------------------------- /week-6/PC.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/week-6/PC.pdf -------------------------------------------------------------------------------- /week-6/lib.v: -------------------------------------------------------------------------------- 1 | module invert (input wire i, output wire o); 2 | assign o = !i; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (t, o); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (t, o); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (t, o); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | module mux2 (input wire i0, i1, j, output wire o); 72 | assign o = (j==0)?i0:i1; 73 | endmodule 74 | 75 | module mux4 (input wire [0:3] i, input wire j1, j0, output wire o); 76 | wire t0, t1; 77 | mux2 mux2_0 (i[0], i[1], j1, t0); 78 | mux2 mux2_1 (i[2], i[3], j1, t1); 79 | mux2 mux2_2 (t0, t1, j0, o); 80 | endmodule 81 | 82 | module mux8 (input wire [0:7] i, input wire j2, j1, j0, output wire o); 83 | wire t0, t1; 84 | mux4 mux4_0 (i[0:3], j2, j1, t0); 85 | mux4 mux4_1 (i[4:7], j2, j1, t1); 86 | mux2 mux2_0 (t0, t1, j0, o); 87 | endmodule 88 | 89 | module demux2 (input wire i, j, output wire o0, o1); 90 | assign o0 = (j==0)?i:1'b0; 91 | assign o1 = (j==1)?i:1'b0; 92 | endmodule 93 | 94 | module demux4 (input wire i, j1, j0, output wire [0:3] o); 95 | wire t0, t1; 96 | demux2 demux2_0 (i, j1, t0, t1); 97 | demux2 demux2_1 (t0, j0, o[0], o[1]); 98 | demux2 demux2_2 (t1, j0, o[2], o[3]); 99 | endmodule 100 | 101 | module demux8 (input wire i, j2, j1, j0, output wire [0:7] o); 102 | wire t0, t1; 103 | demux2 demux2_0 (i, j2, t0, t1); 104 | demux4 demux4_0 (t0, j1, j0, o[0:3]); 105 | demux4 demux4_1 (t1, j1, j0, o[4:7]); 106 | endmodule 107 | 108 | module df (input wire clk, in, output wire out); 109 | reg df_out; 110 | always@(posedge clk) df_out <= in; 111 | assign out = df_out; 112 | endmodule 113 | 114 | module dfr (input wire clk, reset, in, output wire out); 115 | wire reset_, df_in; 116 | invert invert_0 (reset, reset_); 117 | and2 and2_0 (in, reset_, df_in); 118 | df df_0 (clk, df_in, out); 119 | endmodule 120 | 121 | module dfrl (input wire clk, reset, load, in, output wire out); 122 | wire _in; 123 | mux2 mux2_0(out, in, load, _in); 124 | dfr dfr_1(clk, reset, _in, out); 125 | endmodule 126 | -------------------------------------------------------------------------------- /week-6/pc.v: -------------------------------------------------------------------------------- 1 | module fa (input wire i0, i1, cin, output wire sum, cout); 2 | wire t0, t1, t2; 3 | 4 | xor3 _i0 (i0, i1, cin, sum); 5 | 6 | and2 _i1 (i0, i1, t0); 7 | 8 | and2 _i2 (i1, cin, t1); 9 | 10 | and2 _i3 (cin, i0, t2); 11 | 12 | or3 _i4 (t0, t1, t2, cout); 13 | 14 | endmodule 15 | 16 | 17 | 18 | module addsub (input wire addsub, i0, i1, cin, output wire sumdiff, cout); 19 | 20 | wire t; 21 | 22 | fa _i0 (i0, t, cin, sumdiff, cout); 23 | 24 | xor2 _i1 (i1, addsub, t); 25 | 26 | endmodule 27 | 28 | 29 | 30 | module pc_slice (input wire clk, reset, cin, load, inc, sub, offset, 31 | output wire cout, pc); 32 | 33 | wire in, inc_; 34 | 35 | invert invert_0 (inc, inc_); 36 | 37 | and2 and2_0 (offset, inc_, in_as); 38 | 39 | addsub addsub_0 (sub, pc, in_as, sub, in, cout); 40 | 41 | dfrl dfrl_0 (clk, reset, load, in, pc); 42 | 43 | endmodule 44 | 45 | 46 | 47 | module pc_slice0 (input wire clk, reset, cin, load, inc, sub, offset, output wire cout, pc); 48 | 49 | wire in; 50 | 51 | or2 or2_0 (offset, inc, in_as); 52 | 53 | addsub addsub_0 (sub, pc, in_as, sub, in, cout); 54 | 55 | dfrl dfrl_0 (clk, reset, load, in, pc); 56 | 57 | endmodule 58 | 59 | 60 | 61 | module pc (input wire clk, reset, inc, add, sub, input wire [15:0] offset, output wire [15:0] pc); 62 | 63 | input wire load; 64 | input wire [15:0] c; 65 | 66 | or3 or3_0 (inc, add, sub, load); 67 | 68 | pc_slice0 pc_slice_0 (clk, reset, sub, load, inc, sub, offset[0], c[0], pc[0]); 69 | 70 | pc_slice pc_slice_1 (clk, reset, c[0], load, inc, sub, offset[1], c[1], pc[1]); 71 | 72 | pc_slice pc_slice_2 (clk, reset, c[1], load, inc, sub, offset[2], c[2], pc[2]); 73 | 74 | pc_slice pc_slice_3 (clk, reset, c[2], load, inc, sub, offset[3], c[3], pc[3]); 75 | 76 | pc_slice pc_slice_4 (clk, reset, c[3], load, inc, sub, offset[4], c[4], pc[4]); 77 | 78 | pc_slice pc_slice_5 (clk, reset, c[4], load, inc, sub, offset[5], c[5], pc[5]); 79 | 80 | pc_slice pc_slice_6 (clk, reset, c[5], load, inc, sub, offset[6], c[6], pc[6]); 81 | 82 | pc_slice pc_slice_7 (clk, reset, c[6], load, inc, sub, offset[7], c[7], pc[7]); 83 | 84 | pc_slice pc_slice_8 (clk, reset, c[7], load, inc, sub, offset[8], c[8], pc[8]); 85 | 86 | pc_slice pc_slice_9 (clk, reset, c[8], load, inc, sub, offset[9], c[9], pc[9]); 87 | 88 | pc_slice pc_slice_10 (clk, reset, c[9], load, inc, sub, offset[10], c[10], pc[10]); 89 | 90 | pc_slice pc_slice_11 (clk, reset, c[10], load, inc, sub, offset[11], c[11], pc[11]); 91 | 92 | pc_slice pc_slice_12 (clk, reset, c[11], load, inc, sub, offset[12], c[12], pc[12]); 93 | 94 | pc_slice pc_slice_13 (clk, reset, c[12], load, inc, sub, offset[13], c[13], pc[13]); 95 | 96 | pc_slice pc_slice_14 (clk, reset, c[13], load, inc, sub, offset[14], c[14], pc[14]); 97 | 98 | pc_slice pc_slice_15 (clk, reset, c[14], load, inc, sub, offset[15], c[15], pc[15]); 99 | 100 | endmodule 101 | -------------------------------------------------------------------------------- /week-6/tb_pc.v: -------------------------------------------------------------------------------- 1 | // Test bench for PC: 2 | 3 | `timescale 1 ns / 100 ps 4 | `define TESTVECS 5 5 | 6 | module tb; 7 | reg clk, reset, inc, add, sub; 8 | reg [15:0] offset; 9 | wire [15:0] pc; 10 | reg [18:0] test_vecs [0:(`TESTVECS-1)]; 11 | integer i; 12 | initial begin $dumpfile("tb_pc.vcd"); $dumpvars(0,tb); end 13 | initial begin reset = 1'b1; #12.5 reset = 1'b0; end 14 | initial clk = 1'b0; always #5 clk =~ clk; 15 | initial begin 16 | test_vecs[0][18] = 1'b1; test_vecs[0][17] = 1'b0; test_vecs[0][16] = 1'b0; 17 | test_vecs[0][15:0] = 15'hxx; 18 | test_vecs[1][18] = 1'b0; test_vecs[1][17] = 1'b1; test_vecs[1][16] = 1'b0; 19 | test_vecs[1][15:0] = 15'ha5; 20 | test_vecs[2][18] = 1'b0; test_vecs[2][17] = 1'b0; test_vecs[2][16] = 1'b0; 21 | test_vecs[2][15:0] = 15'hxx; 22 | test_vecs[3][18] = 1'b1; test_vecs[3][17] = 1'b0; test_vecs[3][16] = 1'b0; 23 | test_vecs[3][15:0] = 15'hxx; 24 | test_vecs[4][18] = 1'b0; test_vecs[4][17] = 1'b0; test_vecs[4][16] = 1'b1; 25 | test_vecs[4][15:0] = 15'h14; 26 | end 27 | initial {inc, add, sub, offset} = 0; 28 | pc pc_0 (clk, reset, inc, add, sub, offset, pc); 29 | initial begin 30 | #6 for(i=0;i<`TESTVECS;i=i+1) 31 | begin #10 {inc, add, sub, offset}=test_vecs[i]; end 32 | #100 $finish; 33 | end 34 | always@(reset or inc or add or sub ) 35 | $monitor("At time = %t, Reset= %b,inc=%b, add=%b,sub = %b,pc =%h ", $time,reset,inc,add,sub,pc); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /week-7/Diagram.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sufiiyan/verilog/03f0ff7aa78050c1bbb8ad55df7e7041ba056eeb/week-7/Diagram.docx -------------------------------------------------------------------------------- /week-7/alu.v: -------------------------------------------------------------------------------- 1 | module fa (input wire i0, i1, cin, output wire sum, cout); 2 | wire t0, t1, t2; 3 | xor3 _i0 (i0, i1, cin, sum); 4 | and2 _i1 (i0, i1, t0); 5 | and2 _i2 (i1, cin, t1); 6 | and2 _i3 (cin, i0, t2); 7 | or3 _i4 (t0, t1, t2, cout); 8 | endmodule 9 | 10 | module addsub (input wire addsub, i0, i1, cin, output wire sumdiff, cout); 11 | wire t; 12 | fa _i0 (i0, t, cin, sumdiff, cout); 13 | xor2 _i1 (i1, addsub, t); 14 | endmodule 15 | 16 | module alu_slice (input wire [1:0] op, input wire i0, i1, cin, output wire o, cout); 17 | wire t_sumdiff, t_and, t_or, t_andor; 18 | addsub _i0 (op[0], i0, i1, cin, t_sumdiff, cout); 19 | and2 _i1 (i0, i1, t_and); 20 | or2 _i2 (i0, i1, t_or); 21 | mux2 _i3 (t_and, t_or, op[0], t_andor); 22 | mux2 _i4 (t_sumdiff, t_andor, op[1], o); 23 | endmodule 24 | 25 | module alu (input wire [1:0] op, input wire [15:0] i0, i1, 26 | output wire [15:0] o, output wire cout); 27 | wire [14:0] c; 28 | alu_slice _i0 (op, i0[0], i1[0], op[0] , o[0], c[0]); 29 | alu_slice _i1 (op, i0[1], i1[1], c[0], o[1], c[1]); 30 | alu_slice _i2 (op, i0[2], i1[2], c[1], o[2], c[2]); 31 | alu_slice _i3 (op, i0[3], i1[3], c[2], o[3], c[3]); 32 | alu_slice _i4 (op, i0[4], i1[4], c[3], o[4], c[4]); 33 | alu_slice _i5 (op, i0[5], i1[5], c[4], o[5], c[5]); 34 | alu_slice _i6 (op, i0[6], i1[6], c[5], o[6], c[6]); 35 | alu_slice _i7 (op, i0[7], i1[7], c[6], o[7], c[7]); 36 | alu_slice _i8 (op, i0[8], i1[8], c[7], o[8], c[8]); 37 | alu_slice _i9 (op, i0[9], i1[9], c[8], o[9], c[9]); 38 | alu_slice _i10 (op, i0[10], i1[10], c[9] , o[10], c[10]); 39 | alu_slice _i11 (op, i0[11], i1[11], c[10], o[11], c[11]); 40 | alu_slice _i12 (op, i0[12], i1[12], c[11], o[12], c[12]); 41 | alu_slice _i13 (op, i0[13], i1[13], c[12], o[13], c[13]); 42 | alu_slice _i14 (op, i0[14], i1[14], c[13], o[14], c[14]); 43 | alu_slice _i15 (op, i0[15], i1[15], c[14], o[15], cout); 44 | endmodule 45 | -------------------------------------------------------------------------------- /week-7/lib.v: -------------------------------------------------------------------------------- 1 | module invert (input wire i, output wire o); 2 | assign o = !i; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (t, o); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (t, o); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (t, o); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | module mux2 (input wire i0, i1, j, output wire o); 72 | assign o = (j==0)?i0:i1; 73 | endmodule 74 | 75 | module mux4 (input wire [0:3] i, input wire j1, j0, output wire o); 76 | wire t0, t1; 77 | mux2 mux2_0 (i[0], i[1], j1, t0); 78 | mux2 mux2_1 (i[2], i[3], j1, t1); 79 | mux2 mux2_2 (t0, t1, j0, o); 80 | endmodule 81 | 82 | module mux8 (input wire [0:7] i, input wire j2, j1, j0, output wire o); 83 | wire t0, t1; 84 | mux4 mux4_0 (i[0:3], j2, j1, t0); 85 | mux4 mux4_1 (i[4:7], j2, j1, t1); 86 | mux2 mux2_0 (t0, t1, j0, o); 87 | endmodule 88 | 89 | module demux2 (input wire i, j, output wire o0, o1); 90 | assign o0 = (j==0)?i:1'b0; 91 | assign o1 = (j==1)?i:1'b0; 92 | endmodule 93 | 94 | module demux4 (input wire i, j1, j0, output wire [0:3] o); 95 | wire t0, t1; 96 | demux2 demux2_0 (i, j1, t0, t1); 97 | demux2 demux2_1 (t0, j0, o[0], o[1]); 98 | demux2 demux2_2 (t1, j0, o[2], o[3]); 99 | endmodule 100 | 101 | module demux8 (input wire i, j2, j1, j0, output wire [0:7] o); 102 | wire t0, t1; 103 | demux2 demux2_0 (i, j2, t0, t1); 104 | demux4 demux4_0 (t0, j1, j0, o[0:3]); 105 | demux4 demux4_1 (t1, j1, j0, o[4:7]); 106 | endmodule 107 | 108 | module df (input wire clk, in, output wire out); 109 | reg df_out; 110 | always@(posedge clk) df_out <= in; 111 | assign out = df_out; 112 | endmodule 113 | 114 | module dfr (input wire clk, reset, in, output wire out); 115 | wire reset_, df_in; 116 | invert invert_0 (reset, reset_); 117 | and2 and2_0 (in, reset_, df_in); 118 | df df_0 (clk, df_in, out); 119 | endmodule 120 | 121 | module dfrl (input wire clk, reset, load, in, output wire out); 122 | wire _in; 123 | mux2 mux2_0(out, in, load, _in); 124 | dfr dfr_1(clk, reset, _in, out); 125 | endmodule 126 | 127 | module dfs (input wire clk, set, in, output wire out); 128 | wire dfr_in,dfr_out; 129 | invert invert_0(in, dfr_in); 130 | invert invert_1(dfr_out, out); 131 | dfr dfr_2(clk, set, dfr_in, dfr_out); 132 | endmodule 133 | 134 | module dfsl (input wire clk, set, load, in, output wire out); 135 | wire _in; 136 | mux2 mux2_0(out, in, load, _in); 137 | dfs dfs_1(clk, set, _in, out); 138 | endmodule 139 | 140 | 141 | -------------------------------------------------------------------------------- /week-7/mproc.v: -------------------------------------------------------------------------------- 1 | module ir (input wire clk, reset, load, input wire [15:0] din, output wire [15:0] dout); 2 | dfrl dfrl_0 (clk, reset, load, din['h0], dout['h0]); 3 | dfrl dfrl_1 (clk, reset, load, din['h1], dout['h1]); 4 | dfrl dfrl_2 (clk, reset, load, din['h2], dout['h2]); 5 | dfrl dfrl_3 (clk, reset, load, din['h3], dout['h3]); 6 | dfrl dfrl_4 (clk, reset, load, din['h4], dout['h4]); 7 | dfrl dfrl_5 (clk, reset, load, din['h5], dout['h5]); 8 | dfrl dfrl_6 (clk, reset, load, din['h6], dout['h6]); 9 | dfrl dfrl_7 (clk, reset, load, din['h7], dout['h7]); 10 | dfrl dfrl_8 (clk, reset, load, din['h8], dout['h8]); 11 | dfrl dfrl_9 (clk, reset, load, din['h9], dout['h9]); 12 | dfrl dfrl_a (clk, reset, load, din['ha], dout['ha]); 13 | dfrl dfrl_b (clk, reset, load, din['hb], dout['hb]); 14 | dfrl dfrl_c (clk, reset, load, din['hc], dout['hc]); 15 | dfrl dfrl_d (clk, reset, load, din['hd], dout['hd]); 16 | dfrl dfrl_e (clk, reset, load, din['he], dout['he]); 17 | dfrl dfrl_f (clk, reset, load, din['hf], dout['hf]); 18 | endmodule 19 | 20 | module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, output wire [1:0] op, output wire pc_inc, load_ir, wr_reg); 21 | 22 | assign rd_addr_a[0] = cur_ins[0]; 23 | assign rd_addr_a[1] = cur_ins[1]; 24 | assign rd_addr_a[2] = cur_ins[2]; 25 | 26 | assign rd_addr_b[0] = cur_ins[3]; 27 | assign rd_addr_b[1] = cur_ins[4]; 28 | assign rd_addr_b[2] = cur_ins[5]; 29 | 30 | assign wr_addr[0] = cur_ins[6]; 31 | assign wr_addr[1] = cur_ins[7]; 32 | assign wr_addr[2] = cur_ins[8]; 33 | 34 | assign op[0] = cur_ins[9]; 35 | assign op[1] = cur_ins[10]; 36 | 37 | wire t1,t2,t3; 38 | 39 | or3 o1(cur_ins[11],cur_ins[12],cur_ins[13],t1); 40 | or3 o2(cur_ins[14],cur_ins[15],t1,t2); 41 | invert o3(t2,t3); 42 | dfsl g1(clk,reset,1'b1,pc_inc,load_ir); 43 | dfrl g2(clk,reset,1'b1,load_ir,pc_inc); 44 | and2 o4(pc_inc, t3,wr_reg); 45 | endmodule 46 | 47 | module mproc (input wire clk, reset, input wire [15:0] ins, output wire [15:0] addr); 48 | wire pc_inc, cout; wire [2:0] rd_addr_a, rd_addr_b, wr_addr; wire [1:0] op; wire [15:0] cur_ins, d_out_a, d_out_b; 49 | 50 | pc pc_0 (clk, reset, pc_inc, 1'b0, 1'b0, 16'b0, addr); 51 | ir ir_0 (clk, reset, load_ir, ins, cur_ins); 52 | control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, pc_inc, load_ir, wr_reg); 53 | reg_alu reg_alu_0 (clk, reset, 1'b1, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, 16'b0, d_out_a, d_out_b, cout); 54 | endmodule 55 | -------------------------------------------------------------------------------- /week-7/mproc_mem.v: -------------------------------------------------------------------------------- 1 | module ram_128_16 (input wire clk, reset, wr, input wire [6:0] addr, input wire [15:0] din, output wire [15:0] dout); 2 | reg [0:127] ram [15:0]; 3 | 4 | initial begin 5 | ram[0]=16'o000100; 6 | ram[1]=16'o001201; 7 | ram[2]=16'o002321; 8 | ram[3]=16'o003432; 9 | end 10 | always @(wr) ram[addr]=din; 11 | assign dout=ram[addr]; 12 | endmodule 13 | 14 | module mproc_mem (input wire clk, reset); 15 | wire [15:0] addr; wire [15:0] ins; 16 | 17 | ram_128_16 ram_128_16_0 (clk, reset, 1'b0, addr[6:0], 16'b0, ins); 18 | mproc mproc_0 (clk, reset, ins, addr); 19 | endmodule 20 | -------------------------------------------------------------------------------- /week-7/pc.v: -------------------------------------------------------------------------------- 1 | module pc_slice (input wire clk, reset, cin, load, inc, sub, offset, 2 | output wire cout, pc); 3 | wire in, inc_; 4 | invert invert_0 (inc, inc_); 5 | and2 and2_0 (offset, inc_, t); 6 | addsub addsub_0 (sub, pc, t, cin, in, cout); 7 | dfrl dfrl_0 (clk, reset, load, in, pc); 8 | endmodule 9 | 10 | module pc_slice0 (input wire clk, reset, cin, load, inc, sub, offset, 11 | output wire cout, pc); 12 | wire in; 13 | or2 or2_0 (offset, inc, t); 14 | addsub addsub_0 (sub, pc, t, cin, in, cout); 15 | dfrl dfrl_0 (clk, reset, load, in, pc); 16 | endmodule 17 | 18 | module pc (input wire clk, reset, inc, add, sub, input wire [15:0] offset, 19 | output wire [15:0] pc); 20 | input wire load; input wire [15:0] c; 21 | or3 or3_0 (inc, add, sub, load); 22 | pc_slice0 pc_slice_0 (clk, reset, sub, load, inc, sub, offset[0], c[0], pc[0]); 23 | pc_slice pc_slice_1 (clk, reset, c[0], load, inc, sub, offset[1], c[1], pc[1]); 24 | pc_slice pc_slice_2 (clk, reset, c[1], load, inc, sub, offset[2], c[2], pc[2]); 25 | pc_slice pc_slice_3 (clk, reset, c[2], load, inc, sub, offset[3], c[3], pc[3]); 26 | pc_slice pc_slice_4 (clk, reset, c[3], load, inc, sub, offset[4], c[4], pc[4]); 27 | pc_slice pc_slice_5 (clk, reset, c[4], load, inc, sub, offset[5], c[5], pc[5]); 28 | pc_slice pc_slice_6 (clk, reset, c[5], load, inc, sub, offset[6], c[6], pc[6]); 29 | pc_slice pc_slice_7 (clk, reset, c[6], load, inc, sub, offset[7], c[7], pc[7]); 30 | pc_slice pc_slice_8 (clk, reset, c[7], load, inc, sub, offset[8], c[8], pc[8]); 31 | pc_slice pc_slice_9 (clk, reset, c[8], load, inc, sub, offset[9], c[9], pc[9]); 32 | pc_slice pc_slice_10 (clk, reset, c[9], load, inc, sub, offset[10], c[10], pc[10]); 33 | pc_slice pc_slice_11 (clk, reset, c[10], load, inc, sub, offset[11], c[11], pc[11]); 34 | pc_slice pc_slice_12 (clk, reset, c[11], load, inc, sub, offset[12], c[12], pc[12]); 35 | pc_slice pc_slice_13 (clk, reset, c[12], load, inc, sub, offset[13], c[13], pc[13]); 36 | pc_slice pc_slice_14 (clk, reset, c[13], load, inc, sub, offset[14], c[14], pc[14]); 37 | pc_slice pc_slice_15 (clk, reset, c[14], load, inc, sub, offset[15], c[15], pc[15]); 38 | endmodule 39 | -------------------------------------------------------------------------------- /week-7/reg_alu.v: -------------------------------------------------------------------------------- 1 | module reg_file_2_1 (input wire clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, d_in, output wire d_out_a, d_out_b); 2 | wire l0, l1, o0, o1; 3 | dfrl dfrl_0 (clk, reset, l0, d_in, o0); 4 | dfrl dfrl_1 (clk, reset, l1, d_in, o1); 5 | mux2 mux2_a (o0, o1, rd_addr_a, d_out_a); 6 | mux2 mux2_b (o0, o1, rd_addr_b, d_out_b); 7 | demux2 demux2_0 (wr, wr_addr, l0, l1); 8 | endmodule 9 | 10 | module _reg_file_2_1 (input wire clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, d_in, output wire d_out_a, d_out_b); 11 | wire l0, l1, o0, o1; 12 | dfsl dfsl_0 (clk, reset, l0, d_in, o0); 13 | dfrl dfrl_1 (clk, reset, l1, d_in, o1); 14 | mux2 mux2_a (o0, o1, rd_addr_a, d_out_a); 15 | mux2 mux2_b (o0, o1, rd_addr_b, d_out_b); 16 | demux2 demux2_0 (wr, wr_addr, l0, l1); 17 | endmodule 18 | 19 | module _reg_file_4_1 (input wire clk, reset, wr, input wire [1:0] rd_addr_a, rd_addr_b, wr_addr, input wire d_in, output wire d_out_a, d_out_b); 20 | wire wr0, wr1, o0_a, o0_b, o1_a, o1_b; 21 | _reg_file_2_1 reg_file_2_1_0 (clk, reset, wr0, rd_addr_a[0], rd_addr_b[0], wr_addr[0], 22 | d_in, o0_a, o0_b); 23 | reg_file_2_1 reg_file_2_1_1 (clk, reset, wr1, rd_addr_a[0], rd_addr_b[0], wr_addr[0], 24 | d_in, o1_a, o1_b); 25 | mux2 mux2_a (o0_a, o1_a, rd_addr_a[1], d_out_a); 26 | mux2 mux2_b (o0_b, o1_b, rd_addr_b[1], d_out_b); 27 | demux2 demux2_0 (wr, wr_addr[1], wr0, wr1); 28 | endmodule 29 | 30 | module reg_file_4_1 (input wire clk, reset, wr, input wire [1:0] rd_addr_a, rd_addr_b, wr_addr, input wire d_in, output wire d_out_a, d_out_b); 31 | wire wr0, wr1, o0_a, o0_b, o1_a, o1_b; 32 | reg_file_2_1 reg_file_2_1_0 (clk, reset, wr0, rd_addr_a[0], rd_addr_b[0], wr_addr[0], 33 | d_in, o0_a, o0_b); 34 | reg_file_2_1 reg_file_2_1_1 (clk, reset, wr1, rd_addr_a[0], rd_addr_b[0], wr_addr[0], 35 | d_in, o1_a, o1_b); 36 | mux2 mux2_a (o0_a, o1_a, rd_addr_a[1], d_out_a); 37 | mux2 mux2_b (o0_b, o1_b, rd_addr_b[1], d_out_b); 38 | demux2 demux2_0 (wr, wr_addr[1], wr0, wr1); 39 | endmodule 40 | 41 | module reg_file_8_1 (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire d_in, output wire d_out_a, d_out_b); 42 | wire wr0, wr1, o0_a, o0_b, o1_a, o1_b; 43 | _reg_file_4_1 reg_file_4_1_0 (clk, reset, wr0, rd_addr_a[1:0], rd_addr_b[1:0], wr_addr[1:0], 44 | d_in, o0_a, o0_b); 45 | reg_file_4_1 reg_file_4_1_1 (clk, reset, wr1, rd_addr_a[1:0], rd_addr_b[1:0], wr_addr[1:0], 46 | d_in, o1_a, o1_b); 47 | mux2 mux2_a (o0_a, o1_a, rd_addr_a[2], d_out_a); 48 | mux2 mux2_b (o0_b, o1_b, rd_addr_b[2], d_out_b); 49 | demux2 demux2_0 (wr, wr_addr[2], wr0, wr1); 50 | endmodule 51 | 52 | module reg_file_8_4 (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [3:0] d_in, output wire [3:0] d_out_a, d_out_b); 53 | reg_file_8_1 reg_file_8_1_0 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 54 | d_in[0], d_out_a[0], d_out_b[0]); 55 | reg_file_8_1 reg_file_8_1_1 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 56 | d_in[1], d_out_a[1], d_out_b[1]); 57 | reg_file_8_1 reg_file_8_1_2 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 58 | d_in[2], d_out_a[2], d_out_b[2]); 59 | reg_file_8_1 reg_file_8_1_3 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 60 | d_in[3], d_out_a[3], d_out_b[3]); 61 | endmodule 62 | 63 | module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b); 64 | reg_file_8_4 reg_file_8_4_0 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 65 | d_in[3:0], d_out_a[3:0], d_out_b[3:0]); 66 | reg_file_8_4 reg_file_8_4_1 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 67 | d_in[7:4], d_out_a[7:4], d_out_b[7:4]); 68 | reg_file_8_4 reg_file_8_4_2 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 69 | d_in[11:8], d_out_a[11:8], d_out_b[11:8]); 70 | reg_file_8_4 reg_file_8_4_3 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, 71 | d_in[15:12], d_out_a[15:12], d_out_b[15:12]); 72 | endmodule 73 | 74 | module mux2_4 (input wire [3:0] i0, i1, input wire j, output wire [3:0] o); 75 | mux2 mux2_0 (i0[0], i1[0], j, o[0]); 76 | mux2 mux2_1 (i0[1], i1[1], j, o[1]); 77 | mux2 mux2_2 (i0[2], i1[2], j, o[2]); 78 | mux2 mux2_3 (i0[3], i1[3], j, o[3]); 79 | endmodule 80 | 81 | module mux2_16 (input wire [15:0] i0, i1, input wire j, output wire [15:0] o); 82 | mux2_4 mux2_4_0 (i0[3:0], i1[3:0], j, o[3:0]); 83 | mux2_4 mux2_4_1 (i0[7:4], i1[7:4], j, o[7:4]); 84 | mux2_4 mux2_4_2 (i0[11:8], i1[11:8], j, o[11:8]); 85 | mux2_4 mux2_4_3 (i0[15:12], i1[15:12], j, o[15:12]); 86 | endmodule 87 | 88 | module reg_alu (input wire clk, reset, sel, wr, input wire [1:0] op, input wire [2:0] rd_addr_a, 89 | rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b, output wire cout); 90 | wire [15:0] d_in_alu, d_in_reg; wire cout_0; 91 | alu alu_0 (op, d_out_a, d_out_b, d_in_alu, cout_0); 92 | reg_file reg_file_0 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, d_in_reg, d_out_a, d_out_b); 93 | mux2_16 mux2_16_0 (d_in, d_in_alu, sel, d_in_reg); 94 | dfr dfr_0 (clk, reset, cout_0, cout); 95 | endmodule 96 | -------------------------------------------------------------------------------- /week-7/tb_mproc_mem.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 100 ps 2 | 3 | `define TESTVECS 4 4 | 5 | 6 | module tb; 7 | 8 | reg clk, reset; 9 | 10 | integer i; 11 | 12 | initial begin 13 | $dumpfile("tb_mproc_mem.vcd"); 14 | $dumpvars(0,tb); 15 | end 16 | 17 | initial 18 | begin 19 | reset = 1'b1; 20 | #12.5 reset = 1'b0; 21 | end 22 | 23 | initial clk = 1'b0; 24 | always #5 clk =~ clk; 25 | 26 | mproc_mem mproc_mem_0 (clk, reset); 27 | 28 | initial begin 29 | 30 | #6 for(i=0;i<`TESTVECS;i=i+1) 31 | 32 | begin #10; end 33 | 34 | #100 $finish; 35 | 36 | end 37 | endmodule 38 | --------------------------------------------------------------------------------