├── a.out ├── .DS_Store ├── bank ├── .DS_Store ├── .load.swo ├── .load.swp ├── .test.c.swp ├── .test.cc.swp ├── .craft.py.swo ├── .craft.py.swp ├── .osx_elf.h.swo ├── .osx_elf.h.swp ├── .load_bank.cc.swl ├── .load_bank.cc.swn ├── .load_bank.cc.swo ├── .load_bank.cc.swp ├── .load_bank.h.swm ├── .load_bank.h.swn ├── .load_bank.h.swo ├── .load_bank.h.swp ├── testing │ └── test_exec ├── craft.py ├── osx_elf.h ├── .w.swp ├── .NetrwMessage.swp ├── .craft.pye.swo ├── .craft.pye.swp ├── .load_bank.cc.swm └── load_bank.h ├── debug ├── test_exec ├── .debug.cc.swm ├── .debug.cc.swn ├── .debug.cc.swo ├── .debug.cc.swp └── debug.cc ├── reversing ├── test ├── tete ├── donna_debug ├── .craft.py.swo ├── test.s ├── geo.sh ├── craft.py └── .craft.pa.swp ├── banks ├── .arm64.bank.swp └── arm64.bank ├── tooling ├── build_all.sh └── cleanup.sh ├── cleanup.sh ├── web ├── templates │ ├── .index.html.swp │ └── index.html ├── __pycache__ │ ├── dweb.cpython-39.pyc │ ├── donna_backend.cpython-38.pyc │ └── donna_backend.cpython-39.pyc ├── dweb.py └── .we.swp ├── data ├── decompiledtete.dn └── reginfo │ ├── tete0.reginfo │ ├── tete1.reginfo │ ├── tete2.reginfo │ ├── tete3.reginfo │ ├── tete4.reginfo │ ├── tete5.reginfo │ └── tete6.reginfo ├── notes ├── README.md ├── donna.py ├── .ba.swp ├── .test.s.swo ├── .test.s.swp ├── .web.py.swp └── LICENSE /a.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/a.out -------------------------------------------------------------------------------- /.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/.DS_Store -------------------------------------------------------------------------------- /bank/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.DS_Store -------------------------------------------------------------------------------- /bank/.load.swo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load.swo -------------------------------------------------------------------------------- /bank/.load.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load.swp -------------------------------------------------------------------------------- /debug/test_exec: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/debug/test_exec -------------------------------------------------------------------------------- /reversing/test: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/reversing/test -------------------------------------------------------------------------------- /reversing/tete: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/reversing/tete -------------------------------------------------------------------------------- /bank/.test.c.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.test.c.swp -------------------------------------------------------------------------------- /bank/.test.cc.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.test.cc.swp -------------------------------------------------------------------------------- /bank/.craft.py.swo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.craft.py.swo -------------------------------------------------------------------------------- /bank/.craft.py.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.craft.py.swp -------------------------------------------------------------------------------- /bank/.osx_elf.h.swo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.osx_elf.h.swo -------------------------------------------------------------------------------- /bank/.osx_elf.h.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.osx_elf.h.swp -------------------------------------------------------------------------------- /debug/.debug.cc.swm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/debug/.debug.cc.swm -------------------------------------------------------------------------------- /debug/.debug.cc.swn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/debug/.debug.cc.swn -------------------------------------------------------------------------------- /debug/.debug.cc.swo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/debug/.debug.cc.swo -------------------------------------------------------------------------------- /debug/.debug.cc.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/debug/.debug.cc.swp -------------------------------------------------------------------------------- /bank/.load_bank.cc.swl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.cc.swl -------------------------------------------------------------------------------- /bank/.load_bank.cc.swn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.cc.swn -------------------------------------------------------------------------------- /bank/.load_bank.cc.swo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.cc.swo -------------------------------------------------------------------------------- /bank/.load_bank.cc.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.cc.swp -------------------------------------------------------------------------------- /bank/.load_bank.h.swm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.h.swm -------------------------------------------------------------------------------- /bank/.load_bank.h.swn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.h.swn -------------------------------------------------------------------------------- /bank/.load_bank.h.swo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.h.swo -------------------------------------------------------------------------------- /bank/.load_bank.h.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/.load_bank.h.swp -------------------------------------------------------------------------------- /bank/testing/test_exec: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/bank/testing/test_exec -------------------------------------------------------------------------------- /banks/.arm64.bank.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/banks/.arm64.bank.swp -------------------------------------------------------------------------------- /reversing/donna_debug: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/reversing/donna_debug -------------------------------------------------------------------------------- /reversing/.craft.py.swo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/reversing/.craft.py.swo -------------------------------------------------------------------------------- /tooling/build_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | cd ../ 3 | c++ ./debug/debug.cc -o backend -I ./bank; 4 | -------------------------------------------------------------------------------- /cleanup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | cd ./data/ 3 | rm * 4 | cd ./reginfo 5 | rm * 6 | 7 | cd ../../ 8 | 9 | -------------------------------------------------------------------------------- /reversing/test.s: -------------------------------------------------------------------------------- 1 | .globl _start 2 | .align 2 3 | _start: 4 | mov x1,x30 5 | mov w1,w30 6 | 7 | 8 | -------------------------------------------------------------------------------- /web/templates/.index.html.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/web/templates/.index.html.swp -------------------------------------------------------------------------------- /web/__pycache__/dweb.cpython-39.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/web/__pycache__/dweb.cpython-39.pyc -------------------------------------------------------------------------------- /tooling/cleanup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | cd .. 3 | 4 | cd ./data/ 5 | rm * 6 | cd ./reginfo 7 | rm * 8 | cd ../../ 9 | 10 | -------------------------------------------------------------------------------- /web/__pycache__/donna_backend.cpython-38.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/web/__pycache__/donna_backend.cpython-38.pyc -------------------------------------------------------------------------------- /web/__pycache__/donna_backend.cpython-39.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suibex/donna/HEAD/web/__pycache__/donna_backend.cpython-39.pyc -------------------------------------------------------------------------------- /reversing/geo.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | as test.s -o tete; 4 | ld tete -o test; 5 | ./donna_debug test ./banks/arm64.bank; 6 | #./build_all.sh && ./donna_debug test ./banks/arm64.bank; 7 | -------------------------------------------------------------------------------- /data/decompiledtete.dn: -------------------------------------------------------------------------------- 1 | 0x400078: movz x0,#20 2 | 0x40007c: movz x1,#10 3 | 0x400080: movz x2,#0 4 | 0x400084: add x2,x2,#1 5 | 0x400088: cmpx x2,x1 6 | 0x40008c: cmpx x30,x20 7 | 0x400090: b.c #524285 8 | -------------------------------------------------------------------------------- /reversing/craft.py: -------------------------------------------------------------------------------- 1 | import os,io,sys 2 | 3 | 4 | dn =lambda x, n: format(x, 'b').zfill(n) 5 | 6 | def log(test): 7 | n = test 8 | num = dn(n,32) 9 | for i in range(32): 10 | if( i%4==0): 11 | print(" ",end="") 12 | print(num[i],end="") 13 | print("") 14 | 15 | 16 | #test =0x5280028d 17 | #test = 0x8d028052 18 | log(0xaa1e03e1) 19 | log(0xeb01005f) 20 | log(0xeb1403df) 21 | -------------------------------------------------------------------------------- /data/reginfo/tete0.reginfo: -------------------------------------------------------------------------------- 1 | w0: 0 2 | w1: 0 3 | w2: 0 4 | w3: 0 5 | w4: 0 6 | w5: 0 7 | w6: 0 8 | w7: 0 9 | w8: 0 10 | w9: 0 11 | w10: 0 12 | w11: 0 13 | w12: 0 14 | w13: 0 15 | w14: 0 16 | w15: 0 17 | w16: 0 18 | w17: 0 19 | w18: 0 20 | w19: 0 21 | w20: 0 22 | w21: 0 23 | w22: 0 24 | w23: 0 25 | w24: 0 26 | w25: 0 27 | w26: 0 28 | w27: 0 29 | w28: 0 30 | w29: 0 31 | w30: 0 32 | w31: 281474976708384 33 | pc: 4194424 34 | sp: 281474976708384 35 | pstate: 4096 -------------------------------------------------------------------------------- /data/reginfo/tete1.reginfo: -------------------------------------------------------------------------------- 1 | w0: 20 2 | w1: 0 3 | w2: 0 4 | w3: 0 5 | w4: 0 6 | w5: 0 7 | w6: 0 8 | w7: 0 9 | w8: 0 10 | w9: 0 11 | w10: 0 12 | w11: 0 13 | w12: 0 14 | w13: 0 15 | w14: 0 16 | w15: 0 17 | w16: 0 18 | w17: 0 19 | w18: 0 20 | w19: 0 21 | w20: 0 22 | w21: 0 23 | w22: 0 24 | w23: 0 25 | w24: 0 26 | w25: 0 27 | w26: 0 28 | w27: 0 29 | w28: 0 30 | w29: 0 31 | w30: 0 32 | w31: 281474976708384 33 | pc: 4194428 34 | sp: 281474976708384 35 | pstate: 2101248 -------------------------------------------------------------------------------- /data/reginfo/tete2.reginfo: -------------------------------------------------------------------------------- 1 | w0: 20 2 | w1: 10 3 | w2: 0 4 | w3: 0 5 | w4: 0 6 | w5: 0 7 | w6: 0 8 | w7: 0 9 | w8: 0 10 | w9: 0 11 | w10: 0 12 | w11: 0 13 | w12: 0 14 | w13: 0 15 | w14: 0 16 | w15: 0 17 | w16: 0 18 | w17: 0 19 | w18: 0 20 | w19: 0 21 | w20: 0 22 | w21: 0 23 | w22: 0 24 | w23: 0 25 | w24: 0 26 | w25: 0 27 | w26: 0 28 | w27: 0 29 | w28: 0 30 | w29: 0 31 | w30: 0 32 | w31: 281474976708384 33 | pc: 4194432 34 | sp: 281474976708384 35 | pstate: 2101248 -------------------------------------------------------------------------------- /data/reginfo/tete3.reginfo: -------------------------------------------------------------------------------- 1 | w0: 20 2 | w1: 10 3 | w2: 0 4 | w3: 0 5 | w4: 0 6 | w5: 0 7 | w6: 0 8 | w7: 0 9 | w8: 0 10 | w9: 0 11 | w10: 0 12 | w11: 0 13 | w12: 0 14 | w13: 0 15 | w14: 0 16 | w15: 0 17 | w16: 0 18 | w17: 0 19 | w18: 0 20 | w19: 0 21 | w20: 0 22 | w21: 0 23 | w22: 0 24 | w23: 0 25 | w24: 0 26 | w25: 0 27 | w26: 0 28 | w27: 0 29 | w28: 0 30 | w29: 0 31 | w30: 0 32 | w31: 281474976708384 33 | pc: 4194436 34 | sp: 281474976708384 35 | pstate: 2101248 -------------------------------------------------------------------------------- /data/reginfo/tete4.reginfo: -------------------------------------------------------------------------------- 1 | w0: 20 2 | w1: 10 3 | w2: 1 4 | w3: 0 5 | w4: 0 6 | w5: 0 7 | w6: 0 8 | w7: 0 9 | w8: 0 10 | w9: 0 11 | w10: 0 12 | w11: 0 13 | w12: 0 14 | w13: 0 15 | w14: 0 16 | w15: 0 17 | w16: 0 18 | w17: 0 19 | w18: 0 20 | w19: 0 21 | w20: 0 22 | w21: 0 23 | w22: 0 24 | w23: 0 25 | w24: 0 26 | w25: 0 27 | w26: 0 28 | w27: 0 29 | w28: 0 30 | w29: 0 31 | w30: 0 32 | w31: 281474976708384 33 | pc: 4194440 34 | sp: 281474976708384 35 | pstate: 2101248 -------------------------------------------------------------------------------- /data/reginfo/tete5.reginfo: -------------------------------------------------------------------------------- 1 | w0: 20 2 | w1: 10 3 | w2: 1 4 | w3: 0 5 | w4: 0 6 | w5: 0 7 | w6: 0 8 | w7: 0 9 | w8: 0 10 | w9: 0 11 | w10: 0 12 | w11: 0 13 | w12: 0 14 | w13: 0 15 | w14: 0 16 | w15: 0 17 | w16: 0 18 | w17: 0 19 | w18: 0 20 | w19: 0 21 | w20: 0 22 | w21: 0 23 | w22: 0 24 | w23: 0 25 | w24: 0 26 | w25: 0 27 | w26: 0 28 | w27: 0 29 | w28: 0 30 | w29: 0 31 | w30: 0 32 | w31: 281474976708384 33 | pc: 4194444 34 | sp: 281474976708384 35 | pstate: 2149584896 -------------------------------------------------------------------------------- /data/reginfo/tete6.reginfo: -------------------------------------------------------------------------------- 1 | w0: 20 2 | w1: 10 3 | w2: 1 4 | w3: 0 5 | w4: 0 6 | w5: 0 7 | w6: 0 8 | w7: 0 9 | w8: 0 10 | w9: 0 11 | w10: 0 12 | w11: 0 13 | w12: 0 14 | w13: 0 15 | w14: 0 16 | w15: 0 17 | w16: 0 18 | w17: 0 19 | w18: 0 20 | w19: 0 21 | w20: 0 22 | w21: 0 23 | w22: 0 24 | w23: 0 25 | w24: 0 26 | w25: 0 27 | w26: 0 28 | w27: 0 29 | w28: 0 30 | w29: 0 31 | w30: 0 32 | w31: 281474976708384 33 | pc: 4194448 34 | sp: 281474976708384 35 | pstate: 1612713984 -------------------------------------------------------------------------------- /notes: -------------------------------------------------------------------------------- 1 | 2 | donna v4.0 3 | actually more like qira but whatever. 4 | it has to first have banker system that is going to decrypt back the instructions. 5 | everything else is just an addon 6 | 7 | how do we find the instruction? 8 | example: 9 | 0101 0010 1000 0000 0000 0010 1001 1010 <-fetched binary number 10 | xxx1 1010 1x0m mmmm xx1x 10nn nnnd dddd - asrv Rd Rn Rm <- example from arm64.bank 11 | compare first three "numbers" 12 | but skip everything that isnt 1 or 0 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /bank/craft.py: -------------------------------------------------------------------------------- 1 | import os,io,sys 2 | 3 | dn =lambda x, n: format(x, 'b').zfill(n) 4 | 5 | #test =0x5280028d 6 | #test = 0x8d028052 7 | test = 0x5280028d 8 | n = test 9 | num = dn(n,32) 10 | print(num) 11 | 12 | 13 | mov = "x10x00101xxiiiiiiiiiiiiiiiiddddd" 14 | 15 | #print("x00x 0010 1xxi iiii iiii iiii iiid dddd - movn Rd HALF") 16 | #opcodes=[int(num[:4],2),int(num[4:8],2)] 17 | #val = num[10:27] 18 | value="" 19 | reg= "" 20 | for i in range(len(mov)): 21 | if(mov[i] == 'i'): 22 | value+=num[i] 23 | if(mov[i] == 'd'): 24 | reg+=num[i] 25 | 26 | reg = int(reg,2) 27 | value = int(value,2) 28 | print(reg,value) 29 | 30 | -------------------------------------------------------------------------------- /web/dweb.py: -------------------------------------------------------------------------------- 1 | """ 2 | *part of nitrodegen's god tool for debugging aarch64 based systems.* 3 | 4 | web-server module 5 | its going to run all of the greatest technology for your 'perfect' debugging. 6 | (this code is ass) 7 | 8 | (C) Gavrilo Palalic 2022. 9 | """ 10 | import os,io,sys 11 | import struct 12 | from flask import * 13 | data = [] 14 | markings="" 15 | app = Flask(__name__,static_folder='./static') 16 | class DonnaWebServer(object): 17 | def __init__(self): 18 | 19 | app = Flask(__name__,static_folder='./static') 20 | def run_server(self): 21 | app.run("0.0.0.0",3001,debug=True)#qira basic shit 22 | @app.route('/',methods=['GET','POST']) 23 | def main(): 24 | return render_template("index.html") 25 | @app.route('/file_request',methods=['GET','POST']) 26 | def send_file_data(): 27 | #data=[data[0],data[1],data[2],markings] 28 | 29 | return jsonify(data) 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # donna 2 |

3 | debugger often named "never again" (donna) is a debugger and analyzer made for ARM ELF executables that runs on Linux. 4 |
Not a competitor to gdb or lldb or qira.
5 |
Created by me , so feel free to change and modify it , as long as you don't sell it ,copy it,etc...
6 |

'i'm not into you, i'm donna.' - Suits

7 |

donna provides you with webserver that you can connect to by localhost, port 3001

8 |
Not a fan of websites? , you have 'backend' executable so you can run donna without webserver (but why?) 9 |

10 |

Timeless debugging , no need to set breakpoints.

11 | 12 | ![Screenshot 2022-10-23 at 17 56 05](https://user-images.githubusercontent.com/59802817/197403075-d7384e4c-1d60-43e3-a9a8-ac13699a20b4.png) 13 | 14 | 15 | 16 |

donna in Safari ( backend running on docker):

17 | 18 | ![Screenshot 2022-10-23 at 17 54 47](https://user-images.githubusercontent.com/59802817/197403040-2136d0c8-a8b5-4115-83c0-1c486cf4cc86.png) 19 | 20 |

Limitations of donna:

21 |

22 |
well , donna does support banking ( you can load your custom instructions by .bank file ), it isn't documented. so , feel free to reverse engineer that.
also, donna uses ptrace (macOS hates ptrace. so debugging part of donna, doesn't work on macOS). 23 |
I do not consider donna a usable tool for some professional reverse engineering. this is just my shot at building a debugger. 24 |
feel free to help me make donna great by contributing updates and fixes!
25 |
donna only works on debian Linux , more preferably , Ubuntu 18.04 and higher!
26 |

27 | 28 |

how to build donna?

29 |
to build donna. just run 'build_all.sh' and you're done. easy.
30 | 31 | 32 |

have a nice day.

33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /donna.py: -------------------------------------------------------------------------------- 1 | """ 2 | *part of nitrodegen's god tool for debugging aarch64 based systems.* 3 | donna backend and frontend wrapper 4 | this module is used to actually run the app and everything else 5 | 6 | (C) Gavrilo Palalic 2022 7 | """ 8 | import os,io,sys 9 | 10 | if(len(sys.argv) < 2): 11 | print("***** donna v4.0 *****\n\tARM ELF debugger and analyzer. (maybe expanded in future)") 12 | print("how to use:\nprovide filename of the file you want to analyze.\nexample: python3 donna.py ") 13 | exit(1) 14 | 15 | def file_markings(filename,dec): 16 | BASE_ADDR = 0x400000 #TODO:actually find the address again, don't just try to predict. 17 | #but im lazy so whatever. 18 | d = open(filename,"rb") 19 | 20 | d = d.read() 21 | addresses=[] 22 | dec = dec.split("\n") 23 | for x in dec: 24 | if(len(x) > 1): 25 | x=x.split(":")[0].replace("0x","") 26 | x = int(x,base=16) 27 | addresses.append(x-BASE_ADDR) 28 | #exit(1) 29 | analyzed="" 30 | result="" 31 | 32 | for byte in d: 33 | if(byte <0x22 or byte>0xd088): 34 | byte="." 35 | else: 36 | byte=chr(byte) 37 | analyzed+=byte 38 | 39 | 40 | for i in range(len(analyzed)): 41 | bb = analyzed[i] 42 | for j in range(len(addresses)): 43 | if(i == addresses[j]): 44 | bb="" 45 | 46 | for z in range(4): 47 | 48 | bb+=analyzed[addresses[j]+z] 49 | bb=""+bb+"" 50 | result+=(bb) 51 | return result 52 | 53 | def read_config_data(filename): 54 | analysis=None 55 | reginfo=[] 56 | data = os.listdir("./data") 57 | print("*** reading analysis...") 58 | for file in data: 59 | #print(file) 60 | if(file != "reginfo"): 61 | if(".dn" in file): 62 | fname = file.split("decompiled")[1].replace(".dn","") 63 | if(filename == fname): 64 | d = open("./data/"+file) 65 | d =d.read() 66 | analysis = d 67 | 68 | else: 69 | d = os.listdir("./data/reginfo") 70 | for x in d: 71 | fdd = x.split(".") 72 | fname=fdd[0] 73 | if(filename in fname): 74 | z = open("./data/reginfo/"+x) 75 | z =z.read() 76 | part = fname.split(filename)[1] 77 | part=int(part) 78 | # print(part) 79 | reginfo.append((z,part)) 80 | 81 | for i in range(len(reginfo)): 82 | for j in range(len(reginfo)): 83 | if(reginfo[i][1] < reginfo[j][1]): 84 | t = reginfo[i] 85 | reginfo[i] = reginfo[j] 86 | reginfo[j] =t 87 | reg=[] 88 | for i in range(len(reginfo)): 89 | reg.append(reginfo[i][0]) 90 | 91 | reginfo= reg 92 | 93 | return [analysis,reginfo] 94 | os.system("cd tooling && ./cleanup.sh && cd ../") 95 | sys.path.insert(1, './web') 96 | import dweb 97 | filename = sys.argv[1] 98 | data=read_config_data(filename) 99 | markings = file_markings(filename,data[0]) 100 | os.system("./backend "+filename +" ./banks/arm64.bank") 101 | data= (filename,data[0],data[1],markings) 102 | dweb.data=data 103 | wb = dweb.DonnaWebServer() 104 | wb.run_server() 105 | 106 | -------------------------------------------------------------------------------- /bank/osx_elf.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #define __u32 uint32_t 6 | #define __u64 uint64_t 7 | #define __u16 uint16_t 8 | #define __u32 uint32_t 9 | #define __u64 uint64_t 10 | #define __u16 uint16_t 11 | #define __s32 uint16_t 12 | #define __s64 uint32_t 13 | #define __s16 uint8_t 14 | typedef __u32 Elf32_Addr; 15 | typedef __u16 Elf32_Half; 16 | typedef __u32 Elf32_Off; 17 | typedef __s32 Elf32_Sword; 18 | typedef __u32 Elf32_Word; 19 | 20 | /* 64-bit ELF base types. */ 21 | typedef __u64 Elf64_Addr; 22 | typedef __u16 Elf64_Half; 23 | typedef __s16 Elf64_SHalf; 24 | typedef __u64 Elf64_Off; 25 | typedef __s32 Elf64_Sword; 26 | typedef __u32 Elf64_Word; 27 | typedef __u64 Elf64_Xword; 28 | typedef __s64 Elf64_Sxword; 29 | 30 | 31 | 32 | #define EI_NIDENT 16 33 | 34 | typedef struct elf32_hdr{ 35 | unsigned char e_ident[EI_NIDENT]; 36 | Elf32_Half e_type; 37 | Elf32_Half e_machine; 38 | Elf32_Word e_version; 39 | Elf32_Addr e_entry; /* Entry point */ 40 | Elf32_Off e_phoff; 41 | Elf32_Off e_shoff; 42 | Elf32_Word e_flags; 43 | Elf32_Half e_ehsize; 44 | Elf32_Half e_phentsize; 45 | Elf32_Half e_phnum; 46 | Elf32_Half e_shentsize; 47 | Elf32_Half e_shnum; 48 | Elf32_Half e_shstrndx; 49 | } Elf32_Ehdr; 50 | 51 | typedef struct elf64_hdr { 52 | unsigned char e_ident[EI_NIDENT]; /* ELF "magic number" */ 53 | Elf64_Half e_type; 54 | Elf64_Half e_machine; 55 | Elf64_Word e_version; 56 | Elf64_Addr e_entry; /* Entry point virtual address */ 57 | Elf64_Off e_phoff; /* Program header table file offset */ 58 | Elf64_Off e_shoff; /* Section header table file offset */ 59 | Elf64_Word e_flags; 60 | Elf64_Half e_ehsize; 61 | Elf64_Half e_phentsize; 62 | Elf64_Half e_phnum; 63 | Elf64_Half e_shentsize; 64 | Elf64_Half e_shnum; 65 | Elf64_Half e_shstrndx; 66 | } Elf64_Ehdr; 67 | 68 | /* These constants define the permissions on sections in the program 69 | header, p_flags. */ 70 | #define PF_R 0x4 71 | #define PF_W 0x2 72 | #define PF_X 0x1 73 | 74 | typedef struct elf32_phdr{ 75 | Elf32_Word p_type; 76 | Elf32_Off p_offset; 77 | Elf32_Addr p_vaddr; 78 | Elf32_Addr p_paddr; 79 | Elf32_Word p_filesz; 80 | Elf32_Word p_memsz; 81 | Elf32_Word p_flags; 82 | Elf32_Word p_align; 83 | } Elf32_Phdr; 84 | 85 | typedef struct elf64_phdr { 86 | Elf64_Word p_type; 87 | Elf64_Word p_flags; 88 | Elf64_Off p_offset; /* Segment file offset */ 89 | Elf64_Addr p_vaddr; /* Segment virtual address */ 90 | Elf64_Addr p_paddr; /* Segment physical address */ 91 | Elf64_Xword p_filesz; /* Segment size in file */ 92 | Elf64_Xword p_memsz; /* Segment size in memory */ 93 | Elf64_Xword p_align; /* Segment alignment, file & memory */ 94 | } Elf64_Phdr; 95 | 96 | 97 | typedef struct elf32_shdr { 98 | Elf32_Word sh_name; 99 | Elf32_Word sh_type; 100 | Elf32_Word sh_flags; 101 | Elf32_Addr sh_addr; 102 | Elf32_Off sh_offset; 103 | Elf32_Word sh_size; 104 | Elf32_Word sh_link; 105 | Elf32_Word sh_info; 106 | Elf32_Word sh_addralign; 107 | Elf32_Word sh_entsize; 108 | } Elf32_Shdr; 109 | 110 | typedef struct elf64_shdr { 111 | Elf64_Word sh_name; /* Section name, index in string tbl */ 112 | Elf64_Word sh_type; /* Type of section */ 113 | Elf64_Xword sh_flags; /* Miscellaneous section attributes */ 114 | Elf64_Addr sh_addr; /* Section virtual addr at execution */ 115 | Elf64_Off sh_offset; /* Section file offset */ 116 | Elf64_Xword sh_size; /* Size of section in bytes */ 117 | Elf64_Word sh_link; /* Index of another section */ 118 | Elf64_Word sh_info; /* Additional section information */ 119 | Elf64_Xword sh_addralign; /* Section alignment */ 120 | Elf64_Xword sh_entsize; /* Entry size if section holds table */ 121 | } Elf64_Shdr; 122 | 123 | 124 | 125 | -------------------------------------------------------------------------------- /.ba.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.1]root796c0bc08be8/home/donna/donna/ba U3210#"! U -------------------------------------------------------------------------------- /.test.s.swo: -------------------------------------------------------------------------------- 1 | b0VIM 8.1wBTc !wroot796c0bc08be8/home/donna/donna/test.s U3210#"! U -------------------------------------------------------------------------------- /.test.s.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.1(root796c0bc08be8/home/donna/donna/test.s U3210#"! U -------------------------------------------------------------------------------- /.web.py.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.1I root796c0bc08be8/home/donna/donna/web.py 3210#"! U -------------------------------------------------------------------------------- /bank/.w.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.2+agavrilomorelife~gavrilo/Desktop/donna/bank/w 3210#"! U -------------------------------------------------------------------------------- /web/.we.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.1E root796c0bc08be8/home/donna/donna/web/we 3210#"! U -------------------------------------------------------------------------------- /bank/.NetrwMessage.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.2Vagavrilomorelife~gavrilo/Desktop/donna/bank/NetrwMessage U3210#"! U -------------------------------------------------------------------------------- /bank/.craft.pye.swo: -------------------------------------------------------------------------------- 1 | b0VIM 8.2}fgavrilomorelife~gavrilo/Desktop/donna/bank/craft.pye U3210#"! U -------------------------------------------------------------------------------- /bank/.craft.pye.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.2>fgavrilomorelife~gavrilo/Desktop/donna/bank/craft.pye U3210#"! U -------------------------------------------------------------------------------- /bank/.load_bank.cc.swm: -------------------------------------------------------------------------------- 1 | b0VIM 8.1Vroot796c0bc08be8/home/donna/donna/bank/load_bank.cc 3210#"! U -------------------------------------------------------------------------------- /reversing/.craft.pa.swp: -------------------------------------------------------------------------------- 1 | b0VIM 8.1? 2 | root796c0bc08be8/home/donna/donna/reversing/craft.pa 3210#"! U -------------------------------------------------------------------------------- /debug/debug.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include "load_bank.h" 14 | #include 15 | #include 16 | #include 17 | #include 18 | #define ARM 0x00 19 | #define X86 0x01 20 | #define __u64 uint64_t 21 | #define NT_PRSTATUS 1 22 | using namespace std; 23 | //copied from linux/ptrace.h <-- for some reason , macOS devs haven't finished this struct. 24 | //apparently they do not like debugging. only closed source code and zero knowledge of the user. why cook? 25 | //macos is actually a really fun os to use , just closed source thing kinda f's it up. 26 | struct user_pt_regiz{ 27 | __u64 regs [31]; 28 | __u64 sp; 29 | __u64 pc; 30 | __u64 pstate; 31 | }; 32 | class WeakAssDebugger{ 33 | public: 34 | bool debug; 35 | pid_t address; 36 | string filename; 37 | int arch; 38 | vectoraddresses; 39 | 40 | WeakAssDebugger(vector p ,string fn,bool debug_option,int a){ 41 | arch =a; 42 | debug=debug_option; 43 | filename = fn; 44 | for(int i =0;i old_data; 76 | wait(&stat); 77 | while(WIFSTOPPED(stat)){ 78 | if(bab==addresses.size()){ 79 | break; 80 | } 81 | unsigned int old=0; 82 | struct user_pt_regiz regs; 83 | struct iovec io; 84 | io.iov_base = ®s; 85 | io.iov_len = sizeof(regs); 86 | /*//idk why this doesnt work but ok. 87 | auto data = ptrace(PTRACE_PEEKDATA,addr,addresses[bab],nullptr); 88 | old = data; 89 | if(arch == ARM){ 90 | data = brk; 91 | } 92 | ptrace(PTRACE_POKEDATA,addr,addresses[bab],data); 93 | */ 94 | //data = ptrace(PTRACE_PEEKDATA,addr,addresses[bab],nullptr); 95 | //printf("\nDATA:%x",data); 96 | if(ptrace(PTRACE_GETREGSET,addr,(void*)NT_PRSTATUS,(void*)&io)==-1){ 97 | printf("\nbad request."); 98 | exit(1); 99 | } 100 | save_register_data(regs,bab); 101 | ptrace(PTRACE_PEEKDATA,addr,addresses[bab],old); 102 | ptrace(PTRACE_SINGLESTEP,addr,0,0); 103 | wait(&stat); 104 | bab++; 105 | } 106 | } 107 | void start_debug(){ 108 | pid_t pid = fork(); 109 | address=pid; 110 | if(pid ==0 ){ 111 | personality(ADDR_NO_RANDOMIZE); 112 | printf("*** donna started process with pid:%d \n",getpid()); 113 | ptrace(PTRACE_TRACEME,0,0,NULL); 114 | execl(filename.c_str(),("./"+filename).c_str(),NULL); 115 | // exit(1); 116 | } 117 | else{ 118 | cycle_through_instructions(pid); 119 | printf("*** donna's register catching done.\n"); 120 | } 121 | 122 | } 123 | 124 | 125 | }; 126 | 127 | 128 | //testing purpouses 129 | void donna_main(string filename,string bf){ 130 | //cout<> instr = bank->banker_load_file(filename); 133 | string decompiled; 134 | stringstream ss; 135 | //decompiling actual file and saving the addresses for later use (debugging) 136 | vector address_savings; 137 | for(int i =0 ;iopcode_decode(hex); 141 | ss.clear(); 142 | string address; 143 | char a[64]; 144 | sprintf(a,"%x",addr); 145 | address=a; 146 | address ="0x"+address+":\t"+res; 147 | decompiled+=address+"\n"; 148 | address_savings.push_back(addr); 149 | } 150 | 151 | if(bank->debug){ 152 | printf("*** saving decompiled data to 'data' folder.\n"); 153 | } 154 | 155 | ofstream str("./data/decompiled"+filename+".dn"); 156 | str<start_debug(); 160 | //ok at this point, we god decompiled binary, we got register data. lets see where these instructions are located in the actual file. this will be done in python 161 | //c++ stuff done for now .great , atleast for basic arm binaries ( current goal ) 162 | } 163 | int main(int argc,char *argv[]){ 164 | //printf("*** donna v4.0 , completely rewritten. works ok with small binaries. do not try anything fancy here."); 165 | if(argc< 2){ 166 | printf("*** donna debugger v4.0\n\tprovide filename of executable\n\tprovide bank file for architecture (example. arm64.bank)\n"); 167 | exit(1); 168 | } 169 | string filename =argv[1]; 170 | string arch = argv[2]; 171 | donna_main(filename,arch); 172 | } 173 | 174 | -------------------------------------------------------------------------------- /web/templates/index.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | donna 8 | 122 | 123 | 124 | 125 |
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143 | 144 | 145 | 255 | 256 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Creative Commons Legal Code 2 | 3 | CC0 1.0 Universal 4 | 5 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 6 | LEGAL SERVICES. DISTRIBUTION OF THIS DOCUMENT DOES NOT CREATE AN 7 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 8 | INFORMATION ON AN "AS-IS" BASIS. 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Should any part of the License for any 94 | reason be judged legally invalid or ineffective under applicable law, such 95 | partial invalidity or ineffectiveness shall not invalidate the remainder 96 | of the License, and in such case Affirmer hereby affirms that he or she 97 | will not (i) exercise any of his or her remaining Copyright and Related 98 | Rights in the Work or (ii) assert any associated claims and causes of 99 | action with respect to the Work, in either case contrary to Affirmer's 100 | express Statement of Purpose. 101 | 102 | 4. Limitations and Disclaimers. 103 | 104 | a. No trademark or patent rights held by Affirmer are waived, abandoned, 105 | surrendered, licensed or otherwise affected by this document. 106 | b. Affirmer offers the Work as-is and makes no representations or 107 | warranties of any kind concerning the Work, express, implied, 108 | statutory or otherwise, including without limitation warranties of 109 | title, merchantability, fitness for a particular purpose, non 110 | infringement, or the absence of latent or other defects, accuracy, or 111 | the present or absence of errors, whether or not discoverable, all to 112 | the greatest extent permissible under applicable law. 113 | c. Affirmer disclaims responsibility for clearing rights of other persons 114 | that may apply to the Work or any use thereof, including without 115 | limitation any person's Copyright and Related Rights in the Work. 116 | Further, Affirmer disclaims responsibility for obtaining any necessary 117 | consents, permissions or other rights required for any use of the 118 | Work. 119 | d. Affirmer understands and acknowledges that Creative Commons is not a 120 | party to this document and has no duty or obligation with respect to 121 | this CC0 or use of the Work. 122 | -------------------------------------------------------------------------------- /bank/load_bank.h: -------------------------------------------------------------------------------- 1 | /* 2 | * *part of nitrodegen's god tools for debugging* 3 | * 4 | * donna debugger v4.0 (one that actually works on arm64) 5 | * decompiler header. 6 | * usage:decompiling the binary and returning instructions along with addresses. 7 | * 8 | * (C) Gavrilo Palalic 2022. 9 | */ 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include "osx_elf.h" 24 | #define MADDR 0x1234 25 | using namespace std; 26 | vector split(string str,string del){ 27 | vectordele; 28 | ssize_t beg,pos=0; 29 | while((beg=str.find_first_not_of(del,pos)) != string::npos){ // loop until you find everything that isn't a delimiter , and always set that to be beginning 30 | pos = str.find_first_of(del,pos+1);//position is always the next case of del 31 | 32 | dele.push_back(str.substr(beg,pos-beg)); // and push 33 | } 34 | return dele; 35 | } 36 | 37 | int bin_to_dec(string a){ 38 | 39 | int res=0; 40 | int base =1 ; 41 | for(int i = a.length()-1;i>=0;i--){ 42 | if(a[i] == '1'){ 43 | res+=base; 44 | 45 | } 46 | base=base*2; 47 | 48 | } 49 | return res; 50 | } 51 | class Banker{ 52 | 53 | public: 54 | string bank_file; 55 | int opcode_size; 56 | vectorbank_ocodes; 57 | vectordecoded; 58 | bool debug; 59 | 60 | //this is where we load the actual instruction bank, split all lines and insert into new vector. 61 | Banker(string filename,bool de){ 62 | bank_file=filename; 63 | debug = de; 64 | if(debug){ 65 | printf("\n*** loading bank:%s",bank_file.c_str()); 66 | } 67 | ifstream stream(bank_file); 68 | stringstream ss; 69 | 70 | ss<results; 103 | 104 | for(int i =2;i1){ 107 | vectorspt = split(g,"-"); 108 | 109 | string tmplt = spt[0]; 110 | string blob; 111 | for(int j =0;j= occurance_op4 && found_5 >= occurance_op5 && found_6 >= occurance_op6 && found_1 >= occurance_op1 && found_3>=occurance_op3){ 173 | return g; 174 | } 175 | } 176 | 177 | 178 | } 179 | } 180 | 181 | return "NULL"; 182 | } 183 | char define_oprand(string oprand){ 184 | char result; 185 | //took from binutils 186 | if(oprand != "EXCEPTION" && oprand.size() == 2 ){ 187 | result=oprand[1]; 188 | 189 | } 190 | else{ 191 | 192 | if(oprand.find("ADDR") != string::npos && oprand != "ADDR_SIMM9" && oprand != "ADDR_SIMPLE"){ 193 | result='i'; 194 | } 195 | else if(oprand == "ADDR_PCREL19"){ 196 | result='i'; 197 | } 198 | else if(oprand == "IMMR"){ 199 | result='i'; 200 | } 201 | else if(oprand == "IMMS"){ 202 | result='i'; 203 | } 204 | else if(oprand == "CCMP_IMM" || oprand == "NZCV" || oprand=="COND"){ 205 | result='c'; 206 | } 207 | else if(oprand == "UIMM3_OP2" ){ 208 | result='o'; 209 | } 210 | else if(oprand == "HALF"){ 211 | result='i'; 212 | } 213 | else if(oprand == "ADDR_SIMM7"){ 214 | result='t'; 215 | } 216 | else if(oprand =="AIMM"){ 217 | result='i'; 218 | } 219 | if(oprand == "EXCEPTION"){ 220 | result='i'; 221 | } 222 | else if(oprand == "Rd_SP"){ 223 | result='d'; 224 | } 225 | else if(oprand == "Rn_SP" || oprand == "Rm_EXT"){ 226 | result='n'; 227 | } 228 | 229 | }//TODO: FIGURE OUT WHY ARE THERE DIFFERENT LETTERS TO THIS! 230 | return result; 231 | } 232 | string opcode_decode(int number){ 233 | string res = bitset<32>(number).to_string(); 234 | if(debug){ 235 | cout<<"\nbinary :"<result; 238 | string op1,op2; 239 | for(int i =0;i<4;i++){ 240 | op1+=res[i]; 241 | } 242 | for(int i =4;i<8;i++){ 243 | op2+=res[i]; 244 | } 245 | string op3; 246 | for(int i =8;i<12;i++){ 247 | op3+=res[i]; 248 | } 249 | 250 | string op4; 251 | for(int i =28;i<32;i++){ 252 | op4+=res[i]; 253 | } 254 | 255 | string op5; 256 | for(int i =20;i<24;i++){ 257 | op5+=res[i]; 258 | } 259 | string op6; 260 | for(int i =24;i<28;i++){ 261 | op6+=res[i]; 262 | } 263 | 264 | string blob=search_for_instruction(op1,op2,op3,op4,op5,op6); 265 | if(blob== "NULL"){ 266 | return ""; 267 | printf("\ncannot decode instruction."); 268 | //exit(1); 269 | } 270 | 271 | 272 | if(debug){ 273 | cout<<"*** binary:"<popit = split(blob,"-"); 278 | 279 | string scheme = popit[0]; 280 | string he; 281 | for(int j=0;jinstr_package; 289 | 290 | vectorextension = split(popit[1]," "); 291 | vectorlook_for; 292 | extension.erase(extension.begin()); 293 | if(debug){ 294 | cout<<"extension size:"<>n; 319 | 320 | if(look_for[i] == 'd' || look_for[i] =='t' || look_for[i] == 'n'){ 321 | if(extension[0] != "movw"){ 322 | op = "x"; 323 | } 324 | else{ 325 | op="w"; 326 | } 327 | } 328 | 329 | else{ 330 | op="#"; 331 | } 332 | op = op+n; 333 | instr_package.push_back(op); 334 | 335 | } 336 | string instruction=instr_package[0]+"\t"; 337 | for(int i =1;i >banker_load_file(string f){ 349 | 350 | vector> instructions; 351 | //load ELF file here. 352 | int fd = open(f.c_str(),O_RDONLY); 353 | struct stat st; 354 | fstat(fd,&st); 355 | long size = st.st_size; 356 | 357 | if(debug){ 358 | cout<<"\n*** file size:"<e_ident[4]; 368 | if(arch == 2){ 369 | Elf64_Shdr *shdr = (Elf64_Shdr*)(mb+ehdr->e_shoff); 370 | Elf64_Shdr *shr = &shdr[ehdr->e_shstrndx]; 371 | Elf64_Phdr *phdr = (Elf64_Phdr*)(mb+ehdr->e_phoff); 372 | 373 | const char *const shstrp = (const char*)mb+shr->sh_offset; 374 | for(int i =0;ie_shnum;i++){ 375 | string n = shstrp+shdr[i].sh_name; 376 | cout<<"FUNCTIONS:"<e_shoff); 393 | 394 | Elf32_Shdr *shr = &shdr[ehdr1->e_shstrndx]; 395 | Elf32_Phdr *phdr = (Elf32_Phdr*)(mb+ehdr1->e_phoff); 396 | const char *const shstrp = (const char*)mb+shr->sh_offset; 397 | for(int i =0;ie_shnum;i++){ 398 | string n = shstrp+shdr[i].sh_name; 399 | if(n == ".text"){ 400 | start_of_program=shdr[i].sh_addr; 401 | size_of_executable=shdr[i].sh_size; 402 | break; 403 | } 404 | // } 405 | 406 | } 407 | runtime_addr =phdr[0].p_vaddr; 408 | 409 | } 410 | //how to find this real address in file? actualaddr - runtime address 411 | 412 | //it should always be the first one. lmao. 413 | int actual_entry= start_of_program-runtime_addr; 414 | 415 | if(debug){ 416 | printf("\n***.text entry:0x%lx , runtime address:0x%lx",start_of_program,runtime_addr); 417 | printf("\n*** reading .text entry contents..."); 418 | } 419 | 420 | stringstream ss; 421 | ss.clear(); 422 | int bobi =0; 423 | for(int i =actual_entry;i=i;j--){ 427 | ss.clear(); 428 | char dd[32]; 429 | sprintf(dd,"%x",mb[j]); 430 | 431 | string n; 432 | ss<>n; 434 | if(n.length() == 1){ 435 | n="0"+n; 436 | } 437 | 438 | num+=n; 439 | } 440 | //cout<>kk; 447 | //cout<oprand->opcode 468 | 469 | */ 470 | /****** example usage of load_bank. decoding!*/ 471 | // int main(int argc,char* argv[]){ 472 | /* 473 | 474 | Banker *bank = new Banker("./banks/arm64.bank",false); 475 | vector> instr = bank->banker_load_file("./testing/test_exec"); 476 | for(int i =0;iopcode_decode(exec); 481 | printf("0x%x\t: %s\n",addr,res.c_str()); 482 | } 483 | */ 484 | //} 485 | 486 | -------------------------------------------------------------------------------- /banks/arm64.bank: -------------------------------------------------------------------------------- 1 | arm64: 2 | 32 3 | 1110 1011 000n nnnn dddd dddd ddd1 1111 - cmpx Rd Rn 4 | 1010 1010 000n nnnn xxxx xxxx xxxd dddd - movr Rd Rn 5 | 0010 1010 000n nnnn xxxx xxxx xxxd dddd - movw Rd Rn 6 | xx01 1110 xx1x xxx0 1011 10nn nnnd dddd - abs Sd Sn 7 | xx00 1110 xx1x xxx0 1011 10nn nnnd dddd - abs Vd Vn 8 | x001 1010 000m mmmm xxxx 00nn nnnd dddd - adc Rd Rn Rm 9 | x011 1010 000m mmmm xxxx 00nn nnnd dddd - adcs Rd Rn Rm 10 | x100 1110 xx1m mmmm 0100 00nn nnnd dddd - addhn2 Vd Vn Vm 11 | x000 1110 xx1m mmmm 0100 00nn nnnd dddd - addhn Vd Vn Vm 12 | xxx1 1110 xx11 xxx1 1011 10nn nnnd dddd - addp Sd Vn 13 | xxx0 1110 xx1m mmmm 1011 11nn nnnd dddd - addp Vd Vn Vm 14 | x000 1011 xx0x xxxx xxxx xxnn nnnd dddd - add Rd Rn Rm_SFT 15 | x00x 0001 SSii iiii iiii iinn nnnd dddd - add Rd_SP Rn_SP AIMM 16 | x000 1011 0x1x xxxx xxxx xxnn nnnd dddd - add Rd_SP Rn_SP Rm_EXT 17 | x101 1110 xx1m mmmm x000 01nn nnnd dddd - add Sd Sn Sm 18 | x010 1011 xx0x xxxx xxxx xxnn nnnd dddd - adds Rd Rn Rm_SFT 19 | x01x 0001 SSii iiii iiii iinn nnnd dddd - adds Rd Rn_SP AIMM 20 | x010 1011 0x1x xxxx xxxx xxnn nnnd dddd - adds Rd Rn_SP Rm_EXT 21 | xx00 1110 xx1m mmmm 1000 01nn nnnd dddd - add Vd Vn Vm 22 | xxx0 1110 xx11 xxx1 1011 10nn nnnd dddd - addv Fd Vn 23 | 1iix 0000 iiii iiii iiii iiii iiid dddd - adrp Rd ADDR_ADRP 24 | 0iix 0000 iiii iiii iiii iiii iiid dddd - adr Rd ADDR_PCREL21 25 | xxx0 1110 xx1x 1xxx 0101 10nn nnnd dddd - aesd Vd Vn 26 | xxx0 1110 xx1x 1xx0 0100 10nn nnnd dddd - aese Vd Vn 27 | xxx0 1110 xx1x 1xx0 0111 10nn nnnd dddd - aesimc Vd Vn 28 | xxx0 1110 xx1x 1xx0 0110 10nn nnnd dddd - aesmc Vd Vn 29 | x000 1010 xx0x xxxx xxxx xxnn nnnd dddd - and Rd Rn Rm_SFT 30 | x00x 0010 0Nii iiii iiii iinn nnnd dddd - and Rd_SP Rn LIMM 31 | x11x 0010 0Nii iiii iiii iinn nnnd dddd - ands Rd Rn LIMM 32 | x110 1010 xx0x xxxx xxxx xxnn nnnd dddd - ands Rd Rn Rm_SFT 33 | xx00 1110 001m mmmm 0001 11nn nnnd dddd - and Vd Vn Vm 34 | xxx1 1010 1x0m mmmm xx1x 10nn nnnd dddd - asrv Rd Rn Rm 35 | 000x 01ii iiii iiii iiii iiii iiii iiii - b ADDR_PCREL26 36 | 010x 0100 iiii iiii iiii iiii iiix xxxx - b.c ADDR_PCREL19 37 | xx1x 0011 0xii iiii iiii iinn nnnd dddd - bfm Rd Rn IMMR IMMS 38 | x00x 1010 xx1x xxxx xxxx xxnn nnnd dddd - bic Rd Rn Rm_SFT 39 | x11x 1010 xx1x xxxx xxxx xxnn nnnd dddd - bics Rd Rn Rm_SFT 40 | xx10 1111 xxxx xxxx 0xx1 x1xx xxxd dddd - bic Vd SIMD_IMM_SFT 41 | xx10 1111 xxxx xxxx 10x1 01xx xxxd dddd - bic Vd SIMD_IMM_SFT 42 | xx00 1110 011m mmmm 0001 11nn nnnd dddd - bic Vd Vn Vm 43 | xx10 1110 111m mmmm 0001 11nn nnnd dddd - bif Vd Vn Vm 44 | xx10 1110 101m mmmm 0001 11nn nnnd dddd - bit Vd Vn Vm 45 | 100x 01ii iiii iiii iiii iiii iiii iiii - bl ADDR_PCREL26 46 | x10x 0110 0x1x xxxx xxxx xxnn nnnx xxxx - blr Rn 47 | 110x 0100 xx1i iiii iiii iiii iiix xx00 - brk EXCEPTION 48 | x10x 0110 000x xxxx xxxx xxnn nnnx xxxx - br Rn 49 | xx10 1110 011m mmmm 0001 11nn nnnd dddd - bsl Vd Vn Vm 50 | xx1x 0101 iiii iiii iiii iiii iiit tttt - cbnz Rt ADDR_PCREL19 51 | xx1x 0100 iiii iiii iiii iiii iiit tttt - cbz Rt ADDR_PCREL19 52 | x0x1 1010 0x0i iiii xxxx 10nn nnnx cccc - ccmn Rn CCMP_IMM NZCV COND 53 | x0x1 1010 010m mmmm xxxx 00nn nnnx cccc - ccmn Rn Rm NZCV COND 54 | x1x1 1010 0x0i iiii xxxx 10nn nnnx cccc - ccmp Rn CCMP_IMM NZCV COND 55 | x1x1 1010 010m mmmm xxxx 00nn nnnx cccc - ccmp Rn Rm NZCV COND 56 | x10x 01x1 xxx0 0xxx xxx1 mmmm 010x xxxx - clrex UIMM4 57 | xxx1 1010 x10x xxxx xxx1 01nn nnnd dddd - cls Rd Rn 58 | xx00 1110 xx1x 0xx0 0100 10nn nnnd dddd - cls Vd Vn 59 | xxx1 1010 110x xxxx xxx1 00nn nnnd dddd - clz Rd Rn 60 | xx10 1110 xx1x 0xx0 0100 10nn nnnd dddd - clz Vd Vn 61 | xx01 1110 xx1x xxx0 1001 10nn nnnd dddd - cmeq Sd Sn IMM0 62 | xx11 1110 xx1m mmmm 1000 11nn nnnd dddd - cmeq Sd Sn Sm 63 | xx00 1110 xx1x xxx0 1001 10nn nnnd dddd - cmeq Vd Vn IMM0 64 | xx10 1110 xx1m mmmm 1000 11nn nnnd dddd - cmeq Vd Vn Vm 65 | xx11 1110 xx1x xxxx 1000 10nn nnnd dddd - cmge Sd Sn IMM0 66 | x101 1110 xx1m mmmm x011 11nn nnnd dddd - cmge Sd Sn Sm 67 | xx10 1110 xx1x xxx0 1000 10nn nnnd dddd - cmge Vd Vn IMM0 68 | xx00 1110 xx1m mmmm 0011 11nn nnnd dddd - cmge Vd Vn Vm 69 | x101 1110 xx1x xxxx 1000 10nn nnnd dddd - cmgt Sd Sn IMM0 70 | x101 1110 xx1m mmmm 0x11 01nn nnnd dddd - cmgt Sd Sn Sm 71 | xx00 1110 xx1x xxx0 1000 10nn nnnd dddd - cmgt Vd Vn IMM0 72 | xx00 1110 xx1m mmmm 0011 01nn nnnd dddd - cmgt Vd Vn Vm 73 | xx11 1110 xx1m mmmm 0x11 01nn nnnd dddd - cmhi Sd Sn Sm 74 | xx10 1110 xx1m mmmm 0011 01nn nnnd dddd - cmhi Vd Vn Vm 75 | xx11 1110 xx1m mmmm xx11 11nn nnnd dddd - cmhs Sd Sn Sm 76 | xx10 1110 xx1m mmmm 0011 11nn nnnd dddd - cmhs Vd Vn Vm 77 | xx11 1110 xx1x xxx0 1001 10nn nnnd dddd - cmle Sd Sn IMM0 78 | xx10 1110 xx1x xxx0 1001 10nn nnnd dddd - cmle Vd Vn IMM0 79 | xxx1 1110 xx10 xxx0 1010 10nn nnnd dddd - cmlt Sd Sn IMM0 80 | xxx0 1110 xx10 xxx0 1010 10nn nnnd dddd - cmlt Vd Vn IMM0 81 | x101 1110 xx1m mmmm 1000 11nn nnnd dddd - cmtst Sd Sn Sm 82 | xx00 1110 xx1m mmmm 1000 11nn nnnd dddd - cmtst Vd Vn Vm 83 | xx00 1110 xx1x 0xxx 0101 10nn nnnd dddd - cnt Vd Vn 84 | x0x1 1010 100m mmmm xxxx 00nn nnnd dddd - csel Rd Rn Rm COND 85 | x0x1 1010 x00m mmmm xxxx 01nn nnnd dddd - csinc Rd Rn Rm COND 86 | x1x1 1010 100m mmmm xxxx 00nn nnnd dddd - csinv Rd Rn Rm COND 87 | x1x1 1010 x00m mmmm xxxx 01nn nnnd dddd - csneg Rd Rn Rm COND 88 | 110x 0100 xx1i iiii iiii iiii iiix xx01 - dcps1 EXCEPTION 89 | 110x 0100 xx1i iiii iiii iiii iiix xx10 - dcps2 EXCEPTION 90 | 110x 0100 xx1i iiii iiii iiii iiix xx11 - dcps3 EXCEPTION 91 | x10x 01x1 xxx0 0xxx xxx1 xxxx xx1x xxxx - dmb BARRIER 92 | x10x 0110 1x1x xxxx xxxx xxxx xxxx xxxx - drps 93 | x10x 01x1 xxx0 0xxx xxx1 xxxx x00x xxxx - dsb BARRIER 94 | x1x1 1110 xx0x xxxx xxxx x1nn nnnd dddd - dup Sd En 95 | xx00 1110 xx0x xxxx xxxx 01nn nnnd dddd - dup Vd En 96 | xx00 1110 xx0x xxxx xx00 11nn nnnd dddd - dup Vd Rn 97 | x10x 1010 xx1x xxxx xxxx xxnn nnnd dddd - eon Rd Rn Rm_SFT 98 | x100 1010 xx0x xxxx xxxx xxnn nnnd dddd - eor Rd Rn Rm_SFT 99 | x10x 0010 0Nii iiii iiii iinn nnnd dddd - eor Rd_SP Rn LIMM 100 | xx10 1110 001m mmmm 0001 11nn nnnd dddd - eor Vd Vn Vm 101 | x10x 0110 100x xxxx xxxx xxxx xxxx xxxx - eret 102 | xxxx 0011 1xxm mmmm iiii iinn nnnd dddd - extr Rd Rn Rm IMMS 103 | xx10 1110 xx0m mmmm xiii i0nn nnnd dddd - ext Vd Vn Vm IDX 104 | xx11 1110 xx1m mmmm 1x01 01nn nnnd dddd - fabd Sd Sn Sm 105 | xx10 1110 1x1m mmmm 1101 01nn nnnd dddd - fabd Vd Vn Vm 106 | xxx1 1110 xx1x x000 1100 00nn nnnd dddd - fabs Fd Fn 107 | xx0x 1110 xx10 xxx0 1111 10nn nnnd dddd - fabs Vd Vn 108 | xx11 1110 0x1m mmmm x110 11nn nnnd dddd - facge Sd Sn Sm 109 | xxx0 1110 0x1m mmmm 1110 11nn nnnd dddd - facge Vd Vn Vm 110 | xx11 1110 1x1m mmmm x110 11nn nnnd dddd - facgt Sd Sn Sm 111 | xxx0 1110 1x1m mmmm 1110 11nn nnnd dddd - facgt Vd Vn Vm 112 | x001 1110 xx1m mmmm 0010 10nn nnnd dddd - fadd Fd Fn Fm 113 | xxxx 1110 xx11 xxx0 1101 10nn nnnd dddd - faddp Sd Vn 114 | xx10 1110 0x1m mmmm 1101 01nn nnnd dddd - faddp Vd Vn Vm 115 | xx00 1110 0x1m mmmm 1101 01nn nnnd dddd - fadd Vd Vn Vm 116 | x001 1110 xx1m mmmm xxxx 01nn nnn1 cccc - fccmpe Fn Fm NZCV COND 117 | x001 1110 xx1m mmmm xxxx 01nn nnn0 cccc - fccmp Fn Fm NZCV COND 118 | xx01 1110 xx10 xxx0 1101 10nn nnnd dddd - fcmeq Sd Sn IMM0 119 | x101 1110 xx1m mmmm xx10 01nn nnnd dddd - fcmeq Sd Sn Sm 120 | xx00 1110 xx10 xxx0 1101 10nn nnnd dddd - fcmeq Vd Vn IMM0 121 | xx00 1110 0x1m mmmm 1110 01nn nnnd dddd - fcmeq Vd Vn Vm 122 | xx11 1110 xx10 xxx0 1100 10nn nnnd dddd - fcmge Sd Sn IMM0 123 | xx11 1110 0x1m mmmm xx10 01nn nnnd dddd - fcmge Sd Sn Sm 124 | xx10 1110 xx10 xxx0 1100 10nn nnnd dddd - fcmge Vd Vn IMM0 125 | xx10 1110 0x1m mmmm 1110 01nn nnnd dddd - fcmge Vd Vn Vm 126 | xx01 1110 xx10 xxx0 1100 10nn nnnd dddd - fcmgt Sd Sn IMM0 127 | xx11 1110 1x1m mmmm xx10 01nn nnnd dddd - fcmgt Sd Sn Sm 128 | xx00 1110 xx10 xxx0 1100 10nn nnnd dddd - fcmgt Vd Vn IMM0 129 | xxx0 1110 1x1m mmmm 1110 01nn nnnd dddd - fcmgt Vd Vn Vm 130 | xx11 1110 xx10 xxx0 1101 10nn nnnd dddd - fcmle Sd Sn IMM0 131 | xx10 1110 xx10 xxx0 1101 10nn nnnd dddd - fcmle Vd Vn IMM0 132 | xxx1 1110 xx1x xxxx 1110 10nn nnnd dddd - fcmlt Sd Sn IMM0 133 | xxx0 1110 xx1x xxxx 1110 10nn nnnd dddd - fcmlt Vd Vn IMM0 134 | xxx1 1110 xx1m mmmm 0010 00nn nnn1 0xxx - fcmpe Fn Fm 135 | xxx1 1110 xx1x xxxx 0010 00nn nnn1 1xxx - fcmpe Fn FPIMM0 136 | xxx1 1110 xx1m mmmm 0010 00nn nnn0 0xxx - fcmp Fn Fm 137 | xxx1 1110 xx1x xxxx 0010 00nn nnn0 1xxx - fcmp Fn FPIMM0 138 | x001 1110 xx1m mmmm xxxx 11nn nnnd dddd - fcsel Fd Fn Fm COND 139 | xxx1 1110 xx1x x100 0000 00nn nnnd dddd - fcvtas Rd Fn 140 | xx01 1110 0x1x xxx1 1100 10nn nnnd dddd - fcvtas Sd Sn 141 | xx00 1110 0x1x xxx1 1100 10nn nnnd dddd - fcvtas Vd Vn 142 | xxx1 1110 xx1x x101 0000 00nn nnnd dddd - fcvtau Rd Fn 143 | xx11 1110 0x1x xxx1 1100 10nn nnnd dddd - fcvtau Sd Sn 144 | xx10 1110 0x1x xxx1 1100 10nn nnnd dddd - fcvtau Vd Vn 145 | xxx1 1110 xx1x x01x x100 00nn nnnd dddd - fcvt Fd Fn 146 | x1x0 1110 xx1x xxx1 0111 10nn nnnd dddd - fcvtl2 Vd Vn 147 | x0x0 1110 xx1x xxx1 0111 10nn nnnd dddd - fcvtl Vd Vn 148 | xxx1 1110 xx11 0000 0000 00nn nnnd dddd - fcvtms Rd Fn 149 | xx01 1110 0x10 xxx1 1011 10nn nnnd dddd - fcvtms Sd Sn 150 | xx00 1110 0x10 xxx1 1011 10nn nnnd dddd - fcvtms Vd Vn 151 | xxx1 1110 xx11 0001 0000 00nn nnnd dddd - fcvtmu Rd Fn 152 | xx11 1110 0x10 xxx1 1011 10nn nnnd dddd - fcvtmu Sd Sn 153 | xx10 1110 0x10 xxx1 1011 10nn nnnd dddd - fcvtmu Vd Vn 154 | x100 1110 xx1x xxx1 0110 10nn nnnd dddd - fcvtn2 Vd Vn 155 | xxx1 1110 xx10 0000 0000 00nn nnnd dddd - fcvtns Rd Fn 156 | xx01 1110 0x10 xxx1 1010 10nn nnnd dddd - fcvtns Sd Sn 157 | xx00 1110 0x10 xxx1 1010 10nn nnnd dddd - fcvtns Vd Vn 158 | xxx1 1110 xx10 0001 0000 00nn nnnd dddd - fcvtnu Rd Fn 159 | xx11 1110 0x10 xxx1 1010 10nn nnnd dddd - fcvtnu Sd Sn 160 | xx10 1110 0x10 xxx1 1010 10nn nnnd dddd - fcvtnu Vd Vn 161 | x000 1110 xx1x xxx1 0110 10nn nnnd dddd - fcvtn Vd Vn 162 | xxx1 1110 xx10 1000 0000 00nn nnnd dddd - fcvtps Rd Fn 163 | xx01 1110 1x10 xxx1 1010 10nn nnnd dddd - fcvtps Sd Sn 164 | xx00 1110 1x10 xxx1 1010 10nn nnnd dddd - fcvtps Vd Vn 165 | xxx1 1110 xx10 1001 0000 00nn nnnd dddd - fcvtpu Rd Fn 166 | xx11 1110 1x10 xxx1 1010 10nn nnnd dddd - fcvtpu Sd Sn 167 | xx10 1110 1x10 xxx1 1010 10nn nnnd dddd - fcvtpu Vd Vn 168 | x110 1110 xx1x xxx1 0110 10nn nnnd dddd - fcvtxn2 Vd Vn 169 | xx11 1110 xx1x xxxx 0110 10nn nnnd dddd - fcvtxn Sd Sn 170 | x010 1110 xx1x xxx1 0110 10nn nnnd dddd - fcvtxn Vd Vn 171 | xxx1 1110 xx11 1000 0000 00nn nnnd dddd - fcvtzs Rd Fn 172 | x0x1 1110 xx0x xx00 SSSS SSnn nnnd dddd - fcvtzs Rd Fn FBITS 173 | xx01 1110 1x10 xxx1 1011 10nn nnnd dddd - fcvtzs Sd Sn 174 | x101 1111 xxxx xxxx 1x1x 11nn nnnd dddd - fcvtzs Sd Sn IMM_VLSR 175 | xx00 1110 1x10 xxx1 1011 10nn nnnd dddd - fcvtzs Vd Vn 176 | xx00 1111 xxxx xxxx 1x11 11nn nnnd dddd - fcvtzs Vd Vn IMM_VLSR 177 | xxx1 1110 xx11 1001 0000 00nn nnnd dddd - fcvtzu Rd Fn 178 | x0x1 1110 xx0x xx01 SSSS SSnn nnnd dddd - fcvtzu Rd Fn FBITS 179 | xx11 1110 1x10 xxx1 1011 10nn nnnd dddd - fcvtzu Sd Sn 180 | xx11 1111 xxxx xxxx 1x11 11nn nnnd dddd - fcvtzu Sd Sn IMM_VLSR 181 | xx10 1110 1x10 xxx1 1011 10nn nnnd dddd - fcvtzu Vd Vn 182 | xx10 1111 xxxx xxxx 1x11 11nn nnnd dddd - fcvtzu Vd Vn IMM_VLSR 183 | x0x1 1110 xx1m mmmm 0001 10nn nnnd dddd - fdiv Fd Fn Fm 184 | xx10 1110 0x1m mmmm 1111 11nn nnnd dddd - fdiv Vd Vn Vm 185 | x001 1111 xx0m mmmm 0aaa aann nnnd dddd - fmadd Fd Fn Fm Fa 186 | x001 1110 xx1m mmmm 0100 10nn nnnd dddd - fmax Fd Fn Fm 187 | xx01 1110 xx1m mmmm 0110 10nn nnnd dddd - fmaxnm Fd Fn Fm 188 | xxx1 1110 0x11 xxx0 1100 10nn nnnd dddd - fmaxnmp Sd Vn 189 | xx10 1110 0x1m mmmm 1100 01nn nnnd dddd - fmaxnmp Vd Vn Vm 190 | xx00 1110 0x1m mmmm 1100 01nn nnnd dddd - fmaxnm Vd Vn Vm 191 | xxx0 1110 0x11 xxx0 1100 10nn nnnd dddd - fmaxnmv Fd Vn 192 | xxx1 1110 0x11 xxx0 1111 10nn nnnd dddd - fmaxp Sd Vn 193 | xx10 1110 0x1m mmmm 1111 01nn nnnd dddd - fmaxp Vd Vn Vm 194 | xx00 1110 0x1m mmmm 1111 01nn nnnd dddd - fmax Vd Vn Vm 195 | xxx0 1110 0x11 xxx0 1111 10nn nnnd dddd - fmaxv Fd Vn 196 | xxx1 1110 xx1m mmmm 0101 10nn nnnd dddd - fmin Fd Fn Fm 197 | x001 1110 xx1m mmmm 0111 10nn nnnd dddd - fminnm Fd Fn Fm 198 | xxx1 1110 1x11 xxx0 1100 10nn nnnd dddd - fminnmp Sd Vn 199 | xx10 1110 1x1m mmmm 1100 01nn nnnd dddd - fminnmp Vd Vn Vm 200 | xx00 1110 1x1m mmmm 1100 01nn nnnd dddd - fminnm Vd Vn Vm 201 | xxx0 1110 1x11 xxx0 1100 10nn nnnd dddd - fminnmv Fd Vn 202 | xxx1 1110 1x11 xxx0 1111 10nn nnnd dddd - fminp Sd Vn 203 | xx10 1110 1x1m mmmm 1111 01nn nnnd dddd - fminp Vd Vn Vm 204 | xx00 1110 1x1m mmmm 1111 01nn nnnd dddd - fmin Vd Vn Vm 205 | xxx0 1110 1x11 xxx0 1111 10nn nnnd dddd - fminv Fd Vn 206 | x101 1111 xxxm mmmm 000x x0nn nnnd dddd - fmla Sd Sn Em 207 | xxx0 1111 xxxm mmmm 0001 x0nn nnnd dddd - fmla Vd Vn Em 208 | xxx0 1110 0x1m mmmm 1100 11nn nnnd dddd - fmla Vd Vn Vm 209 | x101 1111 xxxm mmmm 010x x0nn nnnd dddd - fmls Sd Sn Em 210 | xxx0 1111 xxxm mmmm 0101 x0nn nnnd dddd - fmls Vd Vn Em 211 | xxx0 1110 1x1m mmmm 1100 11nn nnnd dddd - fmls Vd Vn Vm 212 | xxx1 1110 xx1x x000 0100 00nn nnnd dddd - fmov Fd Fn 213 | x0x1 1110 xx1i iiii iii1 00xx xxxd dddd - fmov Fd FPIMM 214 | xxx1 1110 xx1x 0111 0000 00nn nnnd dddd - fmov Fd Rn 215 | xxx1 1110 xx1x 0110 0000 00nn nnnd dddd - fmov Rd Fn 216 | xxx1 1110 xx1x 1110 0000 00nn nnnd dddd - fmov Rd VnD1 217 | xxx1 1110 xx1x 1111 0000 00nn nnnd dddd - fmov VdD1 Rn 218 | xx00 1111 xxxx xxxx 1111 01xx xxxd dddd - fmov Vd SIMD_FPIMM 219 | xx10 1111 xxxx xxxx 1111 01xx xxxd dddd - fmov Vd SIMD_FPIMM 220 | x001 1111 xx0m mmmm 1aaa aann nnnd dddd - fmsub Fd Fn Fm Fa 221 | x0x1 1110 xx1m mmmm 0000 10nn nnnd dddd - fmul Fd Fn Fm 222 | x101 1111 xxxm mmmm 1001 x0nn nnnd dddd - fmul Sd Sn Em 223 | xx00 1111 xxxm mmmm 1001 x0nn nnnd dddd - fmul Vd Vn Em 224 | xx10 1110 xx1m mmmm 1101 11nn nnnd dddd - fmul Vd Vn Vm 225 | xx11 1111 xxxm mmmm 1xxx x0nn nnnd dddd - fmulx Sd Sn Em 226 | x101 1110 xx1m mmmm 1x01 11nn nnnd dddd - fmulx Sd Sn Sm 227 | xx10 1111 xxxm mmmm 1001 x0nn nnnd dddd - fmulx Vd Vn Em 228 | xx00 1110 xx1m mmmm 1101 11nn nnnd dddd - fmulx Vd Vn Vm 229 | xxx1 1110 xx1x x001 0100 00nn nnnd dddd - fneg Fd Fn 230 | xx1x 1110 xx10 xxx0 1111 10nn nnnd dddd - fneg Vd Vn 231 | x001 1111 xx1m mmmm 0aaa aann nnnd dddd - fnmadd Fd Fn Fm Fa 232 | x001 1111 xx1m mmmm 1aaa aann nnnd dddd - fnmsub Fd Fn Fm Fa 233 | x001 1110 xx1m mmmm 1000 10nn nnnd dddd - fnmul Fd Fn Fm 234 | xx01 1110 1x1x xxx1 1101 10nn nnnd dddd - frecpe Sd Sn 235 | xx00 1110 1x1x xxx1 1101 10nn nnnd dddd - frecpe Vd Vn 236 | x101 1110 0x1m mmmm x111 11nn nnnd dddd - frecps Sd Sn Sm 237 | xx00 1110 0x1m mmmm 1111 11nn nnnd dddd - frecps Vd Vn Vm 238 | xxx1 1110 xx1x xxx1 1111 10nn nnnd dddd - frecpx Sd Sn 239 | xxx1 1110 xx1x x110 0100 00nn nnnd dddd - frinta Fd Fn 240 | xx10 1110 0x1x xxx1 1000 10nn nnnd dddd - frinta Vd Vn 241 | xxx1 1110 xx1x x11x 1100 00nn nnnd dddd - frinti Fd Fn 242 | xx1x 1110 1x1x xxx1 1001 10nn nnnd dddd - frinti Vd Vn 243 | xxx1 1110 xx1x x101 0100 00nn nnnd dddd - frintm Fd Fn 244 | xx0x 1110 0x1x xxx1 1001 10nn nnnd dddd - frintm Vd Vn 245 | xxx1 1110 xx1x x100 0100 00nn nnnd dddd - frintn Fd Fn 246 | xx00 1110 0x1x xxx1 1000 10nn nnnd dddd - frintn Vd Vn 247 | xxx1 1110 xx1x x100 1100 00nn nnnd dddd - frintp Fd Fn 248 | xxx0 1110 1x1x xxx1 1000 10nn nnnd dddd - frintp Vd Vn 249 | xxx1 1110 xx1x x111 0100 00nn nnnd dddd - frintx Fd Fn 250 | xx1x 1110 0x1x xxx1 1001 10nn nnnd dddd - frintx Vd Vn 251 | xxx1 1110 xx1x x101 1100 00nn nnnd dddd - frintz Fd Fn 252 | xx0x 1110 1x1x xxx1 1001 10nn nnnd dddd - frintz Vd Vn 253 | xx11 1110 1x1x xxx1 1101 10nn nnnd dddd - frsqrte Sd Sn 254 | xx10 1110 1x1x xxx1 1101 10nn nnnd dddd - frsqrte Vd Vn 255 | x101 1110 1x1m mmmm x111 11nn nnnd dddd - frsqrts Sd Sn Sm 256 | xxx0 1110 1x1m mmmm 1111 11nn nnnd dddd - frsqrts Vd Vn Vm 257 | xxx1 1110 xx1x x001 1100 00nn nnnd dddd - fsqrt Fd Fn 258 | xxx0 1110 xx1x xxx1 1111 10nn nnnd dddd - fsqrt Vd Vn 259 | x001 1110 xx1m mmmm 0011 10nn nnnd dddd - fsub Fd Fn Fm 260 | xx00 1110 1x1m mmmm 1101 01nn nnnd dddd - fsub Vd Vn Vm 261 | x10x 01x1 xxx0 0xxx xx10 mmmm ooox xxxx - hint UIMM7 262 | 110x 0100 xx0i iiii iiii iiii iiix xx00 - hlt EXCEPTION 263 | 110x 0100 xx0i iiii iiii iiii iiix xx10 - hvc EXCEPTION 264 | xx10 1110 xx0x xxxx xxxx x1nn nnnd dddd - ins Ed En 265 | xx00 1110 xx0x xxxx xx01 11nn nnnd dddd - ins Ed Rn 266 | x10x 01x1 xxx0 0xxx xxx1 xxxx 110x xxxx - isb BARRIER_ISB 267 | xx00 1101 110x xxxx xx0x xxxx xxxx xxxx - ld1 LEt SIMD_ADDR_POST 268 | xx00 1101 010x xxxx xx0x xxxx xxxx xxxx - ld1 LEt SIMD_ADDR_SIMPLE 269 | xx00 110x 111x xxxx xx0x xxxx xxxx xxxx - ld2 LEt SIMD_ADDR_POST 270 | xx00 1101 011x xxxx xx0x xxxx xxxx xxxx - ld2 LEt SIMD_ADDR_SIMPLE 271 | xx00 1101 110x xxxx xx1x xxxx xxxx xxxx - ld3 LEt SIMD_ADDR_POST 272 | xx00 1101 010x xxxx xx1x xxxx xxxx xxxx - ld3 LEt SIMD_ADDR_SIMPLE 273 | xx00 110x 111x xxxx xx1x xxxx xxxx xxxx - ld4 LEt SIMD_ADDR_POST 274 | xx00 1101 011x xxxx xx1x xxxx xxxx xxxx - ld4 LEt SIMD_ADDR_SIMPLE 275 | xx00 1100 110x xxxx xxxx xxxx xxxx xxxx - ld4 LVt SIMD_ADDR_POST 276 | xx00 1100 01xx xxxx xxxx xxxx xxxx xxxx - ld4 LVt SIMD_ADDR_SIMPLE 277 | 0000 100x 11xx xxxx xxxx xxxx xxxt tttt - ldarb Rt ADDR_SIMPLE 278 | 0100 100x 11xx xxxx xxxx xxxx xxxt tttt - ldarh Rt ADDR_SIMPLE 279 | 1x00 100x 11xx xxxx xxxx xxxx xxxt tttt - ldar Rt ADDR_SIMPLE 280 | xx00 100x 011x xxxx 1ttt ttxx xxxt tttt - ldaxp Rt Rt2 ADDR_SIMPLE 281 | 0000 100x 010x xxxx 1xxx xxxx xxxt tttt - ldaxrb Rt ADDR_SIMPLE 282 | 0100 100x 010x xxxx 1xxx xxxx xxxt tttt - ldaxrh Rt ADDR_SIMPLE 283 | 1x00 100x 010x xxxx 1xxx xxxx xxxt tttt - ldaxr Rt ADDR_SIMPLE 284 | xx10 110I 01ii iiii ittt ttxx xxxt tttt - ldnp Ft Ft2 ADDR_SIMM7 285 | x010 100I 01ii iiii ittt ttxx xxxt tttt - ldnp Rt Rt2 ADDR_SIMM7 286 | xx10 110I 01ii iiii ittt ttxx xxxt tttt - ldp Ft Ft2 ADDR_SIMM7 287 | xx10 110I 11ii iiii ittt ttxx xxxt tttt - ldp Ft Ft2 ADDR_SIMM7 288 | x010 100I 11ii iiii ittt ttxx xxxt tttt - ldp Rt Rt2 ADDR_SIMM7 289 | x110 100I 01ii iiii ittt ttxx xxxt tttt - ldpsw Rt Rt2 ADDR_SIMM7 290 | x110 100I 11ii iiii ittt ttxx xxxt tttt - ldpsw Rt Rt2 ADDR_SIMM7 291 | 0011 1000 011x xxxx xxxx 10xx xxxt tttt - ldrb Rt ADDR_REGOFF 292 | 0011 1000 01xi iiii iiii I1xx xxxt tttt - ldrb Rt ADDR_SIMM9 293 | 00x1 1001 01ii iiii iiii iinn nnnt tttt - ldrb Rt ADDR_UIMM12 294 | xx01 1100 iiii iiii iiii iiii iiit tttt - ldr Ft ADDR_PCREL19 295 | xx11 1100 x1xx xxxx xxxx 10xx xxxt tttt - ldr Ft ADDR_REGOFF 296 | xx11 1100 x1xi iiii iiii I1xx xxxt tttt - ldr Ft ADDR_SIMM9 297 | xxx1 1101 x1ii iiii iiii iinn nnnt tttt - ldr Ft ADDR_UIMM12 298 | 0111 1000 011x xxxx xxxx 10xx xxxt tttt - ldrh Rt ADDR_REGOFF 299 | 0111 1000 01xi iiii iiii I1xx xxxt tttt - ldrh Rt ADDR_SIMM9 300 | 01x1 1001 01ii iiii iiii iinn nnnt tttt - ldrh Rt ADDR_UIMM12 301 | 0x01 1000 iiii iiii iiii iiii iiit tttt - ldr Rt ADDR_PCREL19 302 | 1x11 1000 011x xxxx xxxx 10xx xxxt tttt - ldr Rt ADDR_REGOFF 303 | 1x11 1000 01xi iiii iiii I1xx xxxt tttt - ldr Rt ADDR_SIMM9 304 | 1xx1 1001 01ii iiii iiii iinn nnnt tttt - ldr Rt ADDR_UIMM12 305 | 0011 1000 1x1x xxxx xxxx 10xx xxxt tttt - ldrsb Rt ADDR_REGOFF 306 | 0011 1000 1xxi iiii iiii I1xx xxxt tttt - ldrsb Rt ADDR_SIMM9 307 | 00x1 1001 1xii iiii iiii iinn nnnt tttt - ldrsb Rt ADDR_UIMM12 308 | 0111 1000 1x1x xxxx xxxx 10xx xxxt tttt - ldrsh Rt ADDR_REGOFF 309 | x111 1000 1xxi iiii iiii I1xx xxxt tttt - ldrsh Rt ADDR_SIMM9 310 | 01x1 1001 1xii iiii iiii iinn nnnt tttt - ldrsh Rt ADDR_UIMM12 311 | 1001 1000 iiii iiii iiii iiii iiit tttt - ldrsw Rt ADDR_PCREL19 312 | 1011 1000 1x1x xxxx xxxx 10xx xxxt tttt - ldrsw Rt ADDR_REGOFF 313 | 1011 1000 1xxi iiii iiii I1xx xxxt tttt - ldrsw Rt ADDR_SIMM9 314 | 10x1 1001 1xii iiii iiii iinn nnnt tttt - ldrsw Rt ADDR_UIMM12 315 | 0011 1000 010i iiii iiii I0xx xxxt tttt - ldtrb Rt ADDR_SIMM9 316 | 0111 1000 010i iiii iiii I0xx xxxt tttt - ldtrh Rt ADDR_SIMM9 317 | 1x11 1000 010i iiii iiii I0xx xxxt tttt - ldtr Rt ADDR_SIMM9 318 | 0011 1000 1x0i iiii iiii I0xx xxxt tttt - ldtrsb Rt ADDR_SIMM9 319 | x111 1000 1x0i iiii iiii I0xx xxxt tttt - ldtrsh Rt ADDR_SIMM9 320 | 1011 1000 1x0i iiii iiii I0xx xxxt tttt - ldtrsw Rt ADDR_SIMM9 321 | 0011 1000 01xi iiii iiii I0xx xxxt tttt - ldurb Rt ADDR_SIMM9 322 | xx11 1100 x1xi iiii iiii I0xx xxxt tttt - ldur Ft ADDR_SIMM9 323 | 0111 1000 01xi iiii iiii I0xx xxxt tttt - ldurh Rt ADDR_SIMM9 324 | 1x11 1000 01xi iiii iiii I0xx xxxt tttt - ldur Rt ADDR_SIMM9 325 | 0011 1000 1xxi iiii iiii I0xx xxxt tttt - ldursb Rt ADDR_SIMM9 326 | 0111 1000 1xxi iiii iiii I0xx xxxt tttt - ldursh Rt ADDR_SIMM9 327 | 1011 1000 1xxi iiii iiii I0xx xxxt tttt - ldursw Rt ADDR_SIMM9 328 | xx00 100x 011x xxxx 0ttt ttxx xxxt tttt - ldxp Rt Rt2 ADDR_SIMPLE 329 | 0000 100x 010x xxxx 0xxx xxxx xxxt tttt - ldxrb Rt ADDR_SIMPLE 330 | 0100 100x 010x xxxx 0xxx xxxx xxxt tttt - ldxrh Rt ADDR_SIMPLE 331 | 1x00 100x 010x xxxx 0xxx xxxx xxxt tttt - ldxr Rt ADDR_SIMPLE 332 | xxx1 1010 110m mmmm xx10 00nn nnnd dddd - lslv Rd Rn Rm 333 | xxx1 1010 x10m mmmm xx10 01nn nnnd dddd - lsrv Rd Rn Rm 334 | xxx1 1011 x00m mmmm 0aaa aann nnnd dddd - madd Rd Rn Rm Ra 335 | xxx0 1111 xxxm mmmm 0000 x0nn nnnd dddd - mla Vd Vn Em 336 | xx00 1110 xx1m mmmm 1001 01nn nnnd dddd - mla Vd Vn Vm 337 | xxx0 1111 xxxm mmmm 0100 x0nn nnnd dddd - mls Vd Vn Em 338 | xx10 1110 xx1m mmmm 1001 01nn nnnd dddd - mls Vd Vn Vm 339 | xx10 1111 xxxx xxxx 1110 01xx xxxd dddd - movi Sd SIMD_IMM 340 | xx00 1111 xxxx xxxx 1110 01xx xxxd dddd - movi Vd SIMD_IMM 341 | xx00 1111 xxxx xxxx 0xx0 x1xx xxxd dddd - movi Vd SIMD_IMM_SFT 342 | xx00 1111 xxxx xxxx 10x0 01xx xxxd dddd - movi Vd SIMD_IMM_SFT 343 | xx00 1111 xxxx xxxx 110x 01xx xxxd dddd - movi Vd SIMD_IMM_SFT 344 | xx1x 0010 1xxi iiii iiii iiii iiid dddd - movk Rd HALF 345 | x00x 0010 1xxi iiii iiii iiii iiid dddd - movn Rd HALF 346 | x10x 0010 1xxi iiii iiii iiii iiid dddd - movz Rd HALF 347 | x10x 01x1 xx11 xxxx xxxx xxxx xxxt tttt - mrs Rt SYSREG 348 | x10x 01x1 xxx0 0xxx xx00 mmmm xxxx xxxx - msr PSTATEFIELD UIMM4 349 | x10x 01x1 xx01 xxxx xxxx xxxx xxxt tttt - msr SYSREG Rt 350 | xxx1 1011 xx0m mmmm 1aaa aann nnnd dddd - msub Rd Rn Rm Ra 351 | xxx0 1111 xxxm mmmm 1000 x0nn nnnd dddd - mul Vd Vn Em 352 | xx00 1110 xx1m mmmm 1001 11nn nnnd dddd - mul Vd Vn Vm 353 | xx10 1111 xxxx xxxx 0xx0 x1xx xxxd dddd - mvni Vd SIMD_IMM_SFT 354 | xx10 1111 xxxx xxxx 10x0 01xx xxxd dddd - mvni Vd SIMD_IMM_SFT 355 | xx10 1111 xxxx xxxx 110x 01xx xxxd dddd - mvni Vd SIMD_IMM_SFT 356 | xx11 1110 xx1x xxx0 1011 10nn nnnd dddd - neg Sd Sn 357 | xx10 1110 xx1x xxx0 1011 10nn nnnd dddd - neg Vd Vn 358 | xx10 1110 x01x 0xxx 0101 10nn nnnd dddd - not Vd Vn 359 | x01x 1010 xx1x xxxx xxxx xxnn nnnd dddd - orn Rd Rn Rm_SFT 360 | xx00 1110 111m mmmm 0001 11nn nnnd dddd - orn Vd Vn Vm 361 | x010 1010 xx0x xxxx xxxx xxnn nnnd dddd - orr Rd Rn Rm_SFT 362 | x01x 0010 0Nii iiii iiii iinn nnnd dddd - orr Rd_SP Rn LIMM 363 | xx00 1111 xxxx xxxx 0xx1 x1xx xxxd dddd - orr Vd SIMD_IMM_SFT 364 | xx00 1111 xxxx xxxx 10x1 01xx xxxd dddd - orr Vd SIMD_IMM_SFT 365 | xx00 1110 101m mmmm 0001 11nn nnnd dddd - orr Vd Vn Vm 366 | x1xx 1110 x01m mmmm 1110 00nn nnnd dddd - pmull2 Vd Vn Vm 367 | x1xx 1110 x11m mmmm 1110 00nn nnnd dddd - pmull2 Vd Vn Vm 368 | x0xx 1110 x01m mmmm 1110 00nn nnnd dddd - pmull Vd Vn Vm 369 | x0xx 1110 x11m mmmm 1110 00nn nnnd dddd - pmull Vd Vn Vm 370 | xx10 1110 xx1m mmmm 1001 11nn nnnd dddd - pmul Vd Vn Vm 371 | 1101 1000 iiii iiii iiii iiii iiix xxxx - prfm PRFOP ADDR_PCREL19 372 | 1111 1000 1x1x xxxx xxxx 10xx xxxx xxxx - prfm PRFOP ADDR_REGOFF 373 | 11x1 1001 1xii iiii iiii iinn nnnx xxxx - prfm PRFOP ADDR_UIMM12 374 | 1111 1000 1xxi iiii iiii I0xx xxxx xxxx - prfum PRFOP ADDR_SIMM9 375 | x110 1110 xx1m mmmm 0100 00nn nnnd dddd - raddhn2 Vd Vn Vm 376 | x010 1110 xx1m mmmm 0100 00nn nnnd dddd - raddhn Vd Vn Vm 377 | xxx1 1010 110x xxxx xx00 00nn nnnd dddd - rbit Rd Rn 378 | xx10 1110 x11x 0xxx 0101 10nn nnnd dddd - rbit Vd Vn 379 | x10x 0110 x10x xxxx xxxx xxnn nnnx xxxx - ret Rn 380 | xxx1 1010 x10x xxxx xx00 01nn nnnd dddd - rev16 Rd Rn 381 | xxx0 1110 xx1x xxxx 0001 10nn nnnd dddd - rev16 Vd Vn 382 | 11x1 1010 1x0x xxxx xx0x 10nn nnnd dddd - rev32 Rd Rn 383 | xx10 1110 xx1x xxxx 0000 10nn nnnd dddd - rev32 Vd Vn 384 | xx00 1110 xx1x xxxx 0000 10nn nnnd dddd - rev64 Vd Vn 385 | 01x1 1010 1x0x xxxx xx0x 10nn nnnd dddd - rev Rd Rn 386 | x1x1 1010 xx0x xxxx xx0x 11nn nnnd dddd - rev Rd Rn 387 | xxx1 1010 xx0m mmmm xx1x 11nn nnnd dddd - rorv Rd Rn Rm 388 | x100 1111 xxxx xxxx 1xx0 11nn nnnd dddd - rshrn2 Vd Vn IMM_VLSR 389 | x000 1111 xxxx xxxx 1xx0 11nn nnnd dddd - rshrn Vd Vn IMM_VLSR 390 | x11x 1110 xx1m mmmm 0110 00nn nnnd dddd - rsubhn2 Vd Vn Vm 391 | x01x 1110 xx1m mmmm 0110 00nn nnnd dddd - rsubhn Vd Vn Vm 392 | x100 1110 xx1m mmmm 0101 00nn nnnd dddd - sabal2 Vd Vn Vm 393 | x000 1110 xx1m mmmm 0101 00nn nnnd dddd - sabal Vd Vn Vm 394 | xx00 1110 xx1m mmmm 0111 11nn nnnd dddd - saba Vd Vn Vm 395 | x100 1110 xx1m mmmm x111 00nn nnnd dddd - sabdl2 Vd Vn Vm 396 | x000 1110 xx1m mmmm x111 00nn nnnd dddd - sabdl Vd Vn Vm 397 | xx00 1110 xx1m mmmm 0111 01nn nnnd dddd - sabd Vd Vn Vm 398 | xx00 1110 xx1x 0xx0 0110 10nn nnnd dddd - sadalp Vd Vn 399 | x100 1110 xx1m mmmm 0000 00nn nnnd dddd - saddl2 Vd Vn Vm 400 | xx00 1110 xx1x xxx0 0010 10nn nnnd dddd - saddlp Vd Vn 401 | x000 1110 xx1m mmmm 0000 00nn nnnd dddd - saddl Vd Vn Vm 402 | xx00 1110 xx11 xxx0 0011 10nn nnnd dddd - saddlv Fd Vn 403 | x100 1110 xx1m mmmm 0001 00nn nnnd dddd - saddw2 Vd Vn Vm 404 | x000 1110 xx1m mmmm 0001 00nn nnnd dddd - saddw Vd Vn Vm 405 | x101 1010 000m mmmm xxxx 00nn nnnd dddd - sbc Rd Rn Rm 406 | x111 1010 000m mmmm xxxx 00nn nnnd dddd - sbcs Rd Rn Rm 407 | x00x 0011 0xii iiii iiii iinn nnnd dddd - sbfm Rd Rn IMMR IMMS 408 | xxx1 1110 xx1x x010 0000 00nn nnnd dddd - scvtf Fd Rn 409 | x0x1 1110 xx0x xx10 SSSS SSnn nnnd dddd - scvtf Fd Rn FBITS 410 | xx01 1110 0x1x xxx1 1101 10nn nnnd dddd - scvtf Sd Sn 411 | x101 1111 xxxx xxxx 1xx0 01nn nnnd dddd - scvtf Sd Sn IMM_VLSR 412 | xx00 1110 0x1x xxx1 1101 10nn nnnd dddd - scvtf Vd Vn 413 | x0x1 1010 xx0m mmmm xx0x 11nn nnnd dddd - sdiv Rd Rn Rm 414 | x1x1 1110 xx0m mmmm x000 x0nn nnnd dddd - sha1c Fd Fn Vm 415 | x1x1 1110 xx1x xxxx 0000 10nn nnnd dddd - sha1h Fd Fn 416 | x1x1 1110 xx0m mmmm x010 x0nn nnnd dddd - sha1m Fd Fn Vm 417 | x1x1 1110 xx0m mmmm x001 x0nn nnnd dddd - sha1p Fd Fn Vm 418 | x1x1 1110 xx0m mmmm xx11 x0nn nnnd dddd - sha1su0 Vd Vn Vm 419 | x1x1 1110 xx1x xxxx 0001 10nn nnnd dddd - sha1su1 Vd Vn 420 | x1x1 1110 xx0m mmmm x101 x0nn nnnd dddd - sha256h2 Fd Fn Vm 421 | x1x1 1110 xx0m mmmm x100 x0nn nnnd dddd - sha256h Fd Fn Vm 422 | x101 1110 xx1x xxxx 0010 10nn nnnd dddd - sha256su0 Vd Vn 423 | x1x1 1110 xx0m mmmm x110 x0nn nnnd dddd - sha256su1 Vd Vn Vm 424 | xx00 1110 xx1m mmmm 0000 01nn nnnd dddd - shadd Vd Vn Vm 425 | x1x0 1110 xx1x xxx1 0011 10nn nnnd dddd - shll2 Vd Vn SHLL_IMM 426 | x0x0 1110 xx1x xxx1 0011 10nn nnnd dddd - shll Vd Vn SHLL_IMM 427 | x101 1111 xxxx xxxx 0101 x1nn nnnd dddd - shl Sd Sn IMM_VLSL 428 | xx00 1110 xx1m mmmm 0010 01nn nnnd dddd - shsub Vd Vn Vm 429 | xx11 1111 xxxx xxxx 0101 xxnn nnnd dddd - sli Sd Sn IMM_VLSL 430 | xxx1 1011 0x1m mmmm 0aaa aann nnnd dddd - smaddl Rd Rn Rm Ra 431 | xx00 1110 xx1m mmmm 1010 01nn nnnd dddd - smaxp Vd Vn Vm 432 | xx00 1110 xx1m mmmm 0110 01nn nnnd dddd - smax Vd Vn Vm 433 | xx0x 1110 xx11 xxx0 1010 10nn nnnd dddd - smaxv Fd Vn 434 | 110x 0100 xx0i iiii iiii iiii iiix xx11 - smc EXCEPTION 435 | xx00 1110 xx1m mmmm 1010 11nn nnnd dddd - sminp Vd Vn Vm 436 | xx00 1110 xx1m mmmm 0110 11nn nnnd dddd - smin Vd Vn Vm 437 | xx0x 1110 xx11 xxx1 1010 10nn nnnd dddd - sminv Fd Vn 438 | x100 1111 xxxm mmmm 0010 x0nn nnnd dddd - smlal2 Vd Vn Em 439 | x10x 1110 xx1m mmmm 1000 00nn nnnd dddd - smlal2 Vd Vn Vm 440 | x000 1111 xxxm mmmm 0010 x0nn nnnd dddd - smlal Vd Vn Em 441 | x00x 1110 xx1m mmmm 1000 00nn nnnd dddd - smlal Vd Vn Vm 442 | x100 1111 xxxm mmmm 0110 x0nn nnnd dddd - smlsl2 Vd Vn Em 443 | x10x 1110 xx1m mmmm 1010 00nn nnnd dddd - smlsl2 Vd Vn Vm 444 | x000 1111 xxxm mmmm 0110 x0nn nnnd dddd - smlsl Vd Vn Em 445 | x00x 1110 xx1m mmmm 1010 00nn nnnd dddd - smlsl Vd Vn Vm 446 | xx00 1110 xx0x xxxx xx10 11nn nnnd dddd - smov Rd En 447 | xxx1 1011 0x1m mmmm 1aaa aann nnnd dddd - smsubl Rd Rn Rm Ra 448 | xxx1 1011 010m mmmm 0xxx xxnn nnnd dddd - smulh Rd Rn Rm 449 | x100 1111 xxxm mmmm 1x10 x0nn nnnd dddd - smull2 Vd Vn Em 450 | x100 1110 xx1m mmmm 1100 00nn nnnd dddd - smull2 Vd Vn Vm 451 | x000 1111 xxxm mmmm 1x10 x0nn nnnd dddd - smull Vd Vn Em 452 | x000 1110 xx1m mmmm 1100 00nn nnnd dddd - smull Vd Vn Vm 453 | x101 1110 xx1x xxxx 0111 10nn nnnd dddd - sqabs Sd Sn 454 | xx00 1110 xx1x 0xx0 0111 10nn nnnd dddd - sqabs Vd Vn 455 | x101 1110 xx1m mmmm 0000 11nn nnnd dddd - sqadd Sd Sn Sm 456 | xx00 1110 xx1m mmmm 0000 11nn nnnd dddd - sqadd Vd Vn Vm 457 | x1x0 1111 xxxm mmmm 0011 x0nn nnnd dddd - sqdmlal2 Vd Vn Em 458 | x1x0 1110 xx1m mmmm 1001 00nn nnnd dddd - sqdmlal2 Vd Vn Vm 459 | x101 1111 xxxm mmmm 001x x0nn nnnd dddd - sqdmlal Sd Sn Em 460 | x1x1 1110 xx1m mmmm x001 00nn nnnd dddd - sqdmlal Sd Sn Sm 461 | x0x0 1111 xxxm mmmm 0011 x0nn nnnd dddd - sqdmlal Vd Vn Em 462 | x0x0 1110 xx1m mmmm 1001 00nn nnnd dddd - sqdmlal Vd Vn Vm 463 | x1x0 1111 xxxm mmmm 0111 x0nn nnnd dddd - sqdmlsl2 Vd Vn Em 464 | x1x0 1110 xx1m mmmm 1011 00nn nnnd dddd - sqdmlsl2 Vd Vn Vm 465 | x101 1111 xxxm mmmm 011x x0nn nnnd dddd - sqdmlsl Sd Sn Em 466 | x1x1 1110 xx1m mmmm xx11 00nn nnnd dddd - sqdmlsl Sd Sn Sm 467 | x0x0 1111 xxxm mmmm 0111 x0nn nnnd dddd - sqdmlsl Vd Vn Em 468 | x0x0 1110 xx1m mmmm 1011 00nn nnnd dddd - sqdmlsl Vd Vn Vm 469 | x101 1111 xxxm mmmm 1xx0 x0nn nnnd dddd - sqdmulh Sd Sn Em 470 | x101 1110 xx1m mmmm 1x11 01nn nnnd dddd - sqdmulh Sd Sn Sm 471 | xxx0 1111 xxxm mmmm 1100 x0nn nnnd dddd - sqdmulh Vd Vn Em 472 | xx00 1110 xx1m mmmm 1011 01nn nnnd dddd - sqdmulh Vd Vn Vm 473 | x1x0 1111 xxxm mmmm 1x11 x0nn nnnd dddd - sqdmull2 Vd Vn Em 474 | x1x0 1110 xx1m mmmm 1101 00nn nnnd dddd - sqdmull2 Vd Vn Vm 475 | x101 1111 xxxm mmmm 1x11 x0nn nnnd dddd - sqdmull Sd Sn Em 476 | x1x1 1110 xx1m mmmm x101 00nn nnnd dddd - sqdmull Sd Sn Sm 477 | x0x0 1111 xxxm mmmm 1x11 x0nn nnnd dddd - sqdmull Vd Vn Em 478 | x0x0 1110 xx1m mmmm 1101 00nn nnnd dddd - sqdmull Vd Vn Vm 479 | xx11 1110 xx1x xxxx 0111 10nn nnnd dddd - sqneg Sd Sn 480 | xx10 1110 xx1x 0xx0 0111 10nn nnnd dddd - sqneg Vd Vn 481 | x101 1111 xxxm mmmm 1101 x0nn nnnd dddd - sqrdmulh Sd Sn Em 482 | xx11 1110 xx1m mmmm 1x11 01nn nnnd dddd - sqrdmulh Sd Sn Sm 483 | xxx0 1111 xxxm mmmm 1101 x0nn nnnd dddd - sqrdmulh Vd Vn Em 484 | xx10 1110 xx1m mmmm 1011 01nn nnnd dddd - sqrdmulh Vd Vn Vm 485 | x101 1110 xx1m mmmm 0x01 11nn nnnd dddd - sqrshl Sd Sn Sm 486 | xx00 1110 xx1m mmmm 0101 11nn nnnd dddd - sqrshl Vd Vn Vm 487 | x100 1111 xxxx xxxx 1x01 11nn nnnd dddd - sqrshrn2 Vd Vn IMM_VLSR 488 | x101 1111 xxxx xxxx 1x0x 11nn nnnd dddd - sqrshrn Sd Sn IMM_VLSR 489 | x000 1111 xxxx xxxx 1x01 11nn nnnd dddd - sqrshrn Vd Vn IMM_VLSR 490 | x110 1111 xxxx xxxx 1xx0 11nn nnnd dddd - sqrshrun2 Vd Vn IMM_VLSR 491 | xx11 1111 xxxx xxxx 1xx0 11nn nnnd dddd - sqrshrun Sd Sn IMM_VLSR 492 | x010 1111 xxxx xxxx 1xx0 11nn nnnd dddd - sqrshrun Vd Vn IMM_VLSR 493 | x101 1111 xxxx xxxx 0111 x1nn nnnd dddd - sqshl Sd Sn IMM_VLSL 494 | x101 1110 xx1m mmmm x100 11nn nnnd dddd - sqshl Sd Sn Sm 495 | xx11 1111 xxxx xxxx 0110 xxnn nnnd dddd - sqshlu Sd Sn IMM_VLSL 496 | xx00 1110 xx1m mmmm 0100 11nn nnnd dddd - sqshl Vd Vn Vm 497 | x101 1111 xxxx xxxx 1xx1 01nn nnnd dddd - sqshrn Sd Sn IMM_VLSR 498 | xx11 1111 xxxx xxxx 1x00 01nn nnnd dddd - sqshrun Sd Sn IMM_VLSR 499 | x101 1110 xx1m mmmm xx10 11nn nnnd dddd - sqsub Sd Sn Sm 500 | xx00 1110 xx1m mmmm 0010 11nn nnnd dddd - sqsub Vd Vn Vm 501 | x100 1110 xx1x xxx1 0100 10nn nnnd dddd - sqxtn2 Vd Vn 502 | x101 1110 xx1x xxxx 0100 10nn nnnd dddd - sqxtn Sd Sn 503 | x000 1110 xx1x xxx1 0100 10nn nnnd dddd - sqxtn Vd Vn 504 | x110 1110 xx1x xxx1 0010 10nn nnnd dddd - sqxtun2 Vd Vn 505 | xx11 1110 xx1x xxxx 0010 10nn nnnd dddd - sqxtun Sd Sn 506 | x010 1110 xx1x xxx1 0010 10nn nnnd dddd - sqxtun Vd Vn 507 | xx00 1110 xx1m mmmm 0001 01nn nnnd dddd - srhadd Vd Vn Vm 508 | xx11 1111 xxxx xxxx 0100 xxnn nnnd dddd - sri Sd Sn IMM_VLSR 509 | x101 1110 xx1m mmmm xx01 01nn nnnd dddd - srshl Sd Sn Sm 510 | xx00 1110 xx1m mmmm 0101 01nn nnnd dddd - srshl Vd Vn Vm 511 | x101 1111 xxxx xxxx 0x10 x1nn nnnd dddd - srshr Sd Sn IMM_VLSR 512 | x101 1111 xxxx xxxx 0011 x1nn nnnd dddd - srsra Sd Sn IMM_VLSR 513 | x101 1110 xx1m mmmm x100 01nn nnnd dddd - sshl Sd Sn Sm 514 | xx00 1110 xx1m mmmm 0100 01nn nnnd dddd - sshl Vd Vn Vm 515 | x101 1111 xxxx xxxx 0x00 x1nn nnnd dddd - sshr Sd Sn IMM_VLSR 516 | x101 1111 xxxx xxxx 0001 x1nn nnnd dddd - ssra Sd Sn IMM_VLSR 517 | x100 1110 xx1m mmmm 0010 00nn nnnd dddd - ssubl2 Vd Vn Vm 518 | x000 1110 xx1m mmmm 0010 00nn nnnd dddd - ssubl Vd Vn Vm 519 | x100 1110 xx1m mmmm 0011 00nn nnnd dddd - ssubw2 Vd Vn Vm 520 | x000 1110 xx1m mmmm 0011 00nn nnnd dddd - ssubw Vd Vn Vm 521 | xx00 1101 100x xxxx xx0x xxxx xxxx xxxx - st1 LEt SIMD_ADDR_POST 522 | xx00 1101 000x xxxx xx0x xxxx xxxx xxxx - st1 LEt SIMD_ADDR_SIMPLE 523 | xx00 110x 101x xxxx xx0x xxxx xxxx xxxx - st2 LEt SIMD_ADDR_POST 524 | xx00 1101 001x xxxx xx0x xxxx xxxx xxxx - st2 LEt SIMD_ADDR_SIMPLE 525 | xx00 1101 100x xxxx xx1x xxxx xxxx xxxx - st3 LEt SIMD_ADDR_POST 526 | xx00 1101 000x xxxx xx1x xxxx xxxx xxxx - st3 LEt SIMD_ADDR_SIMPLE 527 | xx00 110x 101x xxxx xx1x xxxx xxxx xxxx - st4 LEt SIMD_ADDR_POST 528 | xx00 1101 001x xxxx xx1x xxxx xxxx xxxx - st4 LEt SIMD_ADDR_SIMPLE 529 | xx00 1100 100x xxxx xxxx xxxx xxxx xxxx - st4 LVt SIMD_ADDR_POST 530 | xx00 1100 00xx xxxx xxxx xxxx xxxx xxxx - st4 LVt SIMD_ADDR_SIMPLE 531 | 0000 100x 10xx xxxx xxxx xxxx xxxt tttt - stlrb Rt ADDR_SIMPLE 532 | 0100 100x 10xx xxxx xxxx xxxx xxxt tttt - stlrh Rt ADDR_SIMPLE 533 | 1x00 100x 10xx xxxx xxxx xxxx xxxt tttt - stlr Rt ADDR_SIMPLE 534 | xx00 100x 001s ssss 1ttt ttxx xxxt tttt - stlxp Rs Rt Rt2 ADDR_SIMPLE 535 | 0000 100x 000s ssss 1xxx xxxx xxxt tttt - stlxrb Rs Rt ADDR_SIMPLE 536 | 0100 100x 000s ssss 1xxx xxxx xxxt tttt - stlxrh Rs Rt ADDR_SIMPLE 537 | 1x00 100x 000s ssss 1xxx xxxx xxxt tttt - stlxr Rs Rt ADDR_SIMPLE 538 | xx10 110I 00ii iiii ittt ttxx xxxt tttt - stnp Ft Ft2 ADDR_SIMM7 539 | xx10 100I 00ii iiii ittt ttxx xxxt tttt - stnp Rt Rt2 ADDR_SIMM7 540 | xx10 110I 00ii iiii ittt ttxx xxxt tttt - stp Ft Ft2 ADDR_SIMM7 541 | xx10 110I 10ii iiii ittt ttxx xxxt tttt - stp Ft Ft2 ADDR_SIMM7 542 | xx10 100I 10ii iiii ittt ttxx xxxt tttt - stp Rt Rt2 ADDR_SIMM7 543 | 0011 1000 001x xxxx xxxx 10xx xxxt tttt - strb Rt ADDR_REGOFF 544 | 0011 1000 00xi iiii iiii I1xx xxxt tttt - strb Rt ADDR_SIMM9 545 | 00x1 1001 00ii iiii iiii iinn nnnt tttt - strb Rt ADDR_UIMM12 546 | xx11 1100 x0xx xxxx xxxx 10xx xxxt tttt - str Ft ADDR_REGOFF 547 | xx11 1100 x0xi iiii iiii I1xx xxxt tttt - str Ft ADDR_SIMM9 548 | xxx1 1101 x0ii iiii iiii iinn nnnt tttt - str Ft ADDR_UIMM12 549 | 0111 1000 001x xxxx xxxx 10xx xxxt tttt - strh Rt ADDR_REGOFF 550 | 0111 1000 00xi iiii iiii I1xx xxxt tttt - strh Rt ADDR_SIMM9 551 | 01x1 1001 00ii iiii iiii iinn nnnt tttt - strh Rt ADDR_UIMM12 552 | 1x11 1000 001x xxxx xxxx 10xx xxxt tttt - str Rt ADDR_REGOFF 553 | 1x11 1000 00xi iiii iiii I1xx xxxt tttt - str Rt ADDR_SIMM9 554 | 1xx1 1001 00ii iiii iiii iinn nnnt tttt - str Rt ADDR_UIMM12 555 | 0011 1000 000i iiii iiii I0xx xxxt tttt - sttrb Rt ADDR_SIMM9 556 | 0111 1000 000i iiii iiii I0xx xxxt tttt - sttrh Rt ADDR_SIMM9 557 | 1x11 1000 000i iiii iiii I0xx xxxt tttt - sttr Rt ADDR_SIMM9 558 | 0011 1000 00xi iiii iiii I0xx xxxt tttt - sturb Rt ADDR_SIMM9 559 | xx11 1100 x0xi iiii iiii I0xx xxxt tttt - stur Ft ADDR_SIMM9 560 | 0111 1000 00xi iiii iiii I0xx xxxt tttt - sturh Rt ADDR_SIMM9 561 | 1x11 1000 00xi iiii iiii I0xx xxxt tttt - stur Rt ADDR_SIMM9 562 | xx00 100x 001s ssss 0ttt ttxx xxxt tttt - stxp Rs Rt Rt2 ADDR_SIMPLE 563 | 0000 100x 000s ssss 0xxx xxxx xxxt tttt - stxrb Rs Rt ADDR_SIMPLE 564 | 0100 100x 000s ssss 0xxx xxxx xxxt tttt - stxrh Rs Rt ADDR_SIMPLE 565 | 1x00 100x 000s ssss 0xxx xxxx xxxt tttt - stxr Rs Rt ADDR_SIMPLE 566 | x10x 1110 xx1m mmmm 0110 00nn nnnd dddd - subhn2 Vd Vn Vm 567 | x00x 1110 xx1m mmmm 0110 00nn nnnd dddd - subhn Vd Vn Vm 568 | x100 1011 xx0x xxxx xxxx xxnn nnnd dddd - sub Rd Rn Rm_SFT 569 | x10x 0001 SSii iiii iiii iinn nnnd dddd - sub Rd_SP Rn_SP AIMM 570 | x100 1011 0x1x xxxx xxxx xxnn nnnd dddd - sub Rd_SP Rn_SP Rm_EXT 571 | xx11 1110 xx1m mmmm x000 01nn nnnd dddd - sub Sd Sn Sm 572 | x110 1011 xx0x xxxx xxxx xxnn nnnd dddd - subs Rd Rn Rm_SFT 573 | x11x 0001 SSii iiii iiii iinn nnnd dddd - subs Rd Rn_SP AIMM 574 | x110 1011 0x1x xxxx xxxx xxnn nnnd dddd - subs Rd Rn_SP Rm_EXT 575 | xx10 1110 xx1m mmmm 1000 01nn nnnd dddd - sub Vd Vn Vm 576 | x101 1110 xx1x xxxx 0011 10nn nnnd dddd - suqadd Sd Sn 577 | xx00 1110 xx10 xxx0 0011 10nn nnnd dddd - suqadd Vd Vn 578 | 110x 0100 xx0i iiii iiii iiii iiix xx01 - svc EXCEPTION 579 | x10x 01x1 xx10 1ooo nnnn mmmm ooot tttt - sysl Rt UIMM3_OP1 Cn Cm UIMM3_OP2 580 | x10x 01x1 xx00 1ooo nnnn mmmm ooot tttt - sys UIMM3_OP1 Cn Cm UIMM3_OP2 Rt 581 | xx00 1110 xx0m mmmm xxx0 00nn nnnd dddd - tbl Vd LVn Vm 582 | bx1x 0111 bbbb biii iiii iiii iiit tttt - tbnz Rt BIT_NUM ADDR_PCREL14 583 | xx00 1110 xx0m mmmm xxx1 00nn nnnd dddd - tbx Vd LVn Vm 584 | bx1x 0110 bbbb biii iiii iiii iiit tttt - tbz Rt BIT_NUM ADDR_PCREL14 585 | xx00 1110 xx0m mmmm x0x0 10nn nnnd dddd - trn1 Vd Vn Vm 586 | xx00 1110 xx0m mmmm x1x0 10nn nnnd dddd - trn2 Vd Vn Vm 587 | x110 1110 xx1m mmmm 0101 00nn nnnd dddd - uabal2 Vd Vn Vm 588 | x010 1110 xx1m mmmm 0101 00nn nnnd dddd - uabal Vd Vn Vm 589 | xx10 1110 xx1m mmmm 0111 11nn nnnd dddd - uaba Vd Vn Vm 590 | x110 1110 xx1m mmmm x111 00nn nnnd dddd - uabdl2 Vd Vn Vm 591 | x010 1110 xx1m mmmm x111 00nn nnnd dddd - uabdl Vd Vn Vm 592 | xx10 1110 xx1m mmmm 0111 01nn nnnd dddd - uabd Vd Vn Vm 593 | xx10 1110 xx1x 0xx0 0110 10nn nnnd dddd - uadalp Vd Vn 594 | x110 1110 xx1m mmmm 0000 00nn nnnd dddd - uaddl2 Vd Vn Vm 595 | xx10 1110 xx1x xxx0 0010 10nn nnnd dddd - uaddlp Vd Vn 596 | x010 1110 xx1m mmmm 0000 00nn nnnd dddd - uaddl Vd Vn Vm 597 | xx10 1110 xx11 xxx0 0011 10nn nnnd dddd - uaddlv Fd Vn 598 | x110 1110 xx1m mmmm 0001 00nn nnnd dddd - uaddw2 Vd Vn Vm 599 | x010 1110 xx1m mmmm 0001 00nn nnnd dddd - uaddw Vd Vn Vm 600 | x10x 0011 0xii iiii iiii iinn nnnd dddd - ubfm Rd Rn IMMR IMMS 601 | xxx1 1110 xx1x x011 0000 00nn nnnd dddd - ucvtf Fd Rn 602 | x0x1 1110 xx0x xx11 SSSS SSnn nnnd dddd - ucvtf Fd Rn FBITS 603 | xx11 1110 0x1x xxx1 1101 10nn nnnd dddd - ucvtf Sd Sn 604 | xx11 1111 xxxx xxxx 1x10 01nn nnnd dddd - ucvtf Sd Sn IMM_VLSR 605 | xx10 1110 0x1x xxx1 1101 10nn nnnd dddd - ucvtf Vd Vn 606 | x0x1 1010 1x0m mmmm xx0x 10nn nnnd dddd - udiv Rd Rn Rm 607 | xx10 1110 xx1m mmmm 0000 01nn nnnd dddd - uhadd Vd Vn Vm 608 | xx10 1110 xx1m mmmm 0010 01nn nnnd dddd - uhsub Vd Vn Vm 609 | xxxx 1011 1x1m mmmm 0aaa aann nnnd dddd - umaddl Rd Rn Rm Ra 610 | xx10 1110 xx1m mmmm 1010 01nn nnnd dddd - umaxp Vd Vn Vm 611 | xx10 1110 xx1m mmmm 0110 01nn nnnd dddd - umax Vd Vn Vm 612 | xx1x 1110 xx11 xxx0 1010 10nn nnnd dddd - umaxv Fd Vn 613 | xx10 1110 xx1m mmmm 1010 11nn nnnd dddd - uminp Vd Vn Vm 614 | xx10 1110 xx1m mmmm 0110 11nn nnnd dddd - umin Vd Vn Vm 615 | xx1x 1110 xx11 xxx1 1010 10nn nnnd dddd - uminv Fd Vn 616 | x110 1111 xxxm mmmm 0010 x0nn nnnd dddd - umlal2 Vd Vn Em 617 | x11x 1110 xx1m mmmm 1000 00nn nnnd dddd - umlal2 Vd Vn Vm 618 | x010 1111 xxxm mmmm 0010 x0nn nnnd dddd - umlal Vd Vn Em 619 | x01x 1110 xx1m mmmm 1000 00nn nnnd dddd - umlal Vd Vn Vm 620 | x110 1111 xxxm mmmm 0110 x0nn nnnd dddd - umlsl2 Vd Vn Em 621 | x11x 1110 xx1m mmmm 1010 00nn nnnd dddd - umlsl2 Vd Vn Vm 622 | x010 1111 xxxm mmmm 0110 x0nn nnnd dddd - umlsl Vd Vn Em 623 | x01x 1110 xx1m mmmm 1010 00nn nnnd dddd - umlsl Vd Vn Vm 624 | xx00 1110 xx0x xxxx xx11 11nn nnnd dddd - umov Rd En 625 | xxxx 1011 1x1m mmmm 1aaa aann nnnd dddd - umsubl Rd Rn Rm Ra 626 | xxx1 1011 110m mmmm 0xxx xxnn nnnd dddd - umulh Rd Rn Rm 627 | x110 1111 xxxm mmmm 1x10 x0nn nnnd dddd - umull2 Vd Vn Em 628 | x110 1110 xx1m mmmm 1100 00nn nnnd dddd - umull2 Vd Vn Vm 629 | x010 1111 xxxm mmmm 1x10 x0nn nnnd dddd - umull Vd Vn Em 630 | x010 1110 xx1m mmmm 1100 00nn nnnd dddd - umull Vd Vn Vm 631 | xx11 1110 xx1m mmmm 0000 11nn nnnd dddd - uqadd Sd Sn Sm 632 | xx10 1110 xx1m mmmm 0000 11nn nnnd dddd - uqadd Vd Vn Vm 633 | xx11 1110 xx1m mmmm xx01 11nn nnnd dddd - uqrshl Sd Sn Sm 634 | xx10 1110 xx1m mmmm 0101 11nn nnnd dddd - uqrshl Vd Vn Vm 635 | x110 1111 xxxx xxxx 1x01 11nn nnnd dddd - uqrshrn2 Vd Vn IMM_VLSR 636 | xx11 1111 xxxx xxxx 1x01 11nn nnnd dddd - uqrshrn Sd Sn IMM_VLSR 637 | x010 1111 xxxx xxxx 1x01 11nn nnnd dddd - uqrshrn Vd Vn IMM_VLSR 638 | xx11 1111 xxxx xxxx 0111 xxnn nnnd dddd - uqshl Sd Sn IMM_VLSL 639 | xx11 1110 xx1m mmmm x100 11nn nnnd dddd - uqshl Sd Sn Sm 640 | xx10 1110 xx1m mmmm 0100 11nn nnnd dddd - uqshl Vd Vn Vm 641 | xx11 1111 xxxx xxxx 1xx1 01nn nnnd dddd - uqshrn Sd Sn IMM_VLSR 642 | xx11 1110 xx1m mmmm x010 11nn nnnd dddd - uqsub Sd Sn Sm 643 | xx10 1110 xx1m mmmm 0010 11nn nnnd dddd - uqsub Vd Vn Vm 644 | x110 1110 xx1x xxx1 0100 10nn nnnd dddd - uqxtn2 Vd Vn 645 | xx11 1110 xx1x xxxx 0100 10nn nnnd dddd - uqxtn Sd Sn 646 | x010 1110 xx1x xxx1 0100 10nn nnnd dddd - uqxtn Vd Vn 647 | xx0x 1110 1x1x xxx1 1100 10nn nnnd dddd - urecpe Vd Vn 648 | xx10 1110 xx1m mmmm 0001 01nn nnnd dddd - urhadd Vd Vn Vm 649 | xx11 1110 xx1m mmmm 0x01 01nn nnnd dddd - urshl Sd Sn Sm 650 | xx10 1110 xx1m mmmm 0101 01nn nnnd dddd - urshl Vd Vn Vm 651 | xx11 1111 xxxx xxxx 0010 xxnn nnnd dddd - urshr Sd Sn IMM_VLSR 652 | xx1x 1110 1x1x xxx1 1100 10nn nnnd dddd - ursqrte Vd Vn 653 | xx11 1111 xxxx xxxx 0011 xxnn nnnd dddd - ursra Sd Sn IMM_VLSR 654 | xx11 1110 xx1m mmmm x100 01nn nnnd dddd - ushl Sd Sn Sm 655 | xx10 1110 xx1m mmmm 0100 01nn nnnd dddd - ushl Vd Vn Vm 656 | xx11 1111 xxxx xxxx 0000 xxnn nnnd dddd - ushr Sd Sn IMM_VLSR 657 | xx11 1110 xx1x xxxx 0011 10nn nnnd dddd - usqadd Sd Sn 658 | xx10 1110 xx10 xxx0 0011 10nn nnnd dddd - usqadd Vd Vn 659 | xx11 1111 xxxx xxxx 0001 xxnn nnnd dddd - usra Sd Sn IMM_VLSR 660 | x110 1110 xx1m mmmm 0010 00nn nnnd dddd - usubl2 Vd Vn Vm 661 | x010 1110 xx1m mmmm 0010 00nn nnnd dddd - usubl Vd Vn Vm 662 | x110 1110 xx1m mmmm 0011 00nn nnnd dddd - usubw2 Vd Vn Vm 663 | x010 1110 xx1m mmmm 0011 00nn nnnd dddd - usubw Vd Vn Vm 664 | xx00 1110 xx0m mmmm x001 10nn nnnd dddd - uzp1 Vd Vn Vm 665 | xx00 1110 xx0m mmmm x101 10nn nnnd dddd - uzp2 Vd Vn Vm 666 | x100 1110 xx1x xxx1 0010 10nn nnnd dddd - xtn2 Vd Vn 667 | x000 1110 xx1x xxx1 0010 10nn nnnd dddd - xtn Vd Vn 668 | xx00 1110 xx0m mmmm x011 10nn nnnd dddd - zip1 Vd Vn Vm 669 | xx00 1110 xx0m mmmm x111 10nn nnnd dddd - zip2 Vd Vn Vm 670 | 671 | --------------------------------------------------------------------------------