├── LICENSE
├── README.md
├── SvLibDR
    ├── .gitattributes
    ├── README.md
    ├── ReceiverUART
    │   ├── ReceiverUART.sv
    │   ├── RxUART_logic.sv
    │   ├── RxUART_timeout.sv
    │   ├── SingleRxUART.sv
    │   ├── simulate.do
    │   └── tb.sv
    ├── SingleRxUART
    │   ├── SingleRxUART.sv
    │   ├── simulate.do
    │   └── tb.sv
    ├── SingleSPImaster
    │   ├── SingleSPImaster.sv
    │   ├── simulate.do
    │   └── tb.sv
    ├── SingleSPIslave
    │   ├── SingleSPIslave.sv
    │   ├── simulate.do
    │   └── tb.sv
    ├── SingleTxUART
    │   ├── SingleTxUART.sv
    │   ├── simulate.do
    │   └── tb.sv
    └── TransmitterUART
    │   ├── SingleTxUART.sv
    │   ├── TransmitterUART.sv
    │   ├── TxUART_logic.sv
    │   ├── simulate.do
    │   └── tb.sv
├── SystemVerilog-Bitmap-Library-AXI-Image-VIP
    ├── LICENSE
    ├── README.md
    ├── axi_stream_video_image.sv
    ├── axi_stream_video_image_example.sv
    ├── axi_stream_video_image_in_vip.sv
    ├── axi_stream_video_image_out_vip.sv
    └── bitmap_processing.sv
├── basic_verilog
    ├── ActionBurst.v
    ├── ActionBurst2.v
    ├── ActionBurst2_tb.v
    ├── ActionBurst_tb.v
    ├── Advanced Synthesis Cookbook
    │   ├── arbitration
    │   │   ├── arbiter.v
    │   │   ├── arbiter_tb.v
    │   │   ├── bitscan.v
    │   │   ├── bitscan_tb.v
    │   │   ├── log2.inc
    │   │   ├── prio_encode.cpp
    │   │   ├── prio_encode.v
    │   │   ├── tx_4channel_arbiter.v
    │   │   └── tx_4channel_arbiter_tb.sv
    │   ├── arithmetic
    │   │   ├── adder_tree.v
    │   │   ├── adder_tree_layer.v
    │   │   ├── adder_tree_node.v
    │   │   ├── adder_tree_tb.v
    │   │   ├── addsub.v
    │   │   ├── basic_adder.v
    │   │   ├── compress_32.v
    │   │   ├── cordic.v
    │   │   ├── cordic_angle_table.cpp
    │   │   ├── cordic_tb.v
    │   │   ├── divider.v
    │   │   ├── divider_tb.v
    │   │   ├── double_addsub.v
    │   │   ├── double_addsub_tb.v
    │   │   ├── iter_addsub.v
    │   │   ├── karatsuba_mult.v
    │   │   ├── karatsuba_mult_tb.v
    │   │   ├── lc_mult_signed.v
    │   │   ├── lc_mult_signed_tb.v
    │   │   ├── log2.inc
    │   │   ├── make_comp.cpp
    │   │   ├── make_sum.cpp
    │   │   ├── mult_3tick.v
    │   │   ├── mult_shift.v
    │   │   ├── mult_shift_tb.v
    │   │   ├── pipeline_add.v
    │   │   ├── pipeline_add_msb.v
    │   │   ├── pipeline_add_tb.v
    │   │   ├── select_add.v
    │   │   ├── select_add_speed_test.v
    │   │   ├── six_three_comp.v
    │   │   ├── split_add.v
    │   │   ├── sum_of_3bit_pair.v
    │   │   ├── sum_of_64.v
    │   │   ├── ternary_add.v
    │   │   ├── ternary_sum_nine.v
    │   │   ├── thirtysix_six_comp.v
    │   │   ├── three_two_comp.v
    │   │   ├── twelve_four_comp.v
    │   │   └── wide_compress.v
    │   ├── communication
    │   │   ├── decoder_8b10b.v
    │   │   ├── descrambler.v
    │   │   ├── encoder_8b10b.v
    │   │   ├── encoder_tb.v
    │   │   ├── gear_expt.cpp
    │   │   ├── gear_expt2.cpp
    │   │   ├── gearbox_20_22.v
    │   │   ├── gearbox_20_66.v
    │   │   ├── gearbox_20_67.v
    │   │   ├── gearbox_20_67_tb.sv
    │   │   ├── gearbox_32_33.v
    │   │   ├── gearbox_32_66.v
    │   │   ├── gearbox_32_66_tb.sv
    │   │   ├── gearbox_33_32.v
    │   │   ├── gearbox_33_32_tb.sv
    │   │   ├── gearbox_40_66.v
    │   │   ├── gearbox_40_67.v
    │   │   ├── gearbox_40_67_tb.sv
    │   │   ├── gearbox_66_20.v
    │   │   ├── gearbox_66_20_tb.sv
    │   │   ├── gearbox_66_32.v
    │   │   ├── gearbox_66_32_tb.sv
    │   │   ├── gearbox_66_40.v
    │   │   ├── gearbox_66_40_tb.sv
    │   │   ├── gearbox_67_20.v
    │   │   ├── gearbox_67_20_tb.sv
    │   │   ├── gearbox_67_40.v
    │   │   ├── parallax_gps.v
    │   │   ├── scrambler.v
    │   │   ├── scrambler_tb.sv
    │   │   ├── two_to_one.v
    │   │   ├── uart.v
    │   │   ├── uart_hw_test.v
    │   │   ├── uart_tb.v
    │   │   ├── x4_decoder_8b10b.v
    │   │   ├── x4_encoder_8b10b.v
    │   │   └── x4_encoder_tb.sv
    │   ├── compare
    │   │   ├── carry_and.v
    │   │   ├── carry_and_speed_test.v
    │   │   ├── carry_and_tb.v
    │   │   ├── compare_masks.inc
    │   │   ├── compare_tb.v
    │   │   ├── cook.sh
    │   │   ├── equal_const.v
    │   │   ├── equal_const_tb.v
    │   │   ├── highest_10.inc
    │   │   ├── in_range.v
    │   │   ├── in_range_tb.v
    │   │   ├── less_than_const.v
    │   │   ├── log2.inc
    │   │   ├── match_or_inv.v
    │   │   ├── match_or_inv_tb.v
    │   │   ├── min_max.v
    │   │   ├── min_max_tb.v
    │   │   ├── over_under.v
    │   │   ├── pipe_equal.v
    │   │   ├── pipe_equal_tb.v
    │   │   └── tester.cpp
    │   ├── counter
    │   │   ├── cntr.v
    │   │   ├── cntr_modulus.v
    │   │   ├── cntr_modulus_la.v
    │   │   ├── cntr_updn.v
    │   │   ├── counter_tb.v
    │   │   ├── gray_cntr.v
    │   │   ├── gray_cntr_la.v
    │   │   ├── gray_cntr_tb.v
    │   │   ├── seconds_counter.v
    │   │   ├── seconds_counter_tb.v
    │   │   ├── system_timer.v
    │   │   └── system_timer_tb.v
    │   ├── crc
    │   │   ├── crc16_dat16.v
    │   │   ├── crc16_dat24.v
    │   │   ├── crc16_dat32.v
    │   │   ├── crc16_dat8.v
    │   │   ├── crc24_dat64.v
    │   │   ├── crc24_dat64_only_flat.v
    │   │   ├── crc24_zer64_flat.v
    │   │   ├── crc24_zer64x2_flat.v
    │   │   ├── crc24_zer64x3_flat.v
    │   │   ├── crc32_128_tb.v
    │   │   ├── crc32_dat104.v
    │   │   ├── crc32_dat112.v
    │   │   ├── crc32_dat120.v
    │   │   ├── crc32_dat128.v
    │   │   ├── crc32_dat128_any_byte.v
    │   │   ├── crc32_dat16.v
    │   │   ├── crc32_dat24.v
    │   │   ├── crc32_dat32.v
    │   │   ├── crc32_dat32_any_byte.v
    │   │   ├── crc32_dat40.v
    │   │   ├── crc32_dat48.v
    │   │   ├── crc32_dat56.v
    │   │   ├── crc32_dat64.v
    │   │   ├── crc32_dat64_any_byte.v
    │   │   ├── crc32_dat72.v
    │   │   ├── crc32_dat8.v
    │   │   ├── crc32_dat80.v
    │   │   ├── crc32_dat88.v
    │   │   ├── crc32_dat96.v
    │   │   ├── crc32_tb.v
    │   │   ├── crc32c_dat32.v
    │   │   ├── crc32c_dat64.v
    │   │   ├── crc32c_dat64_only.v
    │   │   ├── crc32c_tb.sv
    │   │   ├── crc32c_zer64.v
    │   │   ├── crc_ethernet.v
    │   │   ├── crc_register.v
    │   │   └── xor6.v
    │   ├── crypto
    │   │   ├── aes
    │   │   │   ├── aes_128.cpp
    │   │   │   ├── aes_128.v
    │   │   │   ├── aes_128_tb.v
    │   │   │   ├── aes_256.cpp
    │   │   │   ├── aes_256.v
    │   │   │   ├── aes_256_tb.v
    │   │   │   ├── aes_round_128.v
    │   │   │   ├── aes_round_256.v
    │   │   │   ├── evolve_key.v
    │   │   │   ├── evolve_key_256_tb.v
    │   │   │   ├── mix_columns.v
    │   │   │   ├── shift_rows.cpp
    │   │   │   ├── shift_rows.v
    │   │   │   ├── sub_bytes.cpp
    │   │   │   └── sub_bytes.v
    │   │   ├── des
    │   │   │   ├── des.v
    │   │   │   ├── des_tb.v
    │   │   │   ├── round.v
    │   │   │   ├── sboxes.v
    │   │   │   └── ucrypt.v
    │   │   ├── rc4
    │   │   │   ├── rc4.cpp
    │   │   │   ├── rc4.v
    │   │   │   └── rc4_tb.v
    │   │   └── sha
    │   │   │   ├── delay_reg.v
    │   │   │   ├── delay_reg_tb.v
    │   │   │   ├── log2.inc
    │   │   │   ├── sha384_tb.v
    │   │   │   ├── sha512.v
    │   │   │   ├── sha512_tb.v
    │   │   │   ├── sha_padding.v
    │   │   │   ├── sha_padding_b_tb.v
    │   │   │   ├── sha_padding_c_tb.v
    │   │   │   └── sha_padding_tb.v
    │   ├── debug
    │   │   ├── bin_to_asc_hex.v
    │   │   ├── clock_crossing_fifo.v
    │   │   ├── four_lane_jtag_probe.v
    │   │   ├── frequency_monitor.v
    │   │   ├── jtag_to_c_probe.v
    │   │   ├── log2.inc
    │   │   ├── quad_stream_grabber.v
    │   │   ├── quad_stream_grabber_tb.sv
    │   │   ├── read_c_probe.cpp
    │   │   ├── read_c_probe.h
    │   │   ├── stream_grabber.v
    │   │   ├── stream_grabber_tb.sv
    │   │   ├── stream_mux.v
    │   │   ├── temp_sense.v
    │   │   └── temp_sense_s5.v
    │   ├── ecc
    │   │   ├── ecc_16bit_tb.v
    │   │   ├── ecc_2bit.cpp
    │   │   ├── ecc_2bit.v
    │   │   ├── ecc_2bit_tb.v
    │   │   ├── ecc_32bit_tb.v
    │   │   ├── ecc_64bit_tb.v
    │   │   ├── ecc_8bit_tb.v
    │   │   ├── ecc_generate.cpp
    │   │   ├── ecc_matrix_16bit.v
    │   │   ├── ecc_matrix_32bit.v
    │   │   ├── ecc_matrix_64bit.v
    │   │   ├── ecc_matrix_8bit.v
    │   │   ├── log2.inc
    │   │   ├── ram_block.v
    │   │   ├── ram_speed_test.v
    │   │   ├── reed_sol.cpp
    │   │   ├── reed_sol.v
    │   │   ├── soft_ecc_ram_16bit.v
    │   │   ├── soft_ecc_ram_16bit_tb.v
    │   │   ├── soft_ecc_ram_32bit.v
    │   │   ├── soft_ecc_ram_32bit_tb.v
    │   │   ├── soft_ecc_ram_64bit.v
    │   │   ├── soft_ecc_ram_64bit_tb.v
    │   │   ├── soft_ecc_ram_8bit.v
    │   │   └── xor6.v
    │   ├── ethernet_fec
    │   │   ├── annex74_tb.sv
    │   │   ├── crc_flat.v
    │   │   ├── crc_speed.v
    │   │   ├── fec_check.v
    │   │   ├── fec_gen.v
    │   │   ├── fec_parity.v
    │   │   ├── fec_rot_1.v
    │   │   ├── fec_rot_10.v
    │   │   ├── fec_rot_11.v
    │   │   ├── fec_rot_12.v
    │   │   ├── fec_rot_13.v
    │   │   ├── fec_rot_14.v
    │   │   ├── fec_rot_15.v
    │   │   ├── fec_rot_16.v
    │   │   ├── fec_rot_17.v
    │   │   ├── fec_rot_18.v
    │   │   ├── fec_rot_19.v
    │   │   ├── fec_rot_2.v
    │   │   ├── fec_rot_20.v
    │   │   ├── fec_rot_21.v
    │   │   ├── fec_rot_22.v
    │   │   ├── fec_rot_23.v
    │   │   ├── fec_rot_24.v
    │   │   ├── fec_rot_25.v
    │   │   ├── fec_rot_26.v
    │   │   ├── fec_rot_27.v
    │   │   ├── fec_rot_28.v
    │   │   ├── fec_rot_29.v
    │   │   ├── fec_rot_3.v
    │   │   ├── fec_rot_30.v
    │   │   ├── fec_rot_31.v
    │   │   ├── fec_rot_32.v
    │   │   ├── fec_rot_4.v
    │   │   ├── fec_rot_5.v
    │   │   ├── fec_rot_6.v
    │   │   ├── fec_rot_7.v
    │   │   ├── fec_rot_8.v
    │   │   ├── fec_rot_9.v
    │   │   ├── fec_rot_n2112.v
    │   │   ├── fec_tb.sv
    │   │   ├── pn2112_table.v
    │   │   ├── pn2112_tb.sv
    │   │   └── reverse_32.inc
    │   ├── float
    │   │   ├── approx_fp_div.v
    │   │   ├── approx_fp_div_lut.v
    │   │   ├── approx_fp_div_tb.v
    │   │   ├── approx_fp_invsqrt.v
    │   │   ├── approx_fp_invsqrt_tb.v
    │   │   ├── approx_fp_sqrt.v
    │   │   ├── approx_fp_sqrt_tb.v
    │   │   ├── div_tbl_gen.cpp
    │   │   ├── fixed_to_float.v
    │   │   ├── fixed_to_float_tb.v
    │   │   ├── float_to_fixed.v
    │   │   ├── inv_sqrt.tbl
    │   │   ├── mult_3tick.v
    │   │   ├── scale_up.v
    │   │   └── test_stimulus.cpp
    │   ├── interlaken_lane
    │   │   ├── crc32c_dat64.v
    │   │   ├── crc32c_dat64_only.v
    │   │   ├── crc32c_tb.sv
    │   │   ├── crc32c_zer64.v
    │   │   ├── dec_67_64.v
    │   │   ├── enc_64_67.v
    │   │   ├── frame_sync_control.v
    │   │   ├── gearbox_20_67.v
    │   │   ├── gearbox_20_67_tb.sv
    │   │   ├── gearbox_67_20.v
    │   │   ├── gearbox_67_20_tb.sv
    │   │   ├── lane_bits.txt
    │   │   ├── lane_bits_err.txt
    │   │   ├── lane_rx.v
    │   │   ├── lane_rx_crc.v
    │   │   ├── lane_rx_tb.sv
    │   │   ├── lane_tb.sv
    │   │   ├── lane_tx.v
    │   │   ├── lane_tx_crc.v
    │   │   ├── log2.inc
    │   │   ├── make_lane_traffic.cpp
    │   │   ├── scrambler_lfsr.v
    │   │   ├── scrambler_tb.sv
    │   │   ├── six_three_comp.v
    │   │   ├── sum_of_3bit_pair.v
    │   │   ├── ternary_add.v
    │   │   ├── twelve_four_comp.v
    │   │   ├── word_align_control.v
    │   │   └── xor6.v
    │   ├── muxing
    │   │   ├── barrel_shift.v
    │   │   ├── bus_mux.v
    │   │   ├── eight_to_one.v
    │   │   ├── eight_to_one_tb.v
    │   │   ├── eight_to_twenty.v
    │   │   ├── five_to_twenty.v
    │   │   ├── log2.inc
    │   │   ├── pipelined_word_mux.v
    │   │   ├── pipelined_word_mux_tb.v
    │   │   ├── priority_mux.v
    │   │   ├── priority_mux_tb.v
    │   │   ├── rotate_internal.v
    │   │   ├── shift_tb.v
    │   │   ├── simple_mux.v
    │   │   ├── twenty_to_eight.v
    │   │   ├── twenty_to_eight_tb.sv
    │   │   ├── twenty_to_five.v
    │   │   └── twenty_to_five_tb.sv
    │   ├── random
    │   │   ├── bilbo_lfsr.v
    │   │   ├── bilbo_lfsr_tb.v
    │   │   ├── c_rand.v
    │   │   ├── chain_delay_adjust.v
    │   │   ├── chain_delay_race.v
    │   │   ├── chain_delay_rand.v
    │   │   ├── lfsr.v
    │   │   ├── lfsr_test.v
    │   │   ├── log2.inc
    │   │   ├── make_scrambler.cpp
    │   │   ├── pipelined_word_mux.v
    │   │   ├── rand_test.cpp
    │   │   ├── rand_test.v
    │   │   ├── ring_counter.v
    │   │   ├── unstable_counters.v
    │   │   ├── word_stream_scramble.v
    │   │   └── word_stream_scramble_tb.v
    │   ├── storage
    │   │   ├── buf_2to3.v
    │   │   ├── buf_3to2.v
    │   │   ├── buffer_tb.v
    │   │   ├── cam_ram_block.v
    │   │   ├── cam_ram_block_tb.v
    │   │   ├── fifo.v
    │   │   ├── fifo_hw_test.v
    │   │   ├── fifo_hw_test_tb.v
    │   │   ├── fifo_tb.v
    │   │   ├── flag_array.v
    │   │   ├── gray_to_bin.v
    │   │   ├── insert_parity.v
    │   │   ├── mlab_dcfifo.v
    │   │   ├── mlab_dcfifo_tb.sv
    │   │   ├── mlab_delay.v
    │   │   ├── mlab_delay_tb.sv
    │   │   ├── mlab_fifo_cells.v
    │   │   ├── mlab_sr_cells.v
    │   │   ├── ram_based_cam.v
    │   │   ├── ram_based_cam_tb.v
    │   │   ├── ram_block.v
    │   │   ├── ram_delay_reg.v
    │   │   ├── ram_delay_reg_tb.v
    │   │   ├── random_delay.v
    │   │   ├── ready_skid.v
    │   │   ├── ready_skid_tb.sv
    │   │   ├── reg_based_cam.v
    │   │   ├── reg_based_cam_tb.v
    │   │   ├── reg_cam_cell.v
    │   │   ├── register_bank.v
    │   │   ├── register_bank_tb.v
    │   │   ├── remove_parity.v
    │   │   ├── rx_buffer_fifo_2.v
    │   │   ├── rx_buffer_fifo_2_tb.sv
    │   │   ├── simple_quad.v
    │   │   ├── simple_quad_tb.v
    │   │   ├── test_pattern.v
    │   │   └── tx_buffer_fifo_8word.v
    │   ├── synchronization
    │   │   ├── clock_follow.v
    │   │   ├── clock_mux.v
    │   │   ├── clock_mux_tb.v
    │   │   ├── reset_control.v
    │   │   ├── reset_control_tb.v
    │   │   ├── reset_filter.v
    │   │   └── synchronizer.v
    │   ├── translation
    │   │   ├── asc_hex_to_nybble.v
    │   │   ├── asc_to_7seg.v
    │   │   ├── asc_to_lcd.v
    │   │   ├── bcd_add_chain.v
    │   │   ├── bin_to_7seg.v
    │   │   ├── bin_to_asc_hex.v
    │   │   ├── bin_to_dec.v
    │   │   ├── bin_to_dec_tb.v
    │   │   ├── bin_to_gray.v
    │   │   ├── gray_tb.v
    │   │   ├── gray_to_bin.v
    │   │   ├── log2.inc
    │   │   ├── make_mask.cpp
    │   │   ├── mask_16.v
    │   │   ├── mask_32.v
    │   │   ├── mask_tb.v
    │   │   ├── one_hot.v
    │   │   ├── one_hot_tb.v
    │   │   └── onehot_to_bin.v
    │   ├── utility
    │   │   ├── build_float_vpi.sh
    │   │   ├── clean.sh
    │   │   ├── float_vpi.cpp
    │   │   ├── legal.cpp
    │   │   ├── legal.txt
    │   │   ├── log2.inc
    │   │   ├── make_case_tb.v
    │   │   ├── msim_all.sh
    │   │   ├── quartus_all.sh
    │   │   ├── reverse_32.inc
    │   │   ├── reverse_8.inc
    │   │   ├── txt_to_c.cpp
    │   │   └── vpi_user.h
    │   └── video
    │   │   ├── bmp_to_font.cpp
    │   │   ├── display_char.v
    │   │   ├── display_char_tb.sv
    │   │   ├── double_addsub.v
    │   │   ├── eightbyeight_sad.v
    │   │   ├── eightbyeight_sad_tb.v
    │   │   ├── eightbyeight_sad_test.v
    │   │   ├── font.bmp
    │   │   ├── font_rom.v
    │   │   ├── fourbyfour_sad.v
    │   │   ├── fourbyfour_sad_tb.v
    │   │   ├── frame.bin
    │   │   ├── log2.inc
    │   │   ├── pair_sad.v
    │   │   ├── rgb_to_hue.v
    │   │   ├── rgb_to_hue_tb.v
    │   │   ├── ternary_add.v
    │   │   ├── vga_driver.v
    │   │   ├── ycbcr_to_rgb.v
    │   │   └── ycbcr_to_rgb_tb.v
    ├── KCPSM6_Release9_30Sept14
    │   ├── JTAG_Loader
    │   │   ├── JTAG_Loader_RH_32
    │   │   ├── JTAG_Loader_RH_64
    │   │   ├── JTAG_Loader_Win7_32.exe
    │   │   ├── JTAG_Loader_Win7_64.exe
    │   │   ├── JTAG_Loader_WinXP_32.exe
    │   │   ├── JTAG_Loader_WinXP_64.exe
    │   │   └── msvcr100.dll
    │   ├── KCPSM6_User_Guide_30Sept14.pdf
    │   ├── Known_Issues_and_Workarounds.txt
    │   ├── Miscellaneous
    │   │   ├── ROM_form_for_multiple_instances.vhd
    │   │   └── kcpsm6_without_slice_packing_attributes.vhd
    │   ├── PicoBlaze_Design_in_Vivado.pdf
    │   ├── READ_ME_FIRST.txt
    │   ├── ROM_form.vhd
    │   ├── ROM_form_templates
    │   │   ├── ROM_form_128_14March13.vhd
    │   │   ├── ROM_form_256_5Aug11.vhd
    │   │   ├── ROM_form_7S_1K5_with_ecc_5Dec13.vhd
    │   │   ├── ROM_form_7S_1K_14March13.vhd
    │   │   ├── ROM_form_7S_2K_14March13.vhd
    │   │   ├── ROM_form_7S_2K_with_error_detection_14March13.vhd
    │   │   ├── ROM_form_7S_4K_14March13.vhd
    │   │   ├── ROM_form_JTAGLoader_14March13.vhd
    │   │   ├── ROM_form_JTAGLoader_3Mar11.vhd
    │   │   ├── ROM_form_JTAGLoader_Vivado_2June14.vhd
    │   │   ├── ROM_form_S6_1K_5Aug11.vhd
    │   │   ├── ROM_form_S6_2K_5Aug11.vhd
    │   │   ├── ROM_form_S6_4K_23Nov12.vhd
    │   │   ├── ROM_form_V6_1K_14March13.vhd
    │   │   ├── ROM_form_V6_2K_14March13.vhd
    │   │   └── ROM_form_V6_4K_14March13.vhd
    │   ├── Reference_Design_License.pdf
    │   ├── Reference_Designs
    │   │   ├── I2C
    │   │   │   ├── KC705_KCPSM6_I2C_EEPROM_reference_design.pdf
    │   │   │   ├── PicoTerm_routines.psm
    │   │   │   ├── i2c_routines.psm
    │   │   │   ├── kc705_i2c_devices.psm
    │   │   │   ├── kc705_kcpsm6_i2c_eeprom.ucf
    │   │   │   ├── kc705_kcpsm6_i2c_eeprom.vhd
    │   │   │   ├── m24c08_i2c_uart_bridge.psm
    │   │   │   └── soft_delays_100mhz.psm
    │   │   ├── ICAP
    │   │   │   ├── ICAPE2_routines.psm
    │   │   │   ├── KC705_KCPSM6_ICAP_reference_design.pdf
    │   │   │   ├── PicoTerm_routines.psm
    │   │   │   ├── RAM_4096x8_routines.psm
    │   │   │   ├── icap_control.psm
    │   │   │   ├── kc705_kcpsm6_icap.vhd
    │   │   │   ├── kc705_kcpsm6_icap.xdc
    │   │   │   ├── line_input_and_editing.psm
    │   │   │   └── ram_4096x8.vhd
    │   │   ├── SPI
    │   │   │   ├── KC705_KCPSM6_SPI_Flash_reference_design.pdf
    │   │   │   ├── N25Q128_SPI_routines.psm
    │   │   │   ├── PicoTerm_routines.psm
    │   │   │   ├── kc705_kcpsm6_spi_flash.ucf
    │   │   │   ├── kc705_kcpsm6_spi_flash.vhd
    │   │   │   ├── n25q128_spi_uart_bridge.psm
    │   │   │   └── soft_delays_100mhz.psm
    │   │   ├── VC707_KCPSM6_VID_PMBus_and_more.pdf
    │   │   └── XADC
    │   │   │   ├── KC705_KCPSM6_XADC_reference_design.pdf
    │   │   │   ├── PicoTerm_routines.psm
    │   │   │   ├── kc705_kcpsm6_xadc.ucf
    │   │   │   ├── kc705_kcpsm6_xadc.vhd
    │   │   │   ├── soft_delays_200mhz.psm
    │   │   │   ├── xadc_monitor.psm
    │   │   │   └── xadc_routines.psm
    │   ├── UART_and_PicoTerm
    │   │   ├── ATLYS_design
    │   │   │   ├── PicoTerm_routines.psm
    │   │   │   ├── atlys_real_time_clock.psm
    │   │   │   ├── soft_delays_100mhz.psm
    │   │   │   ├── uart6_atlys.ucf
    │   │   │   ├── uart6_atlys.v
    │   │   │   └── uart6_atlys.vhd
    │   │   ├── BAUD_rate_counter_calculator.xlsx
    │   │   ├── KC705_design
    │   │   │   ├── auto_baud_rate_control.psm
    │   │   │   ├── testbench_uart6_kc705.vhd
    │   │   │   ├── uart6_kc705.ucf
    │   │   │   ├── uart6_kc705.v
    │   │   │   ├── uart6_kc705.vhd
    │   │   │   ├── uart6_kc705.xdc
    │   │   │   └── uart_interface_routines.psm
    │   │   ├── ML605_design
    │   │   │   ├── uart6_ml605.ucf
    │   │   │   ├── uart6_ml605.v
    │   │   │   ├── uart6_ml605.vhd
    │   │   │   ├── uart_control.psm
    │   │   │   └── uart_interface_routines.psm
    │   │   ├── PicoTerm.exe
    │   │   ├── PicoTerm_README.txt
    │   │   ├── UART6_README.txt
    │   │   ├── UART6_User_Guide_and_Reference_Designs_30Sept14.pdf
    │   │   ├── uart_rx6.v
    │   │   ├── uart_rx6.vhd
    │   │   ├── uart_tx6.v
    │   │   └── uart_tx6.vhd
    │   ├── Verilog
    │   │   ├── ROM_form.v
    │   │   ├── ROM_form_128_14March13.v
    │   │   ├── ROM_form_256_5Aug11.v
    │   │   ├── ROM_form_7S_1K_14March13.v
    │   │   ├── ROM_form_7S_2K_14March13.v
    │   │   ├── ROM_form_7S_4K_14March13.v
    │   │   ├── ROM_form_JTAGLoader_14March13.v
    │   │   ├── ROM_form_JTAGLoader_3Mar11.v
    │   │   ├── ROM_form_JTAGLoader_Vivado_2June14.v
    │   │   ├── ROM_form_S6_1K_5Aug11.v
    │   │   ├── ROM_form_S6_2K_5Aug11.v
    │   │   ├── ROM_form_S6_4K_26Nov12.v
    │   │   ├── ROM_form_V6_1K_14March13.v
    │   │   ├── ROM_form_V6_2K_14March13.v
    │   │   ├── ROM_form_V6_4K_14March13.v
    │   │   ├── kcpsm6.v
    │   │   └── kcpsm6_design_template.v
    │   ├── all_kcpsm6_syntax.psm
    │   ├── kcpsm6.exe
    │   ├── kcpsm6.vhd
    │   ├── kcpsm6_assembler_readme.txt
    │   └── kcpsm6_design_template.vhd
    ├── NDivide.v
    ├── README.md
    ├── UartRx.v
    ├── UartRxExtreme.v
    ├── UartTx.v
    ├── UartTxExtreme.v
    ├── UartTxExtreme_UartRxExtreme_tb.v
    ├── UartTx_UartRx_tb.v
    ├── adder_tree.sv
    ├── adder_tree_tb.sv
    ├── avalon_mm_master_templates
    │   ├── Avalon_MM_Masters_Readme.pdf
    │   ├── burst_read_master.v
    │   ├── burst_write_master.v
    │   ├── custom_master.v
    │   ├── custom_masters_hw.tcl
    │   ├── latency_aware_read_master.v
    │   └── write_master.v
    ├── axi4l_logger.sv
    ├── axi_master_slave_templates
    │   ├── M00_axi.v
    │   ├── S00_axi.v
    │   └── S00_axi_lite.v
    ├── benchmark_projects
    │   ├── benchmark_results.txt
    │   ├── gowin_benchmark
    │   │   ├── gowin_benchmark.gprj
    │   │   ├── gowin_benchmark.gprj.user
    │   │   ├── impl
    │   │   │   └── project_process_config.json
    │   │   ├── readme.txt
    │   │   └── src
    │   │   │   ├── dynamic_delay.sv
    │   │   │   ├── main.sv
    │   │   │   └── timing.sdc
    │   ├── ise_benchmark
    │   │   ├── .gitignore
    │   │   ├── dynamic_delay.v
    │   │   ├── ise_benchmark.xise
    │   │   ├── main.ucf
    │   │   ├── main.v
    │   │   └── readme.txt
    │   ├── quartus_benchmark
    │   │   ├── dynamic_delay.sv
    │   │   ├── main.sdc
    │   │   ├── main.sv
    │   │   ├── post_flow.tcl
    │   │   ├── project_version.tcl
    │   │   ├── readme.txt
    │   │   ├── test.qpf
    │   │   └── test.qsf
    │   └── vivado_benchmark
    │   │   ├── allow_undefined_ports.tcl
    │   │   ├── post_flow_vivado.tcl
    │   │   ├── readme.txt
    │   │   ├── vivado_benchmark.srcs
    │   │       ├── constrs_1
    │   │       │   └── timing.sdc
    │   │       └── sources_1
    │   │       │   ├── dynamic_delay.sv
    │   │       │   └── main.sv
    │   │   └── vivado_benchmark.xpr
    ├── bin2gray.sv
    ├── bin2pos.sv
    ├── bin2pos_tb.sv
    ├── cdc_data.sv
    ├── cdc_strobe.sv
    ├── cdc_strobe_tb.sv
    ├── clk_divider.sv
    ├── clogb2.svh
    ├── debounce.v
    ├── debounce_tb.v
    ├── delay.sv
    ├── delay_tb.sv
    ├── delayed_event.sv
    ├── dual_port_ram_templates
    │   ├── byte_enabled_true_dual_port_ram.v
    │   ├── true_dual_port_ram_dual_clock.v
    │   └── xilinx_true_dual_port_read_first_2_clock_ram.v
    ├── dynamic_delay.sv
    ├── dynamic_delay_tb.sv
    ├── edge_detect.sv
    ├── edge_detect_tb.sv
    ├── encoder.v
    ├── encoder_tb.v
    ├── example_projects
    │   ├── fast_counter_iterative_test
    │   │   ├── FMAX plots_cyclonev.png
    │   │   ├── FMAX plots_cyclonev.xlsx
    │   │   ├── Makefile
    │   │   ├── base
    │   │   │   ├── Makefile
    │   │   │   ├── define.vh
    │   │   │   ├── fast_counter.sv
    │   │   │   ├── main.sdc
    │   │   │   ├── main.sv
    │   │   │   ├── test.qpf
    │   │   │   └── test.qsf
    │   │   ├── fmax.rpt
    │   │   └── redme.md
    │   ├── quartus_test_prj_template_v4.7z
    │   ├── quartus_test_prj_template_v4
    │   │   ├── .gitignore
    │   │   ├── Makefile
    │   │   ├── clean_quartus.bat
    │   │   ├── debug
    │   │   │   └── in_out_data.stp
    │   │   ├── ip
    │   │   │   ├── .qsys_edit
    │   │   │   │   ├── filters.xml
    │   │   │   │   ├── jtag_io.xml
    │   │   │   │   ├── jtag_io_schematic.nlv
    │   │   │   │   └── preferences.xml
    │   │   │   ├── jtag_io.qsys
    │   │   │   ├── jtag_io.sopcinfo
    │   │   │   ├── jtag_io
    │   │   │   │   ├── jtag_io.bsf
    │   │   │   │   ├── jtag_io.cmp
    │   │   │   │   ├── jtag_io.html
    │   │   │   │   ├── jtag_io.xml
    │   │   │   │   ├── jtag_io_bb.v
    │   │   │   │   ├── jtag_io_generation.rpt
    │   │   │   │   ├── jtag_io_inst.v
    │   │   │   │   ├── jtag_io_inst.vhd
    │   │   │   │   └── synthesis
    │   │   │   │   │   ├── jtag_io.debuginfo
    │   │   │   │   │   ├── jtag_io.qip
    │   │   │   │   │   ├── jtag_io.regmap
    │   │   │   │   │   ├── jtag_io.v
    │   │   │   │   │   └── submodules
    │   │   │   │   │       ├── altera_avalon_packets_to_master.v
    │   │   │   │   │       ├── altera_avalon_sc_fifo.v
    │   │   │   │   │       ├── altera_avalon_st_bytes_to_packets.v
    │   │   │   │   │       ├── altera_avalon_st_clock_crosser.v
    │   │   │   │   │       ├── altera_avalon_st_idle_inserter.v
    │   │   │   │   │       ├── altera_avalon_st_idle_remover.v
    │   │   │   │   │       ├── altera_avalon_st_jtag_interface.sdc
    │   │   │   │   │       ├── altera_avalon_st_jtag_interface.v
    │   │   │   │   │       ├── altera_avalon_st_packets_to_bytes.v
    │   │   │   │   │       ├── altera_avalon_st_pipeline_base.v
    │   │   │   │   │       ├── altera_avalon_st_pipeline_stage.sv
    │   │   │   │   │       ├── altera_jtag_dc_streaming.v
    │   │   │   │   │       ├── altera_jtag_sld_node.v
    │   │   │   │   │       ├── altera_jtag_streaming.v
    │   │   │   │   │       ├── altera_merlin_arbitrator.sv
    │   │   │   │   │       ├── altera_merlin_burst_uncompressor.sv
    │   │   │   │   │       ├── altera_merlin_master_agent.sv
    │   │   │   │   │       ├── altera_merlin_master_translator.sv
    │   │   │   │   │       ├── altera_merlin_reorder_memory.sv
    │   │   │   │   │       ├── altera_merlin_slave_agent.sv
    │   │   │   │   │       ├── altera_merlin_slave_translator.sv
    │   │   │   │   │       ├── altera_merlin_traffic_limiter.sv
    │   │   │   │   │       ├── altera_reset_controller.sdc
    │   │   │   │   │       ├── altera_reset_controller.v
    │   │   │   │   │       ├── altera_reset_synchronizer.v
    │   │   │   │   │       ├── altera_std_synchronizer_nocut.v
    │   │   │   │   │       ├── jtag_io_in0.v
    │   │   │   │   │       ├── jtag_io_master_0.v
    │   │   │   │   │       ├── jtag_io_master_0_b2p_adapter.sv
    │   │   │   │   │       ├── jtag_io_master_0_p2b_adapter.sv
    │   │   │   │   │       ├── jtag_io_master_0_timing_adt.sv
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0.v
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_avalon_st_adapter.v
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_cmd_demux.sv
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_cmd_mux.sv
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_router.sv
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_router_001.sv
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_rsp_demux.sv
    │   │   │   │   │       ├── jtag_io_mm_interconnect_0_rsp_mux.sv
    │   │   │   │   │       └── jtag_io_out0.v
    │   │   │   └── sys_pll
    │   │   │   │   ├── sys_pll.bsf
    │   │   │   │   ├── sys_pll.cmp
    │   │   │   │   ├── sys_pll.ppf
    │   │   │   │   ├── sys_pll.qip
    │   │   │   │   ├── sys_pll.sip
    │   │   │   │   ├── sys_pll.spd
    │   │   │   │   ├── sys_pll.v
    │   │   │   │   ├── sys_pll
    │   │   │   │       ├── sys_pll_0002.qip
    │   │   │   │       └── sys_pll_0002.v
    │   │   │   │   ├── sys_pll_sim.f
    │   │   │   │   └── sys_pll_sim
    │   │   │   │       ├── aldec
    │   │   │   │           └── rivierapro_setup.tcl
    │   │   │   │       ├── cadence
    │   │   │   │           ├── cds.lib
    │   │   │   │           ├── hdl.var
    │   │   │   │           └── ncsim_setup.sh
    │   │   │   │       ├── mentor
    │   │   │   │           └── msim_setup.tcl
    │   │   │   │       ├── synopsys
    │   │   │   │           ├── vcs
    │   │   │   │           │   └── vcs_setup.sh
    │   │   │   │           └── vcsmx
    │   │   │   │           │   ├── synopsys_sim.setup
    │   │   │   │           │   └── vcsmx_setup.sh
    │   │   │   │       └── sys_pll.vo
    │   │   ├── program_de10.bat
    │   │   ├── src
    │   │   │   ├── clk_divider.sv
    │   │   │   ├── clogb2.svh
    │   │   │   ├── define.svh
    │   │   │   ├── delay.sv
    │   │   │   ├── edge_detect.sv
    │   │   │   ├── main.sdc
    │   │   │   └── main.sv
    │   │   ├── test.qpf
    │   │   └── test.qsf
    │   ├── testbench_template_tb
    │   │   ├── .gitignore
    │   │   ├── c_rand.v
    │   │   ├── clk_divider.sv
    │   │   ├── compile.bat
    │   │   ├── compile.tcl
    │   │   ├── delay.sv
    │   │   ├── edge_detect.sv
    │   │   └── main_tb.sv
    │   └── vivado_test_prj_template_v2
    │   │   ├── .gitignore
    │   │   ├── hard_clean_vivado.bat
    │   │   ├── src
    │   │       ├── clk_divider.sv
    │   │       ├── clogb2.svh
    │   │       ├── define.svh
    │   │       ├── delay.sv
    │   │       ├── edge_detect.sv
    │   │       ├── main.sv
    │   │       ├── physical.xdc
    │   │       └── timing.xdc
    │   │   ├── test.srcs
    │   │       └── sources_1
    │   │       │   └── ip
    │   │       │       ├── clk_wiz_0
    │   │       │           ├── clk_wiz_0.dcp
    │   │       │           ├── clk_wiz_0.v
    │   │       │           ├── clk_wiz_0.veo
    │   │       │           ├── clk_wiz_0.xci
    │   │       │           ├── clk_wiz_0.xdc
    │   │       │           ├── clk_wiz_0.xml
    │   │       │           ├── clk_wiz_0_board.xdc
    │   │       │           ├── clk_wiz_0_clk_wiz.v
    │   │       │           ├── clk_wiz_0_ooc.xdc
    │   │       │           ├── clk_wiz_0_sim_netlist.v
    │   │       │           ├── clk_wiz_0_sim_netlist.vhdl
    │   │       │           ├── clk_wiz_0_stub.v
    │   │       │           ├── clk_wiz_0_stub.vhdl
    │   │       │           ├── doc
    │   │       │           │   └── clk_wiz_v6_0_changelog.txt
    │   │       │           ├── mmcm_pll_drp_func_7s_mmcm.vh
    │   │       │           ├── mmcm_pll_drp_func_7s_pll.vh
    │   │       │           ├── mmcm_pll_drp_func_us_mmcm.vh
    │   │       │           ├── mmcm_pll_drp_func_us_pll.vh
    │   │       │           ├── mmcm_pll_drp_func_us_plus_mmcm.vh
    │   │       │           └── mmcm_pll_drp_func_us_plus_pll.vh
    │   │       │       └── vio_0
    │   │       │           ├── doc
    │   │       │               └── vio_v3_0_changelog.txt
    │   │       │           ├── hdl
    │   │       │               ├── ltlib_v1_0_vl_rfs.v
    │   │       │               ├── verilog
    │   │       │               │   ├── ltlib_v1_0_0_lib_fn.vh
    │   │       │               │   ├── ltlib_v1_0_0_ver.vh
    │   │       │               │   ├── xsdbs_v1_0_2_i2x.vh
    │   │       │               │   └── xsdbs_v1_0_2_in.vh
    │   │       │               ├── vio_v3_0_19_vio_include.v
    │   │       │               ├── vio_v3_0_syn_rfs.v
    │   │       │               └── xsdbs_v1_0_vl_rfs.v
    │   │       │           ├── sim
    │   │       │               └── vio_0.v
    │   │       │           ├── synth
    │   │       │               └── vio_0.v
    │   │       │           ├── vio_0.dcp
    │   │       │           ├── vio_0.veo
    │   │       │           ├── vio_0.vho
    │   │       │           ├── vio_0.xci
    │   │       │           ├── vio_0.xdc
    │   │       │           ├── vio_0.xml
    │   │       │           ├── vio_0_ooc.xdc
    │   │       │           ├── vio_0_sim_netlist.v
    │   │       │           ├── vio_0_sim_netlist.vhdl
    │   │       │           ├── vio_0_stub.v
    │   │       │           └── vio_0_stub.vhdl
    │   │   └── test.xpr
    ├── fast_counter.sv
    ├── fast_counter_tb.sv
    ├── fifo_single_clock_ram.sv
    ├── fifo_single_clock_ram_init.mem
    ├── fifo_single_clock_ram_tb.sv
    ├── fifo_single_clock_reg_v1.sv
    ├── fifo_single_clock_reg_v1_init.svh
    ├── fifo_single_clock_reg_v1_tb.sv
    ├── fifo_single_clock_reg_v2.sv
    ├── fifo_single_clock_reg_v2_init.svh
    ├── fifo_single_clock_reg_v2_tb.sv
    ├── gitignores
    │   ├── .gitignore_modelsim
    │   ├── .gitignore_quartus
    │   └── .gitignore_vivado
    ├── gray2bin.sv
    ├── gray_tb.sv
    ├── leave_one_hot.sv
    ├── leave_one_hot_tb.sv
    ├── license
    │   ├── 88x31.png
    │   └── Creative Commons — Attribution-ShareAlike 4_0 International — CC BY-SA 4_0.htm
    ├── lifo.sv
    ├── lifo_tb.sv
    ├── main_tb.sv
    ├── moving_average.sv
    ├── moving_average_tb.sv
    ├── pack_unpack_array.v
    ├── pacoblaze-2.2
    │   ├── Contributors.txt
    │   ├── Copyright.txt
    │   ├── Doxyfile
    │   ├── KCAsm.jar
    │   ├── License.txt
    │   ├── build.xml
    │   ├── docs
    │   │   ├── pacoblaze.pdf
    │   │   └── picoblaze.pdf
    │   ├── kcasm
    │   │   ├── AsmExpression.class
    │   │   ├── AsmExpression.java
    │   │   ├── Assembler.class
    │   │   ├── Assembler.java
    │   │   ├── Assembler1.class
    │   │   ├── Assembler1.java
    │   │   ├── Assembler2.class
    │   │   ├── Assembler2.java
    │   │   ├── Assembler3.class
    │   │   ├── Assembler3.java
    │   │   ├── Command.class
    │   │   ├── Command.java
    │   │   ├── Comment.class
    │   │   ├── Comment.java
    │   │   ├── Copy of Assembler.java
    │   │   ├── Environment.class
    │   │   ├── Environment.java
    │   │   ├── Instruction.class
    │   │   ├── Instruction.java
    │   │   ├── Instruction1.class
    │   │   ├── Instruction1.java
    │   │   ├── Instruction2.class
    │   │   ├── Instruction2.java
    │   │   ├── Instruction3.class
    │   │   ├── Instruction3.java
    │   │   ├── KCAsm$1.class
    │   │   ├── KCAsm$JJCalls.class
    │   │   ├── KCAsm$LookaheadSuccess.class
    │   │   ├── KCAsm.class
    │   │   ├── KCAsm.java
    │   │   ├── KCAsm.jj
    │   │   ├── KCAsmConstants.class
    │   │   ├── KCAsmConstants.java
    │   │   ├── KCAsmTokenManager.class
    │   │   ├── KCAsmTokenManager.java
    │   │   ├── Label.class
    │   │   ├── Label.java
    │   │   ├── MANIFEST.MF
    │   │   ├── Makefile
    │   │   ├── ParseException.class
    │   │   ├── ParseException.java
    │   │   ├── SimpleCharStream.class
    │   │   ├── SimpleCharStream.java
    │   │   ├── Symbol$Type.class
    │   │   ├── Symbol.class
    │   │   ├── Symbol.java
    │   │   ├── Token.class
    │   │   ├── Token.java
    │   │   ├── TokenMgrError.class
    │   │   ├── TokenMgrError.java
    │   │   └── kcasm
    │   │   │   ├── AsmExpression.html
    │   │   │   ├── Assembler.html
    │   │   │   ├── Assembler1.html
    │   │   │   ├── Assembler2.html
    │   │   │   ├── Assembler3.html
    │   │   │   ├── Command.html
    │   │   │   ├── Comment.html
    │   │   │   ├── Environment.html
    │   │   │   ├── Instruction.html
    │   │   │   ├── Instruction1.html
    │   │   │   ├── Instruction2.html
    │   │   │   ├── Instruction3.html
    │   │   │   ├── Label.html
    │   │   │   ├── Symbol.Type.html
    │   │   │   ├── Symbol.html
    │   │   │   ├── allclasses-frame.html
    │   │   │   ├── allclasses-noframe.html
    │   │   │   ├── constant-values.html
    │   │   │   ├── deprecated-list.html
    │   │   │   ├── help-doc.html
    │   │   │   ├── index-all.html
    │   │   │   ├── index.html
    │   │   │   ├── overview-tree.html
    │   │   │   ├── package-frame.html
    │   │   │   ├── package-list
    │   │   │   ├── package-summary.html
    │   │   │   ├── package-tree.html
    │   │   │   ├── resources
    │   │   │       └── inherit.gif
    │   │   │   └── stylesheet.css
    │   ├── pacoblaze
    │   │   ├── Makefile
    │   │   ├── addsub.v
    │   │   ├── addsub_tb.v
    │   │   ├── blockram.v
    │   │   ├── cmprnd3_tb.v
    │   │   ├── compare3_tb.v
    │   │   ├── compare3m_tb.v
    │   │   ├── int_test.v
    │   │   ├── pacoblaze.v
    │   │   ├── pacoblaze
    │   │   │   ├── addsub.v
    │   │   │   ├── addsub.v.html
    │   │   │   ├── addsub_tb.v
    │   │   │   ├── addsub_tb.v.html
    │   │   │   ├── blank_printIt.html
    │   │   │   ├── blockram.v
    │   │   │   ├── blockram.v.html
    │   │   │   ├── cmprnd3_tb.v
    │   │   │   ├── cmprnd3_tb.v.html
    │   │   │   ├── compare3_tb.v
    │   │   │   ├── compare3_tb.v.html
    │   │   │   ├── compare3m_tb.v
    │   │   │   ├── compare3m_tb.v.html
    │   │   │   ├── index-f.html
    │   │   │   ├── index-fn.html
    │   │   │   ├── index-m.html
    │   │   │   ├── index-s.html
    │   │   │   ├── index-s.p2.html
    │   │   │   ├── index-s.p3.html
    │   │   │   ├── index-s.p4.html
    │   │   │   ├── index-s.p5.html
    │   │   │   ├── index-t.html
    │   │   │   ├── index.html
    │   │   │   ├── int_test.v
    │   │   │   ├── int_test.v.html
    │   │   │   ├── pacoblaze.v
    │   │   │   ├── pacoblaze.v.html
    │   │   │   ├── pacoblaze1.v
    │   │   │   ├── pacoblaze1.v.html
    │   │   │   ├── pacoblaze1_idu_xst.v
    │   │   │   ├── pacoblaze1_idu_xst.v.html
    │   │   │   ├── pacoblaze1_tb.v
    │   │   │   ├── pacoblaze1_tb.v.html
    │   │   │   ├── pacoblaze1_xst.v
    │   │   │   ├── pacoblaze1_xst.v.html
    │   │   │   ├── pacoblaze2.v
    │   │   │   ├── pacoblaze2.v.html
    │   │   │   ├── pacoblaze2_idu_xst.v
    │   │   │   ├── pacoblaze2_idu_xst.v.html
    │   │   │   ├── pacoblaze2_xst.v
    │   │   │   ├── pacoblaze2_xst.v.html
    │   │   │   ├── pacoblaze3.v
    │   │   │   ├── pacoblaze3.v.html
    │   │   │   ├── pacoblaze3_dregister_xst.v
    │   │   │   ├── pacoblaze3_dregister_xst.v.html
    │   │   │   ├── pacoblaze3_idu_xst.v
    │   │   │   ├── pacoblaze3_idu_xst.v.html
    │   │   │   ├── pacoblaze3_tb.v
    │   │   │   ├── pacoblaze3_tb.v.html
    │   │   │   ├── pacoblaze3_xst.v
    │   │   │   ├── pacoblaze3_xst.v.html
    │   │   │   ├── pacoblaze3b_tb.v
    │   │   │   ├── pacoblaze3b_tb.v.html
    │   │   │   ├── pacoblaze3m.v
    │   │   │   ├── pacoblaze3m.v.html
    │   │   │   ├── pacoblaze3m_tb.v
    │   │   │   ├── pacoblaze3m_tb.v.html
    │   │   │   ├── pacoblaze3m_xst.v
    │   │   │   ├── pacoblaze3m_xst.v.html
    │   │   │   ├── pacoblaze_alu.v
    │   │   │   ├── pacoblaze_alu.v.html
    │   │   │   ├── pacoblaze_dregister.v
    │   │   │   ├── pacoblaze_dregister.v.html
    │   │   │   ├── pacoblaze_dregister_tb.v
    │   │   │   ├── pacoblaze_dregister_tb.v.html
    │   │   │   ├── pacoblaze_idu.v
    │   │   │   ├── pacoblaze_idu.v.html
    │   │   │   ├── pacoblaze_idu_tb.v
    │   │   │   ├── pacoblaze_idu_tb.v.html
    │   │   │   ├── pacoblaze_inc.v
    │   │   │   ├── pacoblaze_inc.v.html
    │   │   │   ├── pacoblaze_register.v
    │   │   │   ├── pacoblaze_register.v.html
    │   │   │   ├── pacoblaze_scratch.v
    │   │   │   ├── pacoblaze_scratch.v.html
    │   │   │   ├── pacoblaze_stack.v
    │   │   │   ├── pacoblaze_stack.v.html
    │   │   │   ├── pacoblaze_util.v
    │   │   │   ├── pacoblaze_util.v.html
    │   │   │   ├── test.v
    │   │   │   ├── test.v.html
    │   │   │   ├── timescale_inc.v
    │   │   │   ├── timescale_inc.v.html
    │   │   │   ├── uclock.v
    │   │   │   ├── uclock.v.html
    │   │   │   ├── uclock_ti.v
    │   │   │   ├── uclock_ti.v.html
    │   │   │   ├── v2html-b1.gif
    │   │   │   ├── v2html-b2.gif
    │   │   │   ├── v2html-b3.gif
    │   │   │   ├── v2html-c.gif
    │   │   │   ├── v2html-i.gif
    │   │   │   ├── v2html-up.gif
    │   │   │   ├── v2html-x.gif
    │   │   │   └── v2html.css
    │   │   ├── pacoblaze1.v
    │   │   ├── pacoblaze1_idu_xst.v
    │   │   ├── pacoblaze1_tb.v
    │   │   ├── pacoblaze1_xst.v
    │   │   ├── pacoblaze2.v
    │   │   ├── pacoblaze2_idu_xst.v
    │   │   ├── pacoblaze2_xst.v
    │   │   ├── pacoblaze3.v
    │   │   ├── pacoblaze3_dregister_xst.v
    │   │   ├── pacoblaze3_idu_xst.v
    │   │   ├── pacoblaze3_tb.v
    │   │   ├── pacoblaze3_xst.v
    │   │   ├── pacoblaze3b_tb.v
    │   │   ├── pacoblaze3m.v
    │   │   ├── pacoblaze3m_tb.v
    │   │   ├── pacoblaze3m_xst.v
    │   │   ├── pacoblaze_alu.v
    │   │   ├── pacoblaze_dregister.v
    │   │   ├── pacoblaze_dregister_tb.v
    │   │   ├── pacoblaze_idu.v
    │   │   ├── pacoblaze_idu_tb.v
    │   │   ├── pacoblaze_inc.v
    │   │   ├── pacoblaze_register.v
    │   │   ├── pacoblaze_scratch.v
    │   │   ├── pacoblaze_stack.v
    │   │   ├── pacoblaze_util.v
    │   │   ├── test.v
    │   │   ├── testall.sh
    │   │   ├── timescale_inc.v
    │   │   ├── uclock.v
    │   │   └── uclock_ti.v
    │   ├── test
    │   │   ├── Makefile
    │   │   ├── adc_ctrl.psm
    │   │   ├── adc_ctrl.rmh
    │   │   ├── adc_ctrl_rom.v
    │   │   ├── auto_pwm.psm
    │   │   ├── auto_pwm.rmh
    │   │   ├── auto_pwm_rom.v
    │   │   ├── clock.psm
    │   │   ├── clock.rmh
    │   │   ├── clock_rom.v
    │   │   ├── control.psm
    │   │   ├── control.rmh
    │   │   ├── control_rom.v
    │   │   ├── dac_ctrl.psm
    │   │   ├── dac_ctrl.rmh
    │   │   ├── dac_ctrl_rom.v
    │   │   ├── fc_ctrl.psm
    │   │   ├── fc_ctrl.rmh
    │   │   ├── fc_ctrl_rom.v
    │   │   ├── fg_ctrl.psm
    │   │   ├── fg_ctrl.rmh
    │   │   ├── fg_ctrl_rom.v
    │   │   ├── int_test.psm
    │   │   ├── int_test.rmh
    │   │   ├── int_test2.psm
    │   │   ├── int_test2.rmh
    │   │   ├── int_test2.vhd
    │   │   ├── int_test2_rom.v
    │   │   ├── int_test_rom.v
    │   │   ├── led_ctrl.psm
    │   │   ├── led_ctrl.rmh
    │   │   ├── led_ctrl_rom.v
    │   │   ├── ls_test.psm
    │   │   ├── ls_test.rmh
    │   │   ├── ls_test_rom.v
    │   │   ├── pb3_int.psm
    │   │   ├── pb3_int.rmh
    │   │   ├── pb3_int_rom.v
    │   │   ├── pb3_ret.psm
    │   │   ├── pb3_ret.rmh
    │   │   ├── pb3_ret_rom.v
    │   │   ├── pb3_test.psm
    │   │   ├── pb3_test.rmh
    │   │   ├── pb3_test_rom.v
    │   │   ├── pb3m_test.psm
    │   │   ├── pb3m_test.rmh
    │   │   ├── pb3m_test_rom.v
    │   │   ├── progctrl.psm
    │   │   ├── progctrl.rmh
    │   │   ├── progctrl_rom.v
    │   │   ├── pwm_ctrl.psm
    │   │   ├── pwm_ctrl.rmh
    │   │   ├── pwm_ctrl_rom.v
    │   │   ├── security.psm
    │   │   ├── security.rmh
    │   │   ├── security_rom.v
    │   │   ├── sha1prog.psm
    │   │   ├── sha1prog.rmh
    │   │   ├── sha1prog_rom.v
    │   │   ├── spi_prog.psm
    │   │   ├── spi_prog.rmh
    │   │   ├── spi_prog_rom.v
    │   │   ├── test3.psm
    │   │   ├── test3.rmh
    │   │   ├── test3_rom.v
    │   │   ├── testint.psm
    │   │   ├── testint.rmh
    │   │   ├── testint_rom.v
    │   │   ├── testsub.psm
    │   │   ├── testsub.rmh
    │   │   ├── testsub_rom.v
    │   │   ├── uclock.psm
    │   │   ├── uclock.rmh
    │   │   └── uclock_rom.v
    │   └── xilinx
    │   │   ├── kcpsm2.v
    │   │   ├── kcpsm3.v
    │   │   └── unisims
    │   │       ├── FD.v
    │   │       ├── FDE.v
    │   │       ├── FDR.v
    │   │       ├── FDRE.v
    │   │       ├── FDRSE.v
    │   │       ├── FDS.v
    │   │       ├── INV.v
    │   │       ├── LUT1.v
    │   │       ├── LUT2.v
    │   │       ├── LUT3.v
    │   │       ├── LUT4.v
    │   │       ├── MUXCY.v
    │   │       ├── MUXF5.v
    │   │       ├── RAM16X1D.v
    │   │       ├── RAM32X1S.v
    │   │       ├── RAM64X1S.v
    │   │       ├── XORCY.v
    │   │       └── glbl.v
    ├── pdm_modulator.sv
    ├── pdm_modulator_tb.png
    ├── pdm_modulator_tb.sv
    ├── pos2bin.sv
    ├── pos2bin_tb.sv
    ├── prbs_gen_chk.sv
    ├── prbs_gen_chk_tb.sv
    ├── preview_fifo.sv
    ├── preview_fifo_tb.sv
    ├── priority_enc.sv
    ├── pulse_gen.sv
    ├── pulse_gen_tb.sv
    ├── pulse_stretch.sv
    ├── pulse_stretch_tb.sv
    ├── pwm_modulator.sv
    ├── pwm_modulator_tb.png
    ├── pwm_modulator_tb.sv
    ├── read_ahead_buf.sv
    ├── reset_set.sv
    ├── reset_set_comb.sv
    ├── reverse_bytes.sv
    ├── reverse_dimensions.sv
    ├── reverse_dimensions_tb.sv
    ├── reverse_vector.sv
    ├── reverse_vector_tb.sv
    ├── round_robin_enc.sv
    ├── round_robin_performance_enc.sv
    ├── round_robin_performance_enc_tb.sv
    ├── scripts
    │   ├── Vivado_init.tcl
    │   ├── allow_undefined_ports.tcl
    │   ├── allow_wors.tcl
    │   ├── ba.tcl
    │   ├── check_numeric_filenames.sh
    │   ├── clean_modelsim.bat
    │   ├── clean_quartus.bat
    │   ├── clean_recursively.bat
    │   ├── clean_vivado.bat
    │   ├── compile_quartus.bat
    │   ├── convert_sof_to_jam.bat
    │   ├── convert_sof_to_rbf.bat
    │   ├── dse_quartus.bat
    │   ├── export_autoplaced_pins.tcl
    │   ├── find_large_files.bat
    │   ├── git-merge-fix.sh
    │   ├── hard_clean_modelsim.bat
    │   ├── hard_clean_vivado.bat
    │   ├── init_system_console.bat
    │   ├── iverilog_compile.bat
    │   ├── jtag_to_axi_master.tcl
    │   ├── mem_writer.sh
    │   ├── mem_writer_adv.py
    │   ├── mem_writer_adv_examples
    │   │   ├── 1024cos.mem
    │   │   ├── 1024sin.mem
    │   │   ├── 128cos.mem
    │   │   ├── 128lin.mem
    │   │   └── 128sin.mem
    │   ├── mem_writer_examples
    │   │   ├── 1024x32bit_linear.mem
    │   │   ├── 1024x32bit_random.mem
    │   │   ├── 128x16bit_linear.mem
    │   │   ├── 128x16bit_random.mem
    │   │   ├── 128x32bit_linear.mem
    │   │   ├── 128x32bit_random.mem
    │   │   ├── 16x16bit_linear.mem
    │   │   ├── 16x16bit_random.mem
    │   │   ├── 16x32bit_linear.mem
    │   │   ├── 16x32bit_random.mem
    │   │   ├── 16x8bit_linear.mem
    │   │   ├── 16x8bit_random.mem
    │   │   ├── 2048x32bit_linear.mem
    │   │   ├── 2048x32bit_random.mem
    │   │   ├── 256x16bit_linear.mem
    │   │   ├── 256x16bit_random.mem
    │   │   ├── 256x32bit_linear.mem
    │   │   ├── 256x32bit_random.mem
    │   │   ├── 32x16bit_linear.mem
    │   │   ├── 32x16bit_random.mem
    │   │   ├── 32x32bit_linear.mem
    │   │   ├── 32x32bit_random.mem
    │   │   ├── 4096x32bit_linear.mem
    │   │   ├── 4096x32bit_random.mem
    │   │   ├── 512x32bit_linear.mem
    │   │   ├── 512x32bit_random.mem
    │   │   ├── 64x16bit_linear.mem
    │   │   ├── 64x16bit_random.mem
    │   │   ├── 64x32bit_linear.mem
    │   │   ├── 64x32bit_random.mem
    │   │   ├── 65536x32bit_linear.mem
    │   │   └── 65536x32bit_random.mem
    │   ├── modelsim_compile.bat
    │   ├── modelsim_compile.sh
    │   ├── modelsim_compile.tcl
    │   ├── post_flow_quartus.tcl
    │   ├── post_flow_vivado.tcl
    │   ├── program_all.bat
    │   ├── project_version_auto_increment.tcl
    │   ├── quartus_system_console_init.tcl
    │   ├── set_project_directory.tcl
    │   ├── setup_jtag_server_quartus.bat
    │   ├── update_git_repos.sh
    │   └── write_avalon_mm_from_file.tcl
    ├── scripts_for_intel_hls
    │   ├── b.bat
    │   ├── build_recursively.bat
    │   ├── hls_type_size_win64.txt
    │   ├── i.bat
    │   └── test.cpp
    ├── set_reset.sv
    ├── set_reset_comb.sv
    ├── soft_latch.sv
    ├── soft_latch_tb.sv
    ├── spi_master.sv
    ├── spi_master_tb.sv
    ├── true_dual_port_write_first_2_clock_ram.sv
    ├── true_single_port_write_first_ram.sv
    ├── uart_debug_printer.sv
    ├── uart_rx.sv
    ├── uart_rx_shifter.sv
    ├── uart_tx.sv
    ├── uart_tx_rx_shifter_tb.png
    ├── uart_tx_rx_shifter_tb.sv
    ├── uart_tx_shifter.sv
    └── vm80a.v
└── generic_systemverilog_designs_library
    ├── LICENSE
    ├── README.md
    ├── binary_counter
        ├── binary_counter.sv
        └── tb.sv
    ├── binary_to_gray
        └── binary_to_gray.sv
    ├── demultiplexer
        └── demux.sv
    ├── full_adder
        └── full_adder.sv
    ├── full_subtractor
        └── full_subtractor.sv
    ├── gray_counter
        └── gray_counter.sv
    └── multiplexer
        └── mux.sv


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1 | # SvLibDR
2 |  SysteVerilog Library from Digital Rabbit
3 | 


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/SvLibDR/ReceiverUART/ReceiverUART.sv:
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/SvLibDR/ReceiverUART/RxUART_logic.sv:
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/SvLibDR/ReceiverUART/RxUART_timeout.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/ReceiverUART/RxUART_timeout.sv


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/SvLibDR/ReceiverUART/SingleRxUART.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/ReceiverUART/SingleRxUART.sv


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/SvLibDR/ReceiverUART/simulate.do:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/ReceiverUART/simulate.do


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/SvLibDR/ReceiverUART/tb.sv:
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/SvLibDR/SingleRxUART/SingleRxUART.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleRxUART/simulate.do


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/SvLibDR/SingleRxUART/tb.sv:
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/SvLibDR/SingleSPImaster/SingleSPImaster.sv:
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/SvLibDR/SingleSPImaster/simulate.do:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleSPImaster/simulate.do


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/SvLibDR/SingleSPImaster/tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleSPImaster/tb.sv


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/SvLibDR/SingleSPIslave/SingleSPIslave.sv:
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/SvLibDR/SingleSPIslave/simulate.do:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleSPIslave/simulate.do


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/SvLibDR/SingleSPIslave/tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleSPIslave/tb.sv


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/SvLibDR/SingleTxUART/SingleTxUART.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleTxUART/SingleTxUART.sv


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/SvLibDR/SingleTxUART/simulate.do:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleTxUART/simulate.do


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/SvLibDR/SingleTxUART/tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/SingleTxUART/tb.sv


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/SvLibDR/TransmitterUART/SingleTxUART.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/TransmitterUART/SingleTxUART.sv


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/SvLibDR/TransmitterUART/TransmitterUART.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/TransmitterUART/TransmitterUART.sv


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/SvLibDR/TransmitterUART/TxUART_logic.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/TransmitterUART/TxUART_logic.sv


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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SvLibDR/TransmitterUART/simulate.do


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/SvLibDR/TransmitterUART/tb.sv:
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/SystemVerilog-Bitmap-Library-AXI-Image-VIP/LICENSE:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SystemVerilog-Bitmap-Library-AXI-Image-VIP/LICENSE


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/SystemVerilog-Bitmap-Library-AXI-Image-VIP/README.md:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/SystemVerilog-Bitmap-Library-AXI-Image-VIP/README.md


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/SystemVerilog-Bitmap-Library-AXI-Image-VIP/bitmap_processing.sv:
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/basic_verilog/ActionBurst.v:
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/basic_verilog/ActionBurst2.v:
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/basic_verilog/Advanced Synthesis Cookbook/arithmetic/basic_adder.v:
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/basic_verilog/Advanced Synthesis Cookbook/arithmetic/divider.v:
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/basic_verilog/Advanced Synthesis Cookbook/arithmetic/iter_addsub.v:
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/basic_verilog/Advanced Synthesis Cookbook/arithmetic/log2.inc:
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/basic_verilog/Advanced Synthesis Cookbook/arithmetic/sum_of_64.v:
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/basic_verilog/Advanced Synthesis Cookbook/utility/log2.inc:
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/basic_verilog/KCPSM6_Release9_30Sept14/JTAG_Loader/msvcr100.dll:
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/basic_verilog/KCPSM6_Release9_30Sept14/READ_ME_FIRST.txt:
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/basic_verilog/KCPSM6_Release9_30Sept14/ROM_form.vhd:
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/basic_verilog/KCPSM6_Release9_30Sept14/Verilog/ROM_form.v:
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/basic_verilog/KCPSM6_Release9_30Sept14/Verilog/kcpsm6.v:
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/basic_verilog/KCPSM6_Release9_30Sept14/all_kcpsm6_syntax.psm:
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/basic_verilog/KCPSM6_Release9_30Sept14/kcpsm6.exe:
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/basic_verilog/KCPSM6_Release9_30Sept14/kcpsm6.vhd:
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/basic_verilog/README.md:
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/basic_verilog/avalon_mm_master_templates/burst_read_master.v:
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/basic_verilog/axi4l_logger.sv:
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/basic_verilog/benchmark_projects/benchmark_results.txt:
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/basic_verilog/benchmark_projects/gowin_benchmark/readme.txt:
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/basic_verilog/benchmark_projects/gowin_benchmark/src/main.sv:
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/basic_verilog/benchmark_projects/gowin_benchmark/src/timing.sdc:
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/basic_verilog/benchmark_projects/ise_benchmark/.gitignore:
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/basic_verilog/benchmark_projects/ise_benchmark/dynamic_delay.v:
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/basic_verilog/benchmark_projects/ise_benchmark/main.ucf:
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/basic_verilog/benchmark_projects/ise_benchmark/main.v:
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/basic_verilog/benchmark_projects/ise_benchmark/readme.txt:
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/basic_verilog/benchmark_projects/quartus_benchmark/main.sdc:
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/basic_verilog/benchmark_projects/quartus_benchmark/main.sv:
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/basic_verilog/debounce_tb.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/debounce_tb.v


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/basic_verilog/delay.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/delay.sv


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/basic_verilog/delay_tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/delay_tb.sv


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/basic_verilog/delayed_event.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/delayed_event.sv


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/basic_verilog/dynamic_delay.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/dynamic_delay.sv


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/basic_verilog/dynamic_delay_tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/dynamic_delay_tb.sv


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/basic_verilog/edge_detect.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/edge_detect.sv


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/basic_verilog/edge_detect_tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/edge_detect_tb.sv


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/basic_verilog/encoder.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/encoder.v


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/basic_verilog/encoder_tb.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/encoder_tb.v


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/basic_verilog/example_projects/fast_counter_iterative_test/base/define.vh:
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1 | `define WIDTH 5


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/basic_verilog/example_projects/quartus_test_prj_template_v4.7z:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/example_projects/quartus_test_prj_template_v4.7z


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/basic_verilog/example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll_sim/cadence/hdl.var:
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3 | 


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1 | PROJECT_REVISION = "test"
2 | 


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/basic_verilog/example_projects/testbench_template_tb/.gitignore:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/example_projects/testbench_template_tb/.gitignore


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/basic_verilog/example_projects/testbench_template_tb/c_rand.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/example_projects/testbench_template_tb/c_rand.v


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/basic_verilog/example_projects/testbench_template_tb/compile.bat:
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1 | modelsim.exe -do compile.tcl


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/basic_verilog/example_projects/testbench_template_tb/compile.tcl:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/example_projects/testbench_template_tb/compile.tcl


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/basic_verilog/example_projects/testbench_template_tb/delay.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/example_projects/testbench_template_tb/delay.sv


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/basic_verilog/example_projects/testbench_template_tb/main_tb.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/example_projects/testbench_template_tb/main_tb.sv


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/basic_verilog/fast_counter.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fast_counter.sv


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/basic_verilog/fast_counter_tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fast_counter_tb.sv


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/basic_verilog/fifo_single_clock_ram.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_ram.sv


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/basic_verilog/fifo_single_clock_ram_init.mem:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_ram_init.mem


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/basic_verilog/fifo_single_clock_ram_tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_ram_tb.sv


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/basic_verilog/fifo_single_clock_reg_v1.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_reg_v1.sv


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/basic_verilog/fifo_single_clock_reg_v1_init.svh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_reg_v1_init.svh


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/basic_verilog/fifo_single_clock_reg_v1_tb.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_reg_v1_tb.sv


--------------------------------------------------------------------------------
/basic_verilog/fifo_single_clock_reg_v2.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_reg_v2.sv


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/basic_verilog/fifo_single_clock_reg_v2_init.svh:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_reg_v2_init.svh


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/basic_verilog/fifo_single_clock_reg_v2_tb.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/fifo_single_clock_reg_v2_tb.sv


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/basic_verilog/gitignores/.gitignore_modelsim:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/gitignores/.gitignore_modelsim


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/basic_verilog/gitignores/.gitignore_quartus:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/gitignores/.gitignore_quartus


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/basic_verilog/gitignores/.gitignore_vivado:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/gitignores/.gitignore_vivado


--------------------------------------------------------------------------------
/basic_verilog/gray2bin.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/gray2bin.sv


--------------------------------------------------------------------------------
/basic_verilog/gray_tb.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/gray_tb.sv


--------------------------------------------------------------------------------
/basic_verilog/leave_one_hot.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/leave_one_hot.sv


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/basic_verilog/leave_one_hot_tb.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/leave_one_hot_tb.sv


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/basic_verilog/license/88x31.png:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/license/88x31.png


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/basic_verilog/lifo.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/lifo.sv


--------------------------------------------------------------------------------
/basic_verilog/lifo_tb.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/lifo_tb.sv


--------------------------------------------------------------------------------
/basic_verilog/main_tb.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/main_tb.sv


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/basic_verilog/moving_average.sv:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/moving_average.sv


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/basic_verilog/moving_average_tb.sv:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/moving_average_tb.sv


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/basic_verilog/pack_unpack_array.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pack_unpack_array.v


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/basic_verilog/pacoblaze-2.2/Contributors.txt:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/Contributors.txt


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/Copyright.txt:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/Copyright.txt


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/Doxyfile:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/Doxyfile


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/basic_verilog/pacoblaze-2.2/KCAsm.jar:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/KCAsm.jar


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/License.txt:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/License.txt


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/build.xml:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/build.xml


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/docs/pacoblaze.pdf:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/docs/pacoblaze.pdf


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/docs/picoblaze.pdf:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/docs/picoblaze.pdf


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/AsmExpression.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/AsmExpression.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/AsmExpression.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/AsmExpression.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Assembler.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Assembler.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler.java


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/basic_verilog/pacoblaze-2.2/kcasm/Assembler1.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler1.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Assembler1.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler1.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Assembler2.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler2.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Assembler2.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler2.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Assembler3.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler3.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Assembler3.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Assembler3.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Command.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Command.class


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/basic_verilog/pacoblaze-2.2/kcasm/Command.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Command.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Comment.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Comment.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Comment.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Comment.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Copy of Assembler.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Copy of Assembler.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Environment.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Environment.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Environment.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Environment.java


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Instruction.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction.class


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/basic_verilog/pacoblaze-2.2/kcasm/Instruction.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction.java


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/basic_verilog/pacoblaze-2.2/kcasm/Instruction1.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction1.class


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/basic_verilog/pacoblaze-2.2/kcasm/Instruction1.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction1.java


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/basic_verilog/pacoblaze-2.2/kcasm/Instruction2.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction2.class


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/basic_verilog/pacoblaze-2.2/kcasm/Instruction2.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction2.java


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/basic_verilog/pacoblaze-2.2/kcasm/Instruction3.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction3.class


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/basic_verilog/pacoblaze-2.2/kcasm/Instruction3.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Instruction3.java


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsm$1.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsm$1.class


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsm$JJCalls.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsm$JJCalls.class


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsm$LookaheadSuccess.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsm$LookaheadSuccess.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/KCAsm.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsm.class


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsm.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsm.java


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsm.jj:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsm.jj


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsmConstants.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsmConstants.class


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsmConstants.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsmConstants.java


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsmTokenManager.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsmTokenManager.class


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/basic_verilog/pacoblaze-2.2/kcasm/KCAsmTokenManager.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/KCAsmTokenManager.java


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/basic_verilog/pacoblaze-2.2/kcasm/Label.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Label.class


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/basic_verilog/pacoblaze-2.2/kcasm/Label.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Label.java


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/basic_verilog/pacoblaze-2.2/kcasm/MANIFEST.MF:
--------------------------------------------------------------------------------
1 | Main-Class: KCAsm
2 | 


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/basic_verilog/pacoblaze-2.2/kcasm/Makefile:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Makefile


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/basic_verilog/pacoblaze-2.2/kcasm/ParseException.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/ParseException.class


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/basic_verilog/pacoblaze-2.2/kcasm/ParseException.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/ParseException.java


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/basic_verilog/pacoblaze-2.2/kcasm/SimpleCharStream.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/SimpleCharStream.class


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/basic_verilog/pacoblaze-2.2/kcasm/SimpleCharStream.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/SimpleCharStream.java


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/basic_verilog/pacoblaze-2.2/kcasm/Symbol$Type.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Symbol$Type.class


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/Symbol.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Symbol.class


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/basic_verilog/pacoblaze-2.2/kcasm/Symbol.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Symbol.java


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/basic_verilog/pacoblaze-2.2/kcasm/Token.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Token.class


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/basic_verilog/pacoblaze-2.2/kcasm/Token.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/Token.java


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/basic_verilog/pacoblaze-2.2/kcasm/TokenMgrError.class:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/TokenMgrError.class


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/basic_verilog/pacoblaze-2.2/kcasm/TokenMgrError.java:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/TokenMgrError.java


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/basic_verilog/pacoblaze-2.2/kcasm/kcasm/AsmExpression.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/AsmExpression.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler1.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler1.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler2.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler2.html


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/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler3.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Assembler3.html


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/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Command.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Command.html


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/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Comment.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Comment.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Environment.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Environment.html


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/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction.html


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/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction1.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction1.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction2.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction2.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction3.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Instruction3.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Label.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Label.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Symbol.Type.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Symbol.Type.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Symbol.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/Symbol.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/allclasses-frame.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/allclasses-frame.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/allclasses-noframe.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/allclasses-noframe.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/constant-values.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/constant-values.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/deprecated-list.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/deprecated-list.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/help-doc.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/help-doc.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/index-all.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/index-all.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/index.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/index.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/overview-tree.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/overview-tree.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/package-frame.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/package-frame.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/package-list:
--------------------------------------------------------------------------------
1 | 
2 | 


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/package-summary.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/package-summary.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/package-tree.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/package-tree.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/resources/inherit.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/resources/inherit.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/kcasm/kcasm/stylesheet.css:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/kcasm/kcasm/stylesheet.css


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/Makefile:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/Makefile


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/addsub.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/addsub.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/addsub_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/addsub_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/blockram.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/blockram.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/compare3_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/compare3_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/compare3m_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/compare3m_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/int_test.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/int_test.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub_tb.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/addsub_tb.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/blockram.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/blockram.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/blockram.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/blockram.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/cmprnd3_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/cmprnd3_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/compare3_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/compare3_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/compare3m_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/compare3m_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-f.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-f.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-fn.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-fn.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-m.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-m.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p2.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p2.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p3.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p3.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p4.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p4.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p5.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-s.p5.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-t.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index-t.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/index.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/int_test.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/int_test.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/int_test.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/int_test.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze1.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze1.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze1_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze1_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze1_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze1_xst.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze2.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze2.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze2_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze2_xst.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3_xst.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3b_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3b_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3m.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3m.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3m_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3m_tb.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_alu.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_alu.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_idu.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_idu.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_inc.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_inc.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_util.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze_util.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/test.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/test.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/test.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/test.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/timescale_inc.v:
--------------------------------------------------------------------------------
1 | `timescale 100ps/10ps
2 | 


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock_ti.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock_ti.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock_ti.v.html:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/uclock_ti.v.html


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-b1.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-b1.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-b2.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-b2.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-b3.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-b3.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-c.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-c.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-i.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-i.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-up.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-up.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-x.gif:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html-x.gif


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html.css:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze/v2html.css


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1_idu_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1_idu_xst.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1_tb.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1_tb.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze1_xst.v


--------------------------------------------------------------------------------
/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze2.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze2.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze2_idu_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze2_idu_xst.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze2_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze2_xst.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_dregister_xst.v:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_dregister_xst.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_idu_xst.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_idu_xst.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_tb.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_tb.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_xst.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3_xst.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3b_tb.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3b_tb.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3m.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3m.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3m_tb.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3m_tb.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3m_xst.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze3m_xst.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister_tb.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister_tb.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_inc.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_inc.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_register.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_register.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_scratch.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_scratch.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_stack.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_stack.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_util.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_util.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/test.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/test.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/testall.sh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/testall.sh


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/basic_verilog/pacoblaze-2.2/pacoblaze/timescale_inc.v:
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1 | `timescale 100ps/10ps
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/basic_verilog/pacoblaze-2.2/pacoblaze/uclock.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/uclock.v


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/basic_verilog/pacoblaze-2.2/pacoblaze/uclock_ti.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/pacoblaze/uclock_ti.v


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/basic_verilog/pacoblaze-2.2/test/Makefile:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/Makefile


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/basic_verilog/pacoblaze-2.2/test/adc_ctrl.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/adc_ctrl.psm


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/basic_verilog/pacoblaze-2.2/test/adc_ctrl.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/adc_ctrl.rmh


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/basic_verilog/pacoblaze-2.2/test/adc_ctrl_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/adc_ctrl_rom.v


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/basic_verilog/pacoblaze-2.2/test/auto_pwm.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/auto_pwm.psm


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/basic_verilog/pacoblaze-2.2/test/auto_pwm.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/auto_pwm.rmh


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/basic_verilog/pacoblaze-2.2/test/auto_pwm_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/auto_pwm_rom.v


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/basic_verilog/pacoblaze-2.2/test/clock.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/clock.psm


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/basic_verilog/pacoblaze-2.2/test/clock.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/clock.rmh


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/basic_verilog/pacoblaze-2.2/test/clock_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/clock_rom.v


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/basic_verilog/pacoblaze-2.2/test/control.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/control.psm


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/basic_verilog/pacoblaze-2.2/test/control.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/control.rmh


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/basic_verilog/pacoblaze-2.2/test/control_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/control_rom.v


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/basic_verilog/pacoblaze-2.2/test/dac_ctrl.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/dac_ctrl.psm


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/basic_verilog/pacoblaze-2.2/test/dac_ctrl.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/dac_ctrl.rmh


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/basic_verilog/pacoblaze-2.2/test/dac_ctrl_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/dac_ctrl_rom.v


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/basic_verilog/pacoblaze-2.2/test/fc_ctrl.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/fc_ctrl.psm


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/basic_verilog/pacoblaze-2.2/test/fc_ctrl.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/fc_ctrl.rmh


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/basic_verilog/pacoblaze-2.2/test/fc_ctrl_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/fc_ctrl_rom.v


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/basic_verilog/pacoblaze-2.2/test/fg_ctrl.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/fg_ctrl.psm


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/basic_verilog/pacoblaze-2.2/test/fg_ctrl.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/fg_ctrl.rmh


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/basic_verilog/pacoblaze-2.2/test/fg_ctrl_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/fg_ctrl_rom.v


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/basic_verilog/pacoblaze-2.2/test/int_test.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/int_test.psm


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/basic_verilog/pacoblaze-2.2/test/int_test.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/int_test.rmh


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/basic_verilog/pacoblaze-2.2/test/int_test2.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/int_test2.psm


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/basic_verilog/pacoblaze-2.2/test/int_test2.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/int_test2.rmh


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/basic_verilog/pacoblaze-2.2/test/int_test2.vhd:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/int_test2.vhd


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/basic_verilog/pacoblaze-2.2/test/int_test2_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/int_test2_rom.v


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/basic_verilog/pacoblaze-2.2/test/int_test_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/int_test_rom.v


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/basic_verilog/pacoblaze-2.2/test/led_ctrl.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/led_ctrl.psm


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/basic_verilog/pacoblaze-2.2/test/led_ctrl.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/led_ctrl.rmh


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/basic_verilog/pacoblaze-2.2/test/led_ctrl_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/led_ctrl_rom.v


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/basic_verilog/pacoblaze-2.2/test/ls_test.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/ls_test.psm


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/basic_verilog/pacoblaze-2.2/test/ls_test.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/ls_test.rmh


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/basic_verilog/pacoblaze-2.2/test/ls_test_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/ls_test_rom.v


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/basic_verilog/pacoblaze-2.2/test/pb3_int.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_int.psm


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/basic_verilog/pacoblaze-2.2/test/pb3_int.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_int.rmh


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/basic_verilog/pacoblaze-2.2/test/pb3_int_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_int_rom.v


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/basic_verilog/pacoblaze-2.2/test/pb3_ret.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_ret.psm


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/basic_verilog/pacoblaze-2.2/test/pb3_ret.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_ret.rmh


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/basic_verilog/pacoblaze-2.2/test/pb3_ret_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_ret_rom.v


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/basic_verilog/pacoblaze-2.2/test/pb3_test.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_test.psm


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/basic_verilog/pacoblaze-2.2/test/pb3_test.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_test.rmh


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/basic_verilog/pacoblaze-2.2/test/pb3_test_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3_test_rom.v


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/basic_verilog/pacoblaze-2.2/test/pb3m_test.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3m_test.psm


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/basic_verilog/pacoblaze-2.2/test/pb3m_test.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3m_test.rmh


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/basic_verilog/pacoblaze-2.2/test/pb3m_test_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pb3m_test_rom.v


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/basic_verilog/pacoblaze-2.2/test/progctrl.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/progctrl.psm


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/basic_verilog/pacoblaze-2.2/test/progctrl.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/progctrl.rmh


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/basic_verilog/pacoblaze-2.2/test/progctrl_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/progctrl_rom.v


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/basic_verilog/pacoblaze-2.2/test/pwm_ctrl.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pwm_ctrl.psm


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/basic_verilog/pacoblaze-2.2/test/pwm_ctrl.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pwm_ctrl.rmh


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/basic_verilog/pacoblaze-2.2/test/pwm_ctrl_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/pwm_ctrl_rom.v


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/basic_verilog/pacoblaze-2.2/test/security.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/security.psm


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/basic_verilog/pacoblaze-2.2/test/security.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/security.rmh


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/basic_verilog/pacoblaze-2.2/test/security_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/security_rom.v


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/basic_verilog/pacoblaze-2.2/test/sha1prog.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/sha1prog.psm


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/basic_verilog/pacoblaze-2.2/test/sha1prog.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/sha1prog.rmh


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/basic_verilog/pacoblaze-2.2/test/sha1prog_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/sha1prog_rom.v


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/basic_verilog/pacoblaze-2.2/test/spi_prog.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/spi_prog.psm


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/basic_verilog/pacoblaze-2.2/test/spi_prog.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/spi_prog.rmh


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/basic_verilog/pacoblaze-2.2/test/spi_prog_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/spi_prog_rom.v


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/basic_verilog/pacoblaze-2.2/test/test3.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/test3.psm


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/basic_verilog/pacoblaze-2.2/test/test3.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/test3.rmh


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/basic_verilog/pacoblaze-2.2/test/test3_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/test3_rom.v


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/basic_verilog/pacoblaze-2.2/test/testint.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/testint.psm


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/basic_verilog/pacoblaze-2.2/test/testint.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/testint.rmh


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/basic_verilog/pacoblaze-2.2/test/testint_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/testint_rom.v


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/basic_verilog/pacoblaze-2.2/test/testsub.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/testsub.psm


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/basic_verilog/pacoblaze-2.2/test/testsub.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/testsub.rmh


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/basic_verilog/pacoblaze-2.2/test/testsub_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/testsub_rom.v


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/basic_verilog/pacoblaze-2.2/test/uclock.psm:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/uclock.psm


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/basic_verilog/pacoblaze-2.2/test/uclock.rmh:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/uclock.rmh


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/basic_verilog/pacoblaze-2.2/test/uclock_rom.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/test/uclock_rom.v


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/basic_verilog/pacoblaze-2.2/xilinx/kcpsm2.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/xilinx/kcpsm3.v


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/basic_verilog/pacoblaze-2.2/xilinx/unisims/FD.v:
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/basic_verilog/pacoblaze-2.2/xilinx/unisims/FDE.v:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/xilinx/unisims/FDE.v


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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/pacoblaze-2.2/xilinx/unisims/FDR.v


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/basic_verilog/pacoblaze-2.2/xilinx/unisims/FDRE.v:
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/basic_verilog/scripts/hard_clean_modelsim.bat:
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/basic_verilog/scripts/mem_writer_adv_examples/1024cos.mem:
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/basic_verilog/scripts/mem_writer_examples/16x16bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/16x16bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/16x32bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/16x32bit_random.mem:
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 1 | 0
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 6 | 5
 7 | 6
 8 | 7
 9 | 8
10 | 9
11 | A
12 | B
13 | C
14 | D
15 | E
16 | F
17 | 


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/basic_verilog/scripts/mem_writer_examples/16x8bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/2048x32bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/2048x32bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/256x16bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/256x16bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/256x32bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/256x32bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/32x16bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/32x16bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/32x32bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/32x32bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/4096x32bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/4096x32bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/512x32bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/512x32bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/64x16bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/64x16bit_random.mem:
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/basic_verilog/scripts/mem_writer_examples/64x32bit_linear.mem:
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/basic_verilog/scripts/mem_writer_examples/64x32bit_random.mem:
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/basic_verilog/scripts/modelsim_compile.bat:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/basic_verilog/scripts/modelsim_compile.sh


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/basic_verilog/scripts/update_git_repos.sh:
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/basic_verilog/scripts/write_avalon_mm_from_file.tcl:
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/basic_verilog/scripts_for_intel_hls/b.bat:
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/basic_verilog/scripts_for_intel_hls/build_recursively.bat:
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/basic_verilog/scripts_for_intel_hls/hls_type_size_win64.txt:
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/basic_verilog/scripts_for_intel_hls/i.bat:
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/basic_verilog/scripts_for_intel_hls/test.cpp:
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/basic_verilog/set_reset.sv:
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/basic_verilog/set_reset_comb.sv:
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/basic_verilog/soft_latch.sv:
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/basic_verilog/soft_latch_tb.sv:
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/basic_verilog/spi_master.sv:
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/basic_verilog/spi_master_tb.sv:
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/basic_verilog/true_dual_port_write_first_2_clock_ram.sv:
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/basic_verilog/true_single_port_write_first_ram.sv:
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/basic_verilog/uart_debug_printer.sv:
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/basic_verilog/uart_rx.sv:
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/basic_verilog/uart_rx_shifter.sv:
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/basic_verilog/uart_tx.sv:
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/basic_verilog/uart_tx_rx_shifter_tb.png:
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/basic_verilog/uart_tx_rx_shifter_tb.sv:
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/basic_verilog/uart_tx_shifter.sv:
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/basic_verilog/vm80a.v:
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/generic_systemverilog_designs_library/LICENSE:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/generic_systemverilog_designs_library/LICENSE


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/generic_systemverilog_designs_library/README.md:
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https://raw.githubusercontent.com/suisuisi/basic_systemverilog/HEAD/generic_systemverilog_designs_library/README.md


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/generic_systemverilog_designs_library/binary_counter/tb.sv:
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/generic_systemverilog_designs_library/demultiplexer/demux.sv:
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/generic_systemverilog_designs_library/full_adder/full_adder.sv:
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/generic_systemverilog_designs_library/multiplexer/mux.sv:
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