├── dff8.v ├── shift_reg.v ├── filt_weight_update.v ├── lms_adapt_filt_4tap.v └── da8.v /dff8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module dff8(Din,Q,clk,rst); 4 | 5 | input signed [7:0]Din; 6 | input clk,rst; 7 | output reg signed [7:0] Q; 8 | always@(posedge clk or posedge rst) 9 | begin 10 | if(rst) 11 | Q<=0; 12 | else 13 | Q<=Din; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /shift_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module shift_reg(xin,clk,rst,x0,x1,x2,x3); 4 | 5 | input signed [7:0] xin; 6 | input clk,rst; 7 | output reg signed [7:0] x0,x1,x2,x3; 8 | 9 | always@(posedge clk or posedge rst) 10 | if(rst) 11 | begin 12 | x3<=8'd0; 13 | x2<=8'd0; 14 | x1<=8'd0; 15 | x0<=8'd0; 16 | end 17 | else 18 | begin 19 | x3<=x2; 20 | x2<=x1; 21 | x1<=x0; 22 | x0<=xin; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /filt_weight_update.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module filt_weight_update( clk,rst,xd0,xd1,xd2,xd3,hn0,hn1,hn2,hn3, errr); 4 | 5 | input signed [9:0] errr; 6 | input clk,rst; 7 | input signed [7:0] xd0, xd1, xd2, xd3; 8 | output reg signed [7:0] hn0, hn1, hn2, hn3; 9 | 10 | always@( posedge clk or posedge rst) 11 | begin 12 | if(rst) 13 | begin 14 | hn0 <= 8'd1; 15 | hn1 <= 8'd1; 16 | hn2 <= 8'd1; 17 | hn3 <= 8'd1; 18 | end 19 | else 20 | begin 21 | hn0 <= hn0 + (((errr*xd0)>>>4) - ((errr*xd0)>>>6)); 22 | hn1 <= hn1 + (((errr*xd1)>>>4) - ((errr*xd1)>>>6)); 23 | hn2 <= hn2 + (((errr*xd2)>>>4) - ((errr*xd2)>>>6)); 24 | hn3 <= hn3 + (((errr*xd3)>>>4) - ((errr*xd3)>>>6)); 25 | end 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /lms_adapt_filt_4tap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lms_adapt_filt_4tap (clk,rst,xin,din,errr,filt_out); 4 | 5 | input signed [7:0] xin; 6 | input signed [9:0] din; 7 | input clk,rst; 8 | output signed [9:0] filt_out; 9 | output signed [9:0] errr; 10 | 11 | /////////////////////////////////////////////////////////////// 12 | wire signed [7:0] x[0:3] ,xd[0:3]; 13 | wire signed [7:0] hn[0:3], h[0:3]; 14 | wire signed [9:0] y_out0; 15 | 16 | shift_reg ad16(xin,clk,rst,x[0],x[1],x[2],x[3]); 17 | 18 | filt_weight_update co_eff( clk,rst,xd[0],xd[1],xd[2],xd[3],hn[0],hn[1],hn[2],hn[3], errr); 19 | 20 | da8 block0(clk,rst,x[0],x[1],x[2],x[3],hn[0],hn[1],hn[2],hn[3],y_out0); 21 | 22 | dff8 D0(x[0],xd[0],clk,rst); 23 | dff8 D1(x[1],xd[1],clk,rst); 24 | dff8 D2(x[2],xd[2],clk,rst); 25 | dff8 D3(x[3],xd[3],clk,rst); 26 | 27 | assign filt_out = y_out0; 28 | assign errr = din - filt_out; 29 | 30 | endmodule 31 | 32 | 33 | 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /da8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module da8 (clk,rst,x0,x1,x2,x3,h0,h1,h2,h3,filter_out); 4 | 5 | input clk,rst; 6 | wire [79:0]yy; 7 | reg signed [18:0] y_out; // filter output 8 | input signed [7:0] x0,x1,x2,x3; //input data 9 | input signed [7:0] h0,h1,h2,h3; // filter co-efficients 10 | integer i; 11 | output signed [9:0] filter_out; 12 | 13 | //////////////////////////////////////// 14 | /////assigning address - ROM contents/// 15 | //////////////////////////////////////// 16 | 17 | wire [3:0] lut_addr [0:7] ; 18 | 19 | assign lut_addr[0] = {x3[0],x2[0], x1[0], x0[0]}; 20 | assign lut_addr[1] = {x3[1],x2[1], x1[1], x0[1]}; 21 | assign lut_addr[2] = {x3[2],x2[2], x1[2], x0[2]}; 22 | assign lut_addr[3] = {x3[3],x2[3], x1[3], x0[3]}; 23 | assign lut_addr[4] = {x3[4],x2[4], x1[4], x0[4]}; 24 | assign lut_addr[5] = {x3[5],x2[5], x1[5], x0[5]}; 25 | assign lut_addr[6] = {x3[6],x2[6], x1[6], x0[6]}; 26 | assign lut_addr[7] = {x3[7],x2[7], x1[7], x0[7]}; 27 | 28 | reg signed [9:0] C_out [0:7]; 29 | 30 | always @(lut_addr) 31 | begin 32 | for (i=0 ; i<8 ; i=i+1 ) 33 | begin 34 | case(lut_addr[i]) 35 | 4'b0000: C_out[i] = 0; 36 | 4'b0001: C_out[i] = h0; 37 | 4'b0010: C_out[i] = h1; 38 | 4'b0011: C_out[i] = h1+h0; 39 | 4'b0100: C_out[i] = h2; 40 | 4'b0101: C_out[i] = h2+h0; 41 | 4'b0110: C_out[i] = h2+h1; 42 | 4'b0111: C_out[i] = h2+h1+h0; 43 | 4'b1000: C_out[i] = h3; 44 | 4'b1001: C_out[i] = h3+h0; 45 | 4'b1010: C_out[i] = h3+h1; 46 | 4'b1011: C_out[i] = h3+h1+h0; 47 | 4'b1100: C_out[i] = h3+h2; 48 | 4'b1101: C_out[i] = h3+h2+h0; 49 | 4'b1110: C_out[i] = h3+h2+h1; 50 | 4'b1111: C_out[i] = h3+h2+h1+h0; 51 | default: C_out[i] = 0; 52 | endcase 53 | if( i == 7 ) 54 | C_out[7] = -C_out[7]; 55 | end 56 | end 57 | 58 | assign yy = {C_out[7],C_out[6],C_out[5],C_out[4],C_out[3],C_out[2],C_out[1],C_out[0]}; 59 | 60 | /////////////////////////////////// 61 | /// shift accumulation process///// 62 | /////////////////////////////////// 63 | 64 | always @ (posedge clk or posedge rst) 65 | begin 66 | if(rst) 67 | y_out <= 0; 68 | else 69 | begin 70 | y_out = 0; 71 | for(i=10;i<81;i=i+10) 72 | begin 73 | case(i) 74 | 10: begin 75 | y_out = (({yy[10-1:10-10],8'b0})+y_out) ; 76 | y_out = y_out >>> 1; 77 | end 78 | 79 | 20: begin 80 | y_out = (({yy[20-1:20-10],8'b0000000000})+y_out) ; 81 | y_out = y_out >>> 1; 82 | end 83 | 84 | 30: begin 85 | y_out = (({yy[30-1:30-10],8'b0000000000})+y_out) ; 86 | y_out = y_out >>> 1; 87 | end 88 | 89 | 40: begin 90 | y_out = (({yy[40-1:40-10],8'b0000000000})+y_out) ; 91 | y_out = y_out >>> 1; 92 | end 93 | 50: begin 94 | y_out = (({yy[50-1:50-10],8'b0000000000})+y_out) ; 95 | y_out = y_out >>> 1; 96 | end 97 | 98 | 60: begin 99 | y_out = (({yy[60-1:60-10],8'b0000000000})+y_out) ; 100 | y_out = y_out >>> 1; 101 | end 102 | 103 | 70: begin 104 | y_out = (({yy[70-1:70-10],8'b0000000000})+y_out) ; 105 | y_out = y_out >>> 1; 106 | end 107 | 108 | 80: begin 109 | y_out = (({yy[80-1:80-10],8'b0000000000})+y_out) ; 110 | y_out = y_out >>> 1; 111 | end 112 | default: y_out<= 0; 113 | endcase 114 | end 115 | end 116 | end 117 | 118 | assign filter_out = y_out[9:0]; 119 | 120 | endmodule 121 | --------------------------------------------------------------------------------