├── Class Assignments ├── WEEK2 19.02.19-23.02.19.docx ├── Week0-15.01.19 to 9.2.19.docx ├── sample question.xlsx ├── week1 11.2.19 to 16.2.19.docx └── week3 ca.docx ├── Lab Assignment └── create ├── Verilog code ├── example.vl ├── example_test.vl ├── examplev2.vl ├── examplev3.vl ├── pipe.vl ├── pipe_test.vl ├── ram.vl └── ram_test.vl └── previous years questions ├── 1444733539cs-btech-cse-new-sem-4th-cs-403-2013_examveda.pdf ├── 1444734241cs-btech-even-cse-sem-4th-cs-403-2014_examveda.pdf ├── 1492158446cs-btech-cse-even-sem-4-cs-403-2015-16-Examveda.pdf ├── 1495626894cs-btech-cse-even-sem-4-cs-403-2015-examveda.pdf └── 1518337204cs-btech-cse-even-sem-4-cs-403-2016-17_examveda.pdf /Class Assignments/WEEK2 19.02.19-23.02.19.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/Class Assignments/WEEK2 19.02.19-23.02.19.docx -------------------------------------------------------------------------------- /Class Assignments/Week0-15.01.19 to 9.2.19.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/Class Assignments/Week0-15.01.19 to 9.2.19.docx -------------------------------------------------------------------------------- /Class Assignments/sample question.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/Class Assignments/sample question.xlsx -------------------------------------------------------------------------------- /Class Assignments/week1 11.2.19 to 16.2.19.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/Class Assignments/week1 11.2.19 to 16.2.19.docx -------------------------------------------------------------------------------- /Class Assignments/week3 ca.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/Class Assignments/week3 ca.docx -------------------------------------------------------------------------------- /Lab Assignment/create: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Verilog code/example.vl: -------------------------------------------------------------------------------- 1 | module mux16to1(in,sel,out); 2 | input[15:0] in; 3 | input[3:0] sel; 4 | output out; 5 | assign out=in[sel]; 6 | endmodule -------------------------------------------------------------------------------- /Verilog code/example_test.vl: -------------------------------------------------------------------------------- 1 | module muxtest; 2 | reg[15:0] A; reg[3:0] S; wire F; 3 | mux16to1 M(.in(A),.sel(S),.out(F)); 4 | initial 5 | begin 6 | $dumpfile("mux16to1.vcd"); 7 | $dumpvars(0,muxtest); 8 | $monitor($time,"A=%h,S=%h,F=%b",A,S,F); 9 | #5 A=16'h3f0a;S=4'h0; 10 | #5 S=4'h1; 11 | #5 S=4'h6; 12 | #5 S=4'hc; 13 | #5 $finish; 14 | end 15 | endmodule -------------------------------------------------------------------------------- /Verilog code/examplev2.vl: -------------------------------------------------------------------------------- 1 | module mux4to1(in,sel,out); 2 | input[3:0] in; 3 | input[1:0] sel; 4 | output out; 5 | assign out=in[sel]; 6 | endmodule 7 | 8 | module mux16to1(in,sel,out); 9 | input[15:0] in; 10 | input[3:0] sel; 11 | output out; 12 | wire[3:0] t; 13 | 14 | mux4to1 M0 (in[3:0],sel[1:0],t[0]); 15 | mux4to1 M1 (in[7:4],sel[1:0],t[1]); 16 | mux4to1 M2 (in[11:8],sel[1:0],t[2]); 17 | mux4to1 M3 (in[15:12],sel[1:0],t[3]); 18 | mux4to1 M4 (t,sel[3:2],out); 19 | endmodule -------------------------------------------------------------------------------- /Verilog code/examplev3.vl: -------------------------------------------------------------------------------- 1 | 2 | module mux2to1(in,sel,out); 3 | input[1:0] in; 4 | input sel; 5 | output out; 6 | assign out=in[sel]; 7 | endmodule 8 | 9 | module mux4to1(in,sel,out); 10 | input[3:0] in; 11 | input[1:0] sel; 12 | output out; 13 | wire[1:0] t; 14 | 15 | mux2to1 M0 (in[1:0],sel[0],t[0]); 16 | mux2to1 M1 (in[3:2],sel[0],t[1]); 17 | mux2to1 M4 (t,sel[1],out); 18 | endmodule 19 | 20 | 21 | module mux16to1(in,sel,out); 22 | input[15:0] in; 23 | input[3:0] sel; 24 | output out; 25 | wire[3:0] t; 26 | 27 | mux4to1 M0 (in[3:0],sel[1:0],t[0]); 28 | mux4to1 M1 (in[7:4],sel[1:0],t[1]); 29 | mux4to1 M2 (in[11:8],sel[1:0],t[2]); 30 | mux4to1 M3 (in[15:12],sel[1:0],t[3]); 31 | mux4to1 M4 (t,sel[3:2],out); 32 | endmodule -------------------------------------------------------------------------------- /Verilog code/pipe.vl: -------------------------------------------------------------------------------- 1 | module pipe_ex(F,A,B,C,D,clk); 2 | parameter N=10; 3 | input [N-1:0] A,B,C,D; 4 | input clk; 5 | output [N-1:0] F; 6 | reg [N-1:0] L12_x1,L12_x2,L12_D,L23_x3,L23_D,L34_F; 7 | assign F=L34_F; 8 | always @(posedge clk) 9 | begin 10 | L12_x1<=#4 A+B; 11 | L12_x2<=#4 C-D; 12 | L12_D<=D; 13 | 14 | L23_x3<=#4 L12_x1+L12_x2; 15 | L23_D<=L12_D; 16 | 17 | L34_F<=#6 L23_x3*L23_D; 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /Verilog code/pipe_test.vl: -------------------------------------------------------------------------------- 1 | module pipe_test; 2 | parameter N=10; 3 | reg [N-1:0] A,B,C,D; 4 | reg clk; 5 | wire [N-1:0] F; 6 | pipe_ex MYPIPE(F,A,B,C,D,clk); 7 | initial clk=0; 8 | always #10 clk=~clk; 9 | initial 10 | begin 11 | #5 A=10;B=12;C=6;D=3; 12 | #20 A=10;B=10;C=5;D=3; 13 | #20 A=20;B=11;C=1;D=4; 14 | #20 A=15;B=10;C=8;D=2; 15 | #20 A=8;B=15;C=5;D=0; 16 | #20 A=10;B=20;C=5;D=3; 17 | #20 A=10;B=10;C=30;D=1; 18 | #20 A=30;B=1;C=2;D=4; 19 | end 20 | initial 21 | begin 22 | $dumpfile("pipe_vcd"); 23 | $dumpvars(0,pipe_test); 24 | $monitor("Time:%d,F=%d",$time,F); 25 | #300 $finish; 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /Verilog code/ram.vl: -------------------------------------------------------------------------------- 1 | module ram2(data_in,data_out,addr,wr,cs); 2 | input [9:0] addr; 3 | input [7:0] data_in; 4 | output [7:0] data_out; 5 | input wr,cs; 6 | 7 | reg [7:0] mem [1023:0]; 8 | assign data_out=mem[addr]; 9 | always @(wr or cs) 10 | if(wr) mem[addr]=data_in; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /Verilog code/ram_test.vl: -------------------------------------------------------------------------------- 1 | module ram_test(); 2 | reg [9:0] address; 3 | reg [7:0] data_in; 4 | wire [7:0] data_out; 5 | reg write,select; 6 | integer k,myseed; 7 | initial myseed=30; 8 | 9 | ram2 ram1(data_in,data_out,address,write,select); 10 | 11 | initial 12 | begin 13 | for(k=0;k<=1023;k=k+1) 14 | begin 15 | address=k; 16 | data_in=(k+k)%256; 17 | write=1; 18 | select=1; 19 | #2 write=0;select=0; 20 | end 21 | repeat(20) 22 | begin 23 | #2 address=$random(myseed)%1023; 24 | write=0;select=1; 25 | $display("Addresss:%5d,Data:%4d",address,data_out); 26 | end 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /previous years questions/1444733539cs-btech-cse-new-sem-4th-cs-403-2013_examveda.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/previous years questions/1444733539cs-btech-cse-new-sem-4th-cs-403-2013_examveda.pdf -------------------------------------------------------------------------------- /previous years questions/1444734241cs-btech-even-cse-sem-4th-cs-403-2014_examveda.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/previous years questions/1444734241cs-btech-even-cse-sem-4th-cs-403-2014_examveda.pdf -------------------------------------------------------------------------------- /previous years questions/1492158446cs-btech-cse-even-sem-4-cs-403-2015-16-Examveda.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/previous years questions/1492158446cs-btech-cse-even-sem-4-cs-403-2015-16-Examveda.pdf -------------------------------------------------------------------------------- /previous years questions/1495626894cs-btech-cse-even-sem-4-cs-403-2015-examveda.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/previous years questions/1495626894cs-btech-cse-even-sem-4-cs-403-2015-examveda.pdf -------------------------------------------------------------------------------- /previous years questions/1518337204cs-btech-cse-even-sem-4-cs-403-2016-17_examveda.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sujitraha01/Computer-Architecture/9dc4e9454e1c9bc9e1057d606f89a52b91ee7043/previous years questions/1518337204cs-btech-cse-even-sem-4-cs-403-2016-17_examveda.pdf --------------------------------------------------------------------------------