├── doc └── tussle.pdf ├── .gitignore ├── tests ├── syntestbench │ ├── README.md │ └── syntestbench.py └── testbench │ ├── tussle_testbench11.vhd │ ├── tussle_testbench3.vhd │ ├── tussle_testbench4.vhd │ ├── tussle_testbench10.vhd │ ├── tussle_testbench5.vhd │ ├── tussle_testbench6.vhd │ ├── tussle_testbench9.vhd │ ├── tussle_testbench7.vhd │ ├── tussle_testbench8.vhd │ ├── tussle_testbench15.vhd │ ├── tussle_testbench1.vhd │ ├── tussle_testbench2.vhd │ ├── tussle_testbench13.vhd │ ├── tussle_testbench12.vhd │ ├── README.md │ └── tussle_testbench14.vhd ├── LICENSE ├── README.md └── src ├── decide_branch.vhd ├── Unit_Clause.vhd ├── Stack_bool.vhd ├── Common.vhd ├── Stack_integer.vhd ├── Stack_formula.vhd ├── Pure_Literal.vhd ├── read_store.vhd ├── Propagate_Literal.vhd ├── DB_kernel.vhd ├── tusSAT_top.vhd └── testing101.vhd /doc/tussle.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sumith1896/tusSAT/HEAD/doc/tussle.pdf -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !*.vhd 3 | !*.txt 4 | !*.md 5 | !.gitignore 6 | !.git/ 7 | !*/ 8 | !*.py 9 | !*.pdf 10 | !LICENSE 11 | 12 | -------------------------------------------------------------------------------- /tests/syntestbench/README.md: -------------------------------------------------------------------------------- 1 | We have incorported a testbench generation code in form of syntestbench python script. 2 | Dependency : Python, SymPy 3 | 4 | Usage: 5 | do 6 | ``` 7 | $ python syntestbench.py > testbench.vhd 8 | ``` 9 | then enter 10 | - number of literals 11 | - number of clauses 12 | - boolean expression 13 | 14 | The code will then be generated in testbench.vhd 15 | 16 | For boolean expressions(these need not be in CNF) 17 | Use & for And, ~ for negation and | for Or 18 | Example : (p | q) & (~p | q) & (p | ~q) 19 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2016 Sumith and Shubham Goel 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## tusSAT 2 | 3 | A hardware SAT solver implementation in VHDL for our [CS 254: Digital Logic Design](https://www.cse.iitb.ac.in/~supratik/courses/cs226/) course project under the guidance of [Prof. Supratik Chakraborty](https://www.cse.iitb.ac.in/~supratik/). The team name of the members `tussle`, hence the name `tusSAT`. 4 | 5 | ## Usage 6 | 7 | You can add the sources to a project and use `tusSAT_top.vhd` as your top module.
8 | You can get ready-to-import project here [https://cse.iitb.ac.in/~sumith/projects/tusSAT.tar.gz](http://cse.iitb.ac.in/~sumith/projects/tusSAT.tar.gz). 9 | 10 | ## Doc 11 | 12 | Our project documentation is in the `doc` section. The code has inline comments added too. 13 | 14 | ## Testing 15 | 16 | The tests are in `tests` subdirectory. The `testbench` are some select testbenches mostly from [DIMACS Satisfiability challenges](ftp://dimacs.rutgers.edu/pub/challenge/satisfiability/benchmarks/cnf/). You can also generate your `.vhd` testbench for your own boolean expression using `syntestbench.py`. This converts the given boolean expression to a `.vhd` testbench. This has [SymPy](http://www.sympy.org/en/index.html) as it's dependency. More detailed instructions can be found in it's readme. 17 | 18 | ## Open source 19 | 20 | The project will be maintained open source under MIT license.
21 | We are welcome for contributions and design suggestions. We are also open to very general VHDL suggestions as we are rookies in this area. Please open an issue in this repository or ping us.
22 | If you send in a PR, ping [@Sumith1896](https://github.com/Sumith1896) or [@shubham-goel](https://github.com/shubham-goel) for review. 23 | -------------------------------------------------------------------------------- /src/decide_branch.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 02:55:19 04/05/2016 6 | -- Design Name: 7 | -- Module Name: decide_branch - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.common.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity decide_branch is 34 | Port ( clock : in STD_LOGIC; 35 | reset : in STD_LOGIC; 36 | find : in STD_LOGIC; 37 | formula_in : in formula; 38 | ended : out STD_LOGIC; 39 | lit_out : out lit); 40 | end decide_branch; 41 | 42 | architecture Behavioral of decide_branch is 43 | signal formula_s : formula := ZERO_FORMULA; 44 | signal lit_s : lit := ZERO_LIT; 45 | signal iterator : INTEGER := 0; 46 | signal computing : STD_LOGIC := '0'; 47 | signal finished : STD_LOGIC := '0'; 48 | 49 | begin 50 | 51 | lit_out <= lit_s; 52 | 53 | process(clock, reset) 54 | begin 55 | --RESET-- 56 | if reset='1' then 57 | formula_s <= ZERO_FORMULA; 58 | lit_s <= ZERO_LIT; 59 | iterator <= 0; 60 | computing <= '0'; 61 | finished <= '0'; 62 | ended <= '0'; 63 | elsif rising_edge(clock) then 64 | ended <= '0'; 65 | if find = '1' and computing = '0' then 66 | formula_s <= formula_in; 67 | computing <= '1'; 68 | finished <= '0'; 69 | ended <= '0'; 70 | elsif computing = '1' then 71 | if formula_s.clauses(iterator).len = 0 then 72 | iterator <= iterator + 1; 73 | else 74 | lit_s.num <= formula_s.clauses(iterator).lits(0).num; 75 | lit_s.val <= not formula_s.clauses(iterator).lits(0).val; 76 | computing <= '0'; 77 | ended <= '1'; 78 | end if; 79 | --ended <= '0'; 80 | --elsif finished = '1' then 81 | -- computing <= 0; 82 | end if; 83 | end if; 84 | 85 | end process; 86 | end Behavioral; 87 | 88 | -------------------------------------------------------------------------------- /src/Unit_Clause.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:17:40 04/04/2016 6 | -- Design Name: 7 | -- Module Name: Unit_Clause - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use work.Common.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity Unit_Clause is 35 | Port ( clock : in STD_LOGIC; 36 | reset : in STD_LOGIC; 37 | find : in STD_LOGIC; 38 | in_formula : in formula; 39 | ended : out STD_LOGIC; 40 | found : out STD_LOGIC; 41 | lit_found : out lit); 42 | end Unit_Clause; 43 | 44 | architecture Behavioral of Unit_Clause is 45 | 46 | signal s_in_formula : formula := ZERO_FORMULA; 47 | signal s_ended : STD_LOGIC := '0'; 48 | signal s_found : STD_LOGIC := '0'; 49 | signal s_lit_found : lit := ZERO_LIT; 50 | signal s_finding : STD_LOGIC := '0'; 51 | signal i : INTEGER := 0; 52 | begin 53 | ended <= s_ended; 54 | found <= s_found; 55 | lit_found <= s_lit_found; 56 | 57 | process(clock,reset) 58 | begin 59 | if reset='1' then 60 | s_ended <= '0'; 61 | s_found <= '0'; 62 | elsif rising_edge(clock) then 63 | s_ended <= '0'; 64 | if find='1' and s_finding='0' then 65 | s_in_formula <= in_formula; 66 | s_finding <= '1'; 67 | s_ended <= '0'; 68 | i <= 0; 69 | elsif s_finding = '1' then 70 | 71 | --for i in 0 to NUMBER_CLAUSES-1 loop 72 | -- exit when ((i = s_in_formula.len)or(_finished='1')); 73 | -- if (s_in_formula.clauses(i)).len = 1 then 74 | -- _found <= '1'; 75 | -- _finished <= '1'; 76 | -- s_lit_found <= (s_in_formula.clauses(i)).lits[0]; 77 | -- end if ; 78 | --end loop ; 79 | --s_ended <= '1'; 80 | 81 | if((i < s_in_formula.len) and (i < NUMBER_CLAUSES)) then 82 | if s_in_formula.clauses(i).len = 1 then 83 | s_finding <= '0'; 84 | s_found <= '1'; 85 | s_ended <= '1'; 86 | s_lit_found <= s_in_formula.clauses(i).lits(0); 87 | else 88 | s_ended <= '0'; 89 | end if; 90 | else 91 | s_finding <= '0'; 92 | s_ended <= '1'; 93 | s_found <= '0'; 94 | end if; 95 | i <= i+1; 96 | end if; 97 | end if; 98 | 99 | end process ; 100 | 101 | end Behavioral; 102 | 103 | -------------------------------------------------------------------------------- /src/Stack_bool.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 02:41:23 04/02/2016 6 | -- Design Name: 7 | -- Module Name: Stack_bool - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use work.Common.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity Stack_bool is 35 | 36 | Port ( clock : in STD_LOGIC; 37 | reset : in STD_LOGIC; 38 | wr_en : in STD_LOGIC; 39 | pop : in STD_LOGIC; 40 | din : in STD_LOGIC; 41 | dout : out STD_LOGIC; 42 | front : out STD_LOGIC; 43 | full : out STD_LOGIC; 44 | empty : out STD_LOGIC); 45 | end Stack_bool; 46 | 47 | architecture Behavioral of Stack_bool is 48 | --DATA VARIABLES 49 | type mem_type is array (bool_stack_size - 1 downto 0) of STD_LOGIC; 50 | signal data : mem_type := (others => '0'); 51 | signal curr_size : INTEGER := 0; 52 | 53 | --OTHER Vars 54 | signal data_in : STD_LOGIC; 55 | signal data_out : STD_LOGIC; 56 | signal full_signal : STD_LOGIC := '0'; 57 | signal empty_signal : STD_LOGIC := '1'; 58 | 59 | begin 60 | 61 | data_in <= din; 62 | dout <= data_out; 63 | full <= full_signal; 64 | empty <= empty_signal; 65 | 66 | process(clock,reset) 67 | variable temp : INTEGER := curr_size; 68 | begin 69 | --RESET 70 | if reset='1' then 71 | data <= (others=> '0'); 72 | curr_size <= 0; 73 | data_out <= '0'; 74 | empty_signal <= '1'; 75 | full_signal <= '0'; 76 | front <= '0'; 77 | 78 | elsif rising_edge(clock) then 79 | -- PUSH 80 | if wr_en='1' and full_signal='0' then 81 | data(curr_size) <= data_in; 82 | curr_size <= curr_size + 1; 83 | temp := temp + 1; 84 | 85 | --POP 86 | elsif pop = '1' and empty_signal='0' then 87 | data_out <= data(curr_size-1); 88 | curr_size <= curr_size - 1; 89 | temp := temp - 1; 90 | end if; 91 | 92 | --FRONT 93 | if temp > 0 then 94 | front <= data(temp-1); 95 | end if; 96 | 97 | --SET_SIGNALS 98 | if temp=(bool_stack_size) then 99 | full_signal <= '1'; 100 | empty_signal <= '0'; 101 | elsif temp=0 then 102 | full_signal <= '0'; 103 | empty_signal <= '1'; 104 | else 105 | full_signal <= '0'; 106 | empty_signal <= '0'; 107 | end if; 108 | 109 | end if; 110 | end process ; 111 | end Behavioral; 112 | 113 | -------------------------------------------------------------------------------- /src/Common.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Package File Template 3 | -- 4 | -- Purpose: This package defines supplemental types, subtypes, 5 | -- constants, and functions 6 | -- 7 | -- To use any of the example code shown below, uncomment the lines and modify as necessary 8 | -- 9 | 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.all; 12 | 13 | package Common is 14 | 15 | -- type is 16 | -- record 17 | -- : std_logic_vector( 7 downto 0); 18 | -- : std_logic; 19 | -- end record; 20 | -- 21 | -- Declare constants 22 | -- 23 | 24 | constant NUMBER_CLAUSES : INTEGER := 1000; 25 | constant NUMBER_LITERALS : INTEGER := 64; 26 | constant LIT_RANGE_ST : INTEGER := 0; 27 | constant LIT_RANGE_END : INTEGER := NUMBER_LITERALS; 28 | constant BOOL_STACK_SIZE : INTEGER := NUMBER_LITERALS; 29 | constant LIT_STACK_SIZE : INTEGER := NUMBER_LITERALS; 30 | constant FORMULA_STACK_SIZE : INTEGER := NUMBER_LITERALS; 31 | 32 | type lit is 33 | record 34 | num : INTEGER range lit_range_st to lit_range_end; 35 | val : std_logic; 36 | end record; 37 | type lit_array is array(number_literals-1 downto 0) of lit; 38 | 39 | type clause is 40 | record 41 | lits : lit_array; 42 | len : INTEGER range 0 to number_literals; 43 | end record; 44 | type clause_array is array(number_clauses-1 downto 0) of clause; 45 | 46 | type formula is 47 | record 48 | clauses : clause_array; 49 | len : INTEGER range 0 to number_clauses; 50 | end record; 51 | type formula_array is array(formula_stack_size downto 0) of formula; 52 | 53 | constant ZERO_LIT : lit := (num=>0,val=>'0'); 54 | constant ZERO_LIT_ARRAY : lit_array := (others => zero_lit); 55 | constant ZERO_CLAUSE : clause := (lits=>zero_lit_array,len=>0); 56 | constant ZERO_CLAUSE_ARRAY : clause_array := (others => zero_clause); 57 | constant ZERO_FORMULA : formula := (clauses=>zero_clause_array,len=>0); 58 | constant ZERO_FORMULA_ARRAY : formula_array := (others => zero_formula); 59 | -- 60 | -- Declare functions and procedure 61 | -- 62 | -- function (signal : in ) return ; 63 | -- procedure ( : in ); 64 | -- 65 | end Common; 66 | 67 | package body Common is 68 | 69 | ---- Example 1 70 | -- function (signal : in ) return is 71 | -- variable : ; 72 | -- begin 73 | -- := xor ; 74 | -- return ; 75 | -- end ; 76 | 77 | ---- Example 2 78 | -- function (signal : in ; 79 | -- signal : in ) return is 80 | -- begin 81 | -- if ( = '1') then 82 | -- return ; 83 | -- else 84 | -- return 'Z'; 85 | -- end if; 86 | -- end ; 87 | 88 | ---- Procedure Example 89 | -- procedure ( : in ) is 90 | -- 91 | -- begin 92 | -- 93 | -- end ; 94 | 95 | end Common; 96 | -------------------------------------------------------------------------------- /src/Stack_integer.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 01:13:23 04/02/2016 6 | -- Design Name: 7 | -- Module Name: Stack_integer - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use work.Common.all; 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity Stack_integer is 34 | 35 | Port ( clock : in STD_LOGIC; 36 | reset : in STD_LOGIC; 37 | wr_en : in STD_LOGIC; 38 | pop : in STD_LOGIC; 39 | din : in lit; 40 | dout : out lit; 41 | front : out lit; 42 | full : out STD_LOGIC; 43 | empty : out STD_LOGIC); 44 | end Stack_integer; 45 | 46 | architecture Behavioral of Stack_integer is 47 | --DATA VARIABLES 48 | type mem_type is array (lit_stack_size-1 downto 0) of lit; 49 | signal data : mem_type := (others => zero_lit); 50 | signal curr_size : INTEGER := 0; 51 | 52 | --OTHER Vars 53 | signal data_in : lit; 54 | signal data_out : lit; 55 | signal full_signal : STD_LOGIC := '0'; 56 | signal empty_signal : STD_LOGIC := '1'; 57 | begin 58 | data_in <= din; 59 | dout <= data_out; 60 | full <= full_signal; 61 | empty <= empty_signal; 62 | 63 | process(clock,reset) 64 | variable temp : INTEGER := curr_size; 65 | begin 66 | --RESET 67 | if reset='1' then 68 | data <= (others=>zero_lit); 69 | curr_size <= 0; 70 | data_out <= zero_lit; 71 | empty_signal <= '1'; 72 | full_signal <= '0'; 73 | front <= zero_lit; 74 | 75 | elsif rising_edge(clock) then 76 | 77 | -- PUSH 78 | if wr_en='1' and full_signal='0' then 79 | data(curr_size) <= data_in; 80 | curr_size <= curr_size + 1; 81 | temp := temp + 1; 82 | 83 | --POP 84 | elsif pop = '1' and empty_signal='0' then 85 | data_out <= data(curr_size-1); 86 | data(curr_size-1) <= zero_lit; 87 | curr_size <= curr_size - 1; 88 | temp := temp - 1; 89 | end if; 90 | 91 | --FRONT 92 | if temp > 0 then 93 | front <= data(temp-1); 94 | end if; 95 | 96 | if temp=(lit_stack_size) then 97 | full_signal <= '1'; 98 | empty_signal <= '0'; 99 | elsif temp=0 then 100 | full_signal <= '0'; 101 | empty_signal <= '1'; 102 | else 103 | full_signal <= '0'; 104 | empty_signal <= '0'; 105 | end if; 106 | 107 | end if; 108 | end process ; 109 | end Behavioral; 110 | 111 | -------------------------------------------------------------------------------- /src/Stack_formula.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 01:13:23 04/02/2016 6 | -- Design Name: 7 | -- Module Name: Stack_formula - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use work.Common.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity Stack_formula is 35 | 36 | Port ( clock : in STD_LOGIC; 37 | reset : in STD_LOGIC; 38 | wr_en : in STD_LOGIC; 39 | pop : in STD_LOGIC; 40 | din : in formula; 41 | dout : out formula; 42 | front : out formula; 43 | full : out STD_LOGIC; 44 | empty : out STD_LOGIC); 45 | end Stack_formula; 46 | 47 | architecture Behavioral of Stack_formula is 48 | --DATA VARIABLES 49 | type mem_type is array (formula_stack_size-1 downto 0) of formula; 50 | signal data : mem_type := (others => zero_formula); 51 | signal curr_size : INTEGER := 0; 52 | 53 | --OTHER Vars 54 | signal data_in : formula; 55 | signal data_out : formula; 56 | signal full_signal : STD_LOGIC := '0'; 57 | signal empty_signal : STD_LOGIC := '1'; 58 | begin 59 | 60 | data_in <= din; 61 | dout <= data_out; 62 | full <= full_signal; 63 | empty <= empty_signal; 64 | 65 | process(clock,reset) 66 | variable temp : INTEGER := curr_size; 67 | begin 68 | --RESET 69 | if reset='1' then 70 | data <= (others=>zero_formula); 71 | curr_size <= 0; 72 | data_out <= zero_formula; 73 | empty_signal <= '1'; 74 | full_signal <= '0'; 75 | front <= zero_formula; 76 | 77 | elsif rising_edge(clock) then 78 | -- PUSH 79 | if wr_en='1' and full_signal='0' then 80 | data(curr_size) <= data_in; 81 | curr_size <= curr_size + 1; 82 | temp := temp + 1; 83 | 84 | --POP 85 | elsif pop = '1' and empty_signal='0' then 86 | data_out <= data(curr_size-1); 87 | curr_size <= curr_size - 1; 88 | temp := temp - 1; 89 | end if; 90 | 91 | --FRONT 92 | if temp > 0 then 93 | front <= data(temp-1); 94 | end if; 95 | 96 | if temp=(formula_stack_size) then 97 | full_signal <= '1'; 98 | empty_signal <= '0'; 99 | elsif temp=0 then 100 | full_signal <= '0'; 101 | empty_signal <= '1'; 102 | else 103 | full_signal <= '0'; 104 | empty_signal <= '0'; 105 | end if; 106 | 107 | end if; 108 | end process ; 109 | end Behavioral; 110 | 111 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench11.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{cnf_3: False, cnf_1: False, cnf_2: True} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "100"; 107 | wait for clock_period; 108 | i <= "001"; 109 | wait for clock_period; 110 | i <= "011"; 111 | wait for clock_period; 112 | i <= "100"; 113 | wait for clock_period; 114 | 115 | load <= '0'; 116 | 117 | -- insert stimulus here 118 | 119 | wait; 120 | end process; 121 | 122 | END; 123 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench3.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --False 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "100"; 107 | wait for clock_period; 108 | i <= "000"; 109 | wait for clock_period; 110 | i <= "000"; 111 | wait for clock_period; 112 | i <= "010"; 113 | wait for clock_period; 114 | i <= "010"; 115 | wait for clock_period; 116 | i <= "100"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench4.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --False 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "100"; 107 | wait for clock_period; 108 | i <= "000"; 109 | wait for clock_period; 110 | i <= "000"; 111 | wait for clock_period; 112 | i <= "100"; 113 | wait for clock_period; 114 | i <= "000"; 115 | wait for clock_period; 116 | i <= "000"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench10.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{a: True, b: True} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "100"; 107 | wait for clock_period; 108 | i <= "000"; 109 | wait for clock_period; 110 | i <= "100"; 111 | wait for clock_period; 112 | i <= "010"; 113 | wait for clock_period; 114 | i <= "010"; 115 | wait for clock_period; 116 | i <= "100"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench5.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{a: True, b: False} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "100"; 107 | wait for clock_period; 108 | i <= "000"; 109 | wait for clock_period; 110 | i <= "000"; 111 | wait for clock_period; 112 | i <= "010"; 113 | wait for clock_period; 114 | i <= "000"; 115 | wait for clock_period; 116 | i <= "000"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench6.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{a: False, b: False} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "100"; 107 | wait for clock_period; 108 | i <= "010"; 109 | wait for clock_period; 110 | i <= "010"; 111 | wait for clock_period; 112 | i <= "100"; 113 | wait for clock_period; 114 | i <= "000"; 115 | wait for clock_period; 116 | i <= "000"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench9.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{a: False, b: True} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "110"; 107 | wait for clock_period; 108 | i <= "000"; 109 | wait for clock_period; 110 | i <= "010"; 111 | wait for clock_period; 112 | i <= "100"; 113 | wait for clock_period; 114 | i <= "000"; 115 | wait for clock_period; 116 | i <= "000"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench7.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{c: True, b: False, a: True} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "110"; 107 | wait for clock_period; 108 | i <= "000"; 109 | wait for clock_period; 110 | i <= "001"; 111 | wait for clock_period; 112 | i <= "010"; 113 | wait for clock_period; 114 | i <= "000"; 115 | wait for clock_period; 116 | i <= "000"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench8.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{b: True, a: True, c: True} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(2 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(2 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(2 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(2 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "100"; 107 | wait for clock_period; 108 | i <= "000"; 109 | wait for clock_period; 110 | i <= "010"; 111 | wait for clock_period; 112 | i <= "000"; 113 | wait for clock_period; 114 | i <= "001"; 115 | wait for clock_period; 116 | i <= "000"; 117 | wait for clock_period; 118 | 119 | load <= '0'; 120 | 121 | -- insert stimulus here 122 | 123 | wait; 124 | end process; 125 | 126 | END; 127 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench15.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{cnf_1: True, cnf_5: False, cnf_3: False, cnf_2: False, cnf_4: False} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(4 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(4 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(4 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(4 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "11100"; 107 | wait for clock_period; 108 | i <= "00000"; 109 | wait for clock_period; 110 | i <= "00000"; 111 | wait for clock_period; 112 | i <= "10001"; 113 | wait for clock_period; 114 | i <= "10100"; 115 | wait for clock_period; 116 | i <= "01000"; 117 | wait for clock_period; 118 | i <= "00011"; 119 | wait for clock_period; 120 | i <= "00100"; 121 | wait for clock_period; 122 | i <= "10000"; 123 | wait for clock_period; 124 | i <= "00110"; 125 | wait for clock_period; 126 | 127 | load <= '0'; 128 | 129 | -- insert stimulus here 130 | 131 | wait; 132 | end process; 133 | 134 | END; 135 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench1.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --False 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(6 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(6 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(6 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(6 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "0000001"; 107 | wait for clock_period; 108 | i <= "0000010"; 109 | wait for clock_period; 110 | i <= "1100010"; 111 | wait for clock_period; 112 | i <= "0000000"; 113 | wait for clock_period; 114 | i <= "0000000"; 115 | wait for clock_period; 116 | i <= "0000011"; 117 | wait for clock_period; 118 | i <= "0010010"; 119 | wait for clock_period; 120 | i <= "1000000"; 121 | wait for clock_period; 122 | i <= "0001010"; 123 | wait for clock_period; 124 | i <= "0100000"; 125 | wait for clock_period; 126 | i <= "0000110"; 127 | wait for clock_period; 128 | i <= "0010000"; 129 | wait for clock_period; 130 | i <= "0000010"; 131 | wait for clock_period; 132 | i <= "0101000"; 133 | wait for clock_period; 134 | i <= "0000010"; 135 | wait for clock_period; 136 | i <= "0010100"; 137 | wait for clock_period; 138 | 139 | load <= '0'; 140 | 141 | -- insert stimulus here 142 | 143 | wait; 144 | end process; 145 | 146 | END; 147 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench2.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{c: False, b: False, e: False, d: False, a: False, g: True, f: True} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(6 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(6 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(6 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(6 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "0000010"; 107 | wait for clock_period; 108 | i <= "0000001"; 109 | wait for clock_period; 110 | i <= "0000001"; 111 | wait for clock_period; 112 | i <= "0000010"; 113 | wait for clock_period; 114 | i <= "1100010"; 115 | wait for clock_period; 116 | i <= "0000000"; 117 | wait for clock_period; 118 | i <= "0010010"; 119 | wait for clock_period; 120 | i <= "1000000"; 121 | wait for clock_period; 122 | i <= "0001010"; 123 | wait for clock_period; 124 | i <= "0100000"; 125 | wait for clock_period; 126 | i <= "0000110"; 127 | wait for clock_period; 128 | i <= "0010000"; 129 | wait for clock_period; 130 | i <= "0000010"; 131 | wait for clock_period; 132 | i <= "0101000"; 133 | wait for clock_period; 134 | i <= "0000010"; 135 | wait for clock_period; 136 | i <= "0010100"; 137 | wait for clock_period; 138 | 139 | load <= '0'; 140 | 141 | -- insert stimulus here 142 | 143 | wait; 144 | end process; 145 | 146 | END; 147 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench13.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{cnf_5: False, cnf_3: False, cnf_2: False, cnf_4: False, cnf_1: False, cnf_6: False} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(5 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(5 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(5 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(5 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "000000"; 107 | wait for clock_period; 108 | i <= "100000"; 109 | wait for clock_period; 110 | i <= "000000"; 111 | wait for clock_period; 112 | i <= "001000"; 113 | wait for clock_period; 114 | i <= "010000"; 115 | wait for clock_period; 116 | i <= "100000"; 117 | wait for clock_period; 118 | i <= "010000"; 119 | wait for clock_period; 120 | i <= "000100"; 121 | wait for clock_period; 122 | i <= "000010"; 123 | wait for clock_period; 124 | i <= "000100"; 125 | wait for clock_period; 126 | i <= "000000"; 127 | wait for clock_period; 128 | i <= "101000"; 129 | wait for clock_period; 130 | i <= "000000"; 131 | wait for clock_period; 132 | i <= "000101"; 133 | wait for clock_period; 134 | i <= "101000"; 135 | wait for clock_period; 136 | i <= "010000"; 137 | wait for clock_period; 138 | i <= "000101"; 139 | wait for clock_period; 140 | i <= "010010"; 141 | wait for clock_period; 142 | 143 | load <= '0'; 144 | 145 | -- insert stimulus here 146 | 147 | wait; 148 | end process; 149 | 150 | END; 151 | -------------------------------------------------------------------------------- /src/Pure_Literal.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:44:50 04/04/2016 6 | -- Design Name: 7 | -- Module Name: Pure_Literal - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.common.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity Pure_Literal is 34 | Port ( clock : in STD_LOGIC; 35 | reset : in STD_LOGIC; 36 | in_formula : in formula; 37 | find : in STD_LOGIC; 38 | ended : out STD_LOGIC; 39 | found : out STD_LOGIC; 40 | lit_found : out lit); 41 | end Pure_Literal; 42 | 43 | architecture Behavioral of Pure_Literal is 44 | 45 | signal s_in_formula : formula := ZERO_FORMULA; 46 | signal s_ended : STD_LOGIC := '0'; 47 | signal s_found : STD_LOGIC := '0'; 48 | signal s_lit_found : lit := ZERO_LIT; 49 | signal s_finding : STD_LOGIC := '0'; 50 | signal s_val_set : STD_LOGIC_VECTOR((number_literals-1) downto 0) := (others => '0'); 51 | signal s_val : STD_LOGIC_VECTOR((number_literals-1) downto 0) := (others => '0'); 52 | signal s_is_pure : STD_LOGIC_VECTOR((number_literals-1) downto 0) := (others => '0'); 53 | signal oiterator : INTEGER := 0; 54 | signal iiterator : INTEGER := 0; 55 | signal piterator : INTEGER := 0; 56 | 57 | 58 | begin 59 | ended <= s_ended; 60 | found <= s_found; 61 | lit_found <= s_lit_found; 62 | 63 | process(clock, reset) 64 | begin 65 | if reset ='1' then 66 | s_in_formula <= ZERO_FORMULA; 67 | s_ended <= '0'; 68 | s_found <= '0'; 69 | s_lit_found <= ZERO_LIT; 70 | s_finding <= '0'; 71 | s_val_set <= (others => '0'); 72 | s_val <= (others => '0'); 73 | s_is_pure <= (others => '1'); 74 | oiterator <= 0; 75 | iiterator <= 0; 76 | piterator <= 0; 77 | 78 | elsif rising_edge(clock) then 79 | s_ended <= '0'; 80 | if find='1' and s_finding='0' then 81 | s_in_formula <= in_formula; 82 | s_finding <= '1'; 83 | s_ended <= '0'; 84 | oiterator <= 0; 85 | iiterator <= 0; 86 | piterator <= 0; 87 | s_val_set <= (others => '0'); 88 | s_val <= (others => '0'); 89 | s_is_pure <= (others => '1'); 90 | 91 | elsif s_finding = '1' then 92 | if oiterator < s_in_formula.len then 93 | if iiterator < s_in_formula.clauses(oiterator).len then 94 | if s_is_pure(s_in_formula.clauses(oiterator).lits(iiterator).num-1) = '1' then 95 | if s_val_set(s_in_formula.clauses(oiterator).lits(iiterator).num-1) = '1' then 96 | if s_val(s_in_formula.clauses(oiterator).lits(iiterator).num-1) /= s_in_formula.clauses(oiterator).lits(iiterator).val then 97 | s_is_pure(s_in_formula.clauses(oiterator).lits(iiterator).num-1) <= '0'; 98 | end if; 99 | else 100 | s_val(s_in_formula.clauses(oiterator).lits(iiterator).num-1) <= s_in_formula.clauses(oiterator).lits(iiterator).val; 101 | s_val_set(s_in_formula.clauses(oiterator).lits(iiterator).num-1) <= '1'; 102 | end if; 103 | end if; 104 | iiterator <= iiterator + 1; 105 | else 106 | iiterator <= 0; 107 | oiterator <= oiterator + 1; 108 | end if; 109 | else 110 | if piterator < number_literals then 111 | if s_is_pure(piterator) = '0' or s_val_set(piterator) = '0' then 112 | piterator <= piterator + 1; 113 | else 114 | s_lit_found.num <= piterator+1; 115 | s_lit_found.val <= s_val(piterator); 116 | s_finding <= '0'; 117 | s_found <= '1'; 118 | s_ended <= '1'; 119 | end if; 120 | else 121 | s_finding <= '0'; 122 | s_found <= '0'; 123 | s_ended <= '1'; 124 | end if; 125 | end if; 126 | end if; 127 | end if; 128 | end process; 129 | end Behavioral; 130 | -------------------------------------------------------------------------------- /src/read_store.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 02:40:37 04/02/2016 6 | -- Design Name: 7 | -- Module Name: read_store - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.common.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity read_store is 34 | Port ( clock : in STD_LOGIC; 35 | reset : in STD_LOGIC; 36 | load : in STD_LOGIC; 37 | i : in STD_LOGIC_VECTOR((number_literals-1) downto 0); 38 | formula_res: out formula; 39 | ended: out STD_LOGIC); 40 | end read_store; 41 | 42 | architecture Behavioral of read_store is 43 | signal temp_formula : formula := ZERO_FORMULA; 44 | type mem_type is array ((2*number_clauses - 1) downto 0) of STD_LOGIC_VECTOR((number_literals-1) downto 0); 45 | signal bit_vec : mem_type := (others => (others => '0')); 46 | signal noofcycles : INTEGER := 0; 47 | signal noofclauses: INTEGER := 0; 48 | signal prev_load : STD_LOGIC := '0'; 49 | signal prev_load1 : STD_LOGIC := '0'; 50 | signal oiterator : INTEGER := 0; 51 | signal iiterator : INTEGER := 0; 52 | signal row_iterator : INTEGER := 0; 53 | signal computing : STD_LOGIC := '0'; 54 | signal finished : STD_LOGIC := '0'; 55 | 56 | begin 57 | 58 | process(clock, reset) 59 | begin 60 | --RESET-- 61 | if reset='1' then 62 | temp_formula <= ZERO_FORMULA; 63 | bit_vec <= (others => (others => '0')); 64 | noofcycles <= 0; 65 | prev_load <= '0'; 66 | prev_load1 <= '0'; 67 | noofclauses <= 0; 68 | oiterator <= 0; 69 | iiterator <= 0; 70 | row_iterator <= 0; 71 | computing <= '0'; 72 | finished <= '0'; 73 | ended <= '0'; 74 | elsif rising_edge(clock) then 75 | -- PARSE 76 | prev_load <= load; 77 | prev_load1 <= prev_load; 78 | ended <= '0'; 79 | if load='1' and computing = '0'then 80 | bit_vec(noofcycles) <= i; 81 | noofcycles <= noofcycles + 1; 82 | ended <= '0'; 83 | 84 | elsif load = '0' and prev_load = '1' then 85 | --prev_load <= '1'; 86 | ended <= '0'; 87 | 88 | elsif load = '0' and prev_load = '0' and prev_load1 = '1' and computing = '0' then 89 | computing <= '1'; 90 | noofclauses <= noofcycles/2; 91 | temp_formula.len <= noofcycles/2; 92 | ended <= '0'; 93 | 94 | elsif computing = '1' then 95 | if oiterator < noofclauses then 96 | if iiterator < number_literals then 97 | if bit_vec(2*oiterator)(iiterator) = '1' and bit_vec(2*oiterator + 1)(iiterator) = '0' then 98 | temp_formula.clauses(oiterator).lits(row_iterator).num <= iiterator + 1; 99 | temp_formula.clauses(oiterator).lits(row_iterator).val <= '1'; 100 | row_iterator <= row_iterator + 1; 101 | elsif bit_vec(2*oiterator)(iiterator) = '0' and bit_vec(2*oiterator + 1)(iiterator) = '1' then 102 | temp_formula.clauses(oiterator).lits(row_iterator).num <= iiterator + 1; 103 | temp_formula.clauses(oiterator).lits(row_iterator).val <= '0'; 104 | row_iterator <= row_iterator + 1; 105 | end if; 106 | iiterator <= iiterator + 1; 107 | else 108 | 109 | if row_iterator = 0 then 110 | temp_formula.len <= temp_formula.len - 1; 111 | end if ; 112 | 113 | iiterator <= 0; 114 | temp_formula.clauses(oiterator).len <= row_iterator; 115 | row_iterator <= 0; 116 | oiterator <= oiterator + 1; 117 | end if; 118 | else 119 | computing <= '0'; 120 | finished <= '1'; 121 | end if; 122 | ended <= '0'; 123 | elsif finished='1' then 124 | formula_res <= temp_formula; 125 | ended <= '1'; 126 | end if; 127 | end if; 128 | end process; 129 | end Behavioral; 130 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench12.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{cnf_2: False, cnf_16: True, cnf_5: True, cnf_10: False, cnf_15: False, cnf_12: True, cnf_8: True, cnf_11: False, cnf_13: True, cnf_4: False, cnf_6: True, cnf_1: True, cnf_7: True, cnf_3: True, cnf_14: False, cnf_9: True} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(15 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(15 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(15 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(15 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "1000000010000000"; 107 | wait for clock_period; 108 | i <= "0000000000000000"; 109 | wait for clock_period; 110 | i <= "0101000000000000"; 111 | wait for clock_period; 112 | i <= "0000000000000000"; 113 | wait for clock_period; 114 | i <= "0100000000000001"; 115 | wait for clock_period; 116 | i <= "0000000000000000"; 117 | wait for clock_period; 118 | i <= "0011000000000000"; 119 | wait for clock_period; 120 | i <= "0000000000000000"; 121 | wait for clock_period; 122 | i <= "0000110000000000"; 123 | wait for clock_period; 124 | i <= "0000000000000000"; 125 | wait for clock_period; 126 | i <= "0000001100000000"; 127 | wait for clock_period; 128 | i <= "0000000000000000"; 129 | wait for clock_period; 130 | i <= "0000000001100000"; 131 | wait for clock_period; 132 | i <= "0000000000000000"; 133 | wait for clock_period; 134 | i <= "0000000000001100"; 135 | wait for clock_period; 136 | i <= "0000000000000000"; 137 | wait for clock_period; 138 | i <= "0000010000000000"; 139 | wait for clock_period; 140 | i <= "0000001000000000"; 141 | wait for clock_period; 142 | i <= "0000000000010000"; 143 | wait for clock_period; 144 | i <= "0000000000001000"; 145 | wait for clock_period; 146 | i <= "0000000000001000"; 147 | wait for clock_period; 148 | i <= "0000000000000100"; 149 | wait for clock_period; 150 | i <= "0000000000000100"; 151 | wait for clock_period; 152 | i <= "0000000100000000"; 153 | wait for clock_period; 154 | i <= "0000000000000010"; 155 | wait for clock_period; 156 | i <= "0000000000000001"; 157 | wait for clock_period; 158 | i <= "0000000000000001"; 159 | wait for clock_period; 160 | i <= "0100000000000000"; 161 | wait for clock_period; 162 | i <= "0000000000000000"; 163 | wait for clock_period; 164 | i <= "0110000000000000"; 165 | wait for clock_period; 166 | i <= "0000000000000000"; 167 | wait for clock_period; 168 | i <= "0000010000000010"; 169 | wait for clock_period; 170 | i <= "0000000000000000"; 171 | wait for clock_period; 172 | i <= "0000000010100000"; 173 | wait for clock_period; 174 | i <= "0000000000000000"; 175 | wait for clock_period; 176 | i <= "0000000000110000"; 177 | wait for clock_period; 178 | 179 | load <= '0'; 180 | 181 | -- insert stimulus here 182 | 183 | wait; 184 | end process; 185 | 186 | END; 187 | -------------------------------------------------------------------------------- /src/Propagate_Literal.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 00:55:55 04/05/2016 6 | -- Design Name: 7 | -- Module Name: Propagate_Literal - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use work.Common.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity Propagate_Literal is 35 | Port ( clock : in STD_LOGIC; 36 | reset : in STD_LOGIC; 37 | find : in STD_LOGIC; 38 | in_formula : in formula; 39 | in_lit : in lit; 40 | ended : out STD_LOGIC; 41 | empty_clause : out STD_LOGIC; 42 | empty_formula : out STD_LOGIC; 43 | out_formula : out formula); 44 | end Propagate_Literal; 45 | 46 | architecture Behavioral of Propagate_Literal is 47 | 48 | signal s_in_formula : formula := ZERO_FORMULA; 49 | signal s_in_lit : lit := ZERO_LIT; 50 | signal s_ended : STD_LOGIC := '0'; 51 | signal s_empty_clause : STD_LOGIC := '0'; 52 | signal s_empty_formula : STD_LOGIC := '0'; 53 | signal s_out_formula : formula := ZERO_FORMULA; 54 | 55 | signal s_finding : STD_LOGIC := '0'; 56 | signal i : INTEGER := 0; 57 | signal j : INTEGER := 0; 58 | 59 | type state is (IDLE,BEGIN_OUTER,BEGIN_INNER,RUN_INNER,END_INNER,END_OUTER,DONE); -- State declaration 60 | signal present_state: state := IDLE; 61 | 62 | signal final_formula : formula := ZERO_FORMULA; 63 | signal temp_clause : clause := ZERO_CLAUSE; 64 | signal num_clauses : INTEGER := 0; 65 | signal num_lits : INTEGER := 0; 66 | 67 | begin 68 | 69 | ended <= s_ended; 70 | empty_clause <= s_empty_clause; 71 | empty_formula <= s_empty_formula; 72 | out_formula <= s_out_formula; 73 | 74 | process(clock,reset) 75 | begin 76 | if reset='1' then 77 | s_in_formula <= ZERO_FORMULA; 78 | s_in_lit <= ZERO_LIT; 79 | s_ended <= '0'; 80 | s_empty_clause <= '0'; 81 | s_empty_formula <= '0'; 82 | s_out_formula <= ZERO_FORMULA; 83 | s_finding <= '0'; 84 | i <= 0; 85 | j <= 0; 86 | present_state <= IDLE; 87 | final_formula <= ZERO_FORMULA; 88 | temp_clause <= ZERO_CLAUSE; 89 | num_clauses <= 0; 90 | num_lits <= 0; 91 | present_state <= IDLE; 92 | 93 | elsif rising_edge(clock) then 94 | 95 | s_ended <= '0'; 96 | if find='1' and s_finding = '0' then 97 | s_in_formula <= in_formula; 98 | s_in_lit <= in_lit; 99 | s_finding <= '1'; 100 | s_ended <= '0'; 101 | present_state <= BEGIN_OUTER; 102 | elsif s_finding = '1' then 103 | s_ended <= '0'; 104 | case( present_state ) is 105 | 106 | when BEGIN_OUTER => 107 | final_formula <= ZERO_FORMULA; 108 | num_clauses <= 0; 109 | i<=0; 110 | present_state <= BEGIN_INNER; 111 | 112 | when BEGIN_INNER => 113 | if i >= s_in_formula.len then 114 | present_state <= END_OUTER; 115 | else 116 | temp_clause <= ZERO_CLAUSE; 117 | num_lits <= 0; 118 | j <= 0; 119 | present_state <= RUN_INNER; 120 | end if; 121 | 122 | when RUN_INNER => 123 | if j >= s_in_formula.clauses(i).len then 124 | present_state <= END_INNER; 125 | else 126 | if s_in_formula.clauses(i).lits(j).num = s_in_lit.num then 127 | if s_in_formula.clauses(i).lits(j).val = s_in_lit.val then 128 | i <= i+1; 129 | present_state <= BEGIN_INNER; 130 | else 131 | j <= j+1; 132 | present_state <= RUN_INNER; 133 | end if ; 134 | elsif s_in_formula.clauses(i).lits(j).num = 0 then 135 | j <= j+1; 136 | present_state <= RUN_INNER; 137 | else 138 | temp_clause.lits(num_lits) <= s_in_formula.clauses(i).lits(j); 139 | temp_clause.len <= num_lits + 1; 140 | num_lits <= num_lits + 1; 141 | j <= j + 1; 142 | present_state <= RUN_INNER; 143 | end if; 144 | end if ; 145 | 146 | when END_INNER => 147 | if num_lits = 0 then 148 | s_ended <= '1'; 149 | s_finding <= '0'; 150 | s_empty_clause <= '1'; 151 | s_empty_formula <= '0'; 152 | s_out_formula <= final_formula; 153 | present_state <= DONE; 154 | else 155 | final_formula.clauses(num_clauses) <= temp_clause; 156 | final_formula.len <= num_clauses+1; 157 | num_clauses <= num_clauses+1; 158 | i <= i+1; 159 | present_state <= BEGIN_INNER; 160 | end if ; 161 | 162 | when END_OUTER => 163 | if num_clauses = 0 then 164 | s_ended <= '1'; 165 | s_finding <= '0'; 166 | s_empty_clause <= '0'; 167 | s_empty_formula <= '1'; 168 | s_out_formula <= final_formula; 169 | present_state <= DONE; 170 | else 171 | s_ended <= '1'; 172 | s_finding <= '0'; 173 | s_empty_clause <= '0'; 174 | s_empty_formula <= '0'; 175 | s_out_formula <= final_formula; 176 | present_state <= DONE; 177 | end if ; 178 | 179 | when DONE => 180 | present_state <= IDLE; 181 | 182 | when others => 183 | s_ended <= '1'; 184 | s_finding <= '0'; 185 | s_empty_clause <= '0'; 186 | s_empty_formula <= '0'; 187 | s_out_formula <= ZERO_FORMULA; 188 | present_state <= IDLE; 189 | 190 | end case ; 191 | end if; 192 | 193 | end if; 194 | end process; 195 | 196 | 197 | end Behavioral; 198 | 199 | -------------------------------------------------------------------------------- /tests/syntestbench/syntestbench.py: -------------------------------------------------------------------------------- 1 | from sympy import * 2 | from sympy.logic.boolalg import Or, Not, conjuncts, disjuncts, to_cnf, to_int_repr, _find_predicates, is_literal 3 | 4 | # error checking 5 | 6 | def repeat_to_length(item, length): 7 | if length == 0: 8 | return [] 9 | if length == 1: 10 | return [item] 11 | else: 12 | return [item] + repeat_to_length(item, length - 1) 13 | 14 | def syntestbench(s, numlit, numclause): 15 | numlit = int(numlit) 16 | numclause = int(numclause) 17 | print("--ANSWER TO THIS TEST BENCH") 18 | print("--", end="") 19 | print(satisfiable(s)) 20 | s = to_cnf(sympify(s)) 21 | symbols = sorted(_find_predicates(s), key=default_sort_key) 22 | symbols_int_repr = set(range(0, len(symbols))) 23 | to_print = [] 24 | if s.func != And: 25 | s1 = repeat_to_length(0, numlit) 26 | s2 = repeat_to_length(0, numlit) 27 | if s.func != Or: 28 | if s.is_Symbol: 29 | s1[symbols.index(s)] = 1 30 | to_print.append(s1) 31 | to_print.append(s2) 32 | else: 33 | s2[symbols.index(Not(s))] = 1 34 | to_print.append(s1) 35 | to_print.append(s2) 36 | else: 37 | for arg in s.args: 38 | if arg.is_Symbol: 39 | s1[symbols.index(arg)] = 1 40 | else: 41 | s2[symbols.index(Not(arg))] = 1 42 | to_print.append(s1) 43 | to_print.append(s2) 44 | 45 | else: 46 | clauses = s.args 47 | for clause in clauses: 48 | s1 = repeat_to_length(0, numlit) 49 | s2 = repeat_to_length(0, numlit) 50 | if clause.func != Or: 51 | if clause.is_Symbol: 52 | s1[symbols.index(clause)] = 1 53 | to_print.append(s1) 54 | to_print.append(s2) 55 | else: 56 | s2[symbols.index(Not(clause))] = 1 57 | to_print.append(s1) 58 | to_print.append(s2) 59 | else: 60 | for arg in clause.args: 61 | if arg.is_Symbol: 62 | s1[symbols.index(arg)] = 1 63 | else: 64 | s2[symbols.index(Not(arg))] = 1 65 | to_print.append(s1) 66 | to_print.append(s2) 67 | 68 | if(numclause > len(to_print)/2): 69 | s1 = repeat_to_length(0, numlit) 70 | s2 = repeat_to_length(0, numlit) 71 | for i in range(numclause - int(len(to_print)/2)): 72 | to_print.append(s1) 73 | to_print.append(s2) 74 | 75 | return to_print 76 | 77 | numlit = input("") 78 | numclause = input("") 79 | response = input("") 80 | 81 | getlist = syntestbench(response, numlit, numclause) 82 | 83 | print("""-------------------------------------------------------------------------------- 84 | -- Company: 85 | -- Engineer: 86 | -- 87 | -- Create Date: 16:09:58 04/06/2016 88 | -- Design Name: 89 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 90 | -- Project Name: controller 91 | -- Target Device: 92 | -- Tool versions: 93 | -- Description: 94 | -- 95 | -- VHDL Test Bench Created by ISE for module: controller 96 | -- 97 | -- Dependencies: 98 | -- 99 | -- Revision: 100 | -- Revision 0.01 - File Created 101 | -- Additional Comments: 102 | -- 103 | -- Notes: 104 | -- This testbench has been automatically generated using types std_logic and 105 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 106 | -- that these types always be used for the top-level I/O of a design in order 107 | -- to guarantee that the testbench will bind correctly to the post-implementation 108 | -- simulation model. 109 | -------------------------------------------------------------------------------- 110 | LIBRARY ieee; 111 | USE ieee.std_logic_1164.ALL; 112 | 113 | -- Uncomment the following library declaration if using 114 | -- arithmetic functions with Signed or Unsigned values 115 | --USE ieee.numeric_std.ALL; 116 | 117 | ENTITY testing101 IS 118 | END testing101; 119 | 120 | ARCHITECTURE behavior OF testing101 IS 121 | 122 | -- Component Declaration for the Unit Under Test (UUT) 123 | 124 | COMPONENT controller 125 | PORT( 126 | clock : IN std_logic; 127 | reset : IN std_logic; 128 | load : IN std_logic; 129 | i : IN std_logic_vector(""" + str(int(numlit) - 1) + """ downto 0); 130 | ended : OUT std_logic; 131 | sat : OUT std_logic; 132 | model : OUT std_logic_vector(""" + str(int(numlit) - 1) + """ downto 0) 133 | ); 134 | END COMPONENT; 135 | 136 | 137 | --Inputs 138 | signal clock : std_logic := '0'; 139 | signal reset : std_logic := '0'; 140 | signal load : std_logic := '0'; 141 | signal i : std_logic_vector(""" + str(int(numlit) - 1) + """ downto 0) := (others => '0'); 142 | 143 | --Outputs 144 | signal ended : std_logic; 145 | signal sat : std_logic; 146 | signal model : std_logic_vector(""" + str(int(numlit) - 1) + """ downto 0); 147 | 148 | -- Clock period definitions 149 | constant clock_period : time := 10 ns; 150 | 151 | BEGIN 152 | 153 | -- Instantiate the Unit Under Test (UUT) 154 | uut: controller PORT MAP ( 155 | clock => clock, 156 | reset => reset, 157 | load => load, 158 | i => i, 159 | ended => ended, 160 | sat => sat, 161 | model => model 162 | ); 163 | 164 | -- Clock process definitions 165 | clock_process :process 166 | begin 167 | clock <= '0'; 168 | wait for clock_period/2; 169 | clock <= '1'; 170 | wait for clock_period/2; 171 | end process; 172 | 173 | 174 | -- Stimulus process 175 | stim_proc: process 176 | begin 177 | -- hold reset state for 100 ns. 178 | 179 | wait for 100 ns; 180 | reset <= '1'; 181 | wait for 2*clock_period; 182 | reset <= '0'; 183 | 184 | load <= '1'; 185 | """) 186 | for listi in getlist: 187 | print("i <= \"", end="") 188 | for x in listi: 189 | print(x, end="") 190 | print("\";") 191 | print("wait for clock_period;") 192 | 193 | print(""" 194 | load <= '0'; 195 | 196 | -- insert stimulus here 197 | 198 | wait; 199 | end process; 200 | 201 | END;""") 202 | 203 | 204 | -------------------------------------------------------------------------------- /tests/testbench/README.md: -------------------------------------------------------------------------------- 1 | The following are the testbenches in the project folder: 2 | 3 | Add the testbenches given: There are 15 test benches are varying difficulties 4 | A lot more can be generated very easily using syntestbench.py in others folder. 5 | 6 | VERY IMP : Change the NUMBER_LITERALS and NUMBER_CLAUSES in the Common.vhd file as per the 7 | boolean expression. These NUMBER_LITERALS can be greater than the number of literals in 8 | the expression(same for number of clauses) but should not be lesser. The fastest simulation 9 | is obtained when it is exactly equal. 10 | Every testbench generated using syntestbench.py has the expected result on first two 11 | lines of the testbench(applies to all files submitted). In case the instructors intends 12 | to generate more using the script you can refer to this for the answer. 13 | 14 | tussle_testbench1.vhd 15 | --------------------- 16 | 17 | This has : 18 | NUMBER_LITERALS = 6 19 | NUMBER_CLAUSES = 7 20 | (a | b |f) & (~b | d | f) &( ~b | ~d | f) &(c | ~a | f) & (~c | e | f) & (~c |~e|f) & (~f | g) & (~f | ~g) 21 | This is unsatisfiable. 22 | 23 | tussle_testbench2.vhd 24 | --------------------- 25 | 26 | This has 27 | NUMBER_LITERALS = 6 28 | NUMBER_CLAUSES = 7 29 | (a | b |f) & (~b | d | f) &( ~b | ~d | f) &(c | ~a | f) & (~c | e | f) & (~c |~e|f) & (~f | g) & (f | ~g) 30 | This is satisfiable and the returned model satisfies it. 31 | 32 | (Following are a few basic and a few advance test cases) 33 | 34 | tussle_testbench3.vhd 35 | --------------------- 36 | NUMBER_LITERALS : 3 37 | NUMBER_CLAUSES : 3 38 | a & (~a | b) & ~b 39 | UNSAT 40 | 41 | tussle_testbench4.vhd 42 | --------------------- 43 | NUMBER_LITERALS : 3 44 | NUMBER_CLAUSES : 3 45 | a & ~a 46 | UNSAT 47 | 48 | tussle_testbench5.vhd 49 | --------------------- 50 | NUMBER_LITERALS : 3 51 | NUMBER_CLAUSES : 3 52 | a & ~b 53 | SAT 54 | 55 | tussle_testbench6.vhd 56 | --------------------- 57 | NUMBER_LITERALS : 3 58 | NUMBER_CLAUSES : 3 59 | (~a | b) &(~b |a) 60 | SAT 61 | 62 | tussle_testbench7.vhd 63 | --------------------- 64 | NUMBER_LITERALS : 3 65 | NUMBER_CLAUSES : 3 66 | (a | b) & (~b | c) 67 | SAT 68 | 69 | tussle_testbench8.vhd 70 | --------------------- 71 | NUMBER_LITERALS : 3 72 | NUMBER_CLAUSES : 3 73 | a & b & c 74 | SAT 75 | 76 | tussle_testbench9.vhd 77 | --------------------- 78 | NUMBER_LITERALS : 3 79 | NUMBER_CLAUSES : 3 80 | (a | b)&(~a | b) 81 | SAT 82 | 83 | tussle_testbench10.vhd 84 | --------------------- 85 | NUMBER_LITERALS : 3 86 | NUMBER_CLAUSES : 3 87 | a &( ~a |b)&(~b | a) 88 | SAT 89 | 90 | The following are a few advance cases. We selected a few. 91 | These were taken as inputs in dimacs format and fed to syntestbench.py 92 | Various tests on satisfiability using dimacs cnf file syntax 93 | You can find lots of cnf files in 94 | ftp://dimacs.rutgers.edu/pub/challenge/satisfiability/benchmarks/cnf/ 95 | 96 | tussle_testbench11.vhd 97 | --------------------- 98 | NUMBER_LITERALS : 3 99 | NUMBER_CLAUSES : 2 100 | And(Or(Not(cnf_1), cnf_2, cnf_3), Or(Not(cnf_3), cnf_1)) 101 | SAT 102 | 103 | tussle_testbench12.vhd 104 | --------------------- 105 | NUMBER_LITERALS : 16 106 | NUMBER_CLAUSES : 18 107 | And(Or(Not(cnf_10), Not(cnf_11)), Or(Not(cnf_10), cnf_9), Or(Not(cnf_14), Not(cnf_8)), Or(Not(cnf_15), cnf_14), Or(Not(cnf_16), cnf_7), Or(Not(cnf_2), Not(cnf_4)), Or(Not(cnf_4), Not(cnf_5)), Or(Not(cnf_6), cnf_5), Or(Not(cnf_7), cnf_6), Or(Not(cnf_9), cnf_8), Or(cnf_1, cnf_2), Or(cnf_10, cnf_12), Or(cnf_10, cnf_9), Or(cnf_11, cnf_12), Or(cnf_13, cnf_14), Or(cnf_15, cnf_16), Or(cnf_3, cnf_4), Or(cnf_6, cnf_7)) 108 | SAT 109 | 110 | tussle_testbench13.vhd 111 | --------------------- 112 | NUMBER_LITERALS : 6 113 | NUMBER_CLAUSES : 9 114 | And(Not(cnf_1), Not(cnf_3), Or(Not(cnf_1), Not(cnf_3)), Or(Not(cnf_1), cnf_2), Or(Not(cnf_2), Not(cnf_5), cnf_4, cnf_6), Or(Not(cnf_2), cnf_1, cnf_3), Or(Not(cnf_4), Not(cnf_6)), Or(Not(cnf_4), cnf_2), Or(Not(cnf_4), cnf_5)) 115 | SAT 116 | 117 | tussle_testbench14.vhd 118 | --------------------- 119 | NUMBER_LITERALS : 42 120 | NUMBER_CLAUSES : 133 121 | And(Or(Not(cnf_1), Not(cnf_13)), Or(Not(cnf_1), Not(cnf_19)), Or(Not(cnf_1), Not(cnf_25)), Or(Not(cnf_1), Not(cnf_31)), Or(Not(cnf_1), Not(cnf_37)), Or(Not(cnf_1), Not(cnf_7)), Or(Not(cnf_10), Not(cnf_16)), Or(Not(cnf_10), Not(cnf_22)), Or(Not(cnf_10), Not(cnf_28)), Or(Not(cnf_10), Not(cnf_34)), Or(Not(cnf_10), Not(cnf_4)), Or(Not(cnf_10), Not(cnf_40)), Or(Not(cnf_11), Not(cnf_17)), Or(Not(cnf_11), Not(cnf_23)), Or(Not(cnf_11), Not(cnf_29)), Or(Not(cnf_11), Not(cnf_35)), Or(Not(cnf_11), Not(cnf_41)), Or(Not(cnf_11), Not(cnf_5)), Or(Not(cnf_12), Not(cnf_18)), Or(Not(cnf_12), Not(cnf_24)), Or(Not(cnf_12), Not(cnf_30)), Or(Not(cnf_12), Not(cnf_36)), Or(Not(cnf_12), Not(cnf_42)), Or(Not(cnf_12), Not(cnf_6)), Or(Not(cnf_13), Not(cnf_19)), Or(Not(cnf_13), Not(cnf_25)), Or(Not(cnf_13), Not(cnf_31)), Or(Not(cnf_13), Not(cnf_37)), Or(Not(cnf_13), Not(cnf_7)), Or(Not(cnf_14), Not(cnf_2)), Or(Not(cnf_14), Not(cnf_20)), Or(Not(cnf_14), Not(cnf_26)), Or(Not(cnf_14), Not(cnf_32)), Or(Not(cnf_14), Not(cnf_38)), Or(Not(cnf_14), Not(cnf_8)), Or(Not(cnf_15), Not(cnf_21)), Or(Not(cnf_15), Not(cnf_27)), Or(Not(cnf_15), Not(cnf_3)), Or(Not(cnf_15), Not(cnf_33)), Or(Not(cnf_15), Not(cnf_39)), Or(Not(cnf_15), Not(cnf_9)), Or(Not(cnf_16), Not(cnf_22)), Or(Not(cnf_16), Not(cnf_28)), Or(Not(cnf_16), Not(cnf_34)), Or(Not(cnf_16), Not(cnf_4)), Or(Not(cnf_16), Not(cnf_40)), Or(Not(cnf_17), Not(cnf_23)), Or(Not(cnf_17), Not(cnf_29)), Or(Not(cnf_17), Not(cnf_35)), Or(Not(cnf_17), Not(cnf_41)), Or(Not(cnf_17), Not(cnf_5)), Or(Not(cnf_18), Not(cnf_24)), Or(Not(cnf_18), Not(cnf_30)), Or(Not(cnf_18), Not(cnf_36)), Or(Not(cnf_18), Not(cnf_42)), Or(Not(cnf_18), Not(cnf_6)), Or(Not(cnf_19), Not(cnf_25)), Or(Not(cnf_19), Not(cnf_31)), Or(Not(cnf_19), Not(cnf_37)), Or(Not(cnf_19), Not(cnf_7)), Or(Not(cnf_2), Not(cnf_20)), Or(Not(cnf_2), Not(cnf_26)), Or(Not(cnf_2), Not(cnf_32)), Or(Not(cnf_2), Not(cnf_38)), Or(Not(cnf_2), Not(cnf_8)), Or(Not(cnf_20), Not(cnf_26)), Or(Not(cnf_20), Not(cnf_32)), Or(Not(cnf_20), Not(cnf_38)), Or(Not(cnf_20), Not(cnf_8)), Or(Not(cnf_21), Not(cnf_27)), Or(Not(cnf_21), Not(cnf_3)), Or(Not(cnf_21), Not(cnf_33)), Or(Not(cnf_21), Not(cnf_39)), Or(Not(cnf_21), Not(cnf_9)), Or(Not(cnf_22), Not(cnf_28)), Or(Not(cnf_22), Not(cnf_34)), Or(Not(cnf_22), Not(cnf_4)), Or(Not(cnf_22), Not(cnf_40)), Or(Not(cnf_23), Not(cnf_29)), Or(Not(cnf_23), Not(cnf_35)), Or(Not(cnf_23), Not(cnf_41)), Or(Not(cnf_23), Not(cnf_5)), Or(Not(cnf_24), Not(cnf_30)), Or(Not(cnf_24), Not(cnf_36)), Or(Not(cnf_24), Not(cnf_42)), Or(Not(cnf_24), Not(cnf_6)), Or(Not(cnf_25), Not(cnf_31)), Or(Not(cnf_25), Not(cnf_37)), Or(Not(cnf_25), Not(cnf_7)), Or(Not(cnf_26), Not(cnf_32)), Or(Not(cnf_26), Not(cnf_38)), Or(Not(cnf_26), Not(cnf_8)), Or(Not(cnf_27), Not(cnf_3)), Or(Not(cnf_27), Not(cnf_33)), Or(Not(cnf_27), Not(cnf_39)), Or(Not(cnf_27), Not(cnf_9)), Or(Not(cnf_28), Not(cnf_34)), Or(Not(cnf_28), Not(cnf_4)), Or(Not(cnf_28), Not(cnf_40)), Or(Not(cnf_29), Not(cnf_35)), Or(Not(cnf_29), Not(cnf_41)), Or(Not(cnf_29), Not(cnf_5)), Or(Not(cnf_3), Not(cnf_33)), Or(Not(cnf_3), Not(cnf_39)), Or(Not(cnf_3), Not(cnf_9)), Or(Not(cnf_30), Not(cnf_36)), Or(Not(cnf_30), Not(cnf_42)), Or(Not(cnf_30), Not(cnf_6)), Or(Not(cnf_31), Not(cnf_37)), Or(Not(cnf_31), Not(cnf_7)), Or(Not(cnf_32), Not(cnf_38)), Or(Not(cnf_32), Not(cnf_8)), Or(Not(cnf_33), Not(cnf_39)), Or(Not(cnf_33), Not(cnf_9)), Or(Not(cnf_34), Not(cnf_4)), Or(Not(cnf_34), Not(cnf_40)), Or(Not(cnf_35), Not(cnf_41)), Or(Not(cnf_35), Not(cnf_5)), Or(Not(cnf_36), Not(cnf_42)), Or(Not(cnf_36), Not(cnf_6)), Or(Not(cnf_37), Not(cnf_7)), Or(Not(cnf_38), Not(cnf_8)), Or(Not(cnf_39), Not(cnf_9)), Or(Not(cnf_4), Not(cnf_40)), Or(Not(cnf_41), Not(cnf_5)), Or(Not(cnf_42), Not(cnf_6)), Or(cnf_1, cnf_2, cnf_3, cnf_4, cnf_5, cnf_6), Or(cnf_10, cnf_11, cnf_12, cnf_7, cnf_8, cnf_9), Or(cnf_13, cnf_14, cnf_15, cnf_16, cnf_17, cnf_18), Or(cnf_19, cnf_20, cnf_21, cnf_22, cnf_23, cnf_24), Or(cnf_25, cnf_26, cnf_27, cnf_28, cnf_29, cnf_30), Or(cnf_31, cnf_32, cnf_33, cnf_34, cnf_35, cnf_36), Or(cnf_37, cnf_38, cnf_39, cnf_40, cnf_41, cnf_42)) 122 | UNSAT 123 | PS: This takes considerable time but does eventually report unsat. 124 | 125 | tussle_testbench15.vhd 126 | --------------------- 127 | NUMBER_LITERALS : 5 128 | NUMBER_CLAUSES : 5 129 | And(Or(Not(cnf_1), Not(cnf_5)), Or(Not(cnf_2), cnf_1, cnf_3), Or(Not(cnf_3), Not(cnf_4), cnf_1), Or(Not(cnf_3), cnf_4, cnf_5), Or(cnf_1, cnf_2, cnf_3)) 130 | SAT 131 | 132 | -------------------------------------------------------------------------------- /src/DB_kernel.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 06:41:02 04/05/2016 6 | -- Design Name: 7 | -- Module Name: DB_Kernel - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use work.common.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity DB_Kernel is 35 | Port ( clock : in STD_LOGIC; 36 | reset : in STD_LOGIC; 37 | find : in STD_LOGIC; 38 | in_formula : in formula; 39 | ended : out STD_LOGIC; 40 | out_formula : out formula; 41 | sat : out STD_LOGIC; 42 | unsat : out STD_LOGIC; 43 | propagating : out STD_LOGIC; 44 | out_lit: out lit); 45 | end DB_Kernel; 46 | 47 | architecture Behavioral of DB_Kernel is 48 | 49 | component Unit_Clause is 50 | Port ( clock : in STD_LOGIC; 51 | reset : in STD_LOGIC; 52 | find : in STD_LOGIC; 53 | in_formula : in formula; 54 | ended : out STD_LOGIC; 55 | found : out STD_LOGIC; 56 | lit_found : out lit); 57 | end component; 58 | 59 | 60 | component Propagate_Literal is 61 | Port ( clock : in STD_LOGIC; 62 | reset : in STD_LOGIC; 63 | find : in STD_LOGIC; 64 | in_formula : in formula; 65 | in_lit : in lit; 66 | ended : out STD_LOGIC; 67 | empty_clause : out STD_LOGIC; 68 | empty_formula : out STD_LOGIC; 69 | out_formula : out formula); 70 | end component; 71 | 72 | component Pure_Literal is 73 | Port ( clock : in STD_LOGIC; 74 | reset : in STD_LOGIC; 75 | find : in STD_LOGIC; 76 | in_formula : in formula; 77 | ended : out STD_LOGIC; 78 | found : out STD_LOGIC; 79 | lit_found : out lit); 80 | end component; 81 | 82 | signal s_in_formula : formula := ZERO_FORMULA; 83 | signal s_out_formula : formula := ZERO_FORMULA; 84 | signal s_out_lit : lit := ZERO_LIT; 85 | --signal s_ended : STD_LOGIC := '1'; 86 | signal s_sat : STD_LOGIC := '0'; 87 | signal s_unsat : STD_LOGIC := '0'; 88 | 89 | signal s_finding : STD_LOGIC := '0'; 90 | signal s_temp_found : STD_LOGIC := '0'; 91 | signal C : lit := ZERO_LIT; 92 | 93 | type state is (UC_b,UC_r,UC_e,PL_b,PL_r,PL_e,PROP_b,PROP_r,PROP_e,IDLE); 94 | signal present_state : state := IDLE; 95 | signal called_from_state : state := IDLE; 96 | 97 | signal UC_lit_found : lit := ZERO_LIT; 98 | signal UC_find : STD_LOGIC := '0'; 99 | signal UC_ended : STD_LOGIC := '0'; 100 | signal UC_found : STD_LOGIC := '0'; 101 | 102 | signal PL_lit_found : lit := ZERO_LIT; 103 | signal PL_find : STD_LOGIC := '0'; 104 | signal PL_ended : STD_LOGIC := '0'; 105 | signal PL_found : STD_LOGIC := '0'; 106 | 107 | signal PropL_find : STD_LOGIC := '0'; 108 | signal PropL_in_lit : lit := ZERO_LIT; 109 | signal PropL_ended : STD_LOGIC := '0'; 110 | signal PropL_empty_clause : STD_LOGIC := '0'; 111 | signal PropL_empty_formula : STD_LOGIC := '0'; 112 | signal PropL_out_formula : formula := ZERO_FORMULA; 113 | 114 | begin 115 | 116 | --out_formula <= s_in_formula; 117 | --out_lit <= C; 118 | 119 | UC : Unit_Clause 120 | port map( 121 | clock => clock, 122 | reset => reset, 123 | find => UC_find, 124 | in_formula => s_in_formula, 125 | ended => UC_ended, 126 | found => UC_found, 127 | lit_found => UC_lit_found 128 | ); 129 | 130 | PL : Pure_Literal 131 | port map( 132 | clock => clock, 133 | reset => reset, 134 | find => PL_find, 135 | in_formula => s_in_formula, 136 | ended => PL_ended, 137 | found => PL_found, 138 | lit_found => PL_lit_found 139 | ); 140 | 141 | PropL : Propagate_Literal 142 | port map( 143 | clock => clock, 144 | reset => reset, 145 | find => PropL_find, 146 | in_formula => s_in_formula, 147 | in_lit => PropL_in_lit, 148 | ended => PropL_ended, 149 | empty_clause => PropL_empty_clause, 150 | empty_formula => PropL_empty_formula, 151 | out_formula => PropL_out_formula 152 | ); 153 | 154 | process(clock,reset) 155 | begin 156 | if reset='1' then 157 | ended <= '0'; 158 | sat <= '0'; 159 | unsat <= '0'; 160 | out_formula <= ZERO_FORMULA; 161 | propagating <= '0'; 162 | out_lit <= ZERO_LIT; 163 | 164 | s_in_formula <= ZERO_FORMULA; 165 | s_finding <= '0'; 166 | present_state <= IDLE; 167 | called_from_state <= IDLE; 168 | 169 | UC_find <= '0'; 170 | PL_find <= '0'; 171 | PropL_find <= '0'; 172 | PropL_in_lit <= ZERO_LIT; 173 | 174 | elsif rising_edge(clock) then 175 | ended <= '0'; 176 | UC_find <= '0'; 177 | PL_find <= '0'; 178 | PropL_find <= '0'; 179 | if find='1' and s_finding = '0' then 180 | s_in_formula <= in_formula; 181 | s_finding <= '1'; 182 | ended <= '0'; 183 | present_state <= UC_b; 184 | sat <= '0'; 185 | unsat <= '0'; 186 | out_formula <= ZERO_FORMULA; 187 | propagating <= '0'; 188 | out_lit <= ZERO_LIT; 189 | elsif s_finding = '1' then 190 | ended <= '0'; 191 | propagating <= '0'; 192 | case( present_state ) is 193 | 194 | when UC_b => 195 | if s_in_formula = ZERO_FORMULA then 196 | ended <= '1'; 197 | sat <= '1'; 198 | unsat <= '0'; 199 | propagating <= '0'; 200 | out_formula <= s_in_formula; 201 | present_state <= IDLE; 202 | s_finding <= '0'; 203 | else 204 | UC_find <= '1'; 205 | present_state <= UC_r; 206 | end if ; 207 | 208 | when UC_r => 209 | if UC_ended = '1' then 210 | C <= UC_lit_found; 211 | s_temp_found <= UC_found; 212 | present_state <= UC_e; 213 | end if ; 214 | 215 | when UC_e => 216 | if(s_temp_found = '1') then 217 | called_from_state <= UC_b; 218 | present_state <= PROP_b; 219 | else 220 | present_state <= PL_b; 221 | end if; 222 | 223 | when PROP_b => 224 | PropL_find <= '1'; 225 | propagating <= '1'; 226 | out_lit <= C; 227 | PropL_in_lit <= C; 228 | present_state <= PROP_r; 229 | 230 | when PROP_r => 231 | if PropL_ended = '1' then 232 | s_sat <= PropL_empty_formula; 233 | s_unsat <= PropL_empty_clause; 234 | s_in_formula <= PropL_out_formula; 235 | present_state <= PROP_e; 236 | end if ; 237 | 238 | when PROP_e => 239 | if s_sat = '1' then 240 | -- RETURN SAT 241 | ended <= '1'; 242 | sat <= '1'; 243 | unsat <= '0'; 244 | propagating <= '0'; 245 | out_formula <= s_in_formula; 246 | present_state <= IDLE; 247 | s_finding <= '0'; 248 | --out_lit <= ZERO_LIT; 249 | elsif s_unsat = '1' then 250 | -- RETURN UNSAT 251 | ended <= '1'; 252 | sat <= '0'; 253 | unsat <= '1'; 254 | propagating <= '0'; 255 | out_formula <= s_in_formula; 256 | present_state <= IDLE; 257 | s_finding <= '0'; 258 | --out_lit <= ZERO_LIT; 259 | else 260 | present_state <= called_from_state; 261 | end if; 262 | 263 | when PL_b => 264 | PL_find <= '1'; 265 | present_state <= PL_r; 266 | 267 | when PL_r => 268 | if PL_ended = '1' then 269 | C <= PL_lit_found; 270 | s_temp_found <= PL_found; 271 | present_state <= PL_e; 272 | end if ; 273 | 274 | when PL_e => 275 | if(s_temp_found = '1') then 276 | called_from_state <= PL_b; 277 | present_state <= PROP_b; 278 | else 279 | --RETURN 280 | ended <= '1'; 281 | sat <= '0'; 282 | unsat <= '0'; 283 | propagating <= '0'; 284 | out_formula <= s_in_formula; 285 | --out_lit <= ZERO_LIT; 286 | 287 | present_state <= IDLE; 288 | s_finding <= '0'; 289 | end if; 290 | 291 | when IDLE => 292 | present_state <= IDLE; 293 | s_finding <= '0'; 294 | end case ; 295 | end if; 296 | end if; 297 | end process; 298 | 299 | end Behavioral; 300 | 301 | -------------------------------------------------------------------------------- /src/tusSAT_top.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 05:26:00 04/05/2016 6 | -- Design Name: 7 | -- Module Name: controller - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.common.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity controller is 34 | Port ( clock : in STD_LOGIC; 35 | reset : in STD_LOGIC; 36 | load : in STD_LOGIC; 37 | i : in STD_LOGIC_VECTOR((number_literals-1) downto 0); 38 | ended : out STD_LOGIC; 39 | sat : out STD_LOGIC; 40 | model : out STD_LOGIC_VECTOR((number_literals-1) downto 0)); 41 | end controller; 42 | 43 | architecture Behavioral of controller is 44 | 45 | --Defining components in Architecture 46 | 47 | component DB_Kernel is 48 | Port ( clock : in STD_LOGIC; 49 | reset : in STD_LOGIC; 50 | find : in STD_LOGIC; 51 | in_formula : in formula; 52 | ended : out STD_LOGIC; 53 | out_formula : out formula; 54 | sat : out STD_LOGIC; 55 | unsat : out STD_LOGIC; 56 | propagating : out STD_LOGIC; 57 | out_lit: out lit); 58 | end component; 59 | 60 | component decide_branch is 61 | Port ( clock : in STD_LOGIC; 62 | reset : in STD_LOGIC; 63 | find : in STD_LOGIC; 64 | formula_in : in formula; 65 | ended : out STD_LOGIC; 66 | lit_out : out lit); 67 | end component; 68 | 69 | component Propagate_Literal is 70 | Port ( clock : in STD_LOGIC; 71 | reset : in STD_LOGIC; 72 | find : in STD_LOGIC; 73 | in_formula : in formula; 74 | in_lit : in lit; 75 | ended : out STD_LOGIC; 76 | empty_clause : out STD_LOGIC; 77 | empty_formula : out STD_LOGIC; 78 | out_formula : out formula); 79 | end component; 80 | 81 | component Stack_integer is 82 | Port ( clock : in STD_LOGIC; 83 | reset : in STD_LOGIC; 84 | wr_en : in STD_LOGIC; 85 | pop : in STD_LOGIC; 86 | din : in lit; 87 | dout : out lit; 88 | front : out lit; 89 | full : out STD_LOGIC; 90 | empty : out STD_LOGIC); 91 | end component; 92 | 93 | component Stack_formula is 94 | Port ( clock : in STD_LOGIC; 95 | reset : in STD_LOGIC; 96 | wr_en : in STD_LOGIC; 97 | pop : in STD_LOGIC; 98 | din : in formula; 99 | dout : out formula; 100 | front : out formula; 101 | full : out STD_LOGIC; 102 | empty : out STD_LOGIC); 103 | end component; 104 | 105 | component Stack_bool is 106 | Port ( clock : in STD_LOGIC; 107 | reset : in STD_LOGIC; 108 | wr_en : in STD_LOGIC; 109 | pop : in STD_LOGIC; 110 | din : in STD_LOGIC; 111 | dout : out STD_LOGIC; 112 | front : out STD_LOGIC; 113 | full : out STD_LOGIC; 114 | empty : out STD_LOGIC); 115 | end component; 116 | 117 | component read_store is 118 | Port ( clock : in STD_LOGIC; 119 | reset : in STD_LOGIC; 120 | load : in STD_LOGIC; 121 | i : in STD_LOGIC_VECTOR((number_literals-1) downto 0); 122 | formula_res: out formula; 123 | ended: out STD_LOGIC); 124 | end component; 125 | 126 | --State definitions to be used 127 | type state is (IDLE, BEFORE_INP, INPING, BACTRACK_POPDB_STACK, BACKTRACK_POPLIT_STACK, NEGATE_BEFORE_PROP, BEFORE_POPULATE_STACK, 128 | POPULATE_STACK, BEFORE_PROP, PROPAGATING, AFTER_PROP, BEFORE_KERNELIZE, KERNELIZING, AFTER_KERNELIZE, 129 | BEFORE_DB, DBING, AFTER_DB, UNSAT, RETURN_MODEL, FILL_VECT, SAT_RETURN, PROPAGATE); 130 | signal present_state : state := BEFORE_INP; 131 | 132 | --Defined signals for port-mapping 133 | signal Kernel_find : STD_LOGIC; 134 | signal Kernel_in_formula : formula; 135 | signal Kernel_ended : STD_LOGIC; 136 | signal Kernel_out_formula : formula; 137 | signal Kernel_sat : STD_LOGIC; 138 | signal Kernel_unsat : STD_LOGIC; 139 | signal Kernel_propagating : STD_LOGIC; 140 | signal Kernel_out_lit: lit; 141 | 142 | signal DB_find : STD_LOGIC; 143 | signal DB_formula_in : formula; 144 | signal DB_ended : STD_LOGIC; 145 | signal DB_lit_out : lit; 146 | 147 | signal Prop_find : STD_LOGIC; 148 | signal Prop_in_formula : formula; 149 | signal Prop_in_lit : lit; 150 | signal Prop_ended : STD_LOGIC; 151 | signal Prop_empty_clause : STD_LOGIC; 152 | signal Prop_empty_formula : STD_LOGIC; 153 | signal Prop_out_formula : formula; 154 | 155 | signal Lit_St_wr_en : STD_LOGIC; 156 | signal Lit_St_pop : STD_LOGIC; 157 | signal Lit_St_din : lit; 158 | signal Lit_St_dout : lit; 159 | signal Lit_St_front : lit; 160 | signal Lit_St_full : STD_LOGIC; 161 | signal Lit_St_empty : STD_LOGIC; 162 | 163 | signal DV_St_wr_en : STD_LOGIC; 164 | signal DV_St_pop : STD_LOGIC; 165 | signal DV_St_din : lit; 166 | signal DV_St_dout : lit; 167 | signal DV_St_front : lit; 168 | signal DV_St_full : STD_LOGIC; 169 | signal DV_St_empty : STD_LOGIC; 170 | 171 | signal Formula_St_wr_en : STD_LOGIC; 172 | signal Formula_St_pop : STD_LOGIC; 173 | signal Formula_St_din : formula; 174 | signal Formula_St_dout : formula; 175 | signal Formula_St_front : formula; 176 | signal Formula_St_full : STD_LOGIC; 177 | signal Formula_St_empty : STD_LOGIC; 178 | 179 | signal Backtrack_St_wr_en : STD_LOGIC; 180 | signal Backtrack_St_pop : STD_LOGIC; 181 | signal Backtrack_St_din : STD_LOGIC; 182 | signal Backtrack_St_dout : STD_LOGIC; 183 | signal Backtrack_St_front : STD_LOGIC; 184 | signal Backtrack_St_full : STD_LOGIC; 185 | signal Backtrack_St_empty : STD_LOGIC; 186 | 187 | signal IP_load : STD_LOGIC; 188 | signal IP_i : STD_LOGIC_VECTOR((number_literals-1) downto 0); 189 | signal IP_formula_res: formula; 190 | signal IP_ended: STD_LOGIC; 191 | 192 | --Other signals to be used in code 193 | signal F : formula; 194 | signal C : lit; 195 | signal to_populate : lit; 196 | signal output_vect : STD_LOGIC_VECTOR((number_literals-1) downto 0); 197 | signal temp_sat : STD_LOGIC; 198 | signal temp_unsat : STD_LOGIC; 199 | signal next_Backtrack : STD_LOGIC; 200 | signal wait_delay : INTEGER; 201 | 202 | begin 203 | 204 | --Port mapping 205 | Kernel : DB_Kernel 206 | port map( 207 | clock => clock, 208 | reset => reset, 209 | find => Kernel_find, 210 | in_formula => Kernel_in_formula, 211 | ended => Kernel_ended, 212 | out_formula => Kernel_out_formula, 213 | sat => Kernel_sat, 214 | unsat => Kernel_unsat, 215 | propagating => Kernel_propagating, 216 | out_lit => Kernel_out_lit 217 | ); 218 | 219 | DB : decide_branch 220 | port map( 221 | clock => clock, 222 | reset => reset, 223 | find => DB_find, 224 | formula_in => DB_formula_in, 225 | ended => DB_ended, 226 | lit_out => DB_lit_out 227 | ); 228 | 229 | Prop : Propagate_Literal 230 | port map( 231 | clock => clock, 232 | reset => reset, 233 | find => Prop_find, 234 | in_formula => Prop_in_formula, 235 | in_lit => Prop_in_lit, 236 | ended => Prop_ended, 237 | empty_clause => Prop_empty_clause, 238 | empty_formula => Prop_empty_formula, 239 | out_formula => Prop_out_formula 240 | ); 241 | 242 | Lit_St : Stack_integer 243 | port map( 244 | clock => clock, 245 | reset => reset, 246 | wr_en => Lit_St_wr_en, 247 | pop => Lit_St_pop, 248 | din => Lit_St_din, 249 | dout => Lit_St_dout, 250 | front => Lit_St_front, 251 | full => Lit_St_full, 252 | empty => Lit_St_empty 253 | ); 254 | 255 | DV_St : Stack_integer 256 | port map( 257 | clock => clock, 258 | reset => reset, 259 | wr_en => DV_St_wr_en, 260 | pop => DV_St_pop, 261 | din => DV_St_din, 262 | dout => DV_St_dout, 263 | front => DV_St_front, 264 | full => DV_St_full, 265 | empty => DV_St_empty 266 | ); 267 | 268 | Formula_St : Stack_formula 269 | port map( 270 | clock => clock, 271 | reset => reset, 272 | wr_en => Formula_St_wr_en, 273 | pop => Formula_St_pop, 274 | din => Formula_St_din, 275 | dout => Formula_St_dout, 276 | front => Formula_St_front, 277 | full => Formula_St_full, 278 | empty => Formula_St_empty 279 | ); 280 | 281 | Backtrack_St : Stack_bool 282 | port map( 283 | clock => clock, 284 | reset => reset, 285 | wr_en => Backtrack_St_wr_en, 286 | pop => Backtrack_St_pop, 287 | din => Backtrack_St_din, 288 | dout => Backtrack_St_dout, 289 | front => Backtrack_St_front, 290 | full => Backtrack_St_full, 291 | empty => Backtrack_St_empty 292 | ); 293 | 294 | IP : read_store 295 | port map( 296 | clock => clock, 297 | reset => reset, 298 | load => load, 299 | i => i, 300 | formula_res => IP_formula_res, 301 | ended => IP_ended 302 | ); 303 | 304 | process(clock,reset) 305 | begin 306 | if reset='1' then 307 | --Reset all variables 308 | ended <= '0'; 309 | sat <= '0'; 310 | model <= (others => '0'); 311 | F <= zero_formula; 312 | C<= zero_lit; 313 | to_populate<= zero_lit; 314 | output_vect<= (others => '0'); 315 | temp_sat<= '0'; 316 | temp_unsat<= '0'; 317 | next_Backtrack<= '0'; 318 | Kernel_find <= '0'; 319 | Kernel_in_formula <= zero_formula; 320 | DB_find <= '0'; 321 | DB_formula_in <= zero_formula; 322 | Prop_find <= '0'; 323 | Prop_in_formula <= zero_formula; 324 | Prop_in_lit <= zero_lit; 325 | Lit_St_wr_en <= '0'; 326 | Lit_St_pop <= '0'; 327 | Lit_St_din <= zero_lit; 328 | DV_St_wr_en <= '0'; 329 | DV_St_pop <= '0'; 330 | DV_St_din <= zero_lit; 331 | Formula_St_wr_en <= '0'; 332 | Formula_St_pop <= '0'; 333 | Formula_St_din <= zero_formula; 334 | Backtrack_St_wr_en <= '0'; 335 | Backtrack_St_pop <= '0'; 336 | Backtrack_St_din <= '0'; 337 | present_state <= BEFORE_INP; 338 | wait_delay <= 0; 339 | 340 | elsif rising_edge(clock) then 341 | --Reset all input variables to entities to make sure that they do not stay high unneccesarily 342 | Kernel_find <= '0'; 343 | DB_find <= '0'; 344 | Prop_find <= '0'; 345 | Lit_St_wr_en <= '0'; 346 | Lit_St_pop <= '0'; 347 | DV_St_wr_en <= '0'; 348 | DV_St_pop <= '0'; 349 | Formula_St_wr_en <= '0'; 350 | Formula_St_pop <= '0'; 351 | Backtrack_St_wr_en <= '0'; 352 | Backtrack_St_pop <= '0'; 353 | 354 | if wait_delay = 0 then 355 | 356 | case(present_state) is 357 | when BEFORE_INP => -- Initial State 358 | if load = '1' then 359 | present_state <= INPING; 360 | end if; 361 | 362 | when INPING => 363 | -- Wait for Input parser to finish parsing 364 | -- After it finishes, Store output 365 | -- Start processing Formula (Start with Kernelization) 366 | if IP_ended = '1' then 367 | F <= IP_formula_res; 368 | present_state <= BEFORE_KERNELIZE; 369 | end if; 370 | 371 | when BEFORE_KERNELIZE=> 372 | --Initialte Kernelization 373 | --Feed formula as input to Kernel entity 374 | Kernel_in_formula <= F; 375 | Kernel_find <= '1'; 376 | present_state <= KERNELIZING; 377 | 378 | when KERNELIZING => 379 | --Wait for Kernelization to end 380 | --While waiting, store literals outputted from Karnelization entity in Lit_Stack 381 | --(These literals are propagated during Kernelization) 382 | if (Kernel_ended = '1') then 383 | F <= Kernel_out_formula; 384 | temp_sat <= Kernel_sat; 385 | temp_unsat <= Kernel_unsat; 386 | present_state <= AFTER_KERNELIZE; 387 | elsif Kernel_propagating = '1' then 388 | Lit_St_din <= Kernel_out_lit; 389 | Lit_St_wr_en <= '1'; 390 | end if; 391 | 392 | when AFTER_KERNELIZE => 393 | --Depending if formula after kernelization returns SAT or UNSAT, 394 | --RETURN SAT or BACKTRACK 395 | --If None, Move to decide DecisionVariable 396 | if temp_sat = '1' then 397 | present_state <= RETURN_MODEL; 398 | elsif temp_unsat = '1' then 399 | present_state <= BACTRACK_POPDB_STACK; 400 | else 401 | present_state <= BEFORE_DB; 402 | end if ; 403 | 404 | when BACTRACK_POPDB_STACK => 405 | --Backtrack_Stack 406 | --RETURN UNSAT if stack is empty 407 | 408 | --Else pop until you find a '1' in backtrack stack 409 | --And flip this literal and propagate it again. 410 | if(Backtrack_St_empty = '1') then 411 | present_state <= UNSAT; 412 | elsif(Backtrack_St_front = '1') then 413 | Backtrack_St_pop <= '1'; 414 | DV_St_pop <= '1'; 415 | Formula_St_pop <= '1'; 416 | wait_delay <= 1; 417 | else 418 | present_state <= BACKTRACK_POPLIT_STACK; 419 | end if; 420 | 421 | when BACKTRACK_POPLIT_STACK => 422 | --Popping excess lits from Literal Stack 423 | if(Lit_St_front.num /= DV_St_front.num) then 424 | Lit_St_pop <= '1'; 425 | wait_delay <= 1; 426 | else 427 | Lit_St_pop <= '1'; 428 | DV_St_pop <= '1'; 429 | Backtrack_St_pop <= '1'; 430 | Formula_St_pop <= '1'; 431 | F <= Formula_St_front; 432 | C <= DV_St_front; 433 | present_state <= NEGATE_BEFORE_PROP; 434 | wait_delay <= 1; 435 | end if; 436 | 437 | when NEGATE_BEFORE_PROP => 438 | --FLipping 439 | C.val <= not C.val; 440 | next_Backtrack <= '1'; 441 | present_state <= PROPAGATE; 442 | 443 | when PROPAGATE => 444 | --Propagate flipped literal 445 | to_populate <= C; 446 | present_state <= BEFORE_POPULATE_STACK; 447 | 448 | when BEFORE_POPULATE_STACK => 449 | --Populate Stacks before propagating 450 | Formula_St_din <= F; 451 | Backtrack_St_din <= next_Backtrack; 452 | DV_St_din <= to_populate; 453 | Lit_St_din <= to_populate; 454 | present_state <= POPULATE_STACK; 455 | 456 | when POPULATE_STACK => 457 | --Populate Stacks before propagating 458 | DV_St_wr_en <= '1'; 459 | Lit_St_wr_en <= '1'; 460 | Backtrack_St_wr_en <= '1'; 461 | Formula_St_wr_en <= '1'; 462 | C <= to_populate; 463 | present_state <= BEFORE_PROP; 464 | 465 | when BEFORE_PROP => 466 | --Feed formula, literal for propagation 467 | Prop_find <= '1'; 468 | Prop_in_formula <= F; 469 | Prop_in_lit <= C; 470 | present_state <= PROPAGATING; 471 | 472 | when PROPAGATING => 473 | --Wait for prop to end 474 | if(Prop_ended = '1') then 475 | F <= Prop_out_formula; 476 | temp_sat <= Prop_empty_formula; 477 | temp_unsat <= Prop_empty_clause; 478 | present_state <= AFTER_PROP; 479 | end if; 480 | 481 | when AFTER_PROP => 482 | --Depending if formula after propagation returns SAT or UNSAT, 483 | --RETURN SAT or BACKTRACK 484 | --Else make next Decision 485 | if(temp_sat = '1') then 486 | present_state <= RETURN_MODEL; 487 | elsif(temp_unsat = '1') then 488 | present_state <= BACTRACK_POPDB_STACK; 489 | else 490 | present_state <= BEFORE_KERNELIZE; 491 | end if; 492 | 493 | when BEFORE_DB => 494 | --Feed formula to decide_branch 495 | DB_formula_in <= F; 496 | DB_find <= '1'; 497 | present_state <= DBING; 498 | 499 | when DBING => 500 | --Waiting for decision to be made 501 | if DB_ended = '1' then 502 | C <= DB_lit_out; 503 | next_Backtrack <= '0'; 504 | present_state <= AFTER_DB; 505 | end if ; 506 | 507 | when AFTER_DB => 508 | --Populate stacks with decision made 509 | to_populate <= C; 510 | present_state <= BEFORE_POPULATE_STACK; 511 | 512 | when UNSAT => 513 | --Return unsat 514 | ended <= '1'; 515 | sat <= '0'; 516 | 517 | when RETURN_MODEL => 518 | --Make model from litstack 519 | output_vect <= (others => '0'); 520 | present_state <= FILL_VECT; 521 | 522 | when FILL_VECT => 523 | if Lit_St_empty = '0' then 524 | output_vect(Lit_St_front.num-1) <= Lit_St_front.val; 525 | Lit_St_pop <= '1'; 526 | wait_delay <= 1; 527 | else 528 | present_state <= SAT_RETURN; 529 | end if ; 530 | 531 | when SAT_RETURN => 532 | --Return Sat 533 | ended <= '1'; 534 | sat <= '1'; 535 | model <= output_vect; 536 | 537 | when OTHERS => 538 | present_state <= IDLE; 539 | 540 | end case ; 541 | else 542 | wait_delay <= wait_delay - 1; 543 | end if; 544 | end if; 545 | end process; 546 | 547 | end Behavioral; 548 | 549 | -------------------------------------------------------------------------------- /src/testing101.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --{cnf_2: True, cnf_3: False, cnf_1: False} 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(63 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(63 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(63 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(63 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "1000000000000000000000000000000000000000000000000000000000000000"; 107 | wait for clock_period; 108 | i <= "0010000000000000000000000000000000000000000000000000000000000000"; 109 | wait for clock_period; 110 | i <= "0110000000000000000000000000000000000000000000000000000000000000"; 111 | wait for clock_period; 112 | i <= "1000000000000000000000000000000000000000000000000000000000000000"; 113 | wait for clock_period; 114 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 115 | wait for clock_period; 116 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 117 | wait for clock_period; 118 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 119 | wait for clock_period; 120 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 121 | wait for clock_period; 122 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 123 | wait for clock_period; 124 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 125 | wait for clock_period; 126 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 127 | wait for clock_period; 128 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 129 | wait for clock_period; 130 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 131 | wait for clock_period; 132 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 133 | wait for clock_period; 134 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 135 | wait for clock_period; 136 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 137 | wait for clock_period; 138 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 139 | wait for clock_period; 140 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 141 | wait for clock_period; 142 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 143 | wait for clock_period; 144 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 145 | wait for clock_period; 146 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 147 | wait for clock_period; 148 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 149 | wait for clock_period; 150 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 151 | wait for clock_period; 152 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 153 | wait for clock_period; 154 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 155 | wait for clock_period; 156 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 157 | wait for clock_period; 158 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 159 | wait for clock_period; 160 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 161 | wait for clock_period; 162 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 163 | wait for clock_period; 164 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 165 | wait for clock_period; 166 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 167 | wait for clock_period; 168 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 169 | wait for clock_period; 170 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 171 | wait for clock_period; 172 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 173 | wait for clock_period; 174 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 175 | wait for clock_period; 176 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 177 | wait for clock_period; 178 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 179 | wait for clock_period; 180 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 181 | wait for clock_period; 182 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 183 | wait for clock_period; 184 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 185 | wait for clock_period; 186 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 187 | wait for clock_period; 188 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 189 | wait for clock_period; 190 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 191 | wait for clock_period; 192 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 193 | wait for clock_period; 194 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 195 | wait for clock_period; 196 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 197 | wait for clock_period; 198 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 199 | wait for clock_period; 200 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 201 | wait for clock_period; 202 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 203 | wait for clock_period; 204 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 205 | wait for clock_period; 206 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 207 | wait for clock_period; 208 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 209 | wait for clock_period; 210 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 211 | wait for clock_period; 212 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 213 | wait for clock_period; 214 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 215 | wait for clock_period; 216 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 217 | wait for clock_period; 218 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 219 | wait for clock_period; 220 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 221 | wait for clock_period; 222 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 223 | wait for clock_period; 224 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 225 | wait for clock_period; 226 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 227 | wait for clock_period; 228 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 229 | wait for clock_period; 230 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 231 | wait for clock_period; 232 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 233 | wait for clock_period; 234 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 235 | wait for clock_period; 236 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 237 | wait for clock_period; 238 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 239 | wait for clock_period; 240 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 241 | wait for clock_period; 242 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 243 | wait for clock_period; 244 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 245 | wait for clock_period; 246 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 247 | wait for clock_period; 248 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 249 | wait for clock_period; 250 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 251 | wait for clock_period; 252 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 253 | wait for clock_period; 254 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 255 | wait for clock_period; 256 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 257 | wait for clock_period; 258 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 259 | wait for clock_period; 260 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 261 | wait for clock_period; 262 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 263 | wait for clock_period; 264 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 265 | wait for clock_period; 266 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 267 | wait for clock_period; 268 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 269 | wait for clock_period; 270 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 271 | wait for clock_period; 272 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 273 | wait for clock_period; 274 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 275 | wait for clock_period; 276 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 277 | wait for clock_period; 278 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 279 | wait for clock_period; 280 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 281 | wait for clock_period; 282 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 283 | wait for clock_period; 284 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 285 | wait for clock_period; 286 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 287 | wait for clock_period; 288 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 289 | wait for clock_period; 290 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 291 | wait for clock_period; 292 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 293 | wait for clock_period; 294 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 295 | wait for clock_period; 296 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 297 | wait for clock_period; 298 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 299 | wait for clock_period; 300 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 301 | wait for clock_period; 302 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 303 | wait for clock_period; 304 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 305 | wait for clock_period; 306 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 307 | wait for clock_period; 308 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 309 | wait for clock_period; 310 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 311 | wait for clock_period; 312 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 313 | wait for clock_period; 314 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 315 | wait for clock_period; 316 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 317 | wait for clock_period; 318 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 319 | wait for clock_period; 320 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 321 | wait for clock_period; 322 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 323 | wait for clock_period; 324 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 325 | wait for clock_period; 326 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 327 | wait for clock_period; 328 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 329 | wait for clock_period; 330 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 331 | wait for clock_period; 332 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 333 | wait for clock_period; 334 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 335 | wait for clock_period; 336 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 337 | wait for clock_period; 338 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 339 | wait for clock_period; 340 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 341 | wait for clock_period; 342 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 343 | wait for clock_period; 344 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 345 | wait for clock_period; 346 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 347 | wait for clock_period; 348 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 349 | wait for clock_period; 350 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 351 | wait for clock_period; 352 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 353 | wait for clock_period; 354 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 355 | wait for clock_period; 356 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 357 | wait for clock_period; 358 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 359 | wait for clock_period; 360 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 361 | wait for clock_period; 362 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 363 | wait for clock_period; 364 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 365 | wait for clock_period; 366 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 367 | wait for clock_period; 368 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 369 | wait for clock_period; 370 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 371 | wait for clock_period; 372 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 373 | wait for clock_period; 374 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 375 | wait for clock_period; 376 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 377 | wait for clock_period; 378 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 379 | wait for clock_period; 380 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 381 | wait for clock_period; 382 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 383 | wait for clock_period; 384 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 385 | wait for clock_period; 386 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 387 | wait for clock_period; 388 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 389 | wait for clock_period; 390 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 391 | wait for clock_period; 392 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 393 | wait for clock_period; 394 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 395 | wait for clock_period; 396 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 397 | wait for clock_period; 398 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 399 | wait for clock_period; 400 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 401 | wait for clock_period; 402 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 403 | wait for clock_period; 404 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 405 | wait for clock_period; 406 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 407 | wait for clock_period; 408 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 409 | wait for clock_period; 410 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 411 | wait for clock_period; 412 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 413 | wait for clock_period; 414 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 415 | wait for clock_period; 416 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 417 | wait for clock_period; 418 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 419 | wait for clock_period; 420 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 421 | wait for clock_period; 422 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 423 | wait for clock_period; 424 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 425 | wait for clock_period; 426 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 427 | wait for clock_period; 428 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 429 | wait for clock_period; 430 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 431 | wait for clock_period; 432 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 433 | wait for clock_period; 434 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 435 | wait for clock_period; 436 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 437 | wait for clock_period; 438 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 439 | wait for clock_period; 440 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 441 | wait for clock_period; 442 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 443 | wait for clock_period; 444 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 445 | wait for clock_period; 446 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 447 | wait for clock_period; 448 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 449 | wait for clock_period; 450 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 451 | wait for clock_period; 452 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 453 | wait for clock_period; 454 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 455 | wait for clock_period; 456 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 457 | wait for clock_period; 458 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 459 | wait for clock_period; 460 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 461 | wait for clock_period; 462 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 463 | wait for clock_period; 464 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 465 | wait for clock_period; 466 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 467 | wait for clock_period; 468 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 469 | wait for clock_period; 470 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 471 | wait for clock_period; 472 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 473 | wait for clock_period; 474 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 475 | wait for clock_period; 476 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 477 | wait for clock_period; 478 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 479 | wait for clock_period; 480 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 481 | wait for clock_period; 482 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 483 | wait for clock_period; 484 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 485 | wait for clock_period; 486 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 487 | wait for clock_period; 488 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 489 | wait for clock_period; 490 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 491 | wait for clock_period; 492 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 493 | wait for clock_period; 494 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 495 | wait for clock_period; 496 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 497 | wait for clock_period; 498 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 499 | wait for clock_period; 500 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 501 | wait for clock_period; 502 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 503 | wait for clock_period; 504 | i <= "0000000000000000000000000000000000000000000000000000000000000000"; 505 | wait for clock_period; 506 | 507 | load <= '0'; 508 | 509 | -- insert stimulus here 510 | 511 | wait; 512 | end process; 513 | 514 | END; 515 | -------------------------------------------------------------------------------- /tests/testbench/tussle_testbench14.vhd: -------------------------------------------------------------------------------- 1 | --ANSWER TO THIS TEST BENCH 2 | --False 3 | -------------------------------------------------------------------------------- 4 | -- Company: 5 | -- Engineer: 6 | -- 7 | -- Create Date: 16:09:58 04/06/2016 8 | -- Design Name: 9 | -- Module Name: /home/sumith1896/sandbox/controller/testing101.vhd 10 | -- Project Name: controller 11 | -- Target Device: 12 | -- Tool versions: 13 | -- Description: 14 | -- 15 | -- VHDL Test Bench Created by ISE for module: controller 16 | -- 17 | -- Dependencies: 18 | -- 19 | -- Revision: 20 | -- Revision 0.01 - File Created 21 | -- Additional Comments: 22 | -- 23 | -- Notes: 24 | -- This testbench has been automatically generated using types std_logic and 25 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 26 | -- that these types always be used for the top-level I/O of a design in order 27 | -- to guarantee that the testbench will bind correctly to the post-implementation 28 | -- simulation model. 29 | -------------------------------------------------------------------------------- 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.ALL; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY testing101 IS 38 | END testing101; 39 | 40 | ARCHITECTURE behavior OF testing101 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT controller 45 | PORT( 46 | clock : IN std_logic; 47 | reset : IN std_logic; 48 | load : IN std_logic; 49 | i : IN std_logic_vector(41 downto 0); 50 | ended : OUT std_logic; 51 | sat : OUT std_logic; 52 | model : OUT std_logic_vector(41 downto 0) 53 | ); 54 | END COMPONENT; 55 | 56 | 57 | --Inputs 58 | signal clock : std_logic := '0'; 59 | signal reset : std_logic := '0'; 60 | signal load : std_logic := '0'; 61 | signal i : std_logic_vector(41 downto 0) := (others => '0'); 62 | 63 | --Outputs 64 | signal ended : std_logic; 65 | signal sat : std_logic; 66 | signal model : std_logic_vector(41 downto 0); 67 | 68 | -- Clock period definitions 69 | constant clock_period : time := 10 ns; 70 | 71 | BEGIN 72 | 73 | -- Instantiate the Unit Under Test (UUT) 74 | uut: controller PORT MAP ( 75 | clock => clock, 76 | reset => reset, 77 | load => load, 78 | i => i, 79 | ended => ended, 80 | sat => sat, 81 | model => model 82 | ); 83 | 84 | -- Clock process definitions 85 | clock_process :process 86 | begin 87 | clock <= '0'; 88 | wait for clock_period/2; 89 | clock <= '1'; 90 | wait for clock_period/2; 91 | end process; 92 | 93 | 94 | -- Stimulus process 95 | stim_proc: process 96 | begin 97 | -- hold reset state for 100 ns. 98 | 99 | wait for 100 ns; 100 | reset <= '1'; 101 | wait for 2*clock_period; 102 | reset <= '0'; 103 | 104 | load <= '1'; 105 | 106 | i <= "000000000000000000000000000000000000000000"; 107 | wait for clock_period; 108 | i <= "100010000000000000000000000000000000000000"; 109 | wait for clock_period; 110 | i <= "000000000000000000000000000000000000000000"; 111 | wait for clock_period; 112 | i <= "100000000010000000000000000000000000000000"; 113 | wait for clock_period; 114 | i <= "000000000000000000000000000000000000000000"; 115 | wait for clock_period; 116 | i <= "100000000000000001000000000000000000000000"; 117 | wait for clock_period; 118 | i <= "000000000000000000000000000000000000000000"; 119 | wait for clock_period; 120 | i <= "100000000000000000000000100000000000000000"; 121 | wait for clock_period; 122 | i <= "000000000000000000000000000000000000000000"; 123 | wait for clock_period; 124 | i <= "100000000000000000000000000000100000000000"; 125 | wait for clock_period; 126 | i <= "000000000000000000000000000000000000000000"; 127 | wait for clock_period; 128 | i <= "100000000000000000000000000000000000000100"; 129 | wait for clock_period; 130 | i <= "000000000000000000000000000000000000000000"; 131 | wait for clock_period; 132 | i <= "010000010000000000000000000000000000000000"; 133 | wait for clock_period; 134 | i <= "000000000000000000000000000000000000000000"; 135 | wait for clock_period; 136 | i <= "010000000000001000000000000000000000000000"; 137 | wait for clock_period; 138 | i <= "000000000000000000000000000000000000000000"; 139 | wait for clock_period; 140 | i <= "010000000000000000001000000000000000000000"; 141 | wait for clock_period; 142 | i <= "000000000000000000000000000000000000000000"; 143 | wait for clock_period; 144 | i <= "010000000000000000000000000100000000000000"; 145 | wait for clock_period; 146 | i <= "000000000000000000000000000000000000000000"; 147 | wait for clock_period; 148 | i <= "010000000000000000000000000000000100000000"; 149 | wait for clock_period; 150 | i <= "000000000000000000000000000000000000000000"; 151 | wait for clock_period; 152 | i <= "010000000000000000000000000000000010000000"; 153 | wait for clock_period; 154 | i <= "000000000000000000000000000000000000000000"; 155 | wait for clock_period; 156 | i <= "001000001000000000000000000000000000000000"; 157 | wait for clock_period; 158 | i <= "000000000000000000000000000000000000000000"; 159 | wait for clock_period; 160 | i <= "001000000000000100000000000000000000000000"; 161 | wait for clock_period; 162 | i <= "000000000000000000000000000000000000000000"; 163 | wait for clock_period; 164 | i <= "001000000000000000000100000000000000000000"; 165 | wait for clock_period; 166 | i <= "000000000000000000000000000000000000000000"; 167 | wait for clock_period; 168 | i <= "001000000000000000000000000010000000000000"; 169 | wait for clock_period; 170 | i <= "000000000000000000000000000000000000000000"; 171 | wait for clock_period; 172 | i <= "001000000000000000000000000000000001000000"; 173 | wait for clock_period; 174 | i <= "000000000000000000000000000000000000000000"; 175 | wait for clock_period; 176 | i <= "001000000000000000000000000000000000010000"; 177 | wait for clock_period; 178 | i <= "000000000000000000000000000000000000000000"; 179 | wait for clock_period; 180 | i <= "000100000100000000000000000000000000000000"; 181 | wait for clock_period; 182 | i <= "000000000000000000000000000000000000000000"; 183 | wait for clock_period; 184 | i <= "000100000000000010000000000000000000000000"; 185 | wait for clock_period; 186 | i <= "000000000000000000000000000000000000000000"; 187 | wait for clock_period; 188 | i <= "000100000000000000000001000000000000000000"; 189 | wait for clock_period; 190 | i <= "000000000000000000000000000000000000000000"; 191 | wait for clock_period; 192 | i <= "000100000000000000000000000001000000000000"; 193 | wait for clock_period; 194 | i <= "000000000000000000000000000000000000000000"; 195 | wait for clock_period; 196 | i <= "000100000000000000000000000000000000100000"; 197 | wait for clock_period; 198 | i <= "000000000000000000000000000000000000000000"; 199 | wait for clock_period; 200 | i <= "000100000000000000000000000000000000001000"; 201 | wait for clock_period; 202 | i <= "000000000000000000000000000000000000000000"; 203 | wait for clock_period; 204 | i <= "000010000010000000000000000000000000000000"; 205 | wait for clock_period; 206 | i <= "000000000000000000000000000000000000000000"; 207 | wait for clock_period; 208 | i <= "000010000000000001000000000000000000000000"; 209 | wait for clock_period; 210 | i <= "000000000000000000000000000000000000000000"; 211 | wait for clock_period; 212 | i <= "000010000000000000000000100000000000000000"; 213 | wait for clock_period; 214 | i <= "000000000000000000000000000000000000000000"; 215 | wait for clock_period; 216 | i <= "000010000000000000000000000000100000000000"; 217 | wait for clock_period; 218 | i <= "000000000000000000000000000000000000000000"; 219 | wait for clock_period; 220 | i <= "000010000000000000000000000000000000000100"; 221 | wait for clock_period; 222 | i <= "000000000000000000000000000000000000000000"; 223 | wait for clock_period; 224 | i <= "000001000001000000000000000000000000000000"; 225 | wait for clock_period; 226 | i <= "000000000000000000000000000000000000000000"; 227 | wait for clock_period; 228 | i <= "000001000000100000000000000000000000000000"; 229 | wait for clock_period; 230 | i <= "000000000000000000000000000000000000000000"; 231 | wait for clock_period; 232 | i <= "000001000000000000100000000000000000000000"; 233 | wait for clock_period; 234 | i <= "000000000000000000000000000000000000000000"; 235 | wait for clock_period; 236 | i <= "000001000000000000000000010000000000000000"; 237 | wait for clock_period; 238 | i <= "000000000000000000000000000000000000000000"; 239 | wait for clock_period; 240 | i <= "000001000000000000000000000000010000000000"; 241 | wait for clock_period; 242 | i <= "000000000000000000000000000000000000000000"; 243 | wait for clock_period; 244 | i <= "000001000000000000000000000000000000000010"; 245 | wait for clock_period; 246 | i <= "000000000000000000000000000000000000000000"; 247 | wait for clock_period; 248 | i <= "000000100000010000000000000000000000000000"; 249 | wait for clock_period; 250 | i <= "000000000000000000000000000000000000000000"; 251 | wait for clock_period; 252 | i <= "000000100000000000010000000000000000000000"; 253 | wait for clock_period; 254 | i <= "000000000000000000000000000000000000000000"; 255 | wait for clock_period; 256 | i <= "000000100000000000000010000000000000000000"; 257 | wait for clock_period; 258 | i <= "000000000000000000000000000000000000000000"; 259 | wait for clock_period; 260 | i <= "000000100000000000000000001000000000000000"; 261 | wait for clock_period; 262 | i <= "000000000000000000000000000000000000000000"; 263 | wait for clock_period; 264 | i <= "000000100000000000000000000000001000000000"; 265 | wait for clock_period; 266 | i <= "000000000000000000000000000000000000000000"; 267 | wait for clock_period; 268 | i <= "000000100000000000000000000000000000000001"; 269 | wait for clock_period; 270 | i <= "000000000000000000000000000000000000000000"; 271 | wait for clock_period; 272 | i <= "000000010000001000000000000000000000000000"; 273 | wait for clock_period; 274 | i <= "000000000000000000000000000000000000000000"; 275 | wait for clock_period; 276 | i <= "000000010000000000001000000000000000000000"; 277 | wait for clock_period; 278 | i <= "000000000000000000000000000000000000000000"; 279 | wait for clock_period; 280 | i <= "000000010000000000000000000100000000000000"; 281 | wait for clock_period; 282 | i <= "000000000000000000000000000000000000000000"; 283 | wait for clock_period; 284 | i <= "000000010000000000000000000000000100000000"; 285 | wait for clock_period; 286 | i <= "000000000000000000000000000000000000000000"; 287 | wait for clock_period; 288 | i <= "000000010000000000000000000000000010000000"; 289 | wait for clock_period; 290 | i <= "000000000000000000000000000000000000000000"; 291 | wait for clock_period; 292 | i <= "000000001000000100000000000000000000000000"; 293 | wait for clock_period; 294 | i <= "000000000000000000000000000000000000000000"; 295 | wait for clock_period; 296 | i <= "000000001000000000000100000000000000000000"; 297 | wait for clock_period; 298 | i <= "000000000000000000000000000000000000000000"; 299 | wait for clock_period; 300 | i <= "000000001000000000000000000010000000000000"; 301 | wait for clock_period; 302 | i <= "000000000000000000000000000000000000000000"; 303 | wait for clock_period; 304 | i <= "000000001000000000000000000000000001000000"; 305 | wait for clock_period; 306 | i <= "000000000000000000000000000000000000000000"; 307 | wait for clock_period; 308 | i <= "000000001000000000000000000000000000010000"; 309 | wait for clock_period; 310 | i <= "000000000000000000000000000000000000000000"; 311 | wait for clock_period; 312 | i <= "000000000100000010000000000000000000000000"; 313 | wait for clock_period; 314 | i <= "000000000000000000000000000000000000000000"; 315 | wait for clock_period; 316 | i <= "000000000100000000000001000000000000000000"; 317 | wait for clock_period; 318 | i <= "000000000000000000000000000000000000000000"; 319 | wait for clock_period; 320 | i <= "000000000100000000000000000001000000000000"; 321 | wait for clock_period; 322 | i <= "000000000000000000000000000000000000000000"; 323 | wait for clock_period; 324 | i <= "000000000100000000000000000000000000100000"; 325 | wait for clock_period; 326 | i <= "000000000000000000000000000000000000000000"; 327 | wait for clock_period; 328 | i <= "000000000100000000000000000000000000001000"; 329 | wait for clock_period; 330 | i <= "000000000000000000000000000000000000000000"; 331 | wait for clock_period; 332 | i <= "000000000010000001000000000000000000000000"; 333 | wait for clock_period; 334 | i <= "000000000000000000000000000000000000000000"; 335 | wait for clock_period; 336 | i <= "000000000010000000000000100000000000000000"; 337 | wait for clock_period; 338 | i <= "000000000000000000000000000000000000000000"; 339 | wait for clock_period; 340 | i <= "000000000010000000000000000000100000000000"; 341 | wait for clock_period; 342 | i <= "000000000000000000000000000000000000000000"; 343 | wait for clock_period; 344 | i <= "000000000010000000000000000000000000000100"; 345 | wait for clock_period; 346 | i <= "000000000000000000000000000000000000000000"; 347 | wait for clock_period; 348 | i <= "000000000001100000000000000000000000000000"; 349 | wait for clock_period; 350 | i <= "000000000000000000000000000000000000000000"; 351 | wait for clock_period; 352 | i <= "000000000001000000100000000000000000000000"; 353 | wait for clock_period; 354 | i <= "000000000000000000000000000000000000000000"; 355 | wait for clock_period; 356 | i <= "000000000001000000000000010000000000000000"; 357 | wait for clock_period; 358 | i <= "000000000000000000000000000000000000000000"; 359 | wait for clock_period; 360 | i <= "000000000001000000000000000000010000000000"; 361 | wait for clock_period; 362 | i <= "000000000000000000000000000000000000000000"; 363 | wait for clock_period; 364 | i <= "000000000001000000000000000000000000000010"; 365 | wait for clock_period; 366 | i <= "000000000000000000000000000000000000000000"; 367 | wait for clock_period; 368 | i <= "000000000000100000100000000000000000000000"; 369 | wait for clock_period; 370 | i <= "000000000000000000000000000000000000000000"; 371 | wait for clock_period; 372 | i <= "000000000000100000000000010000000000000000"; 373 | wait for clock_period; 374 | i <= "000000000000000000000000000000000000000000"; 375 | wait for clock_period; 376 | i <= "000000000000100000000000000000010000000000"; 377 | wait for clock_period; 378 | i <= "000000000000000000000000000000000000000000"; 379 | wait for clock_period; 380 | i <= "000000000000100000000000000000000000000010"; 381 | wait for clock_period; 382 | i <= "000000000000000000000000000000000000000000"; 383 | wait for clock_period; 384 | i <= "000000000000010000010000000000000000000000"; 385 | wait for clock_period; 386 | i <= "000000000000000000000000000000000000000000"; 387 | wait for clock_period; 388 | i <= "000000000000010000000010000000000000000000"; 389 | wait for clock_period; 390 | i <= "000000000000000000000000000000000000000000"; 391 | wait for clock_period; 392 | i <= "000000000000010000000000001000000000000000"; 393 | wait for clock_period; 394 | i <= "000000000000000000000000000000000000000000"; 395 | wait for clock_period; 396 | i <= "000000000000010000000000000000001000000000"; 397 | wait for clock_period; 398 | i <= "000000000000000000000000000000000000000000"; 399 | wait for clock_period; 400 | i <= "000000000000010000000000000000000000000001"; 401 | wait for clock_period; 402 | i <= "000000000000000000000000000000000000000000"; 403 | wait for clock_period; 404 | i <= "000000000000001000001000000000000000000000"; 405 | wait for clock_period; 406 | i <= "000000000000000000000000000000000000000000"; 407 | wait for clock_period; 408 | i <= "000000000000001000000000000100000000000000"; 409 | wait for clock_period; 410 | i <= "000000000000000000000000000000000000000000"; 411 | wait for clock_period; 412 | i <= "000000000000001000000000000000000100000000"; 413 | wait for clock_period; 414 | i <= "000000000000000000000000000000000000000000"; 415 | wait for clock_period; 416 | i <= "000000000000001000000000000000000010000000"; 417 | wait for clock_period; 418 | i <= "000000000000000000000000000000000000000000"; 419 | wait for clock_period; 420 | i <= "000000000000000100000100000000000000000000"; 421 | wait for clock_period; 422 | i <= "000000000000000000000000000000000000000000"; 423 | wait for clock_period; 424 | i <= "000000000000000100000000000010000000000000"; 425 | wait for clock_period; 426 | i <= "000000000000000000000000000000000000000000"; 427 | wait for clock_period; 428 | i <= "000000000000000100000000000000000001000000"; 429 | wait for clock_period; 430 | i <= "000000000000000000000000000000000000000000"; 431 | wait for clock_period; 432 | i <= "000000000000000100000000000000000000010000"; 433 | wait for clock_period; 434 | i <= "000000000000000000000000000000000000000000"; 435 | wait for clock_period; 436 | i <= "000000000000000010000001000000000000000000"; 437 | wait for clock_period; 438 | i <= "000000000000000000000000000000000000000000"; 439 | wait for clock_period; 440 | i <= "000000000000000010000000000001000000000000"; 441 | wait for clock_period; 442 | i <= "000000000000000000000000000000000000000000"; 443 | wait for clock_period; 444 | i <= "000000000000000010000000000000000000100000"; 445 | wait for clock_period; 446 | i <= "000000000000000000000000000000000000000000"; 447 | wait for clock_period; 448 | i <= "000000000000000010000000000000000000001000"; 449 | wait for clock_period; 450 | i <= "000000000000000000000000000000000000000000"; 451 | wait for clock_period; 452 | i <= "000000000000000001000000100000000000000000"; 453 | wait for clock_period; 454 | i <= "000000000000000000000000000000000000000000"; 455 | wait for clock_period; 456 | i <= "000000000000000001000000000000100000000000"; 457 | wait for clock_period; 458 | i <= "000000000000000000000000000000000000000000"; 459 | wait for clock_period; 460 | i <= "000000000000000001000000000000000000000100"; 461 | wait for clock_period; 462 | i <= "000000000000000000000000000000000000000000"; 463 | wait for clock_period; 464 | i <= "000000000000000000100000010000000000000000"; 465 | wait for clock_period; 466 | i <= "000000000000000000000000000000000000000000"; 467 | wait for clock_period; 468 | i <= "000000000000000000100000000000010000000000"; 469 | wait for clock_period; 470 | i <= "000000000000000000000000000000000000000000"; 471 | wait for clock_period; 472 | i <= "000000000000000000100000000000000000000010"; 473 | wait for clock_period; 474 | i <= "000000000000000000000000000000000000000000"; 475 | wait for clock_period; 476 | i <= "000000000000000000010010000000000000000000"; 477 | wait for clock_period; 478 | i <= "000000000000000000000000000000000000000000"; 479 | wait for clock_period; 480 | i <= "000000000000000000010000001000000000000000"; 481 | wait for clock_period; 482 | i <= "000000000000000000000000000000000000000000"; 483 | wait for clock_period; 484 | i <= "000000000000000000010000000000001000000000"; 485 | wait for clock_period; 486 | i <= "000000000000000000000000000000000000000000"; 487 | wait for clock_period; 488 | i <= "000000000000000000010000000000000000000001"; 489 | wait for clock_period; 490 | i <= "000000000000000000000000000000000000000000"; 491 | wait for clock_period; 492 | i <= "000000000000000000001000000100000000000000"; 493 | wait for clock_period; 494 | i <= "000000000000000000000000000000000000000000"; 495 | wait for clock_period; 496 | i <= "000000000000000000001000000000000100000000"; 497 | wait for clock_period; 498 | i <= "000000000000000000000000000000000000000000"; 499 | wait for clock_period; 500 | i <= "000000000000000000001000000000000010000000"; 501 | wait for clock_period; 502 | i <= "000000000000000000000000000000000000000000"; 503 | wait for clock_period; 504 | i <= "000000000000000000000100000010000000000000"; 505 | wait for clock_period; 506 | i <= "000000000000000000000000000000000000000000"; 507 | wait for clock_period; 508 | i <= "000000000000000000000100000000000001000000"; 509 | wait for clock_period; 510 | i <= "000000000000000000000000000000000000000000"; 511 | wait for clock_period; 512 | i <= "000000000000000000000100000000000000010000"; 513 | wait for clock_period; 514 | i <= "000000000000000000000000000000000000000000"; 515 | wait for clock_period; 516 | i <= "000000000000000000000010001000000000000000"; 517 | wait for clock_period; 518 | i <= "000000000000000000000000000000000000000000"; 519 | wait for clock_period; 520 | i <= "000000000000000000000010000000001000000000"; 521 | wait for clock_period; 522 | i <= "000000000000000000000000000000000000000000"; 523 | wait for clock_period; 524 | i <= "000000000000000000000010000000000000000001"; 525 | wait for clock_period; 526 | i <= "000000000000000000000000000000000000000000"; 527 | wait for clock_period; 528 | i <= "000000000000000000000001000001000000000000"; 529 | wait for clock_period; 530 | i <= "000000000000000000000000000000000000000000"; 531 | wait for clock_period; 532 | i <= "000000000000000000000001000000000000100000"; 533 | wait for clock_period; 534 | i <= "000000000000000000000000000000000000000000"; 535 | wait for clock_period; 536 | i <= "000000000000000000000001000000000000001000"; 537 | wait for clock_period; 538 | i <= "000000000000000000000000000000000000000000"; 539 | wait for clock_period; 540 | i <= "000000000000000000000000100000100000000000"; 541 | wait for clock_period; 542 | i <= "000000000000000000000000000000000000000000"; 543 | wait for clock_period; 544 | i <= "000000000000000000000000100000000000000100"; 545 | wait for clock_period; 546 | i <= "000000000000000000000000000000000000000000"; 547 | wait for clock_period; 548 | i <= "000000000000000000000000010000010000000000"; 549 | wait for clock_period; 550 | i <= "000000000000000000000000000000000000000000"; 551 | wait for clock_period; 552 | i <= "000000000000000000000000010000000000000010"; 553 | wait for clock_period; 554 | i <= "000000000000000000000000000000000000000000"; 555 | wait for clock_period; 556 | i <= "000000000000000000000000001000001000000000"; 557 | wait for clock_period; 558 | i <= "000000000000000000000000000000000000000000"; 559 | wait for clock_period; 560 | i <= "000000000000000000000000001000000000000001"; 561 | wait for clock_period; 562 | i <= "000000000000000000000000000000000000000000"; 563 | wait for clock_period; 564 | i <= "000000000000000000000000000100000100000000"; 565 | wait for clock_period; 566 | i <= "000000000000000000000000000000000000000000"; 567 | wait for clock_period; 568 | i <= "000000000000000000000000000100000010000000"; 569 | wait for clock_period; 570 | i <= "000000000000000000000000000000000000000000"; 571 | wait for clock_period; 572 | i <= "000000000000000000000000000010000001000000"; 573 | wait for clock_period; 574 | i <= "000000000000000000000000000000000000000000"; 575 | wait for clock_period; 576 | i <= "000000000000000000000000000010000000010000"; 577 | wait for clock_period; 578 | i <= "000000000000000000000000000000000000000000"; 579 | wait for clock_period; 580 | i <= "000000000000000000000000000001000000100000"; 581 | wait for clock_period; 582 | i <= "000000000000000000000000000000000000000000"; 583 | wait for clock_period; 584 | i <= "000000000000000000000000000001000000001000"; 585 | wait for clock_period; 586 | i <= "000000000000000000000000000000000000000000"; 587 | wait for clock_period; 588 | i <= "000000000000000000000000000000100000000100"; 589 | wait for clock_period; 590 | i <= "000000000000000000000000000000000000000000"; 591 | wait for clock_period; 592 | i <= "000000000000000000000000000000010000000010"; 593 | wait for clock_period; 594 | i <= "000000000000000000000000000000000000000000"; 595 | wait for clock_period; 596 | i <= "000000000000000000000000000000001000000001"; 597 | wait for clock_period; 598 | i <= "000000000000000000000000000000000000000000"; 599 | wait for clock_period; 600 | i <= "000000000000000000000000000000000110000000"; 601 | wait for clock_period; 602 | i <= "000000000000000000000000000000000000000000"; 603 | wait for clock_period; 604 | i <= "000000000000000000000000000000000001010000"; 605 | wait for clock_period; 606 | i <= "000000000000000000000000000000000000000000"; 607 | wait for clock_period; 608 | i <= "000000000000000000000000000000000000101000"; 609 | wait for clock_period; 610 | i <= "100000000001000000000010000000000100011000"; 611 | wait for clock_period; 612 | i <= "000000000000000000000000000000000000000000"; 613 | wait for clock_period; 614 | i <= "011100000000000000000000000000000000000111"; 615 | wait for clock_period; 616 | i <= "000000000000000000000000000000000000000000"; 617 | wait for clock_period; 618 | i <= "000011111100000000000000000000000000000000"; 619 | wait for clock_period; 620 | i <= "000000000000000000000000000000000000000000"; 621 | wait for clock_period; 622 | i <= "000000000010111110000000000000000000000000"; 623 | wait for clock_period; 624 | i <= "000000000000000000000000000000000000000000"; 625 | wait for clock_period; 626 | i <= "000000000000000001111101000000000000000000"; 627 | wait for clock_period; 628 | i <= "000000000000000000000000000000000000000000"; 629 | wait for clock_period; 630 | i <= "000000000000000000000000111111000000000000"; 631 | wait for clock_period; 632 | i <= "000000000000000000000000000000000000000000"; 633 | wait for clock_period; 634 | i <= "000000000000000000000000000000111011100000"; 635 | wait for clock_period; 636 | i <= "000000000000000000000000000000000000000000"; 637 | wait for clock_period; 638 | 639 | load <= '0'; 640 | 641 | -- insert stimulus here 642 | 643 | wait; 644 | end process; 645 | 646 | END; 647 | --------------------------------------------------------------------------------