├── DE2_CCD_PIP ├── CCD_Capture.v ├── DE2_CCD_PIP.v ├── I2C_CCD_Config.v ├── I2C_Controller.v ├── Line_Buffer.v ├── Mirror_Col_2X.v ├── Mirror_Col_4X.v ├── RAW2RGB_2X.v ├── RAW2RGB_4X.v ├── Reset_Delay.v ├── SEG7_LUT.v ├── SEG7_LUT_8.v ├── Sdram_Control_4Port │ ├── Sdram_Control_4Port.v │ ├── Sdram_FIFO.v │ ├── Sdram_PLL.v │ ├── Sdram_Params.h │ ├── command.v │ ├── control_interface.v │ └── sdr_data_path.v ├── Sdram_Params.h ├── Stack_2X_RAM.v ├── Stack_4X_RAM.v ├── VGA_Controller.v └── VGA_Param.h ├── DE2_CCD_edge ├── CCD_Capture.v ├── DE2_CCD.v ├── I2C_CCD_Config.v ├── I2C_Controller.v ├── RAW2RGB.v ├── RGB2YUV.v ├── RGB2YUV_TOP.v ├── Reset_Delay.v ├── SEG7_LUT.v ├── SEG7_LUT_8.v ├── Sdram_Control_4Port │ ├── .command.v.swp │ ├── 42S16400B.pdf │ ├── Sdram_Control_4Port.v │ ├── Sdram_FIFO.v │ ├── Sdram_PLL.v │ ├── Sdram_Params.h │ ├── command.v │ ├── control_interface.v │ └── sdr_data_path.v ├── Sdram_Params.h ├── VGA_Controller.v ├── VGA_Param.h ├── YUV2RGB.v ├── buffer.v ├── const_mult.v ├── control.v ├── ctrl.v ├── filter.v ├── four_mult_two_add.v ├── gen_ram_rdadd.v ├── gen_ram_rden.v ├── gen_ram_rden_tb.v ├── gen_ram_wradd.v ├── gen_ram_wren.v ├── gen_ram_wren_tb.v ├── mux_ram_row.v ├── mux_row.v ├── one_mult.v ├── ram.v ├── ram_blk.v ├── ram_block.v ├── two_d_filter.v └── two_d_filter_tb.v ├── DE2_CCD_gray ├── CCD_Capture.v ├── DE2_CCD.v ├── I2C_CCD_Config.v ├── I2C_Controller.v ├── Line_Buffer.v ├── Mirror_Col.v ├── RAW2RGB.v ├── RGB2Gray.v ├── Reset_Delay.v ├── SEG7_LUT.v ├── SEG7_LUT_8.v ├── Sdram_Control_4Port │ ├── Sdram_Control_4Port.v │ ├── Sdram_FIFO.v │ ├── Sdram_PLL.v │ ├── Sdram_Params.h │ ├── command.v │ ├── control_interface.v │ └── sdr_data_path.v ├── Sdram_Params.h ├── Stack_RAM.v ├── VGA_Controller.v └── VGA_Param.h ├── DE2_CCD_smooth ├── CCD_Capture.v ├── DE2_CCD_smooth.v ├── I2C_CCD_Config.v ├── I2C_Controller.v ├── Line_Buffer.v ├── Mirror_Col.v ├── Multiply.v ├── RAW2RGB.v ├── RGB2Gray.v ├── Reset_Delay.v ├── SEG7_LUT.v ├── SEG7_LUT_8.v ├── Sdram_Control_4Port │ ├── Sdram_Control_4Port.v │ ├── Sdram_FIFO.v │ ├── Sdram_PLL.v │ ├── Sdram_Params.h │ ├── command.v │ ├── control_interface.v │ └── sdr_data_path.v ├── Sdram_Params.h ├── Stack_RAM.v ├── VGA_Controller.v ├── VGA_Param.h ├── denoise_smooth.v ├── filter_buffer.v └── pa.v └── read.md /DE2_CCD_PIP/CCD_Capture.v: -------------------------------------------------------------------------------- 1 | module CCD_Capture( oDATA, 2 | oDVAL, 3 | oX_Cont, 4 | oY_Cont, 5 | oFrame_Cont, 6 | iDATA, 7 | iFVAL, 8 | iLVAL, 9 | iSTART, 10 | iEND, 11 | iCLK, 12 | iRST ); 13 | 14 | input [9:0] iDATA; 15 | input iFVAL; 16 | input iLVAL; 17 | input iSTART; 18 | input iEND; 19 | input iCLK; 20 | input iRST; 21 | output [9:0] oDATA; 22 | output [10:0] oX_Cont; 23 | output [10:0] oY_Cont; 24 | output [31:0] oFrame_Cont; 25 | output oDVAL; 26 | reg Pre_FVAL; 27 | reg mCCD_FVAL; 28 | reg mCCD_LVAL; 29 | reg [9:0] mCCD_DATA; 30 | reg [10:0] X_Cont; 31 | reg [10:0] Y_Cont; 32 | reg [31:0] Frame_Cont; 33 | reg mSTART; 34 | 35 | assign oX_Cont = X_Cont; 36 | assign oY_Cont = Y_Cont; 37 | assign oFrame_Cont = Frame_Cont; 38 | assign oDATA = mCCD_DATA; 39 | assign oDVAL = mCCD_FVAL&mCCD_LVAL; 40 | 41 | always@(posedge iCLK or negedge iRST) 42 | begin 43 | if(!iRST) 44 | mSTART <= 0; 45 | else 46 | begin 47 | if(iSTART) 48 | mSTART <= 1; 49 | if(iEND) 50 | mSTART <= 0; 51 | end 52 | end 53 | 54 | always@(posedge iCLK or negedge iRST) 55 | begin 56 | if(!iRST) 57 | begin 58 | Pre_FVAL <= 0; 59 | mCCD_FVAL <= 0; 60 | mCCD_LVAL <= 0; 61 | mCCD_DATA <= 0; 62 | X_Cont <= 0; 63 | Y_Cont <= 0; 64 | end 65 | else 66 | begin 67 | Pre_FVAL <= iFVAL; 68 | if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART ) 69 | mCCD_FVAL <= 1; 70 | else if({Pre_FVAL,iFVAL}==2'b10) 71 | mCCD_FVAL <= 0; 72 | mCCD_LVAL <= iLVAL; 73 | mCCD_DATA <= iDATA; 74 | if(mCCD_FVAL) 75 | begin 76 | if(mCCD_LVAL) 77 | begin 78 | if(X_Cont<1279) 79 | X_Cont <= X_Cont+1; 80 | else 81 | begin 82 | X_Cont <= 0; 83 | Y_Cont <= Y_Cont+1; 84 | end 85 | end 86 | end 87 | else 88 | begin 89 | X_Cont <= 0; 90 | Y_Cont <= 0; 91 | end 92 | end 93 | end 94 | 95 | always@(posedge iCLK or negedge iRST) 96 | begin 97 | if(!iRST) 98 | Frame_Cont <= 0; 99 | else 100 | begin 101 | if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART ) 102 | Frame_Cont <= Frame_Cont+1; 103 | end 104 | end 105 | 106 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_PIP/I2C_CCD_Config.v: -------------------------------------------------------------------------------- 1 | module I2C_CCD_Config ( // Host Side 2 | iCLK, 3 | iRST_N, 4 | iExposure, 5 | // I2C Side 6 | I2C_SCLK, 7 | I2C_SDAT ); 8 | // Host Side 9 | input iCLK; 10 | input iRST_N; 11 | input [15:0] iExposure; 12 | // I2C Side 13 | output I2C_SCLK; 14 | inout I2C_SDAT; 15 | // Internal Registers/Wires 16 | reg [15:0] mI2C_CLK_DIV; 17 | reg [23:0] mI2C_DATA; 18 | reg mI2C_CTRL_CLK; 19 | reg mI2C_GO; 20 | wire mI2C_END; 21 | wire mI2C_ACK; 22 | reg [15:0] LUT_DATA; 23 | reg [5:0] LUT_INDEX; 24 | reg [3:0] mSetup_ST; 25 | 26 | // Clock Setting 27 | parameter CLK_Freq = 50000000; // 50 MHz 28 | parameter I2C_Freq = 20000; // 20 KHz 29 | // LUT Data Number 30 | parameter LUT_SIZE = 17; 31 | 32 | ///////////////////// I2C Control Clock //////////////////////// 33 | always@(posedge iCLK or negedge iRST_N) 34 | begin 35 | if(!iRST_N) 36 | begin 37 | mI2C_CTRL_CLK <= 0; 38 | mI2C_CLK_DIV <= 0; 39 | end 40 | else 41 | begin 42 | if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) ) 43 | mI2C_CLK_DIV <= mI2C_CLK_DIV+1; 44 | else 45 | begin 46 | mI2C_CLK_DIV <= 0; 47 | mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK; 48 | end 49 | end 50 | end 51 | //////////////////////////////////////////////////////////////////// 52 | I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock 53 | .I2C_SCLK(I2C_SCLK), // I2C CLOCK 54 | .I2C_SDAT(I2C_SDAT), // I2C DATA 55 | .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA] 56 | .GO(mI2C_GO), // GO transfor 57 | .END(mI2C_END), // END transfor 58 | .ACK(mI2C_ACK), // ACK 59 | .RESET(iRST_N) ); 60 | //////////////////////////////////////////////////////////////////// 61 | ////////////////////// Config Control //////////////////////////// 62 | always@(posedge mI2C_CTRL_CLK or negedge iRST_N) 63 | begin 64 | if(!iRST_N) 65 | begin 66 | LUT_INDEX <= 0; 67 | mSetup_ST <= 0; 68 | mI2C_GO <= 0; 69 | end 70 | else 71 | begin 72 | if(LUT_INDEX= 4) & (SD_COUNTER <=30))? ~CLOCK :0 ); 78 | wire I2C_SDAT=SDO?1'bz:0 ; 79 | 80 | reg ACK1,ACK2,ACK3; 81 | wire ACK=ACK1 | ACK2 |ACK3; 82 | 83 | //--I2C COUNTER 84 | always @(negedge RESET or posedge CLOCK ) begin 85 | if (!RESET) SD_COUNTER=6'b111111; 86 | else begin 87 | if (GO==0) 88 | SD_COUNTER=0; 89 | else 90 | if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+1; 91 | end 92 | end 93 | //---- 94 | 95 | always @(negedge RESET or posedge CLOCK ) begin 96 | if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end 97 | else 98 | case (SD_COUNTER) 99 | 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end 100 | //start 101 | 6'd1 : begin SD=I2C_DATA;SDO=0;end 102 | 6'd2 : SCLK=0; 103 | //SLAVE ADDR 104 | 6'd3 : SDO=SD[23]; 105 | 6'd4 : SDO=SD[22]; 106 | 6'd5 : SDO=SD[21]; 107 | 6'd6 : SDO=SD[20]; 108 | 6'd7 : SDO=SD[19]; 109 | 6'd8 : SDO=SD[18]; 110 | 6'd9 : SDO=SD[17]; 111 | 6'd10 : SDO=SD[16]; 112 | 6'd11 : SDO=1'b1;//ACK 113 | 114 | //SUB ADDR 115 | 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end 116 | 6'd13 : SDO=SD[14]; 117 | 6'd14 : SDO=SD[13]; 118 | 6'd15 : SDO=SD[12]; 119 | 6'd16 : SDO=SD[11]; 120 | 6'd17 : SDO=SD[10]; 121 | 6'd18 : SDO=SD[9]; 122 | 6'd19 : SDO=SD[8]; 123 | 6'd20 : SDO=1'b1;//ACK 124 | 125 | //DATA 126 | 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end 127 | 6'd22 : SDO=SD[6]; 128 | 6'd23 : SDO=SD[5]; 129 | 6'd24 : SDO=SD[4]; 130 | 6'd25 : SDO=SD[3]; 131 | 6'd26 : SDO=SD[2]; 132 | 6'd27 : SDO=SD[1]; 133 | 6'd28 : SDO=SD[0]; 134 | 6'd29 : SDO=1'b1;//ACK 135 | 136 | 137 | //stop 138 | 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end 139 | 6'd31 : SCLK=1'b1; 140 | 6'd32 : begin SDO=1'b1; END=1; end 141 | 142 | endcase 143 | end 144 | 145 | 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/Line_Buffer.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %Shift register (RAM-based)% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altshift_taps 5 | 6 | // ============================================================ 7 | // File Name: Line_Buffer.v 8 | // Megafunction Name(s): 9 | // altshift_taps 10 | // ============================================================ 11 | // ************************************************************ 12 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 13 | // 14 | // 5.1 Build 176 10/26/2005 SJ Full Version 15 | // ************************************************************ 16 | 17 | 18 | //Copyright (C) 1991-2005 Altera Corporation 19 | //Your use of Altera Corporation's design tools, logic functions 20 | //and other software and tools, and its AMPP partner logic 21 | //functions, and any output files any of the foregoing 22 | //(including device programming or simulation files), and any 23 | //associated documentation or information are expressly subject 24 | //to the terms and conditions of the Altera Program License 25 | //Subscription Agreement, Altera MegaCore Function License 26 | //Agreement, or other applicable license agreement, including, 27 | //without limitation, that your use is for the sole purpose of 28 | //programming logic devices manufactured by Altera and sold by 29 | //Altera or its authorized distributors. Please refer to the 30 | //applicable agreement for further details. 31 | 32 | 33 | // synopsys translate_off 34 | `timescale 1 ps / 1 ps 35 | // synopsys translate_on 36 | module Line_Buffer ( 37 | clken, 38 | clock, 39 | shiftin, 40 | shiftout, 41 | taps0x, 42 | taps1x); 43 | 44 | input clken; 45 | input clock; 46 | input [9:0] shiftin; 47 | output [9:0] shiftout; 48 | output [9:0] taps0x; 49 | output [9:0] taps1x; 50 | 51 | wire [19:0] sub_wire0; 52 | wire [9:0] sub_wire3; 53 | wire [19:10] sub_wire1 = sub_wire0[19:10]; 54 | wire [9:0] sub_wire2 = sub_wire0[9:0]; 55 | wire [9:0] taps1x = sub_wire1[19:10]; 56 | wire [9:0] taps0x = sub_wire2[9:0]; 57 | wire [9:0] shiftout = sub_wire3[9:0]; 58 | 59 | altshift_taps altshift_taps_component ( 60 | .clken (clken), 61 | .clock (clock), 62 | .shiftin (shiftin), 63 | .taps (sub_wire0), 64 | .shiftout (sub_wire3)); 65 | defparam 66 | altshift_taps_component.lpm_type = "altshift_taps", 67 | altshift_taps_component.number_of_taps = 2, 68 | altshift_taps_component.tap_distance = 1280, 69 | altshift_taps_component.width = 10; 70 | 71 | 72 | endmodule 73 | 74 | // ============================================================ 75 | // CNX file retrieval info 76 | // ============================================================ 77 | // Retrieval info: PRIVATE: CLKEN NUMERIC "1" 78 | // Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1" 79 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 80 | // Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2" 81 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 82 | // Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280" 83 | // Retrieval info: PRIVATE: WIDTH NUMERIC "10" 84 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps" 85 | // Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2" 86 | // Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280" 87 | // Retrieval info: CONSTANT: WIDTH NUMERIC "10" 88 | // Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken 89 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 90 | // Retrieval info: USED_PORT: shiftin 0 0 10 0 INPUT NODEFVAL shiftin[9..0] 91 | // Retrieval info: USED_PORT: shiftout 0 0 10 0 OUTPUT NODEFVAL shiftout[9..0] 92 | // Retrieval info: USED_PORT: taps0x 0 0 10 0 OUTPUT NODEFVAL taps0x[9..0] 93 | // Retrieval info: USED_PORT: taps1x 0 0 10 0 OUTPUT NODEFVAL taps1x[9..0] 94 | // Retrieval info: CONNECT: @shiftin 0 0 10 0 shiftin 0 0 10 0 95 | // Retrieval info: CONNECT: shiftout 0 0 10 0 @shiftout 0 0 10 0 96 | // Retrieval info: CONNECT: taps0x 0 0 10 0 @taps 0 0 10 0 97 | // Retrieval info: CONNECT: taps1x 0 0 10 0 @taps 0 0 10 10 98 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 99 | // Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 100 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 101 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE 102 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE 103 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf FALSE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE 107 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/Mirror_Col_2X.v: -------------------------------------------------------------------------------- 1 | module Mirror_Col_2X( // Input Side 2 | iCCD_R, 3 | iCCD_G, 4 | iCCD_B, 5 | iCCD_DVAL, 6 | iCCD_PIXCLK, 7 | iRST_N, 8 | // Output Side 9 | oCCD_R, 10 | oCCD_G, 11 | oCCD_B, 12 | oCCD_DVAL ); 13 | // Input Side 14 | input [9:0] iCCD_R; 15 | input [9:0] iCCD_G; 16 | input [9:0] iCCD_B; 17 | input iCCD_DVAL; 18 | input iCCD_PIXCLK; 19 | input iRST_N; 20 | // Output Side 21 | output [9:0] oCCD_R; 22 | output [9:0] oCCD_G; 23 | output [9:0] oCCD_B; 24 | output oCCD_DVAL; 25 | // Internal Registers 26 | reg [9:0] Z_Cont; 27 | reg mCCD_DVAL; 28 | 29 | assign oCCD_DVAL = mCCD_DVAL; 30 | 31 | always@(posedge iCCD_PIXCLK or negedge iRST_N) 32 | begin 33 | if(!iRST_N) 34 | begin 35 | mCCD_DVAL <= 0; 36 | Z_Cont <= 0; 37 | end 38 | else 39 | begin 40 | mCCD_DVAL <= iCCD_DVAL; 41 | if(Z_Cont<640) 42 | begin 43 | if(iCCD_DVAL) 44 | Z_Cont <= Z_Cont+1'b1; 45 | end 46 | else 47 | Z_Cont <= 0; 48 | end 49 | end 50 | 51 | Stack_2X_RAM ( .clock(iCCD_PIXCLK), 52 | .data(iCCD_R), 53 | .rdaddress(639-Z_Cont), 54 | .wraddress(Z_Cont), 55 | .wren(iCCD_DVAL), 56 | .q(oCCD_R)); 57 | 58 | Stack_2X_RAM ( .clock(iCCD_PIXCLK), 59 | .data(iCCD_G), 60 | .rdaddress(639-Z_Cont), 61 | .wraddress(Z_Cont), 62 | .wren(iCCD_DVAL), 63 | .q(oCCD_G)); 64 | 65 | Stack_2X_RAM ( .clock(iCCD_PIXCLK), 66 | .data(iCCD_B), 67 | .rdaddress(639-Z_Cont), 68 | .wraddress(Z_Cont), 69 | .wren(iCCD_DVAL), 70 | .q(oCCD_B)); 71 | 72 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_PIP/Mirror_Col_4X.v: -------------------------------------------------------------------------------- 1 | module Mirror_Col_4X( // Input Side 2 | iCCD_R, 3 | iCCD_G, 4 | iCCD_B, 5 | iCCD_DVAL, 6 | iCCD_PIXCLK, 7 | iRST_N, 8 | // Output Side 9 | oCCD_R, 10 | oCCD_G, 11 | oCCD_B, 12 | oCCD_DVAL ); 13 | // Input Side 14 | input [9:0] iCCD_R; 15 | input [9:0] iCCD_G; 16 | input [9:0] iCCD_B; 17 | input iCCD_DVAL; 18 | input iCCD_PIXCLK; 19 | input iRST_N; 20 | // Output Side 21 | output [9:0] oCCD_R; 22 | output [9:0] oCCD_G; 23 | output [9:0] oCCD_B; 24 | output oCCD_DVAL; 25 | // Internal Registers 26 | reg [9:0] Z_Cont; 27 | reg mCCD_DVAL; 28 | 29 | assign oCCD_DVAL = mCCD_DVAL; 30 | 31 | always@(posedge iCCD_PIXCLK or negedge iRST_N) 32 | begin 33 | if(!iRST_N) 34 | begin 35 | mCCD_DVAL <= 0; 36 | Z_Cont <= 0; 37 | end 38 | else 39 | begin 40 | mCCD_DVAL <= iCCD_DVAL; 41 | if(Z_Cont<320) 42 | begin 43 | if(iCCD_DVAL) 44 | Z_Cont <= Z_Cont+1'b1; 45 | end 46 | else 47 | Z_Cont <= 0; 48 | end 49 | end 50 | 51 | Stack_4X_RAM ( .clock(iCCD_PIXCLK), 52 | .data(iCCD_R), 53 | .rdaddress(319-Z_Cont), 54 | .wraddress(Z_Cont), 55 | .wren(iCCD_DVAL), 56 | .q(oCCD_R)); 57 | 58 | Stack_4X_RAM ( .clock(iCCD_PIXCLK), 59 | .data(iCCD_G), 60 | .rdaddress(319-Z_Cont), 61 | .wraddress(Z_Cont), 62 | .wren(iCCD_DVAL), 63 | .q(oCCD_G)); 64 | 65 | Stack_4X_RAM ( .clock(iCCD_PIXCLK), 66 | .data(iCCD_B), 67 | .rdaddress(319-Z_Cont), 68 | .wraddress(Z_Cont), 69 | .wren(iCCD_DVAL), 70 | .q(oCCD_B)); 71 | 72 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_PIP/RAW2RGB_2X.v: -------------------------------------------------------------------------------- 1 | module RAW2RGB_2X( oRed, 2 | oGreen, 3 | oBlue, 4 | oDVAL, 5 | iX_Cont, 6 | iY_Cont, 7 | iDATA, 8 | iDVAL, 9 | iCLK, 10 | iRST ); 11 | 12 | input [10:0] iX_Cont; 13 | input [10:0] iY_Cont; 14 | input [9:0] iDATA; 15 | input iDVAL; 16 | input iCLK; 17 | input iRST; 18 | output [9:0] oRed; 19 | output [9:0] oGreen; 20 | output [9:0] oBlue; 21 | output oDVAL; 22 | wire [9:0] mDATA_0; 23 | wire [9:0] mDATA_1; 24 | reg [9:0] mDATAd_0; 25 | reg [9:0] mDATAd_1; 26 | reg [9:0] mCCD_R; 27 | reg [10:0] mCCD_G; 28 | reg [9:0] mCCD_B; 29 | reg mDVAL; 30 | 31 | assign oRed = mCCD_R[9:0]; 32 | assign oGreen = mCCD_G[10:1]; 33 | assign oBlue = mCCD_B[9:0]; 34 | assign oDVAL = mDVAL; 35 | 36 | Line_Buffer u0 ( .clken(iDVAL), 37 | .clock(iCLK), 38 | .shiftin(iDATA), 39 | .taps0x(mDATA_1), 40 | .taps1x(mDATA_0) ); 41 | 42 | always@(posedge iCLK or negedge iRST) 43 | begin 44 | if(!iRST) 45 | begin 46 | mCCD_R <= 0; 47 | mCCD_G <= 0; 48 | mCCD_B <= 0; 49 | mDATAd_0<= 0; 50 | mDATAd_1<= 0; 51 | mDVAL <= 0; 52 | end 53 | else 54 | begin 55 | mDATAd_0 <= mDATA_0; 56 | mDATAd_1 <= mDATA_1; 57 | mDVAL <= (iY_Cont[0]|iX_Cont[0]) ? 1'b0 : iDVAL; 58 | if({iY_Cont[0],iX_Cont[0]}==2'b01) 59 | begin 60 | mCCD_R <= mDATA_0; 61 | mCCD_G <= mDATAd_0+mDATA_1; 62 | mCCD_B <= mDATAd_1; 63 | end 64 | else if({iY_Cont[0],iX_Cont[0]}==2'b00) 65 | begin 66 | mCCD_R <= mDATAd_0; 67 | mCCD_G <= mDATA_0+mDATAd_1; 68 | mCCD_B <= mDATA_1; 69 | end 70 | else if({iY_Cont[0],iX_Cont[0]}==2'b11) 71 | begin 72 | mCCD_R <= mDATA_1; 73 | mCCD_G <= mDATA_0+mDATAd_1; 74 | mCCD_B <= mDATAd_0; 75 | end 76 | else if({iY_Cont[0],iX_Cont[0]}==2'b10) 77 | begin 78 | mCCD_R <= mDATAd_1; 79 | mCCD_G <= mDATAd_0+mDATA_1; 80 | mCCD_B <= mDATA_0; 81 | end 82 | end 83 | end 84 | 85 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_PIP/RAW2RGB_4X.v: -------------------------------------------------------------------------------- 1 | module RAW2RGB_4X( oRed, 2 | oGreen, 3 | oBlue, 4 | oDVAL, 5 | iX_Cont, 6 | iY_Cont, 7 | iDATA, 8 | iDVAL, 9 | iCLK, 10 | iRST ); 11 | 12 | input [10:0] iX_Cont; 13 | input [10:0] iY_Cont; 14 | input [9:0] iDATA; 15 | input iDVAL; 16 | input iCLK; 17 | input iRST; 18 | output [9:0] oRed; 19 | output [9:0] oGreen; 20 | output [9:0] oBlue; 21 | output oDVAL; 22 | wire [9:0] mDATA_0; 23 | wire [9:0] mDATA_1; 24 | reg [9:0] mDATAd_0; 25 | reg [9:0] mDATAd_1; 26 | reg [9:0] mCCD_R; 27 | reg [10:0] mCCD_G; 28 | reg [9:0] mCCD_B; 29 | reg mDVAL; 30 | 31 | assign oRed = mCCD_R[9:0]; 32 | assign oGreen = mCCD_G[10:1]; 33 | assign oBlue = mCCD_B[9:0]; 34 | assign oDVAL = mDVAL; 35 | 36 | Line_Buffer u0 ( .clken(iDVAL), 37 | .clock(iCLK), 38 | .shiftin(iDATA), 39 | .taps0x(mDATA_1), 40 | .taps1x(mDATA_0) ); 41 | 42 | always@(posedge iCLK or negedge iRST) 43 | begin 44 | if(!iRST) 45 | begin 46 | mCCD_R <= 0; 47 | mCCD_G <= 0; 48 | mCCD_B <= 0; 49 | mDATAd_0<= 0; 50 | mDATAd_1<= 0; 51 | mDVAL <= 0; 52 | end 53 | else 54 | begin 55 | mDATAd_0 <= mDATA_0; 56 | mDATAd_1 <= mDATA_1; 57 | mDVAL <= ( (|iY_Cont[1:0]) | (|iX_Cont[1:0]) ) ? 1'b0 : iDVAL; 58 | if({iY_Cont[0],iX_Cont[0]}==2'b01) 59 | begin 60 | mCCD_R <= mDATA_0; 61 | mCCD_G <= mDATAd_0+mDATA_1; 62 | mCCD_B <= mDATAd_1; 63 | end 64 | else if({iY_Cont[0],iX_Cont[0]}==2'b00) 65 | begin 66 | mCCD_R <= mDATAd_0; 67 | mCCD_G <= mDATA_0+mDATAd_1; 68 | mCCD_B <= mDATA_1; 69 | end 70 | else if({iY_Cont[0],iX_Cont[0]}==2'b11) 71 | begin 72 | mCCD_R <= mDATA_1; 73 | mCCD_G <= mDATA_0+mDATAd_1; 74 | mCCD_B <= mDATAd_0; 75 | end 76 | else if({iY_Cont[0],iX_Cont[0]}==2'b10) 77 | begin 78 | mCCD_R <= mDATAd_1; 79 | mCCD_G <= mDATAd_0+mDATA_1; 80 | mCCD_B <= mDATA_0; 81 | end 82 | end 83 | end 84 | 85 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_PIP/Reset_Delay.v: -------------------------------------------------------------------------------- 1 | module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2); 2 | input iCLK; 3 | input iRST; 4 | output reg oRST_0; 5 | output reg oRST_1; 6 | output reg oRST_2; 7 | 8 | reg [21:0] Cont; 9 | 10 | always@(posedge iCLK or negedge iRST) 11 | begin 12 | if(!iRST) 13 | begin 14 | Cont <= 0; 15 | oRST_0 <= 0; 16 | oRST_1 <= 0; 17 | oRST_2 <= 0; 18 | end 19 | else 20 | begin 21 | if(Cont!=22'h3FFFFF) 22 | Cont <= Cont+1; 23 | if(Cont>=22'h1FFFFF) 24 | oRST_0 <= 1; 25 | if(Cont>=22'h2FFFFF) 26 | oRST_1 <= 1; 27 | if(Cont>=22'h3FFFFF) 28 | oRST_2 <= 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_PIP/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT ( oSEG,iDIG ); 2 | input [3:0] iDIG; 3 | output [6:0] oSEG; 4 | reg [6:0] oSEG; 5 | 6 | always @(iDIG) 7 | begin 8 | case(iDIG) 9 | 4'h1: oSEG = 7'b1111001; // ---t---- 10 | 4'h2: oSEG = 7'b0100100; // | | 11 | 4'h3: oSEG = 7'b0110000; // lt rt 12 | 4'h4: oSEG = 7'b0011001; // | | 13 | 4'h5: oSEG = 7'b0010010; // ---m---- 14 | 4'h6: oSEG = 7'b0000010; // | | 15 | 4'h7: oSEG = 7'b1111000; // lb rb 16 | 4'h8: oSEG = 7'b0000000; // | | 17 | 4'h9: oSEG = 7'b0011000; // ---b---- 18 | 4'ha: oSEG = 7'b0001000; 19 | 4'hb: oSEG = 7'b0000011; 20 | 4'hc: oSEG = 7'b1000110; 21 | 4'hd: oSEG = 7'b0100001; 22 | 4'he: oSEG = 7'b0000110; 23 | 4'hf: oSEG = 7'b0001110; 24 | 4'h0: oSEG = 7'b1000000; 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/SEG7_LUT_8.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG ); 2 | input [31:0] iDIG; 3 | output [6:0] oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7; 4 | 5 | SEG7_LUT u0 ( oSEG0,iDIG[3:0] ); 6 | SEG7_LUT u1 ( oSEG1,iDIG[7:4] ); 7 | SEG7_LUT u2 ( oSEG2,iDIG[11:8] ); 8 | SEG7_LUT u3 ( oSEG3,iDIG[15:12] ); 9 | SEG7_LUT u4 ( oSEG4,iDIG[19:16] ); 10 | SEG7_LUT u5 ( oSEG5,iDIG[23:20] ); 11 | SEG7_LUT u6 ( oSEG6,iDIG[27:24] ); 12 | SEG7_LUT u7 ( oSEG7,iDIG[31:28] ); 13 | 14 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_PIP/Sdram_Control_4Port/Sdram_FIFO.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: Sdram_FIFO.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // ============================================================ 11 | // ************************************************************ 12 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 13 | // 14 | // 5.1 Build 176 10/26/2005 SJ Full Version 15 | // ************************************************************ 16 | 17 | 18 | //Copyright (C) 1991-2005 Altera Corporation 19 | //Your use of Altera Corporation's design tools, logic functions 20 | //and other software and tools, and its AMPP partner logic 21 | //functions, and any output files any of the foregoing 22 | //(including device programming or simulation files), and any 23 | //associated documentation or information are expressly subject 24 | //to the terms and conditions of the Altera Program License 25 | //Subscription Agreement, Altera MegaCore Function License 26 | //Agreement, or other applicable license agreement, including, 27 | //without limitation, that your use is for the sole purpose of 28 | //programming logic devices manufactured by Altera and sold by 29 | //Altera or its authorized distributors. Please refer to the 30 | //applicable agreement for further details. 31 | 32 | 33 | // synopsys translate_off 34 | `timescale 1 ps / 1 ps 35 | // synopsys translate_on 36 | module Sdram_FIFO ( 37 | aclr, 38 | data, 39 | rdclk, 40 | rdreq, 41 | wrclk, 42 | wrreq, 43 | q, 44 | rdempty, 45 | rdusedw, 46 | wrfull, 47 | wrusedw); 48 | 49 | input aclr; 50 | input [15:0] data; 51 | input rdclk; 52 | input rdreq; 53 | input wrclk; 54 | input wrreq; 55 | output [15:0] q; 56 | output rdempty; 57 | output [8:0] rdusedw; 58 | output wrfull; 59 | output [8:0] wrusedw; 60 | 61 | wire sub_wire0; 62 | wire [8:0] sub_wire1; 63 | wire sub_wire2; 64 | wire [15:0] sub_wire3; 65 | wire [8:0] sub_wire4; 66 | wire rdempty = sub_wire0; 67 | wire [8:0] wrusedw = sub_wire1[8:0]; 68 | wire wrfull = sub_wire2; 69 | wire [15:0] q = sub_wire3[15:0]; 70 | wire [8:0] rdusedw = sub_wire4[8:0]; 71 | 72 | dcfifo dcfifo_component ( 73 | .wrclk (wrclk), 74 | .rdreq (rdreq), 75 | .aclr (aclr), 76 | .rdclk (rdclk), 77 | .wrreq (wrreq), 78 | .data (data), 79 | .rdempty (sub_wire0), 80 | .wrusedw (sub_wire1), 81 | .wrfull (sub_wire2), 82 | .q (sub_wire3), 83 | .rdusedw (sub_wire4) 84 | // synopsys translate_off 85 | , 86 | .wrempty (), 87 | .rdfull () 88 | // synopsys translate_on 89 | ); 90 | defparam 91 | dcfifo_component.add_ram_output_register = "OFF", 92 | dcfifo_component.clocks_are_synchronized = "FALSE", 93 | dcfifo_component.intended_device_family = "Cyclone", 94 | dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", 95 | dcfifo_component.lpm_numwords = 512, 96 | dcfifo_component.lpm_showahead = "OFF", 97 | dcfifo_component.lpm_type = "dcfifo", 98 | dcfifo_component.lpm_width = 16, 99 | dcfifo_component.lpm_widthu = 9, 100 | dcfifo_component.overflow_checking = "ON", 101 | dcfifo_component.underflow_checking = "ON", 102 | dcfifo_component.use_eab = "ON"; 103 | 104 | 105 | endmodule 106 | 107 | // ============================================================ 108 | // CNX file retrieval info 109 | // ============================================================ 110 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 111 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 112 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 113 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 114 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 115 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 116 | // Retrieval info: PRIVATE: Depth NUMERIC "512" 117 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 118 | // Retrieval info: PRIVATE: Full NUMERIC "1" 119 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" 120 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 121 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" 122 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 123 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 124 | // Retrieval info: PRIVATE: Optimize NUMERIC "2" 125 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 126 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 127 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 128 | // Retrieval info: PRIVATE: Width NUMERIC "16" 129 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 130 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 131 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 132 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "1" 133 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 134 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 135 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 136 | // Retrieval info: PRIVATE: wsFull NUMERIC "1" 137 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" 138 | // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" 139 | // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" 140 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" 141 | // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" 142 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" 143 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" 144 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 145 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" 146 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" 147 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 148 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 149 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 150 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr 151 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] 152 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] 153 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk 154 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty 155 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq 156 | // Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0] 157 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk 158 | // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull 159 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq 160 | // Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0] 161 | // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 162 | // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 163 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 164 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 165 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 166 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 167 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 168 | // Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0 169 | // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 170 | // Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 171 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 172 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE 179 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE 180 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE 181 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/Sdram_Control_4Port/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/Sdram_Control_4Port/control_interface.v: -------------------------------------------------------------------------------- 1 | module control_interface( 2 | CLK, 3 | RESET_N, 4 | CMD, 5 | ADDR, 6 | REF_ACK, 7 | INIT_ACK, 8 | CM_ACK, 9 | NOP, 10 | READA, 11 | WRITEA, 12 | REFRESH, 13 | PRECHARGE, 14 | LOAD_MODE, 15 | SADDR, 16 | REF_REQ, 17 | INIT_REQ, 18 | CMD_ACK 19 | ); 20 | 21 | `include "Sdram_Params.h" 22 | 23 | input CLK; // System Clock 24 | input RESET_N; // System Reset 25 | input [2:0] CMD; // Command input 26 | input [`ASIZE-1:0] ADDR; // Address 27 | input REF_ACK; // Refresh request acknowledge 28 | input INIT_ACK; // Initial request acknowledge 29 | input CM_ACK; // Command acknowledge 30 | output NOP; // Decoded NOP command 31 | output READA; // Decoded READA command 32 | output WRITEA; // Decoded WRITEA command 33 | output REFRESH; // Decoded REFRESH command 34 | output PRECHARGE; // Decoded PRECHARGE command 35 | output LOAD_MODE; // Decoded LOAD_MODE command 36 | output [`ASIZE-1:0] SADDR; // Registered version of ADDR 37 | output REF_REQ; // Hidden refresh request 38 | output INIT_REQ; // Hidden initial request 39 | output CMD_ACK; // Command acknowledge 40 | 41 | 42 | 43 | reg NOP; 44 | reg READA; 45 | reg WRITEA; 46 | reg REFRESH; 47 | reg PRECHARGE; 48 | reg LOAD_MODE; 49 | reg [`ASIZE-1:0] SADDR; 50 | reg REF_REQ; 51 | reg INIT_REQ; 52 | reg CMD_ACK; 53 | 54 | // Internal signals 55 | reg [15:0] timer; 56 | reg [15:0] init_timer; 57 | 58 | 59 | 60 | // Command decode and ADDR register 61 | always @(posedge CLK or negedge RESET_N) 62 | begin 63 | if (RESET_N == 0) 64 | begin 65 | NOP <= 0; 66 | READA <= 0; 67 | WRITEA <= 0; 68 | SADDR <= 0; 69 | end 70 | 71 | else 72 | begin 73 | 74 | SADDR <= ADDR; // register the address to keep proper 75 | // alignment with the command 76 | 77 | if (CMD == 3'b000) // NOP command 78 | NOP <= 1; 79 | else 80 | NOP <= 0; 81 | 82 | if (CMD == 3'b001) // READA command 83 | READA <= 1; 84 | else 85 | READA <= 0; 86 | 87 | if (CMD == 3'b010) // WRITEA command 88 | WRITEA <= 1; 89 | else 90 | WRITEA <= 0; 91 | 92 | end 93 | end 94 | 95 | 96 | // Generate CMD_ACK 97 | always @(posedge CLK or negedge RESET_N) 98 | begin 99 | if (RESET_N == 0) 100 | CMD_ACK <= 0; 101 | else 102 | if ((CM_ACK == 1) & (CMD_ACK == 0)) 103 | CMD_ACK <= 1; 104 | else 105 | CMD_ACK <= 0; 106 | end 107 | 108 | 109 | // refresh timer 110 | always @(posedge CLK or negedge RESET_N) begin 111 | if (RESET_N == 0) 112 | begin 113 | timer <= 0; 114 | REF_REQ <= 0; 115 | end 116 | else 117 | begin 118 | if (REF_ACK == 1) 119 | begin 120 | timer <= REF_PER; 121 | REF_REQ <=0; 122 | end 123 | else if (INIT_REQ == 1) 124 | begin 125 | timer <= REF_PER+200; 126 | REF_REQ <=0; 127 | end 128 | else 129 | timer <= timer - 1'b1; 130 | 131 | if (timer==0) 132 | REF_REQ <= 1; 133 | 134 | end 135 | end 136 | 137 | // initial timer 138 | always @(posedge CLK or negedge RESET_N) begin 139 | if (RESET_N == 0) 140 | begin 141 | init_timer <= 0; 142 | REFRESH <= 0; 143 | PRECHARGE <= 0; 144 | LOAD_MODE <= 0; 145 | INIT_REQ <= 0; 146 | end 147 | else 148 | begin 149 | if (init_timer < (INIT_PER+201)) 150 | init_timer <= init_timer+1; 151 | 152 | if (init_timer < INIT_PER) 153 | begin 154 | REFRESH <=0; 155 | PRECHARGE <=0; 156 | LOAD_MODE <=0; 157 | INIT_REQ <=1; 158 | end 159 | else if(init_timer == (INIT_PER+20)) 160 | begin 161 | REFRESH <=0; 162 | PRECHARGE <=1; 163 | LOAD_MODE <=0; 164 | INIT_REQ <=0; 165 | end 166 | else if( (init_timer == (INIT_PER+40)) || 167 | (init_timer == (INIT_PER+60)) || 168 | (init_timer == (INIT_PER+80)) || 169 | (init_timer == (INIT_PER+100)) || 170 | (init_timer == (INIT_PER+120)) || 171 | (init_timer == (INIT_PER+140)) || 172 | (init_timer == (INIT_PER+160)) || 173 | (init_timer == (INIT_PER+180)) ) 174 | begin 175 | REFRESH <=1; 176 | PRECHARGE <=0; 177 | LOAD_MODE <=0; 178 | INIT_REQ <=0; 179 | end 180 | else if(init_timer == (INIT_PER+200)) 181 | begin 182 | REFRESH <=0; 183 | PRECHARGE <=0; 184 | LOAD_MODE <=1; 185 | INIT_REQ <=0; 186 | end 187 | else 188 | begin 189 | REFRESH <=0; 190 | PRECHARGE <=0; 191 | LOAD_MODE <=0; 192 | INIT_REQ <=0; 193 | end 194 | end 195 | end 196 | 197 | endmodule 198 | 199 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/Sdram_Control_4Port/sdr_data_path.v: -------------------------------------------------------------------------------- 1 | module sdr_data_path( 2 | CLK, 3 | RESET_N, 4 | DATAIN, 5 | DM, 6 | DQOUT, 7 | DQM 8 | ); 9 | 10 | `include "Sdram_Params.h" 11 | 12 | input CLK; // System Clock 13 | input RESET_N; // System Reset 14 | input [`DSIZE-1:0] DATAIN; // Data input from the host 15 | input [`DSIZE/8-1:0] DM; // byte data masks 16 | output [`DSIZE-1:0] DQOUT; 17 | output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs 18 | reg [`DSIZE/8-1:0] DQM; 19 | 20 | 21 | 22 | // Allign the input and output data to the SDRAM control path 23 | always @(posedge CLK or negedge RESET_N) 24 | begin 25 | if (RESET_N == 0) 26 | DQM <= `DSIZE/8-1'hF; 27 | else 28 | DQM <= DM; 29 | end 30 | 31 | assign DQOUT = DATAIN; 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_PIP/VGA_Controller.v: -------------------------------------------------------------------------------- 1 | module VGA_Controller( // Host Side 2 | iRed, 3 | iGreen, 4 | iBlue, 5 | oRequest, 6 | oCoord_X, 7 | oCoord_Y, 8 | // VGA Side 9 | oVGA_R, 10 | oVGA_G, 11 | oVGA_B, 12 | oVGA_H_SYNC, 13 | oVGA_V_SYNC, 14 | oVGA_SYNC, 15 | oVGA_BLANK, 16 | oVGA_CLOCK, 17 | // Control Signal 18 | iCLK, 19 | iRST_N ); 20 | 21 | `include "VGA_Param.h" 22 | 23 | // Host Side 24 | input [9:0] iRed; 25 | input [9:0] iGreen; 26 | input [9:0] iBlue; 27 | output reg [9:0] oCoord_X; 28 | output reg [9:0] oCoord_Y; 29 | output reg oRequest; 30 | // VGA Side 31 | output [9:0] oVGA_R; 32 | output [9:0] oVGA_G; 33 | output [9:0] oVGA_B; 34 | output reg oVGA_H_SYNC; 35 | output reg oVGA_V_SYNC; 36 | output oVGA_SYNC; 37 | output oVGA_BLANK; 38 | output oVGA_CLOCK; 39 | // Control Signal 40 | input iCLK; 41 | input iRST_N; 42 | 43 | // Internal Registers and Wires 44 | reg [9:0] H_Cont; 45 | reg [9:0] V_Cont; 46 | reg [9:0] Cur_Color_R; 47 | reg [9:0] Cur_Color_G; 48 | reg [9:0] Cur_Color_B; 49 | wire mCursor_EN; 50 | wire mRed_EN; 51 | wire mGreen_EN; 52 | wire mBlue_EN; 53 | 54 | assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC; 55 | assign oVGA_SYNC = 1'b0; 56 | assign oVGA_CLOCK = iCLK; 57 | 58 | assign oVGA_R = ( H_Cont>=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START-2 && H_Cont=Y_START && V_Cont= 4) & (SD_COUNTER <=30))? ~CLOCK :0 ); 78 | wire I2C_SDAT=SDO?1'bz:0 ; 79 | 80 | reg ACK1,ACK2,ACK3; 81 | wire ACK=ACK1 | ACK2 |ACK3; 82 | 83 | //--I2C COUNTER 84 | always @(negedge RESET or posedge CLOCK ) begin 85 | if (!RESET) SD_COUNTER=6'b111111; 86 | else begin 87 | if (GO==0) 88 | SD_COUNTER=0; 89 | else 90 | if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+1; 91 | end 92 | end 93 | //---- 94 | 95 | always @(negedge RESET or posedge CLOCK ) begin 96 | if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end 97 | else 98 | case (SD_COUNTER) 99 | 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end 100 | //start 101 | 6'd1 : begin SD=I2C_DATA;SDO=0;end 102 | 6'd2 : SCLK=0; 103 | //SLAVE ADDR 104 | 6'd3 : SDO=SD[23]; 105 | 6'd4 : SDO=SD[22]; 106 | 6'd5 : SDO=SD[21]; 107 | 6'd6 : SDO=SD[20]; 108 | 6'd7 : SDO=SD[19]; 109 | 6'd8 : SDO=SD[18]; 110 | 6'd9 : SDO=SD[17]; 111 | 6'd10 : SDO=SD[16]; 112 | 6'd11 : SDO=1'b1;//ACK 113 | 114 | //SUB ADDR 115 | 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end 116 | 6'd13 : SDO=SD[14]; 117 | 6'd14 : SDO=SD[13]; 118 | 6'd15 : SDO=SD[12]; 119 | 6'd16 : SDO=SD[11]; 120 | 6'd17 : SDO=SD[10]; 121 | 6'd18 : SDO=SD[9]; 122 | 6'd19 : SDO=SD[8]; 123 | 6'd20 : SDO=1'b1;//ACK 124 | 125 | //DATA 126 | 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end 127 | 6'd22 : SDO=SD[6]; 128 | 6'd23 : SDO=SD[5]; 129 | 6'd24 : SDO=SD[4]; 130 | 6'd25 : SDO=SD[3]; 131 | 6'd26 : SDO=SD[2]; 132 | 6'd27 : SDO=SD[1]; 133 | 6'd28 : SDO=SD[0]; 134 | 6'd29 : SDO=1'b1;//ACK 135 | 136 | 137 | //stop 138 | 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end 139 | 6'd31 : SCLK=1'b1; 140 | 6'd32 : begin SDO=1'b1; END=1; end 141 | 142 | endcase 143 | end 144 | 145 | 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /DE2_CCD_edge/RAW2RGB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 17:04:36 05/29/2007 7 | // Design Name: 8 | // Module Name: RAW2RGB 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module RAW2RGB( 22 | aclr, 23 | data_valid, 24 | clk, 25 | //clken, 26 | data, 27 | data_valid_out, 28 | r_out, 29 | g_out, 30 | b_out 31 | ); 32 | 33 | input aclr; 34 | input data_valid; 35 | input clk; 36 | //input clken; 37 | 38 | input [9:0] data; 39 | 40 | output data_valid_out; 41 | output [9:0] r_out; 42 | output [9:0] g_out; 43 | output [9:0] b_out; 44 | 45 | 46 | wire data_end; 47 | wire [9:0] rama; 48 | wire [10:0] rama_rdadd; 49 | wire rama_rden; 50 | wire [10:0] rama_wradd; 51 | wire rama_wren; 52 | wire [9:0] ramb; 53 | wire [10:0] ramb_rdadd; 54 | wire ramb_rden; 55 | wire [10:0] ramb_wradd; 56 | wire ramb_wren; 57 | 58 | wire row_end; 59 | wire sel_row1; 60 | wire sel_row2; 61 | 62 | wire [9:0] row1_1, row1_2; 63 | wire [9:0] row2_1, row2_2; 64 | 65 | reg data_valid_dly1,data_valid_dly2,data_valid_dly3,data_valid_dly4,data_valid_out; 66 | reg [9:0] r,b; 67 | reg [10:0] g; 68 | 69 | control b2v_inst(.clk(clk), 70 | .aclr(aclr), 71 | .data_valid(data_valid), 72 | .rama_wren(rama_wren), 73 | .ramb_wren(ramb_wren), 74 | .rama_rden(rama_rden), 75 | .ramb_rden(ramb_rden), 76 | .row_end(row_end), 77 | .rama_rdadd(rama_rdadd), 78 | .rama_wradd(rama_wradd), 79 | .ramb_rdadd(ramb_rdadd), 80 | .ramb_wradd(ramb_wradd), 81 | .sel_row1(sel_row1), 82 | .sel_row2(sel_row2)); 83 | 84 | buffer b2v_inst2(.clk(clk), 85 | .rama_wren(rama_wren), 86 | .rama_rden(rama_rden), 87 | .ramb_wren(ramb_wren), 88 | .ramb_rden(ramb_rden), 89 | .datain(data), 90 | .rama_rdadd(rama_rdadd), 91 | .rama_wradd(rama_wradd), 92 | .ramb_rdadd(ramb_rdadd), 93 | .ramb_wradd(ramb_wradd), 94 | .rama(rama), 95 | .ramb(ramb)); 96 | 97 | mux_ram_row b2v_inst1(.clk(clk), 98 | .aclr(aclr), 99 | .row_end(row_end), 100 | .rama(rama), 101 | .ramb(ramb), 102 | .sel_row1(sel_row1), 103 | .sel_row2(sel_row2), 104 | .row1_1(row1_1), 105 | .row1_2(row1_2), 106 | .row2_1(row2_1), 107 | .row2_2(row2_2)); 108 | 109 | always@(posedge clk or negedge aclr) 110 | begin 111 | if(!aclr) 112 | begin 113 | 114 | data_valid_dly1<=0; 115 | data_valid_dly2<=0; 116 | data_valid_dly3<=0; 117 | end 118 | else 119 | begin 120 | data_valid_dly1<=rama_rden; 121 | data_valid_dly2<=data_valid_dly1; 122 | data_valid_dly3<=data_valid_dly2; 123 | end 124 | end 125 | always@(posedge clk or negedge aclr) 126 | begin 127 | if(!aclr) 128 | data_valid_dly4<=0; 129 | else if(data_valid_dly2) 130 | data_valid_dly4<=!data_valid_dly4; 131 | end 132 | always@(posedge clk or negedge aclr) 133 | begin 134 | if(!aclr) 135 | begin 136 | r<=0; 137 | g<=0; 138 | b<=0; 139 | data_valid_out<=0; 140 | end 141 | else 142 | begin 143 | r<=row1_2; 144 | g<=row1_1+row2_2; 145 | b<=row2_1; 146 | //r<=row2_2; 147 | //g<=row1_2+row2_1; 148 | //b<=row1_1; 149 | data_valid_out<=data_valid_dly4; 150 | end 151 | end 152 | assign r_out=r; 153 | assign g_out=g[10:1]; 154 | assign b_out=b; 155 | endmodule 156 | -------------------------------------------------------------------------------- /DE2_CCD_edge/RGB2YUV_TOP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:42:31 05/31/2007 7 | // Design Name: 8 | // Module Name: RGB2YUV 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `timescale 1ns / 10ps 22 | 23 | module RGB2YUV_TOP 24 | ( 25 | Clock, 26 | Reset, 27 | Red, 28 | Green, 29 | Blue, 30 | data_valid_in, 31 | Y, 32 | Cb, 33 | Cr, 34 | data_valid_out 35 | ); 36 | 37 | //parameter TOP_OUT_SIZE = 8; // uncomment to get 8-bit input & output... 38 | parameter TOP_OUT_SIZE = 10; // uncomment to get 10-bit input & output... 39 | 40 | input Clock; 41 | //input ClockEnable; 42 | input Reset; 43 | input [(TOP_OUT_SIZE - 1):0] Red; 44 | input [(TOP_OUT_SIZE - 1):0] Green; 45 | input [(TOP_OUT_SIZE - 1):0] Blue; 46 | input data_valid_in; 47 | output [(TOP_OUT_SIZE - 1):0] Y; 48 | output [(TOP_OUT_SIZE - 1):0] Cb; 49 | output [(TOP_OUT_SIZE - 1):0] Cr; 50 | output data_valid_out; 51 | 52 | reg [(TOP_OUT_SIZE - 1):0] Y; 53 | reg [(TOP_OUT_SIZE - 1):0] Cb; 54 | reg [(TOP_OUT_SIZE - 1):0] Cr; 55 | reg data_valid_out; 56 | reg data_valid_dly1,data_valid_dly2,data_valid_dly3,data_valid_dly4; 57 | // Define internal signals 58 | reg [(TOP_OUT_SIZE - 1):0] R; 59 | reg [(TOP_OUT_SIZE - 1):0] G; 60 | reg [(TOP_OUT_SIZE - 1):0] B; 61 | 62 | wire [(TOP_OUT_SIZE - 1):0] Y_sig; 63 | wire [(TOP_OUT_SIZE - 1):0] Cb_sig; 64 | wire [(TOP_OUT_SIZE - 1):0] Cr_sig; 65 | 66 | // Input registers (should be pushed into IOBs) 67 | always @(posedge Clock or negedge Reset) 68 | begin : In_Reg 69 | if (!Reset) 70 | begin 71 | R <= 0; 72 | G <= 0; 73 | B <= 0; 74 | end 75 | else if (data_valid_in) 76 | begin 77 | R <= Red ; 78 | G <= Green ; 79 | B <= Blue ; 80 | end 81 | end 82 | 83 | // Output registers (should be pushed into IOBs) 84 | always @(posedge Clock or negedge Reset) 85 | begin : Out_Reg 86 | if (!Reset) 87 | begin 88 | Y <= 0; 89 | Cb <= 0; 90 | Cr <= 0; 91 | end 92 | else 93 | begin 94 | Y <= Y_sig ; 95 | Cb <= Cb_sig ; 96 | Cr <= Cr_sig ; 97 | end 98 | end 99 | 100 | 101 | // CSC instantiation 102 | RGB2YUV #(TOP_OUT_SIZE) RGB2YUV 103 | ( 104 | .Clock(Clock), 105 | //.ClockEnable(ClockEnable), 106 | .Reset(Reset), 107 | .R(R), 108 | .G(G), 109 | .B(B), 110 | .Y(Y_sig), 111 | .Cb(Cb_sig), 112 | .Cr(Cr_sig) 113 | ); 114 | 115 | always@(posedge Clock or negedge Reset) 116 | if(!Reset) 117 | begin 118 | data_valid_dly1<=0; 119 | data_valid_dly2<=0; 120 | data_valid_dly3<=0; 121 | data_valid_dly4<=0; 122 | data_valid_out<=0; 123 | end 124 | else 125 | begin 126 | data_valid_dly1<=data_valid_in; 127 | data_valid_dly2<=data_valid_dly1; 128 | data_valid_dly3<=data_valid_dly2; 129 | data_valid_dly4<=data_valid_dly3; 130 | data_valid_out<=data_valid_dly4; 131 | end 132 | endmodule 133 | -------------------------------------------------------------------------------- /DE2_CCD_edge/Reset_Delay.v: -------------------------------------------------------------------------------- 1 | module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2); 2 | input iCLK; 3 | input iRST; 4 | output reg oRST_0; 5 | output reg oRST_1; 6 | output reg oRST_2; 7 | 8 | reg [21:0] Cont; 9 | 10 | always@(posedge iCLK or negedge iRST) 11 | begin 12 | if(!iRST) 13 | begin 14 | Cont <= 0; 15 | oRST_0 <= 0; 16 | oRST_1 <= 0; 17 | oRST_2 <= 0; 18 | end 19 | else 20 | begin 21 | if(Cont!=22'h3FFFFF) 22 | Cont <= Cont+1; 23 | if(Cont>=22'h1FFFFF) 24 | oRST_0 <= 1; 25 | if(Cont>=22'h2FFFFF) 26 | oRST_1 <= 1; 27 | if(Cont>=22'h3FFFFF) 28 | oRST_2 <= 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_edge/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT ( oSEG,iDIG ); 2 | input [3:0] iDIG; 3 | output [6:0] oSEG; 4 | reg [6:0] oSEG; 5 | 6 | always @(iDIG) 7 | begin 8 | case(iDIG) 9 | 4'h1: oSEG = 7'b1111001; // ---t---- 10 | 4'h2: oSEG = 7'b0100100; // | | 11 | 4'h3: oSEG = 7'b0110000; // lt rt 12 | 4'h4: oSEG = 7'b0011001; // | | 13 | 4'h5: oSEG = 7'b0010010; // ---m---- 14 | 4'h6: oSEG = 7'b0000010; // | | 15 | 4'h7: oSEG = 7'b1111000; // lb rb 16 | 4'h8: oSEG = 7'b0000000; // | | 17 | 4'h9: oSEG = 7'b0011000; // ---b---- 18 | 4'ha: oSEG = 7'b0001000; 19 | 4'hb: oSEG = 7'b0000011; 20 | 4'hc: oSEG = 7'b1000110; 21 | 4'hd: oSEG = 7'b0100001; 22 | 4'he: oSEG = 7'b0000110; 23 | 4'hf: oSEG = 7'b0001110; 24 | 4'h0: oSEG = 7'b1000000; 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /DE2_CCD_edge/SEG7_LUT_8.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG ); 2 | input [31:0] iDIG; 3 | output [6:0] oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7; 4 | 5 | SEG7_LUT u0 ( oSEG0,iDIG[3:0] ); 6 | SEG7_LUT u1 ( oSEG1,iDIG[7:4] ); 7 | SEG7_LUT u2 ( oSEG2,iDIG[11:8] ); 8 | SEG7_LUT u3 ( oSEG3,iDIG[15:12] ); 9 | SEG7_LUT u4 ( oSEG4,iDIG[19:16] ); 10 | SEG7_LUT u5 ( oSEG5,iDIG[23:20] ); 11 | SEG7_LUT u6 ( oSEG6,iDIG[27:24] ); 12 | SEG7_LUT u7 ( oSEG7,iDIG[31:28] ); 13 | 14 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_edge/Sdram_Control_4Port/.command.v.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/Sdram_Control_4Port/.command.v.swp -------------------------------------------------------------------------------- /DE2_CCD_edge/Sdram_Control_4Port/42S16400B.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/Sdram_Control_4Port/42S16400B.pdf -------------------------------------------------------------------------------- /DE2_CCD_edge/Sdram_Control_4Port/Sdram_FIFO.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: Sdram_FIFO.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // ============================================================ 11 | // ************************************************************ 12 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 13 | // 14 | // 5.1 Build 176 10/26/2005 SJ Full Version 15 | // ************************************************************ 16 | 17 | 18 | //Copyright (C) 1991-2005 Altera Corporation 19 | //Your use of Altera Corporation's design tools, logic functions 20 | //and other software and tools, and its AMPP partner logic 21 | //functions, and any output files any of the foregoing 22 | //(including device programming or simulation files), and any 23 | //associated documentation or information are expressly subject 24 | //to the terms and conditions of the Altera Program License 25 | //Subscription Agreement, Altera MegaCore Function License 26 | //Agreement, or other applicable license agreement, including, 27 | //without limitation, that your use is for the sole purpose of 28 | //programming logic devices manufactured by Altera and sold by 29 | //Altera or its authorized distributors. Please refer to the 30 | //applicable agreement for further details. 31 | 32 | 33 | // synopsys translate_off 34 | `timescale 1 ps / 1 ps 35 | // synopsys translate_on 36 | module Sdram_FIFO ( 37 | aclr, 38 | data, 39 | rdclk, 40 | rdreq, 41 | wrclk, 42 | wrreq, 43 | q, 44 | rdempty, 45 | rdusedw, 46 | wrfull, 47 | wrusedw); 48 | 49 | input aclr; 50 | input [15:0] data; 51 | input rdclk; 52 | input rdreq; 53 | input wrclk; 54 | input wrreq; 55 | output [15:0] q; 56 | output rdempty; 57 | output [8:0] rdusedw; 58 | output wrfull; 59 | output [8:0] wrusedw; 60 | 61 | wire sub_wire0; 62 | wire [8:0] sub_wire1; 63 | wire sub_wire2; 64 | wire [15:0] sub_wire3; 65 | wire [8:0] sub_wire4; 66 | wire rdempty = sub_wire0; 67 | wire [8:0] wrusedw = sub_wire1[8:0]; 68 | wire wrfull = sub_wire2; 69 | wire [15:0] q = sub_wire3[15:0]; 70 | wire [8:0] rdusedw = sub_wire4[8:0]; 71 | 72 | dcfifo dcfifo_component ( 73 | .wrclk (wrclk), 74 | .rdreq (rdreq), 75 | .aclr (aclr), 76 | .rdclk (rdclk), 77 | .wrreq (wrreq), 78 | .data (data), 79 | .rdempty (sub_wire0), 80 | .wrusedw (sub_wire1), 81 | .wrfull (sub_wire2), 82 | .q (sub_wire3), 83 | .rdusedw (sub_wire4) 84 | // synopsys translate_off 85 | , 86 | .wrempty (), 87 | .rdfull () 88 | // synopsys translate_on 89 | ); 90 | defparam 91 | dcfifo_component.add_ram_output_register = "OFF", 92 | dcfifo_component.clocks_are_synchronized = "FALSE", 93 | dcfifo_component.intended_device_family = "Cyclone", 94 | dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", 95 | dcfifo_component.lpm_numwords = 512, 96 | dcfifo_component.lpm_showahead = "OFF", 97 | dcfifo_component.lpm_type = "dcfifo", 98 | dcfifo_component.lpm_width = 16, 99 | dcfifo_component.lpm_widthu = 9, 100 | dcfifo_component.overflow_checking = "ON", 101 | dcfifo_component.underflow_checking = "ON", 102 | dcfifo_component.use_eab = "ON"; 103 | 104 | 105 | endmodule 106 | 107 | // ============================================================ 108 | // CNX file retrieval info 109 | // ============================================================ 110 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 111 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 112 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 113 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 114 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 115 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 116 | // Retrieval info: PRIVATE: Depth NUMERIC "512" 117 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 118 | // Retrieval info: PRIVATE: Full NUMERIC "1" 119 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" 120 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 121 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" 122 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 123 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 124 | // Retrieval info: PRIVATE: Optimize NUMERIC "2" 125 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 126 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 127 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 128 | // Retrieval info: PRIVATE: Width NUMERIC "16" 129 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 130 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 131 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 132 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "1" 133 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 134 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 135 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 136 | // Retrieval info: PRIVATE: wsFull NUMERIC "1" 137 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" 138 | // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" 139 | // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" 140 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" 141 | // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" 142 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" 143 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" 144 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 145 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" 146 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" 147 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 148 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 149 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 150 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr 151 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] 152 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] 153 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk 154 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty 155 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq 156 | // Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0] 157 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk 158 | // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull 159 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq 160 | // Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0] 161 | // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 162 | // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 163 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 164 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 165 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 166 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 167 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 168 | // Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0 169 | // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 170 | // Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 171 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 172 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE 179 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE 180 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE 181 | -------------------------------------------------------------------------------- /DE2_CCD_edge/Sdram_Control_4Port/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_edge/Sdram_Control_4Port/control_interface.v: -------------------------------------------------------------------------------- 1 | module control_interface( 2 | CLK, 3 | RESET_N, 4 | CMD, 5 | ADDR, 6 | REF_ACK, 7 | INIT_ACK, 8 | CM_ACK, 9 | NOP, 10 | READA, 11 | WRITEA, 12 | REFRESH, 13 | PRECHARGE, 14 | LOAD_MODE, 15 | SADDR, 16 | REF_REQ, 17 | INIT_REQ, 18 | CMD_ACK 19 | ); 20 | 21 | `include "Sdram_Params.h" 22 | 23 | input CLK; // System Clock 24 | input RESET_N; // System Reset 25 | input [2:0] CMD; // Command input 26 | input [`ASIZE-1:0] ADDR; // Address 27 | input REF_ACK; // Refresh request acknowledge 28 | input INIT_ACK; // Initial request acknowledge 29 | input CM_ACK; // Command acknowledge 30 | output NOP; // Decoded NOP command 31 | output READA; // Decoded READA command 32 | output WRITEA; // Decoded WRITEA command 33 | output REFRESH; // Decoded REFRESH command 34 | output PRECHARGE; // Decoded PRECHARGE command 35 | output LOAD_MODE; // Decoded LOAD_MODE command 36 | output [`ASIZE-1:0] SADDR; // Registered version of ADDR 37 | output REF_REQ; // Hidden refresh request 38 | output INIT_REQ; // Hidden initial request 39 | output CMD_ACK; // Command acknowledge 40 | 41 | 42 | 43 | reg NOP; 44 | reg READA; 45 | reg WRITEA; 46 | reg REFRESH; 47 | reg PRECHARGE; 48 | reg LOAD_MODE; 49 | reg [`ASIZE-1:0] SADDR; 50 | reg REF_REQ; 51 | reg INIT_REQ; 52 | reg CMD_ACK; 53 | 54 | // Internal signals 55 | reg [15:0] timer; 56 | reg [15:0] init_timer; 57 | 58 | 59 | 60 | // Command decode and ADDR register 61 | always @(posedge CLK or negedge RESET_N) 62 | begin 63 | if (RESET_N == 0) 64 | begin 65 | NOP <= 0; 66 | READA <= 0; 67 | WRITEA <= 0; 68 | SADDR <= 0; 69 | end 70 | 71 | else 72 | begin 73 | 74 | SADDR <= ADDR; // register the address to keep proper 75 | // alignment with the command 76 | 77 | if (CMD == 3'b000) // NOP command 78 | NOP <= 1; 79 | else 80 | NOP <= 0; 81 | 82 | if (CMD == 3'b001) // READA command 83 | READA <= 1; 84 | else 85 | READA <= 0; 86 | 87 | if (CMD == 3'b010) // WRITEA command 88 | WRITEA <= 1; 89 | else 90 | WRITEA <= 0; 91 | 92 | end 93 | end 94 | 95 | 96 | // Generate CMD_ACK 97 | always @(posedge CLK or negedge RESET_N) 98 | begin 99 | if (RESET_N == 0) 100 | CMD_ACK <= 0; 101 | else 102 | if ((CM_ACK == 1) & (CMD_ACK == 0)) 103 | CMD_ACK <= 1; 104 | else 105 | CMD_ACK <= 0; 106 | end 107 | 108 | 109 | // refresh timer 110 | always @(posedge CLK or negedge RESET_N) begin 111 | if (RESET_N == 0) 112 | begin 113 | timer <= 0; 114 | REF_REQ <= 0; 115 | end 116 | else 117 | begin 118 | if (REF_ACK == 1) 119 | begin 120 | timer <= REF_PER; 121 | REF_REQ <=0; 122 | end 123 | else if (INIT_REQ == 1) 124 | begin 125 | timer <= REF_PER+200; 126 | REF_REQ <=0; 127 | end 128 | else 129 | timer <= timer - 1'b1; 130 | 131 | if (timer==0) 132 | REF_REQ <= 1; 133 | 134 | end 135 | end 136 | 137 | // initial timer 138 | always @(posedge CLK or negedge RESET_N) begin 139 | if (RESET_N == 0) 140 | begin 141 | init_timer <= 0; 142 | REFRESH <= 0; 143 | PRECHARGE <= 0; 144 | LOAD_MODE <= 0; 145 | INIT_REQ <= 0; 146 | end 147 | else 148 | begin 149 | if (init_timer < (INIT_PER+201)) 150 | init_timer <= init_timer+1; 151 | 152 | if (init_timer < INIT_PER) 153 | begin 154 | REFRESH <=0; 155 | PRECHARGE <=0; 156 | LOAD_MODE <=0; 157 | INIT_REQ <=1; 158 | end 159 | else if(init_timer == (INIT_PER+20)) 160 | begin 161 | REFRESH <=0; 162 | PRECHARGE <=1; 163 | LOAD_MODE <=0; 164 | INIT_REQ <=0; 165 | end 166 | else if( (init_timer == (INIT_PER+40)) || 167 | (init_timer == (INIT_PER+60)) || 168 | (init_timer == (INIT_PER+80)) || 169 | (init_timer == (INIT_PER+100)) || 170 | (init_timer == (INIT_PER+120)) || 171 | (init_timer == (INIT_PER+140)) || 172 | (init_timer == (INIT_PER+160)) || 173 | (init_timer == (INIT_PER+180)) ) 174 | begin 175 | REFRESH <=1; 176 | PRECHARGE <=0; 177 | LOAD_MODE <=0; 178 | INIT_REQ <=0; 179 | end 180 | else if(init_timer == (INIT_PER+200)) 181 | begin 182 | REFRESH <=0; 183 | PRECHARGE <=0; 184 | LOAD_MODE <=1; 185 | INIT_REQ <=0; 186 | end 187 | else 188 | begin 189 | REFRESH <=0; 190 | PRECHARGE <=0; 191 | LOAD_MODE <=0; 192 | INIT_REQ <=0; 193 | end 194 | end 195 | end 196 | 197 | endmodule 198 | 199 | -------------------------------------------------------------------------------- /DE2_CCD_edge/Sdram_Control_4Port/sdr_data_path.v: -------------------------------------------------------------------------------- 1 | module sdr_data_path( 2 | CLK, 3 | RESET_N, 4 | DATAIN, 5 | DM, 6 | DQOUT, 7 | DQM 8 | ); 9 | 10 | `include "Sdram_Params.h" 11 | 12 | input CLK; // System Clock 13 | input RESET_N; // System Reset 14 | input [`DSIZE-1:0] DATAIN; // Data input from the host 15 | input [`DSIZE/8-1:0] DM; // byte data masks 16 | output [`DSIZE-1:0] DQOUT; 17 | output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs 18 | reg [`DSIZE/8-1:0] DQM; 19 | 20 | 21 | 22 | // Allign the input and output data to the SDRAM control path 23 | always @(posedge CLK or negedge RESET_N) 24 | begin 25 | if (RESET_N == 0) 26 | DQM <= `DSIZE/8-1'hF; 27 | else 28 | DQM <= DM; 29 | end 30 | 31 | assign DQOUT = DATAIN; 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /DE2_CCD_edge/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_edge/VGA_Controller.v: -------------------------------------------------------------------------------- 1 | module VGA_Controller( // Host Side 2 | iRed, 3 | iGreen, 4 | iBlue, 5 | oRequest, 6 | // VGA Side 7 | oVGA_R, 8 | oVGA_G, 9 | oVGA_B, 10 | oVGA_H_SYNC, 11 | oVGA_V_SYNC, 12 | oVGA_SYNC, 13 | oVGA_BLANK, 14 | oVGA_CLOCK, 15 | // Control Signal 16 | iCLK, 17 | iRST_N ); 18 | 19 | `include "VGA_Param.h" 20 | 21 | // Host Side 22 | input [9:0] iRed; 23 | input [9:0] iGreen; 24 | input [9:0] iBlue; 25 | output reg oRequest; 26 | // VGA Side 27 | output [9:0] oVGA_R; 28 | output [9:0] oVGA_G; 29 | output [9:0] oVGA_B; 30 | output reg oVGA_H_SYNC; 31 | output reg oVGA_V_SYNC; 32 | output oVGA_SYNC; 33 | output oVGA_BLANK; 34 | output oVGA_CLOCK; 35 | // Control Signal 36 | input iCLK; 37 | input iRST_N; 38 | 39 | // Internal Registers and Wires 40 | reg [9:0] H_Cont; 41 | reg [9:0] V_Cont; 42 | reg [9:0] Cur_Color_R; 43 | reg [9:0] Cur_Color_G; 44 | reg [9:0] Cur_Color_B; 45 | wire mCursor_EN; 46 | wire mRed_EN; 47 | wire mGreen_EN; 48 | wire mBlue_EN; 49 | 50 | assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC; 51 | assign oVGA_SYNC = 1'b0; 52 | assign oVGA_CLOCK = iCLK; 53 | 54 | assign oVGA_R = ( H_Cont>=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START-2 && H_Cont=Y_START && V_Cont4095 equals 4095 */ 112 | assign R = (R_int[22]) ? 0 : (R_int[21:20] == 2'b0) ? R_int[19:10] : 10'b1111111111; 113 | assign G = (G_int[22]) ? 0 : (G_int[21:20] == 2'b0) ? G_int[19:10] : 10'b1111111111; 114 | assign B = (B_int[22]) ? 0 : (B_int[21:20] == 2'b0) ? B_int[19:10] : 10'b1111111111; 115 | 116 | always@(posedge clk or negedge rst) 117 | if(!rst) 118 | begin 119 | data_valid_dly1<=0; 120 | data_valid_dly2<=0; 121 | data_valid_out<=0; 122 | end 123 | else 124 | begin 125 | data_valid_dly1<=data_valid_in; 126 | data_valid_dly2<=data_valid_dly1; 127 | data_valid_out<=data_valid_dly2; 128 | //data_valid_out<=data_valid_dly1; 129 | end 130 | endmodule 131 | 132 | -------------------------------------------------------------------------------- /DE2_CCD_edge/buffer.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2002 Altera Corporation 2 | // Any megafunction design, and related netlist (encrypted or decrypted), 3 | // support information, device programming or simulation file, and any other 4 | // associated documentation or information provided by Altera or a partner 5 | // under Altera's Megafunction Partnership Program may be used only 6 | // to program PLD devices (but not masked PLD devices) from Altera. Any 7 | // other use of such megafunction design, netlist, support information, 8 | // device programming or simulation file, or any other related documentation 9 | // or information is prohibited for any other purpose, including, but not 10 | // limited to modification, reverse engineering, de-compiling, or use with 11 | // any other silicon devices, unless such use is explicitly licensed under 12 | // a separate agreement with Altera or a megafunction partner. Title to the 13 | // intellectual property, including patents, copyrights, trademarks, trade 14 | // secrets, or maskworks, embodied in any such megafunction design, netlist, 15 | // support information, device programming or simulation file, or any other 16 | // related documentation or information provided by Altera or a megafunction 17 | // partner, remains with Altera, the megafunction partner, or their respective 18 | // licensors. No other licenses, including any licenses needed under any third 19 | // party's intellectual property, are provided herein. 20 | 21 | module buffer( 22 | clk, 23 | rama_wren, 24 | rama_rden, 25 | ramb_wren, 26 | ramb_rden, 27 | 28 | datain, 29 | rama_rdadd, 30 | rama_wradd, 31 | ramb_rdadd, 32 | ramb_wradd, 33 | 34 | rama, 35 | ramb 36 | 37 | ); 38 | 39 | input clk; 40 | input rama_wren; 41 | input rama_rden; 42 | input ramb_wren; 43 | input ramb_rden; 44 | 45 | input [9:0] datain; 46 | input [10:0] rama_rdadd; 47 | input [10:0] rama_wradd; 48 | input [10:0] ramb_rdadd; 49 | input [10:0] ramb_wradd; 50 | 51 | output [9:0] rama; 52 | output [9:0] ramb; 53 | 54 | reg [9:0] SYNTHESIZED_WIRE_3; 55 | 56 | 57 | 58 | always@(posedge clk) 59 | begin 60 | 61 | SYNTHESIZED_WIRE_3[9] = datain[9]; 62 | SYNTHESIZED_WIRE_3[8] = datain[8]; 63 | SYNTHESIZED_WIRE_3[7] = datain[7]; 64 | SYNTHESIZED_WIRE_3[6] = datain[6]; 65 | SYNTHESIZED_WIRE_3[5] = datain[5]; 66 | SYNTHESIZED_WIRE_3[4] = datain[4]; 67 | SYNTHESIZED_WIRE_3[3] = datain[3]; 68 | SYNTHESIZED_WIRE_3[2] = datain[2]; 69 | SYNTHESIZED_WIRE_3[1] = datain[1]; 70 | SYNTHESIZED_WIRE_3[0] = datain[0]; 71 | 72 | end 73 | 74 | ram_blk b2v_RAM_A(.wren(rama_wren),.rden(rama_rden),.clock(clk),.data(SYNTHESIZED_WIRE_3),.rdaddress(rama_rdadd),.wraddress(rama_wradd),.q(rama)); 75 | 76 | ram_blk b2v_RAM_B(.wren(ramb_wren),.rden(ramb_rden),.clock(clk),.data(SYNTHESIZED_WIRE_3),.rdaddress(ramb_rdadd),.wraddress(ramb_wradd),.q(ramb)); 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /DE2_CCD_edge/const_mult.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------------------------------- 2 | // ?2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, 3 | // patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All 4 | // other trademarks and registered trademarks are the property of their respective owners. 5 | // All specifications are subject to change without notice. 6 | // -------------------------------------------------------------------------------------------- 7 | // NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." 8 | // By providing the design, code, or information as one possible implementation of this 9 | // feature, application, or standard, Xilinx makes no representation that this implementation 10 | // is free from any claims of infringement. You are responsible for obtaining any rights 11 | // you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever 12 | // with respect to the adequacy of the implementation, including but not limited to any 13 | // warranties or representations that this implementation is free from claims of infringement 14 | // and any implied warranties of merchantability or fitness for a particular purpose. 15 | // -------------------------------------------------------------------------------------------- 16 | // 17 | // 18 | // Constant Mutliplier for RGB to YCbCr Conversion 19 | // 20 | // Benoit Payette, Xilinx AE, Montreal 21 | // July 09, 2002 22 | // 23 | // SynplifyPRO v7.1 for synthesis 24 | // MTI v5.6 for simulation 25 | // 26 | // This file is the Verilog const_mult 27 | // 28 | // Description: This is a parameterizable constant multiplier 29 | // 30 | // 31 | 32 | `timescale 1ns / 10ps 33 | 34 | module const_mult 35 | ( 36 | Clock, 37 | //ClockEnable, 38 | Reset, 39 | Color, 40 | Color_Out 41 | ); 42 | 43 | parameter IN_SIZE = 8; 44 | parameter OUT_SIZE = 16; // output size width (integer) 45 | parameter CST_MULT = 66; // constant multiplicand (integer) 46 | 47 | input Clock; 48 | //input ClockEnable; 49 | input Reset; 50 | input [ (IN_SIZE - 1):0] Color; 51 | output[(OUT_SIZE - 1):0] Color_Out; 52 | 53 | reg [(OUT_SIZE - 1):0] Color_Out; 54 | 55 | // ------------------------------ 56 | // RTL code for COLOR_KCM process 57 | // ------------------------------ 58 | always @(posedge Clock or negedge Reset) 59 | begin : COLOR_KCM 60 | if (!Reset) 61 | Color_Out <= 0; 62 | else 63 | Color_Out <= CST_MULT * Color; 64 | end 65 | 66 | 67 | endmodule 68 | -------------------------------------------------------------------------------- /DE2_CCD_edge/control.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2002 Altera Corporation 2 | // Any megafunction design, and related netlist (encrypted or decrypted), 3 | // support information, device programming or simulation file, and any other 4 | // associated documentation or information provided by Altera or a partner 5 | // under Altera's Megafunction Partnership Program may be used only 6 | // to program PLD devices (but not masked PLD devices) from Altera. Any 7 | // other use of such megafunction design, netlist, support information, 8 | // device programming or simulation file, or any other related documentation 9 | // or information is prohibited for any other purpose, including, but not 10 | // limited to modification, reverse engineering, de-compiling, or use with 11 | // any other silicon devices, unless such use is explicitly licensed under 12 | // a separate agreement with Altera or a megafunction partner. Title to the 13 | // intellectual property, including patents, copyrights, trademarks, trade 14 | // secrets, or maskworks, embodied in any such megafunction design, netlist, 15 | // support information, device programming or simulation file, or any other 16 | // related documentation or information provided by Altera or a megafunction 17 | // partner, remains with Altera, the megafunction partner, or their respective 18 | // licensors. No other licenses, including any licenses needed under any third 19 | // party's intellectual property, are provided herein. 20 | `timescale 1ns/1ps 21 | module control( 22 | aclr, 23 | data_valid, 24 | clk, 25 | frame_end, 26 | rama_rden, 27 | ramb_rden, 28 | 29 | rama_wren, 30 | ramb_wren, 31 | 32 | row_end, 33 | rama_rdadd, 34 | rama_wradd, 35 | ramb_rdadd, 36 | ramb_wradd, 37 | 38 | sel_row1, 39 | sel_row2 40 | 41 | ); 42 | 43 | input aclr; 44 | input data_valid; 45 | input clk; 46 | output frame_end; 47 | output rama_rden; 48 | output ramb_rden; 49 | 50 | output rama_wren; 51 | output ramb_wren; 52 | 53 | output row_end; 54 | output [10:0] rama_rdadd; 55 | output [10:0] rama_wradd; 56 | output [10:0] ramb_rdadd; 57 | output [10:0] ramb_wradd; 58 | output sel_row1,sel_row2; 59 | 60 | gen_ram_rdadd b2v_gen_ram_rdadd_u1(.clk(clk), 61 | .aclr(aclr), 62 | .rama_rden(rama_rden), 63 | .ramb_rden(ramb_rden), 64 | .rama_rdadd(rama_rdadd), 65 | .ramb_rdadd(ramb_rdadd)); 66 | 67 | gen_ram_rden b2v_gen_ram_rden_u1(.clk(clk), 68 | .aclr(aclr), 69 | .rama_wren(rama_wren), 70 | .ramb_wren(ramb_wren), 71 | .rama_rden(rama_rden), 72 | .ramb_rden(ramb_rden), 73 | .frame_end(frame_end), 74 | .sel_row1_out(sel_row1), 75 | .sel_row2_out(sel_row2), 76 | .row_end(row_end)); 77 | 78 | gen_ram_wradd b2v_gen_ram_wradd_u1(.clk(clk), 79 | .aclr(aclr), 80 | .rama_wren(rama_wren), 81 | .ramb_wren(ramb_wren), 82 | .rama_wradd(rama_wradd), 83 | .ramb_wradd(ramb_wradd)); 84 | 85 | gen_ram_wren b2v_gen_ram_wren_u1(.clk(clk), 86 | .aclr(aclr), 87 | .data_valid(data_valid), 88 | .rama_wren(rama_wren), 89 | .ramb_wren(ramb_wren)); 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /DE2_CCD_edge/filter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/filter.v -------------------------------------------------------------------------------- /DE2_CCD_edge/gen_ram_rdadd.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/gen_ram_rdadd.v -------------------------------------------------------------------------------- /DE2_CCD_edge/gen_ram_rden.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/gen_ram_rden.v -------------------------------------------------------------------------------- /DE2_CCD_edge/gen_ram_rden_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 08:15:36 05/29/2007 8 | // Design Name: gen_ram_rden 9 | // Module Name: D:/altera_work/CCD/gen_ram_rden_tb.v 10 | // Project Name: CCD 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: gen_ram_rden 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module gen_ram_rden_tb_v; 26 | 27 | // Inputs 28 | reg clk; 29 | reg aclr; 30 | reg rama_wren; 31 | reg ramb_wren; 32 | 33 | // Outputs 34 | wire [1:0] sel_row1_out; 35 | wire [1:0] sel_row2_out; 36 | wire frame_end; 37 | wire rama_rden; 38 | wire ramb_rden; 39 | 40 | // Instantiate the Unit Under Test (UUT) 41 | gen_ram_rden uut ( 42 | .clk(clk), 43 | .aclr(aclr), 44 | .rama_wren(rama_wren), 45 | .ramb_wren(ramb_wren), 46 | .sel_row1_out(sel_row1_out), 47 | .sel_row2_out(sel_row2_out), 48 | .frame_end(frame_end), 49 | .rama_rden(rama_rden), 50 | .ramb_rden(ramb_rden) 51 | ); 52 | 53 | initial begin 54 | // Initialize Inputs 55 | clk = 0; 56 | aclr = 1; 57 | rama_wren = 0; 58 | ramb_wren = 0; 59 | 60 | // Wait 100 ns for global reset to finish 61 | #100; 62 | aclr = 0; 63 | // Add stimulus here 64 | #30 65 | rama_wren = 1; 66 | #240 67 | rama_wren = 0; 68 | ramb_wren = 1; 69 | #240 70 | rama_wren = 1; 71 | ramb_wren = 0; 72 | #240 73 | rama_wren = 0; 74 | ramb_wren = 1; 75 | #240 76 | rama_wren = 1; 77 | ramb_wren = 0; 78 | #240 79 | rama_wren = 0; 80 | ramb_wren = 1; 81 | #240 82 | rama_wren = 1; 83 | ramb_wren = 0; 84 | #240 85 | rama_wren = 0; 86 | ramb_wren = 1; 87 | #240 88 | rama_wren = 1; 89 | ramb_wren = 0; 90 | #240 91 | rama_wren = 0; 92 | ramb_wren = 1; 93 | #240 94 | rama_wren = 0; 95 | ramb_wren = 0; 96 | #400 97 | 98 | 99 | rama_wren = 1; 100 | ramb_wren = 0; 101 | #240 102 | rama_wren = 0; 103 | ramb_wren = 1; 104 | #240 105 | rama_wren = 1; 106 | ramb_wren = 0; 107 | #240 108 | rama_wren = 0; 109 | ramb_wren = 1; 110 | #240 111 | rama_wren = 1; 112 | ramb_wren = 0; 113 | #240 114 | rama_wren = 0; 115 | ramb_wren = 1; 116 | #240 117 | rama_wren = 1; 118 | ramb_wren = 0; 119 | #240 120 | rama_wren = 0; 121 | ramb_wren = 1; 122 | #240 123 | rama_wren = 1; 124 | ramb_wren = 0; 125 | #240 126 | rama_wren = 0; 127 | ramb_wren = 1; 128 | end 129 | always #10 clk=~clk; 130 | endmodule 131 | 132 | -------------------------------------------------------------------------------- /DE2_CCD_edge/gen_ram_wradd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module gen_ram_wradd ( 3 | clk, 4 | aclr, 5 | rama_wren, 6 | ramb_wren, 7 | rama_wradd, 8 | ramb_wradd 9 | ); 10 | 11 | input clk, aclr; 12 | input rama_wren, ramb_wren; 13 | output [10:0] rama_wradd, ramb_wradd; 14 | 15 | //parameter column_size=12,row_size=10; 16 | parameter column_size=1280,row_size=1024; 17 | 18 | //Register Declaration 19 | reg [10:0] rama_wradd, ramb_wradd; 20 | 21 | always @ (posedge clk or negedge aclr) 22 | begin 23 | if (!aclr) 24 | rama_wradd <= 0; 25 | else if (rama_wren) 26 | if(rama_wradd==column_size-1) 27 | rama_wradd<=0; 28 | else 29 | rama_wradd <= rama_wradd + 1; 30 | end 31 | 32 | always @ (posedge clk or negedge aclr) 33 | begin 34 | if (!aclr) 35 | ramb_wradd <= 0; 36 | else if (ramb_wren) 37 | if(ramb_wradd==column_size-1) 38 | ramb_wradd<=0; 39 | else 40 | ramb_wradd <= ramb_wradd + 1; 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /DE2_CCD_edge/gen_ram_wren.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/gen_ram_wren.v -------------------------------------------------------------------------------- /DE2_CCD_edge/gen_ram_wren_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 14:32:35 05/28/2007 8 | // Design Name: gen_ram_wren 9 | // Module Name: D:/altera_work/CCD/gen_ram_wren_tb.v 10 | // Project Name: CCD 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: gen_ram_wren 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module gen_ram_wren_tb_v; 26 | 27 | // Inputs 28 | reg clk; 29 | reg aclr; 30 | reg data_valid; 31 | 32 | // Outputs 33 | wire rama_wren; 34 | wire ramb_wren; 35 | 36 | // Instantiate the Unit Under Test (UUT) 37 | gen_ram_wren uut ( 38 | .clk(clk), 39 | .aclr(aclr), 40 | .data_valid(data_valid), 41 | .rama_wren(rama_wren), 42 | .ramb_wren(ramb_wren) 43 | ); 44 | 45 | initial begin 46 | // Initialize Inputs 47 | clk = 0; 48 | aclr = 1; 49 | data_valid = 0; 50 | 51 | // Wait 100 ns for global reset to finish 52 | #100; 53 | aclr = 0; 54 | // Add stimulus here 55 | #30 56 | //#20 57 | data_valid=1; 58 | end 59 | always #10 clk=~clk; 60 | endmodule 61 | 62 | -------------------------------------------------------------------------------- /DE2_CCD_edge/mux_ram_row.v: -------------------------------------------------------------------------------- 1 | module mux_ram_row ( 2 | clk, 3 | aclr, 4 | rama, 5 | ramb, 6 | 7 | sel_row1, 8 | sel_row2, 9 | 10 | row_end, 11 | row1_1, 12 | row1_2, 13 | 14 | row2_1, 15 | row2_2 16 | 17 | 18 | ); 19 | 20 | parameter idle=0, A=1; 21 | 22 | input clk, aclr; 23 | input [9:0] rama, ramb; 24 | input sel_row1, sel_row2; 25 | input row_end; 26 | output [9:0] row1_1, row1_2; 27 | output [9:0] row2_1, row2_2; 28 | 29 | 30 | 31 | //Reg Declaration 32 | reg [9:0] col1_a, col1_b; 33 | reg [9:0] col2_a, col2_b; 34 | 35 | reg row_end_del1, row_end_del2, row_end_del3, row_end_del4, row_end_del5; 36 | reg [9:0] ram_col2_a, ram_col2_b; 37 | 38 | 39 | //Wire Declaration 40 | wire sel_edge_col3 = row_end_del3; 41 | wire sel_edge_col1 = row_end_del4; 42 | 43 | 44 | 45 | assign row1_1 = sel_edge_col1 ? (10'b0000000000) : (col1_a); 46 | assign row1_2 = col2_a; 47 | 48 | assign row2_1 = sel_edge_col1 ? (10'b0000000000) : (col1_b); 49 | assign row2_2 = col2_b; 50 | 51 | 52 | 53 | always @ (posedge clk or negedge aclr) 54 | begin 55 | if (!aclr) 56 | begin 57 | row_end_del1 <= 0; 58 | row_end_del2 <= 0; 59 | row_end_del3 <= 0; 60 | row_end_del4 <= 0; 61 | row_end_del5 <= 0; 62 | end 63 | else 64 | begin 65 | row_end_del1 <= row_end; 66 | row_end_del2 <= row_end_del1; 67 | row_end_del3 <= row_end_del2; 68 | row_end_del4 <= row_end_del3; 69 | row_end_del5 <= row_end_del4; 70 | end 71 | end 72 | 73 | always @ (rama or sel_row1) 74 | begin 75 | case (sel_row1) 76 | idle: 77 | begin 78 | ram_col2_a = 0; 79 | end 80 | A: 81 | begin 82 | ram_col2_a = rama; 83 | end 84 | endcase 85 | end 86 | 87 | always @ (posedge clk or negedge aclr) 88 | begin 89 | if (!aclr) 90 | begin 91 | col1_a <= 0; 92 | col2_a <= 0; 93 | end 94 | else 95 | begin 96 | col2_a <= ram_col2_a; 97 | col1_a <= col2_a; 98 | end 99 | end 100 | 101 | always @ ( ramb or sel_row2) 102 | begin 103 | case (sel_row2) 104 | idle: 105 | begin 106 | ram_col2_b = 0; 107 | end 108 | A: 109 | begin 110 | ram_col2_b = ramb; 111 | end 112 | endcase 113 | end 114 | 115 | always @ (posedge clk or negedge aclr) 116 | begin 117 | if (!aclr) 118 | begin 119 | col1_b <= 0; 120 | col2_b <= 0; 121 | end 122 | else 123 | begin 124 | col2_b <= ram_col2_b; 125 | col1_b <= col2_b; 126 | end 127 | end 128 | 129 | endmodule 130 | -------------------------------------------------------------------------------- /DE2_CCD_edge/mux_row.v: -------------------------------------------------------------------------------- 1 | module mux_row ( 2 | clk, 3 | aclr, 4 | rama, 5 | ramb, 6 | ramc, 7 | sel_row1, 8 | sel_row2, 9 | sel_row3, 10 | row_end, 11 | row1_1, 12 | row1_2, 13 | row1_3, 14 | row2_1, 15 | row2_2, 16 | row2_3, 17 | row3_1, 18 | row3_2, 19 | row3_3 20 | ); 21 | 22 | parameter idle=0, A=1, B=2, C=3; 23 | 24 | input clk, aclr; 25 | input [9:0] rama, ramb, ramc; 26 | input [1:0] sel_row1, sel_row2, sel_row3; 27 | input row_end; 28 | output [9:0] row1_1, row1_2, row1_3; 29 | output [9:0] row2_1, row2_2, row2_3; 30 | output [9:0] row3_1, row3_2, row3_3; 31 | 32 | 33 | //Reg Declaration 34 | wire [9:0] col1_a, col1_b, col1_c; 35 | wire [9:0] col2_a, col2_b, col2_c; 36 | wire [9:0] col3_a, col3_b, col3_c; 37 | reg row_end_del1, row_end_del2, row_end_del3, row_end_del4, row_end_del5; 38 | reg [9:0] ram_col3_a, ram_col3_b, ram_col3_c; 39 | reg [9:0] ram_col3_a_dly1,ram_col3_a_dly2,ram_col3_a_dly3,ram_col3_a_dly4,ram_col3_a_dly5,ram_col3_a_dly6; 40 | reg [9:0] ram_col3_b_dly1,ram_col3_b_dly2,ram_col3_b_dly3,ram_col3_b_dly4,ram_col3_b_dly5,ram_col3_b_dly6; 41 | reg [9:0] ram_col3_c_dly1,ram_col3_c_dly2,ram_col3_c_dly3,ram_col3_c_dly4,ram_col3_c_dly5,ram_col3_c_dly6; 42 | 43 | //Wire Declaration 44 | wire sel_edge_col3 = row_end_del4; 45 | wire sel_edge_col1 = row_end_del5; 46 | 47 | 48 | /**********************************************************/ 49 | // assign row1_1 = sel_edge_col1 ? (29'b0000000000) : (col1_a); 50 | // assign row1_2 = col2_a; 51 | // assign row1_3 = sel_edge_col3 ? (29'b0000000000) : (col3_a); 52 | // assign row2_1 = sel_edge_col1 ? (29'b0000000000) : (col1_b); 53 | // assign row2_2 = col2_b; 54 | // assign row2_3 = sel_edge_col3 ? (29'b0000000000) : (col3_b); 55 | // assign row3_1 = sel_edge_col1 ? (29'b0000000000) : (col1_c); 56 | // assign row3_2 = col2_c; 57 | // assign row3_3 = sel_edge_col3 ? (29'b0000000000) : (col3_c); 58 | 59 | assign row1_1 = col1_a; 60 | assign row1_2 = col2_a; 61 | assign row1_3 = col3_a; 62 | assign row2_1 = col1_b; 63 | assign row2_2 = col2_b; 64 | assign row2_3 = col3_b; 65 | assign row3_1 = col1_c; 66 | assign row3_2 = col2_c; 67 | assign row3_3 = col3_c; 68 | 69 | always @ (posedge clk or negedge aclr) 70 | begin 71 | if (!aclr) 72 | begin 73 | row_end_del1 <= 0; 74 | row_end_del2 <= 0; 75 | row_end_del3 <= 0; 76 | row_end_del4 <= 0; 77 | row_end_del5 <= 0; 78 | end 79 | else 80 | begin 81 | row_end_del1 <= row_end; 82 | row_end_del2 <= row_end_del1; 83 | row_end_del3 <= row_end_del2; 84 | row_end_del4 <= row_end_del3; 85 | row_end_del5 <= row_end_del4; 86 | end 87 | end 88 | 89 | always @ (rama or ramb or ramc or sel_row1) 90 | begin 91 | case (sel_row1) 92 | idle: 93 | begin 94 | ram_col3_a = 0; 95 | end 96 | A: 97 | begin 98 | ram_col3_a = rama; 99 | end 100 | B: 101 | begin 102 | ram_col3_a = ramb; 103 | end 104 | C: 105 | begin 106 | ram_col3_a = ramc; 107 | end 108 | endcase 109 | end 110 | 111 | 112 | always @ (posedge clk or negedge aclr) 113 | begin 114 | if (!aclr) 115 | begin 116 | ram_col3_a_dly1 <= 0; 117 | ram_col3_a_dly2 <= 0; 118 | ram_col3_a_dly3 <= 0; 119 | ram_col3_a_dly4 <= 0; 120 | ram_col3_a_dly5 <= 0; 121 | ram_col3_a_dly6 <= 0; 122 | end 123 | else 124 | begin 125 | ram_col3_a_dly1 <= ram_col3_a; 126 | ram_col3_a_dly2 <= ram_col3_a_dly1; 127 | ram_col3_a_dly3 <= ram_col3_a_dly2; 128 | ram_col3_a_dly4 <= ram_col3_a_dly3; 129 | ram_col3_a_dly5 <= ram_col3_a_dly4; 130 | ram_col3_a_dly6 <= ram_col3_a_dly5; 131 | end 132 | end 133 | 134 | assign col3_a=ram_col3_a_dly2; 135 | assign col2_a=ram_col3_a_dly4; 136 | assign col1_a=ram_col3_a_dly6; 137 | 138 | always @ (rama or ramb or ramc or sel_row2) 139 | begin 140 | case (sel_row2) 141 | idle: 142 | begin 143 | ram_col3_b = 0; 144 | end 145 | A: 146 | begin 147 | ram_col3_b = rama; 148 | end 149 | B: 150 | begin 151 | ram_col3_b = ramb; 152 | end 153 | C: 154 | begin 155 | ram_col3_b = ramc; 156 | end 157 | endcase 158 | end 159 | 160 | 161 | always @ (posedge clk or negedge aclr) 162 | begin 163 | if (!aclr) 164 | begin 165 | ram_col3_b_dly1 <= 0; 166 | ram_col3_b_dly2 <= 0; 167 | ram_col3_b_dly3 <= 0; 168 | ram_col3_b_dly4 <= 0; 169 | ram_col3_b_dly5 <= 0; 170 | ram_col3_b_dly6 <= 0; 171 | end 172 | else 173 | begin 174 | ram_col3_b_dly1 <= ram_col3_b; 175 | ram_col3_b_dly2 <= ram_col3_b_dly1; 176 | ram_col3_b_dly3 <= ram_col3_b_dly2; 177 | ram_col3_b_dly4 <= ram_col3_b_dly3; 178 | ram_col3_b_dly5 <= ram_col3_b_dly4; 179 | ram_col3_b_dly6 <= ram_col3_b_dly5; 180 | end 181 | end 182 | 183 | assign col3_b=ram_col3_b_dly2; 184 | assign col2_b=ram_col3_b_dly4; 185 | assign col1_b=ram_col3_b_dly6; 186 | 187 | always @ (rama or ramb or ramc or sel_row3) 188 | begin 189 | case (sel_row3) 190 | idle: 191 | begin 192 | ram_col3_c = 0; 193 | end 194 | A: 195 | begin 196 | ram_col3_c = rama; 197 | end 198 | B: 199 | begin 200 | ram_col3_c = ramb; 201 | end 202 | C: 203 | begin 204 | ram_col3_c = ramc; 205 | end 206 | endcase 207 | end 208 | 209 | 210 | always @ (posedge clk or negedge aclr) 211 | begin 212 | if (!aclr) 213 | begin 214 | ram_col3_c_dly1 <= 0; 215 | ram_col3_c_dly2 <= 0; 216 | ram_col3_c_dly3 <= 0; 217 | ram_col3_c_dly4 <= 0; 218 | ram_col3_c_dly5 <= 0; 219 | ram_col3_c_dly6 <= 0; 220 | end 221 | else 222 | begin 223 | ram_col3_c_dly1 <= ram_col3_c; 224 | ram_col3_c_dly2 <= ram_col3_c_dly1; 225 | ram_col3_c_dly3 <= ram_col3_c_dly2; 226 | ram_col3_c_dly4 <= ram_col3_c_dly3; 227 | ram_col3_c_dly5 <= ram_col3_c_dly4; 228 | ram_col3_c_dly6 <= ram_col3_c_dly5; 229 | end 230 | end 231 | 232 | assign col3_c=ram_col3_c_dly2; 233 | assign col2_c=ram_col3_c_dly4; 234 | assign col1_c=ram_col3_c_dly6; 235 | 236 | 237 | 238 | endmodule 239 | -------------------------------------------------------------------------------- /DE2_CCD_edge/ram.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2002 Altera Corporation 2 | // Any megafunction design, and related netlist (encrypted or decrypted), 3 | // support information, device programming or simulation file, and any other 4 | // associated documentation or information provided by Altera or a partner 5 | // under Altera's Megafunction Partnership Program may be used only 6 | // to program PLD devices (but not masked PLD devices) from Altera. Any 7 | // other use of such megafunction design, netlist, support information, 8 | // device programming or simulation file, or any other related documentation 9 | // or information is prohibited for any other purpose, including, but not 10 | // limited to modification, reverse engineering, de-compiling, or use with 11 | // any other silicon devices, unless such use is explicitly licensed under 12 | // a separate agreement with Altera or a megafunction partner. Title to the 13 | // intellectual property, including patents, copyrights, trademarks, trade 14 | // secrets, or maskworks, embodied in any such megafunction design, netlist, 15 | // support information, device programming or simulation file, or any other 16 | // related documentation or information provided by Altera or a megafunction 17 | // partner, remains with Altera, the megafunction partner, or their respective 18 | // licensors. No other licenses, including any licenses needed under any third 19 | // party's intellectual property, are provided herein. 20 | 21 | module ram( 22 | clk, 23 | rama_wren, 24 | rama_rden, 25 | ramb_wren, 26 | ramb_rden, 27 | ramc_wren, 28 | ramc_rden, 29 | datain, 30 | rama_rdadd, 31 | rama_wradd, 32 | ramb_rdadd, 33 | ramb_wradd, 34 | ramc_rdadd, 35 | ramc_wradd, 36 | rama, 37 | ramb, 38 | ramc 39 | ); 40 | 41 | input clk; 42 | input rama_wren; 43 | input rama_rden; 44 | input ramb_wren; 45 | input ramb_rden; 46 | input ramc_wren; 47 | input ramc_rden; 48 | input [9:0] datain; 49 | input [9:0] rama_rdadd; 50 | input [9:0] rama_wradd; 51 | input [9:0] ramb_rdadd; 52 | input [9:0] ramb_wradd; 53 | input [9:0] ramc_rdadd; 54 | input [9:0] ramc_wradd; 55 | output [9:0] rama; 56 | output [9:0] ramb; 57 | output [9:0] ramc; 58 | 59 | reg [9:0] SYNTHESIZED_WIRE_3; 60 | 61 | always@(posedge clk) 62 | begin 63 | begin 64 | 65 | SYNTHESIZED_WIRE_3 <= datain; 66 | 67 | end 68 | end 69 | 70 | ram_block b2v_RAM_A( .wren(rama_wren), 71 | .rden(rama_rden), 72 | .clock(clk), 73 | .data(SYNTHESIZED_WIRE_3), 74 | .rdaddress(rama_rdadd), 75 | .wraddress(rama_wradd), 76 | .q(rama)); 77 | 78 | ram_block b2v_RAM_B( .wren(ramb_wren), 79 | .rden(ramb_rden), 80 | .clock(clk), 81 | .data(SYNTHESIZED_WIRE_3), 82 | .rdaddress(ramb_rdadd), 83 | .wraddress(ramb_wradd), 84 | .q(ramb)); 85 | 86 | ram_block b2v_RAM_C( .wren(ramc_wren), 87 | .rden(ramc_rden), 88 | .clock(clk), 89 | .data(SYNTHESIZED_WIRE_3), 90 | .rdaddress(ramc_rdadd), 91 | .wraddress(ramc_wradd), 92 | .q(ramc)); 93 | 94 | 95 | 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /DE2_CCD_edge/ram_blk.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/ram_blk.v -------------------------------------------------------------------------------- /DE2_CCD_edge/ram_block.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTSYNCRAM% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: ram_blk.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // ============================================================ 11 | // ************************************************************ 12 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 13 | // ************************************************************ 14 | 15 | 16 | //Copyright (C) 1991-2002 Altera Corporation 17 | //Any megafunction design, and related netlist (encrypted or decrypted), 18 | //support information, device programming or simulation file, and any other 19 | //associated documentation or information provided by Altera or a partner 20 | //under Altera's Megafunction Partnership Program may be used only 21 | //to program PLD devices (but not masked PLD devices) from Altera. Any 22 | //other use of such megafunction design, netlist, support information, 23 | //device programming or simulation file, or any other related documentation 24 | //or information is prohibited for any other purpose, including, but not 25 | //limited to modification, reverse engineering, de-compiling, or use with 26 | //any other silicon devices, unless such use is explicitly licensed under 27 | //a separate agreement with Altera or a megafunction partner. Title to the 28 | //intellectual property, including patents, copyrights, trademarks, trade 29 | //secrets, or maskworks, embodied in any such megafunction design, netlist, 30 | //support information, device programming or simulation file, or any other 31 | //related documentation or information provided by Altera or a megafunction 32 | //partner, remains with Altera, the megafunction partner, or their respective 33 | //licensors. No other licenses, including any licenses needed under any third 34 | //party's intellectual property, are provided herein. 35 | 36 | module ram_block ( 37 | data, 38 | wren, 39 | wraddress, 40 | rdaddress, 41 | rden, 42 | clock, 43 | q); 44 | 45 | input [9:0] data; 46 | input wren; 47 | input [9:0] wraddress; 48 | input [9:0] rdaddress; 49 | input rden; 50 | input clock; 51 | output [9:0] q; 52 | reg [9:0] q; 53 | 54 | 55 | 56 | //parameter column_size=12,row_size=16; 57 | parameter column_size=1280,row_size=1024; 58 | 59 | reg [9:0] RAM[column_size/2-1:0]; 60 | always@(posedge clock) 61 | begin 62 | if(wren) 63 | RAM[wraddress]<=data; 64 | if(rden) 65 | q<=RAM[rdaddress]; 66 | end 67 | 68 | 69 | 70 | endmodule 71 | 72 | 73 | 74 | 75 | 76 | -------------------------------------------------------------------------------- /DE2_CCD_edge/two_d_filter.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2002 Altera Corporation 2 | // Any megafunction design, and related netlist (encrypted or decrypted), 3 | // support information, device programming or simulation file, and any other 4 | // associated documentation or information provided by Altera or a partner 5 | // under Altera's Megafunction Partnership Program may be used only 6 | // to program PLD devices (but not masked PLD devices) from Altera. Any 7 | // other use of such megafunction design, netlist, support information, 8 | // device programming or simulation file, or any other related documentation 9 | // or information is prohibited for any other purpose, including, but not 10 | // limited to modification, reverse engineering, de-compiling, or use with 11 | // any other silicon devices, unless such use is explicitly licensed under 12 | // a separate agreement with Altera or a megafunction partner. Title to the 13 | // intellectual property, including patents, copyrights, trademarks, trade 14 | // secrets, or maskworks, embodied in any such megafunction design, netlist, 15 | // support information, device programming or simulation file, or any other 16 | // related documentation or information provided by Altera or a megafunction 17 | // partner, remains with Altera, the megafunction partner, or their respective 18 | // licensors. No other licenses, including any licenses needed under any third 19 | // party's intellectual property, are provided herein. 20 | 21 | module two_d_filter( 22 | aclr, 23 | data_valid_in, 24 | clk, 25 | //clken, 26 | coef1_1, 27 | coef1_2, 28 | coef1_3, 29 | coef2_1, 30 | coef2_2, 31 | coef2_3, 32 | coef3_1, 33 | coef3_2, 34 | coef3_3, 35 | data, 36 | row1_1, 37 | row1_2, 38 | row1_3, 39 | row2_1, 40 | row2_2, 41 | row2_3, 42 | row3_1, 43 | row3_2, 44 | row3_3, 45 | data_valid_out, 46 | result 47 | 48 | ); 49 | 50 | input aclr; 51 | input data_valid_in; 52 | input clk; 53 | //input clken; 54 | input [9:0] coef1_1; 55 | input [9:0] coef1_2; 56 | input [9:0] coef1_3; 57 | input [9:0] coef2_1; 58 | input [9:0] coef2_2; 59 | input [9:0] coef2_3; 60 | input [9:0] coef3_1; 61 | input [9:0] coef3_2; 62 | input [9:0] coef3_3; 63 | input [9:0] data; 64 | output [23:0] result; 65 | output [9:0] row1_1, row1_2, row1_3; 66 | output [9:0] row2_1, row2_2, row2_3; 67 | output [9:0] row3_1, row3_2, row3_3; 68 | output data_valid_out; 69 | 70 | reg data_valid_out; 71 | wire data_end; 72 | wire [9:0] rama; 73 | wire [9:0] rama_rdadd; 74 | wire rama_rden; 75 | wire [9:0] rama_wradd; 76 | wire rama_wren; 77 | wire [9:0] ramb; 78 | wire [9:0] ramb_rdadd; 79 | wire ramb_rden; 80 | wire [9:0] ramb_wradd; 81 | wire ramb_wren; 82 | wire [9:0] ramc; 83 | wire [9:0] ramc_rdadd; 84 | wire ramc_rden; 85 | wire [9:0] ramc_wradd; 86 | wire ramc_wren; 87 | wire row_end; 88 | wire [1:0] sel_row1; 89 | wire [1:0] sel_row2; 90 | wire [1:0] sel_row3; 91 | wire [9:0] row1_1, row1_2, row1_3; 92 | wire [9:0] row2_1, row2_2, row2_3; 93 | wire [9:0] row3_1, row3_2, row3_3; 94 | 95 | 96 | 97 | ctrl b2v_inst ( 98 | .aclr(aclr), 99 | .data_valid_in(data_valid_in), 100 | .clk(clk), 101 | .frame_end_rd(frame_end), 102 | .rama_rden(rama_rden), 103 | .ramb_rden(ramb_rden), 104 | .ramc_rden(ramc_rden), 105 | .rama_wren(rama_wren), 106 | .ramb_wren(ramb_wren), 107 | .ramc_wren(ramc_wren), 108 | .row_end_rd(row_end), 109 | .rama_rdadd(rama_rdadd), 110 | .rama_wradd(rama_wradd), 111 | .ramb_rdadd(ramb_rdadd), 112 | .ramb_wradd(ramb_wradd), 113 | .ramc_rdadd(ramc_rdadd), 114 | .ramc_wradd(ramc_wradd), 115 | .sel_row1_out(sel_row1), 116 | .sel_row2_out(sel_row2), 117 | .sel_row3_out(sel_row3) 118 | ); 119 | 120 | ram b2v_inst2( .clk(clk), 121 | .rama_wren(rama_wren), 122 | .rama_rden(rama_rden), 123 | .ramb_wren(ramb_wren), 124 | .ramb_rden(ramb_rden), 125 | .ramc_wren(ramc_wren), 126 | .ramc_rden(ramc_rden), 127 | .datain(data), 128 | .rama_rdadd(rama_rdadd), 129 | .rama_wradd(rama_wradd), 130 | .ramb_rdadd(ramb_rdadd), 131 | .ramb_wradd(ramb_wradd), 132 | .ramc_rdadd(ramc_rdadd), 133 | .ramc_wradd(ramc_wradd), 134 | .rama(rama), 135 | .ramb(ramb), 136 | .ramc(ramc)); 137 | 138 | mux_row b2v_inst1( .clk(clk), 139 | .aclr(aclr), 140 | .row_end(row_end), 141 | .rama(rama), 142 | .ramb(ramb), 143 | .ramc(ramc), 144 | .sel_row1(sel_row1), 145 | .sel_row2(sel_row2), 146 | .sel_row3(sel_row3), 147 | .row1_1(row1_1), 148 | .row1_2(row1_2), 149 | .row1_3(row1_3), 150 | .row2_1(row2_1), 151 | .row2_2(row2_2), 152 | .row2_3(row2_3), 153 | .row3_1(row3_1), 154 | .row3_2(row3_2), 155 | .row3_3(row3_3)); 156 | 157 | 158 | filter b2v_inst4(.clk(clk), 159 | .aclr(!aclr), 160 | .clken(1), 161 | .coef1_1(coef1_1), 162 | .coef1_2(coef1_2), 163 | .coef1_3(coef1_3), 164 | .coef2_1(coef2_1), 165 | .coef2_2(coef2_2), 166 | .coef2_3(coef2_3), 167 | .coef3_1(coef3_1), 168 | .coef3_2(coef3_2), 169 | .coef3_3(coef3_3), 170 | .row1_1(row1_1), 171 | .row1_2(row1_2), 172 | .row1_3(row1_3), 173 | .row2_1(row2_1), 174 | .row2_2(row2_2), 175 | .row2_3(row2_3), 176 | .row3_1(row3_1), 177 | .row3_2(row3_2), 178 | .row3_3(row3_3), 179 | .result(result)); 180 | reg rama_rden_dly1,rama_rden_dly2,rama_rden_dly3,rama_rden_dly4,rama_rden_dly5,rama_rden_dly6,rama_rden_dly7; 181 | always@(posedge clk or negedge aclr) 182 | if(!aclr) 183 | begin 184 | rama_rden_dly1<=0; 185 | rama_rden_dly2<=0; 186 | rama_rden_dly3<=0; 187 | rama_rden_dly4<=0; 188 | data_valid_out<=0; 189 | end 190 | else 191 | begin 192 | rama_rden_dly1<=rama_rden; 193 | rama_rden_dly2<=rama_rden_dly1; 194 | rama_rden_dly3<=rama_rden_dly2; 195 | rama_rden_dly4<=rama_rden_dly3; 196 | rama_rden_dly5<=rama_rden_dly4; 197 | rama_rden_dly6<=rama_rden_dly5; 198 | rama_rden_dly7<=rama_rden_dly6; 199 | data_valid_out<=rama_rden_dly7; 200 | end 201 | 202 | 203 | endmodule 204 | 205 | 206 | -------------------------------------------------------------------------------- /DE2_CCD_edge/two_d_filter_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/suntodai/FPGA_image_processing/1fc8cb41fef6ede776abb12d3ad5838323092dc6/DE2_CCD_edge/two_d_filter_tb.v -------------------------------------------------------------------------------- /DE2_CCD_gray/CCD_Capture.v: -------------------------------------------------------------------------------- 1 | module CCD_Capture( oDATA, 2 | oDVAL, 3 | oX_Cont, 4 | oY_Cont, 5 | oFrame_Cont, 6 | iDATA, 7 | iFVAL, 8 | iLVAL, 9 | iSTART, 10 | iEND, 11 | iCLK, 12 | iRST ); 13 | 14 | input [9:0] iDATA; 15 | input iFVAL; 16 | input iLVAL; 17 | input iSTART; 18 | input iEND; 19 | input iCLK; 20 | input iRST; 21 | output [9:0] oDATA; 22 | output [10:0] oX_Cont; 23 | output [10:0] oY_Cont; 24 | output [31:0] oFrame_Cont; 25 | output oDVAL; 26 | reg Pre_FVAL; 27 | reg mCCD_FVAL; 28 | reg mCCD_LVAL; 29 | reg [9:0] mCCD_DATA; 30 | reg [10:0] X_Cont; 31 | reg [10:0] Y_Cont; 32 | reg [31:0] Frame_Cont; 33 | reg mSTART; 34 | 35 | assign oX_Cont = X_Cont; 36 | assign oY_Cont = Y_Cont; 37 | assign oFrame_Cont = Frame_Cont; 38 | assign oDATA = mCCD_DATA; 39 | assign oDVAL = mCCD_FVAL&mCCD_LVAL; 40 | 41 | always@(posedge iCLK or negedge iRST) 42 | begin 43 | if(!iRST) 44 | mSTART <= 0; 45 | else 46 | begin 47 | if(iSTART) 48 | mSTART <= 1; 49 | if(iEND) 50 | mSTART <= 0; 51 | end 52 | end 53 | 54 | always@(posedge iCLK or negedge iRST) 55 | begin 56 | if(!iRST) 57 | begin 58 | Pre_FVAL <= 0; 59 | mCCD_FVAL <= 0; 60 | mCCD_LVAL <= 0; 61 | mCCD_DATA <= 0; 62 | X_Cont <= 0; 63 | Y_Cont <= 0; 64 | end 65 | else 66 | begin 67 | Pre_FVAL <= iFVAL; 68 | if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART ) 69 | mCCD_FVAL <= 1; 70 | else if({Pre_FVAL,iFVAL}==2'b10) 71 | mCCD_FVAL <= 0; 72 | mCCD_LVAL <= iLVAL; 73 | mCCD_DATA <= iDATA; 74 | if(mCCD_FVAL) 75 | begin 76 | if(mCCD_LVAL) 77 | begin 78 | if(X_Cont<1279) 79 | X_Cont <= X_Cont+1; 80 | else 81 | begin 82 | X_Cont <= 0; 83 | Y_Cont <= Y_Cont+1; 84 | end 85 | end 86 | end 87 | else 88 | begin 89 | X_Cont <= 0; 90 | Y_Cont <= 0; 91 | end 92 | end 93 | end 94 | 95 | always@(posedge iCLK or negedge iRST) 96 | begin 97 | if(!iRST) 98 | Frame_Cont <= 0; 99 | else 100 | begin 101 | if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART ) 102 | Frame_Cont <= Frame_Cont+1; 103 | end 104 | end 105 | 106 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_gray/I2C_CCD_Config.v: -------------------------------------------------------------------------------- 1 | module I2C_CCD_Config ( // Host Side 2 | iCLK, 3 | iRST_N, 4 | iExposure, 5 | // I2C Side 6 | I2C_SCLK, 7 | I2C_SDAT ); 8 | // Host Side 9 | input iCLK; 10 | input iRST_N; 11 | input [15:0] iExposure; 12 | // I2C Side 13 | output I2C_SCLK; 14 | inout I2C_SDAT; 15 | // Internal Registers/Wires 16 | reg [15:0] mI2C_CLK_DIV; 17 | reg [23:0] mI2C_DATA; 18 | reg mI2C_CTRL_CLK; 19 | reg mI2C_GO; 20 | wire mI2C_END; 21 | wire mI2C_ACK; 22 | reg [15:0] LUT_DATA; 23 | reg [5:0] LUT_INDEX; 24 | reg [3:0] mSetup_ST; 25 | 26 | // Clock Setting 27 | parameter CLK_Freq = 50000000; // 50 MHz 28 | parameter I2C_Freq = 20000; // 20 KHz 29 | // LUT Data Number 30 | parameter LUT_SIZE = 17; 31 | 32 | ///////////////////// I2C Control Clock //////////////////////// 33 | always@(posedge iCLK or negedge iRST_N) 34 | begin 35 | if(!iRST_N) 36 | begin 37 | mI2C_CTRL_CLK <= 0; 38 | mI2C_CLK_DIV <= 0; 39 | end 40 | else 41 | begin 42 | if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) ) 43 | mI2C_CLK_DIV <= mI2C_CLK_DIV+1; 44 | else 45 | begin 46 | mI2C_CLK_DIV <= 0; 47 | mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK; 48 | end 49 | end 50 | end 51 | //////////////////////////////////////////////////////////////////// 52 | I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock 53 | .I2C_SCLK(I2C_SCLK), // I2C CLOCK 54 | .I2C_SDAT(I2C_SDAT), // I2C DATA 55 | .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA] 56 | .GO(mI2C_GO), // GO transfor 57 | .END(mI2C_END), // END transfor 58 | .ACK(mI2C_ACK), // ACK 59 | .RESET(iRST_N) ); 60 | //////////////////////////////////////////////////////////////////// 61 | ////////////////////// Config Control //////////////////////////// 62 | always@(posedge mI2C_CTRL_CLK or negedge iRST_N) 63 | begin 64 | if(!iRST_N) 65 | begin 66 | LUT_INDEX <= 0; 67 | mSetup_ST <= 0; 68 | mI2C_GO <= 0; 69 | end 70 | else 71 | begin 72 | if(LUT_INDEX= 4) & (SD_COUNTER <=30))? ~CLOCK :0 ); 78 | wire I2C_SDAT=SDO?1'bz:0 ; 79 | 80 | reg ACK1,ACK2,ACK3; 81 | wire ACK=ACK1 | ACK2 |ACK3; 82 | 83 | //--I2C COUNTER 84 | always @(negedge RESET or posedge CLOCK ) begin 85 | if (!RESET) SD_COUNTER=6'b111111; 86 | else begin 87 | if (GO==0) 88 | SD_COUNTER=0; 89 | else 90 | if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+1; 91 | end 92 | end 93 | //---- 94 | 95 | always @(negedge RESET or posedge CLOCK ) begin 96 | if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end 97 | else 98 | case (SD_COUNTER) 99 | 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end 100 | //start 101 | 6'd1 : begin SD=I2C_DATA;SDO=0;end 102 | 6'd2 : SCLK=0; 103 | //SLAVE ADDR 104 | 6'd3 : SDO=SD[23]; 105 | 6'd4 : SDO=SD[22]; 106 | 6'd5 : SDO=SD[21]; 107 | 6'd6 : SDO=SD[20]; 108 | 6'd7 : SDO=SD[19]; 109 | 6'd8 : SDO=SD[18]; 110 | 6'd9 : SDO=SD[17]; 111 | 6'd10 : SDO=SD[16]; 112 | 6'd11 : SDO=1'b1;//ACK 113 | 114 | //SUB ADDR 115 | 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end 116 | 6'd13 : SDO=SD[14]; 117 | 6'd14 : SDO=SD[13]; 118 | 6'd15 : SDO=SD[12]; 119 | 6'd16 : SDO=SD[11]; 120 | 6'd17 : SDO=SD[10]; 121 | 6'd18 : SDO=SD[9]; 122 | 6'd19 : SDO=SD[8]; 123 | 6'd20 : SDO=1'b1;//ACK 124 | 125 | //DATA 126 | 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end 127 | 6'd22 : SDO=SD[6]; 128 | 6'd23 : SDO=SD[5]; 129 | 6'd24 : SDO=SD[4]; 130 | 6'd25 : SDO=SD[3]; 131 | 6'd26 : SDO=SD[2]; 132 | 6'd27 : SDO=SD[1]; 133 | 6'd28 : SDO=SD[0]; 134 | 6'd29 : SDO=1'b1;//ACK 135 | 136 | 137 | //stop 138 | 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end 139 | 6'd31 : SCLK=1'b1; 140 | 6'd32 : begin SDO=1'b1; END=1; end 141 | 142 | endcase 143 | end 144 | 145 | 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /DE2_CCD_gray/Line_Buffer.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %Shift register (RAM-based)% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altshift_taps 5 | 6 | // ============================================================ 7 | // File Name: Line_Buffer.v 8 | // Megafunction Name(s): 9 | // altshift_taps 10 | // ============================================================ 11 | // ************************************************************ 12 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 13 | // 14 | // 5.1 Build 176 10/26/2005 SJ Full Version 15 | // ************************************************************ 16 | 17 | 18 | //Copyright (C) 1991-2005 Altera Corporation 19 | //Your use of Altera Corporation's design tools, logic functions 20 | //and other software and tools, and its AMPP partner logic 21 | //functions, and any output files any of the foregoing 22 | //(including device programming or simulation files), and any 23 | //associated documentation or information are expressly subject 24 | //to the terms and conditions of the Altera Program License 25 | //Subscription Agreement, Altera MegaCore Function License 26 | //Agreement, or other applicable license agreement, including, 27 | //without limitation, that your use is for the sole purpose of 28 | //programming logic devices manufactured by Altera and sold by 29 | //Altera or its authorized distributors. Please refer to the 30 | //applicable agreement for further details. 31 | 32 | 33 | // synopsys translate_off 34 | `timescale 1 ps / 1 ps 35 | // synopsys translate_on 36 | module Line_Buffer ( 37 | clken, 38 | clock, 39 | shiftin, 40 | shiftout, 41 | taps0x, 42 | taps1x); 43 | 44 | input clken; 45 | input clock; 46 | input [9:0] shiftin; 47 | output [9:0] shiftout; 48 | output [9:0] taps0x; 49 | output [9:0] taps1x; 50 | 51 | wire [19:0] sub_wire0; 52 | wire [9:0] sub_wire3; 53 | wire [19:10] sub_wire1 = sub_wire0[19:10]; 54 | wire [9:0] sub_wire2 = sub_wire0[9:0]; 55 | wire [9:0] taps1x = sub_wire1[19:10]; 56 | wire [9:0] taps0x = sub_wire2[9:0]; 57 | wire [9:0] shiftout = sub_wire3[9:0]; 58 | 59 | altshift_taps altshift_taps_component ( 60 | .clken (clken), 61 | .clock (clock), 62 | .shiftin (shiftin), 63 | .taps (sub_wire0), 64 | .shiftout (sub_wire3)); 65 | defparam 66 | altshift_taps_component.lpm_type = "altshift_taps", 67 | altshift_taps_component.number_of_taps = 2, 68 | altshift_taps_component.tap_distance = 1280, 69 | altshift_taps_component.width = 10; 70 | 71 | 72 | endmodule 73 | 74 | // ============================================================ 75 | // CNX file retrieval info 76 | // ============================================================ 77 | // Retrieval info: PRIVATE: CLKEN NUMERIC "1" 78 | // Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1" 79 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 80 | // Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2" 81 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 82 | // Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280" 83 | // Retrieval info: PRIVATE: WIDTH NUMERIC "10" 84 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps" 85 | // Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2" 86 | // Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280" 87 | // Retrieval info: CONSTANT: WIDTH NUMERIC "10" 88 | // Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken 89 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 90 | // Retrieval info: USED_PORT: shiftin 0 0 10 0 INPUT NODEFVAL shiftin[9..0] 91 | // Retrieval info: USED_PORT: shiftout 0 0 10 0 OUTPUT NODEFVAL shiftout[9..0] 92 | // Retrieval info: USED_PORT: taps0x 0 0 10 0 OUTPUT NODEFVAL taps0x[9..0] 93 | // Retrieval info: USED_PORT: taps1x 0 0 10 0 OUTPUT NODEFVAL taps1x[9..0] 94 | // Retrieval info: CONNECT: @shiftin 0 0 10 0 shiftin 0 0 10 0 95 | // Retrieval info: CONNECT: shiftout 0 0 10 0 @shiftout 0 0 10 0 96 | // Retrieval info: CONNECT: taps0x 0 0 10 0 @taps 0 0 10 0 97 | // Retrieval info: CONNECT: taps1x 0 0 10 0 @taps 0 0 10 10 98 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 99 | // Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 100 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 101 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE 102 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE 103 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf FALSE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE 107 | -------------------------------------------------------------------------------- /DE2_CCD_gray/Mirror_Col.v: -------------------------------------------------------------------------------- 1 | module Mirror_Col( // Input Side 2 | iCCD_R, 3 | iCCD_G, 4 | iCCD_B, 5 | iCCD_DVAL, 6 | iCCD_PIXCLK, 7 | iRST_N, 8 | // Output Side 9 | oCCD_R, 10 | oCCD_G, 11 | oCCD_B, 12 | oCCD_DVAL ); 13 | // Input Side 14 | input [9:0] iCCD_R; 15 | input [9:0] iCCD_G; 16 | input [9:0] iCCD_B; 17 | input iCCD_DVAL; 18 | input iCCD_PIXCLK; 19 | input iRST_N; 20 | // Output Side 21 | output [9:0] oCCD_R; 22 | output [9:0] oCCD_G; 23 | output [9:0] oCCD_B; 24 | output oCCD_DVAL; 25 | // Internal Registers 26 | reg [9:0] Z_Cont; 27 | reg mCCD_DVAL; 28 | 29 | assign oCCD_DVAL = mCCD_DVAL; 30 | 31 | always@(posedge iCCD_PIXCLK or negedge iRST_N) 32 | begin 33 | if(!iRST_N) 34 | begin 35 | mCCD_DVAL <= 0; 36 | Z_Cont <= 0; 37 | end 38 | else 39 | begin 40 | mCCD_DVAL <= iCCD_DVAL; 41 | if(Z_Cont<640) 42 | begin 43 | if(iCCD_DVAL) 44 | Z_Cont <= Z_Cont+1'b1; 45 | end 46 | else 47 | Z_Cont <= 0; 48 | end 49 | end 50 | 51 | Stack_RAM ( 52 | .clock(iCCD_PIXCLK), 53 | .data(iCCD_R), 54 | .rdaddress(639-Z_Cont), 55 | .wraddress(Z_Cont), 56 | .wren(iCCD_DVAL), 57 | .q(oCCD_R)); 58 | 59 | Stack_RAM ( 60 | .clock(iCCD_PIXCLK), 61 | .data(iCCD_G), 62 | .rdaddress(639-Z_Cont), 63 | .wraddress(Z_Cont), 64 | .wren(iCCD_DVAL), 65 | .q(oCCD_G)); 66 | 67 | Stack_RAM ( 68 | .clock(iCCD_PIXCLK), 69 | .data(iCCD_B), 70 | .rdaddress(639-Z_Cont), 71 | .wraddress(Z_Cont), 72 | .wren(iCCD_DVAL), 73 | .q(oCCD_B)); 74 | 75 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_gray/RAW2RGB.v: -------------------------------------------------------------------------------- 1 | module RAW2RGB( oRed, 2 | oGreen, 3 | oBlue, 4 | oDVAL, 5 | iX_Cont, 6 | iY_Cont, 7 | iDATA, 8 | iDVAL, 9 | iCLK, 10 | iRST ); 11 | 12 | input [10:0] iX_Cont; 13 | input [10:0] iY_Cont; 14 | input [9:0] iDATA; 15 | input iDVAL; 16 | input iCLK; 17 | input iRST; 18 | output [9:0] oRed; 19 | output [9:0] oGreen; 20 | output [9:0] oBlue; 21 | output oDVAL; 22 | wire [9:0] mDATA_0; 23 | wire [9:0] mDATA_1; 24 | reg [9:0] mDATAd_0; 25 | reg [9:0] mDATAd_1; 26 | reg [9:0] mCCD_R; 27 | reg [10:0] mCCD_G; 28 | reg [9:0] mCCD_B; 29 | reg mDVAL; 30 | 31 | assign oRed = mCCD_R[9:0]; 32 | assign oGreen = mCCD_G[10:1]; 33 | assign oBlue = mCCD_B[9:0]; 34 | assign oDVAL = mDVAL; 35 | 36 | Line_Buffer u0 ( .clken(iDVAL), 37 | .clock(iCLK), 38 | .shiftin(iDATA), 39 | .taps0x(mDATA_1), 40 | .taps1x(mDATA_0) ); 41 | 42 | always@(posedge iCLK or negedge iRST) 43 | begin 44 | if(!iRST) 45 | begin 46 | mCCD_R <= 0; 47 | mCCD_G <= 0; 48 | mCCD_B <= 0; 49 | mDATAd_0<= 0; 50 | mDATAd_1<= 0; 51 | mDVAL <= 0; 52 | end 53 | else 54 | begin 55 | mDATAd_0 <= mDATA_0; 56 | mDATAd_1 <= mDATA_1; 57 | mDVAL <= {iY_Cont[0]|iX_Cont[0]} ? 1'b0 : iDVAL; 58 | if({iY_Cont[0],iX_Cont[0]}==2'b01) 59 | begin 60 | mCCD_R <= mDATA_0; 61 | mCCD_G <= mDATAd_0+mDATA_1; 62 | mCCD_B <= mDATAd_1; 63 | end 64 | else if({iY_Cont[0],iX_Cont[0]}==2'b00) 65 | begin 66 | mCCD_R <= mDATAd_0; 67 | mCCD_G <= mDATA_0+mDATAd_1; 68 | mCCD_B <= mDATA_1; 69 | end 70 | else if({iY_Cont[0],iX_Cont[0]}==2'b11) 71 | begin 72 | mCCD_R <= mDATA_1; 73 | mCCD_G <= mDATA_0+mDATAd_1; 74 | mCCD_B <= mDATAd_0; 75 | end 76 | else if({iY_Cont[0],iX_Cont[0]}==2'b10) 77 | begin 78 | mCCD_R <= mDATAd_1; 79 | mCCD_G <= mDATAd_0+mDATA_1; 80 | mCCD_B <= mDATA_0; 81 | end 82 | end 83 | end 84 | 85 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_gray/RGB2Gray.v: -------------------------------------------------------------------------------- 1 | /* 2 | (C) OOMusou 2008 http://oomusou.cnblogs.com 3 | 4 | Filename : RGB2Gray.v 5 | Compiler : Quartus II 7.2 SP3 6 | Description : RGB to gray 7 | Release : 07/14/2008 1.0 8 | */ 9 | 10 | module RGB2Gray ( 11 | input clk, 12 | input rst_n, 13 | input [9:0] i_r, 14 | input [9:0] i_g, 15 | input [9:0] i_b, 16 | output reg [9:0] o_r, 17 | output reg [9:0] o_g, 18 | output reg [9:0] o_b 19 | ); 20 | 21 | always@(posedge clk or negedge rst_n) begin 22 | if (!rst_n) begin 23 | o_r <= {10{1'b0}}; 24 | o_g <= {10{1'b0}}; 25 | o_b <= {10{1'b0}}; 26 | end 27 | else begin 28 | o_r <= (i_r + i_g + i_b) / 3; 29 | o_g <= (i_r + i_g + i_b) / 3; 30 | o_b <= (i_r + i_g + i_b) / 3; 31 | end 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_gray/Reset_Delay.v: -------------------------------------------------------------------------------- 1 | module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2); 2 | input iCLK; 3 | input iRST; 4 | output reg oRST_0; 5 | output reg oRST_1; 6 | output reg oRST_2; 7 | 8 | reg [21:0] Cont; 9 | 10 | always@(posedge iCLK or negedge iRST) 11 | begin 12 | if(!iRST) 13 | begin 14 | Cont <= 0; 15 | oRST_0 <= 0; 16 | oRST_1 <= 0; 17 | oRST_2 <= 0; 18 | end 19 | else 20 | begin 21 | if(Cont!=22'h3FFFFF) 22 | Cont <= Cont+1; 23 | if(Cont>=22'h1FFFFF) 24 | oRST_0 <= 1; 25 | if(Cont>=22'h2FFFFF) 26 | oRST_1 <= 1; 27 | if(Cont>=22'h3FFFFF) 28 | oRST_2 <= 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_gray/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT ( oSEG,iDIG ); 2 | input [3:0] iDIG; 3 | output [6:0] oSEG; 4 | reg [6:0] oSEG; 5 | 6 | always @(iDIG) 7 | begin 8 | case(iDIG) 9 | 4'h1: oSEG = 7'b1111001; // ---t---- 10 | 4'h2: oSEG = 7'b0100100; // | | 11 | 4'h3: oSEG = 7'b0110000; // lt rt 12 | 4'h4: oSEG = 7'b0011001; // | | 13 | 4'h5: oSEG = 7'b0010010; // ---m---- 14 | 4'h6: oSEG = 7'b0000010; // | | 15 | 4'h7: oSEG = 7'b1111000; // lb rb 16 | 4'h8: oSEG = 7'b0000000; // | | 17 | 4'h9: oSEG = 7'b0011000; // ---b---- 18 | 4'ha: oSEG = 7'b0001000; 19 | 4'hb: oSEG = 7'b0000011; 20 | 4'hc: oSEG = 7'b1000110; 21 | 4'hd: oSEG = 7'b0100001; 22 | 4'he: oSEG = 7'b0000110; 23 | 4'hf: oSEG = 7'b0001110; 24 | 4'h0: oSEG = 7'b1000000; 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /DE2_CCD_gray/SEG7_LUT_8.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG ); 2 | input [31:0] iDIG; 3 | output [6:0] oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7; 4 | 5 | SEG7_LUT u0 ( oSEG0,iDIG[3:0] ); 6 | SEG7_LUT u1 ( oSEG1,iDIG[7:4] ); 7 | SEG7_LUT u2 ( oSEG2,iDIG[11:8] ); 8 | SEG7_LUT u3 ( oSEG3,iDIG[15:12] ); 9 | SEG7_LUT u4 ( oSEG4,iDIG[19:16] ); 10 | SEG7_LUT u5 ( oSEG5,iDIG[23:20] ); 11 | SEG7_LUT u6 ( oSEG6,iDIG[27:24] ); 12 | SEG7_LUT u7 ( oSEG7,iDIG[31:28] ); 13 | 14 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_gray/Sdram_Control_4Port/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_gray/Sdram_Control_4Port/control_interface.v: -------------------------------------------------------------------------------- 1 | module control_interface( 2 | CLK, 3 | RESET_N, 4 | CMD, 5 | ADDR, 6 | REF_ACK, 7 | INIT_ACK, 8 | CM_ACK, 9 | NOP, 10 | READA, 11 | WRITEA, 12 | REFRESH, 13 | PRECHARGE, 14 | LOAD_MODE, 15 | SADDR, 16 | REF_REQ, 17 | INIT_REQ, 18 | CMD_ACK 19 | ); 20 | 21 | `include "Sdram_Params.h" 22 | 23 | input CLK; // System Clock 24 | input RESET_N; // System Reset 25 | input [2:0] CMD; // Command input 26 | input [`ASIZE-1:0] ADDR; // Address 27 | input REF_ACK; // Refresh request acknowledge 28 | input INIT_ACK; // Initial request acknowledge 29 | input CM_ACK; // Command acknowledge 30 | output NOP; // Decoded NOP command 31 | output READA; // Decoded READA command 32 | output WRITEA; // Decoded WRITEA command 33 | output REFRESH; // Decoded REFRESH command 34 | output PRECHARGE; // Decoded PRECHARGE command 35 | output LOAD_MODE; // Decoded LOAD_MODE command 36 | output [`ASIZE-1:0] SADDR; // Registered version of ADDR 37 | output REF_REQ; // Hidden refresh request 38 | output INIT_REQ; // Hidden initial request 39 | output CMD_ACK; // Command acknowledge 40 | 41 | 42 | 43 | reg NOP; 44 | reg READA; 45 | reg WRITEA; 46 | reg REFRESH; 47 | reg PRECHARGE; 48 | reg LOAD_MODE; 49 | reg [`ASIZE-1:0] SADDR; 50 | reg REF_REQ; 51 | reg INIT_REQ; 52 | reg CMD_ACK; 53 | 54 | // Internal signals 55 | reg [15:0] timer; 56 | reg [15:0] init_timer; 57 | 58 | 59 | 60 | // Command decode and ADDR register 61 | always @(posedge CLK or negedge RESET_N) 62 | begin 63 | if (RESET_N == 0) 64 | begin 65 | NOP <= 0; 66 | READA <= 0; 67 | WRITEA <= 0; 68 | SADDR <= 0; 69 | end 70 | 71 | else 72 | begin 73 | 74 | SADDR <= ADDR; // register the address to keep proper 75 | // alignment with the command 76 | 77 | if (CMD == 3'b000) // NOP command 78 | NOP <= 1; 79 | else 80 | NOP <= 0; 81 | 82 | if (CMD == 3'b001) // READA command 83 | READA <= 1; 84 | else 85 | READA <= 0; 86 | 87 | if (CMD == 3'b010) // WRITEA command 88 | WRITEA <= 1; 89 | else 90 | WRITEA <= 0; 91 | 92 | end 93 | end 94 | 95 | 96 | // Generate CMD_ACK 97 | always @(posedge CLK or negedge RESET_N) 98 | begin 99 | if (RESET_N == 0) 100 | CMD_ACK <= 0; 101 | else 102 | if ((CM_ACK == 1) & (CMD_ACK == 0)) 103 | CMD_ACK <= 1; 104 | else 105 | CMD_ACK <= 0; 106 | end 107 | 108 | 109 | // refresh timer 110 | always @(posedge CLK or negedge RESET_N) begin 111 | if (RESET_N == 0) 112 | begin 113 | timer <= 0; 114 | REF_REQ <= 0; 115 | end 116 | else 117 | begin 118 | if (REF_ACK == 1) 119 | begin 120 | timer <= REF_PER; 121 | REF_REQ <=0; 122 | end 123 | else if (INIT_REQ == 1) 124 | begin 125 | timer <= REF_PER+200; 126 | REF_REQ <=0; 127 | end 128 | else 129 | timer <= timer - 1'b1; 130 | 131 | if (timer==0) 132 | REF_REQ <= 1; 133 | 134 | end 135 | end 136 | 137 | // initial timer 138 | always @(posedge CLK or negedge RESET_N) begin 139 | if (RESET_N == 0) 140 | begin 141 | init_timer <= 0; 142 | REFRESH <= 0; 143 | PRECHARGE <= 0; 144 | LOAD_MODE <= 0; 145 | INIT_REQ <= 0; 146 | end 147 | else 148 | begin 149 | if (init_timer < (INIT_PER+201)) 150 | init_timer <= init_timer+1; 151 | 152 | if (init_timer < INIT_PER) 153 | begin 154 | REFRESH <=0; 155 | PRECHARGE <=0; 156 | LOAD_MODE <=0; 157 | INIT_REQ <=1; 158 | end 159 | else if(init_timer == (INIT_PER+20)) 160 | begin 161 | REFRESH <=0; 162 | PRECHARGE <=1; 163 | LOAD_MODE <=0; 164 | INIT_REQ <=0; 165 | end 166 | else if( (init_timer == (INIT_PER+40)) || 167 | (init_timer == (INIT_PER+60)) || 168 | (init_timer == (INIT_PER+80)) || 169 | (init_timer == (INIT_PER+100)) || 170 | (init_timer == (INIT_PER+120)) || 171 | (init_timer == (INIT_PER+140)) || 172 | (init_timer == (INIT_PER+160)) || 173 | (init_timer == (INIT_PER+180)) ) 174 | begin 175 | REFRESH <=1; 176 | PRECHARGE <=0; 177 | LOAD_MODE <=0; 178 | INIT_REQ <=0; 179 | end 180 | else if(init_timer == (INIT_PER+200)) 181 | begin 182 | REFRESH <=0; 183 | PRECHARGE <=0; 184 | LOAD_MODE <=1; 185 | INIT_REQ <=0; 186 | end 187 | else 188 | begin 189 | REFRESH <=0; 190 | PRECHARGE <=0; 191 | LOAD_MODE <=0; 192 | INIT_REQ <=0; 193 | end 194 | end 195 | end 196 | 197 | endmodule 198 | 199 | -------------------------------------------------------------------------------- /DE2_CCD_gray/Sdram_Control_4Port/sdr_data_path.v: -------------------------------------------------------------------------------- 1 | module sdr_data_path( 2 | CLK, 3 | RESET_N, 4 | DATAIN, 5 | DM, 6 | DQOUT, 7 | DQM 8 | ); 9 | 10 | `include "Sdram_Params.h" 11 | 12 | input CLK; // System Clock 13 | input RESET_N; // System Reset 14 | input [`DSIZE-1:0] DATAIN; // Data input from the host 15 | input [`DSIZE/8-1:0] DM; // byte data masks 16 | output [`DSIZE-1:0] DQOUT; 17 | output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs 18 | reg [`DSIZE/8-1:0] DQM; 19 | 20 | 21 | 22 | // Allign the input and output data to the SDRAM control path 23 | always @(posedge CLK or negedge RESET_N) 24 | begin 25 | if (RESET_N == 0) 26 | DQM <= `DSIZE/8-1'hF; 27 | else 28 | DQM <= DM; 29 | end 30 | 31 | assign DQOUT = DATAIN; 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /DE2_CCD_gray/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_gray/VGA_Controller.v: -------------------------------------------------------------------------------- 1 | module VGA_Controller( // Host Side 2 | iRed, 3 | iGreen, 4 | iBlue, 5 | oRequest, 6 | // VGA Side 7 | oVGA_R, 8 | oVGA_G, 9 | oVGA_B, 10 | oVGA_H_SYNC, 11 | oVGA_V_SYNC, 12 | oVGA_SYNC, 13 | oVGA_BLANK, 14 | oVGA_CLOCK, 15 | // Control Signal 16 | iCLK, 17 | iRST_N ); 18 | 19 | `include "VGA_Param.h" 20 | 21 | // Host Side 22 | input [9:0] iRed; 23 | input [9:0] iGreen; 24 | input [9:0] iBlue; 25 | output reg oRequest; 26 | // VGA Side 27 | output [9:0] oVGA_R; 28 | output [9:0] oVGA_G; 29 | output [9:0] oVGA_B; 30 | output reg oVGA_H_SYNC; 31 | output reg oVGA_V_SYNC; 32 | output oVGA_SYNC; 33 | output oVGA_BLANK; 34 | output oVGA_CLOCK; 35 | // Control Signal 36 | input iCLK; 37 | input iRST_N; 38 | 39 | // Internal Registers and Wires 40 | reg [9:0] H_Cont; 41 | reg [9:0] V_Cont; 42 | reg [9:0] Cur_Color_R; 43 | reg [9:0] Cur_Color_G; 44 | reg [9:0] Cur_Color_B; 45 | wire mCursor_EN; 46 | wire mRed_EN; 47 | wire mGreen_EN; 48 | wire mBlue_EN; 49 | 50 | assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC; 51 | assign oVGA_SYNC = 1'b0; 52 | assign oVGA_CLOCK = iCLK; 53 | 54 | assign oVGA_R = ( H_Cont>=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START-2 && H_Cont=Y_START && V_Cont= 4) & (SD_COUNTER <=30))? ~CLOCK :0 ); 78 | wire I2C_SDAT=SDO?1'bz:0 ; 79 | 80 | reg ACK1,ACK2,ACK3; 81 | wire ACK=ACK1 | ACK2 |ACK3; 82 | 83 | //--I2C COUNTER 84 | always @(negedge RESET or posedge CLOCK ) begin 85 | if (!RESET) SD_COUNTER=6'b111111; 86 | else begin 87 | if (GO==0) 88 | SD_COUNTER=0; 89 | else 90 | if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+1; 91 | end 92 | end 93 | //---- 94 | 95 | always @(negedge RESET or posedge CLOCK ) begin 96 | if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end 97 | else 98 | case (SD_COUNTER) 99 | 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end 100 | //start 101 | 6'd1 : begin SD=I2C_DATA;SDO=0;end 102 | 6'd2 : SCLK=0; 103 | //SLAVE ADDR 104 | 6'd3 : SDO=SD[23]; 105 | 6'd4 : SDO=SD[22]; 106 | 6'd5 : SDO=SD[21]; 107 | 6'd6 : SDO=SD[20]; 108 | 6'd7 : SDO=SD[19]; 109 | 6'd8 : SDO=SD[18]; 110 | 6'd9 : SDO=SD[17]; 111 | 6'd10 : SDO=SD[16]; 112 | 6'd11 : SDO=1'b1;//ACK 113 | 114 | //SUB ADDR 115 | 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end 116 | 6'd13 : SDO=SD[14]; 117 | 6'd14 : SDO=SD[13]; 118 | 6'd15 : SDO=SD[12]; 119 | 6'd16 : SDO=SD[11]; 120 | 6'd17 : SDO=SD[10]; 121 | 6'd18 : SDO=SD[9]; 122 | 6'd19 : SDO=SD[8]; 123 | 6'd20 : SDO=1'b1;//ACK 124 | 125 | //DATA 126 | 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end 127 | 6'd22 : SDO=SD[6]; 128 | 6'd23 : SDO=SD[5]; 129 | 6'd24 : SDO=SD[4]; 130 | 6'd25 : SDO=SD[3]; 131 | 6'd26 : SDO=SD[2]; 132 | 6'd27 : SDO=SD[1]; 133 | 6'd28 : SDO=SD[0]; 134 | 6'd29 : SDO=1'b1;//ACK 135 | 136 | 137 | //stop 138 | 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end 139 | 6'd31 : SCLK=1'b1; 140 | 6'd32 : begin SDO=1'b1; END=1; end 141 | 142 | endcase 143 | end 144 | 145 | 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /DE2_CCD_smooth/Line_Buffer.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %Shift register (RAM-based)% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altshift_taps 5 | 6 | // ============================================================ 7 | // File Name: Line_Buffer.v 8 | // Megafunction Name(s): 9 | // altshift_taps 10 | // ============================================================ 11 | // ************************************************************ 12 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 13 | // 14 | // 5.1 Build 176 10/26/2005 SJ Full Version 15 | // ************************************************************ 16 | 17 | 18 | //Copyright (C) 1991-2005 Altera Corporation 19 | //Your use of Altera Corporation's design tools, logic functions 20 | //and other software and tools, and its AMPP partner logic 21 | //functions, and any output files any of the foregoing 22 | //(including device programming or simulation files), and any 23 | //associated documentation or information are expressly subject 24 | //to the terms and conditions of the Altera Program License 25 | //Subscription Agreement, Altera MegaCore Function License 26 | //Agreement, or other applicable license agreement, including, 27 | //without limitation, that your use is for the sole purpose of 28 | //programming logic devices manufactured by Altera and sold by 29 | //Altera or its authorized distributors. Please refer to the 30 | //applicable agreement for further details. 31 | 32 | 33 | // synopsys translate_off 34 | `timescale 1 ps / 1 ps 35 | // synopsys translate_on 36 | module Line_Buffer ( 37 | clken, 38 | clock, 39 | shiftin, 40 | shiftout, 41 | taps0x, 42 | taps1x); 43 | 44 | input clken; 45 | input clock; 46 | input [9:0] shiftin; 47 | output [9:0] shiftout; 48 | output [9:0] taps0x; 49 | output [9:0] taps1x; 50 | 51 | wire [19:0] sub_wire0; 52 | wire [9:0] sub_wire3; 53 | wire [19:10] sub_wire1 = sub_wire0[19:10]; 54 | wire [9:0] sub_wire2 = sub_wire0[9:0]; 55 | wire [9:0] taps1x = sub_wire1[19:10]; 56 | wire [9:0] taps0x = sub_wire2[9:0]; 57 | wire [9:0] shiftout = sub_wire3[9:0]; 58 | 59 | altshift_taps altshift_taps_component ( 60 | .clken (clken), 61 | .clock (clock), 62 | .shiftin (shiftin), 63 | .taps (sub_wire0), 64 | .shiftout (sub_wire3)); 65 | defparam 66 | altshift_taps_component.lpm_type = "altshift_taps", 67 | altshift_taps_component.number_of_taps = 2, 68 | altshift_taps_component.tap_distance = 1280, 69 | altshift_taps_component.width = 10; 70 | 71 | 72 | endmodule 73 | 74 | // ============================================================ 75 | // CNX file retrieval info 76 | // ============================================================ 77 | // Retrieval info: PRIVATE: CLKEN NUMERIC "1" 78 | // Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1" 79 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 80 | // Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2" 81 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 82 | // Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280" 83 | // Retrieval info: PRIVATE: WIDTH NUMERIC "10" 84 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps" 85 | // Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2" 86 | // Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280" 87 | // Retrieval info: CONSTANT: WIDTH NUMERIC "10" 88 | // Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken 89 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 90 | // Retrieval info: USED_PORT: shiftin 0 0 10 0 INPUT NODEFVAL shiftin[9..0] 91 | // Retrieval info: USED_PORT: shiftout 0 0 10 0 OUTPUT NODEFVAL shiftout[9..0] 92 | // Retrieval info: USED_PORT: taps0x 0 0 10 0 OUTPUT NODEFVAL taps0x[9..0] 93 | // Retrieval info: USED_PORT: taps1x 0 0 10 0 OUTPUT NODEFVAL taps1x[9..0] 94 | // Retrieval info: CONNECT: @shiftin 0 0 10 0 shiftin 0 0 10 0 95 | // Retrieval info: CONNECT: shiftout 0 0 10 0 @shiftout 0 0 10 0 96 | // Retrieval info: CONNECT: taps0x 0 0 10 0 @taps 0 0 10 0 97 | // Retrieval info: CONNECT: taps1x 0 0 10 0 @taps 0 0 10 10 98 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 99 | // Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 100 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 101 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE 102 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE 103 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf FALSE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE 107 | -------------------------------------------------------------------------------- /DE2_CCD_smooth/Mirror_Col.v: -------------------------------------------------------------------------------- 1 | module Mirror_Col( // Input Side 2 | iCCD_R, 3 | iCCD_G, 4 | iCCD_B, 5 | iCCD_DVAL, 6 | iCCD_PIXCLK, 7 | iRST_N, 8 | // Output Side 9 | oCCD_R, 10 | oCCD_G, 11 | oCCD_B, 12 | oCCD_DVAL ); 13 | // Input Side 14 | input [9:0] iCCD_R; 15 | input [9:0] iCCD_G; 16 | input [9:0] iCCD_B; 17 | input iCCD_DVAL; 18 | input iCCD_PIXCLK; 19 | input iRST_N; 20 | // Output Side 21 | output [9:0] oCCD_R; 22 | output [9:0] oCCD_G; 23 | output [9:0] oCCD_B; 24 | output oCCD_DVAL; 25 | // Internal Registers 26 | reg [9:0] Z_Cont; 27 | reg mCCD_DVAL; 28 | 29 | assign oCCD_DVAL = mCCD_DVAL; 30 | 31 | always@(posedge iCCD_PIXCLK or negedge iRST_N) 32 | begin 33 | if(!iRST_N) 34 | begin 35 | mCCD_DVAL <= 0; 36 | Z_Cont <= 0; 37 | end 38 | else 39 | begin 40 | mCCD_DVAL <= iCCD_DVAL; 41 | if(Z_Cont<640) 42 | begin 43 | if(iCCD_DVAL) 44 | Z_Cont <= Z_Cont+1'b1; 45 | end 46 | else 47 | Z_Cont <= 0; 48 | end 49 | end 50 | 51 | Stack_RAM ( 52 | .clock(iCCD_PIXCLK), 53 | .data(iCCD_R), 54 | .rdaddress(639-Z_Cont), 55 | .wraddress(Z_Cont), 56 | .wren(iCCD_DVAL), 57 | .q(oCCD_R)); 58 | 59 | Stack_RAM ( 60 | .clock(iCCD_PIXCLK), 61 | .data(iCCD_G), 62 | .rdaddress(639-Z_Cont), 63 | .wraddress(Z_Cont), 64 | .wren(iCCD_DVAL), 65 | .q(oCCD_G)); 66 | 67 | Stack_RAM ( 68 | .clock(iCCD_PIXCLK), 69 | .data(iCCD_B), 70 | .rdaddress(639-Z_Cont), 71 | .wraddress(Z_Cont), 72 | .wren(iCCD_DVAL), 73 | .q(oCCD_B)); 74 | 75 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_smooth/RAW2RGB.v: -------------------------------------------------------------------------------- 1 | module RAW2RGB( oRed, 2 | oGreen, 3 | oBlue, 4 | oDVAL, 5 | iX_Cont, 6 | iY_Cont, 7 | iDATA, 8 | iDVAL, 9 | iCLK, 10 | iRST ); 11 | 12 | input [10:0] iX_Cont; 13 | input [10:0] iY_Cont; 14 | input [9:0] iDATA; 15 | input iDVAL; 16 | input iCLK; 17 | input iRST; 18 | output [9:0] oRed; 19 | output [9:0] oGreen; 20 | output [9:0] oBlue; 21 | output oDVAL; 22 | wire [9:0] mDATA_0; 23 | wire [9:0] mDATA_1; 24 | reg [9:0] mDATAd_0; 25 | reg [9:0] mDATAd_1; 26 | reg [9:0] mCCD_R; 27 | reg [10:0] mCCD_G; 28 | reg [9:0] mCCD_B; 29 | reg mDVAL; 30 | 31 | assign oRed = mCCD_R[9:0]; 32 | assign oGreen = mCCD_G[10:1]; 33 | assign oBlue = mCCD_B[9:0]; 34 | assign oDVAL = mDVAL; 35 | 36 | Line_Buffer u0 ( .clken(iDVAL), 37 | .clock(iCLK), 38 | .shiftin(iDATA), 39 | .taps0x(mDATA_1), 40 | .taps1x(mDATA_0) ); 41 | 42 | always@(posedge iCLK or negedge iRST) 43 | begin 44 | if(!iRST) 45 | begin 46 | mCCD_R <= 0; 47 | mCCD_G <= 0; 48 | mCCD_B <= 0; 49 | mDATAd_0<= 0; 50 | mDATAd_1<= 0; 51 | mDVAL <= 0; 52 | end 53 | else 54 | begin 55 | mDATAd_0 <= mDATA_0; 56 | mDATAd_1 <= mDATA_1; 57 | mDVAL <= {iY_Cont[0]|iX_Cont[0]} ? 1'b0 : iDVAL; 58 | if({iY_Cont[0],iX_Cont[0]}==2'b01) 59 | begin 60 | mCCD_R <= mDATA_0; 61 | mCCD_G <= mDATAd_0+mDATA_1; 62 | mCCD_B <= mDATAd_1; 63 | end 64 | else if({iY_Cont[0],iX_Cont[0]}==2'b00) 65 | begin 66 | mCCD_R <= mDATAd_0; 67 | mCCD_G <= mDATA_0+mDATAd_1; 68 | mCCD_B <= mDATA_1; 69 | end 70 | else if({iY_Cont[0],iX_Cont[0]}==2'b11) 71 | begin 72 | mCCD_R <= mDATA_1; 73 | mCCD_G <= mDATA_0+mDATAd_1; 74 | mCCD_B <= mDATAd_0; 75 | end 76 | else if({iY_Cont[0],iX_Cont[0]}==2'b10) 77 | begin 78 | mCCD_R <= mDATAd_1; 79 | mCCD_G <= mDATAd_0+mDATA_1; 80 | mCCD_B <= mDATA_0; 81 | end 82 | end 83 | end 84 | 85 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_smooth/RGB2Gray.v: -------------------------------------------------------------------------------- 1 | /* 2 | (C) OOMusou 2008 http://oomusou.cnblogs.com 3 | 4 | Filename : RGB2Gray.v 5 | Compiler : Quartus II 7.2 SP3 6 | Description : RGB to gray 7 | Release : 07/14/2008 1.0 8 | */ 9 | 10 | module RGB2Gray ( 11 | input clk, 12 | input rst_n, 13 | input [9:0] i_r, 14 | input [9:0] i_g, 15 | input [9:0] i_b, 16 | output reg [9:0] o_r, 17 | output reg [9:0] o_g, 18 | output reg [9:0] o_b 19 | ); 20 | 21 | always@(posedge clk or negedge rst_n) begin 22 | if (!rst_n) begin 23 | o_r <= {10{1'b0}}; 24 | o_g <= {10{1'b0}}; 25 | o_b <= {10{1'b0}}; 26 | end 27 | else begin 28 | o_r <= (i_r + i_g + i_b) / 3; 29 | o_g <= (i_r + i_g + i_b) / 3; 30 | o_b <= (i_r + i_g + i_b) / 3; 31 | end 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_smooth/Reset_Delay.v: -------------------------------------------------------------------------------- 1 | module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2); 2 | input iCLK; 3 | input iRST; 4 | output reg oRST_0; 5 | output reg oRST_1; 6 | output reg oRST_2; 7 | 8 | reg [21:0] Cont; 9 | 10 | always@(posedge iCLK or negedge iRST) 11 | begin 12 | if(!iRST) 13 | begin 14 | Cont <= 0; 15 | oRST_0 <= 0; 16 | oRST_1 <= 0; 17 | oRST_2 <= 0; 18 | end 19 | else 20 | begin 21 | if(Cont!=22'h3FFFFF) 22 | Cont <= Cont+1; 23 | if(Cont>=22'h1FFFFF) 24 | oRST_0 <= 1; 25 | if(Cont>=22'h2FFFFF) 26 | oRST_1 <= 1; 27 | if(Cont>=22'h3FFFFF) 28 | oRST_2 <= 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_smooth/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT ( oSEG,iDIG ); 2 | input [3:0] iDIG; 3 | output [6:0] oSEG; 4 | reg [6:0] oSEG; 5 | 6 | always @(iDIG) 7 | begin 8 | case(iDIG) 9 | 4'h1: oSEG = 7'b1111001; // ---t---- 10 | 4'h2: oSEG = 7'b0100100; // | | 11 | 4'h3: oSEG = 7'b0110000; // lt rt 12 | 4'h4: oSEG = 7'b0011001; // | | 13 | 4'h5: oSEG = 7'b0010010; // ---m---- 14 | 4'h6: oSEG = 7'b0000010; // | | 15 | 4'h7: oSEG = 7'b1111000; // lb rb 16 | 4'h8: oSEG = 7'b0000000; // | | 17 | 4'h9: oSEG = 7'b0011000; // ---b---- 18 | 4'ha: oSEG = 7'b0001000; 19 | 4'hb: oSEG = 7'b0000011; 20 | 4'hc: oSEG = 7'b1000110; 21 | 4'hd: oSEG = 7'b0100001; 22 | 4'he: oSEG = 7'b0000110; 23 | 4'hf: oSEG = 7'b0001110; 24 | 4'h0: oSEG = 7'b1000000; 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /DE2_CCD_smooth/SEG7_LUT_8.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG ); 2 | input [31:0] iDIG; 3 | output [6:0] oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7; 4 | 5 | SEG7_LUT u0 ( oSEG0,iDIG[3:0] ); 6 | SEG7_LUT u1 ( oSEG1,iDIG[7:4] ); 7 | SEG7_LUT u2 ( oSEG2,iDIG[11:8] ); 8 | SEG7_LUT u3 ( oSEG3,iDIG[15:12] ); 9 | SEG7_LUT u4 ( oSEG4,iDIG[19:16] ); 10 | SEG7_LUT u5 ( oSEG5,iDIG[23:20] ); 11 | SEG7_LUT u6 ( oSEG6,iDIG[27:24] ); 12 | SEG7_LUT u7 ( oSEG7,iDIG[31:28] ); 13 | 14 | endmodule -------------------------------------------------------------------------------- /DE2_CCD_smooth/Sdram_Control_4Port/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_smooth/Sdram_Control_4Port/control_interface.v: -------------------------------------------------------------------------------- 1 | module control_interface( 2 | CLK, 3 | RESET_N, 4 | CMD, 5 | ADDR, 6 | REF_ACK, 7 | INIT_ACK, 8 | CM_ACK, 9 | NOP, 10 | READA, 11 | WRITEA, 12 | REFRESH, 13 | PRECHARGE, 14 | LOAD_MODE, 15 | SADDR, 16 | REF_REQ, 17 | INIT_REQ, 18 | CMD_ACK 19 | ); 20 | 21 | `include "Sdram_Params.h" 22 | 23 | input CLK; // System Clock 24 | input RESET_N; // System Reset 25 | input [2:0] CMD; // Command input 26 | input [`ASIZE-1:0] ADDR; // Address 27 | input REF_ACK; // Refresh request acknowledge 28 | input INIT_ACK; // Initial request acknowledge 29 | input CM_ACK; // Command acknowledge 30 | output NOP; // Decoded NOP command 31 | output READA; // Decoded READA command 32 | output WRITEA; // Decoded WRITEA command 33 | output REFRESH; // Decoded REFRESH command 34 | output PRECHARGE; // Decoded PRECHARGE command 35 | output LOAD_MODE; // Decoded LOAD_MODE command 36 | output [`ASIZE-1:0] SADDR; // Registered version of ADDR 37 | output REF_REQ; // Hidden refresh request 38 | output INIT_REQ; // Hidden initial request 39 | output CMD_ACK; // Command acknowledge 40 | 41 | 42 | 43 | reg NOP; 44 | reg READA; 45 | reg WRITEA; 46 | reg REFRESH; 47 | reg PRECHARGE; 48 | reg LOAD_MODE; 49 | reg [`ASIZE-1:0] SADDR; 50 | reg REF_REQ; 51 | reg INIT_REQ; 52 | reg CMD_ACK; 53 | 54 | // Internal signals 55 | reg [15:0] timer; 56 | reg [15:0] init_timer; 57 | 58 | 59 | 60 | // Command decode and ADDR register 61 | always @(posedge CLK or negedge RESET_N) 62 | begin 63 | if (RESET_N == 0) 64 | begin 65 | NOP <= 0; 66 | READA <= 0; 67 | WRITEA <= 0; 68 | SADDR <= 0; 69 | end 70 | 71 | else 72 | begin 73 | 74 | SADDR <= ADDR; // register the address to keep proper 75 | // alignment with the command 76 | 77 | if (CMD == 3'b000) // NOP command 78 | NOP <= 1; 79 | else 80 | NOP <= 0; 81 | 82 | if (CMD == 3'b001) // READA command 83 | READA <= 1; 84 | else 85 | READA <= 0; 86 | 87 | if (CMD == 3'b010) // WRITEA command 88 | WRITEA <= 1; 89 | else 90 | WRITEA <= 0; 91 | 92 | end 93 | end 94 | 95 | 96 | // Generate CMD_ACK 97 | always @(posedge CLK or negedge RESET_N) 98 | begin 99 | if (RESET_N == 0) 100 | CMD_ACK <= 0; 101 | else 102 | if ((CM_ACK == 1) & (CMD_ACK == 0)) 103 | CMD_ACK <= 1; 104 | else 105 | CMD_ACK <= 0; 106 | end 107 | 108 | 109 | // refresh timer 110 | always @(posedge CLK or negedge RESET_N) begin 111 | if (RESET_N == 0) 112 | begin 113 | timer <= 0; 114 | REF_REQ <= 0; 115 | end 116 | else 117 | begin 118 | if (REF_ACK == 1) 119 | begin 120 | timer <= REF_PER; 121 | REF_REQ <=0; 122 | end 123 | else if (INIT_REQ == 1) 124 | begin 125 | timer <= REF_PER+200; 126 | REF_REQ <=0; 127 | end 128 | else 129 | timer <= timer - 1'b1; 130 | 131 | if (timer==0) 132 | REF_REQ <= 1; 133 | 134 | end 135 | end 136 | 137 | // initial timer 138 | always @(posedge CLK or negedge RESET_N) begin 139 | if (RESET_N == 0) 140 | begin 141 | init_timer <= 0; 142 | REFRESH <= 0; 143 | PRECHARGE <= 0; 144 | LOAD_MODE <= 0; 145 | INIT_REQ <= 0; 146 | end 147 | else 148 | begin 149 | if (init_timer < (INIT_PER+201)) 150 | init_timer <= init_timer+1; 151 | 152 | if (init_timer < INIT_PER) 153 | begin 154 | REFRESH <=0; 155 | PRECHARGE <=0; 156 | LOAD_MODE <=0; 157 | INIT_REQ <=1; 158 | end 159 | else if(init_timer == (INIT_PER+20)) 160 | begin 161 | REFRESH <=0; 162 | PRECHARGE <=1; 163 | LOAD_MODE <=0; 164 | INIT_REQ <=0; 165 | end 166 | else if( (init_timer == (INIT_PER+40)) || 167 | (init_timer == (INIT_PER+60)) || 168 | (init_timer == (INIT_PER+80)) || 169 | (init_timer == (INIT_PER+100)) || 170 | (init_timer == (INIT_PER+120)) || 171 | (init_timer == (INIT_PER+140)) || 172 | (init_timer == (INIT_PER+160)) || 173 | (init_timer == (INIT_PER+180)) ) 174 | begin 175 | REFRESH <=1; 176 | PRECHARGE <=0; 177 | LOAD_MODE <=0; 178 | INIT_REQ <=0; 179 | end 180 | else if(init_timer == (INIT_PER+200)) 181 | begin 182 | REFRESH <=0; 183 | PRECHARGE <=0; 184 | LOAD_MODE <=1; 185 | INIT_REQ <=0; 186 | end 187 | else 188 | begin 189 | REFRESH <=0; 190 | PRECHARGE <=0; 191 | LOAD_MODE <=0; 192 | INIT_REQ <=0; 193 | end 194 | end 195 | end 196 | 197 | endmodule 198 | 199 | -------------------------------------------------------------------------------- /DE2_CCD_smooth/Sdram_Control_4Port/sdr_data_path.v: -------------------------------------------------------------------------------- 1 | module sdr_data_path( 2 | CLK, 3 | RESET_N, 4 | DATAIN, 5 | DM, 6 | DQOUT, 7 | DQM 8 | ); 9 | 10 | `include "Sdram_Params.h" 11 | 12 | input CLK; // System Clock 13 | input RESET_N; // System Reset 14 | input [`DSIZE-1:0] DATAIN; // Data input from the host 15 | input [`DSIZE/8-1:0] DM; // byte data masks 16 | output [`DSIZE-1:0] DQOUT; 17 | output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs 18 | reg [`DSIZE/8-1:0] DQM; 19 | 20 | 21 | 22 | // Allign the input and output data to the SDRAM control path 23 | always @(posedge CLK or negedge RESET_N) 24 | begin 25 | if (RESET_N == 0) 26 | DQM <= `DSIZE/8-1'hF; 27 | else 28 | DQM <= DM; 29 | end 30 | 31 | assign DQOUT = DATAIN; 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /DE2_CCD_smooth/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 16 // Width of data bus to SDRAMS 14 | 15 | //parameter INIT_PER = 100; // For Simulation 16 | 17 | // Controller Parameter 18 | //////////// 133 MHz /////////////// 19 | /* 20 | parameter INIT_PER = 32000; 21 | parameter REF_PER = 1536; 22 | parameter SC_CL = 3; 23 | parameter SC_RCD = 3; 24 | parameter SC_RRD = 7; 25 | parameter SC_PM = 1; 26 | parameter SC_BL = 1; 27 | */ 28 | /////////////////////////////////////// 29 | //////////// 100 MHz /////////////// 30 | parameter INIT_PER = 24000; 31 | parameter REF_PER = 1024; 32 | parameter SC_CL = 3; 33 | parameter SC_RCD = 3; 34 | parameter SC_RRD = 7; 35 | parameter SC_PM = 1; 36 | parameter SC_BL = 1; 37 | /////////////////////////////////////// 38 | //////////// 50 MHz /////////////// 39 | /* 40 | parameter INIT_PER = 12000; 41 | parameter REF_PER = 512; 42 | parameter SC_CL = 3; 43 | parameter SC_RCD = 3; 44 | parameter SC_RRD = 7; 45 | parameter SC_PM = 1; 46 | parameter SC_BL = 1; 47 | */ 48 | /////////////////////////////////////// 49 | 50 | // SDRAM Parameter 51 | parameter SDR_BL = (SC_PM == 1)? 3'b111 : 52 | (SC_BL == 1)? 3'b000 : 53 | (SC_BL == 2)? 3'b001 : 54 | (SC_BL == 4)? 3'b010 : 55 | 3'b011 ; 56 | parameter SDR_BT = 1'b0; // Sequential 57 | // 1'b1: // Interteave 58 | parameter SDR_CL = (SC_CL == 2)? 3'b10: 59 | 3'b11; 60 | 61 | -------------------------------------------------------------------------------- /DE2_CCD_smooth/VGA_Controller.v: -------------------------------------------------------------------------------- 1 | module VGA_Controller( // Host Side 2 | iRed, 3 | iGreen, 4 | iBlue, 5 | oRequest, 6 | // VGA Side 7 | oVGA_R, 8 | oVGA_G, 9 | oVGA_B, 10 | oVGA_H_SYNC, 11 | oVGA_V_SYNC, 12 | oVGA_SYNC, 13 | oVGA_BLANK, 14 | oVGA_CLOCK, 15 | // Control Signal 16 | iCLK, 17 | iRST_N ); 18 | 19 | `include "VGA_Param.h" 20 | 21 | // Host Side 22 | input [9:0] iRed; 23 | input [9:0] iGreen; 24 | input [9:0] iBlue; 25 | output reg oRequest; 26 | // VGA Side 27 | output [9:0] oVGA_R; 28 | output [9:0] oVGA_G; 29 | output [9:0] oVGA_B; 30 | output reg oVGA_H_SYNC; 31 | output reg oVGA_V_SYNC; 32 | output oVGA_SYNC; 33 | output oVGA_BLANK; 34 | output oVGA_CLOCK; 35 | // Control Signal 36 | input iCLK; 37 | input iRST_N; 38 | 39 | // Internal Registers and Wires 40 | reg [9:0] H_Cont; 41 | reg [9:0] V_Cont; 42 | reg [9:0] Cur_Color_R; 43 | reg [9:0] Cur_Color_G; 44 | reg [9:0] Cur_Color_B; 45 | wire mCursor_EN; 46 | wire mRed_EN; 47 | wire mGreen_EN; 48 | wire mBlue_EN; 49 | 50 | assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC; 51 | assign oVGA_SYNC = 1'b0; 52 | assign oVGA_CLOCK = iCLK; 53 | 54 | assign oVGA_R = ( H_Cont>=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START && H_Cont=Y_START && V_Cont=X_START-2 && H_Cont=Y_START && V_Cont