├── eric_pearson-1 ├── vdf_portal_config.json ├── readme.txt.txt ├── msu │ ├── rtl │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── open_waves.tcl │ │ │ ├── update_pll.tcl │ │ │ ├── placer_constrs.xdc │ │ │ └── kernel.xml │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ └── full_adder.sv ├── .gitignore ├── build_readme.txt └── modular_square │ └── model │ └── vdf_basic.py ├── eric_pearson-2 ├── vdf_portal_config.json ├── readme.txt.txt ├── msu │ ├── rtl │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── open_waves.tcl │ │ │ ├── update_pll.tcl │ │ │ ├── placer_constrs.xdc │ │ │ └── kernel.xml │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ └── full_adder.sv ├── .gitignore ├── build_readme.txt └── modular_square │ └── model │ └── vdf_basic.py ├── andreas_brokalakis ├── vdf_portal_config.json ├── msu │ ├── rtl │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── placer_constrs.xdc │ │ │ ├── open_waves.tcl │ │ │ └── kernel.xml │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── submission_form.txt └── primitives │ └── rtl │ └── full_adder.sv ├── fpga_enthusiast-1 ├── vdf_portal_config.json ├── msu │ ├── rtl │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── placer_constrs.xdc │ │ │ ├── open_waves.tcl │ │ │ └── kernel.xml │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ ├── full_adder.sv │ │ └── full_adder_6.sv ├── .gitignore └── modular_square │ └── model │ └── vdf_basic.py ├── fpga_enthusiast-2 ├── vdf_portal_config.json ├── msu │ ├── rtl │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ ├── clk_wiz_0 │ │ │ │ │ ├── clk_wiz_0_board.xdc │ │ │ │ │ ├── clk_wiz_0.dcp │ │ │ │ │ ├── clk_wiz_0_stub.v │ │ │ │ │ └── clk_wiz_0_stub.vhdl │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── open_waves.tcl │ │ │ ├── placer_constrs.xdc │ │ │ ├── kernel.xml │ │ │ └── timing_constrs.xdc │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ ├── full_adder.sv │ │ └── full_adder_6.sv ├── .gitignore └── modular_square │ └── model │ └── vdf_basic.py ├── fpga_enthusiast-3 ├── vdf_portal_config.json ├── msu │ ├── rtl │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ ├── clk_wiz_0 │ │ │ │ │ ├── clk_wiz_0_board.xdc │ │ │ │ │ ├── clk_wiz_0.dcp │ │ │ │ │ ├── clk_wiz_0_stub.v │ │ │ │ │ └── clk_wiz_0_stub.vhdl │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── open_waves.tcl │ │ │ ├── placer_constrs.xdc │ │ │ ├── kernel.xml │ │ │ └── timing_constrs.xdc │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ ├── full_adder.sv │ │ └── full_adder_6.sv ├── .gitignore └── modular_square │ └── model │ └── vdf_basic.py ├── silicon_tailor-291 ├── vdf_portal_config.json ├── msu │ ├── rtl │ │ ├── vivado_metzgen │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ ├── msuconfig.vh │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ ├── awsver.txt │ │ │ ├── vivado.jou │ │ │ └── run_vivado.sh │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ ├── msuconfig.vh │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ ├── vivado.jou │ │ │ └── run_vivado.sh │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── open_waves.tcl │ │ │ ├── placer_constrs.xdc │ │ │ └── kernel.xml │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ └── full_adder.sv ├── .gitignore └── modular_square │ ├── model │ └── vdf_basic.py │ └── rtl │ ├── add3.sv │ └── bigadd3.sv ├── silicon_tailor-296 ├── vdf_portal_config.json ├── msu │ ├── rtl │ │ ├── vivado_metzgen │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ ├── msuconfig.vh │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ ├── awsver.txt │ │ │ └── vivado.jou │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ ├── msuconfig.vh │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── vivado.jou │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── open_waves.tcl │ │ │ ├── placer_constrs.xdc │ │ │ └── kernel.xml │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ └── full_adder.sv ├── .gitignore └── modular_square │ ├── model │ └── vdf_basic.py │ └── rtl │ ├── add3.sv │ └── bigadd3.sv ├── silicon_tailor-30 ├── vdf_portal_config.json ├── msu │ ├── rtl │ │ ├── vivado_metzgen │ │ │ ├── generate.sh │ │ │ ├── msu │ │ │ │ ├── msu.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ └── xsim.wdf │ │ │ │ ├── msu.ip_user_files │ │ │ │ │ └── README.txt │ │ │ │ ├── msu.hw │ │ │ │ │ └── msu.lpr │ │ │ │ ├── awsver.txt │ │ │ │ ├── vivado_28187.backup.jou │ │ │ │ ├── vivado_11163.backup.jou │ │ │ │ ├── vivado.jou │ │ │ │ ├── vivado_23167.backup.jou │ │ │ │ └── vivado_28187.backup.log │ │ │ ├── msu.srcs │ │ │ │ ├── msuconfig.vh │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ ├── awsver.txt │ │ │ └── vivado.jou │ │ ├── vivado_ozturk │ │ │ ├── generate.sh │ │ │ ├── msu │ │ │ │ ├── msu.cache │ │ │ │ │ └── wt │ │ │ │ │ │ ├── project.wpc │ │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ │ └── gui_handlers.wdf │ │ │ │ ├── msu.hw │ │ │ │ │ └── msu.lpr │ │ │ │ └── vivado.jou │ │ │ ├── msu.srcs │ │ │ │ ├── msuconfig.vh │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── vivado.jou │ │ ├── vivado_simple │ │ │ ├── generate.sh │ │ │ ├── msu.srcs │ │ │ │ └── constrs_1 │ │ │ │ │ └── new │ │ │ │ │ └── user.xdc │ │ │ └── run_vivado.sh │ │ ├── input_simple.vc │ │ ├── sdaccel │ │ │ ├── centos@54.146.87.226 │ │ │ ├── open_waves.tcl │ │ │ ├── placer_constrs.xdc │ │ │ └── kernel.xml │ │ └── input.vc │ ├── scripts │ │ ├── sdaccel_env.sh │ │ ├── simulation_setup.sh │ │ └── f1_setup.sh │ └── sw │ │ └── Config.h ├── docs │ ├── interface_timing.png │ ├── generate_modulus.md │ └── verilator.md ├── FPGA_Competition_Application_Form.pdf ├── FPGA_Competition_Official_Rules_and_Disclosures.pdf ├── primitives │ ├── README.md │ └── rtl │ │ └── full_adder.sv ├── .gitignore └── modular_square │ ├── model │ └── vdf_basic.py │ └── rtl │ ├── add3.sv │ └── bigadd3.sv └── geriatric_guys_with_gates ├── README.pdf ├── Kurt_Steve.jpg ├── msu ├── rtl │ ├── sdaccel │ │ ├── open_waves.tcl │ │ ├── placer_constrs.xdc │ │ └── kernel.xml │ └── input.vc ├── scripts │ ├── sdaccel_env.sh │ ├── simulation_setup.sh │ └── f1_setup.sh └── sw │ └── Config.h ├── submission_form.txt └── primitives ├── README.md └── rtl ├── full_adder.sv └── compressor_6_to_3_S_bit.sv /eric_pearson-1/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "liveness" 3 | } 4 | -------------------------------------------------------------------------------- /eric_pearson-2/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "liveness" 3 | } 4 | -------------------------------------------------------------------------------- /andreas_brokalakis/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "liveness" 3 | } 4 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "synthesis" 3 | } 4 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "synthesis" 3 | } 4 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "synthesis" 3 | } 4 | -------------------------------------------------------------------------------- /silicon_tailor-291/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "liveness" 3 | } 4 | -------------------------------------------------------------------------------- /silicon_tailor-296/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "liveness" 3 | } 4 | -------------------------------------------------------------------------------- /silicon_tailor-30/vdf_portal_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "target": "liveness" 3 | } 4 | -------------------------------------------------------------------------------- /eric_pearson-1/readme.txt.txt: -------------------------------------------------------------------------------- 1 | This is the starting repo for the 1K sqared modulus operation -------------------------------------------------------------------------------- /eric_pearson-2/readme.txt.txt: -------------------------------------------------------------------------------- 1 | This is the starting repo for the 1K sqared modulus operation -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_metzgen/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_metzgen/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_simple/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | vivado -source msu.tcl -mode batch 4 | 5 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/README.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/geriatric_guys_with_gates/README.pdf -------------------------------------------------------------------------------- /eric_pearson-1/docs/interface_timing.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/eric_pearson-1/docs/interface_timing.png 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-------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/input_simple.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/input_simple.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/input_simple.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . 3 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/input_simple.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . 3 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/input_simple.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . 3 | 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/silicon_tailor-296/FPGA_Competition_Application_Form.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/silicon_tailor-296/FPGA_Competition_Application_Form.pdf -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/msu.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c42617463684d6f6465:1 3 | 6d6f64655f636f756e7465727c4755494d6f6465:4 4 | eof: 5 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/msu/msu.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c42617463684d6f6465:1 3 | 6d6f64655f636f756e7465727c4755494d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr}]] 2 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj_hw_emu/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj_hw_emu/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr}]] 2 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj_hw_emu/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /eric_pearson-1/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/eric_pearson-1/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /eric_pearson-2/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/eric_pearson-2/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj_hw_emu/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj_hw_emu/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr}]] 2 | 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj_hw_emu/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/rtl/sdaccel/open_waves.tcl: -------------------------------------------------------------------------------- 1 | current_fileset 2 | open_wave_database obj/xilinx_aws-vu9p-f1-04261818_dynamic_5_0-0-vdf.hw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.wdb 3 | 4 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/msu.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/fpga_enthusiast-1/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /fpga_enthusiast-2/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/fpga_enthusiast-2/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /fpga_enthusiast-3/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/fpga_enthusiast-3/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr}]] 2 | -------------------------------------------------------------------------------- /silicon_tailor-291/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/silicon_tailor-291/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /silicon_tailor-296/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/silicon_tailor-296/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /silicon_tailor-30/FPGA_Competition_Official_Rules_and_Disclosures.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/silicon_tailor-30/FPGA_Competition_Official_Rules_and_Disclosures.pdf -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/fpga_enthusiast-2/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0.dcp -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/supranational/vdf-fpga-round1-results/HEAD/fpga_enthusiast-3/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0.dcp -------------------------------------------------------------------------------- /geriatric_guys_with_gates/submission_form.txt: -------------------------------------------------------------------------------- 1 | VDF FPGA Competition Submission Form 2 | 3 | Team name: Geriatric Guys with Gates 4 | Expected result (avg ns/square): 44.96ns 5 | Design documentation (below): see README.md file 6 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/msu/msu.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:31:00:00 3 | eof:3363954122 4 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/rtl/input.vc: -------------------------------------------------------------------------------- 1 | // This file typically lists flags required by a large project, e.g. include directories 2 | +librescan +libext+.v+.sv+.vh+.svh -y . -y ./obj_dir/mem -y ../../primitives/rtl -y ../rtl -y ../../modular_square/rtl 3 | -------------------------------------------------------------------------------- /eric_pearson-1/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /eric_pearson-2/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /silicon_tailor-291/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /silicon_tailor-296/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /silicon_tailor-30/docs/generate_modulus.md: -------------------------------------------------------------------------------- 1 | 2 | To generate a new RSA modulus: 3 | ``` 4 | openssl genrsa -out mykey.pem 1024 5 | openssl rsa -in mykey.pem -pubout > mykey.pub 6 | openssl rsa -pubin -modulus -noout -in mykey.pub 7 | rm mykey.pem 8 | rm mykey.pub 9 | ``` 10 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/sdaccel/update_pll.tcl: -------------------------------------------------------------------------------- 1 | set_property CLKFBOUT_MULT_F 8 [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/MMCME4_inst_] 2 | set_property CLKOUT0_DIVIDE_f 7.875 [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/MMCME4_inst_] 3 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/sdaccel/update_pll.tcl: -------------------------------------------------------------------------------- 1 | #set_property CLKFBOUT_MULT_F 7.875 [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/MMCME4_inst_] 2 | #set_property CLKOUT0_DIVIDE_f 7 [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/MMCME4_inst_] 3 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/msu.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | #add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr}]] 2 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] 3 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | #add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr}]] 2 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] 3 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr}]] 2 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_out_i1*}]] 3 | -------------------------------------------------------------------------------- /eric_pearson-1/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /eric_pearson-2/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /silicon_tailor-291/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /silicon_tailor-296/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/msu.hw/msu.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/msu/msu.hw/msu.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /silicon_tailor-30/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/primitives/README.md: -------------------------------------------------------------------------------- 1 | This repository contains low level arithmetic primitives in RTL that can be used for FPGA or ASIC based designs. 2 | 3 | Multiply is a fully parameterized polynomial multiplier with configurable polynomial degree and coefficient bit-width. 4 | 5 | These were created as part of the https://www.cryptophage.com/ project. 6 | -------------------------------------------------------------------------------- /andreas_brokalakis/submission_form.txt: -------------------------------------------------------------------------------- 1 | VDF FPGA Competition Submission Form 2 | 3 | To submit your design: 4 | - submit an official team entry form 5 | - fill in the fields below 6 | - create your final commit with git signoff: 7 | git commit -s -m "round 1 entry" 8 | - email your final repo + commit to hello@vdfalliance.org 9 | 10 | Team name: 11 | Expected result (avg ns/square): 24ns 12 | Design documentation (below): see the main README.md file 13 | 14 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_metzgen/msu.srcs/msuconfig.vh: -------------------------------------------------------------------------------- 1 | `define SQ_IN_BITS_DEF 1024 2 | `define SQ_OUT_BITS_DEF 1024 3 | `define MODULUS_DEF 1024'd124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 4 | `define MOD_LEN_DEF 1024 5 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_ozturk/msu.srcs/msuconfig.vh: -------------------------------------------------------------------------------- 1 | `define SQ_IN_BITS_DEF 1024 2 | `define SQ_OUT_BITS_DEF 2112 3 | `define MODULUS_DEF 1024'd124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 4 | `define MOD_LEN_DEF 1024 5 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_metzgen/msu.srcs/msuconfig.vh: -------------------------------------------------------------------------------- 1 | `define SQ_IN_BITS_DEF 1024 2 | `define SQ_OUT_BITS_DEF 1024 3 | `define MODULUS_DEF 1024'd124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 4 | `define MOD_LEN_DEF 1024 5 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_ozturk/msu.srcs/msuconfig.vh: -------------------------------------------------------------------------------- 1 | `define SQ_IN_BITS_DEF 1024 2 | `define SQ_OUT_BITS_DEF 2112 3 | `define MODULUS_DEF 1024'd124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 4 | `define MOD_LEN_DEF 1024 5 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu.srcs/msuconfig.vh: -------------------------------------------------------------------------------- 1 | `define SQ_IN_BITS_DEF 1024 2 | `define SQ_OUT_BITS_DEF 1024 3 | `define MODULUS_DEF 1024'd124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 4 | `define MOD_LEN_DEF 1024 5 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/msu.srcs/msuconfig.vh: -------------------------------------------------------------------------------- 1 | `define SQ_IN_BITS_DEF 1024 2 | `define SQ_OUT_BITS_DEF 2112 3 | `define MODULUS_DEF 1024'd124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 4 | `define MOD_LEN_DEF 1024 5 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/msu/msu.cache/wt/gui_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:34:00:00 5 | eof:1935755821 6 | -------------------------------------------------------------------------------- /silicon_tailor-291/.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Compiled Object files 5 | *.slo 6 | *.lo 7 | *.o 8 | *.obj 9 | 10 | # Precompiled Headers 11 | *.gch 12 | *.pch 13 | 14 | # Compiled Dynamic libraries 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files 20 | *.mod 21 | *.smod 22 | 23 | # Compiled Static libraries 24 | *.lai 25 | *.la 26 | *.a 27 | *.lib 28 | 29 | # Executables 30 | *.exe 31 | *.out 32 | *.app 33 | 34 | 35 | # Directories 36 | msu.runs/ 37 | msu.sim/ 38 | obj/ 39 | obj_hw_emu/ -------------------------------------------------------------------------------- /silicon_tailor-296/.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Compiled Object files 5 | *.slo 6 | *.lo 7 | *.o 8 | *.obj 9 | 10 | # Precompiled Headers 11 | *.gch 12 | *.pch 13 | 14 | # Compiled Dynamic libraries 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files 20 | *.mod 21 | *.smod 22 | 23 | # Compiled Static libraries 24 | *.lai 25 | *.la 26 | *.a 27 | *.lib 28 | 29 | # Executables 30 | *.exe 31 | *.out 32 | *.app 33 | 34 | 35 | # Directories 36 | msu.runs/ 37 | msu.sim/ 38 | obj/ 39 | obj_hw_emu/ -------------------------------------------------------------------------------- /silicon_tailor-30/.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Compiled Object files 5 | *.slo 6 | *.lo 7 | *.o 8 | *.obj 9 | 10 | # Precompiled Headers 11 | *.gch 12 | *.pch 13 | 14 | # Compiled Dynamic libraries 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files 20 | *.mod 21 | *.smod 22 | 23 | # Compiled Static libraries 24 | *.lai 25 | *.la 26 | *.a 27 | *.lib 28 | 29 | # Executables 30 | *.exe 31 | *.out 32 | *.app 33 | 34 | 35 | # Directories 36 | msu.runs/ 37 | msu.sim/ 38 | obj/ 39 | obj_hw_emu/ -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 5.848-name ap_clk [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_simple/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 10.000 -name ap_clk -waveform {0.000 5.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_metzgen/awsver.txt: -------------------------------------------------------------------------------- 1 | { 2 | "accountId" : "560945186992", 3 | "imageId" : "ami-0e560af290c745f5b", 4 | "availabilityZone" : "us-east-1f", 5 | "ramdiskId" : null, 6 | "kernelId" : null, 7 | "privateIp" : "172.31.85.248", 8 | "devpayProductCodes" : null, 9 | "marketplaceProductCodes" : [ "3sppv90yg5o5uyuw20at6ywak" ], 10 | "version" : "2017-09-30", 11 | "region" : "us-east-1", 12 | "pendingTime" : "2019-09-28T13:25:33Z", 13 | "architecture" : "x86_64", 14 | "billingProducts" : null, 15 | "instanceId" : "i-06e5fda09cdd2baab", 16 | "instanceType" : "z1d.2xlarge" 17 | } -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_metzgen/awsver.txt: -------------------------------------------------------------------------------- 1 | { 2 | "accountId" : "560945186992", 3 | "imageId" : "ami-0e560af290c745f5b", 4 | "availabilityZone" : "us-east-1f", 5 | "ramdiskId" : null, 6 | "kernelId" : null, 7 | "privateIp" : "172.31.85.248", 8 | "devpayProductCodes" : null, 9 | "marketplaceProductCodes" : [ "3sppv90yg5o5uyuw20at6ywak" ], 10 | "version" : "2017-09-30", 11 | "region" : "us-east-1", 12 | "pendingTime" : "2019-09-28T13:25:33Z", 13 | "architecture" : "x86_64", 14 | "billingProducts" : null, 15 | "instanceId" : "i-06e5fda09cdd2baab", 16 | "instanceType" : "z1d.2xlarge" 17 | } -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/awsver.txt: -------------------------------------------------------------------------------- 1 | { 2 | "accountId" : "560945186992", 3 | "imageId" : "ami-0e560af290c745f5b", 4 | "availabilityZone" : "us-east-1f", 5 | "ramdiskId" : null, 6 | "kernelId" : null, 7 | "privateIp" : "172.31.85.248", 8 | "devpayProductCodes" : null, 9 | "marketplaceProductCodes" : [ "3sppv90yg5o5uyuw20at6ywak" ], 10 | "version" : "2017-09-30", 11 | "region" : "us-east-1", 12 | "pendingTime" : "2019-09-28T13:25:33Z", 13 | "architecture" : "x86_64", 14 | "billingProducts" : null, 15 | "instanceId" : "i-06e5fda09cdd2baab", 16 | "instanceType" : "z1d.2xlarge" 17 | } -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/awsver.txt: -------------------------------------------------------------------------------- 1 | { 2 | "accountId" : "560945186992", 3 | "imageId" : "ami-0e560af290c745f5b", 4 | "availabilityZone" : "us-east-1f", 5 | "ramdiskId" : null, 6 | "kernelId" : null, 7 | "privateIp" : "172.31.85.248", 8 | "devpayProductCodes" : null, 9 | "marketplaceProductCodes" : [ "3sppv90yg5o5uyuw20at6ywak" ], 10 | "version" : "2017-09-30", 11 | "region" : "us-east-1", 12 | "pendingTime" : "2019-09-28T13:25:33Z", 13 | "architecture" : "x86_64", 14 | "billingProducts" : null, 15 | "instanceId" : "i-06e5fda09cdd2baab", 16 | "instanceType" : "z1d.2xlarge" 17 | } -------------------------------------------------------------------------------- /eric_pearson-1/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/scripts/sdaccel_env.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # source this script to setup the environment F1 development 4 | 5 | hostname|grep ec2 > /dev/null 6 | if [ $? == 0 ] 7 | then 8 | echo "Setting up the an EC2 environment..." 9 | 10 | else 11 | echo "Setting up an on-premise environment..." 12 | 13 | export XILINX_SDX=/tools/Xilinx/SDx/2018.3 14 | PATH=$PATH:$XILINX_SDX/bin 15 | export AWS_FPGA_REPO_DIR=~/src/project_data/aws-fpga 16 | fi 17 | 18 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR 19 | pushd $AWS_FPGA_REPO_DIR 20 | 21 | # The following will require sudo 22 | source sdaccel_setup.sh 23 | 24 | popd 25 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_iter}]] 2 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR1] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_post}]] 3 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/i_vdfpll}]] 4 | 5 | 6 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] 7 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_iter}]] 2 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR1] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_post}]] 3 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/i_vdfpll}]] 4 | 5 | 6 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] 7 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/sdaccel/placer_constrs.xdc: -------------------------------------------------------------------------------- 1 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_iter}]] 2 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR1] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_post}]] 3 | add_cells_to_pblock [get_pblocks pblock_dynamic_SLR2] [get_cells [list {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/modsqr/i_vdfpll}]] 4 | 5 | 6 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] 7 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_ozturk/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Fri Aug 30 18:16:27 2019 6 | # Process ID: 9492 7 | # Current directory: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk 8 | # Command line: vivado -source msu.tcl -mode batch 9 | # Log file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/vivado.log 10 | # Journal file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/vivado.jou 11 | #----------------------------------------------------------- 12 | source msu.tcl 13 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_ozturk/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Fri Aug 30 18:16:27 2019 6 | # Process ID: 9492 7 | # Current directory: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk 8 | # Command line: vivado -source msu.tcl -mode batch 9 | # Log file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/vivado.log 10 | # Journal file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/vivado.jou 11 | #----------------------------------------------------------- 12 | source msu.tcl 13 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Fri Aug 30 18:16:27 2019 6 | # Process ID: 9492 7 | # Current directory: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk 8 | # Command line: vivado -source msu.tcl -mode batch 9 | # Log file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/vivado.log 10 | # Journal file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/vivado.jou 11 | #----------------------------------------------------------- 12 | source msu.tcl 13 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_metzgen/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sat Sep 28 16:30:03 2019 6 | # Process ID: 27983 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen 8 | # Command line: vivado -source msu.tcl -mode batch 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/vivado.jou 11 | #----------------------------------------------------------- 12 | source msu.tcl 13 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_metzgen/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sat Sep 28 16:30:03 2019 6 | # Process ID: 27983 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen 8 | # Command line: vivado -source msu.tcl -mode batch 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/vivado.jou 11 | #----------------------------------------------------------- 12 | source msu.tcl 13 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sat Sep 28 16:30:03 2019 6 | # Process ID: 27983 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen 8 | # Command line: vivado -source msu.tcl -mode batch 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/vivado.jou 11 | #----------------------------------------------------------- 12 | source msu.tcl 13 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/scripts/simulation_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | grep Ubuntu /etc/os-release > /dev/null 4 | if [ $? == 0 ] 5 | then 6 | # Ubuntu 7 | echo "Running Ubuntu setup..." 8 | 9 | sudo apt update -y 10 | sudo apt install -y python3 libgmp-dev gtkwave 11 | 12 | wget https://www.veripool.org/ftp/verilator-4.016.tgz 13 | sudo apt-get install -y make autoconf g++ flex bison 14 | tar xvzf verilator*.t*gz 15 | cd verilator-4.016/ 16 | ./configure 17 | make -j 4 18 | sudo make install 19 | 20 | else 21 | # Assume CentOS 22 | echo "Running CentOS setup..." 23 | sudo yum update -y 24 | sudo yum install -y gmp-devel verilator python36 gtkwave 25 | fi 26 | 27 | export PATH=/tools/Xilinx/Vivado/2018.3/bin:$PATH 28 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/vivado_28187.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sat Sep 28 16:30:40 2019 6 | # Process ID: 28187 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu 8 | # Command line: vivado msu.xpr 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project msu.xpr 14 | update_compile_order -fileset sources_1 15 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_ozturk/msu/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3 (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Fri Aug 30 18:16:44 2019 6 | # Process ID: 9541 7 | # Current directory: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/msu 8 | # Command line: vivado msu.xpr 9 | # Log file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/msu/vivado.log 10 | # Journal file: /home/pmetzgen/vdf-fpga-metzgen/msu/rtl/vivado_ozturk/msu/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project msu.xpr 14 | update_compile_order -fileset sources_1 15 | synth_design -rtl -name rtl_1 16 | -------------------------------------------------------------------------------- /eric_pearson-1/.gitignore: -------------------------------------------------------------------------------- 1 | **~ 2 | **__pycache__ 3 | **logs 4 | **obj_dir 5 | **obj 6 | **\.dat 7 | **msuconfig.vh 8 | 9 | **vivado_*backup.jou 10 | **vivado_*backup.log 11 | **vivado.jou 12 | **vivado.log 13 | **vivado_pid*.str 14 | 15 | msu/rtl/vivado_ozturk/msu 16 | msu/rtl/vivado_ozturk/test.txt 17 | msu/rtl/vivado_ozturk/msu.cache 18 | msu/rtl/vivado_ozturk/msu.hw 19 | msu/rtl/vivado_ozturk/msu.ip_user_files 20 | msu/rtl/vivado_ozturk/msu.runs 21 | msu/rtl/vivado_ozturk/msu.srcs/mem 22 | msu/rtl/vivado_ozturk/msu.sim 23 | 24 | msu/rtl/vivado_simple/msu 25 | msu/rtl/vivado_simple/test.txt 26 | msu/rtl/vivado_simple/msu.cache 27 | msu/rtl/vivado_simple/msu.hw 28 | msu/rtl/vivado_simple/msu.ip_user_files 29 | msu/rtl/vivado_simple/msu.runs 30 | msu/rtl/vivado_simple/msu.srcs/mem 31 | msu/rtl/vivado_simple/msu.sim 32 | -------------------------------------------------------------------------------- /eric_pearson-2/.gitignore: -------------------------------------------------------------------------------- 1 | **~ 2 | **__pycache__ 3 | **logs 4 | **obj_dir 5 | **obj 6 | **\.dat 7 | **msuconfig.vh 8 | 9 | **vivado_*backup.jou 10 | **vivado_*backup.log 11 | **vivado.jou 12 | **vivado.log 13 | **vivado_pid*.str 14 | 15 | msu/rtl/vivado_ozturk/msu 16 | msu/rtl/vivado_ozturk/test.txt 17 | msu/rtl/vivado_ozturk/msu.cache 18 | msu/rtl/vivado_ozturk/msu.hw 19 | msu/rtl/vivado_ozturk/msu.ip_user_files 20 | msu/rtl/vivado_ozturk/msu.runs 21 | msu/rtl/vivado_ozturk/msu.srcs/mem 22 | msu/rtl/vivado_ozturk/msu.sim 23 | 24 | msu/rtl/vivado_simple/msu 25 | msu/rtl/vivado_simple/test.txt 26 | msu/rtl/vivado_simple/msu.cache 27 | msu/rtl/vivado_simple/msu.hw 28 | msu/rtl/vivado_simple/msu.ip_user_files 29 | msu/rtl/vivado_simple/msu.runs 30 | msu/rtl/vivado_simple/msu.srcs/mem 31 | msu/rtl/vivado_simple/msu.sim 32 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/.gitignore: -------------------------------------------------------------------------------- 1 | **~ 2 | **__pycache__ 3 | **logs 4 | **obj_dir 5 | **obj 6 | **\.dat 7 | **msuconfig.vh 8 | 9 | **vivado_*backup.jou 10 | **vivado_*backup.log 11 | **vivado.jou 12 | **vivado.log 13 | **vivado_pid*.str 14 | 15 | msu/rtl/vivado_ozturk/msu 16 | msu/rtl/vivado_ozturk/test.txt 17 | msu/rtl/vivado_ozturk/msu.cache 18 | msu/rtl/vivado_ozturk/msu.hw 19 | msu/rtl/vivado_ozturk/msu.ip_user_files 20 | msu/rtl/vivado_ozturk/msu.runs 21 | msu/rtl/vivado_ozturk/msu.srcs/mem 22 | msu/rtl/vivado_ozturk/msu.sim 23 | 24 | msu/rtl/vivado_simple/msu 25 | msu/rtl/vivado_simple/test.txt 26 | msu/rtl/vivado_simple/msu.cache 27 | msu/rtl/vivado_simple/msu.hw 28 | msu/rtl/vivado_simple/msu.ip_user_files 29 | msu/rtl/vivado_simple/msu.runs 30 | msu/rtl/vivado_simple/msu.srcs/mem 31 | msu/rtl/vivado_simple/msu.sim 32 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/.gitignore: -------------------------------------------------------------------------------- 1 | **~ 2 | **__pycache__ 3 | **logs 4 | **obj_dir 5 | **obj 6 | **\.dat 7 | **msuconfig.vh 8 | 9 | **vivado_*backup.jou 10 | **vivado_*backup.log 11 | **vivado.jou 12 | **vivado.log 13 | **vivado_pid*.str 14 | 15 | msu/rtl/vivado_ozturk/msu 16 | msu/rtl/vivado_ozturk/test.txt 17 | msu/rtl/vivado_ozturk/msu.cache 18 | msu/rtl/vivado_ozturk/msu.hw 19 | msu/rtl/vivado_ozturk/msu.ip_user_files 20 | msu/rtl/vivado_ozturk/msu.runs 21 | msu/rtl/vivado_ozturk/msu.srcs/mem 22 | msu/rtl/vivado_ozturk/msu.sim 23 | 24 | msu/rtl/vivado_simple/msu 25 | msu/rtl/vivado_simple/test.txt 26 | msu/rtl/vivado_simple/msu.cache 27 | msu/rtl/vivado_simple/msu.hw 28 | msu/rtl/vivado_simple/msu.ip_user_files 29 | msu/rtl/vivado_simple/msu.runs 30 | msu/rtl/vivado_simple/msu.srcs/mem 31 | msu/rtl/vivado_simple/msu.sim 32 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/.gitignore: -------------------------------------------------------------------------------- 1 | **~ 2 | **__pycache__ 3 | **logs 4 | **obj_dir 5 | **obj 6 | **\.dat 7 | **msuconfig.vh 8 | 9 | **vivado_*backup.jou 10 | **vivado_*backup.log 11 | **vivado.jou 12 | **vivado.log 13 | **vivado_pid*.str 14 | 15 | msu/rtl/vivado_ozturk/msu 16 | msu/rtl/vivado_ozturk/test.txt 17 | msu/rtl/vivado_ozturk/msu.cache 18 | msu/rtl/vivado_ozturk/msu.hw 19 | msu/rtl/vivado_ozturk/msu.ip_user_files 20 | msu/rtl/vivado_ozturk/msu.runs 21 | msu/rtl/vivado_ozturk/msu.srcs/mem 22 | msu/rtl/vivado_ozturk/msu.sim 23 | 24 | msu/rtl/vivado_simple/msu 25 | msu/rtl/vivado_simple/test.txt 26 | msu/rtl/vivado_simple/msu.cache 27 | msu/rtl/vivado_simple/msu.hw 28 | msu/rtl/vivado_simple/msu.ip_user_files 29 | msu/rtl/vivado_simple/msu.runs 30 | msu/rtl/vivado_simple/msu.srcs/mem 31 | msu/rtl/vivado_simple/msu.sim 32 | -------------------------------------------------------------------------------- /eric_pearson-1/build_readme.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Copyright 2019 Eric Pearson 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | ################################################################################ 16 | 17 | `define BUILD_NUMBER F031 18 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /eric_pearson-2/build_readme.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Copyright 2019 Eric Pearson 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | ################################################################################ 16 | 17 | `define BUILD_NUMBER F033 18 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_metzgen/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | # This works 3 | #create_clock -period 29.0 -name ap_clk -waveform {0.000 14.5} [get_ports ap_clk] 4 | 5 | # Requires 125MHz clock 6 | create_clock -period 8.0 -name ap_clk -waveform {0.000 4.0} [get_ports ap_clk] 7 | 8 | create_pblock sl_exclusion 9 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 10 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 11 | create_pblock SLR2 12 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_iter]] 13 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 14 | 15 | #set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] -------------------------------------------------------------------------------- /silicon_tailor-291/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_metzgen/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | # This works 3 | #create_clock -period 29.0 -name ap_clk -waveform {0.000 14.5} [get_ports ap_clk] 4 | 5 | # Requires 125MHz clock 6 | create_clock -period 8.0 -name ap_clk -waveform {0.000 4.0} [get_ports ap_clk] 7 | 8 | create_pblock sl_exclusion 9 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 10 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 11 | create_pblock SLR2 12 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_iter]] 13 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 14 | 15 | #set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] -------------------------------------------------------------------------------- /silicon_tailor-296/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | # This works 3 | #create_clock -period 29.0 -name ap_clk -waveform {0.000 14.5} [get_ports ap_clk] 4 | 5 | # Requires 125MHz clock 6 | create_clock -period 8.0 -name ap_clk -waveform {0.000 4.0} [get_ports ap_clk] 7 | 8 | create_pblock sl_exclusion 9 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 10 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 11 | create_pblock SLR2 12 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr/modsqr/i_modsqr_iter]] 13 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 14 | 15 | #set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] -------------------------------------------------------------------------------- /silicon_tailor-30/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/scripts/f1_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run this script to setup newly instantiated hosts 4 | 5 | # Install simulation dependencies 6 | sudo yum update -y 7 | sudo yum install -y gmp-devel verilator python36 8 | 9 | # Install the aws-fpga repo 10 | git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR; 11 | cd $AWS_FPGA_REPO_DIR && git pull; 12 | source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh 13 | 14 | # Install VNC (optional, but provides a richer working environment) 15 | sudo yum -y install tigervnc-server tigervnc-server-minimal 16 | sudo yum -y groupinstall X11 17 | sudo yum --enablerepo=epel -y groups install "Xfce" 18 | sudo yum -y install kdiff3 19 | sudo yum -y install emacs 20 | 21 | cd 22 | mkdir .vnc 23 | cd .vnc 24 | cat < xstartup 25 | #!/bin/bash 26 | startxfce4 & 27 | EOF 28 | chmod +x xstartup 29 | 30 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 8.000 -name ap_clk -waveform {0.000 4.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | 11 | #set_false_path -from [get_clocks -of_objects [get_pins inst_wrapper/inst_kernel/msu/squarer_mmcm/inst/mmcme4_adv_inst/CLKOUT0]] -to [get_clocks ap_clk] 12 | #set_false_path -from [get_clocks ap_clk] -to [get_clocks -of_objects [get_pins inst_wrapper/inst_kernel/msu/squarer_mmcm/inst/mmcme4_adv_inst/CLKOUT0]] 13 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_ozturk/msu.srcs/constrs_1/new/user.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 8.000 -name ap_clk -waveform {0.000 4.000} [get_ports ap_clk] 3 | 4 | create_pblock sl_exclusion 5 | resize_pblock [get_pblocks sl_exclusion] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y9} 6 | set_property EXCLUDE_PLACEMENT 1 [get_pblocks sl_exclusion] 7 | create_pblock SLR2 8 | add_cells_to_pblock [get_pblocks SLR2] [get_cells -quiet [list inst_wrapper/inst_kernel/msu/modsqr/modsqr]] 9 | resize_pblock [get_pblocks SLR2] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 10 | 11 | #set_false_path -from [get_clocks -of_objects [get_pins inst_wrapper/inst_kernel/msu/squarer_mmcm/inst/mmcme4_adv_inst/CLKOUT0]] -to [get_clocks ap_clk] 12 | #set_false_path -from [get_clocks ap_clk] -to [get_clocks -of_objects [get_pins inst_wrapper/inst_kernel/msu/squarer_mmcm/inst/mmcme4_adv_inst/CLKOUT0]] 13 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_simple/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | export MOD_LEN=1024 7 | export SIMPLE_SQ=1 8 | MODEL=msu 9 | 10 | # Set current directory to the location of this script 11 | SCRIPT=$(dirname "$0") 12 | SCRIPTPATH=$(realpath "$SCRIPT") 13 | cd $SCRIPTPATH 14 | 15 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 16 | # (why is there no way to configure the vivado include path?) 17 | rm -f ../msuconfig.vh 18 | 19 | # Generate a test 20 | ../gen_test.py -c -s $MOD_LEN 21 | 22 | # Generate the Vivado project 23 | if [ ! -d msu ]; then 24 | echo "Generating vivado project" 25 | ./generate.sh 26 | fi 27 | 28 | # Update the project directory to the current dir 29 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 30 | #mv $MODEL.xpr_new $MODEL.xpr 31 | 32 | cd msu 33 | vivado $MODEL.xpr & 34 | -------------------------------------------------------------------------------- /eric_pearson-1/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | # t should be small for testing purposes. 15 | # For the final FPGA runs, t will be 2^30 16 | t = NUM_ITERATIONS 17 | 18 | # Iterative modular squaring t times 19 | # This is the function that needs to be optimized on FPGA 20 | for _ in range(t): 21 | x = (x * x) % N 22 | 23 | # Final result is a 1024b value 24 | h = x 25 | print(h) 26 | -------------------------------------------------------------------------------- /eric_pearson-2/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | # t should be small for testing purposes. 15 | # For the final FPGA runs, t will be 2^30 16 | t = NUM_ITERATIONS 17 | 18 | # Iterative modular squaring t times 19 | # This is the function that needs to be optimized on FPGA 20 | for _ in range(t): 21 | x = (x * x) % N 22 | 23 | # Final result is a 1024b value 24 | h = x 25 | print(h) 26 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | # t should be small for testing purposes. 15 | # For the final FPGA runs, t will be 2^30 16 | t = NUM_ITERATIONS 17 | 18 | # Iterative modular squaring t times 19 | # This is the function that needs to be optimized on FPGA 20 | for _ in range(t): 21 | x = (x * x) % N 22 | 23 | # Final result is a 1024b value 24 | h = x 25 | print(h) 26 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | # t should be small for testing purposes. 15 | # For the final FPGA runs, t will be 2^30 16 | t = NUM_ITERATIONS 17 | 18 | # Iterative modular squaring t times 19 | # This is the function that needs to be optimized on FPGA 20 | for _ in range(t): 21 | x = (x * x) % N 22 | 23 | # Final result is a 1024b value 24 | h = x 25 | print(h) 26 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | # t should be small for testing purposes. 15 | # For the final FPGA runs, t will be 2^30 16 | t = NUM_ITERATIONS 17 | 18 | # Iterative modular squaring t times 19 | # This is the function that needs to be optimized on FPGA 20 | for _ in range(t): 21 | x = (x * x) % N 22 | 23 | # Final result is a 1024b value 24 | h = x 25 | print(h) 26 | -------------------------------------------------------------------------------- /silicon_tailor-30/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | 15 | # Dump all 2^i mod M values 16 | for i in range(1020, 2048, 1): 17 | print(i, " 0x", (hex(pow(2, i) % N))[2:].zfill(256), sep='') 18 | 19 | 20 | # t should be small for testing purposes. 21 | # For the final FPGA runs, t will be 2^30 22 | t = NUM_ITERATIONS 23 | 24 | # Iterative modular squaring t times 25 | # This is the function that needs to be optimized on FPGA 26 | for _ in range(t): 27 | x = (x * x) % N 28 | 29 | # Final result is a 1024b value 30 | h = x 31 | print(h) 32 | -------------------------------------------------------------------------------- /silicon_tailor-291/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | 15 | # Dump all 2^i mod M values 16 | for i in range(1020, 2048, 1): 17 | print(i, " 0x", (hex(pow(2, i) % N))[2:].zfill(256), sep='') 18 | 19 | 20 | # t should be small for testing purposes. 21 | # For the final FPGA runs, t will be 2^30 22 | t = NUM_ITERATIONS 23 | 24 | # Iterative modular squaring t times 25 | # This is the function that needs to be optimized on FPGA 26 | for _ in range(t): 27 | x = (x * x) % N 28 | 29 | # Final result is a 1024b value 30 | h = x 31 | print(h) 32 | -------------------------------------------------------------------------------- /silicon_tailor-296/modular_square/model/vdf_basic.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | from random import getrandbits 4 | 5 | # Competition is for 1024 bits 6 | NUM_BITS = 1024 7 | 8 | NUM_ITERATIONS = 1000 9 | 10 | # Rather than being random each time, we will provide randomly generated values 11 | x = getrandbits(NUM_BITS) 12 | N = 124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331 13 | 14 | 15 | # Dump all 2^i mod M values 16 | for i in range(1020, 2048, 1): 17 | print(i, " 0x", (hex(pow(2, i) % N))[2:].zfill(256), sep='') 18 | 19 | 20 | # t should be small for testing purposes. 21 | # For the final FPGA runs, t will be 2^30 22 | t = NUM_ITERATIONS 23 | 24 | # Iterative modular squaring t times 25 | # This is the function that needs to be optimized on FPGA 26 | for _ in range(t): 27 | x = (x * x) % N 28 | 29 | # Final result is a 1024b value 30 | h = x 31 | print(h) 32 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/rtl/sdaccel/kernel.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/vivado_11163.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sun Sep 29 15:22:21 2019 6 | # Process ID: 11163 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu 8 | # Command line: vivado msu.xpr 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project msu.xpr 14 | update_compile_order -fileset sources_1 15 | reset_run synth_1 16 | launch_runs impl_1 -jobs 4 17 | wait_on_run impl_1 18 | open_run impl_1 19 | report_utilization -name utilization_1 20 | close_design 21 | launch_simulation 22 | open_wave_config /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/tb_behav.wcfg 23 | source tb.tcl 24 | close_sim 25 | launch_simulation 26 | open_wave_config /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/tb_behav.wcfg 27 | source tb.tcl 28 | run all 29 | save_wave_config {/home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/tb_behav.wcfg} 30 | close_sim 31 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 4 | // Date : Sun Sep 29 17:13:08 2019 5 | // Host : dorian-VirtualBox running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/dorian/src/vdf-competition/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.v 8 | // Design : clk_wiz_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xcvu9p-fsgd2104-2L-e 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module clk_wiz_0(clk_out1, reset, locked, clk_in1) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */; 18 | output clk_out1; 19 | input reset; 20 | output locked; 21 | input clk_in1; 22 | endmodule 23 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 4 | // Date : Sun Sep 29 17:13:08 2019 5 | // Host : dorian-VirtualBox running 64-bit Ubuntu 16.04.6 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/dorian/src/vdf-competition/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.v 8 | // Design : clk_wiz_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xcvu9p-fsgd2104-2L-e 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module clk_wiz_0(clk_out1, reset, locked, clk_in1) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */; 18 | output clk_out1; 19 | input reset; 20 | output locked; 21 | input clk_in1; 22 | endmodule 23 | -------------------------------------------------------------------------------- /eric_pearson-1/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /eric_pearson-2/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /andreas_brokalakis/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /silicon_tailor-291/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /silicon_tailor-296/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /silicon_tailor-30/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 4 | -- Date : Sun Sep 29 17:13:08 2019 5 | -- Host : dorian-VirtualBox running 64-bit Ubuntu 16.04.6 LTS 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- /home/dorian/src/vdf-competition/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.vhdl 8 | -- Design : clk_wiz_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xcvu9p-fsgd2104-2L-e 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity clk_wiz_0 is 16 | Port ( 17 | clk_out1 : out STD_LOGIC; 18 | reset : in STD_LOGIC; 19 | locked : out STD_LOGIC; 20 | clk_in1 : in STD_LOGIC 21 | ); 22 | 23 | end clk_wiz_0; 24 | 25 | architecture stub of clk_wiz_0 is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 4 | -- Date : Sun Sep 29 17:13:08 2019 5 | -- Host : dorian-VirtualBox running 64-bit Ubuntu 16.04.6 LTS 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- /home/dorian/src/vdf-competition/msu/rtl/vivado_ozturk/msu.srcs/clk_wiz_0/clk_wiz_0_stub.vhdl 8 | -- Design : clk_wiz_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xcvu9p-fsgd2104-2L-e 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity clk_wiz_0 is 16 | Port ( 17 | clk_out1 : out STD_LOGIC; 18 | reset : in STD_LOGIC; 19 | locked : out STD_LOGIC; 20 | clk_in1 : in STD_LOGIC 21 | ); 22 | 23 | end clk_wiz_0; 24 | 25 | architecture stub of clk_wiz_0 is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/primitives/rtl/full_adder.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic Cin, 32 | output logic Cout, 33 | output logic S 34 | ); 35 | 36 | always_comb begin 37 | S = A ^ B ^ Cin; 38 | Cout = (A & B) | (Cin & (A ^ B)); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /silicon_tailor-291/modular_square/rtl/add3.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Silicon Tailor Ltd 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | `timescale 1 ns / 1 ns 18 | 19 | module add3 20 | #( 21 | parameter int N = 32 22 | ) 23 | ( 24 | input logic [N-1:0] a_in, 25 | input logic [N-1:0] b_in, 26 | input logic [N-1:0] c_in, 27 | input logic carry_in, 28 | output logic [N+1:0] sum_out 29 | ); 30 | 31 | 32 | logic [N+1:0] sums; 33 | logic [N+1:0] carrys; 34 | 35 | assign sums = { 2'b0, a_in ^ b_in ^ c_in }; 36 | assign carrys = { 1'b0, (a_in & b_in) | (a_in & c_in) | (b_in & c_in), carry_in }; 37 | 38 | assign sum_out = sums + carrys; 39 | 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /silicon_tailor-296/modular_square/rtl/add3.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Silicon Tailor Ltd 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | `timescale 1 ns / 1 ns 18 | 19 | module add3 20 | #( 21 | parameter int N = 32 22 | ) 23 | ( 24 | input logic [N-1:0] a_in, 25 | input logic [N-1:0] b_in, 26 | input logic [N-1:0] c_in, 27 | input logic carry_in, 28 | output logic [N+1:0] sum_out 29 | ); 30 | 31 | 32 | logic [N+1:0] sums; 33 | logic [N+1:0] carrys; 34 | 35 | assign sums = { 2'b0, a_in ^ b_in ^ c_in }; 36 | assign carrys = { 1'b0, (a_in & b_in) | (a_in & c_in) | (b_in & c_in), carry_in }; 37 | 38 | assign sum_out = sums + carrys; 39 | 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /silicon_tailor-30/modular_square/rtl/add3.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Silicon Tailor Ltd 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | `timescale 1 ns / 1 ns 18 | 19 | module add3 20 | #( 21 | parameter int N = 32 22 | ) 23 | ( 24 | input logic [N-1:0] a_in, 25 | input logic [N-1:0] b_in, 26 | input logic [N-1:0] c_in, 27 | input logic carry_in, 28 | output logic [N+1:0] sum_out 29 | ); 30 | 31 | 32 | logic [N+1:0] sums; 33 | logic [N+1:0] carrys; 34 | 35 | assign sums = { 2'b0, a_in ^ b_in ^ c_in }; 36 | assign carrys = { 1'b0, (a_in & b_in) | (a_in & c_in) | (b_in & c_in), carry_in }; 37 | 38 | assign sum_out = sums + carrys; 39 | 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /eric_pearson-1/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /eric_pearson-2/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /silicon_tailor-291/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /silicon_tailor-296/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /silicon_tailor-30/docs/verilator.md: -------------------------------------------------------------------------------- 1 | # Verilator 2 | 3 | The Ozturk design supports verilator as a simulator. 4 | 5 | While we're big fans of verilator, it unfortunately doesn't support 1024 bit modular squaring using * and %. As a result the default bitwidth for this design when using verilator is 128 bits. We found it can also be finicky with large bitwidths. Unpacked arrays of smaller words seems more stable. 6 | 7 | Enabling verilator takes just a few steps on Ubuntu 18 and AWS F1 CentOS. The setup script requires sudo access to install dependencies. 8 | 9 | ``` 10 | # Install dependencies 11 | ./msu/scripts/simulation_setup.sh 12 | 13 | # Run simulations for both designs 14 | cd msu 15 | make 16 | ``` 17 | 18 | The verilator testbench instantiates the MSU portion of the design as well as the squarer circuit. The MSU interfaces to the SDAccel interfaces and provides control to count the number iterations, capture the result, and send it back to the host driver. 19 | 20 | Simulating the MSU design is a fast way to iterate, debug, and test before moving on to hardware emulation. 21 | 22 | You can run simulations and view waveforms for a particular design as follows: 23 | ``` 24 | cd msu 25 | 26 | # Simple squarer 27 | make clean; make simple 28 | 29 | # 8 cycle Ozturk squarer 30 | make clean; make ozturk 31 | 32 | # View waveforms 33 | gtkwave rtl/obj_dir/logs/vlt_dump.vcd 34 | ``` 35 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/primitives/rtl/compressor_6_to_3_S_bit.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Kurt Baty 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | 16 | *******************************************************************************/ 17 | 18 | // 19 | // compressor 6 to 3 20 | // 21 | // 9/25/2019 22 | // 23 | // by Kurt Baty 24 | // 25 | 26 | /* 27 | A compressor 6:3 Sum bit 28 | */ 29 | 30 | module compressor_6_to_3_S_bit 31 | ( 32 | input logic I0, 33 | input logic I1, 34 | input logic I2, 35 | input logic I3, 36 | input logic I4, 37 | input logic I5, 38 | output logic S 39 | ); 40 | 41 | // this maps to a LUT6 in Xilinx FPGAs 42 | 43 | always_comb begin 44 | S = ^{I5,I4,I3,I2,I1,I0}; 45 | end 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sun Sep 29 17:09:33 2019 6 | # Process ID: 4762 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu 8 | # Command line: vivado msu.xpr 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project msu.xpr 14 | launch_simulation 15 | open_wave_config /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/tb_behav.wcfg 16 | source tb.tcl 17 | update_compile_order -fileset sources_1 18 | run all 19 | close_sim 20 | launch_simulation 21 | open_wave_config /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/tb_behav.wcfg 22 | source tb.tcl 23 | run all 24 | relaunch_sim 25 | run all 26 | save_wave_config {/home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/tb_behav.wcfg} 27 | close_sim 28 | launch_simulation 29 | open_wave_config /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/tb_behav.wcfg 30 | source tb.tcl 31 | run all 32 | reset_run synth_1 33 | launch_runs impl_1 -jobs 4 34 | wait_on_run impl_1 35 | close_sim 36 | open_run impl_1 37 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/primitives/rtl/full_adder_6.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder_6 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic C, 32 | input logic D, 33 | input logic E, 34 | input logic F, 35 | output logic Cout1, 36 | output logic Cout, 37 | output logic S 38 | ); 39 | 40 | logic [2:0] sum; 41 | 42 | always_comb begin 43 | sum = A + B + C + D + E + F; 44 | Cout1 = sum[2]; 45 | Cout = sum[1]; 46 | S = sum[0]; 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/primitives/rtl/full_adder_6.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder_6 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic C, 32 | input logic D, 33 | input logic E, 34 | input logic F, 35 | output logic Cout1, 36 | output logic Cout, 37 | output logic S 38 | ); 39 | 40 | logic [2:0] sum; 41 | 42 | always_comb begin 43 | sum = A + B + C + D + E + F; 44 | Cout1 = sum[2]; 45 | Cout = sum[1]; 46 | S = sum[0]; 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/primitives/rtl/full_adder_6.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | /* 18 | A basic 1-bit full adder 19 | ------- 20 | | FA | 21 | A --> | | --> S 22 | B --> | | 23 | Cin --> | | --> Cout 24 | ------- 25 | */ 26 | 27 | module full_adder_6 28 | ( 29 | input logic A, 30 | input logic B, 31 | input logic C, 32 | input logic D, 33 | input logic E, 34 | input logic F, 35 | output logic Cout1, 36 | output logic Cout, 37 | output logic S 38 | ); 39 | 40 | logic [2:0] sum; 41 | 42 | always_comb begin 43 | sum = A + B + C + D + E + F; 44 | Cout1 = sum[2]; 45 | Cout = sum[1]; 46 | S = sum[0]; 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/vivado_23167.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sat Sep 28 19:16:54 2019 6 | # Process ID: 23167 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu 8 | # Command line: vivado msu.xpr 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project msu.xpr 14 | launch_runs synth_1 -jobs 4 15 | wait_on_run synth_1 16 | update_compile_order -fileset sources_1 17 | update_compile_order -fileset sim_1 18 | open_run synth_1 -name synth_1 19 | launch_runs impl_1 -jobs 4 20 | wait_on_run impl_1 21 | close_design 22 | open_run impl_1 23 | close_design 24 | reset_run synth_1 25 | launch_runs impl_1 -jobs 4 26 | wait_on_run impl_1 27 | reset_run synth_1 28 | launch_runs impl_1 -jobs 4 29 | wait_on_run impl_1 30 | set_property is_enabled false [get_files /home/centos/src/vdf-fpga-metzgen/modular_square/rtl/sum200to1.sv] 31 | update_compile_order -fileset sources_1 32 | set_property is_enabled true [get_files /home/centos/src/vdf-fpga-metzgen/modular_square/rtl/sum200to1.sv] 33 | update_compile_order -fileset sources_1 34 | open_run impl_1 35 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/sdaccel/timing_constrs.xdc: -------------------------------------------------------------------------------- 1 | # Required for SDAccel 2 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] 3 | 4 | # Designate clock crossings as false paths 5 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/reset_e4_reg__0] 6 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/valid_in_cdc/valid_in_pulse_reg] 7 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/valid_out_cdc/valid_in_pulse_reg] 8 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_in_e1_reg*] 9 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_out_i1_reg*] 10 | 11 | # sq_in and sq_out are multi-cycle paths 12 | # https://www.xilinx.com/video/hardware/setting-multicycle-path-exceptions.html 13 | set_multicycle_path 3 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_in_e1_reg*}] 14 | set_multicycle_path 2 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_in_e1_reg*}] -hold 15 | 16 | set_multicycle_path 3 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_out_i1_reg*}] 17 | set_multicycle_path 2 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_out_i1_reg*}] -hold 18 | 19 | 20 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/sdaccel/timing_constrs.xdc: -------------------------------------------------------------------------------- 1 | # Required for SDAccel 2 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] 3 | 4 | # Designate clock crossings as false paths 5 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/reset_e4_reg__0] 6 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/valid_in_cdc/valid_in_pulse_reg] 7 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/valid_out_cdc/valid_in_pulse_reg] 8 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_in_e1_reg*] 9 | set_false_path -from [get_cells WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_out_i1_reg*] 10 | 11 | # sq_in and sq_out are multi-cycle paths 12 | # https://www.xilinx.com/video/hardware/setting-multicycle-path-exceptions.html 13 | set_multicycle_path 3 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_in_e1_reg*}] 14 | set_multicycle_path 2 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_in_e1_reg*}] -hold 15 | 16 | set_multicycle_path 3 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_out_i1_reg*}] 17 | set_multicycle_path 2 -from [get_cells {WRAPPER_INST/CL/vdf_1/inst/inst_wrapper/inst_kernel/msu/modsqr/sq_out_i1_reg*}] -hold 18 | 19 | 20 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /silicon_tailor-296/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /geriatric_guys_with_gates/msu/sw/Config.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright 2019 Supranational LLC 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | */ 16 | 17 | #ifndef _CONFIG_H_ 18 | #define _CONFIG_H_ 19 | 20 | #include 21 | 22 | #define T_LEN 64 23 | 24 | #define MSU_BYTES_PER_WORD 4 25 | #define MSU_WORD_LEN (MSU_BYTES_PER_WORD*8) 26 | #define EXTRA_ELEMENTS 2 27 | #define NUM_SEGMENTS 4 28 | 29 | // Constants for Ozturk construction 30 | #define REDUNDANT_ELEMENTS 2 31 | #define WORD_LEN 16 32 | 33 | // Use to define size of word on cpp side (1,2,4,8) depending on bit_len 34 | #define BN_BUFFER_SIZE 4 // top.sv BIT_LEN = 17-32 35 | 36 | // Use to create offset when using larger words for bit_len 37 | // Such as when bit_len in top.sv is 17b and is 16b here, offset is 16 38 | #define BN_BUFFER_OFFSET 0 39 | 40 | void bn_shl(mpz_t bn, int bits); 41 | void bn_shr(mpz_t bn, int bits); 42 | void bn_init_mask(mpz_t mask, int bits); 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /silicon_tailor-291/modular_square/rtl/bigadd3.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Silicon Tailor Ltd 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | `timescale 1 ns / 1 ns 18 | 19 | 20 | // 21 | // Adds three inputs and a carry 22 | // Note: truncates output to N bits 23 | // 24 | module bigadd3 25 | #( 26 | parameter int N = 32 27 | ) 28 | ( 29 | input logic [N-1:0] a_in, 30 | input logic [N-1:0] b_in, 31 | input logic [N-1:0] c_in, 32 | input logic carry_in, 33 | output logic [N-1:0] sum_out 34 | ); 35 | 36 | 37 | logic [N-1:0] sums; 38 | logic [N-1:0] carrys; 39 | 40 | assign sums = { a_in ^ b_in ^ c_in }; 41 | assign carrys = { (a_in & b_in) | (a_in & c_in) | (b_in & c_in), carry_in }; 42 | 43 | (* keep_hierarchy = "no" *) 44 | bigadd #( .N(N) ) i_bigadd ( 45 | .a_in (sums), 46 | .b_in (carrys), 47 | .sum_out (sum_out) 48 | ); 49 | 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /silicon_tailor-296/modular_square/rtl/bigadd3.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Silicon Tailor Ltd 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | `timescale 1 ns / 1 ns 18 | 19 | 20 | // 21 | // Adds three inputs and a carry 22 | // Note: truncates output to N bits 23 | // 24 | module bigadd3 25 | #( 26 | parameter int N = 32 27 | ) 28 | ( 29 | input logic [N-1:0] a_in, 30 | input logic [N-1:0] b_in, 31 | input logic [N-1:0] c_in, 32 | input logic carry_in, 33 | output logic [N-1:0] sum_out 34 | ); 35 | 36 | 37 | logic [N-1:0] sums; 38 | logic [N-1:0] carrys; 39 | 40 | assign sums = { a_in ^ b_in ^ c_in }; 41 | assign carrys = { (a_in & b_in) | (a_in & c_in) | (b_in & c_in), carry_in }; 42 | 43 | (* keep_hierarchy = "no" *) 44 | bigadd #( .N(N) ) i_bigadd ( 45 | .a_in (sums), 46 | .b_in (carrys), 47 | .sum_out (sum_out) 48 | ); 49 | 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /silicon_tailor-30/modular_square/rtl/bigadd3.sv: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright 2019 Silicon Tailor Ltd 3 | 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | 8 | http://www.apache.org/licenses/LICENSE-2.0 9 | 10 | Unless required by applicable law or agreed to in writing, software 11 | distributed under the License is distributed on an "AS IS" BASIS, 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | See the License for the specific language governing permissions and 14 | limitations under the License. 15 | *******************************************************************************/ 16 | 17 | `timescale 1 ns / 1 ns 18 | 19 | 20 | // 21 | // Adds three inputs and a carry 22 | // Note: truncates output to N bits 23 | // 24 | module bigadd3 25 | #( 26 | parameter int N = 32 27 | ) 28 | ( 29 | input logic [N-1:0] a_in, 30 | input logic [N-1:0] b_in, 31 | input logic [N-1:0] c_in, 32 | input logic carry_in, 33 | output logic [N-1:0] sum_out 34 | ); 35 | 36 | 37 | logic [N-1:0] sums; 38 | logic [N-1:0] carrys; 39 | 40 | assign sums = { a_in ^ b_in ^ c_in }; 41 | assign carrys = { (a_in & b_in) | (a_in & c_in) | (b_in & c_in), carry_in }; 42 | 43 | (* keep_hierarchy = "no" *) 44 | bigadd #( .N(N) ) i_bigadd ( 45 | .a_in (sums), 46 | .b_in (carrys), 47 | .sum_out (sum_out) 48 | ); 49 | 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /silicon_tailor-30/msu/rtl/vivado_metzgen/msu/vivado_28187.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2018.3.op (64-bit) 3 | # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 4 | # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 5 | # Start of session at: Sat Sep 28 16:30:40 2019 6 | # Process ID: 28187 7 | # Current directory: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu 8 | # Command line: vivado msu.xpr 9 | # Log file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.log 10 | # Journal file: /home/centos/src/vdf-fpga-metzgen/msu/rtl/vivado_metzgen/msu/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project msu.xpr 14 | Scanning sources... 15 | Finished scanning sources 16 | WARNING: [filemgmt 56-3] Board Part Repository Path: Could not find the directory '/home/snpeffer/src/vdf/artya7/vivado-boards-master/new/board_files'. 17 | INFO: [IP_Flow 19-234] Refreshing IP repositories 18 | INFO: [IP_Flow 19-1704] No user IP repositories specified 19 | INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.3.op2405991/data/ip'. 20 | open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 6444.723 ; gain = 54.414 ; free physical = 54554 ; free virtual = 77644 21 | update_compile_order -fileset sources_1 22 | exit 23 | INFO: [Common 17-206] Exiting Vivado at Sat Sep 28 16:32:02 2019... 24 | INFO: [filemgmt 56-326] User Interrupt. Could not getCurrentGraph() 25 | INFO: [filemgmt 56-326] User Interrupt. Could not getCurrentGraph() 26 | -------------------------------------------------------------------------------- /andreas_brokalakis/msu/rtl/vivado_ozturk/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | # cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | -------------------------------------------------------------------------------- /eric_pearson-1/msu/rtl/vivado_ozturk/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh mem/reduction_lut_000.dat" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | -------------------------------------------------------------------------------- /eric_pearson-2/msu/rtl/vivado_ozturk/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh mem/reduction_lut_000.dat" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | -------------------------------------------------------------------------------- /fpga_enthusiast-1/msu/rtl/vivado_ozturk/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh mem/reduction_lut_000.dat" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | -------------------------------------------------------------------------------- /fpga_enthusiast-2/msu/rtl/vivado_ozturk/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh mem/reduction_lut_000.dat" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | -------------------------------------------------------------------------------- /fpga_enthusiast-3/msu/rtl/vivado_ozturk/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh mem/reduction_lut_000.dat" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_metzgen/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh mem/reduction_lut_000.dat" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | -------------------------------------------------------------------------------- /silicon_tailor-291/msu/rtl/vivado_ozturk/run_vivado.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | # Configuration 6 | # If using 128 bits be sure to change tb.sv as well. 7 | export MOD_LEN=1024 8 | MODEL=msu 9 | OBJ=../sdaccel/obj_vivado 10 | 11 | # Set current directory to the location of this script 12 | SCRIPT=$(dirname "$0") 13 | SCRIPTPATH=$(realpath "$SCRIPT") 14 | cd $SCRIPTPATH 15 | 16 | # Clean up the msuconfig file in rtl so vivado doesn't choose it 17 | # (why is there no way to configure the vivado include path?) 18 | rm -f ../msuconfig.vh 19 | 20 | # Generate a test 21 | # msuconfig.vh from this script will be replaced with the one from 22 | # makefile.sdaccel. 23 | ../gen_test.py -s ${MOD_LEN} 24 | rm -f msu.srcs/msuconfig.vh 25 | 26 | # Build dependencies 27 | mkdir -p ${MODEL}.srcs 28 | rm -fr ${OBJ} 29 | mkdir -p ${OBJ} 30 | 31 | # Delete the any old files first to ensure they are up to date 32 | TARGETS="msuconfig.vh mem/reduction_lut_000.dat" 33 | export MODSQR_DIR=../../../../../modular_square 34 | DIRECT_TB=1 make -C ${OBJ} -f ../../multiplier.mk ${TARGETS} 35 | 36 | # Copy the ROM files into the src directory. 37 | cp ${OBJ}/msuconfig.vh ${MODEL}.srcs 38 | cp -r ${OBJ}/mem ${MODEL}.srcs 39 | rm -fr ${OBJ} 40 | 41 | # Generate the Vivado project 42 | if [ ! -d msu ]; then 43 | echo "Generating vivado project" 44 | ./generate.sh 45 | fi 46 | 47 | # Update the project directory to the current dir 48 | #sed 's@\(Project [^ ]\+ [^ ]\+ Path="\)[^\\"]\+@\1'$SCRIPTPATH/$MODEL.xpr'@' $MODEL.xpr > $MODEL.xpr_new 49 | #mv $MODEL.xpr_new $MODEL.xpr 50 | 51 | cd msu 52 | vivado $MODEL.xpr & 53 | 54 | 55 | --------------------------------------------------------------------------------