├── .gitmodules ├── DISK.HEX ├── LICENSE.TXT ├── PALETTE.HEX ├── README.txt ├── build ├── Makefile └── project │ └── Makefile ├── clk50mhz.vwf ├── doc ├── arch.svg ├── clocks-2.png ├── clocks.png ├── computer.png ├── floppy.png ├── jtag_statemachine.png ├── putupchik.jpg ├── statecharts.zargo └── wd_statemachine.png ├── firmware ├── HOWTO ├── Makefile ├── cc65-winbuild.zip └── floppysrc │ ├── Makefile │ ├── compile.bat │ ├── config.h │ ├── crt0.S │ ├── diskio.h │ ├── fddimage.c │ ├── fddimage.h │ ├── integer.h │ ├── main.c │ ├── menu.c │ ├── menu.h │ ├── mmc.c │ ├── osd.c │ ├── osd.h │ ├── philes.c │ ├── philes.h │ ├── readme.txt │ ├── serial.c │ ├── serial.h │ ├── slave.c │ ├── slave.h │ ├── specialio.h │ ├── tff.c │ ├── tff.h │ ├── timer.c │ ├── timer.h │ ├── vector.inc │ └── vector.lc ├── project ├── de1 │ ├── vector06cc.cdf │ ├── vector06cc.dpf │ ├── vector06cc.jdi │ ├── vector06cc.pin │ ├── vector06cc.qpf │ ├── vector06cc.qsf │ └── vector06cc.qws ├── de1sram │ ├── vector06cc.cdf │ ├── vector06cc.dpf │ ├── vector06cc.jdi │ ├── vector06cc.pin │ ├── vector06cc.qpf │ ├── vector06cc.qsf │ └── vector06cc.qws └── wxeda │ ├── vector06cc.cdf │ ├── vector06cc.jdi │ ├── vector06cc.pin │ ├── vector06cc.qpf │ ├── vector06cc.qsf │ └── vector06cc.qws ├── scripts ├── googlecode_upload.py ├── makezip.py └── uploader.bat ├── src ├── DE1 │ ├── CLK_LOCK.v │ ├── CMD_Decode.v │ ├── I2C_AV_Config.v │ ├── I2C_Controller.v │ ├── RS232_Command.h │ ├── SDRAM_Controller.v │ ├── SEG7_LUT.v │ ├── USB_JTAG.v │ ├── audio_io.v │ ├── clockster.v │ ├── colorpll.ppf │ ├── colorpll.qip │ ├── colorpll.v │ ├── colorpll_bb.v │ ├── soundcodec.v │ ├── vector06cc.v │ └── video │ │ ├── video.v │ │ └── videomod.v ├── T80 │ ├── T80.vhd │ ├── T8080se.bsf │ ├── T8080se.vhd │ ├── T80_ALU.vhd │ ├── T80_MCode.vhd │ ├── T80_Pack.vhd │ ├── T80_Reg.vhd │ └── T80sef.vhd ├── altmodules │ ├── 1200PALL.HEX │ ├── ayclkdrv.v │ ├── bootrom.qip │ ├── bootrom.v │ ├── bootrom1200.qip │ ├── bootrom1200.v │ ├── bootrom_bb.v │ ├── mclk14mhz.v │ ├── mclk24mhz.bsf │ ├── mclk24mhz.ppf │ ├── mclk24mhz.qip │ ├── mclk24mhz.v │ ├── palette_ram.v │ ├── palette_rom.qip │ ├── palette_rom.v │ ├── pll120.ppf │ ├── pll120.qip │ ├── pll120.v │ ├── pll120_bb.v │ └── vec1200.hex ├── ay │ ├── YM2149_linmix.vhd │ ├── ay8910.vhd │ ├── ayglue.v │ └── ym2149.vhd ├── border_delay.v ├── de1sram │ ├── altmodules │ │ └── mclk24mhz.v │ ├── audio_io.v │ ├── ay │ │ └── ayglue.v │ ├── clockster.v │ ├── soundcodec.v │ ├── sram_map.v │ ├── vector06cc.v │ └── video │ │ ├── framebuffer.v │ │ └── video.v ├── floppy │ ├── 65c02 │ │ └── cpu65xx_en.vhd │ ├── dma_rw.v │ ├── floppy.v │ ├── floppyram.v │ ├── floppyrom.v │ ├── ram1024x8a.v │ ├── ram512x8a.v │ ├── spi.v │ ├── timer100hz.v │ ├── uart │ │ └── txd.vhd │ └── wd1793.v ├── i8253 │ └── 8253.v ├── i82c55 │ └── i82c55.vhd ├── jtag │ └── jtag_top.v ├── keyboard │ ├── ps2k.v │ ├── scan2matrix.v │ └── vectorkeys.v ├── lpm_rom0.v ├── oneshot.v ├── osd │ ├── chargen.v │ ├── e5x7.mif │ ├── screenbuffer.v │ ├── testtext.mif │ └── textmode.v ├── ramdisk │ └── kvaz.v ├── singleclockster.v ├── specialkeys.v ├── video │ ├── framebuffer.v │ ├── multadd.qip │ ├── rambuffer.v │ ├── shiftreg2.v │ └── vga_refresh.v ├── wxeda │ ├── clockster.v │ ├── colorclock.ppf │ ├── colorclock.qip │ ├── colorclock.v │ ├── colorclock_bb.v │ ├── greybox_tmp │ │ └── cbx_args.txt │ ├── soundcodec.v │ ├── tlc549c.v │ ├── vector06cc.v │ ├── video │ │ ├── video.v │ │ └── videomod.v │ ├── wxeda_clocks.ppf │ ├── wxeda_clocks.qip │ ├── wxeda_clocks.v │ └── wxeda_clocks_bb.v └── zagr512.hex ├── testbits.hex ├── tools ├── pal.py ├── pal16.py └── pal4.py └── workbench ├── cputest ├── build.bat ├── cputype.asm ├── cputype.com ├── latch.asm ├── latch.com ├── make.bat ├── test.asm ├── test.com ├── timer.asm ├── timer.com └── zap.bat └── floppy ├── fauxpaw.hex ├── floppywb.cdf ├── floppywb.qpf ├── floppywb.qsf ├── floppywb.qws ├── src ├── 65c02 │ ├── cpu65xx_en.vhd │ └── cpu65xx_en.vhd.bak ├── floppyram.v ├── floppywb.v ├── floppywb.vwf ├── rom.v ├── uart │ └── txd.vhd ├── wd-alone.v └── wd-alone.vwf ├── wd-alone.qpf ├── wd-alone.qsf └── wd-alone.qws /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "firmware/cc65"] 2 | path = firmware/cc65 3 | url = https://github.com/svofski/cc65 4 | branch = vector06cc 5 | -------------------------------------------------------------------------------- /PALETTE.HEX: -------------------------------------------------------------------------------- 1 | :0100000000FF 2 | :0100010000FE 3 | :0100020030CD 4 | :010003007B81 5 | :01000400C932 6 | :01000500DA20 7 | :010006000DEC 8 | :01000700F206 9 | :010008000FE8 10 | :01000900A74F 11 | :01000A0037BE 12 | :01000B003FB5 13 | :01000C0021D2 14 | :01000D00DE14 15 | :01000E00AD44 16 | :01000F00FFF1 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /README.txt: -------------------------------------------------------------------------------- 1 | VECTOR-06C FPGA REPLICA 2 | ~~~~~~~~~~~~~~~~~~~~~~~ 3 | 4 | This project is an attempt to replicate Vector-06C, a Soviet-era home 5 | computer, in FPGA. The primary hardware platform for this project is 6 | Altera DE1 development board. 7 | 8 | 9 | CONTENTS 10 | 11 | * Features 12 | * DE1 Thingies 13 | * DE1 SRAM Mapping and Starter Kit Utility 14 | * Known Problems 15 | * Known ROMs That Have Issues 16 | * Acknowledgements 17 | 18 | 19 | Features 20 | ~~~~~~~~ 21 | 22 | The following features are implemented: 23 | 24 | - CPU 25 | - Perfect timings matching the original machine in every detail 26 | - SRAM is used for everything 27 | - 8253 timer 28 | - tape i/o (and beeper) 29 | - all internal stuff, video modes, palette 30 | - PS/2 keyboard 31 | - 256K RAM disk 32 | - DE1 JTAG interface to JTAG USB API program 33 | - Colour composite TV signal output (PAL) 34 | 35 | 36 | DE1 Thingies 37 | ~~~~~~~~~~~~ 38 | 39 | Enjoy the generous blinkenlights from Terasic and svofski! 40 | 41 | It is important to have switches SW8 and SW9 in "1" position (up). This 42 | enables proper CPU clocking. Other switches just change the blinken pattern 43 | and only important when you're debugging. 44 | 45 | KEY0 is master reset, somewhat like BLK+VVOD. 46 | 47 | KEY1 is manual clock for CPU. Useful only for hardcore debugging. 48 | 49 | KEY3 is same as BLK+SBR: boot ROM is disabled, RST0 is executed. 50 | 51 | If KEY3 is held pressed when KEY0 is being pressed, or when Vector-06C 52 | image is being programmed into FPGA, boot ROM doesn't work at all. 53 | This is useful if you want to preserve SRAM content. 54 | 55 | 56 | 57 | DE1 SRAM Mapping 58 | ~~~~~~~~~~~~~~~~ 59 | DE1 SRAM is addressed by word. This is mapped linearly into bytes, so programs 60 | can be uploaded with CII Starter Kit Control Panel software without any 61 | modifications. However, addresses should be minded. 62 | 63 | Normally a .rom file goes to address 0x0100. Translated into word-address, that 64 | becomes 0x0080. So when uploading a .rom file to Vector, enter "80" in the SRAM 65 | page, "Sequential Write" box. 66 | 67 | Similarly, RAM disk pages start after first 64K, which is 0x10000, or 0x8000 68 | in words. So, for uploading RAM disk images, use address "8000". RAM disk images 69 | can be read Starter Kit Control Panel software and re-uploaded later or used 70 | with an emulator as .edd files. 71 | 72 | 73 | Known Problems 74 | ~~~~~~~~~~~~~~ 75 | 76 | 1. Keyboard input gets stuck when some of the ":()*@" characters are entered. 77 | 78 | This is a problem with PS/2 -> Vector keyboard key/char mapping. 79 | I tried to make it as much PS/2 as possible. But since some characters 80 | shift/key combination differ, there's more than one direct mapping and 81 | this mapping gets stuck. 82 | 83 | Workaround: always carefully press SHIFT, then ":", then release ":", 84 | then release SHIFT. If input gets stuck, unstick it by carefully 85 | pressing same character again. 86 | 87 | 88 | Known ROMs That Have Issues 89 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ 90 | 91 | None. 92 | 93 | Acknowledgements 94 | ~~~~~~~~~~~~~~~~ 95 | 96 | This project uses work of different people. 97 | 98 | T80 CPU by Daniel Wallner with fixes from MikeJ of www.fpgaarcade.com is used 99 | for KR580WM80A. The code is modified in attempt to make this otherwise 100 | excellent CPU cycle-compatible with i8080 and to implement STACK signal in PSW. 101 | 102 | 82C55 code by MikeJ of www.fpgaarcade.com is used without any modifications. 103 | 104 | DE1-specific code uses, or may be based upon, samples from Altera DE1 package. 105 | 106 | Initial 2K bootloader code by Alexander Timoshenko et al. 107 | 108 | Special thanks to Alexander Timoshenko for documentation and general information 109 | about Vector-06C, Dmitry Tselikov for hints and good reference emulator, Roman 110 | Panteleev and Artem Navalon for ve27a with debugger. 111 | 112 | $Id$ 113 | 114 | Viacheslav Slavinsky 115 | http://sensi.org/~svo 116 | http://sensi.org/~svo/vector06c 117 | -------------------------------------------------------------------------------- /build/Makefile: -------------------------------------------------------------------------------- 1 | all: 2 | make -C project 3 | 4 | hdl-clean: 5 | make -C project hdl-clean 6 | 7 | clean: 8 | make -C project clean 9 | -------------------------------------------------------------------------------- /build/project/Makefile: -------------------------------------------------------------------------------- 1 | # Possible targets: de1 de1sram wxeda 2 | 3 | TARGET ?= de1 4 | 5 | PROJECT = vector06cc 6 | TOP_LEVEL_ENTITY = vector06cc 7 | ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf 8 | QUARTUS_DIR = $(HOME)/altera/13.0sp1 9 | export PATH := $(PATH):$(QUARTUS_DIR)/quartus/bin/ 10 | export TCLLIBPATH := \ 11 | . \ 12 | $(QUARTUS_DIR)/quartus/common/tcl/packages/tcllib-1.11/cmdline/ \ 13 | $(QUARTUS_DIR)/quartus/linux/tcl8.5/msgcat/ 14 | 15 | all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt 16 | 17 | firmware-clean: 18 | make -C ../../firmware clean 19 | 20 | hdl-clean: 21 | rm -f src 22 | rm -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db reports *.qpf *.qsf *.summary *.jdi *.smsg *.txt 23 | 24 | clean: hdl-clean firmware-clean 25 | 26 | map: smart.log $(PROJECT).map.rpt 27 | fit: smart.log $(PROJECT).fit.rpt 28 | asm: smart.log $(PROJECT).asm.rpt 29 | sta: smart.log $(PROJECT).sta.rpt 30 | smart: smart.log 31 | 32 | ################################################################### 33 | # Executable Configuration 34 | ################################################################### 35 | 36 | MAP_ARGS = --read_settings_files=on $(addprefix --source=,$(SRCS)) -l ../../src 37 | 38 | #FIT_ARGS = --part=$(PART) --read_settings_files=on 39 | FIT_ARGS = --read_settings_files=on 40 | ASM_ARGS = 41 | STA_ARGS = 42 | 43 | ################################################################### 44 | # Target implementations 45 | ################################################################### 46 | 47 | STAMP = echo done > 48 | 49 | ../../disk.hex: 50 | make -C ../../firmware 51 | 52 | $(PROJECT).map.rpt: map.chg ../../src ../../disk.hex 53 | ln -fs ../src . 54 | quartus_map $(PROJECT).qpf 55 | $(STAMP) fit.chg 56 | 57 | $(PROJECT).fit.rpt: fit.chg $(PROJECT).map.rpt 58 | quartus_fit $(FIT_ARGS) $(PROJECT) 59 | $(STAMP) asm.chg 60 | $(STAMP) sta.chg 61 | 62 | $(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt 63 | quartus_asm $(ASM_ARGS) $(PROJECT) 64 | 65 | $(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt 66 | quartus_sta $(STA_ARGS) $(PROJECT) 67 | 68 | smart.log: $(ASSIGNMENT_FILES) 69 | quartus_sh --determine_smart_action $(PROJECT) > smart.log 70 | 71 | ################################################################### 72 | # Project initialization 73 | ################################################################### 74 | 75 | $(ASSIGNMENT_FILES): 76 | #quartus_sh --prepare -f $(FAMILY) -t $(TOP_LEVEL_ENTITY) $(PROJECT) 77 | #-cat $(BOARDFILE) >> $(PROJECT).qsf 78 | cp ../../project/$(TARGET)/$(PROJECT).qsf . 79 | cp ../../project/$(TARGET)/$(PROJECT).qpf . 80 | map.chg: 81 | $(STAMP) map.chg 82 | fit.chg: 83 | $(STAMP) fit.chg 84 | sta.chg: 85 | $(STAMP) sta.chg 86 | asm.chg: 87 | $(STAMP) asm.chg 88 | 89 | ################################################################### 90 | # Programming the device 91 | ################################################################### 92 | 93 | program: $(PROJECT).sof 94 | quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" 95 | -------------------------------------------------------------------------------- /doc/clocks-2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/clocks-2.png -------------------------------------------------------------------------------- /doc/clocks.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/clocks.png -------------------------------------------------------------------------------- /doc/computer.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/computer.png -------------------------------------------------------------------------------- /doc/floppy.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/floppy.png -------------------------------------------------------------------------------- /doc/jtag_statemachine.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/jtag_statemachine.png -------------------------------------------------------------------------------- /doc/putupchik.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/putupchik.jpg -------------------------------------------------------------------------------- /doc/statecharts.zargo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/statecharts.zargo -------------------------------------------------------------------------------- /doc/wd_statemachine.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/doc/wd_statemachine.png -------------------------------------------------------------------------------- /firmware/HOWTO: -------------------------------------------------------------------------------- 1 | 1. Unzip cc65-winbuild.zip 2 | 2. cd cc65-winbuild 3 | 3. Run build.bat 4 | 4. Wait -------------------------------------------------------------------------------- /firmware/Makefile: -------------------------------------------------------------------------------- 1 | all: cc65 floppysrc 2 | git submodule update --init --remote 3 | cd cc65 && git checkout vector06cc 4 | make -C cc65 TARGETS=vector 5 | make -C floppysrc 6 | 7 | clean: 8 | make -C cc65 clean 9 | make -C floppysrc clean 10 | 11 | -------------------------------------------------------------------------------- /firmware/cc65-winbuild.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/firmware/cc65-winbuild.zip -------------------------------------------------------------------------------- /firmware/floppysrc/Makefile: -------------------------------------------------------------------------------- 1 | C65=../cc65/bin/cc65 2 | A65=../cc65/bin/ca65 3 | L65=../cc65/bin/ld65 4 | 5 | #CINC=c:\usr\lib\cc65\include 6 | #AINC=c:\usr\lib\cc65\asminc 7 | 8 | #OBJS=mmc.o tff.o serial.o main.o 9 | #ASSS=mmc.s tff.s serial.s main.s 10 | OBJS=crt0.o philes.o menu.o osd.o slave.o fddimage.o tff.o mmc.o timer.o serial.o main.o 11 | ASSS=philes.s menu.s osd.s slave.s fddimage.s tff.s mmc.s timer.s serial.s main.s 12 | 13 | # snapshot version of cc65 has a patch regarding -Os 14 | # release version will only work with -Oirs 15 | CFLAGS=-Os -t none -T --cpu 6502 16 | 17 | 18 | 19 | all: disk 20 | 21 | disk: $(OBJS) 22 | $(L65) -C vector.lc $(OBJS) ../cc65/lib/vector.lib -o disk.bin -m disk.map 23 | #bin2hex disk.bin disk.hex 24 | objcopy -Ibinary -Oihex disk.bin disk.hex 25 | cp disk.hex ../.. 26 | 27 | clean: 28 | rm -f $(OBJS) $(ASSS) disk.bin disk.map disk.hex ../../disk.hex 29 | 30 | %.s: %.c 31 | $(C65) $(CFLAGS) -I $(AINC) -I $(CINC) $< 32 | 33 | %.o: %.s 34 | $(A65) -t none $< -o $@ 35 | 36 | %.o: %.S 37 | $(A65) -t none $< -o $@ 38 | 39 | %.o: %.c 40 | 41 | #ld65 -C vector.lc lib/vector.o mmc.o lib/vector.lib -o mmc.bin -m mmc.map 42 | -------------------------------------------------------------------------------- /firmware/floppysrc/compile.bat: -------------------------------------------------------------------------------- 1 | @set PATH=%PATH%;..\cc65-winbuild\mingw\bin;..\cc65-winbuild\mingw\msys\1.0\bin;..\cc65-winbuild\cc65-master\bin;..\cc65-winbuild\bin2hex 2 | @mingw32-make %1 %2 %3 -------------------------------------------------------------------------------- /firmware/floppysrc/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | #define WITH_DMA 5 | 6 | #define WITH_SERIAL 7 | 8 | #define VERBOSE 2 // 1: mostly quiet 9 | // 2: log all requests 10 | // 3: obsessive, print sector dumps 11 | 12 | 13 | #define FDD_SECTOR_SIZE 1024U 14 | #define FDD_NSIDES 2U 15 | #define FDD_NSECTORS 5U 16 | #define SECTOR_SIZE_CODE 3U // 0 = 128, 1 = 256, 2 = 512, 3 = 1024 17 | 18 | #endif -------------------------------------------------------------------------------- /firmware/floppysrc/crt0.S: -------------------------------------------------------------------------------- 1 | ; 2 | ; Startup code for cc65 (Vector-06C FDD emulator version) 3 | ; 4 | ; This must be the *first* file on the linker command line 5 | ; 6 | 7 | .export _exit 8 | .export __STARTUP__ : absolute = 1 ; Mark as startup 9 | 10 | .import _main 11 | .import initlib, donelib, copydata 12 | .import zerobss 13 | .import __RAM_START__, __RAM_SIZE__ ; Linker generated 14 | .import __CONSTRUCTOR_TABLE__, __CONSTRUCTOR_COUNT__ 15 | .import __DESTRUCTOR_TABLE__, __DESTRUCTOR_COUNT__ 16 | 17 | .include "zeropage.inc" 18 | .include "vector.inc" 19 | 20 | .bss 21 | .code 22 | 23 | .segment "STARTUP" 24 | reset: 25 | jsr zerobss 26 | 27 | ; initialize data 28 | jsr copydata 29 | 30 | lda #>(__RAM_START__ + __RAM_SIZE__) 31 | sta sp+1 ; Set argument stack ptr 32 | stz sp ; #<(__RAM_START__ + __RAM_SIZE__) 33 | 34 | jsr initlib 35 | jsr _main 36 | _exit: jsr donelib 37 | exit: jmp exit 38 | 39 | 40 | .proc irq 41 | pha 42 | pla 43 | rti 44 | .endproc 45 | 46 | .proc nmi 47 | rti 48 | .endproc 49 | 50 | -------------------------------------------------------------------------------- /firmware/floppysrc/diskio.h: -------------------------------------------------------------------------------- 1 | /*----------------------------------------------------------------------- 2 | / Low level disk interface modlue include file R0.05 (C)ChaN, 2007 3 | /-----------------------------------------------------------------------*/ 4 | 5 | #ifndef _DISKIO 6 | 7 | #define _READONLY 0 /* 1: Read-only mode */ 8 | #define _USE_IOCTL 0 9 | 10 | #include "integer.h" 11 | 12 | 13 | /* Status of Disk Functions */ 14 | typedef BYTE DSTATUS; 15 | 16 | /* Results of Disk Functions */ 17 | typedef enum { 18 | RES_OK = 0, /* 0: Successful */ 19 | RES_ERROR, /* 1: R/W Error */ 20 | RES_WRPRT, /* 2: Write Protected */ 21 | RES_NOTRDY, /* 3: Not Ready */ 22 | RES_PARERR /* 4: Invalid Parameter */ 23 | } DRESULT; 24 | 25 | 26 | /*---------------------------------------*/ 27 | /* Prototypes for disk control functions */ 28 | 29 | // return RES_NOTRDY if disk doesn't respond 30 | DSTATUS disk_poll(BYTE drv); 31 | 32 | DSTATUS disk_initialize (BYTE); 33 | DSTATUS disk_status (BYTE); 34 | DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); 35 | #if _READONLY == 0 36 | DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); 37 | #endif 38 | DRESULT disk_ioctl (BYTE, BYTE, void*); 39 | void disk_timerproc (void); 40 | 41 | 42 | 43 | 44 | /* Disk Status Bits (DSTATUS) */ 45 | 46 | #define STA_NOINIT 0x01 /* Drive not initialized */ 47 | #define STA_NODISK 0x02 /* No medium in the drive */ 48 | #define STA_PROTECT 0x04 /* Write protected */ 49 | 50 | 51 | /* Command code for disk_ioctrl() */ 52 | 53 | /* Generic command */ 54 | #define CTRL_SYNC 0 /* Mandatory for write functions */ 55 | #define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ 56 | #define GET_SECTOR_SIZE 2 57 | #define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ 58 | #define CTRL_POWER 4 59 | #define CTRL_LOCK 5 60 | #define CTRL_EJECT 6 61 | /* MMC/SDC command */ 62 | #define MMC_GET_TYPE 10 63 | #define MMC_GET_CSD 11 64 | #define MMC_GET_CID 12 65 | #define MMC_GET_OCR 13 66 | #define MMC_GET_SDSTAT 14 67 | /* ATA/CF command */ 68 | #define ATA_GET_REV 20 69 | #define ATA_GET_MODEL 21 70 | #define ATA_GET_SN 22 71 | 72 | 73 | #define _DISKIO 74 | #endif 75 | -------------------------------------------------------------------------------- /firmware/floppysrc/fddimage.c: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: fddimage.c 15 | // 16 | // FDD floppy image implementation 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | 21 | #include "integer.h" 22 | #include "fddimage.h" 23 | #include "tff.h" 24 | #include "config.h" 25 | 26 | enum FDDErrors{ 27 | FDD_OK, 28 | FDD_SEEK_ERROR, 29 | FDD_READ_ERROR, 30 | }; 31 | 32 | static uint8_t fdderror; 33 | 34 | static FDDImage fdd; 35 | 36 | static void seterror(uint8_t e) { 37 | fdderror = e; 38 | } 39 | 40 | uint8_t fdd_clearerror() { 41 | uint8_t result = fdderror; 42 | fdderror = 0; 43 | return result; 44 | } 45 | 46 | uint8_t fdd_load(FIL* file, FDDImage *fdd, uint8_t *bufptr) { 47 | WORD w1; 48 | fdd_clearerror(); 49 | 50 | //fdd->ntracks = file->fsize / (2*FDD_NSECTORS*FDD_SECTOR_SIZE); // these seem to be fixed more or less 51 | fdd->ntracks = (file->fsize >> 10) / 2*FDD_NSECTORS; 52 | 53 | fdd->nsides = FDD_NSIDES; 54 | fdd->nsectors = FDD_NSECTORS; 55 | fdd->sectorsize = FDD_SECTOR_SIZE; 56 | fdd->file = file; 57 | fdd->buffer = bufptr; 58 | 59 | return (uint8_t) 0; 60 | } 61 | 62 | uint8_t fdd_seek(FDDImage *fdd, uint8_t side, uint8_t track, uint8_t sector) { 63 | fdd_clearerror(); 64 | 65 | if (side > FDD_NSIDES|| 66 | track > fdd->ntracks || 67 | sector > FDD_NSECTORS) seterror(FDD_SEEK_ERROR); 68 | 69 | fdd->cur_side = side; 70 | fdd->cur_track = track; 71 | fdd->cur_sector = sector; 72 | fdd->offset = 0; 73 | fdd->ready = 0; 74 | } 75 | 76 | static uint32_t calc_offset(FDDImage* fdd) { 77 | uint32_t offset = FDD_NSIDES*fdd->cur_track + (1-fdd->cur_side); 78 | offset *= FDD_NSECTORS; 79 | offset += fdd->cur_sector - 1; 80 | offset *= FDD_SECTOR_SIZE; 81 | 82 | return offset; 83 | } 84 | 85 | FRESULT fdd_readsector(FDDImage* fdd) { 86 | FRESULT r; 87 | UINT bytesread; 88 | 89 | uint32_t offset = calc_offset(fdd); 90 | 91 | //FDD_NSIDES*fdd->cur_track + (1-fdd->cur_side); 92 | //offset *= FDD_NSECTORS; 93 | //offset += fdd->cur_sector - 1; 94 | //offset *= FDD_SECTOR_SIZE; 95 | 96 | if ((r = f_lseek(fdd->file, offset)) != FR_OK) return r; 97 | 98 | r = f_read(fdd->file, fdd->buffer, FDD_SECTOR_SIZE, &bytesread); 99 | 100 | return r; 101 | } 102 | 103 | FRESULT fdd_writesector(FDDImage* fdd) { 104 | FRESULT r; 105 | UINT bytesread; 106 | 107 | uint32_t offset = calc_offset(fdd); 108 | if ((r = f_lseek(fdd->file, offset)) != FR_OK) return r; 109 | 110 | r = f_write_inplace(fdd->file, fdd->buffer, FDD_SECTOR_SIZE, &bytesread); 111 | 112 | return r; 113 | } 114 | 115 | FRESULT fdd_readadr(FDDImage *fdd) { 116 | uint8_t sizecode = SECTOR_SIZE_CODE; 117 | 118 | // 6 bytes: track, side, sector, sectorsize code, crc1, crc2 119 | fdd->buffer[0] = fdd->cur_track; 120 | fdd->buffer[1] = fdd->cur_side; 121 | fdd->buffer[2] = fdd->cur_sector; 122 | fdd->buffer[3] = sizecode; 123 | fdd->buffer[4] = 0; 124 | fdd->buffer[5] = 0; 125 | 126 | return FR_OK; 127 | } 128 | -------------------------------------------------------------------------------- /firmware/floppysrc/fddimage.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: fddimage.h 15 | // 16 | // FDD floppy image interface 17 | // 18 | // -------------------------------------------------------------------- 19 | #ifndef _FDDIMAGE_H 20 | #define _FDDIMAGE_H 21 | 22 | #include "integer.h" 23 | #include "tff.h" 24 | 25 | typedef struct { 26 | uint8_t nsides; 27 | uint8_t ntracks; 28 | uint8_t nsectors; 29 | uint16_t sectorsize; 30 | 31 | uint8_t cur_side; 32 | uint8_t cur_sector; 33 | uint8_t cur_track; 34 | 35 | FIL* file; 36 | uint16_t offset; // current offset into buffer 37 | uint8_t ready; // 1 => read operation must be performed first 38 | uint8_t *buffer; 39 | } FDDImage; 40 | 41 | uint8_t fdd_clearerror(void); 42 | uint8_t fdd_load(FIL* file, FDDImage *fdd, uint8_t* bufptr); 43 | uint8_t fdd_seek(FDDImage *fdd, uint8_t side, uint8_t track, uint8_t sector); 44 | //uint8_t fdd_nextbyte(FDDImage* fdd); 45 | FRESULT fdd_readsector(FDDImage* fdd); 46 | FRESULT fdd_writesector(FDDImage* fdd); 47 | FRESULT fdd_readadr(FDDImage *fdd); 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /firmware/floppysrc/integer.h: -------------------------------------------------------------------------------- 1 | #ifndef _INTEGER 2 | 3 | /* These types are assumed as 16-bit or larger integer */ 4 | typedef signed int INT; 5 | typedef unsigned int UINT; 6 | 7 | /* These types are assumed as 8-bit integer */ 8 | typedef signed char CHAR; 9 | typedef unsigned char UCHAR; 10 | typedef unsigned char BYTE; 11 | 12 | /* These types are assumed as 16-bit integer */ 13 | typedef signed short SHORT; 14 | typedef unsigned short USHORT; 15 | typedef unsigned short WORD; 16 | 17 | /* These types are assumed as 32-bit integer */ 18 | typedef signed long LONG; 19 | typedef unsigned long ULONG; 20 | typedef unsigned long DWORD; 21 | 22 | /* Boolean type */ 23 | typedef enum { FALSE = 0, TRUE } BOOL; 24 | 25 | typedef BYTE uint8_t; 26 | typedef WORD uint16_t; 27 | typedef DWORD uint32_t; 28 | 29 | #define _INTEGER 30 | #endif 31 | -------------------------------------------------------------------------------- /firmware/floppysrc/main.c: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007-2014, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: main.c 15 | // 16 | // FDC workhorse main module. 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #include 21 | 22 | #include "serial.h" 23 | #include "specialio.h" 24 | #include "integer.h" 25 | 26 | #include "diskio.h" 27 | #include "tff.h" 28 | 29 | #include "timer.h" 30 | #include "config.h" 31 | #include "slave.h" 32 | 33 | #include "osd.h" 34 | 35 | #include "philes.h" 36 | 37 | char* cnotice1 = " VECTOR-06C FPGA REPLICA "; 38 | char* cnotice2 = "(C)2008-14 VIACHESLAV SLAVINSKY"; 39 | 40 | /*---------------------------------------------------------*/ 41 | /* User Provided Timer Function for FatFs module */ 42 | /*---------------------------------------------------------*/ 43 | /* This is a real time clock service to be called from */ 44 | /* FatFs module. Any valid time must be returned even if */ 45 | /* the system does not support a real time clock. */ 46 | DWORD get_fattime (void) 47 | { 48 | return 0; 49 | } 50 | 51 | 52 | BYTE* Buffer = (BYTE *)0x0200; 53 | 54 | void print_result(DRESULT result) { 55 | switch (result) { 56 | case 0: 57 | break; 58 | default: 59 | ser_puts(" :( "); 60 | print_hex((BYTE)result); 61 | ser_nl(); 62 | break; 63 | } 64 | } 65 | 66 | void fill_filename(char *buf, char *fname) { 67 | memset(buf, 0, 12); 68 | strncpy(buf, fname, 12); 69 | } 70 | 71 | #define CHECKRESULT {/*if (result) break;*/} 72 | 73 | extern char* ptrfile; 74 | 75 | void main(void) { 76 | BYTE res; 77 | 78 | DRESULT result; 79 | FRESULT fresult; 80 | 81 | SLAVE_STATUS = 0; 82 | GREEN_LEDS = 0xC3; 83 | 84 | ser_puts("@"); 85 | delay2(10); 86 | 87 | ser_nl(); ser_puts(cnotice1); 88 | ser_nl(); ser_puts(cnotice2); 89 | 90 | thrall(ptrfile, Buffer); 91 | print_result(result); 92 | ser_puts("\r\nWTF?"); 93 | } 94 | -------------------------------------------------------------------------------- /firmware/floppysrc/menu.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: menu.h 15 | // 16 | // Menu functions 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #ifndef _MENU_H 21 | #define _MENU_H 22 | 23 | #include "integer.h" 24 | #include "specialio.h" 25 | #include "osd.h" 26 | 27 | #define AUTOREPEAT 4096 28 | 29 | 30 | #define TXT_MENU_MIDDLE " DISK " 31 | #define TXT_MENU_LEFT " RESET " 32 | #define TXT_MENU_RIGHT " RESTART " 33 | #define TXT_MENU_UP " HOLD " 34 | #define TXT_MENU_DOWN " ABOUT " 35 | 36 | #define TXT_MENU_HALP " Select with Arrows and Enter " 37 | #define TXT_MENU_ABOOTHALP " Press something " 38 | #define TXT_MENU_BUSY " [BUSY] " 39 | #define TXT_MENU_INSERT " INSERT CARD " 40 | #define ALIGN_RIGHT 0 41 | #define ALIGN_MIDDLE 1 42 | #define ALIGN_LEFT 2 43 | 44 | #define MENURESULT_NOTHING 0 45 | #define MENURESULT_DISK 1 46 | #define MENURESULT_RESET 2 47 | #define MENURESULT_RESTART 3 48 | #define MENURESULT_HOLD 4 49 | #define MENURESULT_ABOUT 5 50 | 51 | #define FSEL_ITEMS_PER_PAGE 2*6 // two columns, 6 lines 52 | 53 | uint8_t menu_dispatch(uint8_t tick); 54 | void menu_init(void); 55 | void draw_menu(void); 56 | void draw_item(char *s, uint8_t x, uint8_t y, uint8_t align); 57 | uint8_t menu_busy(uint8_t yes); 58 | 59 | #endif 60 | -------------------------------------------------------------------------------- /firmware/floppysrc/osd.c: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: osd.c 15 | // 16 | // On-Screen Display functions 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #include "specialio.h" 21 | #include "integer.h" 22 | #include "osd.h" 23 | 24 | #include 25 | 26 | extern char* cnotice1; 27 | 28 | uint8_t* dmem = (uint8_t*) DISPLAY_BASE; 29 | 30 | uint8_t x, y; 31 | uint8_t inv; 32 | 33 | void osd_cls(uint8_t hdr) { 34 | x = 0; 35 | y = 0; 36 | inv = 0; 37 | memset(dmem, 32, DISPLAY_RAMSIZE); 38 | if (hdr) { 39 | osd_inv(1); osd_puts(cnotice1); osd_inv(0); 40 | } 41 | } 42 | 43 | void osd_gotoxy(uint8_t _x, uint8_t _y) { 44 | x = _x; 45 | y = _y; 46 | } 47 | 48 | void osd_puts(char *s) { 49 | uint8_t ofs = (y << 5) + x; 50 | int i; 51 | 52 | if (inv) { 53 | for (i = ofs; *s != 0; i++, s++) dmem[i] = 0x80 | *s; 54 | } else { 55 | memcpy(dmem+ofs, s, strlen(s)); 56 | } 57 | } 58 | 59 | void osd_inv(uint8_t i) { 60 | inv = i; 61 | } -------------------------------------------------------------------------------- /firmware/floppysrc/osd.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: osd.h 15 | // 16 | // On-Screen Display functions 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #ifndef _OSD_H 21 | #define _OSD_H 22 | 23 | #include "integer.h" 24 | 25 | void osd_cls(uint8_t hdr); 26 | void osd_gotoxy(uint8_t _x, uint8_t _y); 27 | void osd_puts(char *s); 28 | void osd_inv(uint8_t i); 29 | 30 | #endif -------------------------------------------------------------------------------- /firmware/floppysrc/philes.c: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: philes.c 15 | // 16 | // FAT FS toplevel interface 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #include "integer.h" 21 | #include "philes.h" 22 | #include "diskio.h" 23 | #include "tff.h" 24 | 25 | #include 26 | 27 | FATFS fatfs; 28 | FILINFO finfo; 29 | DIR dir; 30 | 31 | char *ptrfile = "/VECTOR06/xxxxxxxx.xxx\0\0\0"; 32 | 33 | BYTE endsWith(char *s1, const char *suffix) { 34 | int s1len = strlen(s1); 35 | int sulen = strlen(suffix); 36 | 37 | if (sulen > s1len) return 0; 38 | 39 | return strcmp(&s1[s1len - sulen], suffix) == 0; 40 | } 41 | 42 | FRESULT philes_mount() { 43 | FRESULT result = FR_NO_FILESYSTEM; 44 | 45 | disk_initialize(0); 46 | return f_mount(0, &fatfs); 47 | } 48 | 49 | FRESULT philes_opendir() { 50 | FRESULT result; 51 | 52 | ptrfile[9] = 000; 53 | result = f_opendir(&dir, ptrfile); 54 | ptrfile[9] = '/'; 55 | 56 | return result; 57 | } 58 | 59 | static void strxcpy(char *dst, char *src) { 60 | uint8_t i = 12; 61 | while (*src != 0 && i--) *dst++ = *src++; 62 | } 63 | 64 | // fill in file name in buffer pointed by filename 65 | FRESULT philes_nextfile(char *filename, uint8_t terminate) { 66 | while ((f_readdir(&dir, &finfo) == FR_OK) && finfo.fname[0]) { 67 | if (finfo.fattrib & AM_DIR) { 68 | // nowai 69 | } else { 70 | if (endsWith(finfo.fname, ".FDD")) { 71 | if (filename != 0) { 72 | if (terminate) { 73 | strncpy(filename, finfo.fname, 12); 74 | } else { 75 | strxcpy(filename, finfo.fname); 76 | } 77 | } 78 | return 0; 79 | } 80 | } 81 | } 82 | 83 | return FR_NO_FILE; 84 | } -------------------------------------------------------------------------------- /firmware/floppysrc/philes.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: philes.h 15 | // 16 | // FAT FS toplevel interface 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #ifndef _PHILES_H 21 | #define _PHILES_H 22 | 23 | #include "integer.h" 24 | #include "tff.h" 25 | 26 | FRESULT philes_mount(void); 27 | FRESULT philes_opendir(void); 28 | FRESULT philes_nextfile(char *filename, uint8_t terminate); 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /firmware/floppysrc/readme.txt: -------------------------------------------------------------------------------- 1 | Disk I/O Processor for Vector-06C Replica 2 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 | 4 | vector.o and vector.lib based on spectravision library. Makefile of 5 | libsrc section only works in cygwin. 6 | 7 | Vector PIO memory map is defined in vector.lc. 8 | 9 | elm-chan's tff and mmc modules, altered for custom memory-mapped i/o; 10 | based on AVR version. Platform-dependent defines moved to 11 | specialio.h. 12 | 13 | 14 | 15 | Memory mapped I/O 16 | ~~~~~~~~~~~~~~~~~ 17 | 18 | $E000 Misc control signals: 19 | bit 0: MMC card CS_n 20 | 21 | $E001 SPI Data Register 22 | 23 | $E002 SPI control register: 24 | bit 0: SPIF (1 == transmit complete) 25 | 26 | $E003 Socket contact port 27 | bit 4: 0x10 card detect switch 28 | bit 5: 0x20 write protect switch 29 | 30 | -------------------------------------------------------------------------------- /firmware/floppysrc/serial.c: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: serial.c 15 | // 16 | // UART output functions for debugging 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #include "specialio.h" 21 | #include "serial.h" 22 | #include "integer.h" 23 | #include "config.h" 24 | 25 | #ifdef WITH_SERIAL 26 | void ser_putc(char c) { 27 | for(; SERIAL_CTL & SERIAL_RDY != 0;); 28 | SERIAL_TxD = c; 29 | } 30 | 31 | void ser_puts(char *s) { 32 | for(; *s != 0; s++) { 33 | for(; SERIAL_CTL & SERIAL_RDY != 0;); 34 | SERIAL_TxD = *s; 35 | } 36 | } 37 | 38 | void ser_nl(void) { 39 | ser_putc('\r'); 40 | ser_putc('\n'); 41 | } 42 | 43 | BYTE nybble_alpha(BYTE nybble) { 44 | return nybble + (nybble < 0x0a ? '0' : 'a'-0x0a); 45 | } 46 | 47 | void print_hex(BYTE b) { 48 | ser_putc(nybble_alpha((b & 0xf0) >> 4)); 49 | ser_putc(nybble_alpha(b & 0x0f)); 50 | } 51 | 52 | void print_buff(BYTE *Buffer) { 53 | WORD ofs; 54 | BYTE add; 55 | BYTE c; 56 | 57 | for (ofs = 0; ofs < FDD_SECTOR_SIZE; ofs += 16) { 58 | ser_nl(); 59 | for (add = 0; add < 16; add++) { 60 | print_hex(Buffer[ofs+add]); 61 | ser_putc(add == 8 ? '-' : ' '); 62 | } 63 | for (add = 0; add < 16; add++) { 64 | c = Buffer[ofs+add]; 65 | ser_putc(c > 31 && c < 128 ? c : '.'); 66 | } 67 | } 68 | ser_nl(); 69 | } 70 | #endif 71 | 72 | -------------------------------------------------------------------------------- /firmware/floppysrc/serial.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: serial.h 15 | // 16 | // UART output functions for debugging 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #ifndef _SERIAL_H_ 21 | #define _SERIAL_H_ 22 | 23 | #include "integer.h" 24 | #include "config.h" 25 | 26 | #define SERIAL_RDY 0x01 // buffer empty 27 | 28 | #define NL "\r\n" 29 | 30 | #ifdef WITH_SERIAL 31 | 32 | void ser_putc(char c); 33 | void ser_puts(char *s); 34 | void ser_nl(void); 35 | void print_hex(BYTE b); 36 | void print_buff(BYTE *Buffer); 37 | 38 | #else 39 | 40 | #define ser_putc(c) {} 41 | #define ser_puts(s) {} 42 | #define ser_nl(void) {} 43 | #define print_hex(b) {} 44 | #define print_buff(Buffer) {} 45 | 46 | #endif 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /firmware/floppysrc/slave.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: slave.h 15 | // 16 | // Main request handler, runs eternally 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #ifndef _SLAVE_H 21 | #define _SLAVE_H 22 | 23 | #include "integer.h" 24 | 25 | #define SR_OPENERR 1 26 | #define SR_READERR 2 27 | #define SR_FORMAT 3 28 | 29 | #define CPU_REQUEST_READ 0x10 // Request to read one sector at oTRACK, oSECTOR, bit 0 is side (head #) 30 | #define CPU_REQUEST_WRITE 0x20 // Request to write one sector at oTRACK, oSECTOR; bit 0 is side (head #) 31 | #define CPU_REQUEST_READADDR 0x30 // Request to read sector address (return 6 byte header) 32 | #define CPU_REQUEST_NOP 0x40 33 | #define CPU_REQUEST_ACK 0x80 // clear status 34 | #define CPU_REQUEST_FAIL 0xC0 // failure feedback for debug 35 | 36 | #define CPU_STATUS_COMPLETE 0x01 37 | #define CPU_STATUS_SUCCESS 0x02 38 | #define CPU_STATUS_CRC 0x04 39 | #define CPU_STATUS_DRVNOTRDY 0x08 // drive not ready/door not closed 40 | #define CPU_STATUS_BUSY 0x80 41 | 42 | uint8_t thrall(char *imagefile, uint8_t *buffer); 43 | 44 | 45 | #endif -------------------------------------------------------------------------------- /firmware/floppysrc/specialio.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: specialio.h 15 | // 16 | // I/O port mapping for FDC interface 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | 21 | #ifndef _SPECIALIO_J 22 | #define _SPECIALIO_J 23 | 24 | #define IOPORT_BASE 0xE000 25 | #define IOPORT_MMC_A 0x00 /* BIT0: SD_DAT3/CS */ 26 | #define IOPORT_SPDR 0x01 27 | #define IOPORT_SPSR 0x02 28 | #define IOPORT_JOY 0x03 /* Joystick */ 29 | 30 | #define IOPORT_SERIAL_TxD 0x04 31 | #define IOPORT_SERIAL_RxD 0x05 32 | #define IOPORT_SERIAL_CTL 0x06 33 | 34 | #define IOPORT_TIMER_1 0x07 /* counts down by 1 every 10ms */ 35 | #define IOPORT_TIMER_2 0x08 /* counts down by 1 every 10ms */ 36 | 37 | #define IOPORT_CPUREQ 0x09 /* our command */ 38 | #define IOPORT_CPUSTAT 0x0A /* where we set our status */ 39 | #define IOPORT_CPUTRACK 0x0B 40 | #define IOPORT_CPUSECTOR 0x0C 41 | 42 | #define IOPORT_DMAMSB 0x0E 43 | #define IOPORT_DMALSB 0x0F 44 | 45 | #define IOPORT_GLEDS 0x10 46 | 47 | #define IOPORT_OSDCMD 0x11 /* F11,F12,HOLD */ 48 | 49 | 50 | #define DISPLAY_BASE 0xE100 51 | #define DISPLAY_W 32 52 | #define DISPLAY_H 8 53 | #define DISPLAY_RAMSIZE 256 54 | 55 | #define MMC_A (*((unsigned char *)(IOPORT_BASE+IOPORT_MMC_A))) 56 | #define SPDR (*((unsigned char *)(IOPORT_BASE+IOPORT_SPDR))) 57 | #define SPSR (*((unsigned char *)(IOPORT_BASE+IOPORT_SPSR))) 58 | #define JOYSTICK (*((unsigned char *)(IOPORT_BASE+IOPORT_JOY))) 59 | 60 | #define SERIAL_TxD (*((unsigned char *)(IOPORT_BASE+IOPORT_SERIAL_TxD))) 61 | #define SERIAL_RxD (*((unsigned char *)(IOPORT_BASE+IOPORT_SERIAL_RxD))) 62 | #define SERIAL_CTL (*((unsigned char *)(IOPORT_BASE+IOPORT_SERIAL_CTL))) 63 | 64 | #define TIMER_1 (*((unsigned char *)(IOPORT_BASE+IOPORT_TIMER_1))) 65 | #define TIMER_2 (*((unsigned char *)(IOPORT_BASE+IOPORT_TIMER_2))) 66 | 67 | #define MASTER_COMMAND (*((unsigned char *)(IOPORT_BASE+IOPORT_CPUREQ))) 68 | #define SLAVE_STATUS (*((unsigned char *)(IOPORT_BASE+IOPORT_CPUSTAT))) 69 | #define MASTER_TRACK (*((unsigned char *)(IOPORT_BASE+IOPORT_CPUTRACK))) 70 | #define MASTER_SECTOR (*((unsigned char *)(IOPORT_BASE+IOPORT_CPUSECTOR))) 71 | 72 | #define DMAMSB (*((unsigned char *)(IOPORT_BASE+IOPORT_DMAMSB))) 73 | #define DMALSB (*((unsigned char *)(IOPORT_BASE+IOPORT_DMALSB))) 74 | 75 | 76 | #define GREEN_LEDS (*((unsigned char *)(IOPORT_BASE+IOPORT_GLEDS))) 77 | #define OSD_CMD (*((unsigned char *)(IOPORT_BASE+IOPORT_OSDCMD))) 78 | 79 | 80 | #define SOCKWP 0x20 /* Write protect switch (PB5) */ 81 | #define SOCKINS 0x10 /* Card detect switch (PB4) */ 82 | 83 | 84 | #define JOY_LT 0x10 85 | #define JOY_RT 0x08 86 | #define JOY_UP 0x04 87 | #define JOY_DN 0x02 88 | #define JOY_FIRE 0x01 89 | 90 | // MMC_A bits 91 | #define MMC_DAT3 1 92 | 93 | #define SELECT() MMC_A &= ~MMC_DAT3 94 | #define DESELECT() MMC_A |= MMC_DAT3 95 | 96 | #define SPIF 0x01 97 | 98 | #endif -------------------------------------------------------------------------------- /firmware/floppysrc/timer.c: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: timer.c 15 | // 16 | // Delay functions 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #include "integer.h" 21 | #include "specialio.h" 22 | #include "timer.h" 23 | 24 | void delay1(uint8_t ms10) { 25 | for(TIMER_1 = ms10; TIMER_1 !=0;); 26 | } 27 | 28 | void delay2(uint8_t ms10) { 29 | for(TIMER_2 = ms10; TIMER_2 !=0;); 30 | } 31 | -------------------------------------------------------------------------------- /firmware/floppysrc/timer.h: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This code is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Source file: timer.h 15 | // 16 | // Delay functions 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | #ifndef _TIMER_H 21 | #define _TIMER_H 22 | 23 | #include "integer.h" 24 | 25 | void delay1(uint8_t ms10); 26 | void delay2(uint8_t ms10); 27 | 28 | #endif -------------------------------------------------------------------------------- /firmware/floppysrc/vector.inc: -------------------------------------------------------------------------------- 1 | ; supervision symbols 2 | 3 | ; supervision 65c02s 4 | ; in cc65 up to 2.9.1 65c02 means 65c02s 5 | .pc02 6 | 7 | lcd_addr = $4000 8 | LCD_LINESIZE = $30 9 | LCD_WIDTH = 160 10 | LCD_HEIGHT = 160 11 | ; 2 bit per pixel, packed 12 | 13 | lcd_width = $2000 14 | lcd_height = $2001 15 | lcd_xpos = $2002 ; in pixel, bit 0+1 not used 16 | lcd_ypos = $2003 ; weird 17 | 18 | sv_port_r = $2021 19 | sv_port_w = $2022 20 | 21 | sv_timer_count = $2023 22 | ; read for quitting 23 | sv_timer_quit = $2024 24 | 25 | ; bit 0 timer, bit 1 dma 26 | sv_irq_source = $2027 27 | SV_IRQ_REQUEST_TIMER = 1 28 | SV_IRQ_REQUEST_DMA = 2 29 | 30 | ; bit 5,6,7 select bank at 0x8000 31 | sv_bank = $2026 32 | SV_NMI_ENABLE_ON = 1 33 | SV_IRQ_ENABLE_TIMER = 2 34 | SV_IRQ_ENABLE_DMA = 4 35 | SV_LCD_ON = 8 36 | SV_TIMER_MODE_240Hz = $10 ; else 15360 37 | 38 | 39 | ; low activ/pressed 40 | sv_control = $2020 41 | SV_RIGHT = 1 42 | SV_LEFT = 2 43 | SV_DOWN = 4 44 | SV_UP = 8 45 | SV_BUTTONB = $10 46 | SV_BUTTONA = $20 47 | SV_SELECT = $40 48 | SV_START = $80 49 | 50 | ; frequency=125000/counter 51 | sv_audio_right_counter = $2010 ;word 52 | sv_audio_left_counter = $2014 53 | SV_AUDIO_ON =$40 54 | ;bits 0..3 volume 55 | ; bit 4 ? 56 | ; bit 5 ? 57 | sv_audio_right_control = $2012 58 | sv_audio_left_control = $2016 59 | ; write activates tone for x/60 sec (0 means 256) 60 | sv_audio_right_timer = $2013 61 | sv_audio_left_timer = $2017 62 | 63 | 64 | ;read for irq quitting 65 | sv_dma_quit = $2025 66 | sv_dma_on = $201c 67 | ; bit 7 true start, false stop 68 | sv_dma_start = $2018 ; word 69 | sv_dma_size = $201a ; *32 samples 70 | sv_dma_control = $201b 71 | ; bit 0,1 speed: 0 15360, 11 15360/4 72 | ; bit 2,3 volume: 0 silent, 11 loud 73 | 74 | sv_noise_volume = $2028 ; and frequency 75 | sv_noise_timer = $2029 76 | sv_noise_control = $202a 77 | -------------------------------------------------------------------------------- /firmware/floppysrc/vector.lc: -------------------------------------------------------------------------------- 1 | SYMBOLS { 2 | __STACKSIZE__: type = weak, value = $400; 3 | __RAM_SIZE__: type = weak, value = $47FF; 4 | __RAM_START__: type = weak, value = $0800; 5 | } 6 | 7 | MEMORY { 8 | ZP: start = $0080, size = $001A, define = yes; 9 | RAM1: start = $0800, size=$47FF, file=%O; 10 | } 11 | 12 | SEGMENTS { 13 | STARTUP: load = RAM1, type = ro; 14 | CODE: load = RAM1, type = ro, define = yes; 15 | INIT: load = RAM1, type = ro, define = yes, optional = yes; 16 | RODATA: load = RAM1, type = ro; 17 | DATA: load = RAM1, type = rw, run = RAM1, define = yes; 18 | BSS: load = RAM1, type = bss, define = yes; 19 | ZEROPAGE: load = ZP, type = zp; 20 | } 21 | 22 | FEATURES { 23 | CONDES: segment = RODATA, 24 | type = constructor, 25 | label = __CONSTRUCTOR_TABLE__, 26 | count = __CONSTRUCTOR_COUNT__; 27 | CONDES: segment = RODATA, 28 | type = destructor, 29 | label = __DESTRUCTOR_TABLE__, 30 | count = __DESTRUCTOR_COUNT__; 31 | } 32 | 33 | -------------------------------------------------------------------------------- /project/de1/vector06cc.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP2C20F484) Path("reports/") File("vector06cc.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /project/de1/vector06cc.dpf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /project/de1/vector06cc.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /project/de1/vector06cc.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2007 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "7.1" 18 | DATE = "22:55:30 October 17, 2007" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "vector06cc" 24 | -------------------------------------------------------------------------------- /project/de1/vector06cc.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/project/de1/vector06cc.qws -------------------------------------------------------------------------------- /project/de1sram/vector06cc.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP2C20F484) Path("reports/") File("vector06cc.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /project/de1sram/vector06cc.dpf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /project/de1sram/vector06cc.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /project/de1sram/vector06cc.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2007 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "7.1" 18 | DATE = "22:55:30 October 17, 2007" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "vector06cc" 24 | -------------------------------------------------------------------------------- /project/de1sram/vector06cc.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/project/de1sram/vector06cc.qws -------------------------------------------------------------------------------- /project/wxeda/vector06cc.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP4CE6E22) Path("reports/") File("vector06cc.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /project/wxeda/vector06cc.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /project/wxeda/vector06cc.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2007 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "7.1" 18 | DATE = "22:55:30 October 17, 2007" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "vector06cc" 24 | -------------------------------------------------------------------------------- /project/wxeda/vector06cc.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /scripts/makezip.py: -------------------------------------------------------------------------------- 1 | import time 2 | import datetime 3 | import os 4 | 5 | 6 | repurl='http://vector06cc.googlecode.com/svn/trunk/' 7 | 8 | print 'Querying repository %s' % repurl 9 | 10 | pipa = os.popen('svn info %s' % repurl) 11 | results = pipa.read().rsplit() 12 | pipa.close() 13 | irev = results.index('Revision:') 14 | revidx = results[irev+1] 15 | 16 | zipfilename='vector06cc-src-%d%d%d-rev%s.zip' % tuple(list(time.localtime()[0:3]) + [revidx]) 17 | 18 | print 'Creating zip: ', zipfilename 19 | 20 | dirname='vector06cc-rev%s' % revidx 21 | 22 | print 'Checking out source tree to %s' % dirname 23 | 24 | os.system('svn export %s %s' % (repurl,dirname)) 25 | os.system('zip -r %s %s' % (zipfilename,dirname)) 26 | os.system('rd /s/q %s' % dirname) 27 | -------------------------------------------------------------------------------- /scripts/uploader.bat: -------------------------------------------------------------------------------- 1 | del /q *.zip 2 | makezip.py 3 | for %%z in (*.zip) do googlecode_upload.py -s "svn snapshot" -p vector06cc %%z 4 | del /q *.zip -------------------------------------------------------------------------------- /src/DE1/CLK_LOCK.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | 14 | // ============================================================ 15 | // File Name: CLK_LOCK.v 16 | // Megafunction Name(s): 17 | // altclkctrl 18 | // ============================================================ 19 | // ************************************************************ 20 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 21 | // 22 | // 5.0 Build 168 06/22/2005 SP 1 SJ Full Version 23 | // ************************************************************ 24 | 25 | 26 | //Copyright (C) 1991-2005 Altera Corporation 27 | //Your use of Altera Corporation's design tools, logic functions 28 | //and other software and tools, and its AMPP partner logic 29 | //functions, and any output files any of the foregoing 30 | //(including device programming or simulation files), and any 31 | //associated documentation or information are expressly subject 32 | //to the terms and conditions of the Altera Program License 33 | //Subscription Agreement, Altera MegaCore Function License 34 | //Agreement, or other applicable license agreement, including, 35 | //without limitation, that your use is for the sole purpose of 36 | //programming logic devices manufactured by Altera and sold by 37 | //Altera or its authorized distributors. Please refer to the 38 | //applicable agreement for further details. 39 | 40 | 41 | //altclkctrl clock_type="Global Clock" DEVICE_FAMILY="CYCLONE II" clkselect ena inclk outclk 42 | //VERSION_BEGIN 5.0 cbx_altclkbuf 2004:11:30:11:29:52:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END 43 | 44 | //synthesis_resources = clkctrl 1 45 | //synopsys translate_off 46 | `timescale 1 ps / 1 ps 47 | //synopsys translate_on 48 | module CLK_LOCK_altclkctrl_tb8 49 | ( 50 | clkselect, 51 | ena, 52 | inclk, 53 | outclk) /* synthesis synthesis_clearbox=1 */; 54 | input [1:0] clkselect; 55 | input ena; 56 | input [3:0] inclk; 57 | output outclk; 58 | 59 | wire wire_clkctrl1_outclk; 60 | 61 | cycloneii_clkctrl clkctrl1 62 | ( 63 | .clkselect(clkselect), 64 | .ena(ena), 65 | .inclk(inclk), 66 | .outclk(wire_clkctrl1_outclk)); 67 | defparam 68 | clkctrl1.clock_type = "Global Clock", 69 | clkctrl1.ena_register_mode = "none", 70 | clkctrl1.lpm_type = "cycloneii_clkctrl"; 71 | assign 72 | outclk = wire_clkctrl1_outclk; 73 | endmodule //CLK_LOCK_altclkctrl_tb8 74 | //VALID FILE 75 | 76 | 77 | // synopsys translate_off 78 | `timescale 1 ps / 1 ps 79 | // synopsys translate_on 80 | module CLK_LOCK ( 81 | inclk, 82 | outclk)/* synthesis synthesis_clearbox = 1 */; 83 | 84 | input inclk; 85 | output outclk; 86 | 87 | wire sub_wire0; 88 | wire sub_wire1 = 1'h1; 89 | wire [2:0] sub_wire4 = 3'h0; 90 | wire [1:0] sub_wire5 = 2'h0; 91 | wire outclk = sub_wire0; 92 | wire sub_wire2 = inclk; 93 | wire [3:0] sub_wire3 = {sub_wire4, sub_wire2}; 94 | 95 | CLK_LOCK_altclkctrl_tb8 CLK_LOCK_altclkctrl_tb8_component ( 96 | .ena (sub_wire1), 97 | .inclk (sub_wire3), 98 | .clkselect (sub_wire5), 99 | .outclk (sub_wire0)); 100 | 101 | endmodule 102 | 103 | // ============================================================ 104 | // CNX file retrieval info 105 | // ============================================================ 106 | // Retrieval info: PRIVATE: clock_inputs NUMERIC "1" 107 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 108 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 109 | // Retrieval info: CONSTANT: clock_type STRING "Global Clock" 110 | // Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk" 111 | // Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk" 112 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0 113 | // Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0 114 | // Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0 115 | // Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0 116 | // Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0 117 | // Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.v TRUE FALSE 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.inc FALSE FALSE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.cmp FALSE FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.bsf FALSE FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_inst.v FALSE FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_bb.v FALSE FALSE 123 | -------------------------------------------------------------------------------- /src/DE1/I2C_AV_Config.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module I2C_AV_Config ( // Host Side 14 | iCLK, 15 | iRST_N, 16 | // I2C Side 17 | I2C_SCLK, 18 | I2C_SDAT ); 19 | // Host Side 20 | input iCLK; 21 | input iRST_N; 22 | // I2C Side 23 | output I2C_SCLK; 24 | inout I2C_SDAT; 25 | // Internal Registers/Wires 26 | reg [15:0] mI2C_CLK_DIV; 27 | reg [23:0] mI2C_DATA; 28 | reg mI2C_CTRL_CLK; 29 | reg mI2C_GO; 30 | wire mI2C_END; 31 | wire mI2C_ACK; 32 | reg [15:0] LUT_DATA; 33 | reg [3:0] LUT_INDEX; 34 | reg [1:0] mSetup_ST; 35 | 36 | // Clock Setting 37 | parameter CLK_Freq = 50000000; // 50 MHz 38 | parameter I2C_Freq = 20000; // 20 KHz 39 | // LUT Data Number 40 | parameter LUT_SIZE = 11; 41 | // Audio Data Index 42 | parameter Dummy_DATA = 0; 43 | parameter SET_LIN_L = 1; 44 | parameter SET_LIN_R = 2; 45 | parameter SET_HEAD_L = 3; 46 | parameter SET_HEAD_R = 4; 47 | parameter A_PATH_CTRL = 5; 48 | parameter D_PATH_CTRL = 6; 49 | parameter POWER_ON = 7; 50 | parameter SET_FORMAT = 8; 51 | parameter SAMPLE_CTRL = 9; 52 | parameter SET_ACTIVE = 10; 53 | 54 | ///////////////////// I2C Control Clock //////////////////////// 55 | always@(posedge iCLK or negedge iRST_N) 56 | begin 57 | if(!iRST_N) 58 | begin 59 | mI2C_CTRL_CLK <= 0; 60 | mI2C_CLK_DIV <= 0; 61 | end 62 | else 63 | begin 64 | if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) ) 65 | mI2C_CLK_DIV <= mI2C_CLK_DIV+1'b1; 66 | else 67 | begin 68 | mI2C_CLK_DIV <= 0; 69 | mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK; 70 | end 71 | end 72 | end 73 | //////////////////////////////////////////////////////////////////// 74 | I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock 75 | .I2C_SCLK(I2C_SCLK), // I2C CLOCK 76 | .I2C_SDAT(I2C_SDAT), // I2C DATA 77 | .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA] 78 | .GO(mI2C_GO), // GO transfor 79 | .END(mI2C_END), // END transfor 80 | .ACK(mI2C_ACK), // ACK 81 | .RESET(iRST_N) ); 82 | //////////////////////////////////////////////////////////////////// 83 | ////////////////////// Config Control //////////////////////////// 84 | always@(posedge mI2C_CTRL_CLK or negedge iRST_N) 85 | begin 86 | if(!iRST_N) 87 | begin 88 | LUT_INDEX <= 0; 89 | mSetup_ST <= 0; 90 | mI2C_GO <= 0; 91 | end 92 | else 93 | begin 94 | if(LUT_INDEX= 4) & (SD_COUNTER <=30))? ~CLOCK :1'b0 ); 49 | wire I2C_SDAT=SDO?1'bz:1'b0; 50 | 51 | reg ACK1,ACK2,ACK3; 52 | wire ACK=ACK1 | ACK2 |ACK3; 53 | 54 | //--I2C COUNTER 55 | always @(negedge RESET or posedge CLOCK ) begin 56 | if (!RESET) SD_COUNTER=6'b111111; 57 | else begin 58 | if (GO==0) 59 | SD_COUNTER=0; 60 | else 61 | if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+1'b1; 62 | end 63 | end 64 | //---- 65 | 66 | always @(negedge RESET or posedge CLOCK ) begin 67 | if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end 68 | else 69 | case (SD_COUNTER) 70 | 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end 71 | //start 72 | 6'd1 : begin SD=I2C_DATA;SDO=0;end 73 | 6'd2 : SCLK=0; 74 | //SLAVE ADDR 75 | 6'd3 : SDO=SD[23]; 76 | 6'd4 : SDO=SD[22]; 77 | 6'd5 : SDO=SD[21]; 78 | 6'd6 : SDO=SD[20]; 79 | 6'd7 : SDO=SD[19]; 80 | 6'd8 : SDO=SD[18]; 81 | 6'd9 : SDO=SD[17]; 82 | 6'd10 : SDO=SD[16]; 83 | 6'd11 : SDO=1'b1;//ACK 84 | 85 | //SUB ADDR 86 | 6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end 87 | 6'd13 : SDO=SD[14]; 88 | 6'd14 : SDO=SD[13]; 89 | 6'd15 : SDO=SD[12]; 90 | 6'd16 : SDO=SD[11]; 91 | 6'd17 : SDO=SD[10]; 92 | 6'd18 : SDO=SD[9]; 93 | 6'd19 : SDO=SD[8]; 94 | 6'd20 : SDO=1'b1;//ACK 95 | 96 | //DATA 97 | 6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end 98 | 6'd22 : SDO=SD[6]; 99 | 6'd23 : SDO=SD[5]; 100 | 6'd24 : SDO=SD[4]; 101 | 6'd25 : SDO=SD[3]; 102 | 6'd26 : SDO=SD[2]; 103 | 6'd27 : SDO=SD[1]; 104 | 6'd28 : SDO=SD[0]; 105 | 6'd29 : SDO=1'b1;//ACK 106 | 107 | 108 | //stop 109 | 6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end 110 | 6'd31 : SCLK=1'b1; 111 | 6'd32 : begin SDO=1'b1; END=1; end 112 | 113 | endcase 114 | end 115 | 116 | 117 | 118 | endmodule 119 | 120 | // $Id$ 121 | -------------------------------------------------------------------------------- /src/DE1/RS232_Command.h: -------------------------------------------------------------------------------- 1 | ////////////////// Command Action ///////////////////// 2 | parameter SETUP = 8'h61; 3 | parameter ERASE = 8'h72; 4 | parameter WRITE = 8'h83; 5 | parameter READ = 8'h94; 6 | parameter LCD_DAT = 8'h83; 7 | parameter LCD_CMD = 8'h94; 8 | ////////////////// Command Target ///////////////////// 9 | parameter LED = 8'hF0; 10 | parameter SEG7 = 8'hE1; 11 | parameter PS2 = 8'hD2; 12 | parameter FLASH = 8'hC3; 13 | parameter SDRAM = 8'hB4; 14 | parameter SRAM = 8'hA5; 15 | parameter LCD = 8'h96; 16 | parameter VGA = 8'h87; 17 | parameter SDRSEL = 8'h1F; 18 | parameter FLSEL = 8'h2E; 19 | parameter EXTIO = 8'h3D; 20 | parameter SET_REG = 8'h4C; 21 | parameter SRSEL = 8'h5B; 22 | ////////////////// Command Mode ///////////////////// 23 | parameter OUTSEL = 8'h33; 24 | parameter NORMAL = 8'hAA; 25 | parameter DISPLAY = 8'hCC; 26 | parameter BURST = 8'hFF; -------------------------------------------------------------------------------- /src/DE1/SDRAM_Controller.v: -------------------------------------------------------------------------------- 1 | // Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/ 2 | // 3 | // Modified for vector06cc: Ivan Gorodetsky 4 | 5 | 6 | module SDRAM_Controller( 7 | input clk, // Clock 60 MHz 8 | input reset, // System reset 9 | inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits 10 | output reg[11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits 11 | output reg DRAM_LDQM, // SDRAM Low-byte Data Mask 12 | output reg DRAM_UDQM, // SDRAM High-byte Data Mask 13 | output reg DRAM_WE_N, // SDRAM Write Enable 14 | output reg DRAM_CAS_N, // SDRAM Column Address Strobe 15 | output reg DRAM_RAS_N, // SDRAM Row Address Strobe 16 | output DRAM_CS_N, // SDRAM Chip Select 17 | output DRAM_BA_0, // SDRAM Bank Address 0 18 | output DRAM_BA_1, // SDRAM Bank Address 0 19 | input [21:0] iaddr, 20 | input [15:0] idata, 21 | input rd, 22 | input we_n, 23 | output reg [15:0] odata, 24 | output reg [15:0] odata2, 25 | output reg memcpubusy, 26 | output reg rdcpu_finished, 27 | output reg memvidbusy, 28 | input rdv 29 | ); 30 | 31 | parameter ST_RESET0 = 4'd0; 32 | parameter ST_RESET1 = 4'd1; 33 | parameter ST_IDLE = 4'd2; 34 | parameter ST_RAS0 = 4'd3; 35 | parameter ST_RAS1 = 4'd4; 36 | parameter ST_READ0 = 4'd5; 37 | parameter ST_READ1 = 4'd6; 38 | parameter ST_READ2 = 4'd7; 39 | parameter ST_WRITE0 = 4'd8; 40 | parameter ST_WRITE1 = 4'd9; 41 | parameter ST_WRITE2 = 4'd10; 42 | parameter ST_READV = 4'd11; 43 | parameter ST_REFRESH0 = 4'd12; 44 | parameter ST_REFRESH1 = 4'd13; 45 | 46 | 47 | 48 | reg[3:0] state; 49 | reg[21:0] addr; 50 | reg[15:0] data; 51 | reg exrd,exwen,lsb,rdvid; 52 | 53 | assign DRAM_DQ[7:0] = (state==ST_WRITE0)&&(lsb==0) ? data : 8'bZZZZZZZZ; 54 | assign DRAM_DQ[15:8] = (state==ST_WRITE0)&&(lsb==1) ? data : 8'bZZZZZZZZ; 55 | 56 | assign DRAM_CS_N = 1'b0; 57 | assign DRAM_BA_0 = addr[20]; 58 | assign DRAM_BA_1 = addr[21]; 59 | 60 | always @(*) begin 61 | case (state) 62 | ST_RESET0: DRAM_ADDR = 12'b000000100000; 63 | ST_RAS0: DRAM_ADDR = addr[19:8]; 64 | ST_READ0: if(rdvid==1) DRAM_ADDR = {4'b0000,addr[7:0]}; 65 | else DRAM_ADDR = {4'b0100,addr[7:0]}; 66 | ST_READ1: if(rdvid==1) DRAM_ADDR = {4'b0100,addr[7:1],1'b1}; 67 | ST_WRITE0: DRAM_ADDR = {4'b0100,addr[7:0]}; 68 | endcase 69 | case (state) 70 | ST_RESET0: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N} = 3'b000; 71 | ST_RAS0: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N} = 3'b011; 72 | ST_READ0: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N,DRAM_UDQM,DRAM_LDQM} = 5'b10100; 73 | ST_READ1: if(rdvid==1) {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N,DRAM_UDQM,DRAM_LDQM} = 5'b10100; 74 | ST_WRITE0: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N,DRAM_UDQM,DRAM_LDQM} = {3'b100,~lsb,lsb}; 75 | ST_WRITE2: {DRAM_UDQM,DRAM_LDQM} = 2'b00; 76 | ST_REFRESH0: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N} = 3'b001; 77 | default: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N} = 3'b111; 78 | endcase 79 | end 80 | 81 | always @(posedge clk) begin 82 | if (reset) {state,exrd,exwen,rdvid,memcpubusy,memvidbusy,rdcpu_finished}<={ST_RESET0,6'b010000}; 83 | else begin 84 | case (state) 85 | ST_RESET0: state <= ST_RESET1; 86 | ST_RESET1: state <= ST_IDLE; 87 | ST_IDLE: 88 | begin 89 | {memcpubusy,memvidbusy,rdcpu_finished}<=3'b000; 90 | if(rdv==0){exrd,exwen} <= {rd,we_n}; 91 | {addr[17:0],lsb,data,rdvid}<={iaddr[18:1],iaddr[0],idata,rdv}; 92 | casex ({rd,exrd,we_n,exwen,rdv}) 93 | 5'b10110: {state,memcpubusy} <= {ST_RAS0,1'b1}; 94 | 5'b00010: {state,memcpubusy} <= {ST_RAS0,1'b1}; 95 | 5'bxxxx1: {state,memvidbusy} <= {ST_RAS0,1'b1}; 96 | default: state <= ST_IDLE; 97 | endcase 98 | end 99 | ST_RAS0: state<=ST_RAS1; 100 | ST_RAS1: 101 | casex ({exrd,exwen,rdvid}) 102 | 3'b110: state <= ST_READ0; 103 | 3'b000: state <= ST_WRITE0; 104 | 3'bxx1: state <= ST_READ0; 105 | default: state <= ST_IDLE; 106 | endcase 107 | ST_READ0: state <= ST_READ1; 108 | ST_READ1: state <= ST_READ2; 109 | ST_READ2: begin 110 | case(rdvid) 111 | 1'b0:{state,rdcpu_finished,odata[7:0]}<={ST_IDLE,1'b1,lsb?DRAM_DQ[15:8]:DRAM_DQ[7:0]}; 112 | 1'b1:{state,odata} <= {ST_READV,DRAM_DQ[15:0]}; 113 | endcase 114 | end 115 | ST_READV: {state,odata2} <= {ST_REFRESH0,DRAM_DQ[15:0]}; 116 | 117 | ST_WRITE0: state <= ST_WRITE1; 118 | ST_WRITE1: state <= ST_WRITE2; 119 | ST_WRITE2: state <= ST_IDLE; 120 | ST_REFRESH0: state <= ST_REFRESH1; 121 | ST_REFRESH1: state <= ST_IDLE; 122 | default: state <= ST_IDLE; 123 | endcase 124 | end 125 | end 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /src/DE1/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module SEG7_LUT ( oSEG,iDIG ); 14 | input [3:0] iDIG; 15 | output [6:0] oSEG; 16 | reg [6:0] oSEG; 17 | 18 | always @(iDIG) 19 | begin 20 | case(iDIG) 21 | 4'h1: oSEG = 7'b1111001; // ---t---- 22 | 4'h2: oSEG = 7'b0100100; // | | 23 | 4'h3: oSEG = 7'b0110000; // lt rt 24 | 4'h4: oSEG = 7'b0011001; // | | 25 | 4'h5: oSEG = 7'b0010010; // ---m---- 26 | 4'h6: oSEG = 7'b0000010; // | | 27 | 4'h7: oSEG = 7'b1111000; // lb rb 28 | 4'h8: oSEG = 7'b0000000; // | | 29 | 4'h9: oSEG = 7'b0011000; // ---b---- 30 | 4'ha: oSEG = 7'b0001000; 31 | 4'hb: oSEG = 7'b0000011; 32 | 4'hc: oSEG = 7'b1000110; 33 | 4'hd: oSEG = 7'b0100001; 34 | 4'he: oSEG = 7'b0000110; 35 | 4'hf: oSEG = 7'b0001110; 36 | 4'h0: oSEG = 7'b1000000; 37 | endcase 38 | end 39 | endmodule 40 | 41 | module SEG7_LUT_4 ( oSEG0,oSEG1,oSEG2,oSEG3,iDIG ); 42 | input [15:0] iDIG; 43 | output [6:0] oSEG0,oSEG1,oSEG2,oSEG3; 44 | 45 | SEG7_LUT u0 ( oSEG0,iDIG[3:0] ); 46 | SEG7_LUT u1 ( oSEG1,iDIG[7:4] ); 47 | SEG7_LUT u2 ( oSEG2,iDIG[11:8] ); 48 | SEG7_LUT u3 ( oSEG3,iDIG[15:12] ); 49 | 50 | endmodule 51 | 52 | // $Id$ 53 | -------------------------------------------------------------------------------- /src/DE1/USB_JTAG.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module USB_JTAG ( // HOST 14 | iTxD_DATA,oTxD_Done,iTxD_Start, 15 | oRxD_DATA,oRxD_Ready,iRST_n,iCLK, 16 | // JTAG 17 | TDO,TDI,TCS,TCK ); 18 | input [7:0] iTxD_DATA; 19 | input iTxD_Start,iRST_n,iCLK; 20 | output reg [7:0] oRxD_DATA; 21 | output reg oTxD_Done,oRxD_Ready; 22 | input TDI,TCS,TCK; 23 | output TDO; 24 | wire [7:0] mRxD_DATA; 25 | wire mTxD_Done,mRxD_Ready; 26 | reg Pre_TxD_Done,Pre_RxD_Ready; 27 | reg mTCK; 28 | //////////// JTAG CLK Sync. /////////////// 29 | always@(posedge iCLK) mTCK<=TCK; 30 | ///////////////// JTAG Receiver /////////////// 31 | JTAG_REC u0 (mRxD_DATA,mRxD_Ready,TDI,TCS,mTCK); 32 | // JTAG Receiver Sync. 33 | always@(posedge iCLK or negedge iRST_n) 34 | begin 35 | if(!iRST_n) 36 | begin 37 | oRxD_Ready<=0; 38 | Pre_RxD_Ready<=0; 39 | end 40 | else 41 | begin 42 | Pre_RxD_Ready<=mRxD_Ready; 43 | if({Pre_RxD_Ready,mRxD_Ready}==2'b01 && ~iTxD_Start) 44 | begin 45 | oRxD_Ready<=1; 46 | oRxD_DATA<=mRxD_DATA; 47 | end 48 | else 49 | oRxD_Ready<=0; 50 | end 51 | end 52 | /////////////////////////////////////////////////// 53 | ///////////// JTAG Transmitter /////////////// 54 | JTAG_TRANS u1 (iTxD_DATA,iTxD_Start,mTxD_Done,TDO,TCK,TCS); 55 | // JTAG Transmitter Sync. 56 | always@(posedge iCLK or negedge iRST_n) 57 | begin 58 | if(!iRST_n) 59 | begin 60 | oTxD_Done<=0; 61 | Pre_TxD_Done<=0; 62 | end 63 | else 64 | begin 65 | Pre_TxD_Done<=mTxD_Done; 66 | if({Pre_TxD_Done,mTxD_Done}==2'b01) 67 | oTxD_Done<=1; 68 | else 69 | oTxD_Done<=0; 70 | end 71 | end 72 | /////////////////////////////////////////////////// 73 | endmodule 74 | 75 | module JTAG_REC ( // HOST 76 | oRxD_DATA,oRxD_Ready, 77 | // JTAG 78 | TDI,TCS,TCK ); 79 | input TDI,TCS,TCK; 80 | output reg [7:0] oRxD_DATA; 81 | output reg oRxD_Ready; 82 | reg [7:0] rDATA; 83 | reg [2:0] rCont; 84 | always@(posedge TCK or posedge TCS) 85 | begin 86 | if(TCS) 87 | begin 88 | oRxD_Ready<=0; 89 | rCont<=0; 90 | end 91 | else 92 | begin 93 | rCont<=rCont+1'd1; 94 | rDATA<={TDI,rDATA[7:1]}; 95 | if(rCont==0) 96 | begin 97 | oRxD_DATA<={TDI,rDATA[7:1]}; 98 | oRxD_Ready<=1; 99 | end 100 | else 101 | oRxD_Ready<=0; 102 | end 103 | end 104 | endmodule 105 | 106 | module JTAG_TRANS( // HOST 107 | iTxD_DATA,iTxD_Start,oTxD_Done, 108 | // JTAG 109 | TDO,TCK,TCS ); 110 | input [7:0] iTxD_DATA; 111 | input iTxD_Start; 112 | output reg oTxD_Done; 113 | input TCK,TCS; 114 | output reg TDO; 115 | reg [2:0] rCont; 116 | always@(posedge TCK or posedge TCS) 117 | begin 118 | if(TCS) 119 | begin 120 | oTxD_Done<=0; 121 | rCont<=0; 122 | TDO<=0; 123 | end 124 | else 125 | begin 126 | if(iTxD_Start) 127 | begin 128 | rCont<=rCont+1'd1; 129 | TDO<=iTxD_DATA[rCont]; 130 | end 131 | else 132 | begin 133 | rCont<=0; 134 | TDO<=0; 135 | end 136 | if(rCont==7) 137 | oTxD_Done<=1; 138 | else 139 | oTxD_Done<=0; 140 | end 141 | end 142 | 143 | endmodule 144 | 145 | // $Id$ -------------------------------------------------------------------------------- /src/DE1/audio_io.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Stereo and DSP Mode by Ivan Gorodetsky 15 | // 16 | // Design File: audio_io.v 17 | // 18 | // Low-level i/o interface to audio codec. 19 | // Based on development board example: 20 | // 21 | // Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your 22 | // use of Altera Corporation's design tools, logic functions and other 23 | // software and tools, and its AMPP partner logic functions, and any 24 | // output files any of the foregoing (including device programming or 25 | // simulation files), and any associated documentation or information are 26 | // expressly subject to the terms and conditions of the Altera Program 27 | // License Subscription Agreement or other applicable license agreement, 28 | // including, without limitation, that your use is for the sole purpose 29 | // of programming logic devices manufactured by Altera and sold by Altera 30 | // or its authorized distributors. Please refer to the applicable 31 | // agreement for further details. 32 | // 33 | // -------------------------------------------------------------------- 34 | module audio_io( 35 | oAUD_BCK, 36 | oAUD_DATA, 37 | oAUD_LRCK, 38 | iAUD_ADCDAT, 39 | oAUD_ADCLRCK, 40 | iCLK12, 41 | iRST_N, 42 | pulsesL, 43 | pulsesR, 44 | linein); 45 | 46 | parameter REF_CLK = 12000000; // 12 MHz 47 | parameter SAMPLE_RATE = 48000; // 48 kHz 48 | parameter DATA_WIDTH = 16; // 16 Bits 49 | parameter CHANNEL_NUM = 2; // Dual Channel 50 | 51 | // Audio Side 52 | output oAUD_DATA; 53 | output oAUD_LRCK; 54 | output oAUD_BCK=iCLK12; 55 | input iAUD_ADCDAT; 56 | output oAUD_ADCLRCK; 57 | // Control Signals 58 | input iCLK12; 59 | input iRST_N; 60 | input [15:0] pulsesL; 61 | input [15:0] pulsesR; 62 | output [15:0] linein; 63 | 64 | // Internal Registers and Wires 65 | reg [3:0] BCK_DIV; 66 | reg [8:0] LRCK_1X_DIV; 67 | reg [5:0] SEL_Cont; 68 | 69 | reg LRCK_1X; 70 | 71 | always@(negedge oAUD_BCK or negedge iRST_N) 72 | begin 73 | if(!iRST_N) begin 74 | LRCK_1X_DIV <= 0; 75 | LRCK_1X <= 0; 76 | end 77 | else if(LRCK_1X_DIV>=REF_CLK/SAMPLE_RATE-1) begin 78 | LRCK_1X_DIV <= 0; 79 | LRCK_1X <= 1; 80 | end 81 | else begin 82 | LRCK_1X_DIV <= LRCK_1X_DIV+1'd1; 83 | LRCK_1X <= 0; 84 | end 85 | end 86 | 87 | 88 | assign oAUD_LRCK = LRCK_1X; 89 | assign oAUD_ADCLRCK= oAUD_LRCK; 90 | 91 | ////////////////////////////////////////////////// 92 | ////////// 16 Bits PISO MSB First ////////////// 93 | always@(negedge oAUD_BCK or negedge iRST_N) 94 | begin 95 | if(!iRST_N) SEL_Cont <= 0; 96 | else if(oAUD_LRCK==1) 97 | SEL_Cont <= 0; 98 | else if(SEL_Cont!=6'd32) 99 | SEL_Cont <= SEL_Cont+1'd1; 100 | end 101 | 102 | 103 | reg [31:0] pulsebuf; 104 | always @(posedge LRCK_1X) begin 105 | pulsebuf[15:0] <= pulsesR;//R 106 | pulsebuf[31:16] <= pulsesL;//L 107 | end 108 | 109 | assign oAUD_DATA = pulsebuf[~SEL_Cont]; 110 | 111 | assign linein = inputsample; 112 | reg [15:0] inputsample; 113 | reg [15:0] inputbuf; 114 | always @(negedge oAUD_BCK) begin 115 | if(SEL_Cont!=6'd32)inputbuf[~SEL_Cont[3:0]] <= iAUD_ADCDAT; 116 | end 117 | 118 | always @(posedge LRCK_1X) begin 119 | inputsample <= inputbuf;//only one channel 120 | end 121 | 122 | endmodule -------------------------------------------------------------------------------- /src/DE1/clockster.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007-2016 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Modified by Ivan Gorodetsky 15 | // 16 | // Design File: clockster.v 17 | // 18 | // Vector-06C clock generator. 19 | // 20 | // -------------------------------------------------------------------- 21 | 22 | `default_nettype none 23 | 24 | module clockster(clk, clk50, clk24, clkAudio, ce12, ce6, ce6x, ce3, video_slice, pipe_ab, ce1m5, 25 | clkpalFSC, clk60, clk_color_mod); 26 | input [1:0] clk; 27 | input clk50; 28 | output clk24; 29 | output clkAudio = qce12; 30 | output ce12 = qce12; 31 | output ce6 = qce6; 32 | output ce6x = qce6x; 33 | output ce3 = qce3; 34 | output video_slice = qvideo_slice; 35 | output pipe_ab = qpipe_ab; 36 | output ce1m5 = qce1m5; 37 | output clkpalFSC; 38 | output clk60; 39 | output clk_color_mod; 40 | 41 | reg[5:0] ctr; 42 | reg[4:0] initctr; 43 | 44 | reg qce12, qce6, qce6x, qce3, qce3v, qvideo_slice, qpipe_ab, qce1m5; 45 | 46 | wire lock; 47 | 48 | wire clk300; 49 | 50 | mclk24mhz vector_xtal(clk50, clk24, clk300, clk60, lock); 51 | 52 | colorpll(.inclk0(clk[0]), .c0(clk_color_mod)); 53 | 54 | // Derive clock for PAL subcarrier: 4x 4.43361875 55 | `define PHACC_WIDTH 32 56 | //`define PHACC_DELTA 253896634 57 | //`define PHACC_DELTA 507793268 58 | `define PHACC_DELTA 1015586535 59 | 60 | reg [`PHACC_WIDTH-1:0] pal_phase; 61 | wire [`PHACC_WIDTH-1:0] pal_phase_next; 62 | assign pal_phase_next = pal_phase + `PHACC_DELTA; 63 | reg palclkreg; 64 | 65 | always @(posedge clk300) begin 66 | pal_phase <= pal_phase_next; 67 | end 68 | 69 | ayclkdrv clkbufpalfsc(pal_phase[`PHACC_WIDTH-1], clkpalFSC); 70 | 71 | always @(posedge clk24) begin 72 | if (initctr != 3) begin 73 | initctr <= initctr + 1'b1; 74 | end // latch 75 | else begin 76 | qpipe_ab <= ctr[5]; // pipe a/b 2x slower 77 | qce12 <= ctr[0]; // pixel push @12mhz 78 | qce6 <= ctr[1] & ctr[0]; // pixel push @6mhz 79 | qce6x <= ctr[1] & ~ctr[0]; // pre-pixel push @6mhz 80 | 81 | qce3 <= ctr[2] & ctr[1] & !ctr[0]; //00100000 - svofski 82 | 83 | qvideo_slice <= !ctr[2]; 84 | qce1m5 <= !ctr[3] & ctr[2] & ctr[1] & !ctr[0]; 85 | ctr <= ctr + 1'b1; 86 | end 87 | end 88 | endmodule 89 | -------------------------------------------------------------------------------- /src/DE1/colorpll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/DE1/colorpll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "colorpll.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "colorpll_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "colorpll.ppf"] 6 | -------------------------------------------------------------------------------- /src/DE1/soundcodec.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Modified by Ivan Gorodetsky 15 | // 16 | // Design File: soundcodec.v 17 | // 18 | // Audio interface between raw audio pulses from 8253, tape i/o and 19 | // sound codec. Includes simple moving average filter for all but 20 | // tape signals. 21 | // 22 | // -------------------------------------------------------------------- 23 | 24 | `default_nettype none 25 | 26 | module soundcodec(clk12, 27 | pulses, 28 | ay_soundA,ay_soundB,ay_soundC, 29 | rs_soundA,rs_soundB,rs_soundC, 30 | covox, 31 | tapein, reset_n, oAUD_XCK, oAUD_BCK, oAUD_DATA, oAUD_LRCK, iAUD_ADCDAT, oAUD_ADCLRCK); 32 | input clk12; 33 | input [3:0] pulses; 34 | input [7:0] ay_soundA; 35 | input [7:0] ay_soundB; 36 | input [7:0] ay_soundC; 37 | input [7:0] rs_soundA; 38 | input [7:0] rs_soundB; 39 | input [7:0] rs_soundC; 40 | input [7:0] covox; 41 | output reg tapein; 42 | input reset_n; 43 | output oAUD_XCK = clk12; 44 | output oAUD_BCK; 45 | output oAUD_DATA; 46 | output oAUD_LRCK; 47 | input iAUD_ADCDAT; 48 | output oAUD_ADCLRCK; 49 | 50 | parameter HYST = 4; 51 | 52 | reg [7:0] decimator; 53 | always @(posedge clk12) decimator <= decimator + 1'd1; 54 | 55 | wire ma_ce = decimator == 0; 56 | 57 | 58 | wire [15:0] linein; // comes from codec 59 | reg [15:0] ma_pulseL,ma_pulseR; // goes to codec 60 | 61 | reg [7:0] pulses_sample[0:3]; 62 | 63 | // sample * 16 64 | wire [5:0] m04 = {pulses[0], 4'b0}; 65 | wire [5:0] m14 = {pulses[1], 4'b0}; 66 | wire [5:0] m24 = {pulses[2], 4'b0}; 67 | wire [5:0] m34 = {pulses[3], 4'b0}; 68 | 69 | reg [7:0] sum; 70 | 71 | always @(posedge clk12) begin 72 | if (ma_ce) begin 73 | pulses_sample[3] <= pulses_sample[2]; 74 | pulses_sample[2] <= pulses_sample[1]; 75 | pulses_sample[1] <= pulses_sample[0]; 76 | pulses_sample[0] <= m04 + m14 + m24/* + m34*/; 77 | sum <= pulses_sample[0] + pulses_sample[1] + pulses_sample[2] + pulses_sample[3]; 78 | end 79 | ma_pulseL <= {sum[7:1],7'b0}+{m34,8'b0}+{ay_soundC,4'b0}+{ay_soundB,3'b0}+{rs_soundC,4'b0}+{rs_soundB,3'b0}+{covox,4'b0}; 80 | ma_pulseR <= {sum[7:1],7'b0}+{m34,8'b0}+{ay_soundA,4'b0}+{ay_soundB,3'b0}+{rs_soundA,4'b0}+{rs_soundB,3'b0}+{covox,4'b0}; 81 | end 82 | 83 | audio_io audioio(oAUD_BCK,oAUD_DATA,oAUD_LRCK,iAUD_ADCDAT,oAUD_ADCLRCK,clk12,reset_n, 84 | {~ma_pulseL[15],ma_pulseL[14:0]}, 85 | {~ma_pulseR[15],ma_pulseR[14:0]}, 86 | linein); 87 | 88 | wire [7:0] line8in = {~linein[15],linein[14:8]}; // shift signed value to be withing 0..255 range, 128 is midpoint 89 | always @(posedge clk12) begin 90 | if (line8in < 128+HYST) tapein <= 1'b0; 91 | if (line8in > 128-HYST) tapein <= 1'b1; 92 | end 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /src/DE1/video/videomod.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007-2016 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // Video outputs, modulated and regular 11 | // 12 | // -------------------------------------------------------------------- 13 | 14 | 15 | `default_nettype none 16 | 17 | module videomod( 18 | input clk_color_mod, 19 | 20 | input [3:0] video_r, 21 | input [3:0] video_g, 22 | input [3:0] video_b, 23 | input vga_hs, 24 | input vga_vs, 25 | input [4:0] tv_cvbs, 26 | input [4:0] tv_luma, 27 | input [4:0] tv_chroma, 28 | input [1:0] tv_mode, 29 | 30 | output VGA_HS, 31 | output VGA_VS, 32 | output [3:0] VGA_R, 33 | output [3:0] VGA_G, 34 | output [3:0] VGA_B, 35 | output S_VIDEO_Y, 36 | output S_VIDEO_C, 37 | output CVBS 38 | ); 39 | 40 | 41 | wire [3:0] tv_out; 42 | 43 | `ifdef WITH_COMPOSITE 44 | `ifdef COMPOSITE_PWM 45 | reg [5:0] cvbs_pwm; 46 | always @(posedge clk_color_mod) 47 | cvbs_pwm <= cvbs_pwm[4:0] + tv_cvbs[4:0]; 48 | assign tv_out = {4{cvbs_pwm[5]}}; 49 | `else 50 | assign tv_out = tv_cvbs[4:1]; 51 | `endif 52 | `else 53 | assign tv_out = 4'b0; 54 | `endif 55 | 56 | `ifdef WITH_SVIDEO 57 | reg [5:0] luma_pwm; 58 | reg [5:0] chroma_pwm; 59 | always @(posedge clk_color_mod) begin 60 | luma_pwm <= luma_pwm[4:0] + tv_luma[4:0]; 61 | chroma_pwm <= chroma_pwm[4:0] + tv_chroma[4:0]; 62 | end 63 | assign S_VIDEO_Y = luma_pwm[5]; 64 | assign S_VIDEO_C = chroma_pwm[5]; 65 | `endif 66 | 67 | `ifdef WITH_COMPOSITE 68 | `ifdef WITH_VGA 69 | assign VGA_R = tv_mode[0] ? tv_out : video_r; 70 | assign VGA_G = tv_mode[0] ? tv_out : video_g; 71 | assign VGA_B = tv_mode[0] ? tv_out : video_b; 72 | `else 73 | assign VGA_R = tv_out; 74 | assign VGA_G = tv_out; 75 | assign VGA_B = tv_out; 76 | `endif 77 | `else 78 | `ifdef WITH_VGA 79 | assign VGA_R = video_r; 80 | assign VGA_G = video_g; 81 | assign VGA_B = video_b; 82 | `else 83 | assign VGA_R = 4'b0; 84 | assign VGA_G = 4'b0; 85 | assign VGA_B = 4'b0; 86 | `endif 87 | `endif 88 | 89 | assign VGA_VS = vga_vs; 90 | assign VGA_HS = vga_hs; 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /src/T80/T8080se.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2007 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 64 64 400 368) 24 | (text "T8080se" (rect 5 0 46 12)(font "Arial" )) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 272) 28 | (input) 29 | (text "RESET_n" (rect 24 64 75 78)(font "Arial" (font_size 8))) 30 | (text "RESET_n" (rect 24 264 75 278)(font "Arial" (font_size 8))) 31 | (line (pt 0 272)(pt 16 272)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 248) 35 | (input) 36 | (text "CLK" (rect 24 240 47 254)(font "Arial" (font_size 8))) 37 | (text "CLK" (rect 24 240 47 254)(font "Arial" (font_size 8))) 38 | (line (pt 0 248)(pt 16 248)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 232) 42 | (input) 43 | (text "CLKEN" (rect 24 224 62 238)(font "Arial" (font_size 8))) 44 | (text "CLKEN" (rect 24 224 62 238)(font "Arial" (font_size 8))) 45 | (line (pt 0 232)(pt 16 232)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 216) 49 | (input) 50 | (text "READY" (rect 24 208 66 222)(font "Arial" (font_size 8))) 51 | (text "READY" (rect 24 208 66 222)(font "Arial" (font_size 8))) 52 | (line (pt 0 216)(pt 16 216)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 200) 56 | (input) 57 | (text "HOLD" (rect 24 192 57 206)(font "Arial" (font_size 8))) 58 | (text "HOLD" (rect 24 192 57 206)(font "Arial" (font_size 8))) 59 | (line (pt 0 200)(pt 16 200)(line_width 1)) 60 | ) 61 | (port 62 | (pt 0 184) 63 | (input) 64 | (text "INT" (rect 24 176 41 190)(font "Arial" (font_size 8))) 65 | (text "INT" (rect 24 176 41 190)(font "Arial" (font_size 8))) 66 | (line (pt 0 184)(pt 16 184)(line_width 1)) 67 | ) 68 | (port 69 | (pt 0 56) 70 | (input) 71 | (text "DI[7..0]" (rect 24 48 62 62)(font "Arial" (font_size 8))) 72 | (text "DI[7..0]" (rect 24 48 62 62)(font "Arial" (font_size 8))) 73 | (line (pt 0 56)(pt 16 56)(line_width 1)) 74 | ) 75 | (port 76 | (pt 336 120) 77 | (output) 78 | (text "INTE" (rect 286 112 310 126)(font "Arial" (font_size 8))) 79 | (text "INTE" (rect 286 112 310 126)(font "Arial" (font_size 8))) 80 | (line (pt 336 120)(pt 320 120)(line_width 1)) 81 | ) 82 | (port 83 | (pt 336 136) 84 | (output) 85 | (text "DBIN" (rect 286 128 313 142)(font "Arial" (font_size 8))) 86 | (text "DBIN" (rect 286 128 313 142)(font "Arial" (font_size 8))) 87 | (line (pt 336 136)(pt 320 136)(line_width 1)) 88 | ) 89 | (port 90 | (pt 336 152) 91 | (output) 92 | (text "SYNC" (rect 286 144 320 158)(font "Arial" (font_size 8))) 93 | (text "SYNC" (rect 286 144 320 158)(font "Arial" (font_size 8))) 94 | (line (pt 336 152)(pt 320 152)(line_width 1)) 95 | ) 96 | (port 97 | (pt 336 168) 98 | (output) 99 | (text "VAIT" (rect 286 160 314 174)(font "Arial" (font_size 8))) 100 | (text "VAIT" (rect 286 160 314 174)(font "Arial" (font_size 8))) 101 | (line (pt 336 168)(pt 320 168)(line_width 1)) 102 | ) 103 | (port 104 | (pt 336 184) 105 | (output) 106 | (text "HLDA" (rect 286 176 319 190)(font "Arial" (font_size 8))) 107 | (text "HLDA" (rect 286 176 319 190)(font "Arial" (font_size 8))) 108 | (line (pt 336 184)(pt 320 184)(line_width 1)) 109 | ) 110 | (port 111 | (pt 336 200) 112 | (output) 113 | (text "WR_n" (rect 286 192 320 206)(font "Arial" (font_size 8))) 114 | (text "WR_n" (rect 286 192 320 206)(font "Arial" (font_size 8))) 115 | (line (pt 336 200)(pt 320 200)(line_width 1)) 116 | ) 117 | (port 118 | (pt 336 80) 119 | (output) 120 | (text "A[15..0]" (rect 286 72 330 86)(font "Arial" (font_size 8))) 121 | (text "A[15..0]" (rect 286 72 330 86)(font "Arial" (font_size 8))) 122 | (line (pt 336 80)(pt 320 80)(line_width 1)) 123 | ) 124 | (port 125 | (pt 336 56) 126 | (output) 127 | (text "DO[7..0]" (rect 286 48 332 62)(font "Arial" (font_size 8))) 128 | (text "DO[7..0]" (rect 286 48 332 62)(font "Arial" (font_size 8))) 129 | (line (pt 336 56)(pt 320 56)(line_width 1)) 130 | ) 131 | (drawing 132 | (rectangle (rect 16 16 320 288)(line_width 1)) 133 | ) 134 | ) 135 | -------------------------------------------------------------------------------- /src/T80/T80_Reg.vhd: -------------------------------------------------------------------------------- 1 | -- **** 2 | -- T80(b) core. In an effort to merge and maintain bug fixes .... 3 | -- 4 | -- 5 | -- Ver 300 started tidyup 6 | -- MikeJ March 2005 7 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) 8 | -- 9 | -- **** 10 | -- 11 | -- T80 Registers, technology independent 12 | -- 13 | -- Version : 0244 14 | -- 15 | -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) 16 | -- 17 | -- All rights reserved 18 | -- 19 | -- Redistribution and use in source and synthezised forms, with or without 20 | -- modification, are permitted provided that the following conditions are met: 21 | -- 22 | -- Redistributions of source code must retain the above copyright notice, 23 | -- this list of conditions and the following disclaimer. 24 | -- 25 | -- Redistributions in synthesized form must reproduce the above copyright 26 | -- notice, this list of conditions and the following disclaimer in the 27 | -- documentation and/or other materials provided with the distribution. 28 | -- 29 | -- Neither the name of the author nor the names of other contributors may 30 | -- be used to endorse or promote products derived from this software without 31 | -- specific prior written permission. 32 | -- 33 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 34 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 35 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 36 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 37 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 38 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 39 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 40 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 41 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 43 | -- POSSIBILITY OF SUCH DAMAGE. 44 | -- 45 | -- Please report bugs to the author, but before you do so, please 46 | -- make sure that this is not a derivative work and that 47 | -- you have the latest version of this file. 48 | -- 49 | -- The latest version of this file can be found at: 50 | -- http://www.opencores.org/cvsweb.shtml/t51/ 51 | -- 52 | -- Limitations : 53 | -- 54 | -- File history : 55 | -- 56 | -- 0242 : Initial release 57 | -- 58 | -- 0244 : Changed to single register file 59 | -- 60 | 61 | library IEEE; 62 | use IEEE.std_logic_1164.all; 63 | use IEEE.numeric_std.all; 64 | 65 | entity T80_Reg is 66 | port( 67 | Clk : in std_logic; 68 | CEN : in std_logic; 69 | WEH : in std_logic; 70 | WEL : in std_logic; 71 | AddrA : in std_logic_vector(2 downto 0); 72 | AddrB : in std_logic_vector(2 downto 0); 73 | AddrC : in std_logic_vector(2 downto 0); 74 | DIH : in std_logic_vector(7 downto 0); 75 | DIL : in std_logic_vector(7 downto 0); 76 | DOAH : out std_logic_vector(7 downto 0); 77 | DOAL : out std_logic_vector(7 downto 0); 78 | DOBH : out std_logic_vector(7 downto 0); 79 | DOBL : out std_logic_vector(7 downto 0); 80 | DOCH : out std_logic_vector(7 downto 0); 81 | DOCL : out std_logic_vector(7 downto 0) 82 | ); 83 | end T80_Reg; 84 | 85 | architecture rtl of T80_Reg is 86 | 87 | type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); 88 | signal RegsH : Register_Image(0 to 7); 89 | signal RegsL : Register_Image(0 to 7); 90 | 91 | begin 92 | 93 | process (Clk) 94 | begin 95 | if Clk'event and Clk = '1' then 96 | if CEN = '1' then 97 | if WEH = '1' then 98 | RegsH(to_integer(unsigned(AddrA))) <= DIH; 99 | end if; 100 | if WEL = '1' then 101 | RegsL(to_integer(unsigned(AddrA))) <= DIL; 102 | end if; 103 | end if; 104 | end if; 105 | end process; 106 | 107 | DOAH <= RegsH(to_integer(unsigned(AddrA))); 108 | DOAL <= RegsL(to_integer(unsigned(AddrA))); 109 | DOBH <= RegsH(to_integer(unsigned(AddrB))); 110 | DOBL <= RegsL(to_integer(unsigned(AddrB))); 111 | DOCH <= RegsH(to_integer(unsigned(AddrC))); 112 | DOCL <= RegsL(to_integer(unsigned(AddrC))); 113 | 114 | end; 115 | -------------------------------------------------------------------------------- /src/altmodules/1200PALL.HEX: -------------------------------------------------------------------------------- 1 | :200000003F16F7A3F9D83430AEDDF30F383524C14A16F7A3F9D83430AEDDF30F383524C1CF 2 | :20002000F116F7A3F9D83430AEDDF30F383524C18316F7A3F9D83430AEDDF30F383524C1C4 3 | :200040004416F7A3F9D83430AEDDF30F383524C16716F7A3F9D83430AEDDF30F383524C16D 4 | :200060009516F7A3F9D83430AEDDF30F383524C1A016F7A3F9D83430AEDDF30F383524C1C3 5 | :200080003F16F7A3F9D83430AEDDF30F383524C14A16F7A3F9D83430AEDDF30F383524C14F 6 | :2000A000F116F7A3F9D83430AEDDF30F383524C18316F7A3F9D83430AEDDF30F383524C144 7 | :2000C0004416F7A3F9D83430AEDDF30F383524C16716F7A3F9D83430AEDDF30F383524C1ED 8 | :2000E0009516F7A3F9D83430AEDDF30F383524C1A016F7A3F9D83430AEDDF30F383524C143 9 | :2001000036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFFFF1D 10 | :2001200036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFFFFFD 11 | :2001400036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFFFFDD 12 | :2001600036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFFFFBD 13 | :2001800036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFFFF9D 14 | :2001A00036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFFFF7D 15 | :2001C00036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFFFF5D 16 | :2001E00036BB0FD00FFFFFFFBBFFFFFFD0FFFFFF36BB0FD00FFFFFFFBBFFFFFFD0FFFF003C 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /src/altmodules/bootrom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "12.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "bootrom.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "bootrom_bb.v"] 5 | -------------------------------------------------------------------------------- /src/altmodules/bootrom1200.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "bootrom1200.v"] 4 | -------------------------------------------------------------------------------- /src/altmodules/mclk24mhz.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2012 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 256 184) 24 | (text "mclk24mhz" (rect 95 0 174 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 168 25 180)(font "Arial" )) 26 | (port 27 | (pt 0 64) 28 | (input) 29 | (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) 30 | (text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8))) 31 | (line (pt 0 64)(pt 40 64)) 32 | ) 33 | (port 34 | (pt 256 64) 35 | (output) 36 | (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) 37 | (text "c0" (rect 240 50 250 63)(font "Arial" (font_size 8))) 38 | ) 39 | (port 40 | (pt 256 80) 41 | (output) 42 | (text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8))) 43 | (text "c1" (rect 240 66 248 79)(font "Arial" (font_size 8))) 44 | ) 45 | (port 46 | (pt 256 96) 47 | (output) 48 | (text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8))) 49 | (text "c2" (rect 240 82 250 95)(font "Arial" (font_size 8))) 50 | ) 51 | (port 52 | (pt 256 112) 53 | (output) 54 | (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8))) 55 | (text "locked" (rect 221 98 250 111)(font "Arial" (font_size 8))) 56 | ) 57 | (drawing 58 | (text "Cyclone II" (rect 198 168 438 347)(font "Arial" )) 59 | (text "inclk0 frequency: 50.000 MHz" (rect 50 59 223 129)(font "Arial" )) 60 | (text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" )) 61 | (text "Clk " (rect 51 93 116 197)(font "Arial" )) 62 | (text "Ratio" (rect 72 93 164 197)(font "Arial" )) 63 | (text "Ph (dg)" (rect 99 93 227 197)(font "Arial" )) 64 | (text "DC (%)" (rect 133 93 296 197)(font "Arial" )) 65 | (text "c0" (rect 54 107 116 225)(font "Arial" )) 66 | (text "12/25" (rect 72 107 165 225)(font "Arial" )) 67 | (text "0.00" (rect 105 107 226 225)(font "Arial" )) 68 | (text "50.00" (rect 137 107 295 225)(font "Arial" )) 69 | (text "c1" (rect 54 121 115 253)(font "Arial" )) 70 | (text "6/1" (rect 77 121 164 253)(font "Arial" )) 71 | (text "0.00" (rect 105 121 226 253)(font "Arial" )) 72 | (text "50.00" (rect 137 121 295 253)(font "Arial" )) 73 | (text "c2" (rect 54 135 116 281)(font "Arial" )) 74 | (text "6/5" (rect 77 135 165 281)(font "Arial" )) 75 | (text "0.00" (rect 105 135 226 281)(font "Arial" )) 76 | (text "50.00" (rect 137 135 295 281)(font "Arial" )) 77 | (line (pt 0 0)(pt 257 0)) 78 | (line (pt 257 0)(pt 257 185)) 79 | (line (pt 0 185)(pt 257 185)) 80 | (line (pt 0 0)(pt 0 185)) 81 | (line (pt 48 91)(pt 165 91)) 82 | (line (pt 48 104)(pt 165 104)) 83 | (line (pt 48 118)(pt 165 118)) 84 | (line (pt 48 132)(pt 165 132)) 85 | (line (pt 48 146)(pt 165 146)) 86 | (line (pt 48 91)(pt 48 146)) 87 | (line (pt 69 91)(pt 69 146)(line_width 3)) 88 | (line (pt 96 91)(pt 96 146)(line_width 3)) 89 | (line (pt 130 91)(pt 130 146)(line_width 3)) 90 | (line (pt 164 91)(pt 164 146)) 91 | (line (pt 40 48)(pt 207 48)) 92 | (line (pt 207 48)(pt 207 167)) 93 | (line (pt 40 167)(pt 207 167)) 94 | (line (pt 40 48)(pt 40 167)) 95 | (line (pt 255 64)(pt 207 64)) 96 | (line (pt 255 80)(pt 207 80)) 97 | (line (pt 255 96)(pt 207 96)) 98 | (line (pt 255 112)(pt 207 112)) 99 | ) 100 | ) 101 | -------------------------------------------------------------------------------- /src/altmodules/mclk24mhz.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/altmodules/mclk24mhz.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "12.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mclk24mhz.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mclk24mhz.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mclk24mhz.ppf"] 6 | -------------------------------------------------------------------------------- /src/altmodules/palette_rom.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "palette_rom.v"] 4 | -------------------------------------------------------------------------------- /src/altmodules/pll120.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/altmodules/pll120.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "12.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll120.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll120_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll120.ppf"] 6 | -------------------------------------------------------------------------------- /src/ay/ay8910.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/src/ay/ay8910.vhd -------------------------------------------------------------------------------- /src/ay/ayglue.v: -------------------------------------------------------------------------------- 1 | module ayglue(clk, ce, reset_n, address, data, wren, rden, q, soundA,soundB,soundC,odataoe); 2 | input clk; 3 | input ce; 4 | input reset_n; 5 | input address; // port 14 (00) = data; port 15 (01) = address 6 | input [7:0] data; 7 | input wren; 8 | input rden; 9 | output reg[7:0] q; 10 | output odataoe; 11 | 12 | output[7:0] soundA; 13 | output[7:0] soundB; 14 | output[7:0] soundC; 15 | 16 | wire [7:0] odata; 17 | wire odataoe; 18 | 19 | 20 | reg [2:0] ctl; // {I_BDIR,I_BC2,I_BC1} 21 | always begin 22 | case ({address,wren,rden}) 23 | 3'b110: ctl <= 3'b111; // write addr 24 | 3'b010: ctl <= 3'b110; // wr data 25 | 3'b001: ctl <= 3'b011; // rd data 26 | default: ctl <= 3'b010; 27 | endcase 28 | end 29 | 30 | //ay8910 digeridoo( 31 | ym2149 digeridoo( 32 | .DI(data), 33 | .DO(q), 34 | .BDIR(ctl[2]), 35 | .BC(ctl[0]), 36 | .OUT_A(soundA), 37 | .OUT_B(soundB), 38 | .OUT_C(soundC), 39 | .CS(1'b1), 40 | .ENA(ce), 41 | .RESET(~reset_n), 42 | .CLK(clk) 43 | ); 44 | 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /src/ay/ym2149.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/src/ay/ym2149.vhd -------------------------------------------------------------------------------- /src/border_delay.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007-2009 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Authors: Ivan Gorodetsky, Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: border_delay.v 15 | // 16 | // -------------------------------------------------------------------- 17 | 18 | `default_nettype none 19 | 20 | module border_delay(input clk, input ce, input[3:0] i_borderindex, output[3:0] o_delayed); 21 | parameter DELAY; 22 | reg[DELAY-1:0] bob[3:0]; 23 | always @(posedge clk) 24 | if (ce) 25 | begin 26 | bob[0] <= {bob[0][DELAY-2:0], i_borderindex[0]}; 27 | bob[1] <= {bob[1][DELAY-2:0], i_borderindex[1]}; 28 | bob[2] <= {bob[2][DELAY-2:0], i_borderindex[2]}; 29 | bob[3] <= {bob[3][DELAY-2:0], i_borderindex[3]}; 30 | end 31 | assign o_delayed = {bob[3][DELAY-1], bob[2][DELAY-1], bob[1][DELAY-1], bob[0][DELAY-1]}; 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /src/de1sram/audio_io.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: audio_io.v 15 | // 16 | // Low-level i/o interface to audio codec. 17 | // Based on development board example: 18 | // 19 | // Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your 20 | // use of Altera Corporation's design tools, logic functions and other 21 | // software and tools, and its AMPP partner logic functions, and any 22 | // output files any of the foregoing (including device programming or 23 | // simulation files), and any associated documentation or information are 24 | // expressly subject to the terms and conditions of the Altera Program 25 | // License Subscription Agreement or other applicable license agreement, 26 | // including, without limitation, that your use is for the sole purpose 27 | // of programming logic devices manufactured by Altera and sold by Altera 28 | // or its authorized distributors. Please refer to the applicable 29 | // agreement for further details. 30 | // 31 | // -------------------------------------------------------------------- 32 | module audio_io(oAUD_BCK, 33 | oAUD_DATA, 34 | oAUD_LRCK, 35 | iAUD_ADCDAT, 36 | oAUD_ADCLRCK, 37 | iCLK_18_4, 38 | iRST_N, 39 | pulses, 40 | linein); 41 | 42 | parameter REF_CLK = 18432000; // 18.432 MHz 43 | parameter SAMPLE_RATE = 48000; // 48 KHz 44 | parameter DATA_WIDTH = 16; // 16 Bits 45 | parameter CHANNEL_NUM = 2; // Dual Channel 46 | 47 | // Audio Side 48 | output oAUD_DATA; 49 | output oAUD_LRCK; 50 | output reg oAUD_BCK; 51 | input iAUD_ADCDAT; 52 | output oAUD_ADCLRCK; 53 | // Control Signals 54 | input iCLK_18_4; 55 | input iRST_N; 56 | input [15:0] pulses; 57 | output [15:0] linein; 58 | 59 | // Internal Registers and Wires 60 | reg [3:0] BCK_DIV; 61 | reg [8:0] LRCK_1X_DIV; 62 | reg [3:0] SEL_Cont; 63 | 64 | reg LRCK_1X; 65 | 66 | //////////// AUD_BCK Generator ////////////// 67 | always@(posedge iCLK_18_4 or negedge iRST_N) 68 | begin 69 | if(!iRST_N) begin 70 | BCK_DIV <= 0; 71 | oAUD_BCK <= 0; 72 | end 73 | else begin 74 | if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 ) 75 | begin 76 | BCK_DIV <= 0; 77 | oAUD_BCK <= ~oAUD_BCK; 78 | end 79 | else 80 | BCK_DIV <= BCK_DIV + 1'd1; 81 | end 82 | end 83 | ////////////////////////////////////////////////// 84 | //////////// AUD_LRCK Generator ////////////// 85 | always@(posedge iCLK_18_4 or negedge iRST_N) 86 | begin 87 | if(!iRST_N) begin 88 | LRCK_1X_DIV <= 0; 89 | LRCK_1X <= 0; 90 | end 91 | else begin 92 | // LRCK 1X 93 | if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 ) begin 94 | LRCK_1X_DIV <= 0; 95 | LRCK_1X <= ~LRCK_1X; 96 | end else 97 | LRCK_1X_DIV <= LRCK_1X_DIV+1'd1; 98 | end 99 | end 100 | 101 | assign oAUD_LRCK = LRCK_1X; 102 | assign oAUD_ADCLRCK= oAUD_LRCK; 103 | 104 | ////////////////////////////////////////////////// 105 | ////////// 16 Bits PISO MSB First ////////////// 106 | always@(negedge oAUD_BCK or negedge iRST_N) 107 | begin 108 | if(!iRST_N) 109 | SEL_Cont <= 0; 110 | else 111 | SEL_Cont <= SEL_Cont+1'd1; 112 | end 113 | 114 | 115 | reg [15:0] pulsebuf; 116 | always @(negedge LRCK_1X) begin 117 | pulsebuf <= pulses; 118 | end 119 | 120 | assign oAUD_DATA = pulsebuf[~SEL_Cont]; 121 | 122 | assign linein = inputsample; 123 | reg [15:0] inputsample; 124 | reg [15:0] inputbuf; 125 | always @(negedge oAUD_BCK) begin 126 | inputbuf[~SEL_Cont] <= iAUD_ADCDAT; 127 | end 128 | 129 | always @(negedge LRCK_1X) begin 130 | inputsample <= inputbuf; 131 | end 132 | 133 | endmodule 134 | 135 | // $Id$ 136 | 137 | -------------------------------------------------------------------------------- /src/de1sram/ay/ayglue.v: -------------------------------------------------------------------------------- 1 | module ayglue(clk, ce, reset_n, address, data, wren, rden, q, sound,odataoe); 2 | input clk; 3 | input ce; 4 | input reset_n; 5 | input address; // port 14 (00) = data; port 15 (01) = address 6 | input [7:0] data; 7 | input wren; 8 | input rden; 9 | output reg[7:0] q; 10 | output odataoe; 11 | 12 | output[7:0] sound; 13 | 14 | wire [7:0] odata; 15 | wire odataoe; 16 | 17 | always @(odata, odataoe) if (~odataoe) q <= odata; 18 | 19 | reg [2:0] ctl; // {I_BDIR,I_BC2,I_BC1} 20 | always begin 21 | case ({address,wren,rden}) 22 | 3'b110: ctl <= 3'b001; // write addr 23 | 3'b010: ctl <= 3'b110; // wr data 24 | 3'b001: ctl <= 3'b011; // rd data 25 | default: ctl <= 3'b000; 26 | endcase 27 | end 28 | 29 | 30 | YM2149 digeridoo( 31 | .I_DA(data), 32 | .O_DA(odata), 33 | .O_DA_OE_L(odataoe), 34 | 35 | .I_A9_L(1'b0), 36 | .I_A8(1'b1), 37 | .I_BDIR(ctl[2]), 38 | .I_BC2(ctl[1]), 39 | .I_BC1(ctl[0]), 40 | .I_SEL_L(1'b1), // something /16? 41 | 42 | .O_AUDIO(sound), 43 | 44 | .ENA(ce), 45 | .RESET_L(reset_n), 46 | .CLK(clk) 47 | ); 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /src/de1sram/clockster.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007-2009 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: clockster.v 15 | // 16 | // Vector-06C clock generator. 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | `default_nettype none 21 | 22 | module clockster(clk, clk50, clk24, clk18, clk14, ce12, ce6, ce6x, ce3, video_slice, pipe_ab, ce1m5, clkpalFSC); 23 | input [1:0] clk; 24 | input clk50; 25 | output clk24; 26 | output clk18; 27 | output clk14; 28 | output ce12 = qce12; 29 | output ce6 = qce6; 30 | output ce6x = qce6x; 31 | output ce3 = qce3; 32 | output video_slice = qvideo_slice; 33 | output pipe_ab = qpipe_ab; 34 | output ce1m5 = qce1m5; 35 | output clkpalFSC; 36 | 37 | reg[5:0] ctr; 38 | reg[4:0] initctr; 39 | 40 | reg qce12, qce6, qce6x, qce3, qce3v, qvideo_slice, qpipe_ab, qce1m5; 41 | 42 | wire lock; 43 | wire clk13_93; 44 | wire clk14_00; 45 | wire clk14_xx; 46 | 47 | wire clk300x; 48 | wire clk300; 49 | wire clk70k9; 50 | 51 | wire clk30; 52 | wire clk28; 53 | 54 | mclk24mhz vector_xtal(clk50, clk24, clk300, clk28, lock); 55 | 56 | // Derive clock for PAL subcarrier: 4x 4.43361875 57 | `define PHACC_WIDTH 32 58 | `define PHACC_DELTA 253896634 59 | `define PHACC_DELTA 507793268 60 | 61 | reg [`PHACC_WIDTH-1:0] pal_phase; 62 | wire [`PHACC_WIDTH-1:0] pal_phase_next; 63 | assign pal_phase_next = pal_phase + `PHACC_DELTA; 64 | reg palclkreg; 65 | 66 | always @(posedge clk300) begin 67 | pal_phase <= pal_phase_next; 68 | end 69 | 70 | ayclkdrv clkbufpalfsc(pal_phase[`PHACC_WIDTH-1], clkpalFSC); 71 | 72 | `ifdef ONE_50MHZ_PLL_FOR_ALL 73 | 74 | // Make codec 18MHz 75 | `define COPHACC_DELTA 15729 76 | reg [15:0] cophacc; 77 | wire [15:0] cophacc_next = cophacc + `COPHACC_DELTA; 78 | always @(posedge clk300) cophacc <= cophacc_next; 79 | 80 | ayclkdrv clkbuf18mhz(cophacc[15], clk18); 81 | 82 | 83 | // phase accu doesn't work for AY, why? 84 | // 85 | // Make AY 14MHz 86 | //`define AYPHACC_DELTA 12233 87 | //reg [15:0] ayphacc; 88 | //wire [15:0] ayphacc_next = ayphacc + `AYPHACC_DELTA; 89 | //always @(posedge clk300) ayphacc <= ayphacc_next; 90 | // 91 | //ayclkdrv clkbuf14mhz(ayphacc[15], clk14_xx); 92 | 93 | reg[5:0] div300by21; 94 | assign clk14 = clk14_xx; // 300/21 = 14.3MHz 95 | always @(posedge clk300) begin 96 | div300by21 <= div300by21 + 1'b1; 97 | if (div300by21+1'b1 == 21) div300by21 <= 0; 98 | end 99 | ayclkdrv clkbuf14mhz(div300by21[4], clk14_xx); 100 | `else 101 | 102 | mclk14mhz audiopll(.inclk0(clk), .c0(clk14), .c1(clk18)); 103 | 104 | `endif 105 | 106 | always @(posedge clk24) begin 107 | if (initctr != 3) begin 108 | initctr <= initctr + 1'b1; 109 | end // latch 110 | else begin 111 | qpipe_ab <= ctr[5]; // pipe a/b 2x slower 112 | qce12 <= ctr[0]; // pixel push @12mhz 113 | qce6 <= ctr[1] & ctr[0]; // pixel push @6mhz 114 | qce6x <= ctr[1] & ~ctr[0]; // pre-pixel push @6mhz 115 | qce3 <= ctr[2] & ctr[1] & !ctr[0]; 116 | qvideo_slice <= !ctr[2]; 117 | qce1m5 <= !ctr[3] & ctr[2] & ctr[1] & !ctr[0]; 118 | ctr <= ctr + 1'b1; 119 | end 120 | end 121 | endmodule 122 | 123 | // $Id$ 124 | -------------------------------------------------------------------------------- /src/de1sram/soundcodec.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: soundcodec.v 15 | // 16 | // Audio interface between raw audio pulses from 8253, tape i/o and 17 | // sound codec. Includes simple moving average filter for all but 18 | // tape signals. 19 | // 20 | // -------------------------------------------------------------------- 21 | 22 | `default_nettype none 23 | 24 | module soundcodec(clk18, pulses, pcm, tapein, reset_n, oAUD_XCK, oAUD_BCK, oAUD_DATA, oAUD_LRCK, iAUD_ADCDAT, oAUD_ADCLRCK); 25 | input clk18; 26 | input [3:0] pulses; 27 | input [7:0] pcm; 28 | output reg tapein; 29 | input reset_n; 30 | output oAUD_XCK = clk18; 31 | output oAUD_BCK; 32 | output oAUD_DATA; 33 | output oAUD_LRCK; 34 | input iAUD_ADCDAT; 35 | output oAUD_ADCLRCK; 36 | 37 | parameter HYST = 4; 38 | 39 | reg [7:0] decimator; 40 | always @(posedge clk18) decimator <= decimator + 1'd1; 41 | 42 | wire ma_ce = decimator == 0; 43 | 44 | 45 | wire [15:0] linein; // comes from codec 46 | reg [15:0] ma_pulse; // goes to codec 47 | 48 | reg [7:0] pulses_sample[0:3]; 49 | 50 | // sample * 16 51 | wire [5:0] m04 = {pulses[0], 4'b0}; 52 | wire [5:0] m14 = {pulses[1], 4'b0}; 53 | wire [5:0] m24 = {pulses[2], 4'b0}; 54 | wire [5:0] m34 = {pulses[3], 4'b0}; 55 | 56 | reg [7:0] sum; 57 | 58 | always @(posedge clk18) begin 59 | if (ma_ce) begin 60 | pulses_sample[3] <= pulses_sample[2]; 61 | pulses_sample[2] <= pulses_sample[1]; 62 | pulses_sample[1] <= pulses_sample[0]; 63 | pulses_sample[0] <= m04 + m14 + m24/* + m34*/; 64 | sum <= pulses_sample[0] + pulses_sample[1] + pulses_sample[2] + pulses_sample[3]; 65 | end 66 | 67 | ma_pulse <= {sum[7:2], 7'b0} + {m34,8'b0} + {pcm,5'b0}; 68 | 69 | end 70 | 71 | audio_io audioio(oAUD_BCK, oAUD_DATA, oAUD_LRCK, iAUD_ADCDAT, oAUD_ADCLRCK, clk18, reset_n, ma_pulse, linein); 72 | 73 | reg [15:0] level_avg; 74 | reg [7:0] lowest; 75 | reg [7:0] highest; 76 | reg [7:0] abs_low; 77 | reg [7:0] abs_high; 78 | 79 | wire [7:0] line8in = {~linein[15],linein[14:8]}; // shift signed value to be withing 0..255 range, 128 is midpoint 80 | 81 | always @(posedge clk18) begin 82 | if (line8in < 128+HYST) tapein <= 1'b0; 83 | if (line8in > 128-HYST) tapein <= 1'b1; 84 | end 85 | 86 | endmodule 87 | 88 | // $Id$ -------------------------------------------------------------------------------- /src/de1sram/sram_map.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: sram_map.v 15 | // 16 | // Maps linear 64K x 8 address space into 32K x 16 address space 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | `default_nettype none 21 | 22 | module sram_map(SRAM_ADDR, SRAM_DQ, SRAM_WE_N, SRAM_UB_N, SRAM_LB_N, 23 | set_dq_to_dout, memwr_n, abus, dout, din, ramdisk_page, 24 | jtag_addr, jtag_din, jtag_do, jtag_jtag, jtag_nwe); 25 | output [17:0] SRAM_ADDR; 26 | inout reg[15:0] SRAM_DQ; 27 | output SRAM_WE_N; 28 | output SRAM_UB_N; 29 | output SRAM_LB_N; 30 | input set_dq_to_dout; 31 | input memwr_n; 32 | input [15:0] abus; 33 | input [7:0] dout; 34 | output [7:0] din; 35 | input [2:0] ramdisk_page; 36 | 37 | input [17:0] jtag_addr; 38 | input [15:0] jtag_din; 39 | output [15:0] jtag_do = SRAM_DQ;//16'hc3e0;// 40 | input jtag_jtag; 41 | input jtag_nwe; 42 | 43 | assign SRAM_ADDR = jtag_jtag ? jtag_addr : {ramdisk_page, abus[15:1]}; 44 | assign SRAM_UB_N = jtag_jtag ? 1'b0 : ~abus[0]; 45 | assign SRAM_LB_N = jtag_jtag ? 1'b0 : abus[0]; 46 | assign SRAM_WE_N = jtag_jtag ? jtag_nwe : memwr_n; 47 | 48 | always 49 | if (jtag_jtag & ~jtag_nwe) 50 | SRAM_DQ[15:0] <= jtag_din; 51 | else if (set_dq_to_dout) 52 | SRAM_DQ[15:0] <= abus[0] ? {dout, 8'bZZZZZZZZ} : {8'bZZZZZZZZ, dout}; 53 | else 54 | SRAM_DQ[15:0] <= 16'bZZZZZZZZZZZZZZZZ; 55 | 56 | assign din = abus[0] ? SRAM_DQ[15:8] : SRAM_DQ[7:0]; 57 | 58 | endmodule 59 | 60 | // $Id$ -------------------------------------------------------------------------------- /src/de1sram/video/framebuffer.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: framebuffer.v 15 | // 16 | // Vector-06C frame buffer. This module accesses bit planes sequentially, 17 | // loads shift registers and shifts out bits by pixel. 18 | // Originally designed to work at VGA speed, later adopted for 2x slower 19 | // speed of original Vector-06C for compatibility reasons. 20 | // 21 | // This version reads memory 2x more times than necessary. 22 | // 23 | // -------------------------------------------------------------------- 24 | 25 | 26 | `default_nettype none 27 | 28 | //// 29 | // 30 | // Frame Buffer 31 | // 32 | //// 33 | module framebuffer(clk24, ce12, ce_pixel, video_slice, pipe_abx, fb_row, hsync, SRAM_DQ, SRAM_ADDR, coloridx, borderx, testpin); 34 | input clk24; 35 | input ce12; 36 | input ce_pixel; 37 | input video_slice; 38 | input pipe_abx; // pipe selector, should be fed from clockster 39 | 40 | input [8:0] fb_row; 41 | 42 | input hsync; 43 | 44 | input [7:0] SRAM_DQ; 45 | output [15:0] SRAM_ADDR; 46 | 47 | output [3:0] coloridx; 48 | output borderx; 49 | 50 | output [5:0] testpin; 51 | 52 | reg [3:0] wr; // pipeline write pulses, derived from ax count 53 | 54 | assign testpin[0] = wr[0]; 55 | assign testpin[1] = wr[1]; 56 | assign testpin[2] = wr[2]; 57 | assign testpin[3] = wr[3]; 58 | assign testpin[4] = pipe_abx; 59 | assign testpin[5] = video_slice; 60 | 61 | 62 | reg [4:0] column; // byte column number 63 | 64 | reg [1:0] ax; // position counter for generating write pulses 65 | // same as video page number 66 | 67 | reg [15:0] sram_addr; 68 | wire [15:0] SRAM_ADDR; 69 | assign SRAM_ADDR = sram_addr; 70 | 71 | reg [1:0] borderdelay; 72 | reg borderxreg; 73 | assign borderx = borderdelay[0]; 74 | always @(posedge clk24) begin 75 | if (ce_pixel) begin 76 | borderdelay <= {borderxreg, borderdelay[1]}; 77 | end 78 | end 79 | 80 | // enable update on ce12 preceding ce_pixel 81 | wire video_a = video_slice & ce12 & !ce_pixel; 82 | wire video_b = !video_slice & ce12 & !ce_pixel; 83 | 84 | // video_slice occurs 4 times every 8 pixels 85 | always @(posedge clk24) begin 86 | if (video_a) begin 87 | if (ax == 2'b11) begin 88 | if (!hsync & fb_row[0]) begin 89 | column <= 5'h1A; 90 | borderxreg <= 1; 91 | end 92 | else column <= column + 1'b1; 93 | if (column == 0) borderxreg <= ~borderxreg; 94 | end 95 | ax <= ax + 1'b1; 96 | wr[0] <= ax == 2'b00; 97 | wr[1] <= ax == 2'b01; 98 | wr[2] <= ax == 2'b10; 99 | wr[3] <= ax == 2'b11; 100 | end 101 | else begin 102 | wr <= 4'b0000; 103 | end 104 | 105 | if (video_b) 106 | sram_addr <= {1'b1,ax,column[4:0],fb_row[8:1]}; 107 | end 108 | 109 | pipelinx pipdx_0(clk24, ce_pixel, pipe_abx, wr[0], SRAM_DQ, coloridx[3]); 110 | pipelinx pipdx_1(clk24, ce_pixel, pipe_abx, wr[1], SRAM_DQ, coloridx[2]); 111 | pipelinx pipdx_2(clk24, ce_pixel, pipe_abx, wr[2], SRAM_DQ, coloridx[1]); 112 | pipelinx pipdx_3(clk24, ce_pixel, pipe_abx, wr[3], SRAM_DQ, coloridx[0]); 113 | 114 | 115 | endmodule 116 | 117 | 118 | //// 119 | // 120 | // 2 shift registers, selectable by ab 121 | // writeplz: async load 122 | // clk/ce pushes the data out right 123 | // 124 | //// 125 | module pipelinx(clk, ce, ab, writeplz, din, bout); 126 | input clk; 127 | input ce; 128 | input ab; 129 | input writeplz; 130 | input [7:0] din; 131 | output bout; 132 | 133 | wire bouta, boutb; 134 | wire n_ab = !ab; 135 | assign bout = ab ? boutb : bouta; // curent bits of all 4 registers 136 | 137 | shiftreg2 pipa(clk, ce & n_ab, din, writeplz & ab, bouta); 138 | shiftreg2 pipb(clk, ce & ab, din, writeplz & n_ab, boutb); 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /src/floppy/dma_rw.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // ==================================================================== 4 | // VECTOR-06C FPGA REPLICA 5 | // 6 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 7 | // 8 | // This core is distributed under modified BSD license. 9 | // For complete licensing information see LICENSE.TXT. 10 | // -------------------------------------------------------------------- 11 | // 12 | // An open implementation of Vector-06C home computer 13 | // 14 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 15 | // 16 | // Design File: dma_rw.v 17 | // 18 | // DMA controller that can pump 512-byte blocks between SPI and a RAM buffer. 19 | // Buffer address is loaded in iaddr when nblocks input is nonzero. 20 | // A nonzero nblocks value on input initiates transfer (ready == 0). 21 | // Bit 3 of nblocks indicates transfer direction (1 == RAM to SPI). 22 | // While ready == 0, nothing is allowed to access data and address busses. 23 | // -------------------------------------------------------------------- 24 | 25 | module dma_rw(clk, ce, reset_n, iaddr, oaddr, odata, idata, owren, nblocks, ready, ospi_data, ispi_data, ospi_wr, ispi_dsr, debug); 26 | 27 | parameter IDLE=4'd0, BUSY=4'd1, BLOCK=4'd2, OVER=4'd3, NBYTE=4'd4; 28 | parameter BLOCKSIZE=10'd512; 29 | 30 | input clk; // clock 31 | input ce; // clock enable 32 | input reset_n; // reset 33 | 34 | input [15:0] iaddr; // this addr latched as start of the buffer when beginning transfer 35 | output reg [15:0] oaddr; // output address bus 36 | output reg[7:0] odata; // output data (direct from SPI controller) 37 | input [7:0] idata; // data from RAM 38 | output reg owren; // RAM write strobe (positive) 39 | 40 | input [3:0] nblocks; // input: bits [2:0] is the amount of 512-byte blocks to transfer 41 | // a non-zero value initiates transfer 42 | // bit 3: 0: transfer from spi to host ("read") 43 | // 1: transfer from host to spi ("write") 44 | output ready = !busy; // when 0, the controller has exclusive access to busses 45 | 46 | output [7:0] ospi_data; // this data fed to SPI 47 | input [7:0] ispi_data; // SPI data input, routed directly to odata output 48 | output reg ospi_wr; // SPI transfer initiator 49 | input ispi_dsr; // SPI data ready 50 | output [7:0] debug = {rblocks,state}; 51 | 52 | 53 | reg [7:0] idata_r; 54 | reg [2:0] rblocks; 55 | reg dir_tospi; // 0: send data from spi to host ram ("read") 56 | // 1: send data from host ram to spi ("write") 57 | 58 | reg [15:0] addrbase; 59 | reg [9:0] bytectr; 60 | 61 | reg [3:0] state; 62 | 63 | reg busy; 64 | 65 | always odata <= ispi_data; 66 | 67 | // if direction is set FROM spi TO host, poke out FF's 68 | assign ospi_data = idata_r; 69 | 70 | always @(posedge clk) 71 | if (~reset_n) begin 72 | busy <= 0; 73 | rblocks <= 0; 74 | ospi_wr <= 0; 75 | owren <= 0; 76 | state <= IDLE; 77 | end else if (ce) 78 | begin 79 | case (state) 80 | IDLE: 81 | begin 82 | if (nblocks != 0) begin 83 | rblocks <= nblocks[2:0]; 84 | dir_tospi <= nblocks[3]; 85 | busy <= 1; 86 | addrbase <= iaddr;// - (~nblocks[3]); 87 | oaddr <= iaddr; 88 | bytectr <= BLOCKSIZE; 89 | state <= NBYTE; 90 | end 91 | end 92 | NBYTE: 93 | begin 94 | idata_r <= dir_tospi ? idata : 8'hFF; 95 | ospi_wr <= 1; 96 | owren <= 0; 97 | state <= BUSY; 98 | end 99 | BUSY: 100 | begin 101 | ospi_wr <= 0; 102 | if (ispi_dsr) begin 103 | owren <= ~dir_tospi;//1'b1; 104 | // when reading: (addr=0), read spi, write to ram, addr increment 105 | // when writing: (addr=0), read from ram, write spi, addr increment 106 | // hence + dir_tospi for correction 107 | oaddr <= addrbase + (BLOCKSIZE - bytectr) + dir_tospi; 108 | //oaddr <= oaddr + 1'b1; 109 | bytectr <= bytectr - 1'b1; 110 | 111 | if (0 == bytectr - 1'b1) 112 | state <= BLOCK; // roll over to next block or end of line 113 | else 114 | state <= NBYTE; // initiate next byte 115 | 116 | end 117 | end 118 | BLOCK: 119 | begin 120 | owren <= 0; 121 | bytectr <= BLOCKSIZE; 122 | if (rblocks - 1 != 0) begin 123 | rblocks <= rblocks - 1; 124 | state <= NBYTE; 125 | end 126 | else begin 127 | state <= OVER; 128 | end 129 | end 130 | OVER: 131 | begin 132 | busy <= 0; 133 | state <= IDLE; 134 | owren <= 0; 135 | ospi_wr <= 0; 136 | rblocks <= 0; 137 | end 138 | endcase 139 | end 140 | 141 | endmodule 142 | 143 | -------------------------------------------------------------------------------- /src/floppy/spi.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // ==================================================================== 4 | // VECTOR-06C FPGA REPLICA 5 | // 6 | // Copyright (C) 2007, Viacheslav Slavinsky 7 | // 8 | // This core is distributed under modified BSD license. 9 | // For complete licensing information see LICENSE.TXT. 10 | // -------------------------------------------------------------------- 11 | // 12 | // An open implementation of Vector-06C home computer 13 | // 14 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 15 | // 16 | // Design File: spi.v 17 | // 18 | // SPI host, mimics AVR SPI in its most basic mode 19 | // 20 | // -------------------------------------------------------------------- 21 | 22 | module spi(clk, ce, reset_n, mosi, miso, sck, di, wr, do, dsr); 23 | input clk; 24 | input ce; 25 | input reset_n; 26 | output reg mosi; 27 | input miso; 28 | output sck = ~clk & scken; 29 | 30 | input [7:0] di; 31 | input wr; 32 | 33 | output[7:0] do = shiftreg; 34 | output reg dsr; 35 | 36 | reg [7:0] shiftreg; 37 | reg [7:0] shiftski; 38 | 39 | reg [1:0] state = 0; 40 | reg scken = 0; 41 | 42 | always @(posedge clk or negedge reset_n) begin 43 | if (!reset_n) begin 44 | state <= 0; 45 | mosi <= 1'b0; 46 | dsr <= 0; 47 | scken <= 0; 48 | end else begin 49 | if (ce) begin 50 | case (state) 51 | 0: begin 52 | if (wr) begin 53 | dsr <= 1'b0; 54 | state <= 1; 55 | shiftreg <= di; 56 | shiftski <= 8'b11111111; 57 | end 58 | end 59 | 1: begin 60 | scken <= 1; 61 | mosi <= shiftreg[7]; 62 | shiftreg <= {shiftreg[6:0],miso}; 63 | shiftski <= {1'b0,shiftski[7:1]}; 64 | 65 | if (|shiftski == 0) begin 66 | state <= 2; 67 | scken <= 0; 68 | end 69 | end 70 | 2: begin 71 | mosi <= 1'b0; // shouldn't be necessary but a nice debug view 72 | dsr <= 1'b1; 73 | state <= 0; 74 | //scken <= 0; 75 | end 76 | default: ; 77 | endcase 78 | end 79 | end 80 | end 81 | 82 | 83 | endmodule 84 | 85 | -------------------------------------------------------------------------------- /src/floppy/timer100hz.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | // ==================================================================== 3 | // VECTOR-06C FPGA REPLICA 4 | // 5 | // Copyright (C) 2007, Viacheslav Slavinsky 6 | // 7 | // This core is distributed under modified BSD license. 8 | // For complete licensing information see LICENSE.TXT. 9 | // -------------------------------------------------------------------- 10 | // 11 | // An open implementation of Vector-06C home computer 12 | // 13 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 14 | // 15 | // Design File: timer100hz.v 16 | // 17 | // A simple tick-tock timer with async load. 18 | // Used as a peripheral for the floppy CPU. 19 | // 20 | // -------------------------------------------------------------------- 21 | 22 | module timer100hz(clk, di, wren, q); 23 | parameter MCLKFREQ = 24000000; 24 | 25 | input clk; 26 | input [7:0] di; 27 | input wren; 28 | output reg[7:0] q; 29 | 30 | reg [17:0] timerctr; 31 | 32 | wire hz100 = timerctr == 0; 33 | 34 | always @(posedge clk) begin 35 | if (timerctr == 0) 36 | timerctr <= MCLKFREQ/100; 37 | else 38 | timerctr <= timerctr - 1'b1; 39 | end 40 | 41 | always @(posedge clk) begin 42 | if (wren) begin 43 | q <= di; 44 | end 45 | else if (q != 0 && hz100) q <= q - 1'b1; 46 | end 47 | 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /src/floppy/uart/txd.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------ 2 | ------------------------------------------------------------------------------ 3 | -- -- 4 | -- Copyright (c) 2007 Tobias Gubener -- 5 | -- -- 6 | -- This source file is free software: you can redistribute it and/or modify -- 7 | -- it under the terms of the GNU General Public License as published -- 8 | -- by the Free Software Foundation, either version 3 of the License, or -- 9 | -- (at your option) any later version. -- 10 | -- -- 11 | -- This source file is distributed in the hope that it will be useful, -- 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- 14 | -- GNU General Public License for more details. -- 15 | -- -- 16 | -- You should have received a copy of the GNU General Public License -- 17 | -- along with this program. If not, see . -- 18 | -- -- 19 | ------------------------------------------------------------------------------ 20 | ------------------------------------------------------------------------------ 21 | 22 | library IEEE; 23 | use IEEE.std_logic_1164.all; 24 | use IEEE.STD_LOGIC_UNSIGNED.all; 25 | 26 | 27 | entity TXD is 28 | port ( 29 | clk: in std_logic; 30 | ld: in std_logic; 31 | data: in std_logic_vector(7 downto 0); 32 | TxD: out std_logic; 33 | txbusy: buffer std_logic 34 | ); 35 | 36 | end TXD; 37 | 38 | 39 | architecture TXD of TXD is 40 | 41 | signal shift: std_logic_vector(9 downto 0); 42 | signal clkgen: std_logic_vector(9 downto 0); 43 | signal stop: std_logic; 44 | signal shiftout: std_logic; 45 | 46 | begin 47 | TxD <= not shiftout; 48 | process(clk, shift) 49 | begin 50 | if shift = "0000000000" then 51 | txbusy <= '0'; 52 | else 53 | txbusy <= '1'; 54 | end if; 55 | 56 | if clk'event and clk = '1' then 57 | if ld = '1' then 58 | shiftout <= '0'; 59 | shift <= '1' & data & '0'; --STOP,MSB...LSB, START 60 | end if; 61 | if clkgen/=0 then 62 | if ld = '1' and stop = '0' then 63 | clkgen <= "0000000001"; 64 | else 65 | clkgen <= clkgen-1; 66 | end if; 67 | else 68 | -- clkgen <= "1101000000";--832; --96MHz/115200 69 | -- clkgen <= "0111100101";--487; --56MHz/115200 70 | -- clkgen <= "0011110010";--243; --28MHz/115200 71 | clkgen <= "0011010000"; --24MHz/115200 72 | -- clkgen <= "1001110001"; --24MHz/38400 73 | shiftout <= not(shift(0) or not txbusy or ld); 74 | stop <= shift(0); 75 | shift <= '0' & shift(9 downto 1); 76 | end if; 77 | end if; 78 | end process; 79 | 80 | end TXD; 81 | -------------------------------------------------------------------------------- /src/jtag/jtag_top.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: jtag_top.v 15 | // 16 | // A toplevel module of JTAG framework. 17 | // Converts JTAG signals into signals useful in sram_map.v 18 | // Instantiates Altera DE1-specific modules from DE1 directory. 19 | // This module can be re-written to adopt any hardware. 20 | // -------------------------------------------------------------------- 21 | 22 | 23 | `default_nettype none 24 | 25 | module jtag_top(clk24, reset_n, oHOLD, iHLDA, iTCK, oTDO, iTDI, iTCS, oJTAG_ADDR, iJTAG_DATA_TO_HOST, oJTAG_DATA_FROM_HOST, oJTAG_SRAM_WR_N, oJTAG_SELECT); 26 | input clk24; 27 | input reset_n; 28 | 29 | output oHOLD; 30 | input iHLDA; 31 | 32 | input iTCK; 33 | output oTDO; 34 | input iTDI; 35 | input iTCS; 36 | 37 | output [17:0] oJTAG_ADDR; 38 | input [15:0] iJTAG_DATA_TO_HOST; 39 | output [15:0] oJTAG_DATA_FROM_HOST; 40 | output oJTAG_SRAM_WR_N; 41 | output oJTAG_SELECT; 42 | 43 | `ifdef WITH_DE1_JTAG 44 | 45 | CLK_LOCK p0 ( .inclk(iTCK),.outclk(mTCK) ); 46 | 47 | // USB JTAG 48 | wire [7:0] mRXD_DATA,mTXD_DATA; 49 | wire mRXD_Ready,mTXD_Done,mTXD_Start; 50 | wire mTCK; 51 | 52 | USB_JTAG u1 ( // HOST 53 | .iTxD_DATA(mTXD_DATA), 54 | .oTxD_Done(mTXD_Done), 55 | .iTxD_Start(mTXD_Start), 56 | .oRxD_DATA(mRXD_DATA), 57 | .oRxD_Ready(mRXD_Ready), 58 | .iRST_n(reset_n), 59 | .iCLK(clk24), 60 | // raw JTAG 61 | .TDO(oTDO),.TDI(iTDI),.TCS(iTCS),.TCK(mTCK) ); 62 | 63 | CMD_Decode u5 ( // USB JTAG 64 | .iRXD_DATA(mRXD_DATA), 65 | .iRXD_Ready(mRXD_Ready), 66 | .oTXD_DATA(mTXD_DATA), 67 | .oTXD_Start(mTXD_Start), 68 | .iTXD_Done(mTXD_Done), 69 | // SRAM 70 | .iSR_DATA(iJTAG_DATA_TO_HOST), 71 | .oSR_DATA(oJTAG_DATA_FROM_HOST), 72 | .oSR_ADDR(oJTAG_ADDR), 73 | .oSR_WE_N(oJTAG_SRAM_WR_N), 74 | .oJTAG_SEL(oJTAG_SELECT), 75 | // Control 76 | .iCLK(clk24), 77 | .iRST_n(reset_n), 78 | .oHOLD(oHOLD), 79 | .iHLDA(iHLDA)); 80 | `else 81 | assign oJTAG_ADDR = 18'b0; 82 | assign oJTAG_DATA_FROM_HOST=16'b0; 83 | assign oJTAG_SELECT = 1'b0; 84 | assign oJTAG_SRAM_WR_N = 1'b1; 85 | `endif 86 | 87 | endmodule 88 | 89 | // $Id$ -------------------------------------------------------------------------------- /src/keyboard/ps2k.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: ps2k.v 15 | // 16 | // Low-level PS/2 keyboard interface core. 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | `default_nettype none 21 | 22 | module ps2k( 23 | clk, 24 | reset, 25 | ps2_clk, 26 | ps2_data, 27 | rden, 28 | q, 29 | dsr, 30 | overflow); 31 | input clk; 32 | input reset; 33 | 34 | input ps2_clk; 35 | input ps2_data; 36 | 37 | input rden; 38 | output [7:0] q; 39 | output reg dsr; 40 | output overflow = watchdog; 41 | 42 | wire watchdog; 43 | reg watchdogtrig; 44 | ps2watchdog ps2wd(clk, watchdogtrig, watchdog); 45 | 46 | reg [7:0] qreg; 47 | 48 | reg [1:0] state = 2'b00; 49 | 50 | reg [4:0] sampledelay; 51 | reg [1:0] samplebuf; 52 | reg sample_ce; 53 | always @(posedge clk) begin 54 | samplebuf <= {samplebuf[0], ps2_clk}; 55 | sample_ce <= samplebuf[1] & ~samplebuf[0]; 56 | end 57 | 58 | /* 59 | assign dsr = wrptr != rdptr; 60 | */ 61 | 62 | reg [9:0] shiftreg; 63 | reg [7:0] q; 64 | reg [3:0] bitcount = 4'b0; 65 | 66 | always @(posedge clk) begin 67 | if (reset) begin 68 | bitcount <= 4'b0; 69 | q <= 8'b0; 70 | state <= 2'b00; 71 | dsr <= 1'b0; 72 | watchdogtrig <= 0; 73 | end else begin 74 | case (state) 75 | 2'b00: // must be a start bit == 0 76 | begin 77 | watchdogtrig <= 0; 78 | if (sample_ce) begin 79 | if (~ps2_data) begin 80 | bitcount <= 9; 81 | state <= 2'b01; 82 | watchdogtrig <= 1; 83 | end 84 | else state <= 2'b11; 85 | end 86 | end 87 | 2'b01: 88 | begin 89 | if (sample_ce) begin 90 | shiftreg <= {ps2_data, shiftreg[9:1]}; 91 | bitcount <= bitcount - 1'b1; 92 | if (bitcount == 0) state <= 2'b10; 93 | end 94 | else begin 95 | if (watchdog) state <= 2'b11; // stuck 96 | end 97 | end 98 | 2'b10: 99 | begin 100 | if (shiftreg[9] && (^shiftreg[8:0])==1'b1) begin 101 | qreg <= shiftreg[7:0]; 102 | dsr <= 1'b1; 103 | state <= 2'b00; 104 | end 105 | end 106 | 2'b11: 107 | begin 108 | state <= 2'b00; 109 | end 110 | endcase 111 | 112 | if (dsr & rden) begin 113 | q <= qreg; 114 | dsr <= 1'b0; 115 | end 116 | 117 | end 118 | end 119 | 120 | endmodule 121 | 122 | 123 | module ps2watchdog(clk24, trig, watchdog); 124 | input clk24; 125 | input trig; 126 | output reg watchdog; 127 | 128 | reg [15:0] divctr; 129 | always @(posedge clk24) begin 130 | if (divctr == 0 && trig) begin 131 | divctr <= 16'h7FFF; 132 | end 133 | if (divctr != 0) begin 134 | divctr <= divctr - 1'b1; 135 | end 136 | watchdog <= &(~divctr[15:1]) & divctr[0]; 137 | end 138 | 139 | endmodule 140 | 141 | 142 | // $Id$ 143 | -------------------------------------------------------------------------------- /src/oneshot.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: oneshot.v 15 | // 16 | // A parametric one-shot with sampling trigger and clock enable. 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | module oneshot(clk, ce, trigger, q); 21 | parameter CLOCKS = 8'd16; 22 | input clk; 23 | input ce; 24 | input trigger; 25 | output reg q; 26 | 27 | reg [8:0] n_shot; 28 | reg trigsample; 29 | 30 | always @(posedge clk) begin 31 | if (ce) begin 32 | trigsample <= trigger; 33 | if (~trigsample & trigger) begin 34 | q <= 1'b1; 35 | n_shot <= CLOCKS; 36 | end else begin 37 | if (q) n_shot <= n_shot - 1'b1; 38 | if (n_shot == 0) q <= 1'b0; 39 | end 40 | end 41 | end 42 | endmodule 43 | 44 | module oneshot_non_retriggerable(clk, ce, trigger, reset, q); 45 | parameter CLOCKS = 8'd16; 46 | input clk; 47 | input ce; 48 | input trigger; 49 | input reset; 50 | output reg q; 51 | 52 | reg [8:0] n_shot; 53 | reg trigsample; 54 | reg disabled; 55 | 56 | always @(posedge clk) begin 57 | if (ce) begin 58 | trigsample <= trigger; 59 | if (reset) disabled <= 0; 60 | if (~trigsample & trigger & ~disabled) begin 61 | q <= 1'b1; 62 | disabled <= 1'b1; 63 | n_shot <= CLOCKS; 64 | end else begin 65 | if (q) n_shot <= n_shot - 1'b1; 66 | if (n_shot == 0) q <= 1'b0; 67 | end 68 | end 69 | end 70 | endmodule 71 | 72 | // $Id$ 73 | -------------------------------------------------------------------------------- /src/ramdisk/kvaz.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Barkar kvaz support added by Ivan Gorodetsky 15 | // 16 | // Design File: kvaz.v 17 | // 18 | // RAM disk memory mapper. This unit maps standard Vector-06C RAM disk 19 | // into pages 1, 2, 3, 4 of SRAM address space. 20 | // 21 | // -------------------------------------------------------------------- 22 | `default_nettype none 23 | 24 | module kvaz(clk, clke, 25 | reset, 26 | address, 27 | select, 28 | data_in, 29 | stack, 30 | memwr, memrd, 31 | bigram_addr, 32 | debug); 33 | 34 | input clk; 35 | input clke; 36 | input reset; 37 | input [15:0] address; 38 | input select; 39 | input [7:0] data_in; 40 | input stack; 41 | input memwr; 42 | input memrd; 43 | output reg[2:0] bigram_addr; 44 | 45 | output [7:0] debug = {control_reg}; 46 | 47 | // control register 48 | reg [7:0] control_reg; 49 | 50 | always @(posedge clk) begin 51 | if (reset) begin 52 | control_reg <= 0; 53 | end 54 | else if (clke & select) begin 55 | control_reg <= data_in; 56 | end 57 | end 58 | 59 | // control register breakdown 60 | wire [2:0] cr_ram_page = control_reg[1:0] + 1'b1; 61 | wire [2:0] cr_stack_page = control_reg[3:2] + 1'b1; 62 | wire cr_stack_on = control_reg[4]; 63 | wire cr_ram_on = control_reg[5]; 64 | 65 | 66 | wire [3:0] adsel = address[15:12]; 67 | 68 | //wire addr_sel = adsel == 4'hA | adsel == 4'hB | adsel == 4'hC | adsel == 4'hD; //standard 69 | wire addr_sel = adsel == 4'hA | adsel == 4'hB | adsel == 4'hC | adsel == 4'hD | ((adsel==4'h8)|(adsel==4'h9)&&(control_reg[6]==1))|((adsel==4'hE)|(adsel==4'hF)&&(control_reg[7]==1));//Barkar 70 | 71 | wire ram_sel = cr_ram_on & addr_sel & (memwr|memrd); 72 | 73 | wire stack_sel = cr_stack_on & stack & (memwr|memrd); 74 | 75 | always @(stack,memrd,memwr,stack_sel,cr_stack_page,ram_sel,cr_ram_page) begin 76 | bigram_addr <= stack_sel ? cr_stack_page : ram_sel ? cr_ram_page : 3'b000; 77 | end 78 | 79 | endmodule 80 | 81 | // $Id$ -------------------------------------------------------------------------------- /src/singleclockster.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: singleclockster.v 15 | // 16 | // Generate single CPU clocks for key-tapped code execution. 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | `default_nettype none 21 | 22 | module singleclockster(clk24, singleclock_enabled, n_key, singleclock); 23 | input clk24; 24 | input singleclock_enabled; 25 | input n_key; 26 | output reg singleclock; 27 | 28 | reg key1_nreleased; 29 | always @(posedge clk24) begin 30 | if (singleclock_enabled) begin 31 | if (n_key == 1'b0) begin 32 | if (!key1_nreleased) begin 33 | singleclock <= 1; 34 | key1_nreleased <= 1; 35 | end 36 | end 37 | else key1_nreleased <= 0; 38 | 39 | if (singleclock) singleclock <= 0; 40 | end 41 | end 42 | 43 | endmodule 44 | 45 | // $Id$ 46 | -------------------------------------------------------------------------------- /src/specialkeys.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // ==================================================================== 4 | // VECTOR-06C FPGA REPLICA 5 | // 6 | // Copyright (C) 2007, Viacheslav Slavinsky 7 | // 8 | // This core is distributed under modified BSD license. 9 | // For complete licensing information see LICENSE.TXT. 10 | // -------------------------------------------------------------------- 11 | // 12 | // An open implementation of Vector-06C home computer 13 | // 14 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 15 | // 16 | // Design File: specialkeys.v 17 | // 18 | // Handler of 19 | // BLK+SBR (F12, reset with boot rom jettisoned) 20 | // HOLD ScrollLock, bus hold trigger 21 | // -------------------------------------------------------------------- 22 | 23 | 24 | module specialkeys(clk, cpu_ce, reset_n, key_blksbr, key_osd, osd_command, o_disable_rom, o_blksbr_reset, o_osd); 25 | input clk; 26 | input cpu_ce; 27 | input reset_n; 28 | input key_blksbr; 29 | input key_osd; 30 | input [7:0] osd_command; // {F11,F12,HOLD} 31 | output reg o_disable_rom; 32 | output o_blksbr_reset; 33 | output reg o_osd; 34 | 35 | // BLK+SBR 36 | reg rst0toggle = 0; 37 | always @(posedge clk or negedge reset_n) begin 38 | if (!reset_n) begin 39 | o_disable_rom <= 0; 40 | rst0toggle <= 0; 41 | end 42 | else begin 43 | if (key_blksbr) begin 44 | o_disable_rom <= 1; 45 | rst0toggle <= 1; 46 | end 47 | else rst0toggle <= 0; 48 | end 49 | end 50 | 51 | oneshot blksbr(clk, cpu_ce, rst0toggle, o_blksbr_reset); 52 | 53 | 54 | // ScrollLock 55 | reg key_osd_x = 0; 56 | always @(posedge clk or negedge reset_n) begin 57 | if (!reset_n) begin 58 | o_osd <= 0; 59 | key_osd_x <= 0; 60 | end 61 | else begin 62 | key_osd_x <= key_osd; 63 | if (key_osd & ~key_osd_x) 64 | o_osd <= ~o_osd; 65 | end 66 | end 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /src/video/framebuffer.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: framebuffer.v 15 | // 16 | // Vector-06C frame buffer. This module accesses bit planes sequentially, 17 | // loads shift registers and shifts out bits by pixel. 18 | // Originally designed to work at VGA speed, later adopted for 2x slower 19 | // speed of original Vector-06C for compatibility reasons. 20 | // 21 | // This version reads memory 2x more times than necessary. 22 | // 23 | // -------------------------------------------------------------------- 24 | 25 | 26 | `default_nettype none 27 | 28 | //// 29 | // 30 | // Frame Buffer 31 | // 32 | //// 33 | module framebuffer(clk24,ce12,ce_pixel,video_slice,pipe_abx,fb_row,hsync,vdata,vdata2,vdata3,vdata4,SRAM_ADDR,coloridx,borderx,testpin,rdvid); 34 | input clk24; 35 | input ce12; 36 | input ce_pixel; 37 | input video_slice; 38 | input pipe_abx; // pipe selector, should be fed from clockster 39 | 40 | input [8:0] fb_row; 41 | 42 | input hsync; 43 | 44 | input [31:0] vdata; 45 | input [31:0] vdata2; 46 | input [31:0] vdata3; 47 | input [31:0] vdata4; 48 | output [15:0] SRAM_ADDR; 49 | 50 | output [3:0] coloridx; 51 | output borderx; 52 | 53 | output [5:0] testpin; 54 | 55 | output rdvid=wr[0]; 56 | 57 | 58 | reg [3:0] wr; // pipeline write pulses, derived from ax count 59 | 60 | assign testpin[0] = wr[0]; 61 | assign testpin[1] = wr[1]; 62 | assign testpin[2] = wr[2]; 63 | assign testpin[3] = wr[3]; 64 | assign testpin[4] = pipe_abx; 65 | assign testpin[5] = video_slice; 66 | 67 | 68 | reg [4:0] column; // byte column number 69 | 70 | reg [1:0] ax; // position counter for generating write pulses 71 | // same as video page number 72 | 73 | 74 | reg [15:0] sram_addr; 75 | wire [15:0] SRAM_ADDR; 76 | assign SRAM_ADDR = sram_addr; 77 | 78 | reg [1:0] borderdelay; 79 | reg borderxreg; 80 | assign borderx = borderdelay[0]; 81 | always @(posedge clk24) begin 82 | if (ce_pixel) begin 83 | borderdelay <= {borderxreg, borderdelay[1]}; 84 | end 85 | end 86 | 87 | // enable update on ce12 preceding ce_pixel 88 | wire video_en = video_slice & ce12 & !ce_pixel; 89 | 90 | // video_slice occurs 4 times every 8 pixels 91 | // but in SDRAM version it doesn't matter 92 | always @(posedge clk24) begin 93 | if (video_en) begin 94 | if (ax == 2'b11) begin 95 | if (!hsync & fb_row[0]) begin 96 | column <= 5'h1A; 97 | borderxreg <= 1; 98 | end 99 | else column <= column + 1'b1; 100 | if (column == 0) borderxreg <= ~borderxreg; 101 | end 102 | sram_addr <= {1'b1,2'b0,column[4:0],fb_row[8:1]}; 103 | ax <= ax + 1'b1; 104 | wr[0] <= ax == 2'b00; 105 | wr[1] <= ax == 2'b01; 106 | wr[2] <= ax == 2'b10; 107 | wr[3] <= ax == 2'b11; 108 | end 109 | else begin 110 | wr <= 4'b0000; 111 | end 112 | end 113 | 114 | pipelinx pipdx_0(clk24, ce_pixel, pipe_abx, wr[3], vdata[7:0], coloridx[3]); 115 | pipelinx pipdx_1(clk24, ce_pixel, pipe_abx, wr[3], vdata[15:8], coloridx[2]); 116 | pipelinx pipdx_2(clk24, ce_pixel, pipe_abx, wr[3], vdata[23:16], coloridx[1]); 117 | pipelinx pipdx_3(clk24, ce_pixel, pipe_abx, wr[3], vdata[31:24], coloridx[0]); 118 | 119 | 120 | endmodule 121 | 122 | 123 | //// 124 | // 125 | // 2 shift registers, selectable by ab 126 | // writeplz: async load 127 | // clk/ce pushes the data out right 128 | // 129 | //// 130 | module pipelinx(clk, ce, ab, writeplz, din, bout); 131 | input clk; 132 | input ce; 133 | input ab; 134 | input writeplz; 135 | input [7:0] din; 136 | output bout; 137 | 138 | wire bouta, boutb; 139 | wire n_ab = !ab; 140 | assign bout = ab ? boutb : bouta; // curent bits of all 4 registers 141 | 142 | shiftreg2 pipa(clk, ce & n_ab, din, writeplz & ab, bouta); 143 | shiftreg2 pipb(clk, ce & ab, din, writeplz & n_ab, boutb); 144 | 145 | endmodule 146 | -------------------------------------------------------------------------------- /src/video/multadd.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTMULT_ADD" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "multadd.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "multadd_bb.v"] 5 | -------------------------------------------------------------------------------- /src/video/rambuffer.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: rambuffer.v 15 | // 16 | // One-line RAM buffer for scan doubler. 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | `default_nettype none 21 | 22 | module rambuffer(clk, cerd, cewr, wren, resetrd, resetwr, din, dout); 23 | input clk; 24 | input cerd; 25 | input cewr; 26 | input wren; 27 | input resetrd; 28 | input resetwr; 29 | input [7:0] din; 30 | output reg[7:0] dout; 31 | 32 | reg [7:0] pixelram[1023:0]; 33 | 34 | wire [9:0] rdaddr; 35 | wire [9:0] wraddr; 36 | 37 | rdwrctr c1(clk, cerd, resetrd, rdaddr); 38 | rdwrctr c2(clk, cewr, resetwr, wraddr); 39 | 40 | always @(posedge clk) begin 41 | if (wren) begin 42 | pixelram[wraddr] <= din; 43 | end 44 | dout <= pixelram[rdaddr]; 45 | end 46 | 47 | endmodule 48 | 49 | module rdwrctr(clk, ce, reset, q); 50 | input clk; 51 | input ce; 52 | input reset; 53 | output [9:0] q; 54 | 55 | /* 56 | always @(posedge clk) begin 57 | if (ce) begin 58 | if (reset) 59 | q <= 0; 60 | else 61 | q <= q + 1'b1; 62 | end 63 | end 64 | */ 65 | lpm_counter ctr(.clock(clk), .clk_en(ce), .aclr(reset), .q(q)); 66 | defparam ctr.LPM_WIDTH = 10, 67 | ctr.LPM_DIRECTION = "UP"; 68 | 69 | endmodule 70 | 71 | // $Id$ -------------------------------------------------------------------------------- /src/video/shiftreg2.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007, Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Design File: shiftreg2.v 15 | // 16 | // A parallel-load 1-bit shift-out register with (semi) asynchronous load. 17 | // 18 | // -------------------------------------------------------------------- 19 | 20 | module shiftreg2(clk, ce, din, wr, shiftout); 21 | input clk; 22 | input ce; 23 | input [7:0] din; 24 | input wr; 25 | output reg shiftout; 26 | 27 | reg [7:0] data; 28 | 29 | always @(posedge clk) begin 30 | if (wr) begin 31 | data <= {din[6:0],1'b0}; 32 | shiftout <= din[7]; 33 | end 34 | else begin 35 | if (ce) begin 36 | shiftout <= data[7]; 37 | data <= data << 1; 38 | end 39 | end 40 | end 41 | 42 | endmodule 43 | 44 | // $Id$ 45 | -------------------------------------------------------------------------------- /src/wxeda/clockster.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007-2016 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Modified by Ivan Gorodetsky 15 | // 16 | // Design File: clockster.v 17 | // 18 | // Vector-06C clock generator. 19 | // 20 | // -------------------------------------------------------------------- 21 | 22 | `default_nettype none 23 | 24 | module clockster(clk, clk50, clk24, clkAudio, ce12, ce6, ce6x, ce3, video_slice, pipe_ab, ce1m5, clkpalFSC, clk60, clk300, clk_color_mod); 25 | input [1:0] clk; 26 | input clk50; 27 | output clk24; 28 | output clkAudio = qce12; 29 | output ce12 = qce12; 30 | output ce6 = qce6; 31 | output ce6x = qce6x; 32 | output ce3 = qce3; 33 | output video_slice = qvideo_slice; 34 | output pipe_ab = qpipe_ab; 35 | output ce1m5 = qce1m5; 36 | output clkpalFSC; 37 | output clk60; 38 | output clk300; 39 | output clk_color_mod; 40 | 41 | reg[5:0] ctr; 42 | reg[4:0] initctr; 43 | 44 | reg qce12, qce6, qce6x, qce3, qce3v, qvideo_slice, qpipe_ab, qce1m5; 45 | 46 | wire clk300; 47 | wire clk600; 48 | 49 | 50 | wxeda_clocks(.inclk0(clk), .c0(clk24), .c1(clk60), .c2(clk300), .c3(clk600)); 51 | colorclock(.inclk0(clk), .c0(clk_color_mod)); 52 | 53 | // Derive clock for PAL subcarrier: 4x 4.43361875 54 | `define PHACC_WIDTH 32 55 | //`define PHACC_DELTA 253896634 56 | //`define PHACC_DELTA 507793268 57 | `define PHACC_DELTA 1015586535 58 | 59 | reg [`PHACC_WIDTH-1:0] pal_phase; 60 | wire [`PHACC_WIDTH-1:0] pal_phase_next; 61 | assign pal_phase_next = pal_phase + `PHACC_DELTA; 62 | reg palclkreg; 63 | 64 | always @(posedge clk300) begin 65 | pal_phase <= pal_phase_next; 66 | end 67 | 68 | ayclkdrv clkbufpalfsc(pal_phase[`PHACC_WIDTH-1], clkpalFSC); 69 | 70 | always @(posedge clk24) begin 71 | if (initctr != 3) begin 72 | initctr <= initctr + 1'b1; 73 | end // latch 74 | else begin 75 | qpipe_ab <= ctr[5]; // pipe a/b 2x slower 76 | qce12 <= ctr[0]; // pixel push @12mhz 77 | qce6 <= ctr[1] & ctr[0]; // pixel push @6mhz 78 | qce6x <= ctr[1] & ~ctr[0]; // pre-pixel push @6mhz 79 | 80 | qce3 <= ctr[2] & ctr[1] & !ctr[0]; //00100000 - svofski 81 | 82 | qvideo_slice <= !ctr[2]; 83 | qce1m5 <= !ctr[3] & ctr[2] & ctr[1] & !ctr[0]; 84 | ctr <= ctr + 1'b1; 85 | end 86 | end 87 | endmodule 88 | -------------------------------------------------------------------------------- /src/wxeda/colorclock.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /src/wxeda/colorclock.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "colorclock.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "colorclock_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "colorclock.ppf"] 6 | -------------------------------------------------------------------------------- /src/wxeda/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | BANDWIDTH_TYPE=AUTO 2 | CLK0_DIVIDE_BY=2 3 | CLK0_DUTY_CYCLE=50 4 | CLK0_MULTIPLY_BY=1 5 | CLK0_PHASE_SHIFT=0 6 | CLK1_DIVIDE_BY=4 7 | CLK1_DUTY_CYCLE=50 8 | CLK1_MULTIPLY_BY=5 9 | CLK1_PHASE_SHIFT=0 10 | CLK2_DIVIDE_BY=4 11 | CLK2_DUTY_CYCLE=50 12 | CLK2_MULTIPLY_BY=25 13 | CLK2_PHASE_SHIFT=0 14 | CLK3_DIVIDE_BY=2 15 | CLK3_DUTY_CYCLE=50 16 | CLK3_MULTIPLY_BY=25 17 | CLK3_PHASE_SHIFT=0 18 | COMPENSATE_CLOCK=CLK0 19 | INCLK0_INPUT_FREQUENCY=20833 20 | INTENDED_DEVICE_FAMILY="Cyclone IV E" 21 | LPM_TYPE=altpll 22 | OPERATION_MODE=NORMAL 23 | PLL_TYPE=AUTO 24 | PORT_ACTIVECLOCK=PORT_UNUSED 25 | PORT_ARESET=PORT_UNUSED 26 | PORT_CLKBAD0=PORT_UNUSED 27 | PORT_CLKBAD1=PORT_UNUSED 28 | PORT_CLKLOSS=PORT_UNUSED 29 | PORT_CLKSWITCH=PORT_UNUSED 30 | PORT_CONFIGUPDATE=PORT_UNUSED 31 | PORT_FBIN=PORT_UNUSED 32 | PORT_INCLK0=PORT_USED 33 | PORT_INCLK1=PORT_UNUSED 34 | PORT_LOCKED=PORT_UNUSED 35 | PORT_PFDENA=PORT_UNUSED 36 | PORT_PHASECOUNTERSELECT=PORT_UNUSED 37 | PORT_PHASEDONE=PORT_UNUSED 38 | PORT_PHASESTEP=PORT_UNUSED 39 | PORT_PHASEUPDOWN=PORT_UNUSED 40 | PORT_PLLENA=PORT_UNUSED 41 | PORT_SCANACLR=PORT_UNUSED 42 | PORT_SCANCLK=PORT_UNUSED 43 | PORT_SCANCLKENA=PORT_UNUSED 44 | PORT_SCANDATA=PORT_UNUSED 45 | PORT_SCANDATAOUT=PORT_UNUSED 46 | PORT_SCANDONE=PORT_UNUSED 47 | PORT_SCANREAD=PORT_UNUSED 48 | PORT_SCANWRITE=PORT_UNUSED 49 | PORT_clk0=PORT_USED 50 | PORT_clk1=PORT_USED 51 | PORT_clk2=PORT_USED 52 | PORT_clk3=PORT_USED 53 | PORT_clk4=PORT_UNUSED 54 | PORT_clk5=PORT_UNUSED 55 | PORT_clkena0=PORT_UNUSED 56 | PORT_clkena1=PORT_UNUSED 57 | PORT_clkena2=PORT_UNUSED 58 | PORT_clkena3=PORT_UNUSED 59 | PORT_clkena4=PORT_UNUSED 60 | PORT_clkena5=PORT_UNUSED 61 | PORT_extclk0=PORT_UNUSED 62 | PORT_extclk1=PORT_UNUSED 63 | PORT_extclk2=PORT_UNUSED 64 | PORT_extclk3=PORT_UNUSED 65 | WIDTH_CLOCK=5 66 | DEVICE_FAMILY="Cyclone IV E" 67 | CBX_AUTO_BLACKBOX=ALL 68 | inclk 69 | inclk 70 | clk 71 | clk 72 | clk 73 | clk 74 | -------------------------------------------------------------------------------- /src/wxeda/soundcodec.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // An open implementation of Vector-06C home computer 11 | // 12 | // Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | // 14 | // Modified by Ivan Gorodetsky 15 | // 16 | // Design File: soundcodec.v 17 | // 18 | // Audio interface between raw audio pulses from 8253, tape i/o and 19 | // sound codec. Includes simple moving average filter for all but 20 | // tape signals. 21 | // 22 | // This is a version for boards that have no audio codec. WXEDA board. 23 | // 24 | // Sigma-Delta modulated output on o_pwm 25 | // 26 | // -------------------------------------------------------------------- 27 | 28 | `default_nettype none 29 | 30 | module soundcodec(clk24, 31 | pulses, 32 | ay_soundA,ay_soundB,ay_soundC, 33 | rs_soundA,rs_soundB,rs_soundC, 34 | covox, 35 | tapein, reset_n, 36 | o_adc_clk, o_adc_cs_n, i_adc_data_in, 37 | o_pwm); 38 | input clk24; 39 | input [3:0] pulses; 40 | input [7:0] ay_soundA; 41 | input [7:0] ay_soundB; 42 | input [7:0] ay_soundC; 43 | input [7:0] rs_soundA; 44 | input [7:0] rs_soundB; 45 | input [7:0] rs_soundC; 46 | input [7:0] covox; 47 | output reg tapein; 48 | input reset_n; 49 | 50 | output o_adc_clk; 51 | output o_adc_cs_n; 52 | input i_adc_data_in; 53 | 54 | output reg o_pwm; 55 | 56 | parameter HYST = 4; 57 | parameter PWM_WIDTH = 9; 58 | 59 | // o +5V (from USB) 60 | // | 61 | // | / 62 | // o|| 8 Ohm PC 63 | // o|| Speaker 64 | // | \ 65 | // |/ 66 | // o----[ R27 ] -- | 2N3904 67 | // |\, 68 | // | 69 | // | 70 | // --- 71 | // - 72 | // 73 | // at 2:0 2N3904 runs quite hot when playing music through 8-ohm PC speaker, but its loud and nice 74 | // 3:0 it gets some time to chill, but the quality/loudness is worse 75 | reg [2:0] divctr; 76 | always @(posedge clk24) 77 | divctr <= divctr + 1'b1; 78 | wire delta_sigma_ce = divctr == 0; 79 | 80 | wire [2:0] beepsum = {pulses[0] + pulses[1] + pulses[2] + {2{pulses[3]}}}; 81 | wire [9:0] aysum = ay_soundA + ay_soundB + ay_soundC; 82 | wire [9:0] rssum = rs_soundA + rs_soundB + rs_soundC; 83 | 84 | wire [15:0] mixed = {beepsum, 13'b0} + 85 | `ifdef WITH_RSOUND 86 | {aysum, 4'b0} + {rssum, 4'b0} 87 | `else 88 | {aysum, 5'b0} 89 | `endif 90 | + {covox, 4'b0}; 91 | 92 | wire [7:0] line8in; 93 | tlc549c adc(.clk24(clk24), .adc_data_in(i_adc_data_in), .adc_data(line8in), .adc_clk(o_adc_clk), .adc_cs_n(o_adc_cs_n)); 94 | 95 | always @(posedge clk24) begin 96 | if (line8in < 128+HYST) tapein <= 1'b0; 97 | if (line8in > 128-HYST) tapein <= 1'b1; 98 | end 99 | 100 | reg [PWM_WIDTH:0] delta_sigma_accu; 101 | 102 | always @(posedge clk24) 103 | if (delta_sigma_ce) 104 | delta_sigma_accu <= delta_sigma_accu[PWM_WIDTH - 1:0] + mixed[15:15 - (PWM_WIDTH - 1)]; 105 | 106 | always 107 | o_pwm <= delta_sigma_accu[PWM_WIDTH]; 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /src/wxeda/tlc549c.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module tlc549c( 4 | input clk24, 5 | 6 | input adc_data_in, 7 | output reg [7:0] adc_data, 8 | output adc_clk, 9 | output reg adc_cs_n 10 | ); 11 | 12 | reg [7: 0] adc_data_buf; 13 | 14 | reg [3: 0] cnt; 15 | reg adc_clk_valid; 16 | reg adc_cs_n_valid; 17 | 18 | reg clk_40k; 19 | 20 | parameter SP_DIV = 5'd25; 21 | 22 | reg [3:0] clkdiv; 23 | reg clk_1m; 24 | wire ce_1m = clkdiv == 4'd0 && clk_1m; 25 | wire ce_2m = clkdiv == 4'd0; 26 | always@(posedge clk24) begin 27 | if (clkdiv + 1'b1 == 4'd12) begin 28 | clkdiv <= 0; 29 | clk_1m = !clk_1m; 30 | end 31 | else 32 | clkdiv <= clkdiv + 1'b1; 33 | end 34 | 35 | 36 | reg [8:0] cnt1; 37 | wire ce_40k = cnt1 == 0 && clk_40k; 38 | 39 | always @(posedge clk24) 40 | begin 41 | if (ce_2m) begin 42 | if(cnt1 + 1'b1 == 9'd25) begin 43 | cnt1 <= 0; 44 | clk_40k = !clk_40k; 45 | end 46 | else 47 | cnt1 <= cnt1 + 1'b1; 48 | end 49 | 50 | //adc_clk_valid <= !((cnt == 0) | (cnt == 1) | (cnt == 10)); 51 | //adc_cs_n <= !((cnt == 0) | (cnt == 10)); 52 | 53 | end 54 | 55 | always@(posedge clk24) 56 | if (ce_1m) begin 57 | if(clk_40k == 0) 58 | cnt <= 0; 59 | else if(cnt == 10) 60 | cnt <= 10; 61 | else 62 | cnt <= cnt + 1'b1; 63 | 64 | adc_clk_valid <= !((cnt == 0) | (cnt == 1) | (cnt == 10)); 65 | adc_cs_n <= (cnt == 0) | (cnt == 10); 66 | end 67 | 68 | //assign adc_clk = adc_clk_valid ? clk_1m : 1'b0; 69 | assign adc_clk = clk_1m; 70 | 71 | // always@(posedge adc_clk) 72 | // if(adc_cs_n == 0) 73 | // adc_data_buf <= {adc_data_in, adc_data_buf[7:1]}; 74 | always @(posedge clk24) 75 | begin 76 | if (ce_1m) 77 | adc_data_buf <= {adc_data_in, adc_data_buf[7:1]}; 78 | if (ce_1m && ce_40k) 79 | adc_data <= adc_data_buf; 80 | end 81 | endmodule 82 | -------------------------------------------------------------------------------- /src/wxeda/video/videomod.v: -------------------------------------------------------------------------------- 1 | // ==================================================================== 2 | // VECTOR-06C FPGA REPLICA 3 | // 4 | // Copyright (C) 2007-2016 Viacheslav Slavinsky 5 | // 6 | // This core is distributed under modified BSD license. 7 | // For complete licensing information see LICENSE.TXT. 8 | // -------------------------------------------------------------------- 9 | // 10 | // Video outputs, modulated and regular 11 | // 12 | // -------------------------------------------------------------------- 13 | 14 | 15 | `default_nettype none 16 | 17 | module videomod( 18 | input clk_color_mod, 19 | 20 | input [3:0] video_r, 21 | input [3:0] video_g, 22 | input [3:0] video_b, 23 | input vga_hs, 24 | input vga_vs, 25 | input [4:0] tv_cvbs, 26 | input [4:0] tv_luma, 27 | input [4:0] tv_chroma, 28 | 29 | output VGA_HS, 30 | output VGA_VS, 31 | output [3:0] VGA_R, 32 | output [3:0] VGA_G, 33 | output [3:0] VGA_B, 34 | output S_VIDEO_Y, 35 | output S_VIDEO_C, 36 | output CVBS 37 | 38 | ); 39 | 40 | 41 | wire [3:0] tv_out; 42 | 43 | `ifdef WITH_COMPOSITE 44 | `ifdef COMPOSITE_PWM 45 | reg [5:0] cvbs_pwm; 46 | always @(posedge clk_color_mod) 47 | cvbs_pwm <= cvbs_pwm[4:0] + tv_cvbs[4:0]; 48 | assign tv_out = {4{cvbs_pwm[5]}}; 49 | `else 50 | assign tv_out = tv_luma[3:0]; 51 | `endif 52 | `else 53 | assign tv_out = 4'b0; 54 | `endif 55 | 56 | `ifdef WITH_SVIDEO 57 | reg [5:0] luma_pwm; 58 | reg [5:0] chroma_pwm; 59 | always @(posedge clk_color_mod) begin 60 | luma_pwm <= luma_pwm[4:0] + tv_luma[4:0]; 61 | chroma_pwm <= chroma_pwm[4:0] + tv_chroma[4:0]; 62 | end 63 | assign S_VIDEO_Y = luma_pwm[5]; 64 | assign S_VIDEO_C = chroma_pwm[5]; 65 | `endif 66 | 67 | `ifdef WITH_COMPOSITE 68 | assign VGA_R = tv_out; 69 | assign VGA_G = tv_out; 70 | assign VGA_B = tv_out; 71 | `else 72 | `ifdef WITH_VGA 73 | assign VGA_R = video_r; 74 | assign VGA_G = video_g; 75 | assign VGA_B = video_b; 76 | `else 77 | assign VGA_R = 4'b0; 78 | assign VGA_G = 4'b0; 79 | assign VGA_B = 4'b0; 80 | `endif 81 | `endif 82 | 83 | assign VGA_VS = vga_vs; 84 | assign VGA_HS = vga_hs; 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /src/wxeda/wxeda_clocks.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/wxeda/wxeda_clocks.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "wxeda_clocks.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "wxeda_clocks_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "wxeda_clocks.ppf"] 6 | -------------------------------------------------------------------------------- /src/zagr512.hex: -------------------------------------------------------------------------------- 1 | :200000003E9BD3043E88D3003EA8014000D30891D20D00DB01A14878D310CA2900020CC242 2 | :200020001D0004C21D00C339002100C03EE07023BCC22E00C3390000C93E06D30031F0DCAD 3 | :200040001109000EFF606ACD91042D7119712C368104C24500FB76CD7202212A0611E9C476 4 | :200060003E080607CD070621B500E53EC332F1DC32F4DC3AF7DEFEFBCADB06FEEFCAAC0080 5 | :20008000FEF7CA9703FEE7CA9A00FECFCAA000FED7CAA600CDAA04C2E904CD2F01CAB80297 6 | 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/testbits.hex: -------------------------------------------------------------------------------- 1 | :20000000FFFFFFFF2222000044440000AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA44BC 2 | :20002000222222224444444433333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA4400 3 | :20004000222222224444444433333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA44E0 4 | :20006000222222224444444433333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA44C0 5 | :20008000FFF5000036360000AAAA00002A2A2A2AAAAAAAAA2222222244AAAA442222222270 6 | :2000A0004444444433333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA442222222280 7 | :2000C0004444444433333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA442222222260 8 | :2000E0004444444433333333AAAAAAAA2A2A2A2AAAAAAAAA2222222222222222444444440C 9 | :20010000FF005F002A2A000044440000AAAAAAAA2222222244AAAA44222222224444444401 10 | :2001200033333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA442222222244444444FF 11 | :2001400033333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA442222222244444444DF 12 | :2001600033333333AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA4444444444333333337B 13 | :20018000FF0000F522220000000000002222222244AAAA442222222244444444333333335F 14 | :2001A000AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA442222222244444444333333337F 15 | :2001C000AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA442222222244444444333333335F 16 | :2001E000AAAAAAAA2A2A2A2AAAAAAAAA2222222244AAAA442222222244AAAA4422222222B7 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /tools/pal.py: -------------------------------------------------------------------------------- 1 | from math import * 2 | 3 | def pal_coeffs(chord): 4 | U=[-0.147,-0.288,0.436] 5 | V=[0.615,-0.515,-0.1] 6 | 7 | print "\nU+V coefficients at R,G,B for %d phase angles (alpha-5/8):" % chord 8 | 9 | for c in iter(map(lambda a:map(sum, zip(map(lambda x:x*cos(a),V),map(lambda x:x*sin(a),U))), map(lambda x:(x-5/8)*2*pi/chord,range(chord)))): 10 | print "%+2.4f %+2.4f %+2.4f uvsum #(%+4d,%+4d,%+4d)" % tuple(c+map(lambda x:int(x*(2*0.714*256/3.3)*0.72),c)) 11 | 12 | print "\nU-V coefficients at R,G,B for %d phase angles (alpha-3/8):" % chord 13 | for c in iter(map(lambda a:map(sum, zip(map(lambda x:-x*cos(a),V),map(lambda x:x*sin(a),U))), map(lambda x:(x-3/8)*2*pi/chord,range(chord)))): 14 | print "%+2.4f %+2.4f %+2.4f uvsum #(%+4d,%+4d,%+4d)" % tuple(c+map(lambda x:int(x*(2*0.714*256/3.3)*0.72),c)) 15 | 16 | 17 | 18 | def pal_calculate(clk,subcarrier,anglesteps,accu_bits): 19 | multiplier = 2**(accu_bits-3) 20 | print "\nPAL color everything finder" 21 | print "\nFor clk=%f MHz and target subcarrier frequency %f" % (clk, subcarrier) 22 | print "\nPhase accumulator increment = %d" % (round(multiplier*anglesteps/(clk/subcarrier))) 23 | pal_coeffs(anglesteps) 24 | 25 | #map(lambda x:x*2*pi/chord,range(chord)) 26 | 27 | 28 | #pal_calculate(24,4.43361875,4,32) 29 | pal_calculate(24,4.43361875,8,32) 30 | 31 | 32 | Fmclk=150e6 33 | Fsc=4433618.750 34 | width=32 35 | 36 | dPhase=8*Fsc/Fmclk*2**width 37 | 38 | print "Fmclk=%f" % Fmclk 39 | print "Fsc=%f" % Fsc 40 | print "Phase accumulator width = %d" % width 41 | print "delta phase=%d" % int(round(dPhase)) 42 | print "expected 8*Fsc=%f, Fsc=%f" % (dPhase*Fmclk/2**width, dPhase*Fmclk/2**width/8) 43 | 44 | Fsc=14000000 45 | width=16 46 | dPhase=4*Fsc/Fmclk*2**width 47 | print "For 14MHz clock, 16-bit accumulator, delta word=%d" % int(round(dPhase)) 48 | 49 | Fsc=18000000 50 | width=16 51 | dPhase=4*Fsc/Fmclk*2**width 52 | print "For 18MHz clock, 16-bit accumulator, delta word=%d" % int(round(dPhase)) -------------------------------------------------------------------------------- /tools/pal16.py: -------------------------------------------------------------------------------- 1 | from math import * 2 | 3 | def pal_coeffs(chord): 4 | U=[-0.147,-0.288,0.436] 5 | V=[0.615,-0.515,-0.1] 6 | 7 | print "\nU+V coefficients at R,G,B for %d phase angles (alpha-5/8):" % chord 8 | 9 | for c in iter(map(lambda a:map(sum, zip(map(lambda x:x*cos(a),V),map(lambda x:x*sin(a),U))), map(lambda x:(x-5/8)*2*pi/chord,range(chord)))): 10 | print "%+2.4f %+2.4f %+2.4f uvsum #(%+4d,%+4d,%+4d)" % tuple(c+map(lambda x:int(x*(2*0.714*256/3.3)*0.72),c)) 11 | 12 | print "\nU-V coefficients at R,G,B for %d phase angles (alpha-3/8):" % chord 13 | for c in iter(map(lambda a:map(sum, zip(map(lambda x:-x*cos(a),V),map(lambda x:x*sin(a),U))), map(lambda x:(x-3/8)*2*pi/chord,range(chord)))): 14 | print "%+2.4f %+2.4f %+2.4f uvsum #(%+4d,%+4d,%+4d)" % tuple(c+map(lambda x:int(x*(2*0.714*256/3.3)*0.72),c)) 15 | 16 | 17 | 18 | def pal_calculate(clk,subcarrier,anglesteps,accu_bits): 19 | multiplier = 2**(accu_bits-3) 20 | print "\nPAL color everything finder" 21 | print "\nFor clk=%f MHz and target subcarrier frequency %f" % (clk, subcarrier) 22 | print "\nPhase accumulator increment = %d" % (round(multiplier*anglesteps/(clk/subcarrier))) 23 | pal_coeffs(anglesteps) 24 | 25 | #map(lambda x:x*2*pi/chord,range(chord)) 26 | 27 | 28 | #pal_calculate(24,4.43361875,4,32) 29 | pal_calculate(24,4.43361875,16,32) 30 | 31 | 32 | Fmclk=300e6 33 | Fsc=4433618.750 34 | width=32 35 | 36 | dPhase=16*Fsc/Fmclk*2**width 37 | 38 | print "Fmclk=%f" % Fmclk 39 | print "Fsc=%f" % Fsc 40 | print "Phase accumulator width = %d" % width 41 | print "delta phase=%d" % int(round(dPhase)) 42 | print "expected 16*Fsc=%f, Fsc=%f" % (dPhase*Fmclk/2**width, dPhase*Fmclk/2**width/8) 43 | 44 | Fsc=14000000 45 | width=16 46 | dPhase=4*Fsc/Fmclk*2**width 47 | print "For 14MHz clock, 16-bit accumulator, delta word=%d" % int(round(dPhase)) 48 | 49 | Fsc=18000000 50 | width=16 51 | dPhase=4*Fsc/Fmclk*2**width 52 | print "For 18MHz clock, 16-bit accumulator, delta word=%d" % int(round(dPhase)) -------------------------------------------------------------------------------- /tools/pal4.py: -------------------------------------------------------------------------------- 1 | from math import * 2 | 3 | def pal_coeffs(chord): 4 | U=[-0.147,-0.288,0.436] 5 | V=[0.615,-0.515,-0.1] 6 | 7 | print "\nU+V coefficients at R,G,B for %d phase angles (alpha-5/8):" % chord 8 | 9 | for c in iter(map(lambda a:map(sum, zip(map(lambda x:x*cos(a),V),map(lambda x:x*sin(a),U))), map(lambda x:(x-5/(2.0*chord))*2*pi/chord,range(chord)))): 10 | print "%+2.4f %+2.4f %+2.4f uvsum #(%+4d,%+4d,%+4d)" % tuple(c+map(lambda x:int(x*(2*0.714*256/3.3)*0.72),c)) 11 | 12 | print "\nU-V coefficients at R,G,B for %d phase angles (alpha-3/8):" % chord 13 | for c in iter(map(lambda a:map(sum, zip(map(lambda x:-x*cos(a),V),map(lambda x:x*sin(a),U))), map(lambda x:(x-3/(2.0*chord))*2*pi/chord,range(chord)))): 14 | print "%+2.4f %+2.4f %+2.4f uvsum #(%+4d,%+4d,%+4d)" % tuple(c+map(lambda x:int(x*(2*0.714*256/3.3)*0.72),c)) 15 | 16 | 17 | 18 | def pal_calculate(clk,subcarrier,anglesteps,accu_bits): 19 | multiplier = 2**(accu_bits-3) 20 | print "\nPAL color everything finder" 21 | print "\nFor clk=%f MHz and target subcarrier frequency %f" % (clk, subcarrier) 22 | print "\nPhase accumulator increment = %d" % (round(multiplier*anglesteps/(clk/subcarrier))) 23 | pal_coeffs(anglesteps) 24 | 25 | #map(lambda x:x*2*pi/chord,range(chord)) 26 | 27 | 28 | #pal_calculate(24,4.43361875,4,32) 29 | pal_calculate(24,4.43361875,4,32) 30 | 31 | 32 | Fmclk=300e6 33 | Fsc=4433618.750 34 | width=32 35 | 36 | dPhase=4*Fsc/Fmclk*2**width 37 | 38 | print "Fmclk=%f" % Fmclk 39 | print "Fsc=%f" % Fsc 40 | print "Phase accumulator width = %d" % width 41 | print "delta phase=%d" % int(round(dPhase)) 42 | print "expected 4*Fsc=%f, Fsc=%f" % (dPhase*Fmclk/2**width, dPhase*Fmclk/2**width/4) 43 | 44 | dPhase = dPhase - 60 45 | print "expected 4*Fsc=%f, Fsc=%f" % (dPhase*Fmclk/2**width, dPhase*Fmclk/2**width/4) 46 | 47 | Fsc=14000000 48 | width=16 49 | dPhase=4*Fsc/Fmclk*2**width 50 | print "For 14MHz clock, 16-bit accumulator, delta word=%d" % int(round(dPhase)) 51 | 52 | Fsc=18000000 53 | width=16 54 | dPhase=4*Fsc/Fmclk*2**width 55 | print "For 18MHz clock, 16-bit accumulator, delta word=%d" % int(round(dPhase)) -------------------------------------------------------------------------------- /workbench/cputest/build.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | if ""=="%1" @goto error 3 | set P=%1 4 | 5 | del %P%.com 6 | c:\bin\as\bin\asw %P%.asm 7 | c:\bin\as\bin\p2bin -r 256-2048 %P%.p 8 | ren %P%.bin %P%.com 9 | del %P%.p 10 | 11 | :error 12 | echo usage: build.bat sourcefile-without-extension 13 | 14 | :done -------------------------------------------------------------------------------- /workbench/cputest/cputype.asm: -------------------------------------------------------------------------------- 1 | cpu 8080 2 | org 100h 3 | 4 | lxi d, hellojpg 5 | mvi c, 9 6 | call 5 7 | call cpudetect 8 | mvi c, 9 9 | call 5 10 | ret 11 | hellojpg db "DETECTING CPU TYPE",0dh,0ah,"THE CPU IS: $" 12 | msg_z80 db "Z80$" 13 | msg_8080 db "KP580BM80A$" 14 | msg_vm1 db "KP580BM1$" 15 | cpudetect: 16 | lxi d, msg_z80 17 | 18 | xra a 19 | dcr a 20 | rpo 21 | 22 | lxi h, 0020h 23 | push h 24 | pop psw 25 | push psw 26 | pop h 27 | mvi a, 20h 28 | ana l 29 | jz kr580 30 | lxi d, msg_vm1 31 | ret 32 | kr580: lxi d, msg_8080 33 | ret 34 | 35 | end 36 | -------------------------------------------------------------------------------- /workbench/cputest/cputype.com: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/workbench/cputest/cputype.com -------------------------------------------------------------------------------- /workbench/cputest/latch.asm: -------------------------------------------------------------------------------- 1 | ;; ==================================================================== 2 | ;; VECTOR-06C FPGA REPLICA 3 | ;; 4 | ;; Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | ;; 6 | ;; This core is distributed under modified BSD license. 7 | ;; For complete licensing information see LICENSE.TXT. 8 | ;; -------------------------------------------------------------------- 9 | ;; 10 | ;; An open implementation of Vector-06C home computer 11 | ;; 12 | ;; Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | ;; 14 | ;; This will test timer latching, to some extent anyway. 15 | ;; 16 | ;; -------------------------------------------------------------------- 17 | 18 | cpu 8080 19 | org 00100H 20 | 21 | xra a 22 | sta flag 23 | lxi h, lolz 24 | call msg 25 | lxi h, crlf 26 | call msg 27 | call timer ;jump to timer diagnostic 28 | ret 29 | ; 30 | lolz db "VECTOR-06C TIMER LATCH PROBULATOR" 31 | crlf db 0dh, 0ah, '$' 32 | goodmsg db "Good latched MSB: $" 33 | badmsg db "Bad latched MSB: $" 34 | 35 | ; 36 | ; Message output 37 | ; 38 | msg: push psw 39 | push d 40 | mvi c, 9 41 | mov d,h 42 | mov e,l 43 | call 5 44 | pop d 45 | msgret: pop psw 46 | ret 47 | ; 48 | ; character output routine 49 | ; 50 | pchar: push psw 51 | push d 52 | push h 53 | mov e,a 54 | mvi c,2 55 | call 5 56 | pop h 57 | pop d 58 | pop psw 59 | ret 60 | ; 61 | ; Byte output (from Kelly Smith test) 62 | ; 63 | byteo: push psw 64 | call byto1 65 | mov e,a 66 | call pchar 67 | pop psw 68 | call byto2 69 | mov e,a 70 | jmp pchar 71 | byto1: rrc 72 | rrc 73 | rrc 74 | rrc 75 | byto2: ani 0fh 76 | cpi 0ah 77 | jm byto3 78 | adi 7 79 | byto3: adi 30h 80 | ret 81 | 82 | timer: 83 | di 84 | mvi a, 34h ; ctr 0, mode 2, lsb/msb, binary 85 | out 08h 86 | 87 | mvi a, 80h ; 88 | out 0bh 89 | out 0bh ; load msb = lsb 90 | 91 | mvi a, 0h 92 | out 08h ; latch the counter 93 | 94 | in 0bh ; skip lsb 95 | 96 | ; really wait some time 97 | lxi h, 0ffffh 98 | really: 99 | dcx h 100 | mov a,h 101 | ora l 102 | jnz really 103 | 104 | in 0bh 105 | push psw 106 | cpi 80h 107 | jnz baaad 108 | lxi h, goodmsg 109 | jmp over 110 | baaad: 111 | lxi h, badmsg 112 | over: 113 | call msg 114 | pop psw 115 | call byteo 116 | ret 117 | flag: 118 | db 0 119 | 120 | end 121 | 122 | ;; $Id$ 123 | -------------------------------------------------------------------------------- /workbench/cputest/latch.com: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/workbench/cputest/latch.com -------------------------------------------------------------------------------- /workbench/cputest/make.bat: -------------------------------------------------------------------------------- 1 | @call build.bat test 2 | @call build.bat cputype 3 | :all build.bat timer 4 | @call build.bat latch -------------------------------------------------------------------------------- /workbench/cputest/test.com: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/workbench/cputest/test.com -------------------------------------------------------------------------------- /workbench/cputest/timer.asm: -------------------------------------------------------------------------------- 1 | ;; ==================================================================== 2 | ;; VECTOR-06C FPGA REPLICA 3 | ;; 4 | ;; Copyright (C) 2007,2008 Viacheslav Slavinsky 5 | ;; 6 | ;; This core is distributed under modified BSD license. 7 | ;; For complete licensing information see LICENSE.TXT. 8 | ;; -------------------------------------------------------------------- 9 | ;; 10 | ;; An open implementation of Vector-06C home computer 11 | ;; 12 | ;; Author: Viacheslav Slavinsky, http://sensi.org/~svo 13 | ;; 14 | ;; Timer test program. This piece is based on a timer probe 15 | ;; routine found in the SkyNet demo by Sunami et al. 16 | ;; 17 | ;; -------------------------------------------------------------------- 18 | 19 | cpu 8080 20 | org 00100H 21 | 22 | xra a 23 | sta flag 24 | lxi h, lolz 25 | call msg 26 | lxi h, crlf 27 | call msg 28 | jmp timer ;jump to timer diagnostic 29 | ; 30 | lolz db "VECTOR-06C TIMER PROBULATOR" 31 | crlf db 0dh, 0ah, '$' 32 | expec db "Expected $" 33 | bad1 db "B0, got:$" 34 | bad2 db "50, got:$" 35 | bad3 db "30, got:$" 36 | badnik db "Bad, useless timer.$" 37 | good db "It must be a very good timer!$" 38 | 39 | ; 40 | ; Message output 41 | ; 42 | msg: push psw 43 | push d 44 | mvi c, 9 45 | mov d,h 46 | mov e,l 47 | call 5 48 | pop d 49 | msgret: pop psw 50 | ret 51 | ; 52 | ; character output routine 53 | ; 54 | pchar: push psw 55 | push d 56 | push h 57 | mov e,a 58 | mvi c,2 59 | call 5 60 | pop h 61 | pop d 62 | pop psw 63 | ret 64 | ; 65 | ; Byte output (from Kelly Smith test) 66 | ; 67 | byteo: push psw 68 | call byto1 69 | mov e,a 70 | call pchar 71 | pop psw 72 | call byto2 73 | mov e,a 74 | jmp pchar 75 | byto1: rrc 76 | rrc 77 | rrc 78 | rrc 79 | byto2: ani 0fh 80 | cpi 0ah 81 | jm byto3 82 | adi 7 83 | byto3: adi 30h 84 | ret 85 | 86 | timer: 87 | di 88 | mvi a, 14h ; ctr 0, mode 2, lsb only, binary 89 | out 08h 90 | 91 | mvi a, 80h ; load value into ctr0 92 | out 0bh 93 | 94 | mvi a, 54h ; ctr 1, mode 2, lsb only, binary 95 | out 08h 96 | 97 | mvi a, 60h ; load ctr 1 98 | out 0ah 99 | 100 | mvi a, 94h ; ctr 2, mode 2, lsb only, binary 101 | out 08h 102 | 103 | mvi a, 0e0h ; load ctr 2 104 | out 09h 105 | 106 | mvi a, 00h ; ctr 0, latch value 107 | out 08h 108 | 109 | in 0bh ; read value of ctr0 110 | mov c, a 111 | 112 | mvi a, 40h ; load ctr 0 113 | out 08h 114 | 115 | in 0ah ; read ctr 1 116 | mov b, a 117 | 118 | mvi a, 80h ; ctr 2, latch value 119 | out 08h 120 | 121 | in 09h ; read ctr 2 122 | mvi d, 01 123 | cpi 0b0h 124 | cnz fail1 125 | 126 | mov a, c 127 | cpi 50h 128 | cnz fail2 129 | 130 | mov a, b 131 | cpi 30h 132 | cnz fail3 133 | 134 | lda flag 135 | ora a 136 | jnz noir 137 | lxi h, good 138 | call msg 139 | jmp gagg 140 | 141 | noir: 142 | lxi h, badnik 143 | call msg 144 | gagg: 145 | mvi a, 10h 146 | mvi b, 40h 147 | out 8 148 | out 0bh 149 | add b 150 | out 8 151 | out 0ah 152 | add b 153 | out 8 154 | out 09h 155 | ret 156 | fail1: 157 | lxi h, bad1 158 | jmp fail 159 | fail2: 160 | lxi h, bad2 161 | jmp fail 162 | fail3: 163 | lxi h, bad3 164 | fail: 165 | push b 166 | push d 167 | push psw 168 | push h 169 | lxi h, expec 170 | call msg 171 | pop h 172 | call msg 173 | mvi a, 1 174 | sta flag 175 | pop psw 176 | call byteo 177 | lxi h, crlf 178 | call msg 179 | pop d 180 | pop b 181 | ret 182 | flag: 183 | db 0 184 | 185 | end 186 | 187 | ;; $Id$ 188 | -------------------------------------------------------------------------------- /workbench/cputest/timer.com: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/svofski/vector06cc/177ca4294911bfb4d91cedffc88badba02edb502/workbench/cputest/timer.com -------------------------------------------------------------------------------- /workbench/cputest/zap.bat: -------------------------------------------------------------------------------- 1 | @del timer.com 2 | @del cputype.com 3 | @del test.com -------------------------------------------------------------------------------- /workbench/floppy/fauxpaw.hex: -------------------------------------------------------------------------------- 1 | :0100000011EE 2 | :0100010022DC 3 | :0100020030CD 4 | :010003007B81 5 | :01000400C932 6 | :01000500DA20 7 | :010006000DEC 8 | :01000700F206 9 | :010008000FE8 10 | :01000900A74F 11 | :01000A0037BE 12 | :01000B003FB5 13 | :01000C0021D2 14 | :01000D00DE14 15 | :01000E00AD44 16 | :01000F00FFF1 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /workbench/floppy/floppywb.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP2C20F484) Path("C:/usr/src/vector06cc/workbench/floppy/") File("floppywb.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /workbench/floppy/floppywb.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2007 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "7.1" 18 | DATE = "03:36:01 December 22, 2007" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "floppywb" 24 | -------------------------------------------------------------------------------- /workbench/floppy/floppywb.qws: -------------------------------------------------------------------------------- 1 | [ProjectWorkspace] 2 | ptn_Child1=Frames 3 | [ProjectWorkspace.Frames] 4 | ptn_Child1=ChildFrames 5 | [ProjectWorkspace.Frames.ChildFrames] 6 | ptn_Child1=Document-0 7 | <<<<<<< .mine 8 | ptn_Child2=Document-1 9 | ptn_Child3=Document-2 10 | ptn_Child4=Document-3 11 | ptn_Child5=Document-4 12 | [ProjectWorkspace.Frames.ChildFrames.Document-1] 13 | ======= 14 | ptn_Child2=Document-1 15 | ptn_Child3=Document-2 16 | ptn_Child4=Document-3 17 | ptn_Child5=Document-4 18 | ptn_Child6=Document-5 19 | ptn_Child7=Document-6 20 | [ProjectWorkspace.Frames.ChildFrames.Document-0] 21 | >>>>>>> .r192 22 | ptn_Child1=ViewFrame-0 23 | [ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] 24 | DocPathName=src/floppywb.v 25 | DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} 26 | IsChildFrameDetached=False 27 | <<<<<<< .mine 28 | IsActiveChildFrame=False 29 | ptn_Child1=StateMap 30 | [ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap] 31 | AFC_IN_REPORT=False 32 | [ProjectWorkspace.Frames.ChildFrames.Document-2] 33 | ptn_Child1=ViewFrame-0 34 | [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] 35 | DocPathName=../../src/floppy/floppy.v 36 | DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} 37 | IsChildFrameDetached=False 38 | IsActiveChildFrame=False 39 | ptn_Child1=StateMap 40 | [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap] 41 | AFC_IN_REPORT=False 42 | [ProjectWorkspace.Frames.ChildFrames.Document-3] 43 | ptn_Child1=ViewFrame-0 44 | [ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0] 45 | DocPathName=src/floppywb.v 46 | DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} 47 | IsChildFrameDetached=False 48 | IsActiveChildFrame=True 49 | ======= 50 | IsActiveChildFrame=False 51 | >>>>>>> .r192 52 | ptn_Child1=StateMap 53 | [ProjectWorkspace.Frames.ChildFrames.Document-3.ViewFrame-0.StateMap] 54 | AFC_IN_REPORT=False 55 | [ProjectWorkspace.Frames.ChildFrames.Document-1] 56 | ptn_Child1=ViewFrame-0 57 | [ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] 58 | DocPathName=../../src/floppy/floppy.v 59 | DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} 60 | IsChildFrameDetached=False 61 | IsActiveChildFrame=False 62 | ptn_Child1=StateMap 63 | [ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap] 64 | AFC_IN_REPORT=False 65 | [ProjectWorkspace.Frames.ChildFrames.Document-2] 66 | ptn_Child1=ViewFrame-0 67 | [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] 68 | DocPathName=../../src/floppy/wd1793.v 69 | DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} 70 | IsChildFrameDetached=False 71 | IsActiveChildFrame=False 72 | ptn_Child1=StateMap 73 | [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap] 74 | AFC_IN_REPORT=False 75 | -------------------------------------------------------------------------------- /workbench/floppy/src/floppywb.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | `define noSIM 4 | 5 | module floppywb(CLOCK_27, KEY[3:0], LEDr[9:0], LEDg[7:0], SW[9:0], HEX0, HEX1, HEX2, HEX3, 6 | //////////////////// SRAM Interface //////////////// 7 | SRAM_DQ, // SRAM Data bus 16 Bits 8 | SRAM_ADDR, // SRAM Address bus 18 Bits 9 | SRAM_UB_N, // SRAM High-byte Data Mask 10 | SRAM_LB_N, // SRAM Low-byte Data Mask 11 | SRAM_WE_N, // SRAM Write Enable 12 | SRAM_CE_N, // SRAM Chip Enable 13 | SRAM_OE_N, // SRAM Output Enable 14 | 15 | //////////////////// SD_Card Interface //////////////// 16 | SD_DAT, // SD Card Data 17 | SD_DAT3, // SD Card Data 3 18 | SD_CMD, // SD Card Command Signal 19 | SD_CLK, // SD Card Clock 20 | 21 | ///////////////////// USRAT ////////////////////// 22 | UART_TXD, 23 | UART_RXD, 24 | 25 | // host interface (to vector) 26 | hostio_addr, 27 | hostio_idata, 28 | hostio_odata, 29 | hostio_rd, 30 | hostio_wr, 31 | 32 | 33 | GPIO_0 34 | `ifdef SIM 35 | , 36 | floppy_odata, 37 | floppy_debug, 38 | floppy_abus, 39 | debugidata, opcode 40 | `endif 41 | ); 42 | input [1:0] CLOCK_27; 43 | input [3:0] KEY; 44 | output [9:0] LEDr; 45 | output [7:0] LEDg; 46 | input [9:0] SW; 47 | 48 | output [6:0] HEX0; 49 | output [6:0] HEX1; 50 | output [6:0] HEX2; 51 | output [6:0] HEX3; 52 | 53 | //////////////////////// SRAM Interface //////////////////////// 54 | inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits 55 | output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits 56 | output SRAM_UB_N; // SRAM High-byte Data Mask 57 | output SRAM_LB_N; // SRAM Low-byte Data Mask 58 | output SRAM_WE_N; // SRAM Write Enable 59 | output SRAM_CE_N; // SRAM Chip Enable 60 | output SRAM_OE_N; // SRAM Output Enable 61 | 62 | //////////////////// SD Card Interface //////////////////////// 63 | input SD_DAT; // SD Card Data (MISO) 64 | output SD_DAT3; // SD Card Data 3 (CSn) 65 | output SD_CMD; // SD Card Command Signal (MOSI) 66 | output SD_CLK; // SD Card Clock (SCK) 67 | 68 | output UART_TXD; 69 | input UART_RXD; 70 | 71 | // I/O interface to host system (Vector) 72 | input [2:0] hostio_addr; 73 | input [7:0] hostio_idata; 74 | output [7:0] hostio_odata; 75 | input hostio_rd; 76 | input hostio_wr; 77 | 78 | output [12:0] GPIO_0; 79 | 80 | `ifdef SIM 81 | output [7:0] floppy_odata; 82 | output [7:0] floppy_debug; 83 | output [15:0] floppy_abus; 84 | output [7:0] debugidata; 85 | output [7:0] opcode; 86 | `endif 87 | 88 | // CLOCK SETUP 89 | wire mreset_n = KEY[0]; 90 | wire mreset = !mreset_n; 91 | wire clk24, clk18; 92 | wire ce12, ce6, ce3, ce3v, vi53_timer_ce, video_slice, pipe_ab; 93 | 94 | clockster clockmaker( 95 | .clk(CLOCK_27[0]), 96 | .clk24(clk24), 97 | .clk18(clk18), 98 | .ce12(ce12), 99 | .ce6(ce6), 100 | .ce3(ce3), 101 | .ce3v(ce3v), 102 | .video_slice(video_slice), 103 | .pipe_ab(pipe_ab), 104 | .ce1m5(vi53_timer_ce)); 105 | 106 | 107 | assign SRAM_ADDR = 0; 108 | assign SRAM_OE_N = 1; 109 | assign SRAM_CE_N = 1; 110 | assign SRAM_WE_N = 1; 111 | assign SRAM_UB_N = 1; 112 | assign SRAM_LB_N = 1; 113 | assign SRAM_DQ = 16'bZZZZZZZZZZZZZZZZ; 114 | 115 | assign GPIO_0 = {ce12, ce6, ce3, ce3v, vi53_timer_ce, video_slice, pipe_ab}; 116 | //assign LEDg = floppy_odata; 117 | //assign LEDr = floppy_abus; 118 | assign floppy_idata = SRAM_DQ[7:0]; 119 | //assign SRAM_ADDR = floppy_abus; 120 | //assign SRAM_WE_N = floppy_memwr; 121 | 122 | wire [15:0] floppy_abus; 123 | wire [7:0] floppy_idata; 124 | wire [7:0] floppy_odata; 125 | wire floppy_memwr; 126 | 127 | reg [21:0] slowclock; 128 | always @(posedge clk24) if (ce3v) slowclock <= slowclock + 1'b1; 129 | 130 | `ifdef SIM 131 | wire floppy_ce = 1; 132 | `else 133 | wire floppy_ce = SW[9] ? ce3v : &slowclock & ce3v; 134 | `endif 135 | 136 | floppy disk( 137 | .clk(clk24), 138 | .ce(floppy_ce), 139 | .reset_n(mreset_n), 140 | .addr(floppy_abus), 141 | .idata(floppy_idata), 142 | .odata(floppy_odata), 143 | .memwr(floppy_memwr), 144 | 145 | // host interface (to vector) 146 | .hostio_addr(hostio_addr), 147 | .hostio_idata(hostio_idata), 148 | .hostio_odata(hostio_odata), 149 | .hostio_rd(hostio_rd), 150 | .hostio_wr(hostio_wr), 151 | 152 | .sd_dat(SD_DAT), 153 | .sd_dat3(SD_DAT3), 154 | .sd_cmd(SD_CMD), 155 | .sd_clk(SD_CLK), 156 | .green_leds(LEDg), 157 | .red_leds(LEDr[7:0]), 158 | .uart_txd(UART_TXD) 159 | `ifdef SIM 160 | , 161 | .debug(floppy_debug), 162 | .debugidata(debugidata), 163 | .opcode(opcode) 164 | `endif 165 | ); 166 | 167 | SEG7_LUT_4 seg7display(HEX0, HEX1, HEX2, HEX3, floppy_abus); 168 | 169 | endmodule 170 | -------------------------------------------------------------------------------- /workbench/floppy/src/uart/txd.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------ 2 | ------------------------------------------------------------------------------ 3 | -- -- 4 | -- Copyright (c) 2007 Tobias Gubener -- 5 | -- -- 6 | -- This source file is free software: you can redistribute it and/or modify -- 7 | -- it under the terms of the GNU General Public License as published -- 8 | -- by the Free Software Foundation, either version 3 of the License, or -- 9 | -- (at your option) any later version. -- 10 | -- -- 11 | -- This source file is distributed in the hope that it will be useful, -- 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- 14 | -- GNU General Public License for more details. -- 15 | -- -- 16 | -- You should have received a copy of the GNU General Public License -- 17 | -- along with this program. If not, see . -- 18 | -- -- 19 | ------------------------------------------------------------------------------ 20 | ------------------------------------------------------------------------------ 21 | 22 | library IEEE; 23 | use IEEE.std_logic_1164.all; 24 | use IEEE.STD_LOGIC_UNSIGNED.all; 25 | 26 | 27 | entity TXD is 28 | port ( 29 | clk: in std_logic; 30 | ld: in std_logic; 31 | data: in std_logic_vector(7 downto 0); 32 | TxD: out std_logic; 33 | txbusy: buffer std_logic 34 | ); 35 | 36 | end TXD; 37 | 38 | 39 | architecture TXD of TXD is 40 | 41 | signal shift: std_logic_vector(9 downto 0); 42 | signal clkgen: std_logic_vector(9 downto 0); 43 | signal stop: std_logic; 44 | signal shiftout: std_logic; 45 | 46 | begin 47 | TxD <= not shiftout; 48 | process(clk, shift) 49 | begin 50 | if shift = "0000000000" then 51 | txbusy <= '0'; 52 | else 53 | txbusy <= '1'; 54 | end if; 55 | 56 | if clk'event and clk = '1' then 57 | if ld = '1' then 58 | shiftout <= '0'; 59 | shift <= '1' & data & '0'; --STOP,MSB...LSB, START 60 | end if; 61 | if clkgen/=0 then 62 | if ld = '1' and stop = '0' then 63 | clkgen <= "0000000001"; 64 | else 65 | clkgen <= clkgen-1; 66 | end if; 67 | else 68 | -- clkgen <= "1101000000";--832; --96MHz/115200 69 | -- clkgen <= "0111100101";--487; --56MHz/115200 70 | -- clkgen <= "0011110010";--243; --28MHz/115200 71 | clkgen <= "0011010000"; --24MHz/115200 72 | -- clkgen <= "1001110001"; --24MHz/38400 73 | shiftout <= not(shift(0) or not txbusy or ld); 74 | stop <= shift(0); 75 | shift <= '0' & shift(9 downto 1); 76 | end if; 77 | end if; 78 | end process; 79 | 80 | end TXD; 81 | -------------------------------------------------------------------------------- /workbench/floppy/src/wd-alone.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module wdalone(clk, reset_n, rd, wr, addr, idata, odata, buff_addr, buff_rd, buff_wr, buff_idata, buff_odata, 4 | track, sector, cpu_command, cpu_status, wd_status, wtf); 5 | 6 | 7 | input clk; 8 | input reset_n; 9 | input rd, wr; 10 | input [2:0] addr; 11 | input [7:0] idata; 12 | output [7:0] odata; 13 | 14 | output [8:0] buff_addr; 15 | output buff_rd; 16 | output buff_wr; 17 | output [7:0] buff_idata; 18 | output [7:0] buff_odata; 19 | 20 | output [7:0] track; 21 | output [7:0] sector; 22 | output [7:0] cpu_command; 23 | input [7:0] cpu_status; 24 | output [7:0] wd_status; 25 | output wtf; 26 | 27 | wire [7:0] buff_idata; 28 | 29 | wd1793 vg93(.clk(clk), .clken(1'b1), .reset_n(reset_n), 30 | .rd(rd), .wr(wr), .addr(addr), .idata(idata), .odata(odata), 31 | .buff_addr(buff_addr), .buff_rd(buff_rd), .buff_wr(buff_wr), 32 | .buff_idata(buff_idata), .buff_odata(buff_odata), 33 | .oTRACK(track), 34 | .oSECTOR(sector), 35 | .oCPU_REQUEST(cpu_command), 36 | .iCPU_STATUS(cpu_status), 37 | .oSTATUS(wd_status), 38 | .wtf(wtf)); 39 | 40 | fake_ram fauxpaw( 41 | .address(buff_addr), 42 | .data(buff_odata), 43 | .inclock(~clk), .outclock(clk), 44 | .wren(buff_wr), 45 | .q(buff_idata)); 46 | 47 | endmodule 48 | 49 | 50 | 51 | module fake_ram( 52 | address, 53 | data, 54 | inclock, 55 | outclock, 56 | wren, 57 | q); 58 | 59 | input [3:0] address; 60 | input [7:0] data; 61 | input inclock; 62 | input outclock; 63 | input wren; 64 | output [7:0] q; 65 | 66 | wire [7:0] sub_wire0; 67 | wire [7:0] q = sub_wire0[7:0]; 68 | 69 | altsyncram altsyncram_component ( 70 | .wren_a (wren), 71 | .clock0 (inclock), 72 | //.clock1 (outclock), 73 | .address_a (address), 74 | .data_a (data), 75 | .q_a (sub_wire0), 76 | .aclr0 (1'b0), 77 | .aclr1 (1'b0), 78 | .address_b (1'b1), 79 | .addressstall_a (1'b0), 80 | .addressstall_b (1'b0), 81 | .byteena_a (1'b1), 82 | .byteena_b (1'b1), 83 | .clocken0 (1'b1), 84 | .clocken1 (1'b1), 85 | .clocken2 (1'b1), 86 | .clocken3 (1'b1), 87 | .data_b (1'b1), 88 | .eccstatus (), 89 | .q_b (), 90 | .rden_a (1'b1), 91 | .rden_b (1'b1), 92 | .wren_b (1'b0)); 93 | defparam 94 | altsyncram_component.clock_enable_input_a = "BYPASS", 95 | altsyncram_component.clock_enable_output_a = "BYPASS", 96 | altsyncram_component.init_file = "FAUXPAW.HEX", 97 | altsyncram_component.intended_device_family = "Cyclone II", 98 | altsyncram_component.lpm_type = "altsyncram", 99 | altsyncram_component.numwords_a = 16, 100 | altsyncram_component.operation_mode = "SINGLE_PORT", 101 | altsyncram_component.outdata_aclr_a = "NONE", 102 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 103 | altsyncram_component.power_up_uninitialized = "FALSE", 104 | altsyncram_component.ram_block_type = "M4K", 105 | altsyncram_component.widthad_a = 4, 106 | altsyncram_component.width_a = 8, 107 | altsyncram_component.width_byteena_a = 1; 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /workbench/floppy/wd-alone.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2007 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "7.1" 18 | DATE = "22:21:02 December 28, 2007" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "wd-alone" 24 | -------------------------------------------------------------------------------- /workbench/floppy/wd-alone.qsf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2007 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | # The default values for assignments are stored in the file 17 | # wd-alone_assignment_defaults.qdf 18 | # If this file doesn't exist, and for assignments not listed, see file 19 | # assignment_defaults.qdf 20 | 21 | # Altera recommends that you do not modify this file. This 22 | # file is updated automatically by the Quartus II software 23 | # and any changes you make may be lost or overwritten. 24 | 25 | 26 | set_global_assignment -name DEVICE EP2C20F484C7 27 | set_global_assignment -name FAMILY "Cyclone II" 28 | set_global_assignment -name TOP_LEVEL_ENTITY wdalone 29 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1 30 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:21:02 DECEMBER 28, 2007" 31 | set_global_assignment -name LAST_QUARTUS_VERSION 7.1 32 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA 33 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 34 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 35 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY "C:\\usr\\src\\vector06cc\\workbench\\floppy\\wdalone-reports" 36 | set_global_assignment -name VERILOG_FILE "src/wd-alone.v" 37 | set_global_assignment -name VERILOG_FILE ../../src/floppy/wd1793.v 38 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 39 | set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top 40 | set_global_assignment -name VECTOR_WAVEFORM_FILE "src/wd-alone.vwf" 41 | set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "src/wd-alone.vwf" -------------------------------------------------------------------------------- /workbench/floppy/wd-alone.qws: -------------------------------------------------------------------------------- 1 | [ProjectWorkspace] 2 | ptn_Child1=Frames 3 | [ProjectWorkspace.Frames] 4 | ptn_Child1=ChildFrames 5 | [ProjectWorkspace.Frames.ChildFrames] 6 | ptn_Child1=Document-0 7 | ptn_Child2=Document-1 8 | ptn_Child3=Document-2 9 | ptn_Child4=Document-3 10 | ptn_Child5=Document-4 11 | [ProjectWorkspace.Frames.ChildFrames.Document-1] 12 | ptn_Child1=ViewFrame-0 13 | [ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] 14 | DocPathName=../../src/floppy/wd1793.v 15 | DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde} 16 | IsChildFrameDetached=False 17 | IsActiveChildFrame=False 18 | ptn_Child1=StateMap 19 | [ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap] 20 | AFC_IN_REPORT=False 21 | --------------------------------------------------------------------------------