├── LICENSE ├── README.md ├── a5 └── scr1 │ ├── a5_scr1.qpf │ ├── a5_scr1.qsf │ ├── a5_scr1.sdc │ ├── a5_scr1.srf │ ├── a5_scr1.sv │ ├── ip │ ├── scbl.hex │ ├── scr1_arch_custom.svh │ └── uart │ │ ├── raminfr.v │ │ ├── timescale.v │ │ ├── uart_defines.v │ │ ├── uart_receiver.v │ │ ├── uart_regs.v │ │ ├── uart_rfifo.v │ │ ├── uart_sync_flops.v │ │ ├── uart_tfifo.v │ │ ├── uart_top.v │ │ ├── uart_transmitter.v │ │ └── uart_wb.v │ └── qsys │ └── a5_sopc.qsys ├── arty └── scr1 │ ├── .gitignore │ ├── README.md │ ├── arty_scr1.tcl │ ├── constrs │ ├── arty_scr1_physical.xdc │ ├── arty_scr1_synth.xdc │ └── arty_scr1_timing.xdc │ ├── mem_update.tcl │ ├── scbl.mem │ ├── src │ ├── arty_scr1.sv │ └── scr1_arch_custom.svh │ └── write_mmi.tcl ├── de10lite └── scr1 │ ├── de10lite_scr1.qpf │ ├── de10lite_scr1.qsf │ ├── de10lite_scr1.sdc │ ├── de10lite_scr1.srf │ ├── de10lite_scr1.sv │ ├── ip │ ├── ahb_avalon_bridge.sv │ ├── scbl.hex │ ├── scr1_arch_custom.svh │ └── uart │ │ ├── raminfr.v │ │ ├── timescale.v │ │ ├── uart_defines.v │ │ ├── uart_receiver.v │ │ ├── uart_regs.v │ │ ├── uart_rfifo.v │ │ ├── uart_sync_flops.v │ │ ├── uart_tfifo.v │ │ ├── uart_top.v │ │ ├── uart_transmitter.v │ │ └── uart_wb.v │ └── qsys │ └── de10lite_sopc.qsys └── nexys4ddr └── scr1 ├── README.md ├── constrs ├── nexys4ddr_scr1_physical.xdc ├── nexys4ddr_scr1_synth.xdc └── nexys4ddr_scr1_timing.xdc ├── mem_update.tcl ├── nexys4ddr_scr1.tcl ├── scbl.mem ├── src ├── nexys4ddr_scr1.sv └── scr1_arch_custom.svh └── write_mmi.tcl /LICENSE: -------------------------------------------------------------------------------- 1 | # Solderpad Hardware Licence Version 2.0 2 | 3 | This licence (the “Licence”) operates as a wraparound licence to the Apache License Version 2.0 (the “Apache License”) and grants to You the rights, and imposes the obligations, set out in the Apache License (which can be found here: http://apache.org/licenses/LICENSE-2.0), with the following extensions. It must be read in conjunction with the Apache License. Section 1 below modifies definitions in the Apache License, and section 2 below replaces sections 2 of the Apache License. You may, at your option, choose to treat any Work released under this License as released under the Apache License (thus ignoring all sections written below entirely). Words in italics indicate changes rom the Apache License, but are indicative and not to be taken into account in interpretation. 4 | 5 | 1. The definitions set out in the Apache License are modified as follows: 6 | 7 | Copyright any reference to ‘copyright’ (whether capitalised or not) includes ‘Rights’ (as defined below). 8 | 9 | Contribution also includes any design, as well as any work of authorship. 10 | 11 | Derivative Works shall not include works that remain reversibly separable from, or merely link (or bind by name) or physically connect to or interoperate with the interfaces of the Work and Derivative Works thereof. 12 | 13 | Object form shall mean any form resulting from mechanical transformation or translation of a Source form or the application of a Source form to physical material, including but not limited to compiled object code, generated documentation, the instantiation of a hardware design or physical object and conversions to other media types, including intermediate forms such as bytecodes, FPGA bitstreams, moulds, artwork and semiconductor topographies (mask works). 14 | 15 | Rights means copyright and any similar right including design right (whether registered or unregistered), semiconductor topography (mask) rights and database rights (but excluding Patents and Trademarks). 16 | 17 | Source form shall mean the preferred form for making modifications, including but not limited to source code, net lists, board layouts, CAD files, documentation source, and configuration files. 18 | 19 | Work also includes a design or work of authorship, whether in Source form or other Object form. 20 | 21 | 2. Grant of Licence 22 | 23 | 2.1 Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable license under the Rights to reproduce, prepare Derivative Works of, make, adapt, repair, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form and do anything in relation to the Work as if the Rights did not exist. 24 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SCRx SDK FPGA projects repository 2 | 3 | ## Repository contents 4 | Folder | Description 5 | ------ | ----------- 6 | a5 | Projects for Intel Arria V GX FPGA Starter Kit 7 | arty | Projects for Digilent's Arty board 8 | de10lite | Projects for Terasic's DE10-Lite board 9 | nexys4ddr | Projects for Digilent's Nexys4DDR board 10 | README.md | This file 11 | 12 | -------------------------------------------------------------------------------- /a5/scr1/a5_scr1.qpf: -------------------------------------------------------------------------------- 1 | 2 | QUARTUS_VERSION = "13.0" 3 | DATE = "18:09:23 July 01, 2016" 4 | 5 | # Revisions 6 | PROJECT_REVISION = "a5_scr1" 7 | -------------------------------------------------------------------------------- /a5/scr1/a5_scr1.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************** 2 | # Clocks 3 | #************************************************************** 4 | create_clock -name "OSC_50" -period 20 [get_ports {CLKIN_50_BOT}] 5 | create_clock -name "OSC_50_VIRT" -period 20 6 | create_clock -name "OSC_100" -period 10 [get_ports {CLKINTOP_100_P}] 7 | create_clock -name "OSC_100_VIRT" -period 10 8 | create_clock -name "JTAG_TCK" -period 100 [get_ports {JTAG_TCK }] 9 | create_clock -name "JTAG_TCK_VIRT" -period 100 10 | 11 | set_clock_groups -asynchronous -group {OSC_50 OSC_50_VIRT} \ 12 | -group {OSC_100 OSC_100_VIRT} \ 13 | -group {JTAG_TCK JTAG_TCK_VIRT} 14 | 15 | create_generated_clock -add -source CLKIN_50_BOT -divide_by 5 -multiply_by 3 -duty_cycle 50.00 -name "CPU_CLK" { i_soc|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } 16 | 17 | derive_pll_clocks -create_base_clocks 18 | derive_clock_uncertainty 19 | 20 | #************************************************************** 21 | # False Path 22 | #************************************************************** 23 | set_false_path -to [get_ports {USER_LED[*]}] 24 | set_false_path -to [get_ports {UART_TXD}] 25 | set_false_path -from [get_ports {UART_RXD}] 26 | set_false_path -from [get_ports {JTAG_TRST_N}] 27 | set_false_path -from [get_ports {JTAG_SRST_N}] 28 | set_false_path -from [get_ports {USER_PB[*]}] 29 | 30 | #************************************************************** 31 | # IO Delays 32 | #************************************************************** 33 | set_input_delay -add_delay -clock_fall -clock JTAG_TCK_VIRT -max 5 [get_ports {JTAG_TMS JTAG_TDI}] 34 | set_input_delay -add_delay -clock_fall -clock JTAG_TCK_VIRT -min 0 [get_ports {JTAG_TMS JTAG_TDI}] 35 | set_output_delay -add_delay -clock_fall -clock JTAG_TCK_VIRT -max 5 [get_ports {JTAG_TDO}] 36 | set_output_delay -add_delay -clock_fall -clock JTAG_TCK_VIRT -min 0 [get_ports {JTAG_TDO}] 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /a5/scr1/a5_scr1.srf: -------------------------------------------------------------------------------- 1 | { "" "" "" "Variable or input pin \"byteena_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} 2 | { "" "" "" "34 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} 3 | { "" "" "" "*" { } { } 0 12250 "" 0 0 "Quartus II" 0 -1 0 ""} 4 | { "" "" "" "*" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""} 5 | { "" "" "" "*" { } { } 0 12021 "" 0 0 "Quartus II" 0 -1 0 ""} 6 | { "" "" "" "*" { } { } 0 10281 "" 0 0 "Quartus II" 0 -1 0 ""} 7 | { "" "" "" "*" { } { } 0 12128 "" 0 0 "Quartus II" 0 -1 0 ""} 8 | { "" "" "" "*" { } { } 0 10264 "" 0 0 "Quartus II" 0 -1 0 ""} 9 | { "" "" "" "*" { } { } 0 12133 "" 0 0 "Quartus II" 0 -1 0 ""} 10 | { "" "" "" "*" { } { } 0 12130 "" 0 0 "Quartus II" 0 -1 0 ""} 11 | { "" "" "" "*" { } { } 0 10648 "" 0 0 "Quartus II" 0 -1 0 ""} 12 | { "" "" "" "*" { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} 13 | { "" "" "" "*" { } { } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""} 14 | { "" "" "" "*" { } { } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""} 15 | { "" "" "" "uart_regs.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 16 | { "" "" "" "uart_wb.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 17 | { "" "" "" "uart_receiver.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 18 | { "" "" "" "altera_mem_if_hard_memory_controller_top_arriav.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 19 | { "" "" "" "altera_axi_default_slave.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 20 | { "" "" "" "altera_merlin_burst_adapter.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 21 | { "" "" "" "a5_sopc_ddr3_emif_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 22 | { "" "" "" "a5_sopc_ddr3_emif_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 23 | { "" "" "" "altera_merlin_width_adapter.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 24 | { "" "" "" "altera_merlin_axi_slave_ni.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 25 | { "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 26 | { "" "" "" "altera_mem_if_sequencer_rst.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} 27 | -------------------------------------------------------------------------------- /a5/scr1/a5_scr1.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/syntacore/fpga-sdk-prj/66c9e52b48f8ca59cb986855651523ccd9c8b2c5/a5/scr1/a5_scr1.sv -------------------------------------------------------------------------------- /a5/scr1/ip/scr1_arch_custom.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_ARCH_CUSTOM_SVH 2 | `define SCR1_ARCH_CUSTOM_SVH 3 | /// Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 4 | /// @file 5 | /// @brief Custom Architecture Parameters File 6 | /// 7 | 8 | // Current FPGA build identificators, can be modified 9 | `define SCR1_PTFM_SOC_ID 32'h21051100 10 | `define SCR1_PTFM_BLD_ID 32'h22011204 11 | `define SCR1_PTFM_CORE_CLK_FREQ 32'd30000000 12 | 13 | //`define SCR1_TRGT_FPGA_XILINX // Uncomment if target platform is Xilinx FPGAs 14 | `define SCR1_TRGT_FPGA_INTEL // Uncomment if target platform is Intel FPGAs AND ---> 15 | //`define SCR1_TRGT_FPGA_INTEL_MAX10 // ---> Uncomment if target platform is Intel MAX 10 FPGAs 16 | `define SCR1_TRGT_FPGA_INTEL_ARRIAV // ---> Uncomment if target platform is Intel Arria V FPGAs 17 | 18 | // Uncomment to select recommended core architecture configurations 19 | // Default SCR1 FPGA SDK created for RV32IMC_MAX config 20 | 21 | `define SCR1_CFG_RV32IMC_MAX 22 | //`define SCR1_CFG_RV32IC_BASE 23 | //`define SCR1_CFG_RV32EC_MIN 24 | 25 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_RST_VECTOR = 'hFFFFFF00; // Reset vector 26 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_MTVEC_BASE = 'hFFFFFF80; // MTVEC BASE field reset value 27 | 28 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_MASK = 'hFFFF0000; // TCM mask and size 29 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_PATTERN = 'hF0000000; // TCM address match pattern 30 | 31 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_MASK = 'hFFFFFFE0; // Timer mask (should be 0xFFFFFFE0) 32 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_PATTERN = 'hF0040000; // Timer address match pattern 33 | 34 | 35 | 36 | `endif // SCR1_ARCH_CUSTOM_SVH 37 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/raminfr.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// raminfr.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// Inferrable Distributed RAM for FIFOs //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None . //// 22 | //// //// 23 | //// To Do: //// 24 | //// Nothing so far. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - gorban@opencores.org //// 28 | //// - Jacob Gorban //// 29 | //// //// 30 | //// Created: 2002/07/22 //// 31 | //// Last Updated: 2002/07/22 //// 32 | //// (See log for the revision history) //// 33 | //// //// 34 | //// //// 35 | ////////////////////////////////////////////////////////////////////// 36 | //// //// 37 | //// Copyright (C) 2000, 2001 Authors //// 38 | //// //// 39 | //// This source file may be used and distributed without //// 40 | //// restriction provided that this copyright statement is not //// 41 | //// removed from the file and that any derivative work contains //// 42 | //// the original copyright notice and the associated disclaimer. //// 43 | //// //// 44 | //// This source file is free software; you can redistribute it //// 45 | //// and/or modify it under the terms of the GNU Lesser General //// 46 | //// Public License as published by the Free Software Foundation; //// 47 | //// either version 2.1 of the License, or (at your option) any //// 48 | //// later version. //// 49 | //// //// 50 | //// This source is distributed in the hope that it will be //// 51 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 52 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 53 | //// PURPOSE. See the GNU Lesser General Public License for more //// 54 | //// details. //// 55 | //// //// 56 | //// You should have received a copy of the GNU Lesser General //// 57 | //// Public License along with this source; if not, download it //// 58 | //// from http://www.opencores.org/lgpl.shtml //// 59 | //// //// 60 | ////////////////////////////////////////////////////////////////////// 61 | // 62 | // CVS Revision History 63 | // 64 | // $Log: not supported by cvs2svn $ 65 | // Revision 1.1 2002/07/22 23:02:23 gorban 66 | // Bug Fixes: 67 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 68 | // Problem reported by Kenny.Tung. 69 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 70 | // 71 | // Improvements: 72 | // * Made FIFO's as general inferrable memory where possible. 73 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 74 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 75 | // 76 | // * Added optional baudrate output (baud_o). 77 | // This is identical to BAUDOUT* signal on 16550 chip. 78 | // It outputs 16xbit_clock_rate - the divided clock. 79 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 80 | // 81 | 82 | //Following is the Verilog code for a dual-port RAM with asynchronous read. 83 | module raminfr 84 | (clk, we, a, dpra, di, dpo); 85 | 86 | parameter addr_width = 4; 87 | parameter data_width = 8; 88 | parameter depth = 16; 89 | 90 | input clk; 91 | input we; 92 | input [addr_width-1:0] a; 93 | input [addr_width-1:0] dpra; 94 | input [data_width-1:0] di; 95 | //output [data_width-1:0] spo; 96 | output [data_width-1:0] dpo; 97 | reg [data_width-1:0] ram [depth-1:0]; 98 | 99 | wire [data_width-1:0] dpo; 100 | wire [data_width-1:0] di; 101 | wire [addr_width-1:0] a; 102 | wire [addr_width-1:0] dpra; 103 | 104 | always @(posedge clk) begin 105 | if (we) 106 | ram[a] <= di; 107 | end 108 | // assign spo = ram[a]; 109 | assign dpo = ram[dpra]; 110 | endmodule 111 | 112 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/timescale.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// timescale.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// Defines of the Core //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None //// 22 | //// //// 23 | //// To Do: //// 24 | //// Nothing. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - gorban@opencores.org //// 28 | //// - Jacob Gorban //// 29 | //// - Igor Mohor (igorm@opencores.org) //// 30 | //// //// 31 | //// Created: 2001/05/12 //// 32 | //// Last Updated: 2001/05/17 //// 33 | //// (See log for the revision history) //// 34 | //// //// 35 | //// //// 36 | ////////////////////////////////////////////////////////////////////// 37 | //// //// 38 | //// Copyright (C) 2000, 2001 Authors //// 39 | //// //// 40 | //// This source file may be used and distributed without //// 41 | //// restriction provided that this copyright statement is not //// 42 | //// removed from the file and that any derivative work contains //// 43 | //// the original copyright notice and the associated disclaimer. //// 44 | //// //// 45 | //// This source file is free software; you can redistribute it //// 46 | //// and/or modify it under the terms of the GNU Lesser General //// 47 | //// Public License as published by the Free Software Foundation; //// 48 | //// either version 2.1 of the License, or (at your option) any //// 49 | //// later version. //// 50 | //// //// 51 | //// This source is distributed in the hope that it will be //// 52 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 53 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 54 | //// PURPOSE. See the GNU Lesser General Public License for more //// 55 | //// details. //// 56 | //// //// 57 | //// You should have received a copy of the GNU Lesser General //// 58 | //// Public License along with this source; if not, download it //// 59 | //// from http://www.opencores.org/lgpl.shtml //// 60 | //// //// 61 | ////////////////////////////////////////////////////////////////////// 62 | // Timescale define 63 | 64 | `timescale 1ns/10ps 65 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/uart_defines.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_defines.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// Defines of the Core //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None //// 22 | //// //// 23 | //// To Do: //// 24 | //// Nothing. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - gorban@opencores.org //// 28 | //// - Jacob Gorban //// 29 | //// - Igor Mohor (igorm@opencores.org) //// 30 | //// //// 31 | //// Created: 2001/05/12 //// 32 | //// Last Updated: 2001/05/17 //// 33 | //// (See log for the revision history) //// 34 | //// //// 35 | //// //// 36 | ////////////////////////////////////////////////////////////////////// 37 | //// //// 38 | //// Copyright (C) 2000, 2001 Authors //// 39 | //// //// 40 | //// This source file may be used and distributed without //// 41 | //// restriction provided that this copyright statement is not //// 42 | //// removed from the file and that any derivative work contains //// 43 | //// the original copyright notice and the associated disclaimer. //// 44 | //// //// 45 | //// This source file is free software; you can redistribute it //// 46 | //// and/or modify it under the terms of the GNU Lesser General //// 47 | //// Public License as published by the Free Software Foundation; //// 48 | //// either version 2.1 of the License, or (at your option) any //// 49 | //// later version. //// 50 | //// //// 51 | //// This source is distributed in the hope that it will be //// 52 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 53 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 54 | //// PURPOSE. See the GNU Lesser General Public License for more //// 55 | //// details. //// 56 | //// //// 57 | //// You should have received a copy of the GNU Lesser General //// 58 | //// Public License along with this source; if not, download it //// 59 | //// from http://www.opencores.org/lgpl.shtml //// 60 | //// //// 61 | ////////////////////////////////////////////////////////////////////// 62 | // 63 | // CVS Revision History 64 | // 65 | // $Log: not supported by cvs2svn $ 66 | // Revision 1.13 2003/06/11 16:37:47 gorban 67 | // This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. 68 | // 69 | // Revision 1.12 2002/07/22 23:02:23 gorban 70 | // Bug Fixes: 71 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 72 | // Problem reported by Kenny.Tung. 73 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 74 | // 75 | // Improvements: 76 | // * Made FIFO's as general inferrable memory where possible. 77 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 78 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 79 | // 80 | // * Added optional baudrate output (baud_o). 81 | // This is identical to BAUDOUT* signal on 16550 chip. 82 | // It outputs 16xbit_clock_rate - the divided clock. 83 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 84 | // 85 | // Revision 1.10 2001/12/11 08:55:40 mohor 86 | // Scratch register define added. 87 | // 88 | // Revision 1.9 2001/12/03 21:44:29 gorban 89 | // Updated specification documentation. 90 | // Added full 32-bit data bus interface, now as default. 91 | // Address is 5-bit wide in 32-bit data bus mode. 92 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. 93 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. 94 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. 95 | // My small test bench is modified to work with 32-bit mode. 96 | // 97 | // Revision 1.8 2001/11/26 21:38:54 gorban 98 | // Lots of fixes: 99 | // Break condition wasn't handled correctly at all. 100 | // LSR bits could lose their values. 101 | // LSR value after reset was wrong. 102 | // Timing of THRE interrupt signal corrected. 103 | // LSR bit 0 timing corrected. 104 | // 105 | // Revision 1.7 2001/08/24 21:01:12 mohor 106 | // Things connected to parity changed. 107 | // Clock devider changed. 108 | // 109 | // Revision 1.6 2001/08/23 16:05:05 mohor 110 | // Stop bit bug fixed. 111 | // Parity bug fixed. 112 | // WISHBONE read cycle bug fixed, 113 | // OE indicator (Overrun Error) bug fixed. 114 | // PE indicator (Parity Error) bug fixed. 115 | // Register read bug fixed. 116 | // 117 | // Revision 1.5 2001/05/31 20:08:01 gorban 118 | // FIFO changes and other corrections. 119 | // 120 | // Revision 1.4 2001/05/21 19:12:02 gorban 121 | // Corrected some Linter messages. 122 | // 123 | // Revision 1.3 2001/05/17 18:34:18 gorban 124 | // First 'stable' release. Should be sythesizable now. Also added new header. 125 | // 126 | // Revision 1.0 2001-05-17 21:27:11+02 jacob 127 | // Initial revision 128 | // 129 | // 130 | 131 | // remove comments to restore to use the new version with 8 data bit interface 132 | // in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place 133 | // also, in 8-bit version there'll be no debugging features included 134 | // CAUTION: doesn't work with current version of OR1200 135 | `define DATA_BUS_WIDTH_8 136 | 137 | `ifdef DATA_BUS_WIDTH_8 138 | `define UART_ADDR_WIDTH 3 139 | `define UART_DATA_WIDTH 8 140 | `else 141 | `define UART_ADDR_WIDTH 5 142 | `define UART_DATA_WIDTH 32 143 | `endif 144 | 145 | // Uncomment this if you want your UART to have 146 | // 16xBaudrate output port. 147 | // If defined, the enable signal will be used to drive baudrate_o signal 148 | // It's frequency is 16xbaudrate 149 | 150 | // `define UART_HAS_BAUDRATE_OUTPUT 151 | 152 | // Register addresses 153 | `define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer 154 | `define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter 155 | `define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable 156 | `define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification 157 | `define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control 158 | `define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control 159 | `define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control 160 | `define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status 161 | `define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status 162 | `define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register 163 | `define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2) 164 | `define UART_REG_DL2 `UART_ADDR_WIDTH'd1 165 | 166 | // Interrupt Enable register bits 167 | `define UART_IE_RDA 0 // Received Data available interrupt 168 | `define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt 169 | `define UART_IE_RLS 2 // Receiver Line Status Interrupt 170 | `define UART_IE_MS 3 // Modem Status Interrupt 171 | 172 | // Interrupt Identification register bits 173 | `define UART_II_IP 0 // Interrupt pending when 0 174 | `define UART_II_II 3:1 // Interrupt identification 175 | 176 | // Interrupt identification values for bits 3:1 177 | `define UART_II_RLS 3'b011 // Receiver Line Status 178 | `define UART_II_RDA 3'b010 // Receiver Data available 179 | `define UART_II_TI 3'b110 // Timeout Indication 180 | `define UART_II_THRE 3'b001 // Transmitter Holding Register empty 181 | `define UART_II_MS 3'b000 // Modem Status 182 | 183 | // FIFO Control Register bits 184 | `define UART_FC_TL 1:0 // Trigger level 185 | 186 | // FIFO trigger level values 187 | `define UART_FC_1 2'b00 188 | `define UART_FC_4 2'b01 189 | `define UART_FC_8 2'b10 190 | `define UART_FC_14 2'b11 191 | 192 | // Line Control register bits 193 | `define UART_LC_BITS 1:0 // bits in character 194 | `define UART_LC_SB 2 // stop bits 195 | `define UART_LC_PE 3 // parity enable 196 | `define UART_LC_EP 4 // even parity 197 | `define UART_LC_SP 5 // stick parity 198 | `define UART_LC_BC 6 // Break control 199 | `define UART_LC_DL 7 // Divisor Latch access bit 200 | 201 | // Modem Control register bits 202 | `define UART_MC_DTR 0 203 | `define UART_MC_RTS 1 204 | `define UART_MC_OUT1 2 205 | `define UART_MC_OUT2 3 206 | `define UART_MC_LB 4 // Loopback mode 207 | 208 | // Line Status Register bits 209 | `define UART_LS_DR 0 // Data ready 210 | `define UART_LS_OE 1 // Overrun Error 211 | `define UART_LS_PE 2 // Parity Error 212 | `define UART_LS_FE 3 // Framing Error 213 | `define UART_LS_BI 4 // Break interrupt 214 | `define UART_LS_TFE 5 // Transmit FIFO is empty 215 | `define UART_LS_TE 6 // Transmitter Empty indicator 216 | `define UART_LS_EI 7 // Error indicator 217 | 218 | // Modem Status Register bits 219 | `define UART_MS_DCTS 0 // Delta signals 220 | `define UART_MS_DDSR 1 221 | `define UART_MS_TERI 2 222 | `define UART_MS_DDCD 3 223 | `define UART_MS_CCTS 4 // Complement signals 224 | `define UART_MS_CDSR 5 225 | `define UART_MS_CRI 6 226 | `define UART_MS_CDCD 7 227 | 228 | // FIFO parameter defines 229 | 230 | `define UART_FIFO_WIDTH 8 231 | `define UART_FIFO_DEPTH 16 232 | `define UART_FIFO_POINTER_W 4 233 | `define UART_FIFO_COUNTER_W 5 234 | // receiver fifo has width 11 because it has break, parity and framing error bits 235 | `define UART_FIFO_REC_WIDTH 11 236 | 237 | 238 | `define VERBOSE_WB 0 // All activity on the WISHBONE is recorded 239 | `define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register) 240 | `define FAST_TEST 1 // 64/1024 packets are sent 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/uart_rfifo.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_rfifo.v (Modified from uart_fifo.v) //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core receiver FIFO //// 19 | //// //// 20 | //// To Do: //// 21 | //// Nothing. //// 22 | //// //// 23 | //// Author(s): //// 24 | //// - gorban@opencores.org //// 25 | //// - Jacob Gorban //// 26 | //// - Igor Mohor (igorm@opencores.org) //// 27 | //// //// 28 | //// Created: 2001/05/12 //// 29 | //// Last Updated: 2002/07/22 //// 30 | //// (See log for the revision history) //// 31 | //// //// 32 | //// //// 33 | ////////////////////////////////////////////////////////////////////// 34 | //// //// 35 | //// Copyright (C) 2000, 2001 Authors //// 36 | //// //// 37 | //// This source file may be used and distributed without //// 38 | //// restriction provided that this copyright statement is not //// 39 | //// removed from the file and that any derivative work contains //// 40 | //// the original copyright notice and the associated disclaimer. //// 41 | //// //// 42 | //// This source file is free software; you can redistribute it //// 43 | //// and/or modify it under the terms of the GNU Lesser General //// 44 | //// Public License as published by the Free Software Foundation; //// 45 | //// either version 2.1 of the License, or (at your option) any //// 46 | //// later version. //// 47 | //// //// 48 | //// This source is distributed in the hope that it will be //// 49 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 50 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 51 | //// PURPOSE. See the GNU Lesser General Public License for more //// 52 | //// details. //// 53 | //// //// 54 | //// You should have received a copy of the GNU Lesser General //// 55 | //// Public License along with this source; if not, download it //// 56 | //// from http://www.opencores.org/lgpl.shtml //// 57 | //// //// 58 | ////////////////////////////////////////////////////////////////////// 59 | // 60 | // CVS Revision History 61 | // 62 | // $Log: not supported by cvs2svn $ 63 | // Revision 1.3 2003/06/11 16:37:47 gorban 64 | // This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. 65 | // 66 | // Revision 1.2 2002/07/29 21:16:18 gorban 67 | // The uart_defines.v file is included again in sources. 68 | // 69 | // Revision 1.1 2002/07/22 23:02:23 gorban 70 | // Bug Fixes: 71 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 72 | // Problem reported by Kenny.Tung. 73 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 74 | // 75 | // Improvements: 76 | // * Made FIFO's as general inferrable memory where possible. 77 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 78 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 79 | // 80 | // * Added optional baudrate output (baud_o). 81 | // This is identical to BAUDOUT* signal on 16550 chip. 82 | // It outputs 16xbit_clock_rate - the divided clock. 83 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 84 | // 85 | // Revision 1.16 2001/12/20 13:25:46 mohor 86 | // rx push changed to be only one cycle wide. 87 | // 88 | // Revision 1.15 2001/12/18 09:01:07 mohor 89 | // Bug that was entered in the last update fixed (rx state machine). 90 | // 91 | // Revision 1.14 2001/12/17 14:46:48 mohor 92 | // overrun signal was moved to separate block because many sequential lsr 93 | // reads were preventing data from being written to rx fifo. 94 | // underrun signal was not used and was removed from the project. 95 | // 96 | // Revision 1.13 2001/11/26 21:38:54 gorban 97 | // Lots of fixes: 98 | // Break condition wasn't handled correctly at all. 99 | // LSR bits could lose their values. 100 | // LSR value after reset was wrong. 101 | // Timing of THRE interrupt signal corrected. 102 | // LSR bit 0 timing corrected. 103 | // 104 | // Revision 1.12 2001/11/08 14:54:23 mohor 105 | // Comments in Slovene language deleted, few small fixes for better work of 106 | // old tools. IRQs need to be fix. 107 | // 108 | // Revision 1.11 2001/11/07 17:51:52 gorban 109 | // Heavily rewritten interrupt and LSR subsystems. 110 | // Many bugs hopefully squashed. 111 | // 112 | // Revision 1.10 2001/10/20 09:58:40 gorban 113 | // Small synopsis fixes 114 | // 115 | // Revision 1.9 2001/08/24 21:01:12 mohor 116 | // Things connected to parity changed. 117 | // Clock devider changed. 118 | // 119 | // Revision 1.8 2001/08/24 08:48:10 mohor 120 | // FIFO was not cleared after the data was read bug fixed. 121 | // 122 | // Revision 1.7 2001/08/23 16:05:05 mohor 123 | // Stop bit bug fixed. 124 | // Parity bug fixed. 125 | // WISHBONE read cycle bug fixed, 126 | // OE indicator (Overrun Error) bug fixed. 127 | // PE indicator (Parity Error) bug fixed. 128 | // Register read bug fixed. 129 | // 130 | // Revision 1.3 2001/05/31 20:08:01 gorban 131 | // FIFO changes and other corrections. 132 | // 133 | // Revision 1.3 2001/05/27 17:37:48 gorban 134 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. 135 | // 136 | // Revision 1.2 2001/05/17 18:34:18 gorban 137 | // First 'stable' release. Should be sythesizable now. Also added new header. 138 | // 139 | // Revision 1.0 2001-05-17 21:27:12+02 jacob 140 | // Initial revision 141 | // 142 | // 143 | 144 | // synopsys translate_off 145 | `include "timescale.v" 146 | // synopsys translate_on 147 | 148 | `include "uart_defines.v" 149 | 150 | module uart_rfifo (clk, 151 | wb_rst_i, data_in, data_out, 152 | // Control signals 153 | push, // push strobe, active high 154 | pop, // pop strobe, active high 155 | // status signals 156 | overrun, 157 | count, 158 | error_bit, 159 | fifo_reset, 160 | reset_status 161 | ); 162 | 163 | 164 | // FIFO parameters 165 | parameter fifo_width = `UART_FIFO_WIDTH; 166 | parameter fifo_depth = `UART_FIFO_DEPTH; 167 | parameter fifo_pointer_w = `UART_FIFO_POINTER_W; 168 | parameter fifo_counter_w = `UART_FIFO_COUNTER_W; 169 | 170 | input clk; 171 | input wb_rst_i; 172 | input push; 173 | input pop; 174 | input [fifo_width-1:0] data_in; 175 | input fifo_reset; 176 | input reset_status; 177 | 178 | output [fifo_width-1:0] data_out; 179 | output overrun; 180 | output [fifo_counter_w-1:0] count; 181 | output error_bit; 182 | 183 | wire [fifo_width-1:0] data_out; 184 | wire [7:0] data8_out; 185 | // flags FIFO 186 | reg [2:0] fifo[fifo_depth-1:0]; 187 | 188 | // FIFO pointers 189 | reg [fifo_pointer_w-1:0] top; 190 | reg [fifo_pointer_w-1:0] bottom; 191 | 192 | reg [fifo_counter_w-1:0] count; 193 | reg overrun; 194 | 195 | wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; 196 | 197 | raminfr #(fifo_pointer_w,8,fifo_depth) rfifo 198 | (.clk(clk), 199 | .we(push), 200 | .a(top), 201 | .dpra(bottom), 202 | .di(data_in[fifo_width-1:fifo_width-8]), 203 | .dpo(data8_out) 204 | ); 205 | 206 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 207 | begin 208 | if (wb_rst_i) 209 | begin 210 | top <= #1 0; 211 | bottom <= #1 1'b0; 212 | count <= #1 0; 213 | fifo[0] <= #1 0; 214 | fifo[1] <= #1 0; 215 | fifo[2] <= #1 0; 216 | fifo[3] <= #1 0; 217 | fifo[4] <= #1 0; 218 | fifo[5] <= #1 0; 219 | fifo[6] <= #1 0; 220 | fifo[7] <= #1 0; 221 | fifo[8] <= #1 0; 222 | fifo[9] <= #1 0; 223 | fifo[10] <= #1 0; 224 | fifo[11] <= #1 0; 225 | fifo[12] <= #1 0; 226 | fifo[13] <= #1 0; 227 | fifo[14] <= #1 0; 228 | fifo[15] <= #1 0; 229 | end 230 | else 231 | if (fifo_reset) begin 232 | top <= #1 0; 233 | bottom <= #1 1'b0; 234 | count <= #1 0; 235 | fifo[0] <= #1 0; 236 | fifo[1] <= #1 0; 237 | fifo[2] <= #1 0; 238 | fifo[3] <= #1 0; 239 | fifo[4] <= #1 0; 240 | fifo[5] <= #1 0; 241 | fifo[6] <= #1 0; 242 | fifo[7] <= #1 0; 243 | fifo[8] <= #1 0; 244 | fifo[9] <= #1 0; 245 | fifo[10] <= #1 0; 246 | fifo[11] <= #1 0; 247 | fifo[12] <= #1 0; 248 | fifo[13] <= #1 0; 249 | fifo[14] <= #1 0; 250 | fifo[15] <= #1 0; 251 | end 252 | else 253 | begin 254 | case ({push, pop}) 255 | 2'b10 : if (count0) 262 | begin 263 | fifo[bottom] <= #1 0; 264 | bottom <= #1 bottom + 1'b1; 265 | count <= #1 count - 1'b1; 266 | end 267 | 2'b11 : begin 268 | bottom <= #1 bottom + 1'b1; 269 | top <= #1 top_plus_1; 270 | fifo[top] <= #1 data_in[2:0]; 271 | end 272 | default: ; 273 | endcase 274 | end 275 | end // always 276 | 277 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 278 | begin 279 | if (wb_rst_i) 280 | overrun <= #1 1'b0; 281 | else 282 | if(fifo_reset | reset_status) 283 | overrun <= #1 1'b0; 284 | else 285 | if(push & ~pop & (count==fifo_depth)) 286 | overrun <= #1 1'b1; 287 | end // always 288 | 289 | 290 | // please note though that data_out is only valid one clock after pop signal 291 | assign data_out = {data8_out,fifo[bottom]}; 292 | 293 | // Additional logic for detection of error conditions (parity and framing) inside the FIFO 294 | // for the Line Status Register bit 7 295 | 296 | wire [2:0] word0 = fifo[0]; 297 | wire [2:0] word1 = fifo[1]; 298 | wire [2:0] word2 = fifo[2]; 299 | wire [2:0] word3 = fifo[3]; 300 | wire [2:0] word4 = fifo[4]; 301 | wire [2:0] word5 = fifo[5]; 302 | wire [2:0] word6 = fifo[6]; 303 | wire [2:0] word7 = fifo[7]; 304 | 305 | wire [2:0] word8 = fifo[8]; 306 | wire [2:0] word9 = fifo[9]; 307 | wire [2:0] word10 = fifo[10]; 308 | wire [2:0] word11 = fifo[11]; 309 | wire [2:0] word12 = fifo[12]; 310 | wire [2:0] word13 = fifo[13]; 311 | wire [2:0] word14 = fifo[14]; 312 | wire [2:0] word15 = fifo[15]; 313 | 314 | // a 1 is returned if any of the error bits in the fifo is 1 315 | assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | 316 | word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | 317 | word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | 318 | word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); 319 | 320 | endmodule 321 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/uart_sync_flops.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_sync_flops.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core receiver logic //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None known //// 22 | //// //// 23 | //// To Do: //// 24 | //// Thourough testing. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - Andrej Erzen (andreje@flextronics.si) //// 28 | //// - Tadej Markovic (tadejm@flextronics.si) //// 29 | //// //// 30 | //// Created: 2004/05/20 //// 31 | //// Last Updated: 2004/05/20 //// 32 | //// (See log for the revision history) //// 33 | //// //// 34 | //// //// 35 | ////////////////////////////////////////////////////////////////////// 36 | //// //// 37 | //// Copyright (C) 2000, 2001 Authors //// 38 | //// //// 39 | //// This source file may be used and distributed without //// 40 | //// restriction provided that this copyright statement is not //// 41 | //// removed from the file and that any derivative work contains //// 42 | //// the original copyright notice and the associated disclaimer. //// 43 | //// //// 44 | //// This source file is free software; you can redistribute it //// 45 | //// and/or modify it under the terms of the GNU Lesser General //// 46 | //// Public License as published by the Free Software Foundation; //// 47 | //// either version 2.1 of the License, or (at your option) any //// 48 | //// later version. //// 49 | //// //// 50 | //// This source is distributed in the hope that it will be //// 51 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 52 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 53 | //// PURPOSE. See the GNU Lesser General Public License for more //// 54 | //// details. //// 55 | //// //// 56 | //// You should have received a copy of the GNU Lesser General //// 57 | //// Public License along with this source; if not, download it //// 58 | //// from http://www.opencores.org/lgpl.shtml //// 59 | //// //// 60 | ////////////////////////////////////////////////////////////////////// 61 | // 62 | // CVS Revision History 63 | // 64 | // $Log: not supported by cvs2svn $ 65 | // 66 | 67 | 68 | `include "timescale.v" 69 | 70 | 71 | module uart_sync_flops 72 | ( 73 | // internal signals 74 | rst_i, 75 | clk_i, 76 | stage1_rst_i, 77 | stage1_clk_en_i, 78 | async_dat_i, 79 | sync_dat_o 80 | ); 81 | 82 | parameter Tp = 1; 83 | parameter width = 1; 84 | parameter init_value = 1'b0; 85 | 86 | input rst_i; // reset input 87 | input clk_i; // clock input 88 | input stage1_rst_i; // synchronous reset for stage 1 FF 89 | input stage1_clk_en_i; // synchronous clock enable for stage 1 FF 90 | input [width-1:0] async_dat_i; // asynchronous data input 91 | output [width-1:0] sync_dat_o; // synchronous data output 92 | 93 | 94 | // 95 | // Interal signal declarations 96 | // 97 | 98 | reg [width-1:0] sync_dat_o; 99 | reg [width-1:0] flop_0; 100 | 101 | 102 | // first stage 103 | always @ (posedge clk_i or posedge rst_i) 104 | begin 105 | if (rst_i) 106 | flop_0 <= #Tp {width{init_value}}; 107 | else 108 | flop_0 <= #Tp async_dat_i; 109 | end 110 | 111 | // second stage 112 | always @ (posedge clk_i or posedge rst_i) 113 | begin 114 | if (rst_i) 115 | sync_dat_o <= #Tp {width{init_value}}; 116 | else if (stage1_rst_i) 117 | sync_dat_o <= #Tp {width{init_value}}; 118 | else if (stage1_clk_en_i) 119 | sync_dat_o <= #Tp flop_0; 120 | end 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/uart_tfifo.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_tfifo.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core transmitter FIFO //// 19 | //// //// 20 | //// To Do: //// 21 | //// Nothing. //// 22 | //// //// 23 | //// Author(s): //// 24 | //// - gorban@opencores.org //// 25 | //// - Jacob Gorban //// 26 | //// - Igor Mohor (igorm@opencores.org) //// 27 | //// //// 28 | //// Created: 2001/05/12 //// 29 | //// Last Updated: 2002/07/22 //// 30 | //// (See log for the revision history) //// 31 | //// //// 32 | //// //// 33 | ////////////////////////////////////////////////////////////////////// 34 | //// //// 35 | //// Copyright (C) 2000, 2001 Authors //// 36 | //// //// 37 | //// This source file may be used and distributed without //// 38 | //// restriction provided that this copyright statement is not //// 39 | //// removed from the file and that any derivative work contains //// 40 | //// the original copyright notice and the associated disclaimer. //// 41 | //// //// 42 | //// This source file is free software; you can redistribute it //// 43 | //// and/or modify it under the terms of the GNU Lesser General //// 44 | //// Public License as published by the Free Software Foundation; //// 45 | //// either version 2.1 of the License, or (at your option) any //// 46 | //// later version. //// 47 | //// //// 48 | //// This source is distributed in the hope that it will be //// 49 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 50 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 51 | //// PURPOSE. See the GNU Lesser General Public License for more //// 52 | //// details. //// 53 | //// //// 54 | //// You should have received a copy of the GNU Lesser General //// 55 | //// Public License along with this source; if not, download it //// 56 | //// from http://www.opencores.org/lgpl.shtml //// 57 | //// //// 58 | ////////////////////////////////////////////////////////////////////// 59 | // 60 | // CVS Revision History 61 | // 62 | // $Log: not supported by cvs2svn $ 63 | // Revision 1.1 2002/07/22 23:02:23 gorban 64 | // Bug Fixes: 65 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 66 | // Problem reported by Kenny.Tung. 67 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 68 | // 69 | // Improvements: 70 | // * Made FIFO's as general inferrable memory where possible. 71 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 72 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 73 | // 74 | // * Added optional baudrate output (baud_o). 75 | // This is identical to BAUDOUT* signal on 16550 chip. 76 | // It outputs 16xbit_clock_rate - the divided clock. 77 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 78 | // 79 | // Revision 1.16 2001/12/20 13:25:46 mohor 80 | // rx push changed to be only one cycle wide. 81 | // 82 | // Revision 1.15 2001/12/18 09:01:07 mohor 83 | // Bug that was entered in the last update fixed (rx state machine). 84 | // 85 | // Revision 1.14 2001/12/17 14:46:48 mohor 86 | // overrun signal was moved to separate block because many sequential lsr 87 | // reads were preventing data from being written to rx fifo. 88 | // underrun signal was not used and was removed from the project. 89 | // 90 | // Revision 1.13 2001/11/26 21:38:54 gorban 91 | // Lots of fixes: 92 | // Break condition wasn't handled correctly at all. 93 | // LSR bits could lose their values. 94 | // LSR value after reset was wrong. 95 | // Timing of THRE interrupt signal corrected. 96 | // LSR bit 0 timing corrected. 97 | // 98 | // Revision 1.12 2001/11/08 14:54:23 mohor 99 | // Comments in Slovene language deleted, few small fixes for better work of 100 | // old tools. IRQs need to be fix. 101 | // 102 | // Revision 1.11 2001/11/07 17:51:52 gorban 103 | // Heavily rewritten interrupt and LSR subsystems. 104 | // Many bugs hopefully squashed. 105 | // 106 | // Revision 1.10 2001/10/20 09:58:40 gorban 107 | // Small synopsis fixes 108 | // 109 | // Revision 1.9 2001/08/24 21:01:12 mohor 110 | // Things connected to parity changed. 111 | // Clock devider changed. 112 | // 113 | // Revision 1.8 2001/08/24 08:48:10 mohor 114 | // FIFO was not cleared after the data was read bug fixed. 115 | // 116 | // Revision 1.7 2001/08/23 16:05:05 mohor 117 | // Stop bit bug fixed. 118 | // Parity bug fixed. 119 | // WISHBONE read cycle bug fixed, 120 | // OE indicator (Overrun Error) bug fixed. 121 | // PE indicator (Parity Error) bug fixed. 122 | // Register read bug fixed. 123 | // 124 | // Revision 1.3 2001/05/31 20:08:01 gorban 125 | // FIFO changes and other corrections. 126 | // 127 | // Revision 1.3 2001/05/27 17:37:48 gorban 128 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. 129 | // 130 | // Revision 1.2 2001/05/17 18:34:18 gorban 131 | // First 'stable' release. Should be sythesizable now. Also added new header. 132 | // 133 | // Revision 1.0 2001-05-17 21:27:12+02 jacob 134 | // Initial revision 135 | // 136 | // 137 | 138 | // synopsys translate_off 139 | `include "timescale.v" 140 | // synopsys translate_on 141 | 142 | `include "uart_defines.v" 143 | 144 | module uart_tfifo (clk, 145 | wb_rst_i, data_in, data_out, 146 | // Control signals 147 | push, // push strobe, active high 148 | pop, // pop strobe, active high 149 | // status signals 150 | overrun, 151 | count, 152 | fifo_reset, 153 | reset_status 154 | ); 155 | 156 | 157 | // FIFO parameters 158 | parameter fifo_width = `UART_FIFO_WIDTH; 159 | parameter fifo_depth = `UART_FIFO_DEPTH; 160 | parameter fifo_pointer_w = `UART_FIFO_POINTER_W; 161 | parameter fifo_counter_w = `UART_FIFO_COUNTER_W; 162 | 163 | input clk; 164 | input wb_rst_i; 165 | input push; 166 | input pop; 167 | input [fifo_width-1:0] data_in; 168 | input fifo_reset; 169 | input reset_status; 170 | 171 | output [fifo_width-1:0] data_out; 172 | output overrun; 173 | output [fifo_counter_w-1:0] count; 174 | 175 | wire [fifo_width-1:0] data_out; 176 | 177 | // FIFO pointers 178 | reg [fifo_pointer_w-1:0] top; 179 | reg [fifo_pointer_w-1:0] bottom; 180 | 181 | reg [fifo_counter_w-1:0] count; 182 | reg overrun; 183 | wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; 184 | 185 | raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo 186 | (.clk(clk), 187 | .we(push), 188 | .a(top), 189 | .dpra(bottom), 190 | .di(data_in), 191 | .dpo(data_out) 192 | ); 193 | 194 | 195 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 196 | begin 197 | if (wb_rst_i) 198 | begin 199 | top <= #1 0; 200 | bottom <= #1 1'b0; 201 | count <= #1 0; 202 | end 203 | else 204 | if (fifo_reset) begin 205 | top <= #1 0; 206 | bottom <= #1 1'b0; 207 | count <= #1 0; 208 | end 209 | else 210 | begin 211 | case ({push, pop}) 212 | 2'b10 : if (count0) 218 | begin 219 | bottom <= #1 bottom + 1'b1; 220 | count <= #1 count - 1'b1; 221 | end 222 | 2'b11 : begin 223 | bottom <= #1 bottom + 1'b1; 224 | top <= #1 top_plus_1; 225 | end 226 | default: ; 227 | endcase 228 | end 229 | end // always 230 | 231 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 232 | begin 233 | if (wb_rst_i) 234 | overrun <= #1 1'b0; 235 | else 236 | if(fifo_reset | reset_status) 237 | overrun <= #1 1'b0; 238 | else 239 | if(push & (count==fifo_depth)) 240 | overrun <= #1 1'b1; 241 | end // always 242 | 243 | endmodule 244 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/uart_top.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_top.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core top level. //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// Note that transmitter and receiver instances are inside //// 22 | //// the uart_regs.v file. //// 23 | //// //// 24 | //// To Do: //// 25 | //// Nothing so far. //// 26 | //// //// 27 | //// Author(s): //// 28 | //// - gorban@opencores.org //// 29 | //// - Jacob Gorban //// 30 | //// - Igor Mohor (igorm@opencores.org) //// 31 | //// //// 32 | //// Created: 2001/05/12 //// 33 | //// Last Updated: 2001/05/17 //// 34 | //// (See log for the revision history) //// 35 | //// //// 36 | //// //// 37 | ////////////////////////////////////////////////////////////////////// 38 | //// //// 39 | //// Copyright (C) 2000, 2001 Authors //// 40 | //// //// 41 | //// This source file may be used and distributed without //// 42 | //// restriction provided that this copyright statement is not //// 43 | //// removed from the file and that any derivative work contains //// 44 | //// the original copyright notice and the associated disclaimer. //// 45 | //// //// 46 | //// This source file is free software; you can redistribute it //// 47 | //// and/or modify it under the terms of the GNU Lesser General //// 48 | //// Public License as published by the Free Software Foundation; //// 49 | //// either version 2.1 of the License, or (at your option) any //// 50 | //// later version. //// 51 | //// //// 52 | //// This source is distributed in the hope that it will be //// 53 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 54 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 55 | //// PURPOSE. See the GNU Lesser General Public License for more //// 56 | //// details. //// 57 | //// //// 58 | //// You should have received a copy of the GNU Lesser General //// 59 | //// Public License along with this source; if not, download it //// 60 | //// from http://www.opencores.org/lgpl.shtml //// 61 | //// //// 62 | ////////////////////////////////////////////////////////////////////// 63 | // 64 | // CVS Revision History 65 | // 66 | // $Log: not supported by cvs2svn $ 67 | // Revision 1.18 2002/07/22 23:02:23 gorban 68 | // Bug Fixes: 69 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 70 | // Problem reported by Kenny.Tung. 71 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 72 | // 73 | // Improvements: 74 | // * Made FIFO's as general inferrable memory where possible. 75 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 76 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 77 | // 78 | // * Added optional baudrate output (baud_o). 79 | // This is identical to BAUDOUT* signal on 16550 chip. 80 | // It outputs 16xbit_clock_rate - the divided clock. 81 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 82 | // 83 | // Revision 1.17 2001/12/19 08:40:03 mohor 84 | // Warnings fixed (unused signals removed). 85 | // 86 | // Revision 1.16 2001/12/06 14:51:04 gorban 87 | // Bug in LSR[0] is fixed. 88 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. 89 | // 90 | // Revision 1.15 2001/12/03 21:44:29 gorban 91 | // Updated specification documentation. 92 | // Added full 32-bit data bus interface, now as default. 93 | // Address is 5-bit wide in 32-bit data bus mode. 94 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. 95 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. 96 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. 97 | // My small test bench is modified to work with 32-bit mode. 98 | // 99 | // Revision 1.14 2001/11/07 17:51:52 gorban 100 | // Heavily rewritten interrupt and LSR subsystems. 101 | // Many bugs hopefully squashed. 102 | // 103 | // Revision 1.13 2001/10/20 09:58:40 gorban 104 | // Small synopsis fixes 105 | // 106 | // Revision 1.12 2001/08/25 15:46:19 gorban 107 | // Modified port names again 108 | // 109 | // Revision 1.11 2001/08/24 21:01:12 mohor 110 | // Things connected to parity changed. 111 | // Clock devider changed. 112 | // 113 | // Revision 1.10 2001/08/23 16:05:05 mohor 114 | // Stop bit bug fixed. 115 | // Parity bug fixed. 116 | // WISHBONE read cycle bug fixed, 117 | // OE indicator (Overrun Error) bug fixed. 118 | // PE indicator (Parity Error) bug fixed. 119 | // Register read bug fixed. 120 | // 121 | // Revision 1.4 2001/05/31 20:08:01 gorban 122 | // FIFO changes and other corrections. 123 | // 124 | // Revision 1.3 2001/05/21 19:12:02 gorban 125 | // Corrected some Linter messages. 126 | // 127 | // Revision 1.2 2001/05/17 18:34:18 gorban 128 | // First 'stable' release. Should be sythesizable now. Also added new header. 129 | // 130 | // Revision 1.0 2001-05-17 21:27:12+02 jacob 131 | // Initial revision 132 | // 133 | // 134 | // synopsys translate_off 135 | `include "timescale.v" 136 | // synopsys translate_on 137 | 138 | `include "uart_defines.v" 139 | 140 | module uart_top ( 141 | wb_clk_i, 142 | 143 | // Wishbone signals 144 | wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, 145 | int_o, // interrupt request 146 | 147 | // UART signals 148 | // serial input/output 149 | stx_pad_o, srx_pad_i, 150 | 151 | // modem signals 152 | rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i 153 | `ifdef UART_HAS_BAUDRATE_OUTPUT 154 | , baud_o 155 | `endif 156 | ); 157 | 158 | parameter uart_data_width = `UART_DATA_WIDTH; 159 | parameter uart_addr_width = `UART_ADDR_WIDTH; 160 | 161 | input wb_clk_i; 162 | 163 | // WISHBONE interface 164 | input wb_rst_i; 165 | input [uart_addr_width-1:0] wb_adr_i; 166 | input [uart_data_width-1:0] wb_dat_i; 167 | output [uart_data_width-1:0] wb_dat_o; 168 | input wb_we_i; 169 | input wb_stb_i; 170 | input wb_cyc_i; 171 | input [3:0] wb_sel_i; 172 | output wb_ack_o; 173 | output int_o; 174 | 175 | // UART signals 176 | input srx_pad_i; 177 | output stx_pad_o; 178 | output rts_pad_o; 179 | input cts_pad_i; 180 | output dtr_pad_o; 181 | input dsr_pad_i; 182 | input ri_pad_i; 183 | input dcd_pad_i; 184 | 185 | // optional baudrate output 186 | `ifdef UART_HAS_BAUDRATE_OUTPUT 187 | output baud_o; 188 | `endif 189 | 190 | 191 | wire stx_pad_o; 192 | wire rts_pad_o; 193 | wire dtr_pad_o; 194 | 195 | wire [uart_addr_width-1:0] wb_adr_i; 196 | wire [uart_data_width-1:0] wb_dat_i; 197 | wire [uart_data_width-1:0] wb_dat_o; 198 | 199 | wire [7:0] wb_dat8_i; // 8-bit internal data input 200 | wire [7:0] wb_dat8_o; // 8-bit internal data output 201 | wire [31:0] wb_dat32_o; // debug interface 32-bit output 202 | wire [3:0] wb_sel_i; // WISHBONE select signal 203 | wire [uart_addr_width-1:0] wb_adr_int; 204 | wire we_o; // Write enable for registers 205 | wire re_o; // Read enable for registers 206 | // 207 | // MODULE INSTANCES 208 | // 209 | 210 | `ifdef DATA_BUS_WIDTH_8 211 | `else 212 | // debug interface wires 213 | wire [3:0] ier; 214 | wire [3:0] iir; 215 | wire [1:0] fcr; 216 | wire [4:0] mcr; 217 | wire [7:0] lcr; 218 | wire [7:0] msr; 219 | wire [7:0] lsr; 220 | wire [`UART_FIFO_COUNTER_W-1:0] rf_count; 221 | wire [`UART_FIFO_COUNTER_W-1:0] tf_count; 222 | wire [2:0] tstate; 223 | wire [3:0] rstate; 224 | `endif 225 | 226 | `ifdef DATA_BUS_WIDTH_8 227 | //// WISHBONE interface module 228 | uart_wb wb_interface( 229 | .clk( wb_clk_i ), 230 | .wb_rst_i( wb_rst_i ), 231 | .wb_dat_i(wb_dat_i), 232 | .wb_dat_o(wb_dat_o), 233 | .wb_dat8_i(wb_dat8_i), 234 | .wb_dat8_o(wb_dat8_o), 235 | .wb_dat32_o(32'b0), 236 | .wb_sel_i(4'b0), 237 | .wb_we_i( wb_we_i ), 238 | .wb_stb_i( wb_stb_i ), 239 | .wb_cyc_i( wb_cyc_i ), 240 | .wb_ack_o( wb_ack_o ), 241 | .wb_adr_i(wb_adr_i), 242 | .wb_adr_int(wb_adr_int), 243 | .we_o( we_o ), 244 | .re_o(re_o) 245 | ); 246 | `else 247 | uart_wb wb_interface( 248 | .clk( wb_clk_i ), 249 | .wb_rst_i( wb_rst_i ), 250 | .wb_dat_i(wb_dat_i), 251 | .wb_dat_o(wb_dat_o), 252 | .wb_dat8_i(wb_dat8_i), 253 | .wb_dat8_o(wb_dat8_o), 254 | .wb_sel_i(wb_sel_i), 255 | .wb_dat32_o(wb_dat32_o), 256 | .wb_we_i( wb_we_i ), 257 | .wb_stb_i( wb_stb_i ), 258 | .wb_cyc_i( wb_cyc_i ), 259 | .wb_ack_o( wb_ack_o ), 260 | .wb_adr_i(wb_adr_i), 261 | .wb_adr_int(wb_adr_int), 262 | .we_o( we_o ), 263 | .re_o(re_o) 264 | ); 265 | `endif 266 | 267 | // Registers 268 | uart_regs regs( 269 | .clk( wb_clk_i ), 270 | .wb_rst_i( wb_rst_i ), 271 | .wb_addr_i( wb_adr_int ), 272 | .wb_dat_i( wb_dat8_i ), 273 | .wb_dat_o( wb_dat8_o ), 274 | .wb_we_i( we_o ), 275 | .wb_re_i(re_o), 276 | .modem_inputs( {cts_pad_i, dsr_pad_i, 277 | ri_pad_i, dcd_pad_i} ), 278 | .stx_pad_o( stx_pad_o ), 279 | .srx_pad_i( srx_pad_i ), 280 | `ifdef DATA_BUS_WIDTH_8 281 | `else 282 | // debug interface signals enabled 283 | .ier(ier), 284 | .iir(iir), 285 | .fcr(fcr), 286 | .mcr(mcr), 287 | .lcr(lcr), 288 | .msr(msr), 289 | .lsr(lsr), 290 | .rf_count(rf_count), 291 | .tf_count(tf_count), 292 | .tstate(tstate), 293 | .rstate(rstate), 294 | `endif 295 | .rts_pad_o( rts_pad_o ), 296 | .dtr_pad_o( dtr_pad_o ), 297 | .int_o( int_o ) 298 | `ifdef UART_HAS_BAUDRATE_OUTPUT 299 | , .baud_o(baud_o) 300 | `endif 301 | 302 | ); 303 | 304 | `ifdef DATA_BUS_WIDTH_8 305 | `else 306 | uart_debug_if dbg(/*AUTOINST*/ 307 | // Outputs 308 | .wb_dat32_o (wb_dat32_o[31:0]), 309 | // Inputs 310 | .wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]), 311 | .ier (ier[3:0]), 312 | .iir (iir[3:0]), 313 | .fcr (fcr[1:0]), 314 | .mcr (mcr[4:0]), 315 | .lcr (lcr[7:0]), 316 | .msr (msr[7:0]), 317 | .lsr (lsr[7:0]), 318 | .rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]), 319 | .tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]), 320 | .tstate (tstate[2:0]), 321 | .rstate (rstate[3:0])); 322 | `endif 323 | 324 | initial 325 | begin 326 | `ifdef DATA_BUS_WIDTH_8 327 | $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n"); 328 | `else 329 | $display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n"); 330 | `endif 331 | `ifdef UART_HAS_BAUDRATE_OUTPUT 332 | $display("(%m) UART INFO: Has baudrate output\n"); 333 | `else 334 | $display("(%m) UART INFO: Doesn't have baudrate output\n"); 335 | `endif 336 | end 337 | 338 | endmodule 339 | 340 | 341 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/uart_transmitter.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_transmitter.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core transmitter logic //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None known //// 22 | //// //// 23 | //// To Do: //// 24 | //// Thourough testing. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - gorban@opencores.org //// 28 | //// - Jacob Gorban //// 29 | //// - Igor Mohor (igorm@opencores.org) //// 30 | //// //// 31 | //// Created: 2001/05/12 //// 32 | //// Last Updated: 2001/05/17 //// 33 | //// (See log for the revision history) //// 34 | //// //// 35 | //// //// 36 | ////////////////////////////////////////////////////////////////////// 37 | //// //// 38 | //// Copyright (C) 2000, 2001 Authors //// 39 | //// //// 40 | //// This source file may be used and distributed without //// 41 | //// restriction provided that this copyright statement is not //// 42 | //// removed from the file and that any derivative work contains //// 43 | //// the original copyright notice and the associated disclaimer. //// 44 | //// //// 45 | //// This source file is free software; you can redistribute it //// 46 | //// and/or modify it under the terms of the GNU Lesser General //// 47 | //// Public License as published by the Free Software Foundation; //// 48 | //// either version 2.1 of the License, or (at your option) any //// 49 | //// later version. //// 50 | //// //// 51 | //// This source is distributed in the hope that it will be //// 52 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 53 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 54 | //// PURPOSE. See the GNU Lesser General Public License for more //// 55 | //// details. //// 56 | //// //// 57 | //// You should have received a copy of the GNU Lesser General //// 58 | //// Public License along with this source; if not, download it //// 59 | //// from http://www.opencores.org/lgpl.shtml //// 60 | //// //// 61 | ////////////////////////////////////////////////////////////////////// 62 | // 63 | // CVS Revision History 64 | // 65 | // $Log: not supported by cvs2svn $ 66 | // Revision 1.18 2002/07/22 23:02:23 gorban 67 | // Bug Fixes: 68 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 69 | // Problem reported by Kenny.Tung. 70 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 71 | // 72 | // Improvements: 73 | // * Made FIFO's as general inferrable memory where possible. 74 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 75 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 76 | // 77 | // * Added optional baudrate output (baud_o). 78 | // This is identical to BAUDOUT* signal on 16550 chip. 79 | // It outputs 16xbit_clock_rate - the divided clock. 80 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 81 | // 82 | // Revision 1.16 2002/01/08 11:29:40 mohor 83 | // tf_pop was too wide. Now it is only 1 clk cycle width. 84 | // 85 | // Revision 1.15 2001/12/17 14:46:48 mohor 86 | // overrun signal was moved to separate block because many sequential lsr 87 | // reads were preventing data from being written to rx fifo. 88 | // underrun signal was not used and was removed from the project. 89 | // 90 | // Revision 1.14 2001/12/03 21:44:29 gorban 91 | // Updated specification documentation. 92 | // Added full 32-bit data bus interface, now as default. 93 | // Address is 5-bit wide in 32-bit data bus mode. 94 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. 95 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. 96 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. 97 | // My small test bench is modified to work with 32-bit mode. 98 | // 99 | // Revision 1.13 2001/11/08 14:54:23 mohor 100 | // Comments in Slovene language deleted, few small fixes for better work of 101 | // old tools. IRQs need to be fix. 102 | // 103 | // Revision 1.12 2001/11/07 17:51:52 gorban 104 | // Heavily rewritten interrupt and LSR subsystems. 105 | // Many bugs hopefully squashed. 106 | // 107 | // Revision 1.11 2001/10/29 17:00:46 gorban 108 | // fixed parity sending and tx_fifo resets over- and underrun 109 | // 110 | // Revision 1.10 2001/10/20 09:58:40 gorban 111 | // Small synopsis fixes 112 | // 113 | // Revision 1.9 2001/08/24 21:01:12 mohor 114 | // Things connected to parity changed. 115 | // Clock devider changed. 116 | // 117 | // Revision 1.8 2001/08/23 16:05:05 mohor 118 | // Stop bit bug fixed. 119 | // Parity bug fixed. 120 | // WISHBONE read cycle bug fixed, 121 | // OE indicator (Overrun Error) bug fixed. 122 | // PE indicator (Parity Error) bug fixed. 123 | // Register read bug fixed. 124 | // 125 | // Revision 1.6 2001/06/23 11:21:48 gorban 126 | // DL made 16-bit long. Fixed transmission/reception bugs. 127 | // 128 | // Revision 1.5 2001/06/02 14:28:14 gorban 129 | // Fixed receiver and transmitter. Major bug fixed. 130 | // 131 | // Revision 1.4 2001/05/31 20:08:01 gorban 132 | // FIFO changes and other corrections. 133 | // 134 | // Revision 1.3 2001/05/27 17:37:49 gorban 135 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. 136 | // 137 | // Revision 1.2 2001/05/21 19:12:02 gorban 138 | // Corrected some Linter messages. 139 | // 140 | // Revision 1.1 2001/05/17 18:34:18 gorban 141 | // First 'stable' release. Should be sythesizable now. Also added new header. 142 | // 143 | // Revision 1.0 2001-05-17 21:27:12+02 jacob 144 | // Initial revision 145 | // 146 | // 147 | 148 | // synopsys translate_off 149 | `include "timescale.v" 150 | // synopsys translate_on 151 | 152 | `include "uart_defines.v" 153 | 154 | module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); 155 | 156 | input clk; 157 | input wb_rst_i; 158 | input [7:0] lcr; 159 | input tf_push; 160 | input [7:0] wb_dat_i; 161 | input enable; 162 | input tx_reset; 163 | input lsr_mask; //reset of fifo 164 | output stx_pad_o; 165 | output [2:0] tstate; 166 | output [`UART_FIFO_COUNTER_W-1:0] tf_count; 167 | 168 | reg [2:0] tstate; 169 | reg [4:0] counter; 170 | reg [2:0] bit_counter; // counts the bits to be sent 171 | reg [6:0] shift_out; // output shift register 172 | reg stx_o_tmp; 173 | reg parity_xor; // parity of the word 174 | reg tf_pop; 175 | reg bit_out; 176 | 177 | // TX FIFO instance 178 | // 179 | // Transmitter FIFO signals 180 | wire [`UART_FIFO_WIDTH-1:0] tf_data_in; 181 | wire [`UART_FIFO_WIDTH-1:0] tf_data_out; 182 | wire tf_push; 183 | wire tf_overrun; 184 | wire [`UART_FIFO_COUNTER_W-1:0] tf_count; 185 | 186 | assign tf_data_in = wb_dat_i; 187 | 188 | uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO 189 | .clk( clk ), 190 | .wb_rst_i( wb_rst_i ), 191 | .data_in( tf_data_in ), 192 | .data_out( tf_data_out ), 193 | .push( tf_push ), 194 | .pop( tf_pop ), 195 | .overrun( tf_overrun ), 196 | .count( tf_count ), 197 | .fifo_reset( tx_reset ), 198 | .reset_status(lsr_mask) 199 | ); 200 | 201 | // TRANSMITTER FINAL STATE MACHINE 202 | 203 | parameter s_idle = 3'd0; 204 | parameter s_send_start = 3'd1; 205 | parameter s_send_byte = 3'd2; 206 | parameter s_send_parity = 3'd3; 207 | parameter s_send_stop = 3'd4; 208 | parameter s_pop_byte = 3'd5; 209 | 210 | always @(posedge clk or posedge wb_rst_i) 211 | begin 212 | if (wb_rst_i) 213 | begin 214 | tstate <= #1 s_idle; 215 | stx_o_tmp <= #1 1'b1; 216 | counter <= #1 5'b0; 217 | shift_out <= #1 7'b0; 218 | bit_out <= #1 1'b0; 219 | parity_xor <= #1 1'b0; 220 | tf_pop <= #1 1'b0; 221 | bit_counter <= #1 3'b0; 222 | end 223 | else 224 | if (enable) 225 | begin 226 | case (tstate) 227 | s_idle : if (~|tf_count) // if tf_count==0 228 | begin 229 | tstate <= #1 s_idle; 230 | stx_o_tmp <= #1 1'b1; 231 | end 232 | else 233 | begin 234 | tf_pop <= #1 1'b0; 235 | stx_o_tmp <= #1 1'b1; 236 | tstate <= #1 s_pop_byte; 237 | end 238 | s_pop_byte : begin 239 | tf_pop <= #1 1'b1; 240 | case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word 241 | 2'b00 : begin 242 | bit_counter <= #1 3'b100; 243 | parity_xor <= #1 ^tf_data_out[4:0]; 244 | end 245 | 2'b01 : begin 246 | bit_counter <= #1 3'b101; 247 | parity_xor <= #1 ^tf_data_out[5:0]; 248 | end 249 | 2'b10 : begin 250 | bit_counter <= #1 3'b110; 251 | parity_xor <= #1 ^tf_data_out[6:0]; 252 | end 253 | 2'b11 : begin 254 | bit_counter <= #1 3'b111; 255 | parity_xor <= #1 ^tf_data_out[7:0]; 256 | end 257 | endcase 258 | {shift_out[6:0], bit_out} <= #1 tf_data_out; 259 | tstate <= #1 s_send_start; 260 | end 261 | s_send_start : begin 262 | tf_pop <= #1 1'b0; 263 | if (~|counter) 264 | counter <= #1 5'b01111; 265 | else 266 | if (counter == 5'b00001) 267 | begin 268 | counter <= #1 0; 269 | tstate <= #1 s_send_byte; 270 | end 271 | else 272 | counter <= #1 counter - 1'b1; 273 | stx_o_tmp <= #1 1'b0; 274 | end 275 | s_send_byte : begin 276 | if (~|counter) 277 | counter <= #1 5'b01111; 278 | else 279 | if (counter == 5'b00001) 280 | begin 281 | if (bit_counter > 3'b0) 282 | begin 283 | bit_counter <= #1 bit_counter - 1'b1; 284 | {shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]}; 285 | tstate <= #1 s_send_byte; 286 | end 287 | else // end of byte 288 | if (~lcr[`UART_LC_PE]) 289 | begin 290 | tstate <= #1 s_send_stop; 291 | end 292 | else 293 | begin 294 | case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) 295 | 2'b00: bit_out <= #1 ~parity_xor; 296 | 2'b01: bit_out <= #1 1'b1; 297 | 2'b10: bit_out <= #1 parity_xor; 298 | 2'b11: bit_out <= #1 1'b0; 299 | endcase 300 | tstate <= #1 s_send_parity; 301 | end 302 | counter <= #1 0; 303 | end 304 | else 305 | counter <= #1 counter - 1'b1; 306 | stx_o_tmp <= #1 bit_out; // set output pin 307 | end 308 | s_send_parity : begin 309 | if (~|counter) 310 | counter <= #1 5'b01111; 311 | else 312 | if (counter == 5'b00001) 313 | begin 314 | counter <= #1 4'b0; 315 | tstate <= #1 s_send_stop; 316 | end 317 | else 318 | counter <= #1 counter - 1'b1; 319 | stx_o_tmp <= #1 bit_out; 320 | end 321 | s_send_stop : begin 322 | if (~|counter) 323 | begin 324 | casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) 325 | 3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor 326 | 3'b100: counter <= #1 5'b10101; // 1.5 stop bit 327 | default: counter <= #1 5'b11101; // 2 stop bits 328 | endcase 329 | end 330 | else 331 | if (counter == 5'b00001) 332 | begin 333 | counter <= #1 0; 334 | tstate <= #1 s_idle; 335 | end 336 | else 337 | counter <= #1 counter - 1'b1; 338 | stx_o_tmp <= #1 1'b1; 339 | end 340 | 341 | default : // should never get here 342 | tstate <= #1 s_idle; 343 | endcase 344 | end // end if enable 345 | else 346 | tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width 347 | end // transmitter logic 348 | 349 | assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition 350 | 351 | endmodule 352 | -------------------------------------------------------------------------------- /a5/scr1/ip/uart/uart_wb.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_wb.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core WISHBONE interface. //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// Inserts one wait state on all transfers. //// 22 | //// Note affected signals and the way they are affected. //// 23 | //// //// 24 | //// To Do: //// 25 | //// Nothing. //// 26 | //// //// 27 | //// Author(s): //// 28 | //// - gorban@opencores.org //// 29 | //// - Jacob Gorban //// 30 | //// - Igor Mohor (igorm@opencores.org) //// 31 | //// //// 32 | //// Created: 2001/05/12 //// 33 | //// Last Updated: 2001/05/17 //// 34 | //// (See log for the revision history) //// 35 | //// //// 36 | //// //// 37 | ////////////////////////////////////////////////////////////////////// 38 | //// //// 39 | //// Copyright (C) 2000, 2001 Authors //// 40 | //// //// 41 | //// This source file may be used and distributed without //// 42 | //// restriction provided that this copyright statement is not //// 43 | //// removed from the file and that any derivative work contains //// 44 | //// the original copyright notice and the associated disclaimer. //// 45 | //// //// 46 | //// This source file is free software; you can redistribute it //// 47 | //// and/or modify it under the terms of the GNU Lesser General //// 48 | //// Public License as published by the Free Software Foundation; //// 49 | //// either version 2.1 of the License, or (at your option) any //// 50 | //// later version. //// 51 | //// //// 52 | //// This source is distributed in the hope that it will be //// 53 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 54 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 55 | //// PURPOSE. See the GNU Lesser General Public License for more //// 56 | //// details. //// 57 | //// //// 58 | //// You should have received a copy of the GNU Lesser General //// 59 | //// Public License along with this source; if not, download it //// 60 | //// from http://www.opencores.org/lgpl.shtml //// 61 | //// //// 62 | ////////////////////////////////////////////////////////////////////// 63 | // 64 | // CVS Revision History 65 | // 66 | // $Log: not supported by cvs2svn $ 67 | // Revision 1.16 2002/07/29 21:16:18 gorban 68 | // The uart_defines.v file is included again in sources. 69 | // 70 | // Revision 1.15 2002/07/22 23:02:23 gorban 71 | // Bug Fixes: 72 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 73 | // Problem reported by Kenny.Tung. 74 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 75 | // 76 | // Improvements: 77 | // * Made FIFO's as general inferrable memory where possible. 78 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 79 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 80 | // 81 | // * Added optional baudrate output (baud_o). 82 | // This is identical to BAUDOUT* signal on 16550 chip. 83 | // It outputs 16xbit_clock_rate - the divided clock. 84 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 85 | // 86 | // Revision 1.12 2001/12/19 08:03:34 mohor 87 | // Warnings cleared. 88 | // 89 | // Revision 1.11 2001/12/06 14:51:04 gorban 90 | // Bug in LSR[0] is fixed. 91 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. 92 | // 93 | // Revision 1.10 2001/12/03 21:44:29 gorban 94 | // Updated specification documentation. 95 | // Added full 32-bit data bus interface, now as default. 96 | // Address is 5-bit wide in 32-bit data bus mode. 97 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. 98 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. 99 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. 100 | // My small test bench is modified to work with 32-bit mode. 101 | // 102 | // Revision 1.9 2001/10/20 09:58:40 gorban 103 | // Small synopsis fixes 104 | // 105 | // Revision 1.8 2001/08/24 21:01:12 mohor 106 | // Things connected to parity changed. 107 | // Clock devider changed. 108 | // 109 | // Revision 1.7 2001/08/23 16:05:05 mohor 110 | // Stop bit bug fixed. 111 | // Parity bug fixed. 112 | // WISHBONE read cycle bug fixed, 113 | // OE indicator (Overrun Error) bug fixed. 114 | // PE indicator (Parity Error) bug fixed. 115 | // Register read bug fixed. 116 | // 117 | // Revision 1.4 2001/05/31 20:08:01 gorban 118 | // FIFO changes and other corrections. 119 | // 120 | // Revision 1.3 2001/05/21 19:12:01 gorban 121 | // Corrected some Linter messages. 122 | // 123 | // Revision 1.2 2001/05/17 18:34:18 gorban 124 | // First 'stable' release. Should be sythesizable now. Also added new header. 125 | // 126 | // Revision 1.0 2001-05-17 21:27:13+02 jacob 127 | // Initial revision 128 | // 129 | // 130 | 131 | // UART core WISHBONE interface 132 | // 133 | // Author: Jacob Gorban (jacob.gorban@flextronicssemi.com) 134 | // Company: Flextronics Semiconductor 135 | // 136 | 137 | // synopsys translate_off 138 | `include "timescale.v" 139 | // synopsys translate_on 140 | `include "uart_defines.v" 141 | 142 | module uart_wb (clk, wb_rst_i, 143 | wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, 144 | wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i, 145 | we_o, re_o // Write and read enable output for the core 146 | ); 147 | 148 | input clk; 149 | 150 | // WISHBONE interface 151 | input wb_rst_i; 152 | input wb_we_i; 153 | input wb_stb_i; 154 | input wb_cyc_i; 155 | input [3:0] wb_sel_i; 156 | input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line 157 | 158 | `ifdef DATA_BUS_WIDTH_8 159 | input [7:0] wb_dat_i; //input WISHBONE bus 160 | output [7:0] wb_dat_o; 161 | reg [7:0] wb_dat_o; 162 | wire [7:0] wb_dat_i; 163 | reg [7:0] wb_dat_is; 164 | `else // for 32 data bus mode 165 | input [31:0] wb_dat_i; //input WISHBONE bus 166 | output [31:0] wb_dat_o; 167 | reg [31:0] wb_dat_o; 168 | wire [31:0] wb_dat_i; 169 | reg [31:0] wb_dat_is; 170 | `endif // !`ifdef DATA_BUS_WIDTH_8 171 | 172 | output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus 173 | input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o 174 | output [7:0] wb_dat8_i; 175 | input [31:0] wb_dat32_o; // 32 bit data output (for debug interface) 176 | output wb_ack_o; 177 | output we_o; 178 | output re_o; 179 | 180 | wire we_o; 181 | reg wb_ack_o; 182 | reg [7:0] wb_dat8_i; 183 | wire [7:0] wb_dat8_o; 184 | wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus 185 | reg [`UART_ADDR_WIDTH-1:0] wb_adr_is; 186 | reg wb_we_is; 187 | reg wb_cyc_is; 188 | reg wb_stb_is; 189 | reg [3:0] wb_sel_is; 190 | wire [3:0] wb_sel_i; 191 | reg wre ;// timing control signal for write or read enable 192 | 193 | // wb_ack_o FSM 194 | reg [1:0] wbstate; 195 | always @(posedge clk or posedge wb_rst_i) 196 | if (wb_rst_i) begin 197 | wb_ack_o <= #1 1'b0; 198 | wbstate <= #1 0; 199 | wre <= #1 1'b1; 200 | end else 201 | case (wbstate) 202 | 0: begin 203 | if (wb_stb_is & wb_cyc_is) begin 204 | wre <= #1 0; 205 | wbstate <= #1 1; 206 | wb_ack_o <= #1 1; 207 | end else begin 208 | wre <= #1 1; 209 | wb_ack_o <= #1 0; 210 | end 211 | end 212 | 1: begin 213 | wb_ack_o <= #1 0; 214 | wbstate <= #1 2; 215 | wre <= #1 0; 216 | end 217 | 2,3: begin 218 | wb_ack_o <= #1 0; 219 | wbstate <= #1 0; 220 | wre <= #1 0; 221 | end 222 | endcase 223 | 224 | assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers 225 | assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers 226 | 227 | // Sample input signals 228 | always @(posedge clk or posedge wb_rst_i) 229 | if (wb_rst_i) begin 230 | wb_adr_is <= #1 0; 231 | wb_we_is <= #1 0; 232 | wb_cyc_is <= #1 0; 233 | wb_stb_is <= #1 0; 234 | wb_dat_is <= #1 0; 235 | wb_sel_is <= #1 0; 236 | end else begin 237 | wb_adr_is <= #1 wb_adr_i; 238 | wb_we_is <= #1 wb_we_i; 239 | wb_cyc_is <= #1 wb_cyc_i; 240 | wb_stb_is <= #1 wb_stb_i; 241 | wb_dat_is <= #1 wb_dat_i; 242 | wb_sel_is <= #1 wb_sel_i; 243 | end 244 | 245 | `ifdef DATA_BUS_WIDTH_8 // 8-bit data bus 246 | always @(posedge clk or posedge wb_rst_i) 247 | if (wb_rst_i) 248 | wb_dat_o <= #1 0; 249 | else 250 | wb_dat_o <= #1 wb_dat8_o; 251 | 252 | always @(wb_dat_is) 253 | wb_dat8_i = wb_dat_is; 254 | 255 | assign wb_adr_int = wb_adr_is; 256 | 257 | `else // 32-bit bus 258 | // put output to the correct byte in 32 bits using select line 259 | always @(posedge clk or posedge wb_rst_i) 260 | if (wb_rst_i) 261 | wb_dat_o <= #1 0; 262 | else if (re_o) 263 | case (wb_sel_is) 264 | 4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o}; 265 | 4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0}; 266 | 4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0}; 267 | 4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0}; 268 | 4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output 269 | default: wb_dat_o <= #1 0; 270 | endcase // case(wb_sel_i) 271 | 272 | reg [1:0] wb_adr_int_lsb; 273 | 274 | always @(wb_sel_is or wb_dat_is) 275 | begin 276 | case (wb_sel_is) 277 | 4'b0001 : wb_dat8_i = wb_dat_is[7:0]; 278 | 4'b0010 : wb_dat8_i = wb_dat_is[15:8]; 279 | 4'b0100 : wb_dat8_i = wb_dat_is[23:16]; 280 | 4'b1000 : wb_dat8_i = wb_dat_is[31:24]; 281 | default : wb_dat8_i = wb_dat_is[7:0]; 282 | endcase // case(wb_sel_i) 283 | 284 | `ifdef LITLE_ENDIAN 285 | case (wb_sel_is) 286 | 4'b0001 : wb_adr_int_lsb = 2'h0; 287 | 4'b0010 : wb_adr_int_lsb = 2'h1; 288 | 4'b0100 : wb_adr_int_lsb = 2'h2; 289 | 4'b1000 : wb_adr_int_lsb = 2'h3; 290 | default : wb_adr_int_lsb = 2'h0; 291 | endcase // case(wb_sel_i) 292 | `else 293 | case (wb_sel_is) 294 | 4'b0001 : wb_adr_int_lsb = 2'h3; 295 | 4'b0010 : wb_adr_int_lsb = 2'h2; 296 | 4'b0100 : wb_adr_int_lsb = 2'h1; 297 | 4'b1000 : wb_adr_int_lsb = 2'h0; 298 | default : wb_adr_int_lsb = 2'h0; 299 | endcase // case(wb_sel_i) 300 | `endif 301 | end 302 | 303 | assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb}; 304 | 305 | `endif // !`ifdef DATA_BUS_WIDTH_8 306 | 307 | endmodule 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | -------------------------------------------------------------------------------- /arty/scr1/.gitignore: -------------------------------------------------------------------------------- 1 | .Xil/** 2 | arty_scr1/** 3 | !bd/sys_pll/sys_pll.bd 4 | !bd/system/system.bd 5 | 6 | -------------------------------------------------------------------------------- /arty/scr1/README.md: -------------------------------------------------------------------------------- 1 | # SCR1 SDK. Xilinx Vivado Design Suite project for Arty board 2 | 3 | ## Key features 4 | * Board: Digilent Arty (https://reference.digilentinc.com/reference/programmable-logic/arty/start) 5 | * Tool: Xilinx Vivado Design Suite 2017.3 6 | 7 | ## Folder contents 8 | Folder | Description 9 | ------ | ----------- 10 | constrs | Constraint files 11 | src | Project's RTL source files 12 | arty_scr1.tcl | TCL-file for project creation 13 | mem_update.tcl | TCL-file for onchip SRAM memory initialization 14 | README.md | This file 15 | scbl.mem | The onchip SRAM memory content file with the SCR1 Bootloader 16 | write_mmi.tcl | TCL-file with procedures for mem_update.tcl 17 | 18 | Hereinafter this folder is named (the folder containing this README file). 19 | 20 | ## Project deployment 21 | 1. Install Arty's board files in Vivado directory structure, as described here: 22 | https://reference.digilentinc.com/reference/software/vivado/board-files 23 | 24 | 25 | 2. Launch Vivado IDE, and in its Tcl Console change current directory to the . 26 | 27 | 3. In Tcl Console, execute the following command 28 | 29 | 30 | source ./arty_scr1.tcl 31 | 32 | The script "arty_scr1.tcl" creates Vivado project arty_scr1 and prepares used IPs for further synthesis. 33 | 34 | ## Synthesizing design and building bitstream file 35 | In the just deployed and open project, click on 36 | 37 | * Project Navigator / Program and Debug / Generate Bitstream button 38 | 39 | and press OK on the following Vivado confirmation request. 40 | This will start the process of full design rebuilding, from synthesis through bitstream file generation. 41 | 42 | ## Onchip memory update 43 | Due to Vivado Design Suite specifics described in the Xilinx AR #63042, initialization of the onchip memories 44 | is performed after bitstream file generation, by a standalone script mem_update.tcl. 45 | 46 | In the Tcl Console, execute the following commands: 47 | 48 | cd /arty_scr1 49 | source "../../../scripts/xilinx/mem_update.tcl" 50 | 51 | After successful completion, the folder 52 | 53 | /arty_scr1/arty.runs/impl_1 54 | 55 | should contain updated bit-file arty_scr1_top_new.bit and MCS-file arty_scr1_top_new.mcs for configuration FLASH chip programming. 56 | 57 | ## SCR1 Memory Map 58 | Base Address | Length | Name | Description 59 | ------------ | ------ | ------------- | ----------- 60 | 0x00000000 | 256 MB | SDRAM | Onboard DDR3L SDRAM. 61 | 0xF0000000 | 64 kB | TCM | SCR1 Tightly-Coupled Memory (refer to SCR1 EAS). 62 | 0xF0040000 | 32 B | Timer | SCR1 Timer registers (refer to SCR1 EAS). 63 | 0xFF000000 | | MMIO BASE | Base address for Memory-Mapped Peripheral IO resources, resided externally to SCR1 core. 64 | 0xFF000000 | 4 kB | SOC_ID | 32-bit SOC_ID register. 65 | 0xFF001000 | 4 kB | BLD_ID | 32-bit BLD_ID register. 66 | 0xFF002000 | 4 kB | CORE_CLK_FREQ | 32-bit Core Clock Frequency register. 67 | 0xFF010000 | 4 kB | UART | 16550 UART registers (refer to Xilinx IP description for details). Interrupt line is assigned to IRQ[0]. 68 | 0xFF020000 | 4 kB | LED | LED PIO registers: PIO_LED. 69 | 0xFF021000 | 4 kB | LED_RGB | RGB LED PIO registers: PIO_LED_RGB. 70 | 0xFF028000 | 4 kB | BTN | Push Button PIO register: PIO_PBUTTON. Has associated interrupt line assigned to IRQ[1]. 71 | 0xFFFF0000 | 64 kB | SRAM | Onchip SRAM containing pre-programmed SCR Loader firmware. SCR1_RST_VECTOR and SCR1_CSR_MTVEC_BASE are both mapped here. 72 | 73 | ## MMIO Registers 74 | 75 | ### PIO_LED, Programmable IO LED Control Register (0xFF020000) 76 | Bit(s) | Name | Description 77 | -------| ---- | ----------- 78 | 0 | LED0 | LED[0] control: corresponds to the onboard LD4. If a bit is 1, LED is illuminated. 79 | 1 | LED1 | LED[1] control (onboard LD5). 80 | 81 | ### PIO_LED_RGB, Programmable IO LED RGB Control Register (0xFF021000) 82 | Bit(s) | Name | Description 83 | -------| ---- | ----------- 84 | 0..2 | LED0 | LED[0] control: bits [2:0] correspond to {red, green, blue} partial LEDs of the onboard LD0. If a bit is 1, appropriate internal LED is illuminated. 85 | 3..5 | LED1 | LED[1] control (onboard LD1). 86 | 6..8 | LED2 | LED[2] control (onboard LD2). 87 | 9..11 | LED3 | LED[3] control (onboard LD3). 88 | 89 | ### PIO_PBUTTON, Programmable IO Push Button Status Register (0xFF028000) 90 | Bit(s) | Name | Description 91 | -------| ---- | ----------- 92 | 0..3 | BTN | BTN status: bits [3:0] correspond to {BTN3, BTN2, BTN1, BTN0} onboard push buttons. For details refer to the Xilinx AXI GPIO IP documentation. 93 | 94 | 95 | ## SCR1 JTAG Pin-Out 96 | 97 | SCR1 JTAG port is routed to the onboard Pmod connector JD. 98 | 99 | Net | JD bit | Pmod JD pin 100 | -------| ------ | ----------- 101 | TRSTn | 2 | 3 102 | TCK | 3 | 4 103 | TDO | 4 | 7 104 | TDI | 5 | 8 105 | SRSTn | 6 | 9 106 | TMS | 7 | 10 107 | 108 | -------------------------------------------------------------------------------- /arty/scr1/constrs/arty_scr1_synth.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 3 | ## @file 4 | ## @brief Constraint file for Xilinx Vivado synthesis. 5 | ## 6 | 7 | ## Primary Clocks 8 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports OSC_100] 9 | create_clock -period 10.000 -name OSC_100 -waveform {0.000 5.000} -add [get_ports OSC_100] 10 | create_clock -period 40.000 -name CPU_CLK_VIRT -waveform {0.000 20.000} 11 | create_clock -period 100.000 -name JTAG_TCK -waveform {0.000 50.000} -add [get_ports {JD[3]}] 12 | create_clock -period 100.000 -name JTAG_TCK_VIRT -waveform {0.000 50.000} 13 | -------------------------------------------------------------------------------- /arty/scr1/constrs/arty_scr1_timing.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 3 | ## @file 4 | ## @brief Timing constraints file for Xilinx Vivado implementation. 5 | ## 6 | 7 | # NB! Primary clocks are defined in the synthesis constraint file (*_synth.xdc). 8 | 9 | create_generated_clock -name CPU_CLK [get_pins i_soc/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0] 10 | 11 | set_clock_groups -name async_osc100_tck -asynchronous -group {OSC_100 CPU_CLK CPU_CLK_VIRT} -group {JTAG_TCK JTAG_TCK_VIRT} 12 | 13 | set_false_path -from [get_clocks JTAG_TCK] -to [get_clocks CPU_CLK] 14 | set_false_path -from [get_clocks JTAG_TCK_VIRT] -to [get_clocks CPU_CLK] 15 | set_false_path -from [get_clocks CPU_CLK] -to [get_clocks JTAG_TCK] 16 | 17 | set_input_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports RESETn] 18 | set_input_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports FTDI_TXD] 19 | set_input_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports {BTN*}] 20 | set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JD[2]}] 21 | set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JD[4]}] 22 | set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JD[5]}] 23 | set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JD[6]}] 24 | set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JD[7]}] 25 | 26 | set_output_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports FTDI_RXD] 27 | set_output_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports LED*] 28 | set_output_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JD[*]}] 29 | 30 | -------------------------------------------------------------------------------- /arty/scr1/mem_update.tcl: -------------------------------------------------------------------------------- 1 | # Tcl-file for Xilinx Vivado projects: mem_update.tcl 2 | 3 | # Input parameters: 4 | set proj [current_project] 5 | set proj_dir [get_property directory [current_project]] 6 | set top_entity [get_property top [get_filesets sources_1]] 7 | set obj_dir [get_property directory [get_runs impl_1]] 8 | #set mem_file "../[glob -nocomplain *.mem]" 9 | set mem_file "../scbl.mem" 10 | set bit_file "${top_entity}.bit" 11 | set out_file "${top_entity}_new.bit" 12 | set cmd_file "../write_mmi.tcl" 13 | set sram_cell "blk_mem_gen_0" 14 | set mmi_file "${sram_cell}.mmi" 15 | set mcs_file "${top_entity}_new.mcs" 16 | 17 | # Normalization 18 | set obj_dir [file normalize "$obj_dir"] 19 | set mem_file [file normalize "$proj_dir/$mem_file"] 20 | set bit_file [file normalize "$obj_dir/$bit_file"] 21 | set out_file [file normalize "$obj_dir/$out_file"] 22 | set cmd_file [file normalize "$proj_dir/$cmd_file"] 23 | set mmi_file [file normalize "$obj_dir/$mmi_file"] 24 | set mcs_file [file normalize "$obj_dir/$mcs_file"] 25 | 26 | # Check if necessary files are present 27 | if {![file exists $bit_file]} { 28 | error "ERROR! Bit-file $bit_file is not found." 29 | } 30 | if {![file exists $mem_file]} { 31 | error "ERROR! Mem-file $mem_file is not found." 32 | } 33 | 34 | # Sourcing of write_mmi.tcl 35 | # It is necessary for onchip memory initialization. 36 | # For details refer to Xilinx AR 63042. 37 | if {![file exists $cmd_file]} { 38 | error "ERROR! Tcl-script $cmd_file is not found." 39 | } else { 40 | source -quiet $cmd_file 41 | } 42 | 43 | open_run -quiet impl_1 44 | 45 | if {[get_cells -hierarchical $sram_cell] eq ""} { 46 | error "ERROR! SRAM cell $sram_cell is not found in the design impl_1." 47 | } 48 | 49 | write_mmi $sram_cell $mmi_file 50 | 51 | exec updatemem -force --meminfo $mmi_file --data $mem_file --bit $bit_file \ 52 | --proc "dummy" --out $out_file 53 | 54 | write_cfgmem -force -format mcs -size 16 -interface SPIx4 \ 55 | -loadbit "up 0x00000000 $out_file " -checksum \ 56 | -file "$mcs_file" 57 | -------------------------------------------------------------------------------- /arty/scr1/src/scr1_arch_custom.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_ARCH_CUSTOM_SVH 2 | `define SCR1_ARCH_CUSTOM_SVH 3 | /// Copyright by Syntacore LLC ?? 2016, 2017, 2021. See LICENSE for details 4 | /// @file 5 | /// @brief Custom Architecture Parameters File 6 | /// 7 | 8 | // Current FPGA build identificators, can be modified 9 | `define SCR1_PTFM_SOC_ID 32'h21050500 10 | `define SCR1_PTFM_BLD_ID 32'h22011201 11 | `define SCR1_PTFM_CORE_CLK_FREQ 32'd25000000 12 | 13 | `define SCR1_TRGT_FPGA_XILINX // Uncomment if target platform is Xilinx FPGAs 14 | //`define SCR1_TRGT_FPGA_INTEL // Uncomment if target platform is Intel FPGAs AND ---> 15 | //`define SCR1_TRGT_FPGA_INTEL_MAX10 // ---> Uncomment if target platform is Intel MAX 10 FPGAs 16 | //`define SCR1_TRGT_FPGA_INTEL_ARRIAV // ---> Uncomment if target platform is Intel Arria V FPGAs 17 | 18 | 19 | 20 | 21 | 22 | // Uncomment to select recommended core architecture configurations 23 | // Default SCR1 FPGA SDK created for RV32IMC_MAX config 24 | 25 | `define SCR1_CFG_RV32IMC_MAX 26 | //`define SCR1_CFG_RV32IC_BASE 27 | //`define SCR1_CFG_RV32EC_MIN 28 | 29 | 30 | 31 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_RST_VECTOR = 'hFFFFFF00; // Reset vector 32 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_MTVEC_BASE = 'hFFFFFF80; // MTVEC BASE field reset value 33 | 34 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_MASK = 'hFFFF0000; // TCM mask and size 35 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_PATTERN = 'hF0000000; // TCM address match pattern 36 | 37 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_MASK = 'hFFFFFFE0; // Timer mask (should be 0xFFFFFFE0) 38 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_PATTERN = 'hF0040000; // Timer address match pattern 39 | 40 | `endif // SCR1_ARCH_CUSTOM_SVH -------------------------------------------------------------------------------- /arty/scr1/write_mmi.tcl: -------------------------------------------------------------------------------- 1 | #Created by stephenm@xilinx.com. This is not supported by WTS 2 | #The cell_name is the name of the Block RAM in the BD. 3 | #This has been tested with a memory range 0K - 1M 4 | #This only supports data width of 32 bits. 5 | 6 | 7 | proc write_mmi {cell_name filename} { 8 | set proj [current_project] 9 | # set filename "${cell_name}.mmi" 10 | set fileout [open $filename "w"] 11 | set brams [split [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }] " "] 12 | #isolate all BRAMs identified by cell_name 13 | set cell_name_bram "" 14 | for {set i 0} {$i < [llength $brams]} {incr i} { 15 | if { [regexp -nocase $cell_name [lindex $brams $i]] } { 16 | lappend cell_name_bram [lindex $brams $i] 17 | } 18 | } 19 | set proc_found 0 20 | set inst_path "dummy" 21 | #set inst_path [split [get_cells -hierarchical -filter { NAME =~ "*microblaze*" } ] " "] 22 | if {$inst_path == ""} { 23 | puts "Warning: No Processor found" 24 | set inst_path "dummy" 25 | } else { 26 | set proc_found 1 27 | set inst_path [lindex $inst_path 0] 28 | } 29 | 30 | puts $fileout "" 31 | puts $fileout "" 32 | set inst_temp [lindex $brams 0] 33 | set loc_temp [string first $cell_name $inst_temp] 34 | set inst [string range $inst_temp 0 $loc_temp] 35 | set new_inst [string last "/" $inst] 36 | set new_inst [string range $inst 0 $new_inst-1] 37 | puts $fileout " " 38 | set bram_range 0 39 | for {set i 0} {$i < [llength $cell_name_bram]} {incr i} { 40 | set bram_type [get_property REF_NAME [get_cells [lindex $cell_name_bram $i]]] 41 | if {$bram_type == "RAMB36E1"} { 42 | set bram_range [expr {$bram_range + 4096}] 43 | } 44 | } 45 | puts $fileout " " 46 | 47 | set bram [llength $cell_name_bram] 48 | if {$bram >= 32} { 49 | set sequence "7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24" 50 | set bus_blocks [expr {$bram / 32}] 51 | } elseif {$bram >= 16 && $bram < 32} { 52 | set sequence "7,5,3,1,15,13,11,9,23,21,19,17,31,29,27,25" 53 | set bus_blocks 1 54 | } elseif {$bram >= 8 && $bram < 16} { 55 | set sequence "7,3,15,11,23,19,31,27" 56 | set bus_blocks 1 57 | } elseif {$bram >= 4 && $bram < 8} { 58 | set sequence "7,15,23,31" 59 | set bus_blocks 1 60 | } else { 61 | set sequence "15,31" 62 | set bus_blocks 1 63 | } 64 | set sequence [split $sequence ","] 65 | 66 | 67 | for {set b 0} {$b < $bus_blocks} {incr b} { 68 | puts $fileout " " 69 | for {set i 0} {$i < [llength $sequence]} {incr i} { 70 | for {set j 0} {$j < [llength $cell_name_bram]} {incr j} { 71 | set block_start [expr {32768 * $b}] 72 | set bmm_width [bram_info [lindex $cell_name_bram $j] "bit_lane"] 73 | set bmm_width [split $bmm_width ":"] 74 | set bmm_msb [lindex $bmm_width 0] 75 | set bmm_lsb [lindex $bmm_width 1] 76 | set bmm_range [bram_info [lindex $cell_name_bram $j] "range"] 77 | set split_ranges [split $bmm_range ":"] 78 | set MSB [lindex $sequence $i] 79 | if {$MSB == $bmm_msb && $block_start == [lindex $split_ranges 0]} { 80 | set bram_type [get_property REF_NAME [get_cells [lindex $cell_name_bram $j]]] 81 | set status [get_property STATUS [get_cells [lindex $cell_name_bram $j]]] 82 | 83 | if {$status == "UNPLACED"} { 84 | set placed "X0Y0" 85 | } else { 86 | set placed [get_property LOC [get_cells [lindex $cell_name_bram $j]]] 87 | set placed_list [split $placed "_"] 88 | set placed [lindex $placed_list 1] 89 | } 90 | set bram_type [get_property REF_NAME [get_cells [lindex $cell_name_bram $j]]] 91 | if {$bram_type == "RAMB36E1"} { 92 | set bram_type "RAMB32" 93 | } 94 | 95 | puts $fileout " " 96 | puts $fileout " " 97 | puts $fileout " " 98 | puts $fileout " " 99 | puts $fileout " " 100 | } 101 | } 102 | } 103 | puts $fileout " " 104 | puts $fileout " " 105 | } 106 | puts $fileout " " 107 | puts $fileout "" 108 | puts $fileout " " 110 | puts $fileout "" 111 | close $fileout 112 | puts "MMI file ($filename) created successfully." 113 | puts "To run Updatemem, use the command line below after write_bitstream:" 114 | puts "updatemem -force --meminfo $filename --data .elf/mem --bit .bit --proc $inst_path --out .bit" 115 | } 116 | 117 | proc bram_info {bram type} { 118 | set temp [get_property bmm_info_memory_device [get_cells $bram]] 119 | set bmm_info_memory_device [regexp {\[(.+)\]\[(.+)\]} $temp all 1 2] 120 | if {$type == "bit_lane"} { 121 | return $1 122 | } elseif {$type == "range"} { 123 | return $2 124 | } else { 125 | return $all 126 | } 127 | } 128 | 129 | proc export2sdk {} { 130 | set proj [current_project] 131 | set file_list "" 132 | set get_impl [split [get_runs] " "] 133 | set get_impl [lindex $get_impl [expr {[llength $get_impl] - 1}]] 134 | set sdk_dir [glob -nocomplain -type d *.sdk] 135 | if {$sdk_dir == ""} { 136 | puts "Creating SDK folder: ${proj}.sdk" 137 | file mkdir ${proj}.sdk 138 | } 139 | set mmi_file [glob -nocomplain -directory ${proj}.runs/${get_impl} *.mmi] 140 | if {$mmi_file != ""} { 141 | lappend file_list $mmi_file 142 | } 143 | set bit_file [glob -nocomplain -directory ${proj}.runs/${get_impl} *.bit] 144 | if {$bit_file != ""} { 145 | lappend file_list $bit_file 146 | } 147 | set hwdef_file [glob -nocomplain -directory ${proj}.runs/${get_impl} *.hwdef] 148 | if {$hwdef_file != ""} { 149 | lappend file_list $hwdef_file 150 | } 151 | write_sysdef -force -meminfo $mmi_file -hwdef $hwdef_file -bitfile $bit_file -file ${proj}.sdk/test.hdf 152 | puts "Creating HDF file containing" 153 | for {set i 0} {$i <= [llength $file_list]} {incr i} { 154 | puts [lindex $file_list $i] 155 | } 156 | } 157 | -------------------------------------------------------------------------------- /de10lite/scr1/de10lite_scr1.qpf: -------------------------------------------------------------------------------- 1 | 2 | DATE = "13:36:13 August 25, 2017" 3 | QUARTUS_VERSION = "16.0.0" 4 | 5 | # Revisions 6 | PROJECT_REVISION = "de10lite_scr1" -------------------------------------------------------------------------------- /de10lite/scr1/de10lite_scr1.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************** 2 | # Clocks 3 | #************************************************************** 4 | create_clock -name MAX10_CLK2_50 -period 20 [get_ports {MAX10_CLK2_50}] 5 | create_clock -name JTAG_TCK -period 200 [get_ports {JTAG_TCK}] 6 | create_clock -name CLK_SDRAM_EXT_VIRT -period 10 7 | 8 | create_generated_clock -source MAX10_CLK2_50 \ 9 | -divide_by 5 \ 10 | -multiply_by 2 \ 11 | -duty_cycle 50.00 \ 12 | -name CPU_CLK \ 13 | { i_soc|sys_pll|sd1|pll7|clk[0] } 14 | 15 | create_generated_clock -source MAX10_CLK2_50 \ 16 | -multiply_by 2 \ 17 | -duty_cycle 50.00 \ 18 | -name CLK_SDRAM \ 19 | { i_soc|sys_pll|sd1|pll7|clk[1] } 20 | 21 | create_generated_clock -source MAX10_CLK2_50 \ 22 | -multiply_by 2 \ 23 | -phase 108.00 \ 24 | -duty_cycle 50.00 \ 25 | -name CLK_SDRAM_EXT \ 26 | { i_soc|sys_pll|sd1|pll7|clk[2] } 27 | 28 | derive_pll_clocks -create_base_clocks 29 | derive_clock_uncertainty 30 | 31 | 32 | 33 | set_clock_groups -asynchronous -group {MAX10_CLK2_50} 34 | set_clock_groups -asynchronous -group {JTAG_TCK} 35 | set_clock_groups -asynchronous -group {CPU_CLK} 36 | set_clock_groups -asynchronous -group {CLK_SDRAM_EXT CLK_SDRAM_EXT_VIRT} 37 | 38 | #************************************************************** 39 | # False Path 40 | #************************************************************** 41 | set_false_path -to [get_ports {DRAM_CLK}] 42 | set_false_path -to [get_ports {HEX*}] 43 | set_false_path -to [get_ports {LEDR*}] 44 | set_false_path -to [get_ports {UART_TXD}] 45 | set_false_path -from [get_ports {UART_RXD}] 46 | set_false_path -from [get_ports {JTAG_SRST_N}] 47 | set_false_path -from [get_ports {JTAG_TRST_N}] 48 | set_false_path -from [get_ports {KEY*}] 49 | set_false_path -from [get_ports {SW*}] 50 | 51 | #************************************************************** 52 | # Set Input Delay 53 | #************************************************************** 54 | # suppose +- 100 ps skew 55 | # Board Delay (Data) + Propagation Delay - Board Delay (Clock) 56 | # max 5.4(max) +0.4(trace delay) +0.1 = 5.9 57 | # min 2.7(min) +0.4(trace delay) -0.1 = 3.0 58 | set_input_delay -max -clock CLK_SDRAM_EXT_VIRT 5.9 [get_ports DRAM_DQ*] 59 | set_input_delay -min -clock CLK_SDRAM_EXT_VIRT 3.0 [get_ports DRAM_DQ*] 60 | 61 | #shift-window 62 | set_multicycle_path -from [get_clocks {CLK_SDRAM_EXT_VIRT}] \ 63 | -to [get_clocks {MAX10_CLK2_50}] \ 64 | -setup 2 65 | 66 | set_input_delay -add_delay -clock_fall -clock JTAG_TCK -max 5 [get_ports {JTAG_TMS JTAG_TDI}] 67 | set_input_delay -add_delay -clock_fall -clock JTAG_TCK -min 0 [get_ports {JTAG_TMS JTAG_TDI}] 68 | 69 | #************************************************************** 70 | # Set Output Delay 71 | #************************************************************** 72 | # suppose +- 100 ps skew 73 | # max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device) 74 | # min : Board Delay (Data) - Board Delay (Clock) - th (External Device) 75 | # max 1.5+0.1 =1.6 76 | # min -0.8-0.1 = 0.9 77 | set_output_delay -max -clock CLK_SDRAM_EXT_VIRT 1.6 [get_ports {DRAM_DQ* DRAM_*DQM}] 78 | set_output_delay -min -clock CLK_SDRAM_EXT_VIRT -0.9 [get_ports {DRAM_DQ* DRAM_*DQM}] 79 | set_output_delay -max -clock CLK_SDRAM_EXT_VIRT 1.6 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}] 80 | set_output_delay -min -clock CLK_SDRAM_EXT_VIRT -0.9 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}] 81 | 82 | set_output_delay -add_delay -clock_fall -clock JTAG_TCK -max 5 [get_ports {JTAG_TDO}] 83 | set_output_delay -add_delay -clock_fall -clock JTAG_TCK -min 0 [get_ports {JTAG_TDO}] -------------------------------------------------------------------------------- /de10lite/scr1/de10lite_scr1.srf: -------------------------------------------------------------------------------- 1 | { "" "" "" "De10lite_qsys.uart: uart.RS_232_Modem must be exported, or connected to a matching conduit." { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""} 2 | { "" "" "" "*" { } { } 0 12250 "" 0 0 "Design Software" 0 -1 0 ""} 3 | { "" "" "" "*" { } { } 0 12021 "" 0 0 "Design Software" 0 -1 0 ""} 4 | { "" "" "" "*" { } { } 0 10281 "" 0 0 "Design Software" 0 -1 0 ""} 5 | { "" "" "" "*" { } { } 0 12128 "" 0 0 "Design Software" 0 -1 0 ""} 6 | { "" "" "" "*" { } { } 0 12130 "" 0 0 "Design Software" 0 -1 0 ""} 7 | { "" "" "" "*" { } { } 0 10264 "" 0 0 "Design Software" 0 -1 0 ""} 8 | { "" "" "" "*" { } { } 0 12133 "" 0 0 "Design Software" 0 -1 0 ""} 9 | { "" "" "" "*" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""} 10 | { "" "" "" "*" { } { } 0 176250 "" 0 0 "Design Software" 0 -1 0 ""} 11 | { "" "" "" "*" { } { } 0 176251 "" 0 0 "Design Software" 0 -1 0 ""} 12 | { "" "" "" "*" { } { } 0 13024 "" 0 0 "Design Software" 0 -1 0 ""} 13 | { "" "" "" "*" { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} 14 | { "" "" "" "*" { } { } 0 10648 "" 0 0 "Design Software" 0 -1 0 ""} 15 | { "" "" "" "altera_merlin_width_adapter.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} 16 | { "" "" "" "altera_error_response_slave.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} 17 | { "" "" "" "altera_merlin_axi_slave_ni.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} 18 | { "" "" "" "de10lite_qsys_sdram.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} 19 | { "" "" "" "uart_regs.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} 20 | { "" "" "" "uart_receiver.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} 21 | { "" "" "" "uart_wb.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} 22 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/ahb_avalon_bridge.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 2 | /// @file 3 | /// @brief Avalon to AMBA AHB bridge 4 | /// 5 | 6 | module ahb_avalon_bridge 7 | ( 8 | // avalon master side 9 | input logic clk, 10 | input logic reset_n, 11 | output logic [31:0] address, 12 | output logic write, 13 | output logic read, 14 | output logic [ 3:0] byteenable, 15 | output logic [31:0] writedata, 16 | input logic waitrequest, 17 | input logic readdatavalid, 18 | input logic [31:0] readdata, 19 | input logic [1:0] response, 20 | 21 | // ahb slave side 22 | output logic [31:0] HRDATA, 23 | output logic HRESP, 24 | input logic [ 2:0] HSIZE, 25 | input logic [ 1:0] HTRANS, 26 | input logic [ 3:0] HPROT, 27 | input logic [31:0] HADDR, 28 | input logic [31:0] HWDATA, 29 | input logic HWRITE, 30 | output logic HREADY 31 | ); 32 | 33 | typedef enum logic [1:0] { 34 | IDLE, 35 | WRITE, 36 | READ, 37 | READ_STALL 38 | } type_state_e; 39 | 40 | type_state_e state; 41 | type_state_e nextState; 42 | logic [31:0] haddr_reg; 43 | 44 | 45 | 46 | 47 | always_ff @ (posedge clk, negedge reset_n) 48 | begin 49 | if (!reset_n) state <= IDLE; 50 | else state <= nextState; 51 | end 52 | 53 | always_ff @ (posedge clk, negedge reset_n) 54 | begin 55 | if (!reset_n) begin 56 | haddr_reg <= 32'h0; 57 | end 58 | else if ((HTRANS == 2'b10) | (HTRANS == 2'b11)) begin 59 | haddr_reg <= HADDR; 60 | end 61 | end 62 | 63 | always_ff @ (posedge clk, negedge reset_n) 64 | begin 65 | if (!reset_n) begin 66 | byteenable = 4'b1111; 67 | end 68 | else if ((HTRANS == 2'b10) | (HTRANS == 2'b11)) begin 69 | case ({HADDR[1:0],HSIZE}) 70 | {2'b00,SCR1_HSIZE_8B }: byteenable = 4'b0001; 71 | {2'b01,SCR1_HSIZE_8B }: byteenable = 4'b0010; 72 | {2'b10,SCR1_HSIZE_8B }: byteenable = 4'b0100; 73 | {2'b11,SCR1_HSIZE_8B }: byteenable = 4'b1000; 74 | {2'b00,SCR1_HSIZE_16B}: byteenable = 4'b0011; 75 | {2'b10,SCR1_HSIZE_16B}: byteenable = 4'b1100; 76 | {2'b00,SCR1_HSIZE_32B}: byteenable = 4'b1111; 77 | default: byteenable = 4'b0000; 78 | endcase 79 | end 80 | end 81 | 82 | assign writedata = HWDATA; 83 | assign HRDATA = readdata; 84 | assign address = haddr_reg; 85 | assign HRESP = response != 2'b00; 86 | 87 | always_comb 88 | begin 89 | nextState = state; 90 | HREADY = 1'b1; 91 | case (state) 92 | IDLE: begin 93 | if ((HTRANS == 2'b10) | (HTRANS == 2'b11)) begin 94 | if (HWRITE) begin 95 | nextState = WRITE; 96 | end 97 | else begin 98 | nextState = READ; 99 | end 100 | end 101 | end 102 | 103 | WRITE: begin 104 | if (!waitrequest) begin 105 | if ((HTRANS == 2'b10) | (HTRANS == 2'b11)) begin 106 | if (!HWRITE) begin 107 | nextState = READ; 108 | end 109 | end 110 | else begin 111 | nextState = IDLE; 112 | end 113 | end 114 | else begin 115 | HREADY = 1'b0; 116 | end 117 | end 118 | 119 | READ: begin 120 | if (readdatavalid) begin 121 | if ((HTRANS == 2'b10) | (HTRANS == 2'b11)) begin 122 | if (HWRITE) begin 123 | nextState = WRITE; 124 | end 125 | end 126 | else begin 127 | nextState = IDLE; 128 | end 129 | end 130 | else begin 131 | HREADY = 1'b0; 132 | if (!waitrequest) begin 133 | nextState = READ_STALL; 134 | end 135 | end 136 | end 137 | 138 | READ_STALL: begin 139 | if (readdatavalid) begin 140 | if ((HTRANS == 2'b10) | (HTRANS == 2'b11)) begin 141 | if (HWRITE) begin 142 | nextState = WRITE; 143 | end 144 | else begin 145 | nextState = READ; 146 | end 147 | end 148 | else begin 149 | nextState = IDLE; 150 | end 151 | end 152 | else begin 153 | HREADY = 1'b0; 154 | end 155 | end 156 | endcase 157 | end 158 | 159 | assign write = (state == WRITE); 160 | assign read = (state == READ); 161 | 162 | endmodule : ahb_avalon_bridge 163 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/scr1_arch_custom.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_ARCH_CUSTOM_SVH 2 | `define SCR1_ARCH_CUSTOM_SVH 3 | /// Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 4 | /// @file 5 | /// @brief Custom Architecture Parameters File 6 | /// 7 | 8 | // Current FPGA build identificators, can be modified 9 | `define SCR1_PTFM_SOC_ID 32'h21041500 10 | `define SCR1_PTFM_BLD_ID 32'h22011203 11 | `define SCR1_PTFM_CORE_CLK_FREQ 32'd20000000 12 | 13 | //`define SCR1_TRGT_FPGA_XILINX // Uncomment if target platform is Xilinx FPGAs 14 | `define SCR1_TRGT_FPGA_INTEL // Uncomment if target platform is Intel FPGAs AND ---> 15 | `define SCR1_TRGT_FPGA_INTEL_MAX10 // ---> Uncomment if target platform is Intel MAX 10 FPGAs 16 | //`define SCR1_TRGT_FPGA_INTEL_ARRIAV // ---> Uncomment if target platform is Intel Arria V FPGAs 17 | 18 | // Uncomment to select recommended core architecture configurations 19 | // Default SCR1 FPGA SDK created for RV32IMC_MAX config 20 | 21 | `define SCR1_CFG_RV32IMC_MAX 22 | //`define SCR1_CFG_RV32IC_BASE 23 | //`define SCR1_CFG_RV32EC_MIN 24 | 25 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_RST_VECTOR = 'hFFFFFF00; // Reset vector 26 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_MTVEC_BASE = 'hFFFFFF80; // MTVEC BASE field reset value 27 | 28 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_MASK = 'hFFFF0000; // TCM mask and size 29 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_PATTERN = 'hF0000000; // TCM address match pattern 30 | 31 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_MASK = 'hFFFFFFE0; // Timer mask (should be 0xFFFFFFE0) 32 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_PATTERN = 'hF0040000; // Timer address match pattern 33 | 34 | `endif // SCR1_ARCH_CUSTOM_SVH 35 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/raminfr.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// raminfr.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// Inferrable Distributed RAM for FIFOs //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None . //// 22 | //// //// 23 | //// To Do: //// 24 | //// Nothing so far. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - gorban@opencores.org //// 28 | //// - Jacob Gorban //// 29 | //// //// 30 | //// Created: 2002/07/22 //// 31 | //// Last Updated: 2002/07/22 //// 32 | //// (See log for the revision history) //// 33 | //// //// 34 | //// //// 35 | ////////////////////////////////////////////////////////////////////// 36 | //// //// 37 | //// Copyright (C) 2000, 2001 Authors //// 38 | //// //// 39 | //// This source file may be used and distributed without //// 40 | //// restriction provided that this copyright statement is not //// 41 | //// removed from the file and that any derivative work contains //// 42 | //// the original copyright notice and the associated disclaimer. //// 43 | //// //// 44 | //// This source file is free software; you can redistribute it //// 45 | //// and/or modify it under the terms of the GNU Lesser General //// 46 | //// Public License as published by the Free Software Foundation; //// 47 | //// either version 2.1 of the License, or (at your option) any //// 48 | //// later version. //// 49 | //// //// 50 | //// This source is distributed in the hope that it will be //// 51 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 52 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 53 | //// PURPOSE. See the GNU Lesser General Public License for more //// 54 | //// details. //// 55 | //// //// 56 | //// You should have received a copy of the GNU Lesser General //// 57 | //// Public License along with this source; if not, download it //// 58 | //// from http://www.opencores.org/lgpl.shtml //// 59 | //// //// 60 | ////////////////////////////////////////////////////////////////////// 61 | // 62 | // CVS Revision History 63 | // 64 | // $Log: not supported by cvs2svn $ 65 | // Revision 1.1 2002/07/22 23:02:23 gorban 66 | // Bug Fixes: 67 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 68 | // Problem reported by Kenny.Tung. 69 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 70 | // 71 | // Improvements: 72 | // * Made FIFO's as general inferrable memory where possible. 73 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 74 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 75 | // 76 | // * Added optional baudrate output (baud_o). 77 | // This is identical to BAUDOUT* signal on 16550 chip. 78 | // It outputs 16xbit_clock_rate - the divided clock. 79 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 80 | // 81 | 82 | //Following is the Verilog code for a dual-port RAM with asynchronous read. 83 | module raminfr 84 | (clk, we, a, dpra, di, dpo); 85 | 86 | parameter addr_width = 4; 87 | parameter data_width = 8; 88 | parameter depth = 16; 89 | 90 | input clk; 91 | input we; 92 | input [addr_width-1:0] a; 93 | input [addr_width-1:0] dpra; 94 | input [data_width-1:0] di; 95 | //output [data_width-1:0] spo; 96 | output [data_width-1:0] dpo; 97 | reg [data_width-1:0] ram [depth-1:0]; 98 | 99 | wire [data_width-1:0] dpo; 100 | wire [data_width-1:0] di; 101 | wire [addr_width-1:0] a; 102 | wire [addr_width-1:0] dpra; 103 | 104 | always @(posedge clk) begin 105 | if (we) 106 | ram[a] <= di; 107 | end 108 | // assign spo = ram[a]; 109 | assign dpo = ram[dpra]; 110 | endmodule 111 | 112 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/timescale.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// timescale.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// Defines of the Core //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None //// 22 | //// //// 23 | //// To Do: //// 24 | //// Nothing. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - gorban@opencores.org //// 28 | //// - Jacob Gorban //// 29 | //// - Igor Mohor (igorm@opencores.org) //// 30 | //// //// 31 | //// Created: 2001/05/12 //// 32 | //// Last Updated: 2001/05/17 //// 33 | //// (See log for the revision history) //// 34 | //// //// 35 | //// //// 36 | ////////////////////////////////////////////////////////////////////// 37 | //// //// 38 | //// Copyright (C) 2000, 2001 Authors //// 39 | //// //// 40 | //// This source file may be used and distributed without //// 41 | //// restriction provided that this copyright statement is not //// 42 | //// removed from the file and that any derivative work contains //// 43 | //// the original copyright notice and the associated disclaimer. //// 44 | //// //// 45 | //// This source file is free software; you can redistribute it //// 46 | //// and/or modify it under the terms of the GNU Lesser General //// 47 | //// Public License as published by the Free Software Foundation; //// 48 | //// either version 2.1 of the License, or (at your option) any //// 49 | //// later version. //// 50 | //// //// 51 | //// This source is distributed in the hope that it will be //// 52 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 53 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 54 | //// PURPOSE. See the GNU Lesser General Public License for more //// 55 | //// details. //// 56 | //// //// 57 | //// You should have received a copy of the GNU Lesser General //// 58 | //// Public License along with this source; if not, download it //// 59 | //// from http://www.opencores.org/lgpl.shtml //// 60 | //// //// 61 | ////////////////////////////////////////////////////////////////////// 62 | // Timescale define 63 | 64 | `timescale 1ns/10ps 65 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/uart_defines.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_defines.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// Defines of the Core //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None //// 22 | //// //// 23 | //// To Do: //// 24 | //// Nothing. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - gorban@opencores.org //// 28 | //// - Jacob Gorban //// 29 | //// - Igor Mohor (igorm@opencores.org) //// 30 | //// //// 31 | //// Created: 2001/05/12 //// 32 | //// Last Updated: 2001/05/17 //// 33 | //// (See log for the revision history) //// 34 | //// //// 35 | //// //// 36 | ////////////////////////////////////////////////////////////////////// 37 | //// //// 38 | //// Copyright (C) 2000, 2001 Authors //// 39 | //// //// 40 | //// This source file may be used and distributed without //// 41 | //// restriction provided that this copyright statement is not //// 42 | //// removed from the file and that any derivative work contains //// 43 | //// the original copyright notice and the associated disclaimer. //// 44 | //// //// 45 | //// This source file is free software; you can redistribute it //// 46 | //// and/or modify it under the terms of the GNU Lesser General //// 47 | //// Public License as published by the Free Software Foundation; //// 48 | //// either version 2.1 of the License, or (at your option) any //// 49 | //// later version. //// 50 | //// //// 51 | //// This source is distributed in the hope that it will be //// 52 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 53 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 54 | //// PURPOSE. See the GNU Lesser General Public License for more //// 55 | //// details. //// 56 | //// //// 57 | //// You should have received a copy of the GNU Lesser General //// 58 | //// Public License along with this source; if not, download it //// 59 | //// from http://www.opencores.org/lgpl.shtml //// 60 | //// //// 61 | ////////////////////////////////////////////////////////////////////// 62 | // 63 | // CVS Revision History 64 | // 65 | // $Log: not supported by cvs2svn $ 66 | // Revision 1.13 2003/06/11 16:37:47 gorban 67 | // This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. 68 | // 69 | // Revision 1.12 2002/07/22 23:02:23 gorban 70 | // Bug Fixes: 71 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 72 | // Problem reported by Kenny.Tung. 73 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 74 | // 75 | // Improvements: 76 | // * Made FIFO's as general inferrable memory where possible. 77 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 78 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 79 | // 80 | // * Added optional baudrate output (baud_o). 81 | // This is identical to BAUDOUT* signal on 16550 chip. 82 | // It outputs 16xbit_clock_rate - the divided clock. 83 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 84 | // 85 | // Revision 1.10 2001/12/11 08:55:40 mohor 86 | // Scratch register define added. 87 | // 88 | // Revision 1.9 2001/12/03 21:44:29 gorban 89 | // Updated specification documentation. 90 | // Added full 32-bit data bus interface, now as default. 91 | // Address is 5-bit wide in 32-bit data bus mode. 92 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. 93 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. 94 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. 95 | // My small test bench is modified to work with 32-bit mode. 96 | // 97 | // Revision 1.8 2001/11/26 21:38:54 gorban 98 | // Lots of fixes: 99 | // Break condition wasn't handled correctly at all. 100 | // LSR bits could lose their values. 101 | // LSR value after reset was wrong. 102 | // Timing of THRE interrupt signal corrected. 103 | // LSR bit 0 timing corrected. 104 | // 105 | // Revision 1.7 2001/08/24 21:01:12 mohor 106 | // Things connected to parity changed. 107 | // Clock devider changed. 108 | // 109 | // Revision 1.6 2001/08/23 16:05:05 mohor 110 | // Stop bit bug fixed. 111 | // Parity bug fixed. 112 | // WISHBONE read cycle bug fixed, 113 | // OE indicator (Overrun Error) bug fixed. 114 | // PE indicator (Parity Error) bug fixed. 115 | // Register read bug fixed. 116 | // 117 | // Revision 1.5 2001/05/31 20:08:01 gorban 118 | // FIFO changes and other corrections. 119 | // 120 | // Revision 1.4 2001/05/21 19:12:02 gorban 121 | // Corrected some Linter messages. 122 | // 123 | // Revision 1.3 2001/05/17 18:34:18 gorban 124 | // First 'stable' release. Should be sythesizable now. Also added new header. 125 | // 126 | // Revision 1.0 2001-05-17 21:27:11+02 jacob 127 | // Initial revision 128 | // 129 | // 130 | 131 | // remove comments to restore to use the new version with 8 data bit interface 132 | // in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place 133 | // also, in 8-bit version there'll be no debugging features included 134 | // CAUTION: doesn't work with current version of OR1200 135 | `define DATA_BUS_WIDTH_8 136 | 137 | `ifdef DATA_BUS_WIDTH_8 138 | `define UART_ADDR_WIDTH 3 139 | `define UART_DATA_WIDTH 8 140 | `else 141 | `define UART_ADDR_WIDTH 5 142 | `define UART_DATA_WIDTH 32 143 | `endif 144 | 145 | // Uncomment this if you want your UART to have 146 | // 16xBaudrate output port. 147 | // If defined, the enable signal will be used to drive baudrate_o signal 148 | // It's frequency is 16xbaudrate 149 | 150 | // `define UART_HAS_BAUDRATE_OUTPUT 151 | 152 | // Register addresses 153 | `define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer 154 | `define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter 155 | `define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable 156 | `define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification 157 | `define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control 158 | `define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control 159 | `define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control 160 | `define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status 161 | `define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status 162 | `define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register 163 | `define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2) 164 | `define UART_REG_DL2 `UART_ADDR_WIDTH'd1 165 | 166 | // Interrupt Enable register bits 167 | `define UART_IE_RDA 0 // Received Data available interrupt 168 | `define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt 169 | `define UART_IE_RLS 2 // Receiver Line Status Interrupt 170 | `define UART_IE_MS 3 // Modem Status Interrupt 171 | 172 | // Interrupt Identification register bits 173 | `define UART_II_IP 0 // Interrupt pending when 0 174 | `define UART_II_II 3:1 // Interrupt identification 175 | 176 | // Interrupt identification values for bits 3:1 177 | `define UART_II_RLS 3'b011 // Receiver Line Status 178 | `define UART_II_RDA 3'b010 // Receiver Data available 179 | `define UART_II_TI 3'b110 // Timeout Indication 180 | `define UART_II_THRE 3'b001 // Transmitter Holding Register empty 181 | `define UART_II_MS 3'b000 // Modem Status 182 | 183 | // FIFO Control Register bits 184 | `define UART_FC_TL 1:0 // Trigger level 185 | 186 | // FIFO trigger level values 187 | `define UART_FC_1 2'b00 188 | `define UART_FC_4 2'b01 189 | `define UART_FC_8 2'b10 190 | `define UART_FC_14 2'b11 191 | 192 | // Line Control register bits 193 | `define UART_LC_BITS 1:0 // bits in character 194 | `define UART_LC_SB 2 // stop bits 195 | `define UART_LC_PE 3 // parity enable 196 | `define UART_LC_EP 4 // even parity 197 | `define UART_LC_SP 5 // stick parity 198 | `define UART_LC_BC 6 // Break control 199 | `define UART_LC_DL 7 // Divisor Latch access bit 200 | 201 | // Modem Control register bits 202 | `define UART_MC_DTR 0 203 | `define UART_MC_RTS 1 204 | `define UART_MC_OUT1 2 205 | `define UART_MC_OUT2 3 206 | `define UART_MC_LB 4 // Loopback mode 207 | 208 | // Line Status Register bits 209 | `define UART_LS_DR 0 // Data ready 210 | `define UART_LS_OE 1 // Overrun Error 211 | `define UART_LS_PE 2 // Parity Error 212 | `define UART_LS_FE 3 // Framing Error 213 | `define UART_LS_BI 4 // Break interrupt 214 | `define UART_LS_TFE 5 // Transmit FIFO is empty 215 | `define UART_LS_TE 6 // Transmitter Empty indicator 216 | `define UART_LS_EI 7 // Error indicator 217 | 218 | // Modem Status Register bits 219 | `define UART_MS_DCTS 0 // Delta signals 220 | `define UART_MS_DDSR 1 221 | `define UART_MS_TERI 2 222 | `define UART_MS_DDCD 3 223 | `define UART_MS_CCTS 4 // Complement signals 224 | `define UART_MS_CDSR 5 225 | `define UART_MS_CRI 6 226 | `define UART_MS_CDCD 7 227 | 228 | // FIFO parameter defines 229 | 230 | `define UART_FIFO_WIDTH 8 231 | `define UART_FIFO_DEPTH 16 232 | `define UART_FIFO_POINTER_W 4 233 | `define UART_FIFO_COUNTER_W 5 234 | // receiver fifo has width 11 because it has break, parity and framing error bits 235 | `define UART_FIFO_REC_WIDTH 11 236 | 237 | 238 | `define VERBOSE_WB 0 // All activity on the WISHBONE is recorded 239 | `define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register) 240 | `define FAST_TEST 1 // 64/1024 packets are sent 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/uart_rfifo.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_rfifo.v (Modified from uart_fifo.v) //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core receiver FIFO //// 19 | //// //// 20 | //// To Do: //// 21 | //// Nothing. //// 22 | //// //// 23 | //// Author(s): //// 24 | //// - gorban@opencores.org //// 25 | //// - Jacob Gorban //// 26 | //// - Igor Mohor (igorm@opencores.org) //// 27 | //// //// 28 | //// Created: 2001/05/12 //// 29 | //// Last Updated: 2002/07/22 //// 30 | //// (See log for the revision history) //// 31 | //// //// 32 | //// //// 33 | ////////////////////////////////////////////////////////////////////// 34 | //// //// 35 | //// Copyright (C) 2000, 2001 Authors //// 36 | //// //// 37 | //// This source file may be used and distributed without //// 38 | //// restriction provided that this copyright statement is not //// 39 | //// removed from the file and that any derivative work contains //// 40 | //// the original copyright notice and the associated disclaimer. //// 41 | //// //// 42 | //// This source file is free software; you can redistribute it //// 43 | //// and/or modify it under the terms of the GNU Lesser General //// 44 | //// Public License as published by the Free Software Foundation; //// 45 | //// either version 2.1 of the License, or (at your option) any //// 46 | //// later version. //// 47 | //// //// 48 | //// This source is distributed in the hope that it will be //// 49 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 50 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 51 | //// PURPOSE. See the GNU Lesser General Public License for more //// 52 | //// details. //// 53 | //// //// 54 | //// You should have received a copy of the GNU Lesser General //// 55 | //// Public License along with this source; if not, download it //// 56 | //// from http://www.opencores.org/lgpl.shtml //// 57 | //// //// 58 | ////////////////////////////////////////////////////////////////////// 59 | // 60 | // CVS Revision History 61 | // 62 | // $Log: not supported by cvs2svn $ 63 | // Revision 1.3 2003/06/11 16:37:47 gorban 64 | // This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. 65 | // 66 | // Revision 1.2 2002/07/29 21:16:18 gorban 67 | // The uart_defines.v file is included again in sources. 68 | // 69 | // Revision 1.1 2002/07/22 23:02:23 gorban 70 | // Bug Fixes: 71 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 72 | // Problem reported by Kenny.Tung. 73 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 74 | // 75 | // Improvements: 76 | // * Made FIFO's as general inferrable memory where possible. 77 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 78 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 79 | // 80 | // * Added optional baudrate output (baud_o). 81 | // This is identical to BAUDOUT* signal on 16550 chip. 82 | // It outputs 16xbit_clock_rate - the divided clock. 83 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 84 | // 85 | // Revision 1.16 2001/12/20 13:25:46 mohor 86 | // rx push changed to be only one cycle wide. 87 | // 88 | // Revision 1.15 2001/12/18 09:01:07 mohor 89 | // Bug that was entered in the last update fixed (rx state machine). 90 | // 91 | // Revision 1.14 2001/12/17 14:46:48 mohor 92 | // overrun signal was moved to separate block because many sequential lsr 93 | // reads were preventing data from being written to rx fifo. 94 | // underrun signal was not used and was removed from the project. 95 | // 96 | // Revision 1.13 2001/11/26 21:38:54 gorban 97 | // Lots of fixes: 98 | // Break condition wasn't handled correctly at all. 99 | // LSR bits could lose their values. 100 | // LSR value after reset was wrong. 101 | // Timing of THRE interrupt signal corrected. 102 | // LSR bit 0 timing corrected. 103 | // 104 | // Revision 1.12 2001/11/08 14:54:23 mohor 105 | // Comments in Slovene language deleted, few small fixes for better work of 106 | // old tools. IRQs need to be fix. 107 | // 108 | // Revision 1.11 2001/11/07 17:51:52 gorban 109 | // Heavily rewritten interrupt and LSR subsystems. 110 | // Many bugs hopefully squashed. 111 | // 112 | // Revision 1.10 2001/10/20 09:58:40 gorban 113 | // Small synopsis fixes 114 | // 115 | // Revision 1.9 2001/08/24 21:01:12 mohor 116 | // Things connected to parity changed. 117 | // Clock devider changed. 118 | // 119 | // Revision 1.8 2001/08/24 08:48:10 mohor 120 | // FIFO was not cleared after the data was read bug fixed. 121 | // 122 | // Revision 1.7 2001/08/23 16:05:05 mohor 123 | // Stop bit bug fixed. 124 | // Parity bug fixed. 125 | // WISHBONE read cycle bug fixed, 126 | // OE indicator (Overrun Error) bug fixed. 127 | // PE indicator (Parity Error) bug fixed. 128 | // Register read bug fixed. 129 | // 130 | // Revision 1.3 2001/05/31 20:08:01 gorban 131 | // FIFO changes and other corrections. 132 | // 133 | // Revision 1.3 2001/05/27 17:37:48 gorban 134 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. 135 | // 136 | // Revision 1.2 2001/05/17 18:34:18 gorban 137 | // First 'stable' release. Should be sythesizable now. Also added new header. 138 | // 139 | // Revision 1.0 2001-05-17 21:27:12+02 jacob 140 | // Initial revision 141 | // 142 | // 143 | 144 | // synopsys translate_off 145 | `include "timescale.v" 146 | // synopsys translate_on 147 | 148 | `include "uart_defines.v" 149 | 150 | module uart_rfifo (clk, 151 | wb_rst_i, data_in, data_out, 152 | // Control signals 153 | push, // push strobe, active high 154 | pop, // pop strobe, active high 155 | // status signals 156 | overrun, 157 | count, 158 | error_bit, 159 | fifo_reset, 160 | reset_status 161 | ); 162 | 163 | 164 | // FIFO parameters 165 | parameter fifo_width = `UART_FIFO_WIDTH; 166 | parameter fifo_depth = `UART_FIFO_DEPTH; 167 | parameter fifo_pointer_w = `UART_FIFO_POINTER_W; 168 | parameter fifo_counter_w = `UART_FIFO_COUNTER_W; 169 | 170 | input clk; 171 | input wb_rst_i; 172 | input push; 173 | input pop; 174 | input [fifo_width-1:0] data_in; 175 | input fifo_reset; 176 | input reset_status; 177 | 178 | output [fifo_width-1:0] data_out; 179 | output overrun; 180 | output [fifo_counter_w-1:0] count; 181 | output error_bit; 182 | 183 | wire [fifo_width-1:0] data_out; 184 | wire [7:0] data8_out; 185 | // flags FIFO 186 | reg [2:0] fifo[fifo_depth-1:0]; 187 | 188 | // FIFO pointers 189 | reg [fifo_pointer_w-1:0] top; 190 | reg [fifo_pointer_w-1:0] bottom; 191 | 192 | reg [fifo_counter_w-1:0] count; 193 | reg overrun; 194 | 195 | wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; 196 | 197 | raminfr #(fifo_pointer_w,8,fifo_depth) rfifo 198 | (.clk(clk), 199 | .we(push), 200 | .a(top), 201 | .dpra(bottom), 202 | .di(data_in[fifo_width-1:fifo_width-8]), 203 | .dpo(data8_out) 204 | ); 205 | 206 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 207 | begin 208 | if (wb_rst_i) 209 | begin 210 | top <= #1 0; 211 | bottom <= #1 1'b0; 212 | count <= #1 0; 213 | fifo[0] <= #1 0; 214 | fifo[1] <= #1 0; 215 | fifo[2] <= #1 0; 216 | fifo[3] <= #1 0; 217 | fifo[4] <= #1 0; 218 | fifo[5] <= #1 0; 219 | fifo[6] <= #1 0; 220 | fifo[7] <= #1 0; 221 | fifo[8] <= #1 0; 222 | fifo[9] <= #1 0; 223 | fifo[10] <= #1 0; 224 | fifo[11] <= #1 0; 225 | fifo[12] <= #1 0; 226 | fifo[13] <= #1 0; 227 | fifo[14] <= #1 0; 228 | fifo[15] <= #1 0; 229 | end 230 | else 231 | if (fifo_reset) begin 232 | top <= #1 0; 233 | bottom <= #1 1'b0; 234 | count <= #1 0; 235 | fifo[0] <= #1 0; 236 | fifo[1] <= #1 0; 237 | fifo[2] <= #1 0; 238 | fifo[3] <= #1 0; 239 | fifo[4] <= #1 0; 240 | fifo[5] <= #1 0; 241 | fifo[6] <= #1 0; 242 | fifo[7] <= #1 0; 243 | fifo[8] <= #1 0; 244 | fifo[9] <= #1 0; 245 | fifo[10] <= #1 0; 246 | fifo[11] <= #1 0; 247 | fifo[12] <= #1 0; 248 | fifo[13] <= #1 0; 249 | fifo[14] <= #1 0; 250 | fifo[15] <= #1 0; 251 | end 252 | else 253 | begin 254 | case ({push, pop}) 255 | 2'b10 : if (count0) 262 | begin 263 | fifo[bottom] <= #1 0; 264 | bottom <= #1 bottom + 1'b1; 265 | count <= #1 count - 1'b1; 266 | end 267 | 2'b11 : begin 268 | bottom <= #1 bottom + 1'b1; 269 | top <= #1 top_plus_1; 270 | fifo[top] <= #1 data_in[2:0]; 271 | end 272 | default: ; 273 | endcase 274 | end 275 | end // always 276 | 277 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 278 | begin 279 | if (wb_rst_i) 280 | overrun <= #1 1'b0; 281 | else 282 | if(fifo_reset | reset_status) 283 | overrun <= #1 1'b0; 284 | else 285 | if(push & ~pop & (count==fifo_depth)) 286 | overrun <= #1 1'b1; 287 | end // always 288 | 289 | 290 | // please note though that data_out is only valid one clock after pop signal 291 | assign data_out = {data8_out,fifo[bottom]}; 292 | 293 | // Additional logic for detection of error conditions (parity and framing) inside the FIFO 294 | // for the Line Status Register bit 7 295 | 296 | wire [2:0] word0 = fifo[0]; 297 | wire [2:0] word1 = fifo[1]; 298 | wire [2:0] word2 = fifo[2]; 299 | wire [2:0] word3 = fifo[3]; 300 | wire [2:0] word4 = fifo[4]; 301 | wire [2:0] word5 = fifo[5]; 302 | wire [2:0] word6 = fifo[6]; 303 | wire [2:0] word7 = fifo[7]; 304 | 305 | wire [2:0] word8 = fifo[8]; 306 | wire [2:0] word9 = fifo[9]; 307 | wire [2:0] word10 = fifo[10]; 308 | wire [2:0] word11 = fifo[11]; 309 | wire [2:0] word12 = fifo[12]; 310 | wire [2:0] word13 = fifo[13]; 311 | wire [2:0] word14 = fifo[14]; 312 | wire [2:0] word15 = fifo[15]; 313 | 314 | // a 1 is returned if any of the error bits in the fifo is 1 315 | assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | 316 | word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | 317 | word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | 318 | word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); 319 | 320 | endmodule 321 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/uart_sync_flops.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_sync_flops.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core receiver logic //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// None known //// 22 | //// //// 23 | //// To Do: //// 24 | //// Thourough testing. //// 25 | //// //// 26 | //// Author(s): //// 27 | //// - Andrej Erzen (andreje@flextronics.si) //// 28 | //// - Tadej Markovic (tadejm@flextronics.si) //// 29 | //// //// 30 | //// Created: 2004/05/20 //// 31 | //// Last Updated: 2004/05/20 //// 32 | //// (See log for the revision history) //// 33 | //// //// 34 | //// //// 35 | ////////////////////////////////////////////////////////////////////// 36 | //// //// 37 | //// Copyright (C) 2000, 2001 Authors //// 38 | //// //// 39 | //// This source file may be used and distributed without //// 40 | //// restriction provided that this copyright statement is not //// 41 | //// removed from the file and that any derivative work contains //// 42 | //// the original copyright notice and the associated disclaimer. //// 43 | //// //// 44 | //// This source file is free software; you can redistribute it //// 45 | //// and/or modify it under the terms of the GNU Lesser General //// 46 | //// Public License as published by the Free Software Foundation; //// 47 | //// either version 2.1 of the License, or (at your option) any //// 48 | //// later version. //// 49 | //// //// 50 | //// This source is distributed in the hope that it will be //// 51 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 52 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 53 | //// PURPOSE. See the GNU Lesser General Public License for more //// 54 | //// details. //// 55 | //// //// 56 | //// You should have received a copy of the GNU Lesser General //// 57 | //// Public License along with this source; if not, download it //// 58 | //// from http://www.opencores.org/lgpl.shtml //// 59 | //// //// 60 | ////////////////////////////////////////////////////////////////////// 61 | // 62 | // CVS Revision History 63 | // 64 | // $Log: not supported by cvs2svn $ 65 | // 66 | 67 | 68 | `include "timescale.v" 69 | 70 | 71 | module uart_sync_flops 72 | ( 73 | // internal signals 74 | rst_i, 75 | clk_i, 76 | stage1_rst_i, 77 | stage1_clk_en_i, 78 | async_dat_i, 79 | sync_dat_o 80 | ); 81 | 82 | parameter Tp = 1; 83 | parameter width = 1; 84 | parameter init_value = 1'b0; 85 | 86 | input rst_i; // reset input 87 | input clk_i; // clock input 88 | input stage1_rst_i; // synchronous reset for stage 1 FF 89 | input stage1_clk_en_i; // synchronous clock enable for stage 1 FF 90 | input [width-1:0] async_dat_i; // asynchronous data input 91 | output [width-1:0] sync_dat_o; // synchronous data output 92 | 93 | 94 | // 95 | // Interal signal declarations 96 | // 97 | 98 | reg [width-1:0] sync_dat_o; 99 | reg [width-1:0] flop_0; 100 | 101 | 102 | // first stage 103 | always @ (posedge clk_i or posedge rst_i) 104 | begin 105 | if (rst_i) 106 | flop_0 <= #Tp {width{init_value}}; 107 | else 108 | flop_0 <= #Tp async_dat_i; 109 | end 110 | 111 | // second stage 112 | always @ (posedge clk_i or posedge rst_i) 113 | begin 114 | if (rst_i) 115 | sync_dat_o <= #Tp {width{init_value}}; 116 | else if (stage1_rst_i) 117 | sync_dat_o <= #Tp {width{init_value}}; 118 | else if (stage1_clk_en_i) 119 | sync_dat_o <= #Tp flop_0; 120 | end 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/uart_tfifo.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_tfifo.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core transmitter FIFO //// 19 | //// //// 20 | //// To Do: //// 21 | //// Nothing. //// 22 | //// //// 23 | //// Author(s): //// 24 | //// - gorban@opencores.org //// 25 | //// - Jacob Gorban //// 26 | //// - Igor Mohor (igorm@opencores.org) //// 27 | //// //// 28 | //// Created: 2001/05/12 //// 29 | //// Last Updated: 2002/07/22 //// 30 | //// (See log for the revision history) //// 31 | //// //// 32 | //// //// 33 | ////////////////////////////////////////////////////////////////////// 34 | //// //// 35 | //// Copyright (C) 2000, 2001 Authors //// 36 | //// //// 37 | //// This source file may be used and distributed without //// 38 | //// restriction provided that this copyright statement is not //// 39 | //// removed from the file and that any derivative work contains //// 40 | //// the original copyright notice and the associated disclaimer. //// 41 | //// //// 42 | //// This source file is free software; you can redistribute it //// 43 | //// and/or modify it under the terms of the GNU Lesser General //// 44 | //// Public License as published by the Free Software Foundation; //// 45 | //// either version 2.1 of the License, or (at your option) any //// 46 | //// later version. //// 47 | //// //// 48 | //// This source is distributed in the hope that it will be //// 49 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 50 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 51 | //// PURPOSE. See the GNU Lesser General Public License for more //// 52 | //// details. //// 53 | //// //// 54 | //// You should have received a copy of the GNU Lesser General //// 55 | //// Public License along with this source; if not, download it //// 56 | //// from http://www.opencores.org/lgpl.shtml //// 57 | //// //// 58 | ////////////////////////////////////////////////////////////////////// 59 | // 60 | // CVS Revision History 61 | // 62 | // $Log: not supported by cvs2svn $ 63 | // Revision 1.1 2002/07/22 23:02:23 gorban 64 | // Bug Fixes: 65 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 66 | // Problem reported by Kenny.Tung. 67 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 68 | // 69 | // Improvements: 70 | // * Made FIFO's as general inferrable memory where possible. 71 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 72 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 73 | // 74 | // * Added optional baudrate output (baud_o). 75 | // This is identical to BAUDOUT* signal on 16550 chip. 76 | // It outputs 16xbit_clock_rate - the divided clock. 77 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 78 | // 79 | // Revision 1.16 2001/12/20 13:25:46 mohor 80 | // rx push changed to be only one cycle wide. 81 | // 82 | // Revision 1.15 2001/12/18 09:01:07 mohor 83 | // Bug that was entered in the last update fixed (rx state machine). 84 | // 85 | // Revision 1.14 2001/12/17 14:46:48 mohor 86 | // overrun signal was moved to separate block because many sequential lsr 87 | // reads were preventing data from being written to rx fifo. 88 | // underrun signal was not used and was removed from the project. 89 | // 90 | // Revision 1.13 2001/11/26 21:38:54 gorban 91 | // Lots of fixes: 92 | // Break condition wasn't handled correctly at all. 93 | // LSR bits could lose their values. 94 | // LSR value after reset was wrong. 95 | // Timing of THRE interrupt signal corrected. 96 | // LSR bit 0 timing corrected. 97 | // 98 | // Revision 1.12 2001/11/08 14:54:23 mohor 99 | // Comments in Slovene language deleted, few small fixes for better work of 100 | // old tools. IRQs need to be fix. 101 | // 102 | // Revision 1.11 2001/11/07 17:51:52 gorban 103 | // Heavily rewritten interrupt and LSR subsystems. 104 | // Many bugs hopefully squashed. 105 | // 106 | // Revision 1.10 2001/10/20 09:58:40 gorban 107 | // Small synopsis fixes 108 | // 109 | // Revision 1.9 2001/08/24 21:01:12 mohor 110 | // Things connected to parity changed. 111 | // Clock devider changed. 112 | // 113 | // Revision 1.8 2001/08/24 08:48:10 mohor 114 | // FIFO was not cleared after the data was read bug fixed. 115 | // 116 | // Revision 1.7 2001/08/23 16:05:05 mohor 117 | // Stop bit bug fixed. 118 | // Parity bug fixed. 119 | // WISHBONE read cycle bug fixed, 120 | // OE indicator (Overrun Error) bug fixed. 121 | // PE indicator (Parity Error) bug fixed. 122 | // Register read bug fixed. 123 | // 124 | // Revision 1.3 2001/05/31 20:08:01 gorban 125 | // FIFO changes and other corrections. 126 | // 127 | // Revision 1.3 2001/05/27 17:37:48 gorban 128 | // Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. 129 | // 130 | // Revision 1.2 2001/05/17 18:34:18 gorban 131 | // First 'stable' release. Should be sythesizable now. Also added new header. 132 | // 133 | // Revision 1.0 2001-05-17 21:27:12+02 jacob 134 | // Initial revision 135 | // 136 | // 137 | 138 | // synopsys translate_off 139 | `include "timescale.v" 140 | // synopsys translate_on 141 | 142 | `include "uart_defines.v" 143 | 144 | module uart_tfifo (clk, 145 | wb_rst_i, data_in, data_out, 146 | // Control signals 147 | push, // push strobe, active high 148 | pop, // pop strobe, active high 149 | // status signals 150 | overrun, 151 | count, 152 | fifo_reset, 153 | reset_status 154 | ); 155 | 156 | 157 | // FIFO parameters 158 | parameter fifo_width = `UART_FIFO_WIDTH; 159 | parameter fifo_depth = `UART_FIFO_DEPTH; 160 | parameter fifo_pointer_w = `UART_FIFO_POINTER_W; 161 | parameter fifo_counter_w = `UART_FIFO_COUNTER_W; 162 | 163 | input clk; 164 | input wb_rst_i; 165 | input push; 166 | input pop; 167 | input [fifo_width-1:0] data_in; 168 | input fifo_reset; 169 | input reset_status; 170 | 171 | output [fifo_width-1:0] data_out; 172 | output overrun; 173 | output [fifo_counter_w-1:0] count; 174 | 175 | wire [fifo_width-1:0] data_out; 176 | 177 | // FIFO pointers 178 | reg [fifo_pointer_w-1:0] top; 179 | reg [fifo_pointer_w-1:0] bottom; 180 | 181 | reg [fifo_counter_w-1:0] count; 182 | reg overrun; 183 | wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; 184 | 185 | raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo 186 | (.clk(clk), 187 | .we(push), 188 | .a(top), 189 | .dpra(bottom), 190 | .di(data_in), 191 | .dpo(data_out) 192 | ); 193 | 194 | 195 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 196 | begin 197 | if (wb_rst_i) 198 | begin 199 | top <= #1 0; 200 | bottom <= #1 1'b0; 201 | count <= #1 0; 202 | end 203 | else 204 | if (fifo_reset) begin 205 | top <= #1 0; 206 | bottom <= #1 1'b0; 207 | count <= #1 0; 208 | end 209 | else 210 | begin 211 | case ({push, pop}) 212 | 2'b10 : if (count0) 218 | begin 219 | bottom <= #1 bottom + 1'b1; 220 | count <= #1 count - 1'b1; 221 | end 222 | 2'b11 : begin 223 | bottom <= #1 bottom + 1'b1; 224 | top <= #1 top_plus_1; 225 | end 226 | default: ; 227 | endcase 228 | end 229 | end // always 230 | 231 | always @(posedge clk or posedge wb_rst_i) // synchronous FIFO 232 | begin 233 | if (wb_rst_i) 234 | overrun <= #1 1'b0; 235 | else 236 | if(fifo_reset | reset_status) 237 | overrun <= #1 1'b0; 238 | else 239 | if(push & (count==fifo_depth)) 240 | overrun <= #1 1'b1; 241 | end // always 242 | 243 | endmodule 244 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/uart_top.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_top.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core top level. //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// Note that transmitter and receiver instances are inside //// 22 | //// the uart_regs.v file. //// 23 | //// //// 24 | //// To Do: //// 25 | //// Nothing so far. //// 26 | //// //// 27 | //// Author(s): //// 28 | //// - gorban@opencores.org //// 29 | //// - Jacob Gorban //// 30 | //// - Igor Mohor (igorm@opencores.org) //// 31 | //// //// 32 | //// Created: 2001/05/12 //// 33 | //// Last Updated: 2001/05/17 //// 34 | //// (See log for the revision history) //// 35 | //// //// 36 | //// //// 37 | ////////////////////////////////////////////////////////////////////// 38 | //// //// 39 | //// Copyright (C) 2000, 2001 Authors //// 40 | //// //// 41 | //// This source file may be used and distributed without //// 42 | //// restriction provided that this copyright statement is not //// 43 | //// removed from the file and that any derivative work contains //// 44 | //// the original copyright notice and the associated disclaimer. //// 45 | //// //// 46 | //// This source file is free software; you can redistribute it //// 47 | //// and/or modify it under the terms of the GNU Lesser General //// 48 | //// Public License as published by the Free Software Foundation; //// 49 | //// either version 2.1 of the License, or (at your option) any //// 50 | //// later version. //// 51 | //// //// 52 | //// This source is distributed in the hope that it will be //// 53 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 54 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 55 | //// PURPOSE. See the GNU Lesser General Public License for more //// 56 | //// details. //// 57 | //// //// 58 | //// You should have received a copy of the GNU Lesser General //// 59 | //// Public License along with this source; if not, download it //// 60 | //// from http://www.opencores.org/lgpl.shtml //// 61 | //// //// 62 | ////////////////////////////////////////////////////////////////////// 63 | // 64 | // CVS Revision History 65 | // 66 | // $Log: not supported by cvs2svn $ 67 | // Revision 1.18 2002/07/22 23:02:23 gorban 68 | // Bug Fixes: 69 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 70 | // Problem reported by Kenny.Tung. 71 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 72 | // 73 | // Improvements: 74 | // * Made FIFO's as general inferrable memory where possible. 75 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 76 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 77 | // 78 | // * Added optional baudrate output (baud_o). 79 | // This is identical to BAUDOUT* signal on 16550 chip. 80 | // It outputs 16xbit_clock_rate - the divided clock. 81 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 82 | // 83 | // Revision 1.17 2001/12/19 08:40:03 mohor 84 | // Warnings fixed (unused signals removed). 85 | // 86 | // Revision 1.16 2001/12/06 14:51:04 gorban 87 | // Bug in LSR[0] is fixed. 88 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. 89 | // 90 | // Revision 1.15 2001/12/03 21:44:29 gorban 91 | // Updated specification documentation. 92 | // Added full 32-bit data bus interface, now as default. 93 | // Address is 5-bit wide in 32-bit data bus mode. 94 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. 95 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. 96 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. 97 | // My small test bench is modified to work with 32-bit mode. 98 | // 99 | // Revision 1.14 2001/11/07 17:51:52 gorban 100 | // Heavily rewritten interrupt and LSR subsystems. 101 | // Many bugs hopefully squashed. 102 | // 103 | // Revision 1.13 2001/10/20 09:58:40 gorban 104 | // Small synopsis fixes 105 | // 106 | // Revision 1.12 2001/08/25 15:46:19 gorban 107 | // Modified port names again 108 | // 109 | // Revision 1.11 2001/08/24 21:01:12 mohor 110 | // Things connected to parity changed. 111 | // Clock devider changed. 112 | // 113 | // Revision 1.10 2001/08/23 16:05:05 mohor 114 | // Stop bit bug fixed. 115 | // Parity bug fixed. 116 | // WISHBONE read cycle bug fixed, 117 | // OE indicator (Overrun Error) bug fixed. 118 | // PE indicator (Parity Error) bug fixed. 119 | // Register read bug fixed. 120 | // 121 | // Revision 1.4 2001/05/31 20:08:01 gorban 122 | // FIFO changes and other corrections. 123 | // 124 | // Revision 1.3 2001/05/21 19:12:02 gorban 125 | // Corrected some Linter messages. 126 | // 127 | // Revision 1.2 2001/05/17 18:34:18 gorban 128 | // First 'stable' release. Should be sythesizable now. Also added new header. 129 | // 130 | // Revision 1.0 2001-05-17 21:27:12+02 jacob 131 | // Initial revision 132 | // 133 | // 134 | // synopsys translate_off 135 | `include "timescale.v" 136 | // synopsys translate_on 137 | 138 | `include "uart_defines.v" 139 | 140 | module uart_top ( 141 | wb_clk_i, 142 | 143 | // Wishbone signals 144 | wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, 145 | int_o, // interrupt request 146 | 147 | // UART signals 148 | // serial input/output 149 | stx_pad_o, srx_pad_i, 150 | 151 | // modem signals 152 | rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i 153 | `ifdef UART_HAS_BAUDRATE_OUTPUT 154 | , baud_o 155 | `endif 156 | ); 157 | 158 | parameter uart_data_width = `UART_DATA_WIDTH; 159 | parameter uart_addr_width = `UART_ADDR_WIDTH; 160 | 161 | input wb_clk_i; 162 | 163 | // WISHBONE interface 164 | input wb_rst_i; 165 | input [uart_addr_width-1:0] wb_adr_i; 166 | input [uart_data_width-1:0] wb_dat_i; 167 | output [uart_data_width-1:0] wb_dat_o; 168 | input wb_we_i; 169 | input wb_stb_i; 170 | input wb_cyc_i; 171 | input [3:0] wb_sel_i; 172 | output wb_ack_o; 173 | output int_o; 174 | 175 | // UART signals 176 | input srx_pad_i; 177 | output stx_pad_o; 178 | output rts_pad_o; 179 | input cts_pad_i; 180 | output dtr_pad_o; 181 | input dsr_pad_i; 182 | input ri_pad_i; 183 | input dcd_pad_i; 184 | 185 | // optional baudrate output 186 | `ifdef UART_HAS_BAUDRATE_OUTPUT 187 | output baud_o; 188 | `endif 189 | 190 | 191 | wire stx_pad_o; 192 | wire rts_pad_o; 193 | wire dtr_pad_o; 194 | 195 | wire [uart_addr_width-1:0] wb_adr_i; 196 | wire [uart_data_width-1:0] wb_dat_i; 197 | wire [uart_data_width-1:0] wb_dat_o; 198 | 199 | wire [7:0] wb_dat8_i; // 8-bit internal data input 200 | wire [7:0] wb_dat8_o; // 8-bit internal data output 201 | wire [31:0] wb_dat32_o; // debug interface 32-bit output 202 | wire [3:0] wb_sel_i; // WISHBONE select signal 203 | wire [uart_addr_width-1:0] wb_adr_int; 204 | wire we_o; // Write enable for registers 205 | wire re_o; // Read enable for registers 206 | // 207 | // MODULE INSTANCES 208 | // 209 | 210 | `ifdef DATA_BUS_WIDTH_8 211 | `else 212 | // debug interface wires 213 | wire [3:0] ier; 214 | wire [3:0] iir; 215 | wire [1:0] fcr; 216 | wire [4:0] mcr; 217 | wire [7:0] lcr; 218 | wire [7:0] msr; 219 | wire [7:0] lsr; 220 | wire [`UART_FIFO_COUNTER_W-1:0] rf_count; 221 | wire [`UART_FIFO_COUNTER_W-1:0] tf_count; 222 | wire [2:0] tstate; 223 | wire [3:0] rstate; 224 | `endif 225 | 226 | `ifdef DATA_BUS_WIDTH_8 227 | //// WISHBONE interface module 228 | uart_wb wb_interface( 229 | .clk( wb_clk_i ), 230 | .wb_rst_i( wb_rst_i ), 231 | .wb_dat_i(wb_dat_i), 232 | .wb_dat_o(wb_dat_o), 233 | .wb_dat8_i(wb_dat8_i), 234 | .wb_dat8_o(wb_dat8_o), 235 | .wb_dat32_o(32'b0), 236 | .wb_sel_i(4'b0), 237 | .wb_we_i( wb_we_i ), 238 | .wb_stb_i( wb_stb_i ), 239 | .wb_cyc_i( wb_cyc_i ), 240 | .wb_ack_o( wb_ack_o ), 241 | .wb_adr_i(wb_adr_i), 242 | .wb_adr_int(wb_adr_int), 243 | .we_o( we_o ), 244 | .re_o(re_o) 245 | ); 246 | `else 247 | uart_wb wb_interface( 248 | .clk( wb_clk_i ), 249 | .wb_rst_i( wb_rst_i ), 250 | .wb_dat_i(wb_dat_i), 251 | .wb_dat_o(wb_dat_o), 252 | .wb_dat8_i(wb_dat8_i), 253 | .wb_dat8_o(wb_dat8_o), 254 | .wb_sel_i(wb_sel_i), 255 | .wb_dat32_o(wb_dat32_o), 256 | .wb_we_i( wb_we_i ), 257 | .wb_stb_i( wb_stb_i ), 258 | .wb_cyc_i( wb_cyc_i ), 259 | .wb_ack_o( wb_ack_o ), 260 | .wb_adr_i(wb_adr_i), 261 | .wb_adr_int(wb_adr_int), 262 | .we_o( we_o ), 263 | .re_o(re_o) 264 | ); 265 | `endif 266 | 267 | // Registers 268 | uart_regs regs( 269 | .clk( wb_clk_i ), 270 | .wb_rst_i( wb_rst_i ), 271 | .wb_addr_i( wb_adr_int ), 272 | .wb_dat_i( wb_dat8_i ), 273 | .wb_dat_o( wb_dat8_o ), 274 | .wb_we_i( we_o ), 275 | .wb_re_i(re_o), 276 | .modem_inputs( {cts_pad_i, dsr_pad_i, 277 | ri_pad_i, dcd_pad_i} ), 278 | .stx_pad_o( stx_pad_o ), 279 | .srx_pad_i( srx_pad_i ), 280 | `ifdef DATA_BUS_WIDTH_8 281 | `else 282 | // debug interface signals enabled 283 | .ier(ier), 284 | .iir(iir), 285 | .fcr(fcr), 286 | .mcr(mcr), 287 | .lcr(lcr), 288 | .msr(msr), 289 | .lsr(lsr), 290 | .rf_count(rf_count), 291 | .tf_count(tf_count), 292 | .tstate(tstate), 293 | .rstate(rstate), 294 | `endif 295 | .rts_pad_o( rts_pad_o ), 296 | .dtr_pad_o( dtr_pad_o ), 297 | .int_o( int_o ) 298 | `ifdef UART_HAS_BAUDRATE_OUTPUT 299 | , .baud_o(baud_o) 300 | `endif 301 | 302 | ); 303 | 304 | `ifdef DATA_BUS_WIDTH_8 305 | `else 306 | uart_debug_if dbg(/*AUTOINST*/ 307 | // Outputs 308 | .wb_dat32_o (wb_dat32_o[31:0]), 309 | // Inputs 310 | .wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]), 311 | .ier (ier[3:0]), 312 | .iir (iir[3:0]), 313 | .fcr (fcr[1:0]), 314 | .mcr (mcr[4:0]), 315 | .lcr (lcr[7:0]), 316 | .msr (msr[7:0]), 317 | .lsr (lsr[7:0]), 318 | .rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]), 319 | .tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]), 320 | .tstate (tstate[2:0]), 321 | .rstate (rstate[3:0])); 322 | `endif 323 | 324 | initial 325 | begin 326 | `ifdef DATA_BUS_WIDTH_8 327 | $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n"); 328 | `else 329 | $display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n"); 330 | `endif 331 | `ifdef UART_HAS_BAUDRATE_OUTPUT 332 | $display("(%m) UART INFO: Has baudrate output\n"); 333 | `else 334 | $display("(%m) UART INFO: Doesn't have baudrate output\n"); 335 | `endif 336 | end 337 | 338 | endmodule 339 | 340 | 341 | -------------------------------------------------------------------------------- /de10lite/scr1/ip/uart/uart_wb.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// uart_wb.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the "UART 16550 compatible" project //// 7 | //// http://www.opencores.org/cores/uart16550/ //// 8 | //// //// 9 | //// Documentation related to this project: //// 10 | //// - http://www.opencores.org/cores/uart16550/ //// 11 | //// //// 12 | //// Projects compatibility: //// 13 | //// - WISHBONE //// 14 | //// RS232 Protocol //// 15 | //// 16550D uart (mostly supported) //// 16 | //// //// 17 | //// Overview (main Features): //// 18 | //// UART core WISHBONE interface. //// 19 | //// //// 20 | //// Known problems (limits): //// 21 | //// Inserts one wait state on all transfers. //// 22 | //// Note affected signals and the way they are affected. //// 23 | //// //// 24 | //// To Do: //// 25 | //// Nothing. //// 26 | //// //// 27 | //// Author(s): //// 28 | //// - gorban@opencores.org //// 29 | //// - Jacob Gorban //// 30 | //// - Igor Mohor (igorm@opencores.org) //// 31 | //// //// 32 | //// Created: 2001/05/12 //// 33 | //// Last Updated: 2001/05/17 //// 34 | //// (See log for the revision history) //// 35 | //// //// 36 | //// //// 37 | ////////////////////////////////////////////////////////////////////// 38 | //// //// 39 | //// Copyright (C) 2000, 2001 Authors //// 40 | //// //// 41 | //// This source file may be used and distributed without //// 42 | //// restriction provided that this copyright statement is not //// 43 | //// removed from the file and that any derivative work contains //// 44 | //// the original copyright notice and the associated disclaimer. //// 45 | //// //// 46 | //// This source file is free software; you can redistribute it //// 47 | //// and/or modify it under the terms of the GNU Lesser General //// 48 | //// Public License as published by the Free Software Foundation; //// 49 | //// either version 2.1 of the License, or (at your option) any //// 50 | //// later version. //// 51 | //// //// 52 | //// This source is distributed in the hope that it will be //// 53 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 54 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 55 | //// PURPOSE. See the GNU Lesser General Public License for more //// 56 | //// details. //// 57 | //// //// 58 | //// You should have received a copy of the GNU Lesser General //// 59 | //// Public License along with this source; if not, download it //// 60 | //// from http://www.opencores.org/lgpl.shtml //// 61 | //// //// 62 | ////////////////////////////////////////////////////////////////////// 63 | // 64 | // CVS Revision History 65 | // 66 | // $Log: not supported by cvs2svn $ 67 | // Revision 1.16 2002/07/29 21:16:18 gorban 68 | // The uart_defines.v file is included again in sources. 69 | // 70 | // Revision 1.15 2002/07/22 23:02:23 gorban 71 | // Bug Fixes: 72 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. 73 | // Problem reported by Kenny.Tung. 74 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. 75 | // 76 | // Improvements: 77 | // * Made FIFO's as general inferrable memory where possible. 78 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). 79 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. 80 | // 81 | // * Added optional baudrate output (baud_o). 82 | // This is identical to BAUDOUT* signal on 16550 chip. 83 | // It outputs 16xbit_clock_rate - the divided clock. 84 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. 85 | // 86 | // Revision 1.12 2001/12/19 08:03:34 mohor 87 | // Warnings cleared. 88 | // 89 | // Revision 1.11 2001/12/06 14:51:04 gorban 90 | // Bug in LSR[0] is fixed. 91 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. 92 | // 93 | // Revision 1.10 2001/12/03 21:44:29 gorban 94 | // Updated specification documentation. 95 | // Added full 32-bit data bus interface, now as default. 96 | // Address is 5-bit wide in 32-bit data bus mode. 97 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. 98 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. 99 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. 100 | // My small test bench is modified to work with 32-bit mode. 101 | // 102 | // Revision 1.9 2001/10/20 09:58:40 gorban 103 | // Small synopsis fixes 104 | // 105 | // Revision 1.8 2001/08/24 21:01:12 mohor 106 | // Things connected to parity changed. 107 | // Clock devider changed. 108 | // 109 | // Revision 1.7 2001/08/23 16:05:05 mohor 110 | // Stop bit bug fixed. 111 | // Parity bug fixed. 112 | // WISHBONE read cycle bug fixed, 113 | // OE indicator (Overrun Error) bug fixed. 114 | // PE indicator (Parity Error) bug fixed. 115 | // Register read bug fixed. 116 | // 117 | // Revision 1.4 2001/05/31 20:08:01 gorban 118 | // FIFO changes and other corrections. 119 | // 120 | // Revision 1.3 2001/05/21 19:12:01 gorban 121 | // Corrected some Linter messages. 122 | // 123 | // Revision 1.2 2001/05/17 18:34:18 gorban 124 | // First 'stable' release. Should be sythesizable now. Also added new header. 125 | // 126 | // Revision 1.0 2001-05-17 21:27:13+02 jacob 127 | // Initial revision 128 | // 129 | // 130 | 131 | // UART core WISHBONE interface 132 | // 133 | // Author: Jacob Gorban (jacob.gorban@flextronicssemi.com) 134 | // Company: Flextronics Semiconductor 135 | // 136 | 137 | // synopsys translate_off 138 | `include "timescale.v" 139 | // synopsys translate_on 140 | `include "uart_defines.v" 141 | 142 | module uart_wb (clk, wb_rst_i, 143 | wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, 144 | wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i, 145 | we_o, re_o // Write and read enable output for the core 146 | ); 147 | 148 | input clk; 149 | 150 | // WISHBONE interface 151 | input wb_rst_i; 152 | input wb_we_i; 153 | input wb_stb_i; 154 | input wb_cyc_i; 155 | input [3:0] wb_sel_i; 156 | input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line 157 | 158 | `ifdef DATA_BUS_WIDTH_8 159 | input [7:0] wb_dat_i; //input WISHBONE bus 160 | output [7:0] wb_dat_o; 161 | reg [7:0] wb_dat_o; 162 | wire [7:0] wb_dat_i; 163 | reg [7:0] wb_dat_is; 164 | `else // for 32 data bus mode 165 | input [31:0] wb_dat_i; //input WISHBONE bus 166 | output [31:0] wb_dat_o; 167 | reg [31:0] wb_dat_o; 168 | wire [31:0] wb_dat_i; 169 | reg [31:0] wb_dat_is; 170 | `endif // !`ifdef DATA_BUS_WIDTH_8 171 | 172 | output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus 173 | input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o 174 | output [7:0] wb_dat8_i; 175 | input [31:0] wb_dat32_o; // 32 bit data output (for debug interface) 176 | output wb_ack_o; 177 | output we_o; 178 | output re_o; 179 | 180 | wire we_o; 181 | reg wb_ack_o; 182 | reg [7:0] wb_dat8_i; 183 | wire [7:0] wb_dat8_o; 184 | wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus 185 | reg [`UART_ADDR_WIDTH-1:0] wb_adr_is; 186 | reg wb_we_is; 187 | reg wb_cyc_is; 188 | reg wb_stb_is; 189 | reg [3:0] wb_sel_is; 190 | wire [3:0] wb_sel_i; 191 | reg wre ;// timing control signal for write or read enable 192 | 193 | // wb_ack_o FSM 194 | reg [1:0] wbstate; 195 | always @(posedge clk or posedge wb_rst_i) 196 | if (wb_rst_i) begin 197 | wb_ack_o <= #1 1'b0; 198 | wbstate <= #1 0; 199 | wre <= #1 1'b1; 200 | end else 201 | case (wbstate) 202 | 0: begin 203 | if (wb_stb_is & wb_cyc_is) begin 204 | wre <= #1 0; 205 | wbstate <= #1 1; 206 | wb_ack_o <= #1 1; 207 | end else begin 208 | wre <= #1 1; 209 | wb_ack_o <= #1 0; 210 | end 211 | end 212 | 1: begin 213 | wb_ack_o <= #1 0; 214 | wbstate <= #1 2; 215 | wre <= #1 0; 216 | end 217 | 2,3: begin 218 | wb_ack_o <= #1 0; 219 | wbstate <= #1 0; 220 | wre <= #1 0; 221 | end 222 | endcase 223 | 224 | assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers 225 | assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers 226 | 227 | // Sample input signals 228 | always @(posedge clk or posedge wb_rst_i) 229 | if (wb_rst_i) begin 230 | wb_adr_is <= #1 0; 231 | wb_we_is <= #1 0; 232 | wb_cyc_is <= #1 0; 233 | wb_stb_is <= #1 0; 234 | wb_dat_is <= #1 0; 235 | wb_sel_is <= #1 0; 236 | end else begin 237 | wb_adr_is <= #1 wb_adr_i; 238 | wb_we_is <= #1 wb_we_i; 239 | wb_cyc_is <= #1 wb_cyc_i; 240 | wb_stb_is <= #1 wb_stb_i; 241 | wb_dat_is <= #1 wb_dat_i; 242 | wb_sel_is <= #1 wb_sel_i; 243 | end 244 | 245 | `ifdef DATA_BUS_WIDTH_8 // 8-bit data bus 246 | always @(posedge clk or posedge wb_rst_i) 247 | if (wb_rst_i) 248 | wb_dat_o <= #1 0; 249 | else 250 | wb_dat_o <= #1 wb_dat8_o; 251 | 252 | always @(wb_dat_is) 253 | wb_dat8_i = wb_dat_is; 254 | 255 | assign wb_adr_int = wb_adr_is; 256 | 257 | `else // 32-bit bus 258 | // put output to the correct byte in 32 bits using select line 259 | always @(posedge clk or posedge wb_rst_i) 260 | if (wb_rst_i) 261 | wb_dat_o <= #1 0; 262 | else if (re_o) 263 | case (wb_sel_is) 264 | 4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o}; 265 | 4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0}; 266 | 4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0}; 267 | 4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0}; 268 | 4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output 269 | default: wb_dat_o <= #1 0; 270 | endcase // case(wb_sel_i) 271 | 272 | reg [1:0] wb_adr_int_lsb; 273 | 274 | always @(wb_sel_is or wb_dat_is) 275 | begin 276 | case (wb_sel_is) 277 | 4'b0001 : wb_dat8_i = wb_dat_is[7:0]; 278 | 4'b0010 : wb_dat8_i = wb_dat_is[15:8]; 279 | 4'b0100 : wb_dat8_i = wb_dat_is[23:16]; 280 | 4'b1000 : wb_dat8_i = wb_dat_is[31:24]; 281 | default : wb_dat8_i = wb_dat_is[7:0]; 282 | endcase // case(wb_sel_i) 283 | 284 | `ifdef LITLE_ENDIAN 285 | case (wb_sel_is) 286 | 4'b0001 : wb_adr_int_lsb = 2'h0; 287 | 4'b0010 : wb_adr_int_lsb = 2'h1; 288 | 4'b0100 : wb_adr_int_lsb = 2'h2; 289 | 4'b1000 : wb_adr_int_lsb = 2'h3; 290 | default : wb_adr_int_lsb = 2'h0; 291 | endcase // case(wb_sel_i) 292 | `else 293 | case (wb_sel_is) 294 | 4'b0001 : wb_adr_int_lsb = 2'h3; 295 | 4'b0010 : wb_adr_int_lsb = 2'h2; 296 | 4'b0100 : wb_adr_int_lsb = 2'h1; 297 | 4'b1000 : wb_adr_int_lsb = 2'h0; 298 | default : wb_adr_int_lsb = 2'h0; 299 | endcase // case(wb_sel_i) 300 | `endif 301 | end 302 | 303 | assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb}; 304 | 305 | `endif // !`ifdef DATA_BUS_WIDTH_8 306 | 307 | endmodule 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | -------------------------------------------------------------------------------- /nexys4ddr/scr1/README.md: -------------------------------------------------------------------------------- 1 | # SCR1 SDK. Xilinx Vivado Design Suite project for Nexys4DDR board 2 | 3 | ## Key features 4 | * Board: Digilent Nexys4DDR (https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start) 5 | * Tool: Xilinx Vivado Design Suite 2018.1 6 | 7 | ## Folder contents 8 | Folder | Description 9 | ------ | ----------- 10 | constrs | Constraint files 11 | src | Project's RTL source files 12 | mem_update.tcl | TCL-file for onchip SRAM memory initialization 13 | nexys4ddr_scr1.tcl | TCL-file for project creation 14 | README.md | This file 15 | scbl.mem | The onchip SRAM memory content file with the SCR1 Bootloader 16 | write_mmi.tcl | TCL-file with procedures for mem_update.tcl 17 | 18 | Hereinafter this folder is named (the folder containing this README file). 19 | 20 | ## Project deployment 21 | 1. Install Nexys4DDR's board files in Vivado directory structure, as described here: 22 | https://reference.digilentinc.com/reference/software/vivado/board-files 23 | 24 | 25 | 2. Launch Vivado IDE, and in its Tcl Console change current directory to the . 26 | 27 | 3. In Tcl Console, execute the following command 28 | 29 | 30 | source ./nexys4ddr_scr1.tcl 31 | 32 | The script "nexys4ddr_scr1.tcl" creates Vivado project nexys4ddr_scr1 and prepares used IPs for further synthesis. 33 | 34 | ## Synthesizing design and building bitstream file 35 | In the just deployed and open project, click on 36 | 37 | * Project Navigator / Program and Debug / Generate Bitstream button 38 | 39 | and press OK on the following Vivado confirmation request. 40 | This will start the process of full design rebuilding, from synthesis through bitstream file generation. 41 | 42 | ## Onchip memory update 43 | Due to Vivado Design Suite specifics described in the Xilinx AR #63042, initialization of the onchip memories 44 | is performed after bitstream file generation, by a standalone script mem_update.tcl. 45 | 46 | In the Tcl Console, execute the following commands: 47 | 48 | cd /nexys4ddr_scr1 49 | source "../mem_update.tcl" 50 | 51 | After successful completion, the folder 52 | 53 | /nexys4ddr_scr1/nexys4ddr_scr1.runs/impl_1 54 | 55 | should contain updated bit-file nexys4ddr_scr1_top_new.bit and MCS-file nexys4ddr_scr1_top_new.mcs for configuration FLASH chip programming. 56 | 57 | ## SCR1 Memory Map 58 | Base Address | Length | Name | Description 59 | ------------ | ------ | ------------- | ----------- 60 | 0x00000000 | 128 MB | SDRAM | Onboard DDR2 SDRAM. 61 | 0xF0000000 | 64 kB | TCM | SCR1 Tightly-Coupled Memory (refer to SCR1 EAS). 62 | 0xF0040000 | 32 B | Timer | SCR1 Timer registers (refer to SCR1 EAS). 63 | 0xFF000000 | | MMIO BASE | Base address for Memory-Mapped Peripheral IO resources, resided externally to SCR1 processor cluster. 64 | 0xFF000000 | 4 kB | SOC_ID | 32-bit SOC_ID register. 65 | 0xFF001000 | 4 kB | BLD_ID | 32-bit BLD_ID register. 66 | 0xFF002000 | 4 kB | CORE_CLK_FREQ | 32-bit Core Clock Frequency register. 67 | 0xFF010000 | 4 kB | UART | 16550 UART registers (refer to Xilinx IP description for details). Interrupt line is assigned to IRQ[0]. 68 | 0xFFFF0000 | 64 kB | SRAM | Onchip SRAM containing pre-programmed SCR Loader firmware. SCR1_RST_VECTOR and SCR1_CSR_MTVEC_BASE are both mapped here. 69 | 70 | ## SCR1 JTAG Pin-Out 71 | 72 | SCR1 JTAG port is routed to the onboard Pmod connector JC. The pin-out is suitable for direct 73 | connecting of the Digilent-HS2 USB JTAG adapter. 74 | 75 | Net | Pmod JC pin 76 | -------| ----------- 77 | TMS | 1 78 | TDI | 2 79 | TDO | 3 80 | TCK | 4 81 | GND | 5 82 | 3V3 | 6 83 | 84 | 85 | -------------------------------------------------------------------------------- /nexys4ddr/scr1/constrs/nexys4ddr_scr1_physical.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 3 | ## @file 4 | ## @brief Physical constraints file for Xilinx Vivado implementation. 5 | ## 6 | 7 | ## Clock & Reset 8 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports CLK100MHZ] 9 | set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports CPU_RESETn] 10 | set_property PULLUP true [get_ports CPU_RESETn] 11 | 12 | ## UART 13 | set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports FTDI_RXD] 14 | set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports FTDI_TXD] 15 | 16 | ## LEDs 17 | set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {LED[0]}] 18 | set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports {LED[1]}] 19 | set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports {LED[2]}] 20 | set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports {LED[3]}] 21 | set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {LED[4]}] 22 | set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {LED[5]}] 23 | set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports {LED[6]}] 24 | set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {LED[7]}] 25 | set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {LED[8]}] 26 | set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports {LED[9]}] 27 | set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {LED[10]}] 28 | set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports {LED[11]}] 29 | set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {LED[12]}] 30 | set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {LED[13]}] 31 | set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports {LED[14]}] 32 | set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports {LED[15]}] 33 | 34 | ## PMOD Header JC 35 | set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}] 36 | set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}] 37 | set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}] 38 | set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}] 39 | 40 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {JC_IBUF[3]}] 41 | set_property PULLDOWN true [get_ports {JC[3]}] 42 | set_property PULLUP true [get_ports {JC[0]}] 43 | set_property PULLUP true [get_ports {JC[1]}] 44 | set_property PULLUP true [get_ports {JC[2]}] 45 | 46 | ## FPGA Configuration 47 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 48 | set_property CONFIG_MODE SPIx4 [current_design] 49 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -------------------------------------------------------------------------------- /nexys4ddr/scr1/constrs/nexys4ddr_scr1_synth.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 3 | ## @file 4 | ## @brief Constraint file for Xilinx Vivado synthesis. 5 | ## 6 | 7 | ## Primary Clocks 8 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports CLK100MHZ] 9 | 10 | create_clock -period 10.000 -name CLK100MHZ -waveform {0.000 5.000} -add [get_ports CLK100MHZ] 11 | create_clock -period 33.333 -name CPU_CLK_VIRT -waveform {0.000 16.666} 12 | create_clock -period 100.000 -name JTAG_TCK -waveform {0.000 50.000} -add [get_ports {JC[3]}] 13 | create_clock -period 100.000 -name JTAG_TCK_VIRT -waveform {0.000 50.000} 14 | 15 | -------------------------------------------------------------------------------- /nexys4ddr/scr1/constrs/nexys4ddr_scr1_timing.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 3 | ## @file 4 | ## @brief Timing constraints file for Xilinx Vivado implementation. 5 | ## 6 | 7 | # NB! Primary clocks are defined in the synthesis constraint file (*_synth.xdc). 8 | 9 | create_generated_clock -name CPU_CLK [get_pins i_soc/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0] 10 | 11 | set_clock_groups -name async_clk100mhz_tck -asynchronous -group {CLK100MHZ CPU_CLK CPU_CLK_VIRT} -group {JTAG_TCK JTAG_TCK_VIRT} 12 | 13 | set_false_path -from [get_clocks JTAG_TCK] -to [get_clocks CPU_CLK] 14 | set_false_path -from [get_clocks JTAG_TCK_VIRT] -to [get_clocks CPU_CLK] 15 | set_false_path -from [get_clocks CPU_CLK] -to [get_clocks JTAG_TCK] 16 | set_false_path -to [get_ports FTDI_RXD] 17 | set_false_path -from [get_ports FTDI_TXD] 18 | set_false_path -to [get_ports {LED[0]}] 19 | 20 | set_input_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports CPU_RESETn] 21 | set_input_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports FTDI_TXD] 22 | set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[*]}] 23 | #set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[0]}] 24 | #set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[1]}] 25 | #set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[2]}] 26 | #set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[4]}] 27 | #set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[5]}] 28 | #set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[6]}] 29 | #set_input_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[7]}] 30 | 31 | set_output_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports FTDI_RXD] 32 | set_output_delay -clock [get_clocks CPU_CLK_VIRT] 3.300 [get_ports LED*] 33 | set_output_delay -clock [get_clocks JTAG_TCK_VIRT] 6.600 [get_ports {JC[*]}] 34 | 35 | #set_input_delay -clock JTAG_TCK -clock_fall -max -add_delay 5.000 [get_ports {JC[0] JC[1]}] 36 | #set_input_delay -clock JTAG_TCK -clock_fall -min -add_delay 0.000 [get_ports {JC[0] JC[1]}] 37 | #set_output_delay -clock JTAG_TCK -clock_fall -max -add_delay 5.000 [get_ports {JC[2]}] 38 | #set_output_delay -clock JTAG_TCK -clock_fall -min -add_delay 0.000 [get_ports {JC[2]}] 39 | 40 | -------------------------------------------------------------------------------- /nexys4ddr/scr1/mem_update.tcl: -------------------------------------------------------------------------------- 1 | # Tcl-file for Xilinx Vivado projects: mem_update.tcl 2 | 3 | # Input parameters: 4 | set proj [current_project] 5 | set proj_dir [get_property directory [current_project]] 6 | set top_entity [get_property top [get_filesets sources_1]] 7 | set obj_dir [get_property directory [get_runs impl_1]] 8 | #set mem_file "../[glob -nocomplain *.mem]" 9 | set mem_file "../scbl.mem" 10 | set bit_file "${top_entity}.bit" 11 | set out_file "${top_entity}_new.bit" 12 | set cmd_file "../write_mmi.tcl" 13 | set sram_cell "blk_mem_gen_0" 14 | set mmi_file "${sram_cell}.mmi" 15 | set mcs_file "${top_entity}_new.mcs" 16 | 17 | # Normalization 18 | set obj_dir [file normalize "$obj_dir"] 19 | set mem_file [file normalize "$proj_dir/$mem_file"] 20 | set bit_file [file normalize "$obj_dir/$bit_file"] 21 | set out_file [file normalize "$obj_dir/$out_file"] 22 | set cmd_file [file normalize "$proj_dir/$cmd_file"] 23 | set mmi_file [file normalize "$obj_dir/$mmi_file"] 24 | set mcs_file [file normalize "$obj_dir/$mcs_file"] 25 | 26 | # Check if necessary files are present 27 | if {![file exists $bit_file]} { 28 | error "ERROR! Bit-file $bit_file is not found." 29 | } 30 | if {![file exists $mem_file]} { 31 | error "ERROR! Mem-file $mem_file is not found." 32 | } 33 | 34 | # Sourcing of write_mmi.tcl 35 | # It is necessary for onchip memory initialization. 36 | # For details refer to Xilinx AR 63042. 37 | if {![file exists $cmd_file]} { 38 | error "ERROR! Tcl-script $cmd_file is not found." 39 | } else { 40 | source -quiet $cmd_file 41 | } 42 | 43 | open_run -quiet impl_1 44 | 45 | if {[get_cells -hierarchical $sram_cell] eq ""} { 46 | error "ERROR! SRAM cell $sram_cell is not found in the design impl_1." 47 | } 48 | 49 | write_mmi $sram_cell $mmi_file 50 | 51 | exec updatemem -force --meminfo $mmi_file --data $mem_file --bit $bit_file \ 52 | --proc "dummy" --out $out_file 53 | 54 | write_cfgmem -force -format mcs -size 16 -interface SPIx4 \ 55 | -loadbit "up 0x00000000 $out_file " -checksum \ 56 | -file "$mcs_file" 57 | -------------------------------------------------------------------------------- /nexys4ddr/scr1/src/scr1_arch_custom.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_ARCH_CUSTOM_SVH 2 | `define SCR1_ARCH_CUSTOM_SVH 3 | /// Copyright by Syntacore LLC © 2016, 2017, 2021. See LICENSE for details 4 | /// @file 5 | /// @brief Custom Architecture Parameters File 6 | /// 7 | 8 | // Current FPGA build identificators, can be modified 9 | `define SCR1_PTFM_SOC_ID 32'h21042600 10 | `define SCR1_PTFM_BLD_ID 32'h22011202 11 | `define SCR1_PTFM_CORE_CLK_FREQ 32'd30000000 12 | 13 | `define SCR1_TRGT_FPGA_XILINX // Uncomment if target platform is Xilinx FPGAs 14 | //`define SCR1_TRGT_FPGA_INTEL // Uncomment if target platform is Intel FPGAs AND ---> 15 | //`define SCR1_TRGT_FPGA_INTEL_MAX10 // ---> Uncomment if target platform is Intel MAX 10 FPGAs 16 | //`define SCR1_TRGT_FPGA_INTEL_ARRIAV // ---> Uncomment if target platform is Intel Arria V FPGAs 17 | 18 | 19 | 20 | 21 | 22 | // Uncomment to select recommended core architecture configurations 23 | // Default SCR1 FPGA SDK created for RV32IMC_MAX config 24 | 25 | `define SCR1_CFG_RV32IMC_MAX 26 | //`define SCR1_CFG_RV32IC_BASE 27 | //`define SCR1_CFG_RV32EC_MIN 28 | 29 | 30 | 31 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_RST_VECTOR = 'hFFFFFF00; // Reset vector 32 | parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_MTVEC_BASE = 'hFFFFFF80; // MTVEC BASE field reset value 33 | 34 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_MASK = 'hFFFF0000; // TCM mask and size 35 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_PATTERN = 'hF0000000; // TCM address match pattern 36 | 37 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_MASK = 'hFFFFFFE0; // Timer mask (should be 0xFFFFFFE0) 38 | parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_PATTERN = 'hF0040000; // Timer address match pattern 39 | 40 | `endif // SCR1_ARCH_CUSTOM_SVH -------------------------------------------------------------------------------- /nexys4ddr/scr1/write_mmi.tcl: -------------------------------------------------------------------------------- 1 | #Created by stephenm@xilinx.com. This is not supported by WTS 2 | #The cell_name is the name of the Block RAM in the BD. 3 | #This has been tested with a memory range 0K - 1M 4 | #This only supports data width of 32 bits. 5 | 6 | 7 | proc write_mmi {cell_name filename} { 8 | set proj [current_project] 9 | # set filename "${cell_name}.mmi" 10 | set fileout [open $filename "w"] 11 | set brams [split [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }] " "] 12 | #isolate all BRAMs identified by cell_name 13 | set cell_name_bram "" 14 | for {set i 0} {$i < [llength $brams]} {incr i} { 15 | if { [regexp -nocase $cell_name [lindex $brams $i]] } { 16 | lappend cell_name_bram [lindex $brams $i] 17 | } 18 | } 19 | set proc_found 0 20 | set inst_path "dummy" 21 | #set inst_path [split [get_cells -hierarchical -filter { NAME =~ "*microblaze*" } ] " "] 22 | if {$inst_path == ""} { 23 | puts "Warning: No Processor found" 24 | set inst_path "dummy" 25 | } else { 26 | set proc_found 1 27 | set inst_path [lindex $inst_path 0] 28 | } 29 | 30 | puts $fileout "" 31 | puts $fileout "" 32 | set inst_temp [lindex $brams 0] 33 | set loc_temp [string first $cell_name $inst_temp] 34 | set inst [string range $inst_temp 0 $loc_temp] 35 | set new_inst [string last "/" $inst] 36 | set new_inst [string range $inst 0 $new_inst-1] 37 | puts $fileout " " 38 | set bram_range 0 39 | for {set i 0} {$i < [llength $cell_name_bram]} {incr i} { 40 | set bram_type [get_property REF_NAME [get_cells [lindex $cell_name_bram $i]]] 41 | if {$bram_type == "RAMB36E1"} { 42 | set bram_range [expr {$bram_range + 4096}] 43 | } 44 | } 45 | puts $fileout " " 46 | 47 | set bram [llength $cell_name_bram] 48 | if {$bram >= 32} { 49 | set sequence "7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24" 50 | set bus_blocks [expr {$bram / 32}] 51 | } elseif {$bram >= 16 && $bram < 32} { 52 | set sequence "7,5,3,1,15,13,11,9,23,21,19,17,31,29,27,25" 53 | set bus_blocks 1 54 | } elseif {$bram >= 8 && $bram < 16} { 55 | set sequence "7,3,15,11,23,19,31,27" 56 | set bus_blocks 1 57 | } elseif {$bram >= 4 && $bram < 8} { 58 | set sequence "7,15,23,31" 59 | set bus_blocks 1 60 | } else { 61 | set sequence "15,31" 62 | set bus_blocks 1 63 | } 64 | set sequence [split $sequence ","] 65 | 66 | 67 | for {set b 0} {$b < $bus_blocks} {incr b} { 68 | puts $fileout " " 69 | for {set i 0} {$i < [llength $sequence]} {incr i} { 70 | for {set j 0} {$j < [llength $cell_name_bram]} {incr j} { 71 | set block_start [expr {32768 * $b}] 72 | set bmm_width [bram_info [lindex $cell_name_bram $j] "bit_lane"] 73 | set bmm_width [split $bmm_width ":"] 74 | set bmm_msb [lindex $bmm_width 0] 75 | set bmm_lsb [lindex $bmm_width 1] 76 | set bmm_range [bram_info [lindex $cell_name_bram $j] "range"] 77 | set split_ranges [split $bmm_range ":"] 78 | set MSB [lindex $sequence $i] 79 | if {$MSB == $bmm_msb && $block_start == [lindex $split_ranges 0]} { 80 | set bram_type [get_property REF_NAME [get_cells [lindex $cell_name_bram $j]]] 81 | set status [get_property STATUS [get_cells [lindex $cell_name_bram $j]]] 82 | 83 | if {$status == "UNPLACED"} { 84 | set placed "X0Y0" 85 | } else { 86 | set placed [get_property LOC [get_cells [lindex $cell_name_bram $j]]] 87 | set placed_list [split $placed "_"] 88 | set placed [lindex $placed_list 1] 89 | } 90 | set bram_type [get_property REF_NAME [get_cells [lindex $cell_name_bram $j]]] 91 | if {$bram_type == "RAMB36E1"} { 92 | set bram_type "RAMB32" 93 | } 94 | 95 | puts $fileout " " 96 | puts $fileout " " 97 | puts $fileout " " 98 | puts $fileout " " 99 | puts $fileout " " 100 | } 101 | } 102 | } 103 | puts $fileout " " 104 | puts $fileout " " 105 | } 106 | puts $fileout " " 107 | puts $fileout "" 108 | puts $fileout " " 110 | puts $fileout "" 111 | close $fileout 112 | puts "MMI file ($filename) created successfully." 113 | puts "To run Updatemem, use the command line below after write_bitstream:" 114 | puts "updatemem -force --meminfo $filename --data .elf/mem --bit .bit --proc $inst_path --out .bit" 115 | } 116 | 117 | proc bram_info {bram type} { 118 | set temp [get_property bmm_info_memory_device [get_cells $bram]] 119 | set bmm_info_memory_device [regexp {\[(.+)\]\[(.+)\]} $temp all 1 2] 120 | if {$type == "bit_lane"} { 121 | return $1 122 | } elseif {$type == "range"} { 123 | return $2 124 | } else { 125 | return $all 126 | } 127 | } 128 | 129 | proc export2sdk {} { 130 | set proj [current_project] 131 | set file_list "" 132 | set get_impl [split [get_runs] " "] 133 | set get_impl [lindex $get_impl [expr {[llength $get_impl] - 1}]] 134 | set sdk_dir [glob -nocomplain -type d *.sdk] 135 | if {$sdk_dir == ""} { 136 | puts "Creating SDK folder: ${proj}.sdk" 137 | file mkdir ${proj}.sdk 138 | } 139 | set mmi_file [glob -nocomplain -directory ${proj}.runs/${get_impl} *.mmi] 140 | if {$mmi_file != ""} { 141 | lappend file_list $mmi_file 142 | } 143 | set bit_file [glob -nocomplain -directory ${proj}.runs/${get_impl} *.bit] 144 | if {$bit_file != ""} { 145 | lappend file_list $bit_file 146 | } 147 | set hwdef_file [glob -nocomplain -directory ${proj}.runs/${get_impl} *.hwdef] 148 | if {$hwdef_file != ""} { 149 | lappend file_list $hwdef_file 150 | } 151 | write_sysdef -force -meminfo $mmi_file -hwdef $hwdef_file -bitfile $bit_file -file ${proj}.sdk/test.hdf 152 | puts "Creating HDF file containing" 153 | for {set i 0} {$i <= [llength $file_list]} {incr i} { 154 | puts [lindex $file_list $i] 155 | } 156 | } 157 | --------------------------------------------------------------------------------