├── .gitignore ├── DemoProjects └── STM32F7Disco-QSPI │ ├── CMakeLists.txt │ ├── ExtraMemories.c │ ├── ExtraMemories.h │ ├── ExtraMemories.xml │ ├── QSPIDemo.cpp │ ├── QSPIDemo.sln │ ├── QSPIDemo.vgdbcmake │ ├── QSPIRoutines.cpp │ ├── STM32F746NG_flash.lds │ ├── stm32f7disco_qspi.elf │ ├── stm32f7xx_hal_conf.h │ └── system_stm32f7xx.c ├── LPC54628_FlashIAP.elf ├── LPC55S16_FlashIAP.elf ├── common ├── CMakeLists.txt ├── FLASHPluginCommon.cpp └── FLASHPluginInterface.h ├── iMXRT1050_HyperFLASH_ROMAPI.elf ├── iMXRT1064_Internal_ROMAPI.elf ├── imxrt ├── IMXRT1050_HyperFLASH_ROMAPI │ ├── CMakeLists.txt │ ├── FLASHPluginConfig.h │ ├── IMXRT1050_HyperFLASH_ROMAPI.sln │ ├── IMXRT1050_HyperFLASH_ROMAPI.vgdbcmake │ ├── MIMXRT1052xxxxx_ram.ld │ ├── board.c │ ├── board.h │ ├── clock_config.c │ ├── clock_config.h │ ├── dcd.c │ ├── dcd.h │ ├── flexspi_romapi_ops.c │ ├── main.cpp │ ├── pin_mux.c │ ├── pin_mux.h │ └── system_MIMXRT1052.c ├── iMXRT1064_Internal_ROMAPI │ ├── CMakeLists.txt │ ├── FLASHPluginConfig.h │ ├── MIMXRT1064xxxxx_ram.ld │ ├── board.c │ ├── board.h │ ├── clock_config.c │ ├── clock_config.h │ ├── dcd.c │ ├── dcd.h │ ├── iMXRT1064_Internal_ROMAPI.sln │ ├── iMXRT1064_Internal_ROMAPI.vgdbcmake │ ├── main.cpp │ ├── pin_mux.c │ ├── pin_mux.h │ └── system_MIMXRT1064.c └── imxrt.cfg ├── nxp_lpc ├── LPC54628_FlashIAP │ ├── CMakeLists.txt │ ├── FLASHPluginConfig.h │ ├── LPC54628_FlashIAP.sln │ ├── LPC54628_FlashIAP.vgdbcmake │ ├── clock_config.c │ ├── clock_config.h │ ├── main.cpp │ └── pin_mux.h └── LPC55S16_FlashIAP │ ├── CMakeLists.txt │ ├── FLASHPluginConfig.h │ ├── LPC55S16_FlashIAP.sln │ ├── LPC55S16_FlashIAP.vgdbcmake │ ├── clock_config.c │ ├── clock_config.h │ └── main.cpp ├── stm32 ├── stm32f769_disco_qspi │ ├── FLASHPluginConfig.h │ ├── Inc │ │ ├── main.h │ │ ├── stm32f7xx_hal_conf.h │ │ └── stm32f7xx_it.h │ ├── Src │ │ └── system_stm32f7xx.c │ ├── main.cpp │ ├── n25q512a.h │ ├── readme.txt │ ├── stm32.props │ ├── stm32.xml │ ├── stm32f769_disco_qspi-Debug.vgdbsettings │ ├── stm32f769_disco_qspi-Release.vgdbsettings │ ├── stm32f769_disco_qspi.sln │ ├── stm32f769_disco_qspi.vcxproj │ ├── stm32f769_disco_qspi.vcxproj.filters │ ├── stm32f769i_eval_qspi.c │ └── stm32f769i_eval_qspi.h └── stm32f7disco_qspi │ ├── FLASHPluginConfig.h │ ├── main.cpp │ ├── stm32.props │ ├── stm32.xml │ ├── stm32f7disco_qspi-Debug.vgdbsettings │ ├── stm32f7disco_qspi-Release.vgdbsettings │ ├── stm32f7disco_qspi.sln │ ├── stm32f7disco_qspi.vcxproj │ ├── stm32f7disco_qspi.vcxproj.filters │ ├── stm32f7xx_hal_conf.h │ └── system_stm32f7xx.c ├── stm32f769_disco_qspi.elf └── stm32f7disco_qspi.elf /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled Object files 2 | *.slo 3 | *.lo 4 | *.o 5 | *.obj 6 | 7 | # Precompiled Headers 8 | *.gch 9 | *.pch 10 | 11 | # Compiled Dynamic libraries 12 | *.so 13 | *.dylib 14 | *.dll 15 | 16 | # Fortran module files 17 | *.mod 18 | 19 | # Compiled Static libraries 20 | *.lai 21 | *.la 22 | *.a 23 | *.lib 24 | 25 | # Executables 26 | *.exe 27 | *.out 28 | *.app 29 | *.pdb 30 | *.exp 31 | Debug 32 | Release 33 | ipch 34 | *.sdf 35 | *.suo 36 | CodeDB 37 | obj 38 | Debug 39 | Release 40 | VisualGDBCache 41 | *.old 42 | *.opendb 43 | .vs 44 | *.user 45 | .visualgdb 46 | -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.15) 2 | 3 | project(QSPIDemo LANGUAGES C CXX ASM) 4 | 5 | find_bsp( 6 | ID com.sysprogs.arm.stm32 7 | VERSION 2023.07 8 | MCU STM32F746NG 9 | FRAMEWORKS com.sysprogs.arm.stm32.hal com.sysprogs.arm.stm32.ll 10 | HWREGISTER_LIST_FILE STM32F7xxxx/DeviceDefinitions/stm32f746xx.xml 11 | DISABLE_GNU_EXTENSIONS) 12 | 13 | add_bsp_based_executable( 14 | NAME QSPIDemo 15 | SOURCES QSPIDemo.cpp system_stm32f7xx.c stm32f7xx_hal_conf.h QSPIRoutines.cpp 16 | GENERATE_MAP 17 | LINKER_SCRIPT STM32F746NG_flash.lds 18 | MEMORY_LIST_FILE ExtraMemories) 19 | -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/ExtraMemories.c: -------------------------------------------------------------------------------- 1 | #include "ExtraMemories.h" 2 | 3 | //Program the _QSPI.bin file to QSPI manually 4 | -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/ExtraMemories.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | //E.g. void QSPI_TEXT func(); 4 | #define QSPI_TEXT __attribute__((section(".qspi_text"))) 5 | 6 | //E.g. int QSPI_DATA g_Initialized = 1; 7 | #define QSPI_DATA __attribute__((section(".qspi_data"))) 8 | 9 | //E.g. int QSPI_BSS g_Uninitialized; 10 | #define QSPI_BSS __attribute__((section(".qspi_bss"))) 11 | 12 | 13 | -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/ExtraMemories.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | QSPI 5 |
2415919104
6 | 65536 7 | FLASH 8 | true 9 | true 10 | true 11 | false 12 | false 13 | false 14 | 15 | -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/QSPIDemo.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | extern "C" void QSPI_TEXT FunctionInQSPIFLASH(); 6 | 7 | #ifdef __cplusplus 8 | extern "C" 9 | #endif 10 | void SysTick_Handler(void) 11 | { 12 | HAL_IncTick(); 13 | HAL_SYSTICK_IRQHandler(); 14 | } 15 | 16 | static const int QSPI_DATA LargeArray[] = { 100, 200, 300, 400, 500, 600 }; 17 | void QSPI_TEXT FunctionInQSPIFLASH() 18 | { 19 | __GPIOC_CLK_ENABLE(); 20 | GPIO_InitTypeDef GPIO_InitStructure; 21 | 22 | GPIO_InitStructure.Pin = GPIO_PIN_12; 23 | 24 | GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; 25 | GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH; 26 | GPIO_InitStructure.Pull = GPIO_NOPULL; 27 | HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); 28 | 29 | for (int i = 0;;i++) 30 | { 31 | HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_SET); 32 | HAL_Delay(LargeArray[i % (sizeof(LargeArray) / sizeof(LargeArray[0]))]); 33 | HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_RESET); 34 | HAL_Delay(LargeArray[i % (sizeof(LargeArray) / sizeof(LargeArray[0]))]); 35 | } 36 | } 37 | 38 | void QSPI_EnableMemoryMappedMode(QSPI_HandleTypeDef *hqspi, uint32_t flashAddress, uint32_t size); 39 | QSPI_HandleTypeDef QSPIHandle; 40 | 41 | int main(void) 42 | { 43 | HAL_Init(); 44 | QSPI_EnableMemoryMappedMode(&QSPIHandle, 0, 0x10000); 45 | FunctionInQSPIFLASH(); 46 | } -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/QSPIDemo.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 17 4 | VisualStudioVersion = 17.6.33723.286 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{803FD0C6-D64E-4E16-9DC3-1DAEC859A3D2}") = "QSPIDemo", "QSPIDemo.vgdbcmake", "{252DF765-2F1E-4E7B-963F-6E775B2D80AA}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|VisualGDB = Debug|VisualGDB 11 | MinSizeRel|VisualGDB = MinSizeRel|VisualGDB 12 | Release|VisualGDB = Release|VisualGDB 13 | RelWithDebInfo|VisualGDB = RelWithDebInfo|VisualGDB 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.Debug|VisualGDB.ActiveCfg = Debug|VisualGDB 17 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.Debug|VisualGDB.Build.0 = Debug|VisualGDB 18 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.MinSizeRel|VisualGDB.ActiveCfg = MinSizeRel|VisualGDB 19 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.MinSizeRel|VisualGDB.Build.0 = MinSizeRel|VisualGDB 20 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.Release|VisualGDB.ActiveCfg = Release|VisualGDB 21 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.Release|VisualGDB.Build.0 = Release|VisualGDB 22 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.RelWithDebInfo|VisualGDB.ActiveCfg = RelWithDebInfo|VisualGDB 23 | {252DF765-2F1E-4E7B-963F-6E775B2D80AA}.RelWithDebInfo|VisualGDB.Build.0 = RelWithDebInfo|VisualGDB 24 | EndGlobalSection 25 | GlobalSection(SolutionProperties) = preSolution 26 | HideSolutionNode = FALSE 27 | EndGlobalSection 28 | EndGlobal 29 | -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/STM32F746NG_flash.lds: -------------------------------------------------------------------------------- 1 | /* Generated by LinkerScriptGenerator [http://visualgdb.com/tools/LinkerScriptGenerator] 2 | * Target: STM32F746NG 3 | * The file is provided under the BSD license. 4 | */ 5 | 6 | ENTRY(Reset_Handler) 7 | 8 | MEMORY 9 | { 10 | FLASH (RX) : ORIGIN = 0x08000000, LENGTH = 1M 11 | SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 320K 12 | /* --- begin generated external memories -- */ 13 | QSPI (RX) : ORIGIN = 0x90000000, LENGTH = 64K 14 | /* --- end generated external memories -- */ 15 | } 16 | 17 | _estack = 0x20050000; 18 | 19 | SECTIONS 20 | { 21 | .isr_vector : 22 | { 23 | . = ALIGN(4); 24 | KEEP(*(.isr_vector)) 25 | . = ALIGN(4); 26 | } > FLASH 27 | 28 | .text : 29 | { 30 | . = ALIGN(4); 31 | _stext = .; 32 | 33 | *(.text) 34 | *(.text*) 35 | *(.rodata) 36 | *(.rodata*) 37 | *(.glue_7) 38 | *(.glue_7t) 39 | KEEP(*(.init)) 40 | KEEP(*(.fini)) 41 | . = ALIGN(4); 42 | _etext = .; 43 | 44 | } > FLASH 45 | 46 | .ARM.extab : 47 | { 48 | . = ALIGN(4); 49 | *(.ARM.extab) 50 | *(.gnu.linkonce.armextab.*) 51 | . = ALIGN(4); 52 | } > FLASH 53 | 54 | .exidx : 55 | { 56 | . = ALIGN(4); 57 | PROVIDE(__exidx_start = .); 58 | *(.ARM.exidx*) 59 | . = ALIGN(4); 60 | PROVIDE(__exidx_end = .); 61 | } > FLASH 62 | 63 | .ARM.attributes : 64 | { 65 | *(.ARM.attributes) 66 | } > FLASH 67 | 68 | .preinit_array : 69 | { 70 | PROVIDE(__preinit_array_start = .); 71 | KEEP(*(.preinit_array*)) 72 | PROVIDE(__preinit_array_end = .); 73 | } > FLASH 74 | 75 | .init_array : 76 | { 77 | PROVIDE(__init_array_start = .); 78 | KEEP(*(SORT(.init_array.*))) 79 | KEEP(*(.init_array*)) 80 | PROVIDE(__init_array_end = .); 81 | } > FLASH 82 | 83 | .fini_array : 84 | { 85 | PROVIDE(__fini_array_start = .); 86 | KEEP(*(.fini_array*)) 87 | KEEP(*(SORT(.fini_array.*))) 88 | PROVIDE(__fini_array_end = .); 89 | } > FLASH 90 | 91 | .data : 92 | { 93 | . = ALIGN(4); 94 | _sdata = .; 95 | 96 | PROVIDE(__data_start__ = _sdata); 97 | *(.data) 98 | *(.data*) 99 | . = ALIGN(4); 100 | _edata = .; 101 | 102 | PROVIDE(__data_end__ = _edata); 103 | } > SRAM AT >FLASH 104 | 105 | _sidata = LOADADDR(.data); 106 | 107 | .bss : 108 | { 109 | . = ALIGN(4); 110 | _sbss = .; 111 | 112 | PROVIDE(__bss_start__ = _sbss); 113 | *(.bss) 114 | *(.bss*) 115 | *(COMMON) 116 | . = ALIGN(4); 117 | _ebss = .; 118 | 119 | PROVIDE(__bss_end__ = _ebss); 120 | } > SRAM 121 | /* --- begin generated external memory sections -- */ 122 | .qspi_text : 123 | { 124 | . = ALIGN(4); 125 | _sqspi_text = .; 126 | 127 | PROVIDE(__qspi_text_start = _sqspi_text); 128 | *(.qspi_text) 129 | *(.qspi_text*) 130 | . = ALIGN(4); 131 | _eqspi_text = .; 132 | 133 | PROVIDE(__qspi_text_end = _eqspi_text); 134 | } > QSPI 135 | 136 | .qspi_data : 137 | { 138 | . = ALIGN(4); 139 | _sqspi_data = .; 140 | 141 | PROVIDE(__qspi_data_start = _sqspi_data); 142 | *(.qspi_data) 143 | *(.qspi_data*) 144 | . = ALIGN(4); 145 | _eqspi_data = .; 146 | 147 | PROVIDE(__qspi_data_end = _eqspi_data); 148 | } > QSPI 149 | 150 | .qspi_bss (NOLOAD) : 151 | { 152 | . = ALIGN(4); 153 | _sqspi_bss = .; 154 | 155 | PROVIDE(__qspi_bss_start = _sqspi_bss); 156 | *(.qspi_bss) 157 | *(.qspi_bss*) 158 | . = ALIGN(4); 159 | _eqspi_bss = .; 160 | 161 | PROVIDE(__qspi_bss_end = _eqspi_bss); 162 | } > QSPI 163 | 164 | /* --- end generated external memory sections -- */ 165 | 166 | 167 | PROVIDE(end = .); 168 | 169 | .heap (NOLOAD) : 170 | { 171 | . = ALIGN(4); 172 | PROVIDE(__heap_start__ = .); 173 | KEEP(*(.heap)) 174 | . = ALIGN(4); 175 | PROVIDE(__heap_end__ = .); 176 | } > SRAM 177 | 178 | .reserved_for_stack (NOLOAD) : 179 | { 180 | . = ALIGN(4); 181 | PROVIDE(__reserved_for_stack_start__ = .); 182 | KEEP(*(.reserved_for_stack)) 183 | . = ALIGN(4); 184 | PROVIDE(__reserved_for_stack_end__ = .); 185 | } > SRAM 186 | 187 | } 188 | 189 | -------------------------------------------------------------------------------- /DemoProjects/STM32F7Disco-QSPI/stm32f7disco_qspi.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/DemoProjects/STM32F7Disco-QSPI/stm32f7disco_qspi.elf -------------------------------------------------------------------------------- /LPC54628_FlashIAP.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/LPC54628_FlashIAP.elf -------------------------------------------------------------------------------- /LPC55S16_FlashIAP.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/LPC55S16_FlashIAP.elf -------------------------------------------------------------------------------- /common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_library(FLASHPlugin INTERFACE FLASHPluginCommon.cpp) 2 | 3 | target_sources(FLASHPlugin INTERFACE 4 | FLASHPluginCommon.cpp) 5 | 6 | target_include_directories(FLASHPlugin INTERFACE .) 7 | -------------------------------------------------------------------------------- /common/FLASHPluginCommon.cpp: -------------------------------------------------------------------------------- 1 | #include "FLASHPluginInterface.h" 2 | #include "FLASHPluginConfig.h" 3 | #include 4 | 5 | #ifndef MINIMUM_PROGRAMMED_BLOCK_SIZE 6 | #error Please define MINIMUM_PROGRAMMED_BLOCK_SIZE in your FLASHPluginConfig.h 7 | #endif 8 | 9 | struct plugin_timeouts 10 | { 11 | unsigned erase; 12 | unsigned write; 13 | unsigned init; 14 | unsigned load; 15 | unsigned protect; 16 | }; 17 | 18 | struct image_plugin_timeouts 19 | { 20 | unsigned size; 21 | struct plugin_timeouts timeouts; 22 | }; 23 | 24 | 25 | //If you want to override default time-out values for the plugin, provide another definition of FLASHPlugin_TimeoutTable in your plugin sources. 26 | extern "C" 27 | { 28 | __attribute__((weak)) image_plugin_timeouts FLASHPlugin_TimeoutTable = 29 | { 30 | .size = sizeof(struct plugin_timeouts), 31 | .timeouts = 32 | { 33 | .erase = 60000, 34 | .write = 1000, 35 | .init = 1000, 36 | .load = 10000, 37 | .protect = 1000, 38 | } 39 | }; 40 | } 41 | 42 | volatile void * __attribute__((used)) g_FunctionTable[] = { 43 | (void *)&FLASHPlugin_Unload, 44 | (void *)&FLASHPlugin_Probe, 45 | (void *)&FLASHPlugin_FindWorkArea, 46 | (void *)&FLASHPlugin_EraseSectors, 47 | #if FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 48 | (void *)&FLASHPlugin_ProgramAsync, 49 | #else 50 | (void *)&FLASHPlugin_ProgramSync, 51 | #endif 52 | 53 | (void *)&FLASHPlugin_ProtectSectors, 54 | (void *)&FLASHPlugin_CheckSectorProtection, 55 | }; 56 | 57 | void FLASHPlugin_InitDone() 58 | { 59 | asm("cpsid i"); 60 | g_FunctionTable[0] = (void *)&FLASHPlugin_TimeoutTable; 61 | } 62 | 63 | int FLASHPlugin_NotImplemented() 64 | { 65 | return -1; 66 | } 67 | 68 | int FLASHPlugin_CheckSectorProtection(unsigned firstSector, unsigned sectorCount, unsigned char *pBuffer) __attribute__((weak, alias("FLASHPlugin_NotImplemented"))); 69 | int FLASHPlugin_ProtectSectors(unsigned protect, unsigned firstSector, unsigned sectorCount)__attribute__((weak, alias("FLASHPlugin_NotImplemented"))); 70 | 71 | #if FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 72 | int FLASHPlugin_ProgramAsync(unsigned startOffset, FIFOHeader *pData, const void *pEndOfData, unsigned bytesToWrite) 73 | { 74 | InterruptEnabler enabler; 75 | unsigned done = 0; 76 | unsigned bufferSize = (char *)pEndOfData - (char *)(pData + 1); 77 | if (bufferSize % MINIMUM_PROGRAMMED_BLOCK_SIZE) 78 | { 79 | pData->ReadPointer = 0; 80 | return -4; 81 | } 82 | unsigned maxBytesAtOnce = ((bufferSize / MINIMUM_PROGRAMMED_BLOCK_SIZE) / 4) * MINIMUM_PROGRAMMED_BLOCK_SIZE; 83 | if (maxBytesAtOnce == 0) 84 | maxBytesAtOnce = bufferSize; 85 | 86 | while (done < bytesToWrite) 87 | { 88 | char *rp = pData->ReadPointer; 89 | char *wp = pData->WritePointer; 90 | if (wp == rp) 91 | continue; 92 | 93 | if (wp < rp) 94 | wp = (char *)pEndOfData; 95 | if (wp > pEndOfData) 96 | { 97 | pData->ReadPointer = 0; 98 | return -1; 99 | } 100 | 101 | unsigned todo = wp - rp; 102 | if (!todo) 103 | continue; 104 | 105 | if (todo % MINIMUM_PROGRAMMED_BLOCK_SIZE) 106 | { 107 | if ((done + todo) != bytesToWrite) 108 | { 109 | pData->ReadPointer = 0; 110 | return -2; //Data should be fed in multiples of MINIMUM_PROGRAMMED_BLOCK_SIZE except for the last block, otherwise the underlying algorithm won't be able to handle it 111 | } 112 | int padding = MINIMUM_PROGRAMMED_BLOCK_SIZE - todo % MINIMUM_PROGRAMMED_BLOCK_SIZE; 113 | for (int i = 0; i < padding; i++) 114 | rp[todo++] = 0xFF; //Pad last page with 0xFFs 115 | } 116 | else 117 | { 118 | if (todo > maxBytesAtOnce) 119 | todo = maxBytesAtOnce; 120 | } 121 | 122 | int done_now = FLASHPlugin_DoProgramSync(startOffset + done, rp, todo); 123 | if (done_now != todo) 124 | { 125 | pData->ReadPointer = 0; 126 | return -3; 127 | } 128 | 129 | rp += todo; 130 | while (rp >= pEndOfData) 131 | rp -= bufferSize; 132 | 133 | pData->ReadPointer = rp; 134 | 135 | done += todo; 136 | } 137 | 138 | return done; 139 | } 140 | #else 141 | int FLASHPlugin_ProgramSync(unsigned startOffset, const void *pData, unsigned bytesToWrite) 142 | { 143 | if (bytesToWrite < MINIMUM_PROGRAMMED_BLOCK_SIZE) 144 | { 145 | memset((char *)pData + bytesToWrite, 0xFF, MINIMUM_PROGRAMMED_BLOCK_SIZE - bytesToWrite); 146 | bytesToWrite = MINIMUM_PROGRAMMED_BLOCK_SIZE; 147 | } 148 | 149 | return FLASHPlugin_DoProgramSync(startOffset, pData, bytesToWrite); 150 | } 151 | #endif 152 | 153 | 154 | #include 155 | #include 156 | #include 157 | 158 | void TestFLASHProgramming(unsigned base, unsigned size) 159 | { 160 | FLASHBankInfo info = FLASHPlugin_Probe(base, size, 0, 0); 161 | 162 | unsigned result = FLASHPlugin_EraseSectors(0, std::min(400, (int)info.BlockCount)); 163 | if (result <= 0) 164 | asm("bkpt 255"); 165 | 166 | #if FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 167 | 168 | FIFOHeader *pHeader = (FIFOHeader *)alloca(sizeof(FIFOHeader) + info.WriteBlockSize * 2); 169 | pHeader->WritePointer = pHeader->ReadPointer = (char *)(pHeader + 1); 170 | memset(pHeader + 1, 0x55, info.WriteBlockSize); 171 | pHeader->WritePointer += info.WriteBlockSize; 172 | 173 | //Normally OpenOCD will launch this method and then start updating pHeader->WritePointer while the method is running. 174 | //This test function pre-initializes WritePointer to indicate that exactly one block has been written to the buffer 175 | //so that the FLASHPlugin_ProgramAsync() will succeed without any further modifications. 176 | result = FLASHPlugin_ProgramAsync(0, pHeader, (char *)(pHeader + 1) + info.WriteBlockSize * 2, info.WriteBlockSize); 177 | if (result != info.WriteBlockSize) 178 | asm("bkpt 255"); 179 | 180 | //After FLASHPlugin_ProgramAsync() data, it should set the ReadPointer at the end of the consumed block. 181 | if(pHeader->ReadPointer != pHeader->WritePointer) 182 | asm("bkpt 255"); 183 | 184 | #else 185 | void *pData = (FIFOHeader *)alloca(info.WriteBlockSize); 186 | memset(pData, 0x55, info.WriteBlockSize); 187 | FLASHPlugin_ProgramSync(0, pData, info.WriteBlockSize); 188 | #endif 189 | } -------------------------------------------------------------------------------- /common/FLASHPluginInterface.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | /* 4 | The Sysprogs fork of OpenOCD uses an ELF file providing the functions below to automaticaly program external FLASH memories. 5 | The usual use scenario is shown below: 6 | 1. OpenOCD makes a backup of the RAM area needed by the image and loads the image 7 | 2. OpenOCD calls the entry point and waits until the image calls FLASHPlugin_InitDone() 8 | 3. OpenOCD calls FLASHPlugin_Probe() and FLASHPlugin_FindWorkArea() to query general information about the FLASH bank 9 | 4. OpenOCD calls FLASHPlugin_Unload() and then restores the RAM area occupied by the image and the work area. 10 | 11 | When gdb requests OpenOCD to write the FLASH memory, the following happens: 12 | 1. The plugin is loaded into the target again 13 | 2. OpenOCD calls FLASHPlugin_EraseSectors() 14 | 3. OpenOCD calls FLASHPlugin_ProgramAsync(). If it's not implemented, it calls FLASHPlugin_ProgramSync() several times instead. 15 | 16 | The FLASH plugin should be linked using the RAM version of the linker script for your device. OpenOCD will then automatically load 17 | the plugin into RAM, let it do the programming and restore the original RAM contents. 18 | */ 19 | 20 | //General information about the FLASH bank. Queried during initialization. 21 | struct FLASHBankInfo 22 | { 23 | //Address of the FLASH bank in the memory space 24 | unsigned BaseAddress; 25 | 26 | //Amount of independently erased blocks 27 | unsigned BlockCount; 28 | 29 | //Size of each block 30 | unsigned BlockSize; 31 | 32 | //Size of smallest independently writable block. All write operations will be rounded up to the 33 | //multiple of this value. If your FLASH does not have such a limiation, simply set it to 1. 34 | unsigned WriteBlockSize; 35 | }; 36 | 37 | //Information about the temporary memory region used to transfer data between PC and the plugin. 38 | //OpenOCD will automatically backup and restore it. 39 | struct WorkAreaInfo 40 | { 41 | void *Address; 42 | unsigned Size; 43 | }; 44 | 45 | //Control structure used control data flow to FLASHPlugin_ProgramAsync() 46 | struct FIFOHeader 47 | { 48 | char * volatile WritePointer; 49 | char * volatile ReadPointer; 50 | }; 51 | 52 | #ifdef __cplusplus 53 | class InterruptEnabler 54 | { 55 | public: 56 | InterruptEnabler() 57 | { 58 | asm("cpsie i"); 59 | } 60 | 61 | ~InterruptEnabler() 62 | { 63 | asm("cpsid i"); 64 | } 65 | }; 66 | #endif 67 | 68 | #ifdef __cplusplus 69 | extern "C" 70 | { 71 | #endif 72 | //This function checks the FLASH bank and returns the general information about it. The base, size, chipWidth and busWidth arguments come from the 73 | //arguments to the 'flash bank' command in OpenOCD and can be ignored or used to compute the FLASH parameters depending on the implementation. 74 | struct FLASHBankInfo FLASHPlugin_Probe(unsigned base, unsigned size, unsigned chipWidth, unsigned busWidth); 75 | 76 | //This function is called by OpenOCD to locate the region of RAM that will be used to transfer data between the PC and the plugin. 77 | //endOfStack points to the end of the stack area allocated by OpenOCD directly beyond the bounds of the image. It is not equal to the usual _estack that points to 78 | //the end of RAM. If the FLASH plugin is designed to run on several different devices with different RAM sizes, it can detect the end of RAM in this function and return 79 | //the area between the endOfStack and end of RAM as the work area. 80 | struct WorkAreaInfo FLASHPlugin_FindWorkArea(void *endOfStack); 81 | 82 | //This function simply erases 'sectorCount' sectors starting from 'firstSector'. It should return the amount of sectors successfully erased or a negative value to indicate an error. 83 | int FLASHPlugin_EraseSectors(unsigned firstSector, unsigned sectorCount); 84 | 85 | //This function is called when the plugin is to be unloaded. It should revert any changes to hardware made during initialization (e.g. disable previousl yenabled interrupts). 86 | //Note that OpenOCD will automatically backup/restore all memory occupied by the plugin image's sections, so the plugin can use global/static variables to record the previous hardware state. 87 | int FLASHPlugin_Unload(); 88 | 89 | //This optional function should program a block of memory at a given offset. 'startOffset' specifies offset in bytes from the beginning of the FLASH bank. 90 | //The function should return 0 on success, error code on failure. 91 | //WARNING: Only implement this function if you encounter problems with FLASHPlugin_ProgramAsync(). 92 | int FLASHPlugin_ProgramSync(unsigned startOffset, const void *pData, unsigned bytesToWrite); 93 | 94 | //This function performs asynchronous programming. OpenOCD will modify the WritePointer field of 'pData' each time it writes new data to the buffer and will expect the function to 95 | //update the ReadPointer field each time it reads a chunk of data. The WritePointer/ReadPointer will only be updated in multiples of WriteBlockSize returned in FLASHPlugin_Probe(). 96 | //The FLASH plugin framework provides a default implementation of this method in FLASHPluginCommon.cpp that calls FLASHPlugin_DoProgramSync() to perform the actual programming. 97 | int FLASHPlugin_ProgramAsync(unsigned startOffset, struct FIFOHeader *pData, const void *pEndOfData, unsigned bytesToWrite); 98 | 99 | //This function should be called by the plugin once it completes initialization. The contents of the function is arbitrary. OpenOCD will set a breakpoint in this function to detect 100 | //when the initialization completes. Once the breakpoint triggers, OpenOCD will intercept the program flow and call various FLASHPlugin() functions. 101 | void __attribute__((noinline)) FLASHPlugin_InitDone(); 102 | 103 | //Non-implemented optional methods will be automatically defined as references to this method. 104 | //OpenOCD will detect this and understand that the methods are not implemented. 105 | int __attribute__((noinline)) FLASHPlugin_NotImplemented(); 106 | 107 | //Optional functions 108 | int FLASHPlugin_CheckSectorProtection(unsigned firstSector, unsigned sectorCount, unsigned char *pBuffer); 109 | int FLASHPlugin_ProtectSectors(unsigned protect, unsigned firstSector, unsigned sectorCount); 110 | 111 | //This function is called by FLASHPlugin_ProgramAsync() to perform the actual programming. It should return the amount of bytes successfully programmed or a negative value to indicate an error. 112 | //The bytesToWrite will always be a multiple of WriteBlockSize except for the last block. 113 | int FLASHPlugin_DoProgramSync(unsigned startOffset, const void *pData, int bytesToWrite); 114 | #ifdef __cplusplus 115 | } 116 | #endif 117 | 118 | //Test interface 119 | #ifdef __cplusplus 120 | extern "C" 121 | { 122 | #endif 123 | //This function will try programming fixed values into the FLASH memory using the interface functions as if OpenOCD was calling them. 124 | //Step through it in the debugger to test out your FLASH driver. It is NOT a part of the API called by OpenOCD. 125 | void TestFLASHProgramming(unsigned base, unsigned size); 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | -------------------------------------------------------------------------------- /iMXRT1050_HyperFLASH_ROMAPI.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/iMXRT1050_HyperFLASH_ROMAPI.elf -------------------------------------------------------------------------------- /iMXRT1064_Internal_ROMAPI.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/iMXRT1064_Internal_ROMAPI.elf -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.15) 2 | 3 | project(IMXRT1050_HyperFLASH_ROMAPI LANGUAGES C CXX ASM) 4 | 5 | find_bsp(ID com.sysprogs.imported.ksdk2x.MIMXRT1052xxxxB 6 | VERSION 2.9.1 7 | MCU MIMXRT1052DVL6B 8 | CONFIGURATION 9 | com.sysprogs.imported.ksdk2x.linker_script=devices/MIMXRT1052/gcc/MIMXRT1052xxxxx_ram.ld 10 | com.sysprogs.bspoptions.arm.floatmode=-mfloat-abi=hard 11 | FRAMEWORKS 12 | com.sysprogs.ksdk2x_imported.platform.Include_common.MIMXRT1052 13 | com.sysprogs.ksdk2x_imported.platform.Include_core_cm7.MIMXRT1052 14 | com.sysprogs.ksdk2x_imported.platform.Include_dsp.MIMXRT1052 15 | com.sysprogs.ksdk2x_imported.component.lists.MIMXRT1052 16 | com.sysprogs.ksdk2x_imported.component.lpuart_adapter.MIMXRT1052 17 | com.sysprogs.ksdk2x_imported.device.MIMXRT1052_CMSIS.MIMXRT1052 18 | com.sysprogs.ksdk2x_imported.device.MIMXRT1052_startup.MIMXRT1052 19 | com.sysprogs.ksdk2x_imported.device.MIMXRT1052_system.MIMXRT1052 20 | com.sysprogs.ksdk2x_imported.platform.drivers.cache_armv7_m7.MIMXRT1052 21 | com.sysprogs.ksdk2x_imported.platform.drivers.clock.MIMXRT1052 22 | com.sysprogs.ksdk2x_imported.platform.drivers.common.MIMXRT1052 23 | com.sysprogs.ksdk2x_imported.platform.drivers.igpio.MIMXRT1052 24 | com.sysprogs.ksdk2x_imported.platform.drivers.iomuxc.MIMXRT1052 25 | com.sysprogs.ksdk2x_imported.platform.drivers.lpuart.MIMXRT1052 26 | com.sysprogs.ksdk2x_imported.driver.romapi.MIMXRT1052 27 | com.sysprogs.ksdk2x_imported.platform.drivers.xip_board.MIMXRT1052 28 | com.sysprogs.ksdk2x_imported.platform.drivers.xip_device.MIMXRT1052 29 | com.sysprogs.ksdk2x_imported.platform.utilities.misc_utilities.MIMXRT1052 30 | HWREGISTER_LIST_FILE devices/MIMXRT1052/MIMXRT1052.vgdbdevice 31 | C_STANDARD 99) 32 | 33 | bsp_include_directories(${BSP_ROOT}/boards/evkbimxrt1050/driver_examples/fsl_romapi) 34 | 35 | bsp_compile_definitions(CPU_MIMXRT1052DVL6B 36 | SDK_DEBUGCONSOLE=1 37 | XIP_EXTERNAL_FLASH=1 38 | XIP_BOOT_HEADER_ENABLE=1) 39 | 40 | add_bsp_based_executable(NAME IMXRT1050_HyperFLASH_ROMAPI 41 | SOURCES 42 | flexspi_romapi_ops.c 43 | main.cpp 44 | pin_mux.c 45 | board.c 46 | clock_config.c 47 | dcd.c 48 | pin_mux.h 49 | board.h 50 | clock_config.h 51 | dcd.h 52 | ../../common/FLASHPluginCommon.cpp 53 | system_MIMXRT1052.c 54 | GENERATE_BIN 55 | GENERATE_MAP 56 | LINKER_SCRIPT MIMXRT1052xxxxx_ram.ld) 57 | target_include_directories(IMXRT1050_HyperFLASH_ROMAPI PRIVATE ../../common .) 58 | set_source_files_properties(${BSP_ROOT}/devices/MIMXRT1052/system_MIMXRT1052.c PROPERTIES HEADER_FILE_ONLY TRUE) 59 | -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/FLASHPluginConfig.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #define FlexSpiInstance 0U 4 | #define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE 5 | #define FLASH_SIZE 0x4000000UL /* 64MBytes */ 6 | #define FLASH_PAGE_SIZE 512UL /* 512Bytes */ 7 | #define FLASH_SECTOR_SIZE 0x40000UL /* 256KBytes */ 8 | #define FLASH_BLOCK_SIZE 0x40000UL /* 256KBytes */ 9 | 10 | 11 | #define MINIMUM_PROGRAMMED_BLOCK_SIZE FLASH_PAGE_SIZE 12 | #define FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 0 -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/IMXRT1050_HyperFLASH_ROMAPI.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.30717.126 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{803FD0C6-D64E-4E16-9DC3-1DAEC859A3D2}") = "IMXRT1050_HyperFLASH_ROMAPI", "IMXRT1050_HyperFLASH_ROMAPI.vgdbcmake", "{43BE5FD6-E375-4075-A3BF-FFA820BE5263}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|VisualGDB = Debug|VisualGDB 11 | MinSizeRel|VisualGDB = MinSizeRel|VisualGDB 12 | Release|VisualGDB = Release|VisualGDB 13 | RelWithDebInfo|VisualGDB = RelWithDebInfo|VisualGDB 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.Debug|VisualGDB.ActiveCfg = Debug|VisualGDB 17 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.Debug|VisualGDB.Build.0 = Debug|VisualGDB 18 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.MinSizeRel|VisualGDB.ActiveCfg = MinSizeRel|VisualGDB 19 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.MinSizeRel|VisualGDB.Build.0 = MinSizeRel|VisualGDB 20 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.Release|VisualGDB.ActiveCfg = Release|VisualGDB 21 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.Release|VisualGDB.Build.0 = Release|VisualGDB 22 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.RelWithDebInfo|VisualGDB.ActiveCfg = RelWithDebInfo|VisualGDB 23 | {43BE5FD6-E375-4075-A3BF-FFA820BE5263}.RelWithDebInfo|VisualGDB.Build.0 = RelWithDebInfo|VisualGDB 24 | EndGlobalSection 25 | GlobalSection(SolutionProperties) = preSolution 26 | HideSolutionNode = FALSE 27 | EndGlobalSection 28 | GlobalSection(ExtensibilityGlobals) = postSolution 29 | SolutionGuid = {EFEE0677-0A56-44C7-B996-BABC85CD4712} 30 | EndGlobalSection 31 | EndGlobal 32 | -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/MIMXRT1052xxxxx_ram.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1052CVJ5B 4 | ** MIMXRT1052CVL5B 5 | ** MIMXRT1052DVJ6B 6 | ** MIMXRT1052DVL6B 7 | ** 8 | ** Compiler: GNU C Compiler 9 | ** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 10 | ** Version: rev. 1.0, 2018-09-21 11 | ** Build: b200110 12 | ** 13 | ** Abstract: 14 | ** Linker file for the GNU C Compiler 15 | ** 16 | ** Copyright 2016 Freescale Semiconductor, Inc. 17 | ** Copyright 2016-2020 NXP 18 | ** All rights reserved. 19 | ** 20 | ** SPDX-License-Identifier: BSD-3-Clause 21 | ** 22 | ** http: www.nxp.com 23 | ** mail: support@nxp.com 24 | ** 25 | ** ################################################################### 26 | */ 27 | 28 | /* Entry Point */ 29 | ENTRY(Reset_Handler) 30 | 31 | HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; 32 | STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; 33 | 34 | /* Specify the memory areas */ 35 | MEMORY 36 | { 37 | OCRAM (RWX) : ORIGIN = 0x20200000, LENGTH = 256K 38 | } 39 | 40 | /* Define output sections */ 41 | SECTIONS 42 | { 43 | /* The startup code goes first into internal RAM */ 44 | .interrupts : 45 | { 46 | __VECTOR_TABLE = .; 47 | __Vectors = .; 48 | . = ALIGN(4); 49 | KEEP(*(.isr_vector)) /* Startup code */ 50 | . = ALIGN(4); 51 | } > OCRAM 52 | 53 | /* The program code and other data goes into internal RAM */ 54 | .text : 55 | { 56 | . = ALIGN(4); 57 | *(.text) /* .text sections (code) */ 58 | *(.text*) /* .text* sections (code) */ 59 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 60 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 61 | *(.glue_7) /* glue arm to thumb code */ 62 | *(.glue_7t) /* glue thumb to arm code */ 63 | *(.eh_frame) 64 | KEEP (*(.init)) 65 | KEEP (*(.fini)) 66 | . = ALIGN(4); 67 | } > OCRAM 68 | 69 | .ARM.extab : 70 | { 71 | *(.ARM.extab* .gnu.linkonce.armextab.*) 72 | } > OCRAM 73 | 74 | .ARM : 75 | { 76 | __exidx_start = .; 77 | *(.ARM.exidx*) 78 | __exidx_end = .; 79 | } > OCRAM 80 | 81 | .ctors : 82 | { 83 | __CTOR_LIST__ = .; 84 | /* gcc uses crtbegin.o to find the start of 85 | the constructors, so we make sure it is 86 | first. Because this is a wildcard, it 87 | doesn't matter if the user does not 88 | actually link against crtbegin.o; the 89 | linker won't look for a file to match a 90 | wildcard. The wildcard also means that it 91 | doesn't matter which directory crtbegin.o 92 | is in. */ 93 | KEEP (*crtbegin.o(.ctors)) 94 | KEEP (*crtbegin?.o(.ctors)) 95 | /* We don't want to include the .ctor section from 96 | from the crtend.o file until after the sorted ctors. 97 | The .ctor section from the crtend file contains the 98 | end of ctors marker and it must be last */ 99 | KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) 100 | KEEP (*(SORT(.ctors.*))) 101 | KEEP (*(.ctors)) 102 | __CTOR_END__ = .; 103 | } > OCRAM 104 | 105 | .dtors : 106 | { 107 | __DTOR_LIST__ = .; 108 | KEEP (*crtbegin.o(.dtors)) 109 | KEEP (*crtbegin?.o(.dtors)) 110 | KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) 111 | KEEP (*(SORT(.dtors.*))) 112 | KEEP (*(.dtors)) 113 | __DTOR_END__ = .; 114 | } > OCRAM 115 | 116 | .preinit_array : 117 | { 118 | PROVIDE_HIDDEN (__preinit_array_start = .); 119 | KEEP (*(.preinit_array*)) 120 | PROVIDE_HIDDEN (__preinit_array_end = .); 121 | } > OCRAM 122 | 123 | .init_array : 124 | { 125 | PROVIDE_HIDDEN (__init_array_start = .); 126 | KEEP (*(SORT(.init_array.*))) 127 | KEEP (*(.init_array*)) 128 | PROVIDE_HIDDEN (__init_array_end = .); 129 | } > OCRAM 130 | 131 | .fini_array : 132 | { 133 | PROVIDE_HIDDEN (__fini_array_start = .); 134 | KEEP (*(SORT(.fini_array.*))) 135 | KEEP (*(.fini_array*)) 136 | PROVIDE_HIDDEN (__fini_array_end = .); 137 | } > OCRAM 138 | 139 | __etext = .; /* define a global symbol at end of code */ 140 | __DATA_ROM = .; /* Symbol is used by startup for data initialization */ 141 | 142 | 143 | .data : 144 | { 145 | . = ALIGN(4); 146 | __DATA_RAM = .; 147 | __data_start__ = .; /* create a global symbol at data start */ 148 | *(m_usb_dma_init_data) 149 | *(.data) /* .data sections */ 150 | *(.data*) /* .data* sections */ 151 | KEEP(*(.jcr*)) 152 | . = ALIGN(4); 153 | __data_end__ = .; /* define a global symbol at data end */ 154 | } > OCRAM 155 | 156 | __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); 157 | .ncache.init : 158 | { 159 | __noncachedata_start__ = .; /* create a global symbol at ncache data start */ 160 | *(NonCacheable.init) 161 | . = ALIGN(4); 162 | __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ 163 | } > OCRAM 164 | . = __noncachedata_init_end__; 165 | .ncache : 166 | { 167 | *(NonCacheable) 168 | . = ALIGN(4); 169 | __noncachedata_end__ = .; /* define a global symbol at ncache data end */ 170 | } > OCRAM 171 | 172 | __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); 173 | 174 | /* Uninitialized data section */ 175 | .bss : 176 | { 177 | /* This is used by the startup in order to initialize the .bss section */ 178 | . = ALIGN(4); 179 | __START_BSS = .; 180 | __bss_start__ = .; 181 | *(m_usb_dma_noninit_data) 182 | *(.bss) 183 | *(.bss*) 184 | *(COMMON) 185 | . = ALIGN(4); 186 | __bss_end__ = .; 187 | __END_BSS = .; 188 | } > OCRAM 189 | 190 | .heap : 191 | { 192 | . = ALIGN(8); 193 | __end__ = .; 194 | PROVIDE(end = .); 195 | __HeapBase = .; 196 | . += HEAP_SIZE; 197 | __HeapLimit = .; 198 | __heap_limit = .; /* Add for _sbrk */ 199 | } > OCRAM 200 | 201 | .stack : 202 | { 203 | . = ALIGN(8); 204 | . += STACK_SIZE; 205 | } > OCRAM 206 | 207 | /* Initializes stack on the end of block */ 208 | __StackTop = ORIGIN(OCRAM) + LENGTH(OCRAM); 209 | __StackLimit = __StackTop - STACK_SIZE; 210 | PROVIDE(__stack = __StackTop); 211 | 212 | .ARM.attributes 0 : { *(.ARM.attributes) } 213 | 214 | ASSERT(__StackLimit >= __HeapLimit, "region OCRAM overflowed with stack and heap") 215 | } 216 | 217 | -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/clock_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2017-2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | #ifndef _CLOCK_CONFIG_H_ 8 | #define _CLOCK_CONFIG_H_ 9 | 10 | #include "fsl_common.h" 11 | 12 | /******************************************************************************* 13 | * Definitions 14 | ******************************************************************************/ 15 | #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 16 | 17 | #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 18 | /******************************************************************************* 19 | ************************ BOARD_InitBootClocks function ************************ 20 | ******************************************************************************/ 21 | 22 | #if defined(__cplusplus) 23 | extern "C" { 24 | #endif /* __cplusplus*/ 25 | 26 | /*! 27 | * @brief This function executes default configuration of clocks. 28 | * 29 | */ 30 | void BOARD_InitBootClocks(void); 31 | 32 | #if defined(__cplusplus) 33 | } 34 | #endif /* __cplusplus*/ 35 | 36 | /******************************************************************************* 37 | ********************** Configuration BOARD_BootClockRUN *********************** 38 | ******************************************************************************/ 39 | /******************************************************************************* 40 | * Definitions for BOARD_BootClockRUN configuration 41 | ******************************************************************************/ 42 | #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ 43 | 44 | /* Clock outputs (values are in Hz): */ 45 | #define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL 46 | #define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL 47 | #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL 48 | #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL 49 | #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL 50 | #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 51 | #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL 52 | #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL 53 | #define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL 54 | #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL 55 | #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL 56 | #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL 57 | #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL 58 | #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL 59 | #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL 60 | #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL 61 | #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL 62 | #define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL 63 | #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL 64 | #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL 65 | #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL 66 | #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL 67 | #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL 68 | #define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL 69 | #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL 70 | #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL 71 | #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL 72 | #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL 73 | #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL 74 | #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL 75 | #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL 76 | #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL 77 | #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL 78 | #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL 79 | #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 80 | #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL 81 | #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL 82 | #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL 83 | #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL 84 | #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL 85 | #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL 86 | #define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL 87 | #define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL 88 | #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL 89 | #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL 90 | 91 | /*! @brief Arm PLL set for BOARD_BootClockRUN configuration. 92 | */ 93 | extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; 94 | /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. 95 | */ 96 | extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; 97 | /*! @brief Sys PLL for BOARD_BootClockRUN configuration. 98 | */ 99 | extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; 100 | /*! @brief Video PLL set for BOARD_BootClockRUN configuration. 101 | */ 102 | extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; 103 | 104 | /******************************************************************************* 105 | * API for BOARD_BootClockRUN configuration 106 | ******************************************************************************/ 107 | #if defined(__cplusplus) 108 | extern "C" { 109 | #endif /* __cplusplus*/ 110 | 111 | /*! 112 | * @brief This function executes configuration of clocks. 113 | * 114 | */ 115 | void BOARD_BootClockRUN(void); 116 | 117 | #if defined(__cplusplus) 118 | } 119 | #endif /* __cplusplus*/ 120 | 121 | #endif /* _CLOCK_CONFIG_H_ */ 122 | 123 | -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/dcd.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | 13 | #ifndef __DCD__ 14 | #define __DCD__ 15 | 16 | #include 17 | 18 | /*! @name Driver version */ 19 | /*@{*/ 20 | /*! @brief XIP_BOARD driver version 2.0.1. */ 21 | #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 22 | /*@}*/ 23 | 24 | /************************************* 25 | * DCD Data 26 | *************************************/ 27 | #define DCD_TAG_HEADER (0xD2) 28 | #define DCD_VERSION (0x41) 29 | #define DCD_TAG_HEADER_SHIFT (24) 30 | #define DCD_ARRAY_SIZE 1 31 | 32 | #endif /* __DCD__ */ 33 | -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/flexspi_romapi_ops.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | #include "fsl_romapi.h" 9 | 10 | #if !defined(XIP_EXTERNAL_FLASH) || (XIP_EXTERNAL_FLASH != 1) 11 | /******************************************************************************* 12 | * Definitions 13 | ******************************************************************************/ 14 | #define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 6U 15 | #define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 7U 16 | 17 | /******************************************************************************* 18 | * Prototypes 19 | ******************************************************************************/ 20 | static status_t FLEXSPI_NorFlash_HyperBusWrite(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes); 21 | static status_t FLEXSPI_NorFlash_HyperBusRead(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes); 22 | 23 | /******************************************************************************* 24 | * Variables 25 | ******************************************************************************/ 26 | 27 | /******************************************************************************* 28 | * Code 29 | ******************************************************************************/ 30 | 31 | static status_t FLEXSPI_NorFlash_HyperBusWrite(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes) 32 | { 33 | flexspi_xfer_t xfer; 34 | xfer.operation = kFLEXSPIOperation_Write; 35 | xfer.seqId = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA; 36 | xfer.seqNum = 1U; 37 | xfer.baseAddress = addr * 2U; // word address for HyperFlash 38 | xfer.isParallelModeEnable = false; 39 | xfer.txBuffer = buffer; 40 | xfer.txSize = bytes; 41 | 42 | status_t status = ROM_FLEXSPI_NorFlash_CommandXfer(instance, &xfer); 43 | 44 | return status; 45 | } 46 | 47 | static status_t FLEXSPI_NorFlash_HyperBusRead(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes) 48 | { 49 | flexspi_xfer_t xfer; 50 | xfer.operation = kFLEXSPIOperation_Read; 51 | xfer.seqId = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA; 52 | xfer.seqNum = 1U; 53 | xfer.baseAddress = addr * 2U; // word address for HyperFlash 54 | xfer.isParallelModeEnable = false; 55 | xfer.rxBuffer = buffer; 56 | xfer.rxSize = bytes; 57 | 58 | status_t status = ROM_FLEXSPI_NorFlash_CommandXfer(instance, &xfer); 59 | 60 | return status; 61 | } 62 | 63 | /* 64 | * @brief Read ID-CFI Parameters 65 | */ 66 | status_t FLEXSPI_NorFlash_VerifyID(uint32_t instance) 67 | { 68 | status_t status = kStatus_InvalidArgument; 69 | uint32_t lut_seq[4]; 70 | 71 | memset(lut_seq, 0, sizeof(lut_seq)); 72 | // Write 73 | lut_seq[0] = FSL_ROM_FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x20, RADDR_DDR, FLEXSPI_8PAD, 0x18); 74 | lut_seq[1] = FSL_ROM_FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, WRITE_DDR, FLEXSPI_8PAD, 0x02); 75 | ROM_FLEXSPI_NorFlash_UpdateLut(instance, HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA, (const uint32_t *)lut_seq, 1U); 76 | 77 | // Read 78 | memset(lut_seq, 0, sizeof(lut_seq)); 79 | lut_seq[0] = FSL_ROM_FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18); 80 | lut_seq[1] = FSL_ROM_FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, READ_DDR, FLEXSPI_8PAD, 0x04); 81 | ROM_FLEXSPI_NorFlash_UpdateLut(instance, HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA, (const uint32_t *)lut_seq, 1U); 82 | 83 | // CFI Entry 84 | uint32_t buffer[2]; 85 | uint8_t data[4] = {0x00, 0x98}; 86 | status = FLEXSPI_NorFlash_HyperBusWrite(instance, 0x555U, (uint32_t *)data, 2U); 87 | if (status != kStatus_Success) 88 | { 89 | return status; 90 | } 91 | 92 | // ID-CFI Read 93 | // Read Query Unique ASCII String 94 | status = FLEXSPI_NorFlash_HyperBusRead(instance, 0x10U, &buffer[0], sizeof(buffer)); 95 | if (status != kStatus_Success) 96 | { 97 | return status; 98 | } 99 | 100 | buffer[1] &= 0xFFFF; 101 | // Check that the data read out is unicode "QRY" in big-endian order 102 | if ((buffer[0] != 0x52005100U) || (buffer[1] != 0x5900U)) 103 | { 104 | status = kStatus_ROM_FLEXSPINOR_Flash_NotFound; 105 | return status; 106 | } 107 | // ASO Exit 0xF000 108 | data[1] = 0xF0U; 109 | status = FLEXSPI_NorFlash_HyperBusWrite(instance, 0x0U, (uint32_t *)data, 2U); 110 | if (status != kStatus_Success) 111 | { 112 | return status; 113 | } 114 | 115 | return status; 116 | } 117 | #endif // XIP_EXTERNAL_FLASH 118 | -------------------------------------------------------------------------------- /imxrt/IMXRT1050_HyperFLASH_ROMAPI/pin_mux.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2017-2018 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | 13 | #ifndef _PIN_MUX_H_ 14 | #define _PIN_MUX_H_ 15 | 16 | /*********************************************************************************************************************** 17 | * Definitions 18 | **********************************************************************************************************************/ 19 | 20 | /*! @brief Direction type */ 21 | typedef enum _pin_mux_direction 22 | { 23 | kPIN_MUX_DirectionInput = 0U, /* Input direction */ 24 | kPIN_MUX_DirectionOutput = 1U, /* Output direction */ 25 | kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ 26 | } pin_mux_direction_t; 27 | 28 | /*! 29 | * @addtogroup pin_mux 30 | * @{ 31 | */ 32 | 33 | /*********************************************************************************************************************** 34 | * API 35 | **********************************************************************************************************************/ 36 | 37 | #if defined(__cplusplus) 38 | extern "C" { 39 | #endif 40 | 41 | /*! 42 | * @brief Calls initialization functions. 43 | * 44 | */ 45 | void BOARD_InitBootPins(void); 46 | 47 | 48 | /*! 49 | * @brief Configures pin routing and optionally pin electrical features. 50 | * 51 | */ 52 | void BOARD_InitPins(void); 53 | 54 | #if defined(__cplusplus) 55 | } 56 | #endif 57 | 58 | /*! 59 | * @} 60 | */ 61 | #endif /* _PIN_MUX_H_ */ 62 | 63 | /*********************************************************************************************************************** 64 | * EOF 65 | **********************************************************************************************************************/ 66 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.15) 2 | 3 | project(iMXRT1064_Internal_ROMAPI LANGUAGES C CXX ASM) 4 | 5 | find_bsp(ID com.sysprogs.imported.ksdk2x.MIMXRT1064xxxxA 6 | VERSION 2.9.1 7 | MCU MIMXRT1064DVL6A 8 | CONFIGURATION 9 | com.sysprogs.imported.ksdk2x.linker_script=devices/MIMXRT1064/gcc/MIMXRT1064xxxxx_ram.ld 10 | com.sysprogs.bspoptions.arm.floatmode=-mfloat-abi=hard 11 | FRAMEWORKS 12 | com.sysprogs.ksdk2x_imported.platform.Include_common.MIMXRT1064 13 | com.sysprogs.ksdk2x_imported.platform.Include_core_cm7.MIMXRT1064 14 | com.sysprogs.ksdk2x_imported.platform.Include_dsp.MIMXRT1064 15 | com.sysprogs.ksdk2x_imported.component.lists.MIMXRT1064 16 | com.sysprogs.ksdk2x_imported.device.MIMXRT1064_CMSIS.MIMXRT1064 17 | com.sysprogs.ksdk2x_imported.device.MIMXRT1064_startup.MIMXRT1064 18 | com.sysprogs.ksdk2x_imported.device.MIMXRT1064_system.MIMXRT1064 19 | com.sysprogs.ksdk2x_imported.platform.drivers.cache_armv7_m7.MIMXRT1064 20 | com.sysprogs.ksdk2x_imported.platform.drivers.clock.MIMXRT1064 21 | com.sysprogs.ksdk2x_imported.platform.drivers.common.MIMXRT1064 22 | com.sysprogs.ksdk2x_imported.platform.drivers.igpio.MIMXRT1064 23 | com.sysprogs.ksdk2x_imported.platform.drivers.iomuxc.MIMXRT1064 24 | com.sysprogs.ksdk2x_imported.driver.romapi.MIMXRT1064 25 | com.sysprogs.ksdk2x_imported.platform.drivers.xip_board.MIMXRT1064 26 | com.sysprogs.ksdk2x_imported.platform.drivers.xip_device.MIMXRT1064 27 | com.sysprogs.ksdk2x_imported.platform.utilities.misc_utilities.MIMXRT1064 28 | HWREGISTER_LIST_FILE devices/MIMXRT1064/MIMXRT1064.vgdbdevice 29 | C_STANDARD 99) 30 | 31 | bsp_include_directories(${BSP_ROOT}/boards/evkmimxrt1064/driver_examples/fsl_romapi) 32 | 33 | bsp_compile_definitions(CPU_MIMXRT1064DVL6A 34 | SDK_DEBUGCONSOLE=1 35 | XIP_EXTERNAL_FLASH=1 36 | XIP_BOOT_HEADER_ENABLE=1) 37 | 38 | add_bsp_based_executable(NAME iMXRT1064_Internal_ROMAPI 39 | SOURCES 40 | main.cpp 41 | pin_mux.c 42 | board.c 43 | clock_config.c 44 | dcd.c 45 | pin_mux.h 46 | board.h 47 | clock_config.h 48 | dcd.h 49 | ../../common/FLASHPluginCommon.cpp 50 | system_MIMXRT1064.c 51 | GENERATE_BIN 52 | GENERATE_MAP 53 | LINKER_SCRIPT MIMXRT1064xxxxx_ram.ld) 54 | 55 | target_include_directories(iMXRT1064_Internal_ROMAPI PRIVATE ../../common .) 56 | set_source_files_properties(${BSP_ROOT}/devices/MIMXRT1064/system_MIMXRT1064.c PROPERTIES HEADER_FILE_ONLY TRUE) 57 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/FLASHPluginConfig.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #define FlexSpiInstance 1U 4 | #define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI2_AMBA_BASE 5 | #define FLASH_SIZE 0x400000UL /* 4MBytes */ 6 | #define FLASH_PAGE_SIZE 256UL /* 256Bytes */ 7 | #define FLASH_SECTOR_SIZE 0x1000UL /* 4KBytes */ 8 | #define FLASH_BLOCK_SIZE 0x10000UL /* 64KBytes */ 9 | 10 | #define MINIMUM_PROGRAMMED_BLOCK_SIZE FLASH_PAGE_SIZE 11 | #define FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 1 -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/MIMXRT1064xxxxx_ram.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1064CVJ5A 4 | ** MIMXRT1064CVL5A 5 | ** MIMXRT1064DVJ6A 6 | ** MIMXRT1064DVL6A 7 | ** 8 | ** Compiler: GNU C Compiler 9 | ** Reference manual: IMXRT1064RM Rev.0.1, 12/2018 | IMXRT1064SRM Rev.3 10 | ** Version: rev. 0.1, 2018-06-22 11 | ** Build: b200110 12 | ** 13 | ** Abstract: 14 | ** Linker file for the GNU C Compiler 15 | ** 16 | ** Copyright 2016 Freescale Semiconductor, Inc. 17 | ** Copyright 2016-2020 NXP 18 | ** All rights reserved. 19 | ** 20 | ** SPDX-License-Identifier: BSD-3-Clause 21 | ** 22 | ** http: www.nxp.com 23 | ** mail: support@nxp.com 24 | ** 25 | ** ################################################################### 26 | */ 27 | 28 | /* Entry Point */ 29 | ENTRY(Reset_Handler) 30 | 31 | HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; 32 | STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; 33 | 34 | /* Specify the memory areas */ 35 | MEMORY 36 | { 37 | OCRAM (RWX) : ORIGIN = 0x20200000, LENGTH = 256K 38 | } 39 | 40 | /* Define output sections */ 41 | SECTIONS 42 | { 43 | /* The startup code goes first into internal RAM */ 44 | .interrupts : 45 | { 46 | __VECTOR_TABLE = .; 47 | __Vectors = .; 48 | . = ALIGN(4); 49 | KEEP(*(.isr_vector)) /* Startup code */ 50 | . = ALIGN(4); 51 | } > OCRAM 52 | 53 | /* The program code and other data goes into internal RAM */ 54 | .text : 55 | { 56 | . = ALIGN(4); 57 | *(.text) /* .text sections (code) */ 58 | *(.text*) /* .text* sections (code) */ 59 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 60 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 61 | *(.glue_7) /* glue arm to thumb code */ 62 | *(.glue_7t) /* glue thumb to arm code */ 63 | *(.eh_frame) 64 | KEEP (*(.init)) 65 | KEEP (*(.fini)) 66 | . = ALIGN(4); 67 | } > OCRAM 68 | 69 | .ARM.extab : 70 | { 71 | *(.ARM.extab* .gnu.linkonce.armextab.*) 72 | } > OCRAM 73 | 74 | .ARM : 75 | { 76 | __exidx_start = .; 77 | *(.ARM.exidx*) 78 | __exidx_end = .; 79 | } > OCRAM 80 | 81 | .ctors : 82 | { 83 | __CTOR_LIST__ = .; 84 | /* gcc uses crtbegin.o to find the start of 85 | the constructors, so we make sure it is 86 | first. Because this is a wildcard, it 87 | doesn't matter if the user does not 88 | actually link against crtbegin.o; the 89 | linker won't look for a file to match a 90 | wildcard. The wildcard also means that it 91 | doesn't matter which directory crtbegin.o 92 | is in. */ 93 | KEEP (*crtbegin.o(.ctors)) 94 | KEEP (*crtbegin?.o(.ctors)) 95 | /* We don't want to include the .ctor section from 96 | from the crtend.o file until after the sorted ctors. 97 | The .ctor section from the crtend file contains the 98 | end of ctors marker and it must be last */ 99 | KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) 100 | KEEP (*(SORT(.ctors.*))) 101 | KEEP (*(.ctors)) 102 | __CTOR_END__ = .; 103 | } > OCRAM 104 | 105 | .dtors : 106 | { 107 | __DTOR_LIST__ = .; 108 | KEEP (*crtbegin.o(.dtors)) 109 | KEEP (*crtbegin?.o(.dtors)) 110 | KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) 111 | KEEP (*(SORT(.dtors.*))) 112 | KEEP (*(.dtors)) 113 | __DTOR_END__ = .; 114 | } > OCRAM 115 | 116 | .preinit_array : 117 | { 118 | PROVIDE_HIDDEN (__preinit_array_start = .); 119 | KEEP (*(.preinit_array*)) 120 | PROVIDE_HIDDEN (__preinit_array_end = .); 121 | } > OCRAM 122 | 123 | .init_array : 124 | { 125 | PROVIDE_HIDDEN (__init_array_start = .); 126 | KEEP (*(SORT(.init_array.*))) 127 | KEEP (*(.init_array*)) 128 | PROVIDE_HIDDEN (__init_array_end = .); 129 | } > OCRAM 130 | 131 | .fini_array : 132 | { 133 | PROVIDE_HIDDEN (__fini_array_start = .); 134 | KEEP (*(SORT(.fini_array.*))) 135 | KEEP (*(.fini_array*)) 136 | PROVIDE_HIDDEN (__fini_array_end = .); 137 | } > OCRAM 138 | 139 | __etext = .; /* define a global symbol at end of code */ 140 | __DATA_ROM = .; /* Symbol is used by startup for data initialization */ 141 | 142 | .data : 143 | { 144 | . = ALIGN(4); 145 | __DATA_RAM = .; 146 | __data_start__ = .; /* create a global symbol at data start */ 147 | *(m_usb_dma_init_data) 148 | *(.data) /* .data sections */ 149 | *(.data*) /* .data* sections */ 150 | KEEP(*(.jcr*)) 151 | . = ALIGN(4); 152 | __data_end__ = .; /* define a global symbol at data end */ 153 | } > OCRAM 154 | __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); 155 | .ncache.init : 156 | { 157 | __noncachedata_start__ = .; /* create a global symbol at ncache data start */ 158 | *(NonCacheable.init) 159 | . = ALIGN(4); 160 | __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ 161 | } > OCRAM 162 | . = __noncachedata_init_end__; 163 | .ncache : 164 | { 165 | *(NonCacheable) 166 | . = ALIGN(4); 167 | __noncachedata_end__ = .; /* define a global symbol at ncache data end */ 168 | } > OCRAM 169 | 170 | __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); 171 | 172 | /* Uninitialized data section */ 173 | .bss : 174 | { 175 | /* This is used by the startup in order to initialize the .bss section */ 176 | . = ALIGN(4); 177 | __START_BSS = .; 178 | __bss_start__ = .; 179 | *(m_usb_dma_noninit_data) 180 | *(.bss) 181 | *(.bss*) 182 | *(COMMON) 183 | . = ALIGN(4); 184 | __bss_end__ = .; 185 | __END_BSS = .; 186 | } > OCRAM 187 | 188 | .heap : 189 | { 190 | . = ALIGN(8); 191 | __end__ = .; 192 | PROVIDE(end = .); 193 | __HeapBase = .; 194 | . += HEAP_SIZE; 195 | __HeapLimit = .; 196 | __heap_limit = .; /* Add for _sbrk */ 197 | } > OCRAM 198 | 199 | .stack : 200 | { 201 | . = ALIGN(8); 202 | . += STACK_SIZE; 203 | } > OCRAM 204 | 205 | /* Initializes stack on the end of block */ 206 | __StackTop = ORIGIN(OCRAM) + LENGTH(OCRAM); 207 | __StackLimit = __StackTop - STACK_SIZE; 208 | PROVIDE(__stack = __StackTop); 209 | 210 | .ARM.attributes 0 : { *(.ARM.attributes) } 211 | 212 | ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") 213 | } 214 | 215 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/clock_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018-2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | #ifndef _CLOCK_CONFIG_H_ 9 | #define _CLOCK_CONFIG_H_ 10 | 11 | #include "fsl_common.h" 12 | 13 | /******************************************************************************* 14 | * Definitions 15 | ******************************************************************************/ 16 | #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 17 | 18 | #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 19 | /******************************************************************************* 20 | ************************ BOARD_InitBootClocks function ************************ 21 | ******************************************************************************/ 22 | 23 | #if defined(__cplusplus) 24 | extern "C" { 25 | #endif /* __cplusplus*/ 26 | 27 | /*! 28 | * @brief This function executes default configuration of clocks. 29 | * 30 | */ 31 | void BOARD_InitBootClocks(void); 32 | 33 | #if defined(__cplusplus) 34 | } 35 | #endif /* __cplusplus*/ 36 | 37 | /******************************************************************************* 38 | ********************** Configuration BOARD_BootClockRUN *********************** 39 | ******************************************************************************/ 40 | /******************************************************************************* 41 | * Definitions for BOARD_BootClockRUN configuration 42 | ******************************************************************************/ 43 | #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ 44 | 45 | /* Clock outputs (values are in Hz): */ 46 | #define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL 47 | #define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL 48 | #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL 49 | #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL 50 | #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL 51 | #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 52 | #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL 53 | #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL 54 | #define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL 55 | #define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL 56 | #define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL 57 | #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL 58 | #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL 59 | #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL 60 | #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL 61 | #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL 62 | #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL 63 | #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL 64 | #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL 65 | #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL 66 | #define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL 67 | #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL 68 | #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL 69 | #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL 70 | #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL 71 | #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL 72 | #define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL 73 | #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL 74 | #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL 75 | #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL 76 | #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL 77 | #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL 78 | #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL 79 | #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL 80 | #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL 81 | #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL 82 | #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL 83 | #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 84 | #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL 85 | #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL 86 | #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL 87 | #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL 88 | #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL 89 | #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL 90 | #define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL 91 | #define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL 92 | #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL 93 | #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL 94 | 95 | /*! @brief Arm PLL set for BOARD_BootClockRUN configuration. 96 | */ 97 | extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; 98 | /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. 99 | */ 100 | extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; 101 | /*! @brief Sys PLL for BOARD_BootClockRUN configuration. 102 | */ 103 | extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; 104 | /*! @brief Video PLL set for BOARD_BootClockRUN configuration. 105 | */ 106 | extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; 107 | 108 | /******************************************************************************* 109 | * API for BOARD_BootClockRUN configuration 110 | ******************************************************************************/ 111 | #if defined(__cplusplus) 112 | extern "C" { 113 | #endif /* __cplusplus*/ 114 | 115 | /*! 116 | * @brief This function executes configuration of clocks. 117 | * 118 | */ 119 | void BOARD_BootClockRUN(void); 120 | 121 | #if defined(__cplusplus) 122 | } 123 | #endif /* __cplusplus*/ 124 | 125 | #endif /* _CLOCK_CONFIG_H_ */ 126 | 127 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/dcd.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | 13 | #ifndef __DCD__ 14 | #define __DCD__ 15 | 16 | #include 17 | 18 | /*! @name Driver version */ 19 | /*@{*/ 20 | /*! @brief XIP_BOARD driver version 2.0.1. */ 21 | #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 22 | /*@}*/ 23 | 24 | /************************************* 25 | * DCD Data 26 | *************************************/ 27 | #define DCD_TAG_HEADER (0xD2) 28 | #define DCD_VERSION (0x41) 29 | #define DCD_TAG_HEADER_SHIFT (24) 30 | #define DCD_ARRAY_SIZE 1 31 | 32 | #endif /* __DCD__ */ 33 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/iMXRT1064_Internal_ROMAPI.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.30717.126 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{803FD0C6-D64E-4E16-9DC3-1DAEC859A3D2}") = "iMXRT1064_Internal_ROMAPI", "iMXRT1064_Internal_ROMAPI.vgdbcmake", "{17910AC3-0947-40B7-B621-66CDE51C9190}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|VisualGDB = Debug|VisualGDB 11 | MinSizeRel|VisualGDB = MinSizeRel|VisualGDB 12 | Release|VisualGDB = Release|VisualGDB 13 | RelWithDebInfo|VisualGDB = RelWithDebInfo|VisualGDB 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {17910AC3-0947-40B7-B621-66CDE51C9190}.Debug|VisualGDB.ActiveCfg = Debug|VisualGDB 17 | {17910AC3-0947-40B7-B621-66CDE51C9190}.Debug|VisualGDB.Build.0 = Debug|VisualGDB 18 | {17910AC3-0947-40B7-B621-66CDE51C9190}.MinSizeRel|VisualGDB.ActiveCfg = MinSizeRel|VisualGDB 19 | {17910AC3-0947-40B7-B621-66CDE51C9190}.MinSizeRel|VisualGDB.Build.0 = MinSizeRel|VisualGDB 20 | {17910AC3-0947-40B7-B621-66CDE51C9190}.Release|VisualGDB.ActiveCfg = Release|VisualGDB 21 | {17910AC3-0947-40B7-B621-66CDE51C9190}.Release|VisualGDB.Build.0 = Release|VisualGDB 22 | {17910AC3-0947-40B7-B621-66CDE51C9190}.RelWithDebInfo|VisualGDB.ActiveCfg = RelWithDebInfo|VisualGDB 23 | {17910AC3-0947-40B7-B621-66CDE51C9190}.RelWithDebInfo|VisualGDB.Build.0 = RelWithDebInfo|VisualGDB 24 | EndGlobalSection 25 | GlobalSection(SolutionProperties) = preSolution 26 | HideSolutionNode = FALSE 27 | EndGlobalSection 28 | GlobalSection(ExtensibilityGlobals) = postSolution 29 | SolutionGuid = {D6CF96B0-C9F9-4872-8FD4-F9285127A296} 30 | EndGlobalSection 31 | EndGlobal 32 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/iMXRT1064_Internal_ROMAPI.vgdbcmake: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | MinGWUnixSlash 7 | $(ToolchainDir) 8 | 9 | true 10 | $(ProjectDir) 11 | false 12 | DeviceDefinition 13 | 14 | 15 | 16 | 17 | com.visualgdb.arm-eabi 18 | 19 | 9.3.1 20 | 9.2.0 21 | 2 22 | 23 | 24 | 25 | DEBUG 26 | build/$(PlatformName)/$(ConfigurationName) 27 | 28 | false 29 | 30 | BuildMachine 31 | BuiltinShortcut 32 | 33 | $(VISUALGDB_DIR)/ninja.exe 34 | $(BuildDir) 35 | 36 | 37 | 38 | false 39 | 40 | BuildMachine 41 | BuiltinShortcut 42 | 43 | $(SYSPROGS_CMAKE_PATH) 44 | 45 | 46 | true 47 | false 48 | false 49 | Ninja 50 | false 51 | RemoveBuildDirectory 52 | false 53 | 54 | 55 | true 56 | true 57 | true 58 | false 59 | true 60 | false 61 | true 62 | HideOuterProjectTargets 63 | true 64 | false 65 | true 66 | 67 | 68 | true 69 | 17910ac3-0947-40b7-b621-66cde51c9190 70 | 71 | Upper 72 | None 73 | true 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | Default 88 | 89 | 90 | 91 | true 92 | 93 | 94 | 95 | 96 | Unknown 97 | 98 | true 99 | true 100 | true 101 | 102 | 103 | 104 | false 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | false 114 | false 115 | false 116 | false 117 | false 118 | false 119 | false 120 | false 121 | false 122 | 123 | false 124 | false 125 | false 126 | false 127 | false 128 | false 129 | true 130 | false 131 | None 132 | false 133 | false 134 | main 135 | true 136 | false 137 | false 138 | false 139 | 0 140 | true 141 | 142 | 143 | com.sysprogs.arm.openocd 144 | cmsis-dap 145 | 0227000040214E4500291019C892002E9E11000097969900 146 | 147 | -f interface/cmsis-dap.cfg -f target/imxrt.cfg -c "adapter speed 3000" -c init -c "reset init" 148 | 149 | 150 | 151 | false 152 | 153 | 131072 154 | Enabled 155 | 156 | set remotetimeout 60 157 | target remote :$$SYS:GDB_PORT$$ 158 | mon halt 159 | mon reset init 160 | load 161 | 162 | false 163 | 0 164 | 0 165 | false 166 | 167 | 168 | 169 | true 170 | Auto 171 | 0 172 | false 173 | false 174 | true 175 | false 176 | false 177 | 178 | _estack 179 | 0 180 | false 181 | 182 | true 183 | 184 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/main.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | #include "fsl_romapi.h" 8 | #include "fsl_cache.h" 9 | 10 | #include "pin_mux.h" 11 | #include "clock_config.h" 12 | #include "board.h" 13 | #include "fsl_common.h" 14 | #include 15 | #include 16 | 17 | /******************************************************************************* 18 | * Prototypes 19 | ******************************************************************************/ 20 | void error_trap(void); 21 | void app_finalize(void); 22 | status_t FLEXSPI_NorFlash_GetVendorID(uint32_t instance, uint32_t *vendorID); 23 | 24 | /******************************************************************************* 25 | * Variables 26 | ******************************************************************************/ 27 | 28 | /*! @brief FLEXSPI NOR flash driver Structure */ 29 | static flexspi_nor_config_t norConfig; 30 | 31 | void error_trap(void) 32 | { 33 | asm("bkpt 255"); 34 | } 35 | 36 | 37 | status_t FLEXSPI_NorFlash_GetVendorID(uint32_t instance, uint32_t *vendorID) 38 | { 39 | uint32_t lut_seq[4]; 40 | memset(lut_seq, 0, sizeof(lut_seq)); 41 | // Read manufacturer ID 42 | lut_seq[0] = FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x9F, READ_SDR, FLEXSPI_1PAD, 4); 43 | ROM_FLEXSPI_NorFlash_UpdateLut(instance, NOR_CMD_LUT_SEQ_IDX_READID, (const uint32_t *)lut_seq, 1U); 44 | 45 | flexspi_xfer_t xfer; 46 | xfer.operation = kFLEXSPIOperation_Read; 47 | xfer.seqId = NOR_CMD_LUT_SEQ_IDX_READID; 48 | xfer.seqNum = 1U; 49 | xfer.baseAddress = 0U; 50 | xfer.isParallelModeEnable = false; 51 | xfer.rxBuffer = vendorID; 52 | xfer.rxSize = 1U; 53 | 54 | uint32_t status = ROM_FLEXSPI_NorFlash_CommandXfer(instance, &xfer); 55 | if (*vendorID != kSerialFlash_Winbond_ManufacturerID) 56 | { 57 | status = kStatus_ROM_FLEXSPINOR_Flash_NotFound; 58 | return status; 59 | } 60 | 61 | return status; 62 | } 63 | 64 | FLASHBankInfo FLASHPlugin_Probe(unsigned base, unsigned size, unsigned width1, unsigned width2) 65 | { 66 | FLASHBankInfo result = { 67 | .BaseAddress = base, 68 | .BlockCount = norConfig.memConfig.sflashA1Size / norConfig.sectorSize, 69 | .BlockSize = norConfig.sectorSize, 70 | .WriteBlockSize = MINIMUM_PROGRAMMED_BLOCK_SIZE 71 | }; 72 | 73 | if (norConfig.pageSize != MINIMUM_PROGRAMMED_BLOCK_SIZE) 74 | error_trap(); 75 | 76 | return result; 77 | } 78 | 79 | WorkAreaInfo FLASHPlugin_FindWorkArea(void *endOfStack) 80 | { 81 | InterruptEnabler enabler; 82 | 83 | WorkAreaInfo info = { .Address = endOfStack, .Size = 4096 }; 84 | return info; 85 | } 86 | 87 | int FLASHPlugin_EraseSectors(unsigned firstSector, unsigned sectorCount) 88 | { 89 | status_t status = ROM_FLEXSPI_NorFlash_Erase(FlexSpiInstance, &norConfig, firstSector * norConfig.sectorSize, sectorCount * norConfig.sectorSize); 90 | if (status != kStatus_Success) 91 | error_trap(); 92 | 93 | return sectorCount; 94 | } 95 | 96 | int FLASHPlugin_Unload() 97 | { 98 | return 0; 99 | } 100 | 101 | int FLASHPlugin_DoProgramSync(unsigned startOffset, const void *pData, int bytesToWrite) 102 | { 103 | int pages = bytesToWrite / FLASH_PAGE_SIZE; 104 | for (int i = 0; i < pages; i++) 105 | { 106 | status_t status = ROM_FLEXSPI_NorFlash_ProgramPage(FlexSpiInstance, 107 | &norConfig, 108 | startOffset + i * FLASH_PAGE_SIZE, 109 | (const uint32_t *)((const char *)pData + i * FLASH_PAGE_SIZE)); 110 | 111 | if (status != kStatus_Success) 112 | return i * FLASH_PAGE_SIZE; 113 | } 114 | 115 | return pages * FLASH_PAGE_SIZE; 116 | } 117 | 118 | int main(void) 119 | { 120 | //BOARD_ConfigMPU(); 121 | BOARD_InitPins(); 122 | BOARD_BootClockRUN(); 123 | 124 | serial_nor_config_option_t option; 125 | memset(&option, 0U, sizeof(option)); 126 | option.option0.U = 0xc0000007U; 127 | 128 | memset(&norConfig, 0U, sizeof(flexspi_nor_config_t)); 129 | 130 | /* Disable I cache */ 131 | SCB_DisableICache(); 132 | 133 | /* Setup FLEXSPI NOR Configuration Block */ 134 | status_t status = ROM_FLEXSPI_NorFlash_GetConfig(FlexSpiInstance, &norConfig, &option); 135 | if (status != kStatus_Success) 136 | error_trap(); 137 | 138 | /* Initializes the FLEXSPI module for the other FLEXSPI APIs */ 139 | status = ROM_FLEXSPI_NorFlash_Init(FlexSpiInstance, &norConfig); 140 | if (status != kStatus_Success) 141 | error_trap(); 142 | 143 | /* Perform software reset after initializing flexspi module */ 144 | ROM_FLEXSPI_NorFlash_ClearCache(FlexSpiInstance); 145 | 146 | //status = FLEXSPI_NorFlash_GetVendorID(FlexSpiInstance, &vendorID); 147 | 148 | FLASHPlugin_InitDone(); 149 | 150 | #ifdef DEBUG 151 | TestFLASHProgramming(0x70000000, 0); 152 | asm("bkpt 255"); //Self-test passed 153 | #endif 154 | 155 | return 0; 156 | } 157 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/pin_mux.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | 13 | /* 14 | * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* 15 | !!GlobalInfo 16 | product: Pins v4.1 17 | processor: MIMXRT1064xxxxA 18 | package_id: MIMXRT1064DVL6A 19 | mcu_data: ksdk2_0 20 | processor_version: 0.0.0 21 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** 22 | */ 23 | 24 | #include "fsl_common.h" 25 | #include "fsl_iomuxc.h" 26 | #include "pin_mux.h" 27 | 28 | /* FUNCTION ************************************************************************************************************ 29 | * 30 | * Function Name : BOARD_InitBootPins 31 | * Description : Calls initialization functions. 32 | * 33 | * END ****************************************************************************************************************/ 34 | void BOARD_InitBootPins(void) { 35 | BOARD_InitPins(); 36 | } 37 | 38 | /* 39 | * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* 40 | BOARD_InitPins: 41 | - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} 42 | - pin_list: 43 | - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, 44 | pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} 45 | - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, 46 | pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} 47 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** 48 | */ 49 | 50 | /* FUNCTION ************************************************************************************************************ 51 | * 52 | * Function Name : BOARD_InitPins 53 | * Description : Configures pin routing and optionally pin electrical features. 54 | * 55 | * END ****************************************************************************************************************/ 56 | void BOARD_InitPins(void) { 57 | CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ 58 | 59 | IOMUXC_SetPinMux( 60 | IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ 61 | 0U); /* Software Input On Field: Input Path is determined by functionality */ 62 | IOMUXC_SetPinMux( 63 | IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ 64 | 0U); /* Software Input On Field: Input Path is determined by functionality */ 65 | IOMUXC_SetPinConfig( 66 | IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ 67 | 0x10B0u); /* Slew Rate Field: Slow Slew Rate 68 | Drive Strength Field: R0/6 69 | Speed Field: medium(100MHz) 70 | Open Drain Enable Field: Open Drain Disabled 71 | Pull / Keep Enable Field: Pull/Keeper Enabled 72 | Pull / Keep Select Field: Keeper 73 | Pull Up / Down Config. Field: 100K Ohm Pull Down 74 | Hyst. Enable Field: Hysteresis Disabled */ 75 | IOMUXC_SetPinConfig( 76 | IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ 77 | 0x10B0u); /* Slew Rate Field: Slow Slew Rate 78 | Drive Strength Field: R0/6 79 | Speed Field: medium(100MHz) 80 | Open Drain Enable Field: Open Drain Disabled 81 | Pull / Keep Enable Field: Pull/Keeper Enabled 82 | Pull / Keep Select Field: Keeper 83 | Pull Up / Down Config. Field: 100K Ohm Pull Down 84 | Hyst. Enable Field: Hysteresis Disabled */ 85 | } 86 | 87 | /*********************************************************************************************************************** 88 | * EOF 89 | **********************************************************************************************************************/ 90 | -------------------------------------------------------------------------------- /imxrt/iMXRT1064_Internal_ROMAPI/pin_mux.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | 13 | #ifndef _PIN_MUX_H_ 14 | #define _PIN_MUX_H_ 15 | 16 | /*********************************************************************************************************************** 17 | * Definitions 18 | **********************************************************************************************************************/ 19 | 20 | /*! @brief Direction type */ 21 | typedef enum _pin_mux_direction 22 | { 23 | kPIN_MUX_DirectionInput = 0U, /* Input direction */ 24 | kPIN_MUX_DirectionOutput = 1U, /* Output direction */ 25 | kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ 26 | } pin_mux_direction_t; 27 | 28 | /*! 29 | * @addtogroup pin_mux 30 | * @{ 31 | */ 32 | 33 | /*********************************************************************************************************************** 34 | * API 35 | **********************************************************************************************************************/ 36 | 37 | #if defined(__cplusplus) 38 | extern "C" { 39 | #endif 40 | 41 | /*! 42 | * @brief Calls initialization functions. 43 | * 44 | */ 45 | void BOARD_InitBootPins(void); 46 | 47 | 48 | /*! 49 | * @brief Configures pin routing and optionally pin electrical features. 50 | * 51 | */ 52 | void BOARD_InitPins(void); 53 | 54 | #if defined(__cplusplus) 55 | } 56 | #endif 57 | 58 | /*! 59 | * @} 60 | */ 61 | #endif /* _PIN_MUX_H_ */ 62 | 63 | /*********************************************************************************************************************** 64 | * EOF 65 | **********************************************************************************************************************/ 66 | -------------------------------------------------------------------------------- /imxrt/imxrt.cfg: -------------------------------------------------------------------------------- 1 | if { [info exists CHIPNAME] } { 2 | set _CHIPNAME $CHIPNAME 3 | } else { 4 | set _CHIPNAME imxrt 5 | } 6 | 7 | source [find mem_helper.tcl] 8 | 9 | # ---------------------------------------------- Auxiliary functions for accessing i.MXRT registers ---------------------------------------------- 10 | 11 | 12 | # SBMR2: Bit 25..24: 13 | # BOOT_MODE[1:0]: 00b - Boot From Fuses 14 | # 01b - Serial Downloader 15 | # 10b - Internal Boot 16 | # 11b - Reserved 17 | proc get_boot_mode {} { 18 | set SRC_SBMR2 [ mrw 0x400F801C ] 19 | set bootmode [expr ($SRC_SBMR2 & 0x03000000) >> 24 ] 20 | return $bootmode 21 | } 22 | 23 | # Boot Device: 0000b - Serial NOR boot via FlexSPI 24 | # 001xb - SD boot via uSDHC 25 | # 10xxb - eMMC/MMC boot via uSDHC 26 | # 01xxb - SLC NAND boot via SEMC 27 | # 0001b - Parallel NOR boot via SEMC 28 | # 11xxb - Serial NAND boot via FlexSPI 29 | proc get_boot_device {} { 30 | set SRC_SBMR1 [ mrw 0x400F8004 ] 31 | set bootdevice [expr ($SRC_SBMR1 & 0x000000F0) >> 4 ] 32 | return $bootdevice 33 | } 34 | 35 | proc get_reset_vector {} { 36 | global FLASH_MEMORY_BASE 37 | set MAX_FLASH_MEMORY_SIZE 0x10000000 38 | 39 | set vector_table_addr [ mrw [expr $FLASH_MEMORY_BASE + 0x1004 ] ] 40 | if { ($vector_table_addr < $FLASH_MEMORY_BASE) || ($vector_table_addr > ($FLASH_MEMORY_BASE + $MAX_FLASH_MEMORY_SIZE)) } { 41 | echo "Invalid vector table address: $vector_table_addr" 42 | return 0 43 | } 44 | 45 | set reset_vector [ mrw [expr $vector_table_addr + 4] ] 46 | return $reset_vector 47 | } 48 | 49 | # ------------------------------------------------------------------------------------------------------------------------------------------------ 50 | 51 | 52 | set RESET_INTO_BOOT_ROM 0 53 | 54 | #The regular "reset halt" command on i.MXRT will stop the chip at the internal entry point in the boot ROM. 55 | #At this point the internal bootloader has not initialized the peripherals set. 56 | #So normally, we want to instead let the bootloader run and stop when it invokes the entry point of the main program. 57 | #The 'reset_into_boot_rom' command controls this behavior. 58 | #Usage: reset_into_boot_rom 0/1 59 | proc reset_into_boot_rom { flag } { 60 | global RESET_INTO_BOOT_ROM 61 | set RESET_INTO_BOOT_ROM $flag 62 | if { $flag } { 63 | echo "'reset halt' will now try to stop in the boot ROM" 64 | } else { 65 | echo "'reset halt' will now try to stop at the entry point in FLASH" 66 | } 67 | 68 | return "" 69 | } 70 | 71 | set FLASH_MEMORY_BASE 0x70000000 72 | 73 | proc init_reset { mode } { 74 | global RESET_INTO_BOOT_ROM 75 | global PENDING_ENTRY_POINT_ADDRESS 76 | set PENDING_ENTRY_POINT_ADDRESS 0 77 | 78 | if { ($mode eq "run") || $RESET_INTO_BOOT_ROM } { 79 | return 80 | } 81 | 82 | set bootmode [ get_boot_mode ] 83 | set bootdev [ get_boot_device ] 84 | 85 | if { $bootmode != 2 } { 86 | echo "Cannot reset into entry when boot mode is $bootmode" 87 | return 88 | } 89 | 90 | if { $bootdev != 0 } { 91 | echo "Cannot reset into entry when boot device is $bootdev" 92 | return 93 | } 94 | 95 | set entry_point [ get_reset_vector ] 96 | 97 | if { $entry_point == 0 } { 98 | echo "Cannot locate the reset vector in FLASH memory. Make sure FLASH is not empty and FlexSPI is initialized." 99 | return 100 | } 101 | 102 | set PENDING_ENTRY_POINT_ADDRESS $entry_point 103 | } 104 | 105 | # 106 | # Only SWD and SPD supported 107 | # 108 | source [find target/swj-dp.tcl] 109 | 110 | if { [info exists CPUTAPID] } { 111 | set _CPU_SWD_TAPID $CPUTAPID 112 | } else { 113 | set _CPU_SWD_TAPID 0x0BD11477 114 | } 115 | 116 | swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID 117 | dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu 118 | 119 | set _TARGETNAME $_CHIPNAME.cpu 120 | target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap 121 | 122 | if { [info exists WORKAREASIZE] } { 123 | set _WORKAREASIZE $WORKAREASIZE 124 | } else { 125 | set _WORKAREASIZE 0x4000 126 | } 127 | 128 | $_TARGETNAME configure -work-area-phys 0x20200000 \ 129 | -work-area-size $_WORKAREASIZE \ 130 | -work-area-backup 0 131 | 132 | $_TARGETNAME configure -event reset-deassert-post { 133 | global PENDING_ENTRY_POINT_ADDRESS 134 | set halt_timeout 1000 135 | 136 | if { $PENDING_ENTRY_POINT_ADDRESS } { 137 | wait_halt $halt_timeout 138 | 139 | set entry_point_hex [ format "0x%X" $PENDING_ENTRY_POINT_ADDRESS ] 140 | echo "Found entry point at $entry_point_hex. Setting a temporary breakpoint and resetting..." 141 | bp $entry_point_hex 2 hw 142 | 143 | resume 144 | wait_halt $halt_timeout 145 | rbp $entry_point_hex 146 | } 147 | } 148 | 149 | #Using SRST on i.MXRT devices will not get the chip to halt. Doing a system reset on the ARM Cortex level instead works as expected 150 | cortex_m reset_config sysresetreq 151 | reset_config none 152 | 153 | #flash bank imxrt plugin $FLASH_MEMORY_BASE 0 0 0 0 flash/iMXRT1064_Internal_ROMAPI 154 | -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.15) 2 | 3 | project(LPC54628_FlashIAP LANGUAGES C CXX ASM) 4 | 5 | find_bsp(ID com.sysprogs.imported.ksdk2x.LPC54628J512 6 | VERSION 2.9.0 7 | MCU LPC54628J512ET180 8 | CONFIGURATION 9 | com.sysprogs.imported.ksdk2x.linker_script=devices/LPC54628/gcc/LPC54628J512_ram.ld 10 | com.sysprogs.bspoptions.arm.floatmode=-mfloat-abi=hard 11 | FRAMEWORKS 12 | com.sysprogs.ksdk2x_imported.platform.Include_common.LPC54628 13 | com.sysprogs.ksdk2x_imported.platform.Include_core_cm4.LPC54628 14 | com.sysprogs.ksdk2x_imported.platform.Include_dsp.LPC54628 15 | com.sysprogs.ksdk2x_imported.component.lists.LPC54628 16 | com.sysprogs.ksdk2x_imported.component.usart_adapter.LPC54628 17 | com.sysprogs.ksdk2x_imported.device.LPC54628_CMSIS.LPC54628 18 | com.sysprogs.ksdk2x_imported.device.LPC54628_startup.LPC54628 19 | com.sysprogs.ksdk2x_imported.device.LPC54628_system.LPC54628 20 | com.sysprogs.ksdk2x_imported.platform.drivers.clock.LPC54628 21 | com.sysprogs.ksdk2x_imported.platform.drivers.common.LPC54628 22 | com.sysprogs.ksdk2x_imported.platform.drivers.emc.LPC54628 23 | com.sysprogs.ksdk2x_imported.platform.drivers.flashiap.LPC54628 24 | com.sysprogs.ksdk2x_imported.platform.drivers.flexcomm.LPC54628 25 | com.sysprogs.ksdk2x_imported.platform.drivers.flexcomm_usart.LPC54628 26 | com.sysprogs.ksdk2x_imported.platform.drivers.inputmux.LPC54628 27 | com.sysprogs.ksdk2x_imported.platform.drivers.inputmux_connections.LPC54628 28 | com.sysprogs.ksdk2x_imported.platform.drivers.lpc_gpio.LPC54628 29 | com.sysprogs.ksdk2x_imported.platform.drivers.lpc_iocon.LPC54628 30 | com.sysprogs.ksdk2x_imported.platform.drivers.power.LPC54628 31 | com.sysprogs.ksdk2x_imported.platform.drivers.reset.LPC54628 32 | com.sysprogs.ksdk2x_imported.platform.utilities.misc_utilities.LPC54628 33 | HWREGISTER_LIST_FILE devices/LPC54628/LPC54628.vgdbdevice 34 | C_STANDARD 99) 35 | 36 | bsp_include_directories(${BSP_ROOT}/boards/lpcxpresso54628/driver_examples/flashiap) 37 | 38 | bsp_compile_definitions(CPU_LPC54628 39 | __USE_CMSIS 40 | CPU_LPC54628J512ET180=1) 41 | 42 | add_bsp_based_executable(NAME LPC54628_FlashIAP 43 | SOURCES 44 | main.cpp 45 | clock_config.c 46 | clock_config.h 47 | ../../common/FLASHPluginCommon.cpp 48 | FLASHPluginConfig.h 49 | GENERATE_BIN 50 | GENERATE_MAP) 51 | 52 | 53 | target_include_directories(LPC54628_FlashIAP PRIVATE ../../common .) -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/FLASHPluginConfig.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include 3 | #include 4 | 5 | #define MINIMUM_PROGRAMMED_BLOCK_SIZE FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES 6 | #define FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 1 -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/LPC54628_FlashIAP.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.31112.23 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{803FD0C6-D64E-4E16-9DC3-1DAEC859A3D2}") = "LPC54628_FlashIAP", "LPC54628_FlashIAP.vgdbcmake", "{BE2AFB13-3F45-4E85-97AF-70594E3DE153}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|VisualGDB = Debug|VisualGDB 11 | MinSizeRel|VisualGDB = MinSizeRel|VisualGDB 12 | Release|VisualGDB = Release|VisualGDB 13 | RelWithDebInfo|VisualGDB = RelWithDebInfo|VisualGDB 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.Debug|VisualGDB.ActiveCfg = Debug|VisualGDB 17 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.Debug|VisualGDB.Build.0 = Debug|VisualGDB 18 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.MinSizeRel|VisualGDB.ActiveCfg = MinSizeRel|VisualGDB 19 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.MinSizeRel|VisualGDB.Build.0 = MinSizeRel|VisualGDB 20 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.Release|VisualGDB.ActiveCfg = Release|VisualGDB 21 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.Release|VisualGDB.Build.0 = Release|VisualGDB 22 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.RelWithDebInfo|VisualGDB.ActiveCfg = RelWithDebInfo|VisualGDB 23 | {BE2AFB13-3F45-4E85-97AF-70594E3DE153}.RelWithDebInfo|VisualGDB.Build.0 = RelWithDebInfo|VisualGDB 24 | EndGlobalSection 25 | GlobalSection(SolutionProperties) = preSolution 26 | HideSolutionNode = FALSE 27 | EndGlobalSection 28 | GlobalSection(ExtensibilityGlobals) = postSolution 29 | SolutionGuid = {563257D2-0428-4980-B8C0-9B8E4374751E} 30 | EndGlobalSection 31 | EndGlobal 32 | -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/LPC54628_FlashIAP.vgdbcmake: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | MinGWUnixSlash 7 | $(ToolchainDir) 8 | 9 | true 10 | $(ProjectDir) 11 | false 12 | false 13 | DeviceDefinition 14 | 15 | 16 | 17 | 18 | com.visualgdb.arm-eabi 19 | 20 | 9.3.1 21 | 9.2.0 22 | 2 23 | 24 | 25 | 26 | DEBUG 27 | build/$(PlatformName)/$(ConfigurationName) 28 | 29 | false 30 | 31 | BuildMachine 32 | BuiltinShortcut 33 | 34 | $(VISUALGDB_DIR)/ninja.exe 35 | $(BuildDir) 36 | 37 | 38 | 39 | false 40 | 41 | BuildMachine 42 | BuiltinShortcut 43 | 44 | $(SYSPROGS_CMAKE_PATH) 45 | 46 | 47 | true 48 | false 49 | false 50 | Ninja 51 | false 52 | RemoveBuildDirectory 53 | false 54 | 55 | 56 | true 57 | true 58 | true 59 | false 60 | true 61 | false 62 | true 63 | HideOuterProjectTargets 64 | true 65 | false 66 | true 67 | 68 | 69 | true 70 | be2afb13-3f45-4e85-97af-70594e3de153 71 | 72 | Upper 73 | None 74 | true 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | Default 89 | 90 | 91 | 92 | true 93 | 94 | 95 | 96 | 97 | Unknown 98 | 99 | true 100 | true 101 | true 102 | 103 | 104 | 105 | false 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | false 115 | false 116 | false 117 | false 118 | false 119 | false 120 | false 121 | false 122 | false 123 | 124 | false 125 | false 126 | false 127 | false 128 | false 129 | false 130 | true 131 | false 132 | None 133 | false 134 | false 135 | main 136 | true 137 | false 138 | false 139 | false 140 | 0 141 | true 142 | 143 | 144 | com.sysprogs.arm.openocd 145 | 146 | -f interface/cmsis-dap.cfg -c "adapter speed 3000" -f target/lpc546xx.cfg -c init -c "reset init" 147 | 148 | 149 | 150 | false 151 | 152 | 131072 153 | Enabled 154 | 155 | set remotetimeout 60 156 | target remote :$$SYS:GDB_PORT$$ 157 | mon halt 158 | mon reset init 159 | load 160 | 161 | false 162 | 0 163 | 0 164 | false 165 | 166 | 167 | 168 | true 169 | Auto 170 | 0 171 | false 172 | false 173 | true 174 | false 175 | false 176 | 177 | _estack 178 | 0 179 | false 180 | 181 | true 182 | 183 | -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/clock_config.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017,2019 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | */ 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | /* 13 | * How to set up clock using clock driver functions: 14 | * 15 | * 1. Setup clock sources. 16 | * 17 | * 2. Setup voltage for the fastest of the clock outputs 18 | * 19 | * 3. Set up wait states of the flash. 20 | * 21 | * 4. Set up all dividers. 22 | * 23 | * 5. Set up all selectors to provide selected clocks. 24 | */ 25 | 26 | /* clang-format off */ 27 | /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* 28 | !!GlobalInfo 29 | product: Clocks v7.0 30 | processor: LPC54628J512 31 | package_id: LPC54628J512ET180 32 | mcu_data: ksdk2_0 33 | processor_version: 0.8.3 34 | board: LPCXpresso54628 35 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ 36 | /* clang-format on */ 37 | 38 | #include "fsl_power.h" 39 | #include "fsl_clock.h" 40 | #include "clock_config.h" 41 | 42 | /* System clock frequency. */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /******************************************************************************* 46 | ******************* Configuration BOARD_BootClockFROHF48M ********************* 47 | ******************************************************************************/ 48 | /* clang-format off */ 49 | /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* 50 | !!Configuration 51 | name: BOARD_BootClockFROHF48M 52 | outputs: 53 | - {id: FRO12M_clock.outFreq, value: 12 MHz} 54 | - {id: FROHF_clock.outFreq, value: 48 MHz} 55 | - {id: MAIN_clock.outFreq, value: 48 MHz} 56 | - {id: System_clock.outFreq, value: 48 MHz} 57 | settings: 58 | - {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} 59 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ 60 | /* clang-format on */ 61 | 62 | /******************************************************************************* 63 | * Variables for BOARD_BootClockFROHF48M configuration 64 | ******************************************************************************/ 65 | /******************************************************************************* 66 | * Code for BOARD_BootClockFROHF48M configuration 67 | ******************************************************************************/ 68 | void BOARD_BootClockFROHF48M(void) 69 | { 70 | /*!< Set up the clock sources */ 71 | /*!< Set up FRO */ 72 | POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ 73 | CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without 74 | accidentally being below the voltage for current speed */ 75 | POWER_SetVoltageForFreq( 76 | 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ 77 | CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ 78 | 79 | /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) 80 | before calling this API since this API is implemented in ROM code */ 81 | CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ 82 | 83 | /*!< Set up dividers */ 84 | CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ 85 | 86 | /*!< Set up clock selectors - Attach clocks to the peripheries */ 87 | CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ 88 | /* Set SystemCoreClock variable. */ 89 | SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; 90 | } 91 | 92 | -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/clock_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017,2019 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | */ 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | 13 | #ifndef _CLOCK_CONFIG_H_ 14 | #define _CLOCK_CONFIG_H_ 15 | 16 | #include "fsl_common.h" 17 | 18 | /******************************************************************************* 19 | * Definitions 20 | ******************************************************************************/ 21 | #define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ 22 | #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ 23 | 24 | /******************************************************************************* 25 | ************************ BOARD_InitBootClocks function ************************ 26 | ******************************************************************************/ 27 | 28 | #if defined(__cplusplus) 29 | extern "C" { 30 | #endif /* __cplusplus*/ 31 | 32 | /*! 33 | * @brief This function executes default configuration of clocks. 34 | * 35 | */ 36 | void BOARD_InitBootClocks(void); 37 | 38 | #if defined(__cplusplus) 39 | } 40 | #endif /* __cplusplus*/ 41 | 42 | /******************************************************************************* 43 | ******************** Configuration BOARD_BootClockFRO12M ********************** 44 | ******************************************************************************/ 45 | /******************************************************************************* 46 | * Definitions for BOARD_BootClockFRO12M configuration 47 | ******************************************************************************/ 48 | #define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */ 49 | 50 | /******************************************************************************* 51 | * API for BOARD_BootClockFRO12M configuration 52 | ******************************************************************************/ 53 | #if defined(__cplusplus) 54 | extern "C" { 55 | #endif /* __cplusplus*/ 56 | 57 | /*! 58 | * @brief This function executes configuration of clocks. 59 | * 60 | */ 61 | void BOARD_BootClockFRO12M(void); 62 | 63 | #if defined(__cplusplus) 64 | } 65 | #endif /* __cplusplus*/ 66 | 67 | /******************************************************************************* 68 | ******************* Configuration BOARD_BootClockFROHF48M ********************* 69 | ******************************************************************************/ 70 | /******************************************************************************* 71 | * Definitions for BOARD_BootClockFROHF48M configuration 72 | ******************************************************************************/ 73 | #define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */ 74 | 75 | /******************************************************************************* 76 | * API for BOARD_BootClockFROHF48M configuration 77 | ******************************************************************************/ 78 | #if defined(__cplusplus) 79 | extern "C" { 80 | #endif /* __cplusplus*/ 81 | 82 | /*! 83 | * @brief This function executes configuration of clocks. 84 | * 85 | */ 86 | void BOARD_BootClockFROHF48M(void); 87 | 88 | #if defined(__cplusplus) 89 | } 90 | #endif /* __cplusplus*/ 91 | 92 | /******************************************************************************* 93 | ******************* Configuration BOARD_BootClockFROHF96M ********************* 94 | ******************************************************************************/ 95 | /******************************************************************************* 96 | * Definitions for BOARD_BootClockFROHF96M configuration 97 | ******************************************************************************/ 98 | #define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */ 99 | 100 | /******************************************************************************* 101 | * API for BOARD_BootClockFROHF96M configuration 102 | ******************************************************************************/ 103 | #if defined(__cplusplus) 104 | extern "C" { 105 | #endif /* __cplusplus*/ 106 | 107 | /*! 108 | * @brief This function executes configuration of clocks. 109 | * 110 | */ 111 | void BOARD_BootClockFROHF96M(void); 112 | 113 | #if defined(__cplusplus) 114 | } 115 | #endif /* __cplusplus*/ 116 | 117 | /******************************************************************************* 118 | ******************** Configuration BOARD_BootClockPLL180M ********************* 119 | ******************************************************************************/ 120 | /******************************************************************************* 121 | * Definitions for BOARD_BootClockPLL180M configuration 122 | ******************************************************************************/ 123 | #define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */ 124 | 125 | /******************************************************************************* 126 | * API for BOARD_BootClockPLL180M configuration 127 | ******************************************************************************/ 128 | #if defined(__cplusplus) 129 | extern "C" { 130 | #endif /* __cplusplus*/ 131 | 132 | /*! 133 | * @brief This function executes configuration of clocks. 134 | * 135 | */ 136 | void BOARD_BootClockPLL180M(void); 137 | 138 | #if defined(__cplusplus) 139 | } 140 | #endif /* __cplusplus*/ 141 | 142 | /******************************************************************************* 143 | ******************** Configuration BOARD_BootClockPLL220M ********************* 144 | ******************************************************************************/ 145 | /******************************************************************************* 146 | * Definitions for BOARD_BootClockPLL220M configuration 147 | ******************************************************************************/ 148 | #define BOARD_BOOTCLOCKPLL220M_CORE_CLOCK 220000000U /*!< Core clock frequency:220000000Hz */ 149 | 150 | /******************************************************************************* 151 | * API for BOARD_BootClockPLL220M configuration 152 | ******************************************************************************/ 153 | #if defined(__cplusplus) 154 | extern "C" { 155 | #endif /* __cplusplus*/ 156 | 157 | /*! 158 | * @brief This function executes configuration of clocks. 159 | * 160 | */ 161 | void BOARD_BootClockPLL220M(void); 162 | 163 | #if defined(__cplusplus) 164 | } 165 | #endif /* __cplusplus*/ 166 | 167 | #endif /* _CLOCK_CONFIG_H_ */ 168 | -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/main.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | */ 8 | 9 | #include "pin_mux.h" 10 | #include "board.h" 11 | #include "fsl_flashiap.h" 12 | #include "fsl_common.h" 13 | 14 | #include 15 | #include 16 | 17 | void error_trap(void) 18 | { 19 | asm("bkpt 255"); 20 | } 21 | 22 | FLASHBankInfo FLASHPlugin_Probe(unsigned base, unsigned size, unsigned width1, unsigned width2) 23 | { 24 | FLASHBankInfo result = { 25 | .BaseAddress = base, 26 | .BlockCount = FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES, 27 | .BlockSize = FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES, 28 | .WriteBlockSize = MINIMUM_PROGRAMMED_BLOCK_SIZE 29 | }; 30 | 31 | return result; 32 | } 33 | 34 | WorkAreaInfo FLASHPlugin_FindWorkArea(void *endOfStack) 35 | { 36 | InterruptEnabler enabler; 37 | 38 | WorkAreaInfo info = { .Address = endOfStack, .Size = 4096 }; 39 | return info; 40 | } 41 | 42 | int FLASHPlugin_EraseSectors(unsigned firstSector, unsigned sectorCount) 43 | { 44 | status_t status = FLASHIAP_PrepareSectorForWrite(firstSector, firstSector + sectorCount - 1); 45 | if (status != kStatus_Success) 46 | error_trap(); 47 | 48 | status = FLASHIAP_EraseSector(firstSector, firstSector + sectorCount - 1, SystemCoreClock); 49 | if (status != kStatus_Success) 50 | error_trap(); 51 | 52 | return sectorCount; 53 | } 54 | 55 | int FLASHPlugin_Unload() 56 | { 57 | return 0; 58 | } 59 | 60 | static char __attribute__((aligned(FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES))) s_PageBuffer[FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES]; 61 | 62 | int FLASHPlugin_DoProgramSync(unsigned startOffset, const void *pData, int bytesToWrite) 63 | { 64 | int sectors = bytesToWrite / FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES; 65 | int i; 66 | for (i = 0; i < sectors; i++) 67 | { 68 | memcpy(s_PageBuffer, ((char *)pData + i * FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES), FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES); 69 | 70 | unsigned offsetInFLASH = startOffset + i * FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES; 71 | if (offsetInFLASH == 0) 72 | { 73 | //The IAP interface will refuse to write first page of the ROM unless the contents look like a 'valid' image. 74 | //The criteria for a 'valid' image are described in section 5.3.5 of UM10912 (rev. 2.4). 75 | //Specifically, the sum of the first 8 vectors in an image must be 0. 76 | //We patch the image on-the-fly in order to make sure it is accepted by the IAP. 77 | uint32_t *pVectors = (uint32_t *)s_PageBuffer; 78 | uint32_t sum = 0; 79 | for (int j = 0; j < 7; j++) 80 | sum += pVectors[j]; 81 | 82 | pVectors[7] = 0 - sum; 83 | } 84 | 85 | status_t status = FLASHIAP_PrepareSectorForWrite(offsetInFLASH / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES, offsetInFLASH / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES); 86 | if (status != kStatus_Success) 87 | break; 88 | 89 | status = FLASHIAP_CopyRamToFlash(offsetInFLASH, 90 | (uint32_t *)s_PageBuffer, 91 | FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES, 92 | SystemCoreClock); 93 | 94 | if (status != kStatus_Success) 95 | break; 96 | } 97 | 98 | if (!i) 99 | return -1; 100 | 101 | return i * FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES; 102 | } 103 | 104 | 105 | int main(void) 106 | { 107 | BOARD_BootClockFROHF48M(); 108 | FLASHPlugin_InitDone(); 109 | 110 | #ifdef DEBUG 111 | TestFLASHProgramming(0, 0); 112 | #endif 113 | 114 | } 115 | -------------------------------------------------------------------------------- /nxp_lpc/LPC54628_FlashIAP/pin_mux.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | */ 8 | 9 | #ifndef _PIN_MUX_H_ 10 | #define _PIN_MUX_H_ 11 | 12 | /*********************************************************************************************************************** 13 | * Definitions 14 | **********************************************************************************************************************/ 15 | 16 | /*! @brief Direction type */ 17 | typedef enum _pin_mux_direction 18 | { 19 | kPIN_MUX_DirectionInput = 0U, /* Input direction */ 20 | kPIN_MUX_DirectionOutput = 1U, /* Output direction */ 21 | kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ 22 | } pin_mux_direction_t; 23 | 24 | /*! 25 | * @addtogroup pin_mux 26 | * @{ 27 | */ 28 | 29 | /*********************************************************************************************************************** 30 | * API 31 | **********************************************************************************************************************/ 32 | 33 | #if defined(__cplusplus) 34 | extern "C" { 35 | #endif 36 | 37 | 38 | /*! 39 | * @brief Configures pin routing and optionally pin electrical features. 40 | * 41 | */ 42 | void BOARD_InitPins(void); /* Function assigned for the Cortex-M4F */ 43 | 44 | #define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ 45 | #define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ 46 | #define IOCON_PIO_INPFILT_OFF 0x0200u /*!<@brief Input filter disabled */ 47 | #define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ 48 | #define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ 49 | #define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ 50 | #define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ 51 | 52 | /*! 53 | * @brief Configures pin routing and optionally pin electrical features. 54 | * 55 | */ 56 | void BOARD_InitPins_Core0(void); /* Function assigned for the Cortex-M4F */ 57 | 58 | #if defined(__cplusplus) 59 | } 60 | #endif 61 | 62 | /*! 63 | * @} 64 | */ 65 | #endif /* _PIN_MUX_H_ */ 66 | 67 | /*********************************************************************************************************************** 68 | * EOF 69 | **********************************************************************************************************************/ 70 | -------------------------------------------------------------------------------- /nxp_lpc/LPC55S16_FlashIAP/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.15) 2 | 3 | project(LPC55S16_FlashIAP LANGUAGES C CXX ASM) 4 | 5 | find_bsp(ID com.sysprogs.imported.ksdk2x.LPC55S16 6 | VERSION 2.9.1 7 | MCU LPC55S16JBD100 8 | CONFIGURATION 9 | com.sysprogs.imported.ksdk2x.linker_script=devices/LPC55S16/gcc/LPC55S16_ram.ld 10 | com.sysprogs.bspoptions.arm.floatmode=-mfloat-abi=hard 11 | FRAMEWORKS 12 | com.sysprogs.ksdk2x_imported.platform.Include_common.LPC55S16 13 | com.sysprogs.ksdk2x_imported.platform.Include_core_cm33.LPC55S16 14 | com.sysprogs.ksdk2x_imported.platform.Include_dsp.LPC55S16 15 | com.sysprogs.ksdk2x_imported.component.lists.LPC55S16 16 | com.sysprogs.ksdk2x_imported.component.usart_adapter.LPC55S16 17 | com.sysprogs.ksdk2x_imported.device.LPC55S16_CMSIS.LPC55S16 18 | com.sysprogs.ksdk2x_imported.device.LPC55S16_startup.LPC55S16 19 | com.sysprogs.ksdk2x_imported.device.LPC55S16_system.LPC55S16 20 | com.sysprogs.ksdk2x_imported.platform.drivers.clock.LPC55S16 21 | com.sysprogs.ksdk2x_imported.platform.drivers.common.LPC55S16 22 | com.sysprogs.ksdk2x_imported.platform.drivers.flexcomm.LPC55S16 23 | com.sysprogs.ksdk2x_imported.platform.drivers.flexcomm_usart.LPC55S16 24 | com.sysprogs.ksdk2x_imported.platform.drivers.iap1.LPC55S16 25 | com.sysprogs.ksdk2x_imported.platform.drivers.inputmux.LPC55S16 26 | com.sysprogs.ksdk2x_imported.platform.drivers.inputmux_connections.LPC55S16 27 | com.sysprogs.ksdk2x_imported.platform.drivers.lpc_gpio.LPC55S16 28 | com.sysprogs.ksdk2x_imported.platform.drivers.lpc_iocon.LPC55S16 29 | com.sysprogs.ksdk2x_imported.platform.drivers.power.LPC55S16 30 | com.sysprogs.ksdk2x_imported.platform.drivers.reset.LPC55S16 31 | com.sysprogs.ksdk2x_imported.platform.utilities.misc_utilities.LPC55S16 32 | HWREGISTER_LIST_FILE devices/LPC55S16/LPC55S16.vgdbdevice 33 | C_STANDARD 99) 34 | 35 | bsp_include_directories(${BSP_ROOT}/boards/lpcxpresso55s16/driver_examples/flashiap) 36 | 37 | bsp_compile_definitions(CPU_LPC55S16JBD100) 38 | 39 | add_bsp_based_executable(NAME LPC55S16_FlashIAP 40 | SOURCES main.cpp clock_config.c clock_config.h ../../common/FLASHPluginCommon.cpp 41 | GENERATE_BIN 42 | GENERATE_MAP) 43 | 44 | target_include_directories(LPC55S16_FlashIAP PRIVATE ../../common .) -------------------------------------------------------------------------------- /nxp_lpc/LPC55S16_FlashIAP/FLASHPluginConfig.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include 3 | 4 | struct FLASHParameters 5 | { 6 | uint32_t BlockBase, SectorSize, TotalSize, PageSize; 7 | }; 8 | 9 | extern struct FLASHParameters g_FLASHParameters; 10 | #define MINIMUM_PROGRAMMED_BLOCK_SIZE g_FLASHParameters.PageSize 11 | #define FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 1 -------------------------------------------------------------------------------- /nxp_lpc/LPC55S16_FlashIAP/LPC55S16_FlashIAP.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio Version 16 4 | VisualStudioVersion = 16.0.31112.23 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{803FD0C6-D64E-4E16-9DC3-1DAEC859A3D2}") = "LPC55S16_FlashIAP", "LPC55S16_FlashIAP.vgdbcmake", "{10B45F8B-0D42-45CC-9A98-B9F247C73EEC}" 7 | EndProject 8 | Global 9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 10 | Debug|VisualGDB = Debug|VisualGDB 11 | MinSizeRel|VisualGDB = MinSizeRel|VisualGDB 12 | Release|VisualGDB = Release|VisualGDB 13 | RelWithDebInfo|VisualGDB = RelWithDebInfo|VisualGDB 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.Debug|VisualGDB.ActiveCfg = Debug|VisualGDB 17 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.Debug|VisualGDB.Build.0 = Debug|VisualGDB 18 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.MinSizeRel|VisualGDB.ActiveCfg = MinSizeRel|VisualGDB 19 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.MinSizeRel|VisualGDB.Build.0 = MinSizeRel|VisualGDB 20 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.Release|VisualGDB.ActiveCfg = Release|VisualGDB 21 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.Release|VisualGDB.Build.0 = Release|VisualGDB 22 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.RelWithDebInfo|VisualGDB.ActiveCfg = RelWithDebInfo|VisualGDB 23 | {10B45F8B-0D42-45CC-9A98-B9F247C73EEC}.RelWithDebInfo|VisualGDB.Build.0 = RelWithDebInfo|VisualGDB 24 | EndGlobalSection 25 | GlobalSection(SolutionProperties) = preSolution 26 | HideSolutionNode = FALSE 27 | EndGlobalSection 28 | GlobalSection(ExtensibilityGlobals) = postSolution 29 | SolutionGuid = {DDCF39C4-6E90-42F5-8734-1C398497848D} 30 | EndGlobalSection 31 | EndGlobal 32 | -------------------------------------------------------------------------------- /nxp_lpc/LPC55S16_FlashIAP/LPC55S16_FlashIAP.vgdbcmake: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | MinGWUnixSlash 7 | $(ToolchainDir) 8 | 9 | true 10 | $(ProjectDir) 11 | false 12 | false 13 | DeviceDefinition 14 | 15 | 16 | 17 | 18 | com.visualgdb.arm-eabi 19 | 20 | 9.3.1 21 | 9.2.0 22 | 2 23 | 24 | 25 | 26 | DEBUG 27 | build/$(PlatformName)/$(ConfigurationName) 28 | 29 | false 30 | $(VISUALGDB_DIR)/ninja.exe 31 | $(BuildDir) 32 | 33 | 34 | 35 | false 36 | $(SYSPROGS_CMAKE_PATH) 37 | 38 | 39 | true 40 | false 41 | false 42 | Ninja 43 | false 44 | RemoveBuildDirectory 45 | false 46 | 47 | 48 | true 49 | true 50 | true 51 | false 52 | true 53 | false 54 | true 55 | HideOuterProjectTargets 56 | true 57 | false 58 | true 59 | 60 | 61 | true 62 | 10b45f8b-0d42-45cc-9a98-b9f247c73eec 63 | 64 | Upper 65 | None 66 | true 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | Default 81 | 82 | 83 | 84 | true 85 | 86 | 87 | 88 | 89 | Unknown 90 | 91 | true 92 | true 93 | true 94 | 95 | 96 | 97 | false 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | false 107 | false 108 | false 109 | false 110 | false 111 | false 112 | false 113 | false 114 | false 115 | 116 | false 117 | false 118 | false 119 | false 120 | false 121 | false 122 | true 123 | false 124 | None 125 | false 126 | false 127 | main 128 | true 129 | false 130 | false 131 | false 132 | 0 133 | true 134 | 135 | 136 | com.sysprogs.arm.openocd 137 | 138 | -f interface/cmsis-dap.cfg -f target/lpc55sxx.cfg -c "adapter speed 3000" -c init 139 | 140 | 141 | 142 | false 143 | 144 | 131072 145 | Enabled 146 | 147 | set remotetimeout 60 148 | target remote :$$SYS:GDB_PORT$$ 149 | mon halt 150 | mon cortex_m lpc55sx_reset 151 | load 152 | 153 | false 154 | 0 155 | 0 156 | false 157 | 158 | 159 | 160 | true 161 | Auto 162 | 0 163 | false 164 | false 165 | true 166 | false 167 | false 168 | 169 | _estack 170 | 0 171 | false 172 | 173 | true 174 | 175 | -------------------------------------------------------------------------------- /nxp_lpc/LPC55S16_FlashIAP/clock_config.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2017-2018 ,2021 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | /* 13 | * How to set up clock using clock driver functions: 14 | * 15 | * 1. Setup clock sources. 16 | * 17 | * 2. Set up wait states of the flash. 18 | * 19 | * 3. Set up all dividers. 20 | * 21 | * 4. Set up all selectors to provide selected clocks. 22 | */ 23 | 24 | /* clang-format off */ 25 | /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* 26 | !!GlobalInfo 27 | product: Clocks v7.0 28 | processor: LPC55S16 29 | package_id: LPC55S16JBD100 30 | mcu_data: ksdk2_0 31 | processor_version: 9.0.0 32 | board: LPCXpresso55S16 33 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ 34 | /* clang-format on */ 35 | 36 | #include "fsl_power.h" 37 | #include "fsl_clock.h" 38 | #include "clock_config.h" 39 | 40 | /******************************************************************************* 41 | * Definitions 42 | ******************************************************************************/ 43 | 44 | /******************************************************************************* 45 | * Variables 46 | ******************************************************************************/ 47 | /* System clock frequency. */ 48 | extern uint32_t SystemCoreClock; 49 | 50 | /******************************************************************************* 51 | ******************* Configuration BOARD_BootClockFROHF96M ********************* 52 | ******************************************************************************/ 53 | /* clang-format off */ 54 | /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* 55 | !!Configuration 56 | name: BOARD_BootClockFROHF96M 57 | outputs: 58 | - {id: FRO_12MHz_clock.outFreq, value: 12 MHz} 59 | - {id: System_clock.outFreq, value: 96 MHz} 60 | settings: 61 | - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} 62 | - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} 63 | sources: 64 | - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} 65 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ 66 | /* clang-format on */ 67 | 68 | /******************************************************************************* 69 | * Variables for BOARD_BootClockFROHF96M configuration 70 | ******************************************************************************/ 71 | /******************************************************************************* 72 | * Code for BOARD_BootClockFROHF96M configuration 73 | ******************************************************************************/ 74 | void BOARD_BootClockFROHF96M(void) 75 | { 76 | #ifndef SDK_SECONDARY_CORE 77 | /*!< Set up the clock sources */ 78 | /*!< Configure FRO192M */ 79 | POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ 80 | CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ 81 | CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ 82 | 83 | CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ 84 | 85 | POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ 86 | CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ 87 | 88 | /*!< Set up dividers */ 89 | CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ 90 | 91 | /*!< Set up clock selectors - Attach clocks to the peripheries */ 92 | CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ 93 | 94 | /*< Set SystemCoreClock variable. */ 95 | SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; 96 | #endif 97 | } 98 | -------------------------------------------------------------------------------- /nxp_lpc/LPC55S16_FlashIAP/clock_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2017-2018 ,2021 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | /*********************************************************************************************************************** 9 | * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file 10 | * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. 11 | **********************************************************************************************************************/ 12 | 13 | #ifndef _CLOCK_CONFIG_H_ 14 | #define _CLOCK_CONFIG_H_ 15 | 16 | #include "fsl_common.h" 17 | 18 | /******************************************************************************* 19 | * Definitions 20 | ******************************************************************************/ 21 | #define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ 22 | #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ 23 | 24 | /******************************************************************************* 25 | ************************ BOARD_InitBootClocks function ************************ 26 | ******************************************************************************/ 27 | 28 | #if defined(__cplusplus) 29 | extern "C" { 30 | #endif /* __cplusplus*/ 31 | 32 | /*! 33 | * @brief This function executes default configuration of clocks. 34 | * 35 | */ 36 | void BOARD_InitBootClocks(void); 37 | 38 | #if defined(__cplusplus) 39 | } 40 | #endif /* __cplusplus*/ 41 | 42 | /******************************************************************************* 43 | ******************** Configuration BOARD_BootClockFRO12M ********************** 44 | ******************************************************************************/ 45 | /******************************************************************************* 46 | * Definitions for BOARD_BootClockFRO12M configuration 47 | ******************************************************************************/ 48 | #define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ 49 | 50 | 51 | /******************************************************************************* 52 | * API for BOARD_BootClockFRO12M configuration 53 | ******************************************************************************/ 54 | #if defined(__cplusplus) 55 | extern "C" { 56 | #endif /* __cplusplus*/ 57 | 58 | /*! 59 | * @brief This function executes configuration of clocks. 60 | * 61 | */ 62 | void BOARD_BootClockFRO12M(void); 63 | 64 | #if defined(__cplusplus) 65 | } 66 | #endif /* __cplusplus*/ 67 | 68 | /******************************************************************************* 69 | ******************* Configuration BOARD_BootClockFROHF96M ********************* 70 | ******************************************************************************/ 71 | /******************************************************************************* 72 | * Definitions for BOARD_BootClockFROHF96M configuration 73 | ******************************************************************************/ 74 | #define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ 75 | 76 | 77 | /******************************************************************************* 78 | * API for BOARD_BootClockFROHF96M configuration 79 | ******************************************************************************/ 80 | #if defined(__cplusplus) 81 | extern "C" { 82 | #endif /* __cplusplus*/ 83 | 84 | /*! 85 | * @brief This function executes configuration of clocks. 86 | * 87 | */ 88 | void BOARD_BootClockFROHF96M(void); 89 | 90 | #if defined(__cplusplus) 91 | } 92 | #endif /* __cplusplus*/ 93 | 94 | /******************************************************************************* 95 | ******************** Configuration BOARD_BootClockPLL100M ********************* 96 | ******************************************************************************/ 97 | /******************************************************************************* 98 | * Definitions for BOARD_BootClockPLL100M configuration 99 | ******************************************************************************/ 100 | #define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ 101 | 102 | 103 | /******************************************************************************* 104 | * API for BOARD_BootClockPLL100M configuration 105 | ******************************************************************************/ 106 | #if defined(__cplusplus) 107 | extern "C" { 108 | #endif /* __cplusplus*/ 109 | 110 | /*! 111 | * @brief This function executes configuration of clocks. 112 | * 113 | */ 114 | void BOARD_BootClockPLL100M(void); 115 | 116 | #if defined(__cplusplus) 117 | } 118 | #endif /* __cplusplus*/ 119 | 120 | /******************************************************************************* 121 | ******************** Configuration BOARD_BootClockPLL150M ********************* 122 | ******************************************************************************/ 123 | /******************************************************************************* 124 | * Definitions for BOARD_BootClockPLL150M configuration 125 | ******************************************************************************/ 126 | #define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ 127 | 128 | 129 | /******************************************************************************* 130 | * API for BOARD_BootClockPLL150M configuration 131 | ******************************************************************************/ 132 | #if defined(__cplusplus) 133 | extern "C" { 134 | #endif /* __cplusplus*/ 135 | 136 | /*! 137 | * @brief This function executes configuration of clocks. 138 | * 139 | */ 140 | void BOARD_BootClockPLL150M(void); 141 | 142 | #if defined(__cplusplus) 143 | } 144 | #endif /* __cplusplus*/ 145 | 146 | /******************************************************************************* 147 | ******************* Configuration BOARD_BootClockPLL1_150M ******************** 148 | ******************************************************************************/ 149 | /******************************************************************************* 150 | * Definitions for BOARD_BootClockPLL1_150M configuration 151 | ******************************************************************************/ 152 | #define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ 153 | 154 | 155 | /******************************************************************************* 156 | * API for BOARD_BootClockPLL1_150M configuration 157 | ******************************************************************************/ 158 | #if defined(__cplusplus) 159 | extern "C" { 160 | #endif /* __cplusplus*/ 161 | 162 | /*! 163 | * @brief This function executes configuration of clocks. 164 | * 165 | */ 166 | void BOARD_BootClockPLL1_150M(void); 167 | 168 | #if defined(__cplusplus) 169 | } 170 | #endif /* __cplusplus*/ 171 | 172 | #endif /* _CLOCK_CONFIG_H_ */ 173 | 174 | -------------------------------------------------------------------------------- /nxp_lpc/LPC55S16_FlashIAP/main.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | */ 7 | 8 | #include "pin_mux.h" 9 | #include "board.h" 10 | #include "fsl_iap.h" 11 | #include "fsl_iap_ffr.h" 12 | #include "fsl_common.h" 13 | #include "fsl_power.h" 14 | 15 | #include 16 | #include 17 | 18 | void error_trap(void) 19 | { 20 | asm("bkpt 255"); 21 | } 22 | 23 | static flash_config_t s_FLASHInstance; 24 | struct FLASHParameters g_FLASHParameters; 25 | 26 | FLASHBankInfo FLASHPlugin_Probe(unsigned base, unsigned size, unsigned width1, unsigned width2) 27 | { 28 | FLASHBankInfo result = { 29 | .BaseAddress = base, 30 | .BlockCount = g_FLASHParameters.TotalSize / g_FLASHParameters.SectorSize, 31 | .BlockSize = g_FLASHParameters.SectorSize, 32 | .WriteBlockSize = MINIMUM_PROGRAMMED_BLOCK_SIZE 33 | }; 34 | 35 | return result; 36 | } 37 | 38 | WorkAreaInfo FLASHPlugin_FindWorkArea(void *endOfStack) 39 | { 40 | InterruptEnabler enabler; 41 | 42 | WorkAreaInfo info = { .Address = endOfStack, .Size = 4096 }; 43 | return info; 44 | } 45 | 46 | int FLASHPlugin_EraseSectors(unsigned firstSector, unsigned sectorCount) 47 | { 48 | status_t status = FLASH_Erase(&s_FLASHInstance, 49 | firstSector * g_FLASHParameters.SectorSize, 50 | sectorCount * g_FLASHParameters.SectorSize, 51 | kFLASH_ApiEraseKey); 52 | 53 | if (status != kStatus_Success) 54 | error_trap(); 55 | 56 | return sectorCount; 57 | } 58 | 59 | int FLASHPlugin_Unload() 60 | { 61 | return 0; 62 | } 63 | 64 | int FLASHPlugin_DoProgramSync(unsigned startOffset, const void *pData, int bytesToWrite) 65 | { 66 | status_t status = FLASH_Program(&s_FLASHInstance, startOffset, (uint8_t *)pData, bytesToWrite); 67 | if (status != kStatus_Success) 68 | error_trap(); 69 | 70 | return bytesToWrite; 71 | } 72 | 73 | int main() 74 | { 75 | POWER_SetBodVbatLevel(kPOWER_BodVbatLevel1650mv, kPOWER_BodHystLevel50mv, false); 76 | BOARD_BootClockFROHF96M(); 77 | 78 | if (FLASH_Init(&s_FLASHInstance) != kStatus_Success) 79 | { 80 | error_trap(); 81 | } 82 | 83 | FLASH_GetProperty(&s_FLASHInstance, kFLASH_PropertyPflashBlockBaseAddr, &g_FLASHParameters.BlockBase); 84 | FLASH_GetProperty(&s_FLASHInstance, kFLASH_PropertyPflashSectorSize, &g_FLASHParameters.SectorSize); 85 | FLASH_GetProperty(&s_FLASHInstance, kFLASH_PropertyPflashTotalSize, &g_FLASHParameters.TotalSize); 86 | FLASH_GetProperty(&s_FLASHInstance, kFLASH_PropertyPflashPageSize, &g_FLASHParameters.PageSize); 87 | 88 | FLASHPlugin_InitDone(); 89 | 90 | #ifdef DEBUG 91 | TestFLASHProgramming(0x00000000, 0); 92 | #endif 93 | 94 | asm("bkpt 255"); 95 | return 0; 96 | } 97 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/FLASHPluginConfig.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "main.h" 3 | #include "stm32f769i_eval_qspi.h" 4 | 5 | #define MINIMUM_PROGRAMMED_BLOCK_SIZE N25Q512A_PAGE_SIZE 6 | #define FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 1 -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/Inc/stm32f7xx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file QSPI/QSPI_MemoryMapped/Inc/stm32f7xx_it.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 30-December-2016 7 | * @brief This file contains the headers of the interrupt handlers. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT(c) 2016 STMicroelectronics

12 | * 13 | * Redistribution and use in source and binary forms, with or without modification, 14 | * are permitted provided that the following conditions are met: 15 | * 1. Redistributions of source code must retain the above copyright notice, 16 | * this list of conditions and the following disclaimer. 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, 18 | * this list of conditions and the following disclaimer in the documentation 19 | * and/or other materials provided with the distribution. 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 | * may be used to endorse or promote products derived from this software 22 | * without specific prior written permission. 23 | * 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 | * 35 | ****************************************************************************** 36 | */ 37 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ 39 | #ifndef __STM32F7xx_IT_H 40 | #define __STM32F7xx_IT_H 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /* Includes ------------------------------------------------------------------*/ 47 | /* Exported types ------------------------------------------------------------*/ 48 | /* Exported constants --------------------------------------------------------*/ 49 | /* Exported macro ------------------------------------------------------------*/ 50 | /* Exported functions ------------------------------------------------------- */ 51 | 52 | void NMI_Handler(void); 53 | void HardFault_Handler(void); 54 | void MemManage_Handler(void); 55 | void BusFault_Handler(void); 56 | void UsageFault_Handler(void); 57 | void SVC_Handler(void); 58 | void DebugMon_Handler(void); 59 | void PendSV_Handler(void); 60 | void SysTick_Handler(void); 61 | void QUADSPI_IRQHandler(void); 62 | void QSPI_DMA_IRQ_HANDLER(void); 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __STM32F7xx_IT_H */ 69 | 70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 71 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/main.cpp: -------------------------------------------------------------------------------- 1 | #include "FLASHPluginConfig.h" 2 | #include 3 | #include 4 | #include "FLASHPluginInterface.h" 5 | 6 | /* 7 | This file implements the interface required by the Sysprogs OpenOCD fork to support programming QSPI FLASH. 8 | 9 | To use this plugin, add the following to the additional command-line arguments of your OpenOCD: 10 | -c "flash bank qspi plugin 0 0 0 0 path/to/stm32f7disco_qspi.elf" 11 | 12 | The base address is typically 0x90000000. 13 | Then simply start debugging your QSPI-enabled program and OpenOCD will detect and program the QSPI memory automatically. 14 | */ 15 | 16 | #ifdef __cplusplus 17 | extern "C" 18 | #endif 19 | void SysTick_Handler(void) 20 | { 21 | HAL_IncTick(); 22 | HAL_SYSTICK_IRQHandler(); 23 | } 24 | 25 | 26 | FLASHBankInfo FLASHPlugin_Probe(unsigned base, unsigned size, unsigned width1, unsigned width2) 27 | { 28 | InterruptEnabler enabler; 29 | 30 | FLASHBankInfo result = { 31 | .BaseAddress = base, 32 | .BlockCount = N25Q512A_FLASH_SIZE / N25Q512A_SUBSECTOR_SIZE, 33 | .BlockSize = N25Q512A_SUBSECTOR_SIZE, 34 | .WriteBlockSize = MINIMUM_PROGRAMMED_BLOCK_SIZE 35 | }; 36 | return result; 37 | } 38 | 39 | WorkAreaInfo FLASHPlugin_FindWorkArea(void *endOfStack) 40 | { 41 | InterruptEnabler enabler; 42 | 43 | WorkAreaInfo info = { .Address = endOfStack, .Size = 4096 }; 44 | return info; 45 | } 46 | 47 | int FLASHPlugin_EraseSectors(unsigned firstSector, unsigned sectorCount) 48 | { 49 | InterruptEnabler enabler; 50 | int initialTick = HAL_GetTick(); 51 | int timeout = 5000; 52 | 53 | for (unsigned i = 0; i < sectorCount; i++) 54 | { 55 | if ((HAL_GetTick() - initialTick) > timeout) 56 | return i; //OpenOCD will continue the erase operation 57 | 58 | uint8_t error = BSP_QSPI_Erase_Block((firstSector + i) * N25Q512A_SUBSECTOR_SIZE); 59 | if (error != QSPI_OK) 60 | return -1; 61 | } 62 | return sectorCount; 63 | } 64 | 65 | int FLASHPlugin_Unload() 66 | { 67 | BSP_QSPI_DeInit(); 68 | HAL_DeInit(); 69 | SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; 70 | 71 | for (int i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) 72 | NVIC->ICER[0] = -1; 73 | 74 | return 0; 75 | } 76 | 77 | int FLASHPlugin_DoProgramSync(unsigned startOffset, const void *pData, int bytesToWrite) 78 | { 79 | uint8_t result = BSP_QSPI_Write((uint8_t *)pData, startOffset, bytesToWrite); 80 | if (result != QSPI_OK) 81 | return 0; 82 | return bytesToWrite; 83 | } 84 | 85 | 86 | int main(void) 87 | { 88 | extern void *g_pfnVectors; 89 | 90 | SCB->VTOR = (uint32_t)&g_pfnVectors; 91 | HAL_Init(); 92 | BSP_QSPI_Init(); 93 | FLASHPlugin_InitDone(); 94 | 95 | #ifdef DEBUG 96 | TestFLASHProgramming(0x90000000, 0); 97 | #endif 98 | 99 | for (;;) 100 | ; 101 | } 102 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/stm32/stm32f769_disco_qspi/readme.txt -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/stm32.props: -------------------------------------------------------------------------------- 1 | 2 | 8 | 9 | 10 | 11 | 12 | ARM_MATH_CM7;STM32F769NI;%(ClCompile.PreprocessorDefinitions) 13 | $(ProjectDir);%(ClCompile.AdditionalIncludeDirectories) 14 | 15 | 16 | 17 | 18 | $(BSP_ROOT)/STM32F7xxxx/LinkerScripts/STM32F769NI_flash.lds 19 | compactcpp;%(Link.AdditionalLibraryNames) 20 | 21 | 22 | 23 | $(BSP_ROOT)/STM32F7xxxx/LinkerScripts/STM32F769NI_flash.lds 24 | 25 | 26 | 27 | 28 | cortex-m7 29 | THUMB 30 | soft 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/stm32.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | com.visualgdb.arm-eabi 4 | 5 | 5.3.0 6 | 7.10.1 7 | 2 8 | 9 | com.sysprogs.arm.stm32 10 | 4.3 11 | STM32F769NI 12 | STM32F7xxxx/DeviceDefinitions/stm32f769xx.xml 13 | 14 | 15 | 16 | com.sysprogs.bspoptions.primary_memory 17 | flash 18 | 19 | 20 | com.sysprogs.bspoptions.arm.floatmode 21 | -mfloat-abi=soft 22 | 23 | 24 | com.sysprogs.toolchainoptions.arm.libctype 25 | 26 | 27 | 28 | com.sysprogs.toolchainoptions.arm.compactcpp 29 | compactcpp 30 | 31 | 32 | com.sysprogs.toolchainoptions.arm.libnosys 33 | 34 | 35 | 36 | 37 | Device-specific files 38 | stm32.mak 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/stm32f769_disco_qspi-Debug.vgdbsettings: -------------------------------------------------------------------------------- 1 | 2 | 3 | Debug 4 | 5 | 6 | 7 | MinGWUnixSlash 8 | 9 | $(ProjectDir) 10 | stm32.xml 11 | 12 | 13 | 14 | 15 | 0 16 | 17 | 18 | stm32f769_disco_qspi.vcxproj 19 | 0 20 | true 21 | 22 | 23 | 24 | 25 | 26 | false 27 | false 28 | false 29 | false 30 | false 31 | false 32 | false 33 | false 34 | false 35 | 36 | false 37 | false 38 | false 39 | false 40 | false 41 | false 42 | true 43 | false 44 | None 45 | false 46 | false 47 | main 48 | true 49 | false 50 | false 51 | false 52 | 53 | 54 | com.sysprogs.arm.openocd 55 | stlink-v2-1 56 | 0670FF535651727067074157 57 | 58 | -f interface/stlink-v2-1.cfg -f target/stm32f7x.cfg -c init -c "reset init" 59 | 60 | 61 | 62 | false 63 | 64 | Enabled 65 | 66 | set remotetimeout 60 67 | target remote :$$SYS:GDB_PORT$$ 68 | mon halt 69 | mon reset init 70 | load 71 | 72 | 73 | 74 | true 75 | Auto 76 | false 77 | false 78 | true 79 | false 80 | true 81 | 82 | _estack 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | Default 96 | 97 | 98 | 99 | true 100 | 101 | 102 | 103 | Unknown 104 | 105 | true 106 | false 107 | 108 | 109 | false 110 | 111 | 112 | VisualGDB\VisualGDBCache 113 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/stm32f769_disco_qspi-Release.vgdbsettings: -------------------------------------------------------------------------------- 1 | 2 | 3 | Release 4 | 5 | 6 | 7 | MinGWUnixSlash 8 | 9 | $(ProjectDir) 10 | stm32.xml 11 | 12 | 13 | 14 | 15 | 0 16 | 17 | 18 | stm32f769_disco_qspi.vcxproj 19 | 0 20 | true 21 | 22 | 23 | 24 | 25 | 26 | false 27 | false 28 | false 29 | false 30 | false 31 | false 32 | false 33 | false 34 | false 35 | 36 | false 37 | false 38 | false 39 | false 40 | false 41 | false 42 | true 43 | false 44 | None 45 | false 46 | false 47 | main 48 | true 49 | false 50 | false 51 | false 52 | 53 | 54 | com.sysprogs.arm.openocd 55 | stlink-v2-1 56 | 0670FF535651727067074157 57 | 58 | -f interface/stlink-v2-1.cfg -f target/stm32f7x.cfg -c init -c "reset init" 59 | 60 | 61 | 62 | false 63 | 64 | Enabled 65 | 66 | set remotetimeout 60 67 | target remote :$$SYS:GDB_PORT$$ 68 | mon halt 69 | mon reset init 70 | load 71 | 72 | 73 | 74 | true 75 | Auto 76 | false 77 | false 78 | true 79 | false 80 | true 81 | 82 | _estack 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | Default 96 | 97 | 98 | 99 | true 100 | 101 | 102 | 103 | Unknown 104 | 105 | true 106 | false 107 | 108 | 109 | false 110 | 111 | 112 | VisualGDB\VisualGDBCache 113 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/stm32f769_disco_qspi.sln: -------------------------------------------------------------------------------- 1 | Microsoft Visual Studio Solution File, Format Version 12.00 2 | # Visual Studio 15 3 | VisualStudioVersion = 15.0.26430.15 4 | MinimumVisualStudioVersion = 10.0.40219.1 5 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "stm32f769_disco_qspi", "stm32f769_disco_qspi.vcxproj", "{19E46D5D-F3CF-4651-BD3F-27F9A1C2D7F4}" 6 | EndProject 7 | Global 8 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 9 | Debug|VisualGDB = Debug|VisualGDB 10 | Release|VisualGDB = Release|VisualGDB 11 | EndGlobalSection 12 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 13 | {19E46D5D-F3CF-4651-BD3F-27F9A1C2D7F4}.Debug|VisualGDB.ActiveCfg = Debug|VisualGDB 14 | {19E46D5D-F3CF-4651-BD3F-27F9A1C2D7F4}.Debug|VisualGDB.Build.0 = Debug|VisualGDB 15 | {19E46D5D-F3CF-4651-BD3F-27F9A1C2D7F4}.Release|VisualGDB.ActiveCfg = Release|VisualGDB 16 | {19E46D5D-F3CF-4651-BD3F-27F9A1C2D7F4}.Release|VisualGDB.Build.0 = Release|VisualGDB 17 | EndGlobalSection 18 | GlobalSection(SolutionProperties) = preSolution 19 | HideSolutionNode = FALSE 20 | EndGlobalSection 21 | EndGlobal 22 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/stm32f769_disco_qspi.vcxproj: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | Debug 6 | VisualGDB 7 | 8 | 9 | Release 10 | VisualGDB 11 | 12 | 13 | 14 | 15.0 15 | {19E46D5D-F3CF-4651-BD3F-27F9A1C2D7F4} 16 | com.sysprogs.arm.stm32 17 | 4.3 18 | 19 | 20 | 21 | 22 | $(ProjectDir)stm32.props 23 | 24 | 25 | $(ProjectDir)stm32.props 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | Debug 35 | com.visualgdb.arm-eabi 36 | 5.3.0/7.10.1/r2 37 | 38 | 39 | com.visualgdb.arm-eabi 40 | 5.3.0/7.10.1/r2 41 | 42 | 43 | 44 | Inc;..\..\common;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/Device/ST/STM32F7xx/Include;$(BSP_ROOT)/STM32F7xxxx/STM32F7xx_HAL_Driver/Inc;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Drivers/BSP/STM32F769I_EVAL;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Drivers/BSP/Components/Common;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Utilities/Log;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Utilities/Fonts;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Utilities/CPU;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/Include;%(ClCompile.AdditionalIncludeDirectories) 45 | %(ClCompile.PreprocessorDefinitions);DEBUG=1;USE_HAL_DRIVER;USE_STM32F769I_EVAL;STM32F769xx 46 | 47 | 48 | 49 | 50 | Inc;..\..\common;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/Device/ST/STM32F7xx/Include;$(BSP_ROOT)/STM32F7xxxx/STM32F7xx_HAL_Driver/Inc;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Drivers/BSP/STM32F769I_EVAL;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Drivers/BSP/Components/Common;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Utilities/Log;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Utilities/Fonts;$(BSP_ROOT)/VendorSamples/STM32Cube_FW_F7_V1.7.0/Utilities/CPU;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/Include;%(ClCompile.AdditionalIncludeDirectories) 51 | %(ClCompile.PreprocessorDefinitions);NDEBUG=1;RELEASE=1;USE_HAL_DRIVER;USE_STM32F769I_EVAL;STM32F769xx 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 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43 | Source files 44 | 45 | 46 | Source files\Src 47 | 48 | 49 | Source files\Shared sources 50 | 51 | 52 | Source files\Shared sources 53 | 54 | 55 | Source files\Shared sources 56 | 57 | 58 | Source files\Shared sources 59 | 60 | 61 | Source files\Shared sources 62 | 63 | 64 | Source files\Shared sources 65 | 66 | 67 | Source files\Shared sources 68 | 69 | 70 | Source files\Shared sources 71 | 72 | 73 | Source files\Shared sources 74 | 75 | 76 | Source files\Shared sources 77 | 78 | 79 | Source files\Shared sources 80 | 81 | 82 | Source files\Shared sources 83 | 84 | 85 | Source files\Shared sources 86 | 87 | 88 | Source files\Shared sources 89 | 90 | 91 | Source files\Shared sources 92 | 93 | 94 | Source files\Shared sources 95 | 96 | 97 | Source files\Device-specific files 98 | 99 | 100 | Source files\Device-specific files 101 | 102 | 103 | Header files\Inc 104 | 105 | 106 | Header files\Inc 107 | 108 | 109 | Header files\Inc 110 | 111 | 112 | VisualGDB settings 113 | 114 | 115 | VisualGDB settings 116 | 117 | 118 | VisualGDB settings 119 | 120 | 121 | 122 | 123 | Source files 124 | 125 | 126 | Source files 127 | 128 | 129 | Source files 130 | 131 | 132 | -------------------------------------------------------------------------------- /stm32/stm32f769_disco_qspi/stm32f769i_eval_qspi.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f769i_eval_qspi.h 4 | * @author MCD Application Team 5 | * @version V2.0.0 6 | * @date 30-December-2016 7 | * @brief This file contains the common defines and functions prototypes for 8 | * the stm32f769i_eval_qspi.c driver. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT(c) 2016 STMicroelectronics

13 | * 14 | * Redistribution and use in source and binary forms, with or without modification, 15 | * are permitted provided that the following conditions are met: 16 | * 1. Redistributions of source code must retain the above copyright notice, 17 | * this list of conditions and the following disclaimer. 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, 19 | * this list of conditions and the following disclaimer in the documentation 20 | * and/or other materials provided with the distribution. 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 22 | * may be used to endorse or promote products derived from this software 23 | * without specific prior written permission. 24 | * 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 | * 36 | ****************************************************************************** 37 | */ 38 | 39 | /** @addtogroup BSP 40 | * @{ 41 | */ 42 | 43 | /** @addtogroup STM32F769I_EVAL 44 | * @{ 45 | */ 46 | 47 | /* Define to prevent recursive inclusion -------------------------------------*/ 48 | #ifndef __STM32F769I_EVAL_QSPI_H 49 | #define __STM32F769I_EVAL_QSPI_H 50 | 51 | #ifdef __cplusplus 52 | extern "C" { 53 | #endif 54 | 55 | /* Includes ------------------------------------------------------------------*/ 56 | #include "stm32f7xx_hal.h" 57 | #include "n25q512a.h" 58 | 59 | /** @addtogroup STM32F769I_EVAL_QSPI 60 | * @{ 61 | */ 62 | 63 | 64 | /* Exported constants --------------------------------------------------------*/ 65 | /** @defgroup STM32F769I_EVAL_QSPI_Exported_Constants Exported Constants 66 | * @{ 67 | */ 68 | /* QSPI Error codes */ 69 | #define QSPI_OK ((uint8_t)0x00) 70 | #define QSPI_ERROR ((uint8_t)0x01) 71 | #define QSPI_BUSY ((uint8_t)0x02) 72 | #define QSPI_NOT_SUPPORTED ((uint8_t)0x04) 73 | #define QSPI_SUSPENDED ((uint8_t)0x08) 74 | 75 | 76 | /* Definition for QSPI clock resources */ 77 | #define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE() 78 | #define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE() 79 | #define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() 80 | #define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() 81 | #define QSPI_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() 82 | #define QSPI_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() 83 | #define QSPI_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() 84 | #define QSPI_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() 85 | 86 | #define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET() 87 | #define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET() 88 | 89 | /* Definition for QSPI Pins */ 90 | #define QSPI_CS_PIN GPIO_PIN_6 91 | #define QSPI_CS_GPIO_PORT GPIOB 92 | #define QSPI_CLK_PIN GPIO_PIN_2 93 | #define QSPI_CLK_GPIO_PORT GPIOB 94 | #define QSPI_D0_PIN GPIO_PIN_8 95 | #define QSPI_D0_GPIO_PORT GPIOF 96 | #define QSPI_D1_PIN GPIO_PIN_9 97 | #define QSPI_D1_GPIO_PORT GPIOF 98 | #define QSPI_D2_PIN GPIO_PIN_7 99 | #define QSPI_D2_GPIO_PORT GPIOF 100 | #define QSPI_D3_PIN GPIO_PIN_6 101 | #define QSPI_D3_GPIO_PORT GPIOF 102 | 103 | /* N25Q512A13GSF40E Micron memory */ 104 | /* Size of the flash */ 105 | #define QSPI_FLASH_SIZE 25 /* Address bus width to access whole memory space */ 106 | #define QSPI_PAGE_SIZE 256 107 | 108 | /** 109 | * @} 110 | */ 111 | 112 | /* Exported types ------------------------------------------------------------*/ 113 | /** @defgroup STM32F769I_EVAL_QSPI_Exported_Types Exported Types 114 | * @{ 115 | */ 116 | /* QSPI Info */ 117 | typedef struct { 118 | uint32_t FlashSize; /*!< Size of the flash */ 119 | uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */ 120 | uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */ 121 | uint32_t ProgPageSize; /*!< Size of pages for the program operation */ 122 | uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */ 123 | } QSPI_Info; 124 | 125 | /** 126 | * @} 127 | */ 128 | 129 | 130 | /* Exported functions --------------------------------------------------------*/ 131 | /** @addtogroup STM32F769I_EVAL_QSPI_Exported_Functions 132 | * @{ 133 | */ 134 | uint8_t BSP_QSPI_Init (void); 135 | uint8_t BSP_QSPI_DeInit (void); 136 | uint8_t BSP_QSPI_Read (uint8_t* pData, uint32_t ReadAddr, uint32_t Size); 137 | uint8_t BSP_QSPI_Write (uint8_t* pData, uint32_t WriteAddr, uint32_t Size); 138 | uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress); 139 | uint8_t BSP_QSPI_Erase_Chip (void); 140 | uint8_t BSP_QSPI_GetStatus (void); 141 | uint8_t BSP_QSPI_GetInfo (QSPI_Info* pInfo); 142 | uint8_t BSP_QSPI_EnableMemoryMappedMode(void); 143 | 144 | /* These functions can be modified in case the current settings 145 | need to be changed for specific application needs */ 146 | void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params); 147 | void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params); 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** 154 | * @} 155 | */ 156 | 157 | #ifdef __cplusplus 158 | } 159 | #endif 160 | 161 | #endif /* __STM32F769I_EVAL_QSPI_H */ 162 | /** 163 | * @} 164 | */ 165 | 166 | /** 167 | * @} 168 | */ 169 | 170 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 171 | -------------------------------------------------------------------------------- /stm32/stm32f7disco_qspi/FLASHPluginConfig.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | 6 | #define MINIMUM_PROGRAMMED_BLOCK_SIZE N25Q128A_PAGE_SIZE 7 | #define FLASH_PLUGIN_SUPPORT_ASYNC_PROGRAMMING 1 -------------------------------------------------------------------------------- /stm32/stm32f7disco_qspi/main.cpp: -------------------------------------------------------------------------------- 1 | #include "FLASHPluginConfig.h" 2 | #include 3 | #include 4 | #include "FLASHPluginInterface.h" 5 | 6 | /* 7 | This file implements the interface required by the Sysprogs OpenOCD fork to support programming QSPI FLASH. 8 | 9 | To use this plugin, add the following to the additional command-line arguments of your OpenOCD: 10 | -c "flash bank qspi plugin 0 0 0 0 path/to/stm32f7disco_qspi.elf" 11 | 12 | The base address is typically 0x90000000. 13 | Then simply start debugging your QSPI-enabled program and OpenOCD will detect and program the QSPI memory automatically. 14 | */ 15 | 16 | #ifdef __cplusplus 17 | extern "C" 18 | #endif 19 | void SysTick_Handler(void) 20 | { 21 | HAL_IncTick(); 22 | HAL_SYSTICK_IRQHandler(); 23 | } 24 | 25 | 26 | FLASHBankInfo FLASHPlugin_Probe(unsigned base, unsigned size, unsigned width1, unsigned width2) 27 | { 28 | InterruptEnabler enabler; 29 | 30 | FLASHBankInfo result = { 31 | .BaseAddress = base, 32 | .BlockCount = N25Q128A_FLASH_SIZE / N25Q128A_SUBSECTOR_SIZE, 33 | .BlockSize = N25Q128A_SUBSECTOR_SIZE, 34 | .WriteBlockSize = MINIMUM_PROGRAMMED_BLOCK_SIZE 35 | }; 36 | return result; 37 | } 38 | 39 | WorkAreaInfo FLASHPlugin_FindWorkArea(void *endOfStack) 40 | { 41 | InterruptEnabler enabler; 42 | 43 | WorkAreaInfo info = { .Address = endOfStack, .Size = 4096 }; 44 | return info; 45 | } 46 | 47 | int FLASHPlugin_EraseSectors(unsigned firstSector, unsigned sectorCount) 48 | { 49 | InterruptEnabler enabler; 50 | int initialTick = HAL_GetTick(); 51 | int timeout = 5000; 52 | 53 | for (unsigned i = 0; i < sectorCount; i++) 54 | { 55 | if ((HAL_GetTick() - initialTick) > timeout) 56 | return i; //OpenOCD will continue the erase operation 57 | 58 | uint8_t error = BSP_QSPI_Erase_Block((firstSector + i) * N25Q128A_SUBSECTOR_SIZE); 59 | if (error != QSPI_OK) 60 | return -1; 61 | } 62 | return sectorCount; 63 | } 64 | 65 | int FLASHPlugin_Unload() 66 | { 67 | BSP_QSPI_DeInit(); 68 | HAL_DeInit(); 69 | SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; 70 | 71 | for (int i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) 72 | NVIC->ICER[0] = -1; 73 | 74 | return 0; 75 | } 76 | 77 | int FLASHPlugin_DoProgramSync(unsigned startOffset, const void *pData, int bytesToWrite) 78 | { 79 | uint8_t result = BSP_QSPI_Write((uint8_t *)pData, startOffset, bytesToWrite); 80 | if (result != QSPI_OK) 81 | return 0; 82 | return bytesToWrite; 83 | } 84 | 85 | 86 | int main(void) 87 | { 88 | extern void *g_pfnVectors; 89 | 90 | SCB->VTOR = (uint32_t)&g_pfnVectors; 91 | HAL_Init(); 92 | BSP_QSPI_Init(); 93 | FLASHPlugin_InitDone(); 94 | 95 | #ifdef DEBUG 96 | TestFLASHProgramming(0x90000000, 0); 97 | #endif 98 | 99 | for (;;) 100 | ; 101 | } 102 | -------------------------------------------------------------------------------- /stm32/stm32f7disco_qspi/stm32.props: -------------------------------------------------------------------------------- 1 | 2 | 8 | 9 | 10 | 11 | 12 | ARM_MATH_CM7;sram_layout;STM32F746NG;STM32F746xx;USE_HAL_DRIVER;VECT_TAB_SRAM;%(ClCompile.PreprocessorDefinitions) 13 | %(ClCompile.AdditionalIncludeDirectories);$(ProjectDir);$(BSP_ROOT)/STM32F7xxxx/BSP/STM32746G-Discovery;$(BSP_ROOT)/STM32F7xxxx/STM32F7xx_HAL_Driver/Inc;$(BSP_ROOT)/STM32F7xxxx/STM32F7xx_HAL_Driver/Inc/Legacy;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/Core/Include;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/Device/ST/STM32F7xx/Include;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/Include;$(BSP_ROOT)/STM32F7xxxx/CMSIS_HAL/RTOS2/Include 14 | 15 | 16 | 17 | 18 | $(BSP_ROOT)/STM32F7xxxx/LinkerScripts/STM32F746NG_sram.lds 19 | --specs=nano.specs --specs=nosys.specs %(Link.AdditionalOptions) 20 | 21 | 22 | 23 | $(BSP_ROOT)/STM32F7xxxx/LinkerScripts/STM32F746NG_sram.lds 24 | 25 | 26 | 27 | 28 | cortex-m7 29 | THUMB 30 | soft 31 | fpv5-sp-d16 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /stm32/stm32f7disco_qspi/stm32.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | com.visualgdb.arm-eabi 4 | 5 | 0 6 | 7 | com.sysprogs.arm.stm32 8 | 2022.08 9 | STM32F746NG 10 | STM32F7xxxx/DeviceDefinitions/stm32f746xx.xml 11 | 12 | 13 | 14 | com.sysprogs.bspoptions.primary_memory 15 | sram 16 | 17 | 18 | com.sysprogs.bspoptions.arm.floatmode 19 | -mfloat-abi=soft 20 | 21 | 22 | com.sysprogs.toolchainoptions.arm.libctype 23 | --specs=nano.specs 24 | 25 | 26 | com.sysprogs.toolchainoptions.arm.libnosys 27 | 28 | 29 | 30 | 31 | Device-specific files 32 | stm32.mak 33 | 34 | com.sysprogs.arm.stm32.bspdrv.stm32746g-discovery 35 | com.sysprogs.arm.stm32.hal 36 | com.sysprogs.arm.stm32.ll 37 | 38 | 39 | 40 | 41 | com.sysprogs.bspoptions.stm32746g-discovery.audio 42 | 43 | 44 | com.sysprogs.bspoptions.stm32746g-discovery.camera 45 | 46 | 47 | com.sysprogs.bspoptions.stm32746g-discovery.eeprom 48 | 49 | 50 | com.sysprogs.bspoptions.stm32746g-discovery.lcd 51 | 52 | 53 | com.sysprogs.bspoptions.stm32746g-discovery.qspi 54 | 1 55 | 56 | 57 | com.sysprogs.bspoptions.stm32746g-discovery.sd 58 | 59 | 60 | com.sysprogs.bspoptions.stm32746g-discovery.sdram 61 | 62 | 63 | com.sysprogs.bspoptions.stm32746g-discovery.ts 64 | 65 | 66 | com.sysprogs.stm32.legacy_hal_src 67 | 68 | 69 | 70 | com.sysprogs.bspoptions.stm32.ll_driver 71 | 72 | 73 | com.sysprogs.bspoptions.stm32746g_discovery.audio 74 | 75 | 76 | 77 | com.sysprogs.bspoptions.stm32746g_discovery.camera 78 | 79 | 80 | 81 | com.sysprogs.bspoptions.stm32746g_discovery.eeprom 82 | 83 | 84 | 85 | com.sysprogs.bspoptions.stm32746g_discovery.lcd 86 | 87 | 88 | 89 | com.sysprogs.bspoptions.stm32746g_discovery.qspi 90 | 1 91 | 92 | 93 | com.sysprogs.bspoptions.stm32746g_discovery.sd 94 | 95 | 96 | 97 | com.sysprogs.bspoptions.stm32746g_discovery.sdram 98 | 99 | 100 | 101 | com.sysprogs.bspoptions.stm32746g_discovery.ts 102 | 103 | 104 | 105 | 106 | -------------------------------------------------------------------------------- /stm32/stm32f7disco_qspi/stm32f7disco_qspi-Debug.vgdbsettings: -------------------------------------------------------------------------------- 1 | 2 | 3 | Debug 4 | 5 | 6 | 7 | MinGWUnixSlash 8 | 9 | true 10 | $(ProjectDir) 11 | false 12 | false 13 | stm32.xml 14 | DeviceDefinition 15 | false 16 | 17 | 18 | 19 | 20 | com.visualgdb.arm-eabi 21 | 22 | 6.2.0 23 | 7.12 24 | 4 25 | 26 | 27 | stm32f7disco_qspi.vcxproj 28 | 0 29 | true 30 | false 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | Default 44 | 45 | 46 | 47 | true 48 | 49 | 50 | 51 | 52 | Unknown 53 | 54 | true 55 | false 56 | 57 | 58 | 59 | 60 | false 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | set $sp=&_estack 70 | 71 | 72 | 73 | 74 | false 75 | false 76 | false 77 | false 78 | false 79 | false 80 | false 81 | false 82 | false 83 | 84 | false 85 | false 86 | false 87 | false 88 | false 89 | false 90 | true 91 | false 92 | None 93 | false 94 | false 95 | main 96 | true 97 | false 98 | false 99 | true 100 | 0 101 | false 102 | 0 103 | true 104 | false 105 | 106 | 107 | com.sysprogs.arm.openocd 108 | 109 | -f interface/stlink-v2-1.cfg -f target/stm32f7x.cfg 110 | 111 | 112 | 113 | false 114 | 115 | 131072 116 | Enabled 117 | 118 | set remotetimeout 60 119 | target remote :$$SYS:GDB_PORT$$ 120 | mon reset init 121 | load 122 | 123 | false 124 | 0 125 | 0 126 | false 127 | 128 | 129 | 130 | true 131 | Auto 132 | 0 133 | false 134 | false 135 | true 136 | false 137 | false 138 | 139 | _estack 140 | 0 141 | false 142 | 143 | None 144 | true 145 | 146 | -------------------------------------------------------------------------------- /stm32/stm32f7disco_qspi/stm32f7disco_qspi-Release.vgdbsettings: -------------------------------------------------------------------------------- 1 | 2 | 3 | Release 4 | 5 | 6 | 7 | MinGWUnixSlash 8 | 9 | $(ProjectDir) 10 | stm32.xml 11 | 12 | 13 | 14 | com.visualgdb.arm-eabi 15 | 16 | 6.2.0 17 | 7.12 18 | 4 19 | 20 | 21 | stm32f7disco_qspi.vcxproj 22 | 0 23 | true 24 | 25 | 26 | 27 | 28 | 29 | false 30 | false 31 | false 32 | false 33 | false 34 | false 35 | false 36 | false 37 | false 38 | 39 | false 40 | false 41 | false 42 | false 43 | false 44 | false 45 | true 46 | false 47 | None 48 | false 49 | false 50 | main 51 | true 52 | false 53 | false 54 | false 55 | 56 | 57 | com.sysprogs.arm.openocd 58 | 59 | 60 | 61 | com.sysprogs.arm.openocd.interface 62 | interface/stlink-v2-1.cfg 63 | 64 | 65 | com.sysprogs.arm.openocd.cpu 66 | 67 | 68 | 69 | com.sysprogs.arm.openocd.chip 70 | 71 | 72 | 73 | com.sysprogs.arm.openocd.board 74 | 75 | 76 | 77 | com.sysprogs.arm.openocd.target 78 | target/stm32f7x.cfg 79 | 80 | 81 | com.sysprogs.arm.openocd.extraargs 82 | -c init -c "reset init" 83 | 84 | 85 | com.sysprogs.arm.openocd.initargs 86 | 87 | 88 | 89 | com.sysprogs.arm.openocd.commands.halt 90 | mon halt 91 | 92 | 93 | com.sysprogs.arm.openocd.commands.program 94 | load 95 | 96 | 97 | com.sysprogs.arm.openocd.commands.autoprogram 98 | 99 | 100 | 101 | com.sysprogs.arm.openocd.commands.reset 102 | mon reset init 103 | 104 | 105 | com.sysprogs.arm.openocd.commands.resetafter 106 | 107 | 108 | 109 | com.sysprogs.arm.openocd.quicksetup.enabled 110 | 1 111 | 112 | 113 | com.sysprogs.arm.openocd.delay 114 | 0 115 | 116 | 117 | com.sysprogs.arm.openocd.transport 118 | 119 | 120 | 121 | com.sysprogs.arm.openocd.quicksetup.interface 122 | stlink-v2-1 123 | 124 | 125 | 126 | 127 | true 128 | Auto 129 | false 130 | false 131 | true 132 | false 133 | true 134 | 135 | _estack 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | Default 149 | 150 | 151 | 152 | true 153 | 154 | 155 | 156 | 157 | Unknown 158 | 159 | true 160 | false 161 | 162 | 163 | false 164 | 165 | 166 | -------------------------------------------------------------------------------- /stm32/stm32f7disco_qspi/stm32f7disco_qspi.sln: -------------------------------------------------------------------------------- 1 | Microsoft Visual Studio Solution File, Format Version 12.00 2 | # Visual Studio 15 3 | VisualStudioVersion = 15.0.26430.15 4 | MinimumVisualStudioVersion = 10.0.40219.1 5 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "stm32f7disco_qspi", "stm32f7disco_qspi.vcxproj", "{D36E11D1-20DB-4B3B-A5CE-64716E38B323}" 6 | EndProject 7 | Global 8 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 9 | Debug|VisualGDB = Debug|VisualGDB 10 | Release|VisualGDB = Release|VisualGDB 11 | EndGlobalSection 12 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 13 | {D36E11D1-20DB-4B3B-A5CE-64716E38B323}.Debug|VisualGDB.ActiveCfg = Debug|VisualGDB 14 | {D36E11D1-20DB-4B3B-A5CE-64716E38B323}.Debug|VisualGDB.Build.0 = Debug|VisualGDB 15 | {D36E11D1-20DB-4B3B-A5CE-64716E38B323}.Release|VisualGDB.ActiveCfg = Release|VisualGDB 16 | {D36E11D1-20DB-4B3B-A5CE-64716E38B323}.Release|VisualGDB.Build.0 = Release|VisualGDB 17 | EndGlobalSection 18 | GlobalSection(SolutionProperties) = preSolution 19 | HideSolutionNode = FALSE 20 | EndGlobalSection 21 | EndGlobal 22 | -------------------------------------------------------------------------------- /stm32f769_disco_qspi.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/stm32f769_disco_qspi.elf -------------------------------------------------------------------------------- /stm32f7disco_qspi.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sysprogs/flash_drivers/9b573382f7899da79b7a4c07633ebeabd51ff227/stm32f7disco_qspi.elf --------------------------------------------------------------------------------