├── .gitmodules ├── sample ├── work │ ├── default │ │ └── test.f │ ├── ready_delay │ │ └── test.f │ ├── read_interleave │ │ └── test.f │ ├── out_of_order_response │ │ └── test.f │ ├── request_delay │ │ └── test.f │ ├── response_delay │ │ └── test.f │ ├── wvalid_preceding_awvalid │ │ └── test.f │ ├── vivado.mk │ ├── dsim.mk │ ├── makefile │ ├── vcs.mk │ └── xcelium.mk └── env │ ├── compile.f │ ├── tvip_axi_sample_pkg.sv │ ├── top.sv │ ├── tvip_axi_sample_test.svh │ ├── tvip_axi_sample_write_read_sequence.svh │ ├── tvip_axi_sample_configuration.svh │ └── tvip_axi_sample_delay.sv ├── .gitignore ├── compile.f ├── .github └── FUNDING.yml ├── src ├── tvip_axi_ral_predictor.svh ├── tvip_axi_undef_internal_macros.svh ├── tvip_axi_internal_macros.svh ├── tvip_axi_status.svh ├── tvip_axi_sequence_base.svh ├── tvip_axi_defines.svh ├── tvip_axi_master_read_sequence.svh ├── tvip_axi_master_write_sequence.svh ├── tvip_axi_master_sequencer.svh ├── tvip_axi_master_agent.svh ├── tvip_axi_master_sequence_base.svh ├── tvip_axi_memory.svh ├── tvip_axi_slave_data_monitor.svh ├── tvip_axi_slave_sequence_base.svh ├── tvip_axi_master_monitor.svh ├── tvip_axi_slave_agent.svh ├── tvip_axi_slave_monitor.svh ├── tvip_axi_component_base.svh ├── tvip_axi_payload_store.svh ├── tvip_axi_pkg.sv ├── tvip_axi_slave_sequencer.svh ├── tvip_axi_driver_base.svh ├── tvip_axi_ral_adapter.svh ├── tvip_axi_agent_base.svh ├── tvip_axi_sequencer_base.svh ├── tvip_axi_slave_default_sequence.svh ├── tvip_axi_if.sv ├── tvip_axi_types_pkg.sv ├── tvip_axi_master_access_sequence.svh ├── tvip_axi_configuration.svh ├── tvip_axi_monitor_base.svh ├── tvip_axi_master_driver.svh ├── tvip_axi_item.svh └── tvip_axi_slave_driver.svh ├── compile.rb ├── setup_submodules.sh ├── README.md └── LICENSE /.gitmodules: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /sample/work/default/test.f: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /tue/ 2 | /tvip-common/ 3 | -------------------------------------------------------------------------------- /sample/work/ready_delay/test.f: -------------------------------------------------------------------------------- 1 | +ENABLE_READY_DELAY 2 | 3 | -------------------------------------------------------------------------------- /sample/work/read_interleave/test.f: -------------------------------------------------------------------------------- 1 | +ENABLE_READ_INTERLEAVE 2 | 3 | -------------------------------------------------------------------------------- /compile.f: -------------------------------------------------------------------------------- 1 | +incdir+${TVIP_AXI_HOME}/src 2 | ${TVIP_AXI_HOME}/src/tvip_axi_pkg.sv 3 | -------------------------------------------------------------------------------- /sample/work/out_of_order_response/test.f: -------------------------------------------------------------------------------- 1 | +ENABLE_OUT_OF_ORDER_RESPONSE 2 | 3 | -------------------------------------------------------------------------------- /sample/work/request_delay/test.f: -------------------------------------------------------------------------------- 1 | +ENABLE_REQUEST_START_DELAY 2 | +ENABLE_WRITE_DATA_DELAY 3 | 4 | -------------------------------------------------------------------------------- /sample/work/response_delay/test.f: -------------------------------------------------------------------------------- 1 | +ENABLE_RESPONSE_START_DELAY 2 | +ENABLE_RESPONSE_DELAY 3 | 4 | -------------------------------------------------------------------------------- /sample/work/wvalid_preceding_awvalid/test.f: -------------------------------------------------------------------------------- 1 | +ENABLE_READY_DELAY 2 | +write_address_delay 3 | 4 | -------------------------------------------------------------------------------- /sample/env/compile.f: -------------------------------------------------------------------------------- 1 | +incdir+${TVIP_AXI_HOME}/sample/env 2 | ${TVIP_AXI_HOME}/sample/env/tvip_axi_sample_pkg.sv 3 | -------------------------------------------------------------------------------- /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | github: [taichi-ishitani] 4 | ko_fi: taichi730 5 | -------------------------------------------------------------------------------- /src/tvip_axi_ral_predictor.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_RAL_PREDICTOR_SVH 2 | `define TVIP_AXI_RAL_PREDICTOR_SVH 3 | typedef tue_reg_predictor #(tvip_axi_item) tvip_axi_ral_predictor; 4 | `endif 5 | -------------------------------------------------------------------------------- /src/tvip_axi_undef_internal_macros.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_UNDEF_INTERNAL_MACROS_SVH 2 | `define TVIP_AXI_UNDEF_INTERNAL_MACROS_SVH 3 | 4 | `undef tvip_axi_4kb_boundary_mask 5 | 6 | `endif 7 | -------------------------------------------------------------------------------- /src/tvip_axi_internal_macros.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_INTERNAL_MACROS_SVH 2 | `define TVIP_AXI_INTERNAL_MACROS_SVH 3 | 4 | `define tvip_axi_4kb_boundary_mask(BURST_SIZE) \ 5 | (tvip_axi_address'('h1000 - BURST_SIZE)) 6 | 7 | `endif 8 | -------------------------------------------------------------------------------- /compile.rb: -------------------------------------------------------------------------------- 1 | if ENV.key?('TVIP_COMMON_HOME') 2 | file_list File.join(ENV['TVIP_COMMON_HOME'], 'compile.rb') 3 | elsif Dir.exist?(File.join(__dir__, 'tvip-common')) 4 | file_list 'tvip-common/compile.rb', from: :current 5 | end 6 | 7 | include_directory 'src' 8 | source_file 'src/tvip_axi_pkg.sv' 9 | -------------------------------------------------------------------------------- /src/tvip_axi_status.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_STATUS_SVH 2 | `define TVIP_AXI_STATUS_SVH 3 | typedef class tvip_axi_memory; 4 | 5 | class tvip_axi_status extends tue_status; 6 | tvip_axi_memory memory; 7 | `tue_object_default_constructor(tvip_axi_status) 8 | `uvm_object_utils(tvip_axi_status) 9 | endclass 10 | `endif 11 | -------------------------------------------------------------------------------- /src/tvip_axi_sequence_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SEQUENCE_BASE_SVH 2 | `define TVIP_AXI_SEQUENCE_BASE_SVH 3 | class tvip_axi_sequence_base #( 4 | type BASE = uvm_sequence, 5 | type SEQUENCER = uvm_sequencer 6 | ) extends BASE; 7 | `tue_object_default_constructor(tvip_axi_sequence_base) 8 | `uvm_declare_p_sequencer(SEQUENCER) 9 | endclass 10 | `endif 11 | -------------------------------------------------------------------------------- /src/tvip_axi_defines.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_DEFINES_SVH 2 | `define TVIP_AXI_DEFINES_SVH 3 | 4 | `ifndef TVIP_AXI_MAX_ID_WIDTH 5 | `define TVIP_AXI_MAX_ID_WIDTH 32 6 | `endif 7 | 8 | `ifndef TVIP_AXI_MAX_ADDRESS_WIDTH 9 | `define TVIP_AXI_MAX_ADDRESS_WIDTH 64 10 | `endif 11 | 12 | `ifndef TVIP_AXI_MAX_DATA_WIDTH 13 | `define TVIP_AXI_MAX_DATA_WIDTH 1024 14 | `endif 15 | 16 | `endif 17 | -------------------------------------------------------------------------------- /src/tvip_axi_master_read_sequence.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_READ_SEQUENCE_SVH 2 | `define TVIP_AXI_MASTER_READ_SEQUENCE_SVH 3 | class tvip_axi_master_read_sequence extends tvip_axi_master_access_sequence; 4 | constraint c_valid_access_type { 5 | access_type == TVIP_AXI_READ_ACCESS; 6 | } 7 | `tue_object_default_constructor(tvip_axi_master_read_sequence) 8 | `uvm_object_utils(tvip_axi_master_read_sequence) 9 | endclass 10 | `endif 11 | -------------------------------------------------------------------------------- /src/tvip_axi_master_write_sequence.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_WRITE_SEQUENCE_SVH 2 | `define TVIP_AXI_MASTER_WRITE_SEQUENCE_SVH 3 | class tvip_axi_master_write_sequence extends tvip_axi_master_access_sequence; 4 | constraint c_valid_access_type { 5 | access_type == TVIP_AXI_WRITE_ACCESS; 6 | } 7 | `tue_object_default_constructor(tvip_axi_master_write_sequence) 8 | `uvm_object_utils(tvip_axi_master_write_sequence) 9 | endclass 10 | `endif 11 | -------------------------------------------------------------------------------- /sample/env/tvip_axi_sample_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SAMPLE_PKG_SV 2 | `define TVIP_AXI_SAMPLE_PKG_SV 3 | package tvip_axi_sample_pkg; 4 | import uvm_pkg::*; 5 | import tue_pkg::*; 6 | import tvip_axi_types_pkg::*; 7 | import tvip_axi_pkg::*; 8 | 9 | `include "uvm_macros.svh" 10 | `include "tue_macros.svh" 11 | 12 | `include "tvip_axi_sample_configuration.svh" 13 | `include "tvip_axi_sample_write_read_sequence.svh" 14 | `include "tvip_axi_sample_test.svh" 15 | endpackage 16 | `endif 17 | -------------------------------------------------------------------------------- /setup_submodules.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash -f 2 | submodules=( 3 | "https://github.com/taichi-ishitani/tue.git tue b49856a47ed162fd0eea4509f2495465d0091e7f" 4 | "https://github.com/taichi-ishitani/tvip-common.git tvip-common be09036727aac5be4c483536b12e7a1e3c0c8b8b" 5 | ) 6 | 7 | for ((i=0; $i < ${#submodules[*]}; i++)) do 8 | temp=(${submodules[$i]}) 9 | url=${temp[0]} 10 | path=${temp[1]} 11 | hash=${temp[2]} 12 | if [ ! -d $path ]; then 13 | git clone $url $path 14 | fi 15 | $(cd $path; git fetch; git checkout $hash) 16 | done 17 | -------------------------------------------------------------------------------- /src/tvip_axi_master_sequencer.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_SEQUENCER_SVH 2 | `define TVIP_AXI_MASTER_SEQUENCER_SVH 3 | typedef tue_sequencer #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .REQ (tvip_axi_master_item ) 7 | ) tvip_axi_master_sequencer_base; 8 | 9 | class tvip_axi_master_sequencer extends tvip_axi_sequencer_base #( 10 | .BASE (tvip_axi_master_sequencer_base ) 11 | ); 12 | `tue_component_default_constructor(tvip_axi_master_sequencer) 13 | `uvm_component_utils(tvip_axi_master_sequencer) 14 | endclass 15 | `endif 16 | -------------------------------------------------------------------------------- /src/tvip_axi_master_agent.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_AGENT_SVH 2 | `define TVIP_AXI_MASTER_AGENT_SVH 3 | typedef tvip_axi_agent_base #( 4 | .WRITE_MONITOR (tvip_axi_master_write_monitor ), 5 | .READ_MONITOR (tvip_axi_master_read_monitor ), 6 | .SEQUENCER (tvip_axi_master_sequencer ), 7 | .DRIVER (tvip_axi_master_driver ) 8 | ) tvip_axi_master_agent_base; 9 | 10 | class tvip_axi_master_agent extends tvip_axi_master_agent_base; 11 | `tue_component_default_constructor(tvip_axi_master_agent) 12 | `uvm_component_utils(tvip_axi_master_agent) 13 | endclass 14 | `endif 15 | -------------------------------------------------------------------------------- /src/tvip_axi_master_sequence_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_SEQUENCE_BASE_SVH 2 | `define TVIP_AXI_MASTER_SEQUENCE_BASE_SVH 3 | typedef tue_sequence #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .REQ (tvip_axi_master_item ) 7 | ) tvip_axi_master_sequence_base_base; 8 | 9 | class tvip_axi_master_sequence_base extends tvip_axi_sequence_base #( 10 | .BASE (tvip_axi_master_sequence_base_base ), 11 | .SEQUENCER (tvip_axi_master_sequencer ) 12 | ); 13 | function new(string name = "tvip_axi_master_sequence_base"); 14 | super.new(name); 15 | set_automatic_phase_objection(0); 16 | endfunction 17 | endclass 18 | `endif 19 | -------------------------------------------------------------------------------- /src/tvip_axi_memory.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MEMORY_SVH 2 | `define TVIP_AXI_MEMORY_SVH 3 | typedef tvip_memory #( 4 | .ADDRESS_WIDTH ($bits(tvip_axi_address) ), 5 | .DATA_WIDTH ($bits(tvip_axi_data) ) 6 | ) tvip_axi_memory_base; 7 | 8 | class tvip_axi_memory extends tue_object_base #( 9 | .BASE (tvip_axi_memory_base ), 10 | .CONFIGURATION (tvip_axi_configuration ), 11 | .STATUS (tvip_axi_status ) 12 | ); 13 | function void set_configuration(tue_configuration configuration); 14 | super.set_configuration(configuration); 15 | byte_width = this.configuration.data_width / 8; 16 | endfunction 17 | 18 | `tue_object_default_constructor(tvip_axi_memory) 19 | `uvm_object_utils(tvip_axi_memory) 20 | endclass 21 | `endif 22 | -------------------------------------------------------------------------------- /src/tvip_axi_slave_data_monitor.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SLAVE_DATA_MONITOR_SVH 2 | `define TVIP_AXI_SLAVE_DATA_MONITOR_SVH 3 | class tvip_axi_slave_data_monitor extends tue_subscriber #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .T (tvip_axi_item ) 7 | ); 8 | protected tvip_axi_memory memory; 9 | 10 | function void build_phase(uvm_phase phase); 11 | super.build_phase(phase); 12 | if (status.memory == null) begin 13 | status.memory = tvip_axi_memory::type_id::create("memory"); 14 | status.memory.set_context(configuration, status); 15 | end 16 | memory = status.memory; 17 | endfunction 18 | 19 | function void write(tvip_axi_item t); 20 | foreach (t.data[i]) begin 21 | memory.put(t.data[i], t.strobe[i], t.burst_size, t.address, i); 22 | end 23 | endfunction 24 | 25 | `tue_component_default_constructor(tvip_axi_slave_data_monitor) 26 | `uvm_component_utils(tvip_axi_slave_data_monitor) 27 | endclass 28 | `endif 29 | -------------------------------------------------------------------------------- /sample/work/vivado.mk: -------------------------------------------------------------------------------- 1 | CLEAN_TARGET += *.pb 2 | CLEAN_TARGET += *.jou 3 | CLEAN_TARGET += *.wdb 4 | CLEAN_TARGET += vivado_*.str 5 | CLEAN_TARGET += xsim.dir 6 | CLEAN_TARGET += .Xil 7 | 8 | XVLOG_ARGS += -sv 9 | XVLOG_ARGS += -log xvlog.log 10 | XVLOG_ARGS += -L uvm 11 | XVLOG_ARGS += -verbose 2 12 | XVLOG_ARGS += $(subst +incdir+, -i , $(shell cat $(FILE_LISTS) | grep +incdir+)) 13 | XVLOG_ARGS += $(shell cat $(FILE_LISTS) | grep -v +incdir+) 14 | 15 | XELAB_ARGS += -log xelab.log 16 | XELAB_ARGS += -verbose 2 17 | XELAB_ARGS += -timescale 1ns/1ps 18 | XELAB_ARGS += -L uvm 19 | XELAB_ARGS += top 20 | 21 | XSIM_ARGS += work.top 22 | XSIM_ARGS += -log $(TEST)/xsim.log 23 | XSIM_ARGS += -f $(TEST)/test.f 24 | 25 | ifeq ($(strip $(GUI)), on) 26 | XELAB_ARGS += -debug all 27 | XSIM_ARGS += -gui 28 | else 29 | XSIM_ARGS += -R 30 | endif 31 | 32 | .PHONY: sim_vivado compile_vivado 33 | 34 | sim_vivado: 35 | [ -d xsim.dir ] || ($(MAKE) compile_vivado) 36 | xsim $(XSIM_ARGS) 37 | 38 | compile_vivado: 39 | xvlog $(XVLOG_ARGS) $(SOURCE_FILES) 40 | xelab $(XELAB_ARGS) 41 | -------------------------------------------------------------------------------- /sample/env/top.sv: -------------------------------------------------------------------------------- 1 | module top(); 2 | timeunit 1ns; 3 | timeprecision 1ps; 4 | 5 | import uvm_pkg::*; 6 | import tue_pkg::*; 7 | import tvip_axi_types_pkg::*; 8 | import tvip_axi_pkg::*; 9 | import tvip_axi_sample_pkg::*; 10 | 11 | bit aclk = 0; 12 | initial begin 13 | forever begin 14 | #(0.5ns); 15 | aclk ^= 1'b1; 16 | end 17 | end 18 | 19 | bit areset_n = 0; 20 | initial begin 21 | repeat (20) @(posedge aclk); 22 | areset_n = 1; 23 | end 24 | 25 | tvip_axi_if axi_if[2](aclk, areset_n); 26 | 27 | tvip_axi_sample_delay #( 28 | .WRITE_ADDRESS_DELAY (8 ), 29 | .WRITE_DATA_DELAY (8 ), 30 | .WRITE_RESPONSE_DELAY (8 ), 31 | .READ_ADDRESS_DELAY (8 ), 32 | .READ_RESPONSE_DELAY (8 ) 33 | ) u_delay ( 34 | aclk, areset_n, axi_if[0], axi_if[1] 35 | ); 36 | 37 | initial begin 38 | uvm_config_db #(tvip_axi_vif)::set(null, "", "vif[0]", axi_if[0]); 39 | uvm_config_db #(tvip_axi_vif)::set(null, "", "vif[1]", axi_if[1]); 40 | run_test("tvip_axi_sample_test"); 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /sample/work/dsim.mk: -------------------------------------------------------------------------------- 1 | DSIM_COMP_ARGS += -genimage image 2 | DSIM_COMP_ARGS += -uvm $(UVM_VERSION) 3 | DSIM_COMP_ARGS += -l dsim_comp.log 4 | DSIM_COMP_ARGS += -timescale 1ns/1ps 5 | DSIM_COMP_ARGS += +define+UVM_NO_DEPRECATED 6 | DSIM_COMP_ARGS += +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTO 7 | DSIM_COMP_ARGS += -top top 8 | 9 | DSIM_SIM_ARGS += -work ../dsim_work 10 | DSIM_SIM_ARGS += -image image 11 | DSIM_SIM_ARGS += -uvm $(UVM_VERSION) 12 | DSIM_SIM_ARGS += -l dsim_simulation.log 13 | DSIM_SIM_ARGS += -f test.f 14 | 15 | ifneq ($(strip $(RANDOM_SEED)), auto) 16 | DSIM_SIM_ARGS += -sv_seed $(RANDOM_SEED) 17 | endif 18 | 19 | ifeq ($(strip $(DUMP)), vcd) 20 | DSIM_COMP_ARGS += +acc 21 | DSIM_SIM_ARGS += -waves dump.vcd 22 | endif 23 | 24 | CLEAN_TARGET += dsim.env 25 | CLEAN_TARGET += dsim_work 26 | CLEAN_TARGET += */dsim.env 27 | CLEAN_TARGET += */metrics.db 28 | 29 | CLEAN_ALL_TARGET += *.vcd 30 | 31 | .PHONY: sim_dsim compile_dsim 32 | 33 | sim_dsim: 34 | [ -f dsim_work/image.so ] || ($(MAKE) compile_dsim) 35 | cd $(TEST); dsim $(DSIM_SIM_ARGS) 36 | 37 | compile_dsim: 38 | dsim $(DSIM_COMP_ARGS) $(addprefix -f , $(FILE_LISTS)) $(SOURCE_FILES) 39 | -------------------------------------------------------------------------------- /src/tvip_axi_slave_sequence_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SLAVE_SEQUENCE_BASE_SVH 2 | `define TVIP_AXI_SLAVE_SEQUENCE_BASE_SVH 3 | typedef tue_sequence #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .REQ (tvip_axi_slave_item ) 7 | ) tvip_axi_slave_sequence_base_base; 8 | 9 | virtual class tvip_axi_slave_sequence_base extends tvip_axi_sequence_base #( 10 | .BASE (tvip_axi_slave_sequence_base_base ), 11 | .SEQUENCER (tvip_axi_slave_sequencer ) 12 | ); 13 | function new(string name = "tvip_axi_master_sequence_base"); 14 | super.new(name); 15 | set_automatic_phase_objection(0); 16 | endfunction 17 | 18 | virtual task get_request( 19 | input tvip_axi_access_type access_type, 20 | ref tvip_axi_slave_item request 21 | ); 22 | p_sequencer.get_request(access_type, request); 23 | endtask 24 | 25 | virtual task get_write_request(ref tvip_axi_slave_item request); 26 | get_request(TVIP_AXI_WRITE_ACCESS, request); 27 | endtask 28 | 29 | virtual task get_read_request(ref tvip_axi_slave_item request); 30 | get_request(TVIP_AXI_READ_ACCESS, request); 31 | endtask 32 | endclass 33 | `endif 34 | -------------------------------------------------------------------------------- /src/tvip_axi_master_monitor.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_MONITOR_SVH 2 | `define TVIP_AXI_MASTER_MONITOR_SVH 3 | typedef tue_param_monitor #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .ITEM (tvip_axi_item ) 7 | ) tvip_axi_master_monitor_base; 8 | 9 | virtual class tvip_axi_master_monitor extends tvip_axi_monitor_base #( 10 | .BASE (tvip_axi_master_monitor_base ), 11 | .ITEM (tvip_axi_master_item ) 12 | ); 13 | `tue_component_default_constructor(tvip_axi_master_monitor) 14 | endclass 15 | 16 | class tvip_axi_master_write_monitor extends tvip_axi_master_monitor; 17 | function new(string name = "tvip_axi_master_write_monitor", uvm_component parent = null); 18 | super.new(name, parent); 19 | write_component = 1; 20 | endfunction 21 | `uvm_component_utils(tvip_axi_master_write_monitor) 22 | endclass 23 | 24 | class tvip_axi_master_read_monitor extends tvip_axi_master_monitor; 25 | function new(string name = "tvip_axi_master_read_monitor", uvm_component parent = null); 26 | super.new(name, parent); 27 | write_component = 0; 28 | endfunction 29 | `uvm_component_utils(tvip_axi_master_read_monitor) 30 | endclass 31 | `endif 32 | -------------------------------------------------------------------------------- /src/tvip_axi_slave_agent.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SLAVE_AGENT_SVH 2 | `define TVIP_AXI_SLAVE_AGENT_SVH 3 | typedef tvip_axi_agent_base #( 4 | .WRITE_MONITOR (tvip_axi_slave_write_monitor ), 5 | .READ_MONITOR (tvip_axi_slave_read_monitor ), 6 | .SEQUENCER (tvip_axi_slave_sequencer ), 7 | .DRIVER (tvip_axi_slave_driver ) 8 | ) tvip_axi_slave_agent_base; 9 | 10 | class tvip_axi_slave_agent extends tvip_axi_slave_agent_base; 11 | tvip_axi_slave_data_monitor data_monitor; 12 | 13 | function void build_phase(uvm_phase phase); 14 | super.build_phase(phase); 15 | data_monitor = tvip_axi_slave_data_monitor::type_id::create("data_monitor", this); 16 | data_monitor.set_context(configuration, status); 17 | endfunction 18 | 19 | function void connect_phase(uvm_phase phase); 20 | super.connect_phase(phase); 21 | write_monitor.request_item_port.connect(data_monitor.analysis_export); 22 | if (is_active_agent()) begin 23 | write_monitor.request_port.connect(sequencer.request_export); 24 | read_monitor.request_port.connect(sequencer.request_export); 25 | end 26 | endfunction 27 | 28 | `tue_component_default_constructor(tvip_axi_slave_agent) 29 | `uvm_component_utils(tvip_axi_slave_agent) 30 | endclass 31 | `endif 32 | -------------------------------------------------------------------------------- /sample/work/makefile: -------------------------------------------------------------------------------- 1 | TVIP_AXI_HOME = $(shell git rev-parse --show-toplevel) 2 | export TVIP_AXI_HOME 3 | 4 | TUE_HOME ?= $(TVIP_AXI_HOME)/tue 5 | export TUE_HOME 6 | 7 | TVIP_COMMON_HOME ?= $(TVIP_AXI_HOME)/tvip-common 8 | export TVIP_COMMON_HOME 9 | 10 | FILE_LISTS += $(TUE_HOME)/compile.f 11 | FILE_LISTS += $(TVIP_COMMON_HOME)/compile.f 12 | FILE_LISTS += $(TVIP_AXI_HOME)/compile.f 13 | FILE_LISTS += $(TVIP_AXI_HOME)/sample/env/compile.f 14 | 15 | SOURCE_FILES += $(TVIP_AXI_HOME)/sample/env/tvip_axi_sample_delay.sv 16 | SOURCE_FILES += $(TVIP_AXI_HOME)/sample/env/top.sv 17 | 18 | SIMULATOR ?= vcs 19 | RANDOM_SEED ?= auto 20 | DUMP ?= off 21 | GUI ?= off 22 | UVM_VERSION ?= 1.2 23 | 24 | TESTS += default 25 | TESTS += request_delay 26 | TESTS += response_delay 27 | TESTS += ready_delay 28 | TESTS += out_of_order_response 29 | TESTS += read_interleave 30 | TESTS += wvalid_preceding_awvalid 31 | 32 | .PHONY: all $(TESTS) clean clean_all 33 | 34 | all: $(TESTS) 35 | 36 | $(TESTS): 37 | make sim_$(SIMULATOR) TEST=$@ 38 | 39 | CLEAN_TARGET += *.log 40 | CLEAN_ALL_TARGET += *.log 41 | CLEAN_ALL_TARGET += *.key 42 | 43 | clean: 44 | rm -rf $(CLEAN_TARGET) 45 | 46 | clean_all: 47 | make clean 48 | rm -rf $(CLEAN_ALL_TARGET) 49 | rm -rf $(addprefix */,$(CLEAN_ALL_TARGET)) 50 | 51 | include vcs.mk 52 | include xcelium.mk 53 | include vivado.mk 54 | include dsim.mk 55 | -------------------------------------------------------------------------------- /src/tvip_axi_slave_monitor.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SLAVE_MONITOR_SVH 2 | `define TVIP_AXI_SLAVE_MONITOR_SVH 3 | typedef tue_reactive_monitor #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .ITEM (tvip_axi_item ) 7 | ) tvip_axi_slave_monitor_base; 8 | 9 | virtual class tvip_axi_slave_monitor extends tvip_axi_monitor_base #( 10 | .BASE (tvip_axi_slave_monitor_base ), 11 | .ITEM (tvip_axi_slave_item ) 12 | ); 13 | task begin_address(tvip_axi_item item); 14 | super.begin_address(item); 15 | write_request(item); 16 | endtask 17 | 18 | function void write_request(tvip_axi_item item); 19 | super.write_request(item); 20 | endfunction 21 | 22 | `tue_component_default_constructor(tvip_axi_master_monitor) 23 | endclass 24 | 25 | class tvip_axi_slave_write_monitor extends tvip_axi_slave_monitor; 26 | function new(string name = "tvip_axi_slave_write_monitor", uvm_component parent = null); 27 | super.new(name, parent); 28 | write_component = 1; 29 | endfunction 30 | `uvm_component_utils(tvip_axi_slave_write_monitor) 31 | endclass 32 | 33 | class tvip_axi_slave_read_monitor extends tvip_axi_slave_monitor; 34 | function new(string name = "tvip_axi_slave_read_monitor", uvm_component parent = null); 35 | super.new(name, parent); 36 | write_component = 0; 37 | endfunction 38 | `uvm_component_utils(tvip_axi_slave_read_monitor) 39 | endclass 40 | `endif 41 | -------------------------------------------------------------------------------- /src/tvip_axi_component_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_COMPONENT_BASE_SVH 2 | `define TVIP_AXI_COMPONENT_BASE_SVH 3 | virtual class tvip_axi_component_base #( 4 | type BASE = uvm_component 5 | ) extends BASE; 6 | protected bit write_component; 7 | protected tvip_axi_vif vif; 8 | 9 | function void build_phase(uvm_phase phase); 10 | super.build_phase(phase); 11 | vif = configuration.vif; 12 | endfunction 13 | 14 | protected function bit is_write_component(); 15 | return write_component; 16 | endfunction 17 | 18 | protected function bit is_read_component(); 19 | return !write_component; 20 | endfunction 21 | 22 | virtual task begin_address(tvip_axi_item item); 23 | if (!item.write_data_began()) begin 24 | void'(begin_tr(item)); 25 | end 26 | item.begin_address(); 27 | endtask 28 | 29 | virtual task end_address(tvip_axi_item item); 30 | item.end_address(); 31 | endtask 32 | 33 | virtual task begin_write_data(tvip_axi_item item); 34 | if (item.is_write()) begin 35 | if (!item.address_began()) begin 36 | void'(begin_tr(item)); 37 | end 38 | item.begin_write_data(); 39 | end 40 | endtask 41 | 42 | virtual task end_write_data(tvip_axi_item item); 43 | if (item.is_write()) begin 44 | item.end_write_data(); 45 | end 46 | endtask 47 | 48 | virtual task begin_response(tvip_axi_item item); 49 | item.begin_response(); 50 | endtask 51 | 52 | virtual task end_response(tvip_axi_item item); 53 | item.end_response(); 54 | end_tr(item); 55 | endtask 56 | 57 | `tue_component_default_constructor(tvip_axi_component_base) 58 | endclass 59 | `endif 60 | -------------------------------------------------------------------------------- /src/tvip_axi_payload_store.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_PAYLOAD_STORE_SVH 2 | `define TVIP_AXI_PAYLOAD_STORE_SVH 3 | class tvip_axi_payload_store; 4 | tvip_axi_item item; 5 | local tvip_axi_data data[$]; 6 | local tvip_axi_strobe strobe[$]; 7 | local tvip_axi_response response[$]; 8 | 9 | static function tvip_axi_payload_store create(tvip_axi_item item); 10 | tvip_axi_payload_store payload_store = new; 11 | payload_store.item = item; 12 | return payload_store; 13 | endfunction 14 | 15 | function void store_write_data( 16 | tvip_axi_data data, 17 | tvip_axi_strobe strobe 18 | ); 19 | if (item.is_write()) begin 20 | this.data.push_back(data); 21 | this.strobe.push_back(strobe); 22 | end 23 | endfunction 24 | 25 | function void store_response( 26 | tvip_axi_response response, 27 | tvip_axi_data data 28 | ); 29 | this.response.push_back(response); 30 | if (item.is_read()) begin 31 | this.data.push_back(data); 32 | end 33 | endfunction 34 | 35 | function void pack_write_data(); 36 | item.put_data(data); 37 | item.put_strobe(strobe); 38 | endfunction 39 | 40 | function void pack_response(); 41 | item.put_response(response); 42 | if (item.is_read()) begin 43 | item.put_data(data); 44 | end 45 | endfunction 46 | 47 | function int get_stored_write_data_count(); 48 | if (item.is_write()) begin 49 | return data.size(); 50 | end 51 | else begin 52 | return 0; 53 | end 54 | endfunction 55 | 56 | function int get_stored_response_count(); 57 | return response.size(); 58 | endfunction 59 | endclass 60 | `endif 61 | -------------------------------------------------------------------------------- /sample/work/vcs.mk: -------------------------------------------------------------------------------- 1 | VCS_ARGS += -full64 2 | VCS_ARGS += -lca 3 | VCS_ARGS += -sverilog 4 | VCS_ARGS += -l compile.log 5 | VCS_ARGS += -timescale=1ns/1ps 6 | VCS_ARGS += -ntb_opts uvm-$(UVM_VERSION) 7 | VCS_ARGS += +define+UVM_NO_DEPRECATED+UVM_OBJECT_MUST_HAVE_CONSTRUCTO 8 | VCS_ARGS += -top top 9 | 10 | SIMV_ARGS += -l simv.log 11 | SIMV_ARGS += -f test.f 12 | 13 | ifeq ($(strip $(RANDOM_SEED)), auto) 14 | SIMV_ARGS += +ntb_random_seed_automatic 15 | else 16 | SIMV_ARGS += +ntb_random_seed=$(RANDOM_SEED) 17 | endif 18 | 19 | ifeq ($(strip $(DUMP)), vpd) 20 | VCS_ARGS += -debug_access 21 | VCS_ARGS += +vcs+vcdpluson 22 | SIMV_ARGS += -vpd_file dump.vpd 23 | endif 24 | 25 | ifeq ($(strip $(DUMP)), fsdb) 26 | VCS_ARGS += -debug_access 27 | VCS_ARGS += -kdb 28 | VCS_ARGS += +vcs+fsdbon 29 | SIMV_ARGS += +fsdbfile+dump.fsdb 30 | endif 31 | 32 | ifeq ($(strip $(GUI)), dve) 33 | VCS_ARGS += -debug_access+all 34 | VCS_ARGS += +vcs+vcdpluson 35 | SIMV_ARGS += -gui=dve 36 | endif 37 | 38 | ifeq ($(strip $(GUI)), verdi) 39 | VCS_ARGS += -debug_access+all 40 | VCS_ARGS += -kdb 41 | VCS_ARGS += +vcs+fsdbon 42 | SIMV_ARGS += -gui=verdi 43 | endif 44 | 45 | CLEAN_TARGET += simv* 46 | CLEAN_TARGET += csrc 47 | CLEAN_TARGET += *.h 48 | 49 | CLEAN_ALL_TARGET += *.vpd 50 | CLEAN_ALL_TARGET += *.fsdb 51 | CLEAN_ALL_TARGET += *.key 52 | CLEAN_ALL_TARGET += *.conf 53 | CLEAN_ALL_TARGET += *.rc 54 | CLEAN_ALL_TARGET += DVEfiles 55 | CLEAN_ALL_TARGET += verdiLog 56 | CLEAN_ALL_TARGET += .inter.vpd.uvm 57 | 58 | .PHONY: sim_vcs compile_vcs 59 | 60 | sim_vcs: 61 | [ -f simv ] || ($(MAKE) compile_vcs) 62 | cd $(TEST); ../simv $(SIMV_ARGS) 63 | 64 | compile_vcs: 65 | vcs $(VCS_ARGS) $(addprefix -f , $(FILE_LISTS)) $(SOURCE_FILES) 66 | -------------------------------------------------------------------------------- /sample/work/xcelium.mk: -------------------------------------------------------------------------------- 1 | XRUN_COMMON_ARGS += -64bit 2 | XRUN_COMMON_ARGS += -timedetail 3 | XRUN_COMMON_ARGS += -status 4 | 5 | XMVLOG_ARGS += -compile 6 | XMVLOG_ARGS += -uvmhome CDNS-$(UVM_VERSION) 7 | XMVLOG_ARGS += -plusperf 8 | XMVLOG_ARGS += -l xmvlog.log 9 | 10 | XMELAB_ARGS += -elaborate 11 | XMELAB_ARGS += -uvmhome CDNS-$(UVM_VERSION) 12 | XMELAB_ARGS += -uvmnoautocompile 13 | XMELAB_ARGS += -timescale 1ns/1ps 14 | XMELAB_ARGS += -newperf 15 | XMELAB_ARGS += -warn_multiple_driver 16 | XMELAB_ARGS += -top worklib.top 17 | XMELAB_ARGS += -l xmelab.log 18 | 19 | XMSIM_ARGS += -R 20 | XMSIM_ARGS += -uvmhome CDNS-$(UVM_VERSION) 21 | XMSIM_ARGS += -xmlibdirname ../xcelium.d 22 | XMSIM_ARGS += -xceligen on 23 | XMSIM_ARGS += -f test.f 24 | XMSIM_ARGS += -l xmsim.log 25 | 26 | ifeq ($(strip $(RANDOM_SEED)), auto) 27 | XMSIM_ARGS += -svseed random 28 | else 29 | XMSIM_ARGS += -svseed $(RANDOM_SEED) 30 | endif 31 | 32 | ifeq ($(GUI), indago) 33 | XMVLOG_ARGS += -classlinedebug 34 | XMELAB_ARGS += -xmdebug 35 | XMELAB_ARGS += -lwdgen 36 | XMSIM_ARGS += -gui -indago 37 | XMSIM_ARGS += -input @"ida_probe -log" 38 | XMSIM_ARGS += -input @"ida_probe -wave -wave_probe_args=\"-all -depth to_cells\"" 39 | endif 40 | 41 | CLEAN_TARGET += xcelium.d 42 | CLEAN_TARGET += *.history 43 | 44 | CLEAN_ALL_TARGET += ida.db 45 | CLEAN_ALL_TARGET += .ida* 46 | CLEAN_ALL_TARGET += indago_logs 47 | 48 | .PHONY: sim_xcelium compile_xcelium 49 | 50 | sim_xcelium: 51 | (xmls -64bit -nolog -snapshot | grep SSS) || $(MAKE) compile_xcelium 52 | cd $(TEST); xrun $(XRUN_COMMON_ARGS) $(XMSIM_ARGS) 53 | 54 | compile_xcelium: 55 | xrun $(XRUN_COMMON_ARGS) $(XMVLOG_ARGS) $(addprefix -f , $(FILE_LISTS)) $(SOURCE_FILES) 56 | xrun $(XRUN_COMMON_ARGS) $(XMELAB_ARGS) 57 | -------------------------------------------------------------------------------- /src/tvip_axi_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_PKG_SV 2 | `define TVIP_AXI_PKG_SV 3 | 4 | `include "tvip_axi_types_pkg.sv" 5 | `include "tvip_axi_if.sv" 6 | 7 | package tvip_axi_pkg; 8 | import uvm_pkg::*; 9 | import tue_pkg::*; 10 | import tvip_common_pkg::*; 11 | import tvip_axi_types_pkg::*; 12 | 13 | `include "uvm_macros.svh" 14 | `include "tue_macros.svh" 15 | `include "tvip_common_macros.svh" 16 | 17 | typedef virtual tvip_axi_if tvip_axi_vif; 18 | 19 | `include "tvip_axi_internal_macros.svh" 20 | `include "tvip_axi_configuration.svh" 21 | `include "tvip_axi_status.svh" 22 | `include "tvip_axi_memory.svh" 23 | `include "tvip_axi_item.svh" 24 | `include "tvip_axi_payload_store.svh" 25 | `include "tvip_axi_component_base.svh" 26 | `include "tvip_axi_monitor_base.svh" 27 | `include "tvip_axi_sequencer_base.svh" 28 | `include "tvip_axi_driver_base.svh" 29 | `include "tvip_axi_agent_base.svh" 30 | `include "tvip_axi_sequence_base.svh" 31 | `include "tvip_axi_master_monitor.svh" 32 | `include "tvip_axi_master_driver.svh" 33 | `include "tvip_axi_master_sequencer.svh" 34 | `include "tvip_axi_master_agent.svh" 35 | `include "tvip_axi_master_sequence_base.svh" 36 | `include "tvip_axi_master_access_sequence.svh" 37 | `include "tvip_axi_master_write_sequence.svh" 38 | `include "tvip_axi_master_read_sequence.svh" 39 | `include "tvip_axi_slave_monitor.svh" 40 | `include "tvip_axi_slave_data_monitor.svh" 41 | `include "tvip_axi_slave_driver.svh" 42 | `include "tvip_axi_slave_sequencer.svh" 43 | `include "tvip_axi_slave_agent.svh" 44 | `include "tvip_axi_slave_sequence_base.svh" 45 | `include "tvip_axi_slave_default_sequence.svh" 46 | `include "tvip_axi_ral_adapter.svh" 47 | `include "tvip_axi_ral_predictor.svh" 48 | `include "tvip_axi_undef_internal_macros.svh" 49 | endpackage 50 | `endif 51 | -------------------------------------------------------------------------------- /src/tvip_axi_slave_sequencer.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SLAVE_SEQUENCER_SVH 2 | `define TVIP_AXI_SLAVE_SEQUENCER_SVH 3 | typedef tue_sequencer #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .REQ (tvip_axi_slave_item ) 7 | ) tvip_axi_slave_sequencer_base; 8 | 9 | class tvip_axi_slave_sequencer extends tvip_axi_sequencer_base #( 10 | .BASE (tvip_axi_slave_sequencer_base ) 11 | ); 12 | uvm_analysis_imp #( 13 | tvip_axi_item, tvip_axi_slave_sequencer 14 | ) request_export; 15 | 16 | protected tvip_axi_item_waiter write_request_waiter; 17 | protected tvip_axi_item_waiter read_request_waiter; 18 | protected tvip_axi_item_waiter request_waiter[tvip_axi_access_type]; 19 | 20 | function void build_phase(uvm_phase phase); 21 | super.build_phase(phase); 22 | 23 | request_export = new("request_export", this); 24 | 25 | write_request_waiter = new("write_request_waiter", this); 26 | write_request_waiter.set_context(configuration, status); 27 | 28 | read_request_waiter = new("read_request_waiter" , this); 29 | read_request_waiter.set_context(configuration, status); 30 | 31 | request_waiter[TVIP_AXI_WRITE_ACCESS] = write_request_waiter; 32 | request_waiter[TVIP_AXI_READ_ACCESS ] = read_request_waiter; 33 | endfunction 34 | 35 | virtual function void write(tvip_axi_item request); 36 | request_waiter[request.access_type].write(request); 37 | endfunction 38 | 39 | virtual task get_request( 40 | input tvip_axi_access_type access_type, 41 | ref tvip_axi_slave_item request 42 | ); 43 | tvip_axi_item item; 44 | request_waiter[access_type].get_item(item); 45 | void'($cast(request, item)); 46 | endtask 47 | 48 | `tue_component_default_constructor(tvip_axi_slave_sequencer) 49 | `uvm_component_utils(tvip_axi_slave_sequencer) 50 | endclass 51 | `endif 52 | -------------------------------------------------------------------------------- /src/tvip_axi_driver_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_DRIVER_BASE_SVH 2 | `define TVIP_AXI_DRIVER_BASE_SVH 3 | class tvip_axi_sub_driver_base #( 4 | type ITEM = uvm_sequence_item 5 | ) extends tue_component #( 6 | .CONFIGURATION (tvip_axi_configuration ), 7 | .STATUS (tvip_axi_status ) 8 | ); 9 | protected uvm_driver #(ITEM) root_driver; 10 | 11 | function new(string name = "tvip_axi_sub_driver_base", uvm_component parent = null); 12 | super.new(name, parent); 13 | void'($cast(root_driver, parent)); 14 | endfunction 15 | 16 | virtual task put_request(tvip_axi_item request); 17 | endtask 18 | 19 | virtual task put_response(tvip_axi_item response); 20 | ITEM item; 21 | void'($cast(item, response)); 22 | root_driver.seq_item_port.put(item); 23 | endtask 24 | endclass 25 | 26 | class tvip_axi_driver_base #( 27 | type ITEM = uvm_sequence_item, 28 | type WRITE_DRIVER = uvm_component, 29 | type READ_DRIVER = uvm_component 30 | ) extends tue_driver #( 31 | .CONFIGURATION (tvip_axi_configuration ), 32 | .STATUS (tvip_axi_status ), 33 | .REQ (ITEM ) 34 | ); 35 | protected WRITE_DRIVER write_driver; 36 | protected READ_DRIVER read_driver; 37 | 38 | function void build_phase(uvm_phase phase); 39 | super.build_phase(phase); 40 | 41 | write_driver = WRITE_DRIVER::type_id::create("write_driver", this); 42 | write_driver.set_context(configuration, status); 43 | 44 | read_driver = READ_DRIVER::type_id::create("read_driver", this); 45 | read_driver.set_context(configuration, status); 46 | endfunction 47 | 48 | task run_phase(uvm_phase phase); 49 | ITEM item; 50 | forever begin 51 | seq_item_port.get(item); 52 | if (item.is_write()) begin 53 | write_driver.put_request(item); 54 | end 55 | else begin 56 | read_driver.put_request(item); 57 | end 58 | end 59 | endtask 60 | 61 | `tue_component_default_constructor(tvip_axi_driver_base) 62 | endclass 63 | `endif 64 | -------------------------------------------------------------------------------- /src/tvip_axi_ral_adapter.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_RAL_ADAPTER_SVH 2 | `define TVIP_AXI_RAL_ADAPTER_SVH 3 | class tvip_axi_ral_adapter extends uvm_reg_adapter; 4 | function new(string name = "tvip_axi_ral_adapter"); 5 | super.new(name); 6 | supports_byte_enable = 1; 7 | provides_responses = 1; 8 | endfunction 9 | 10 | virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); 11 | tvip_axi_master_item axi_item; 12 | 13 | axi_item = tvip_axi_master_item::type_id::create("axi_item"); 14 | axi_item.id = get_axi_id(); 15 | axi_item.address = rw.addr; 16 | axi_item.protection = '0; 17 | axi_item.need_response = 1; 18 | if (rw.kind == UVM_WRITE) begin 19 | axi_item.access_type = TVIP_AXI_WRITE_ACCESS; 20 | axi_item.data = new[1]; 21 | axi_item.data[0] = rw.data; 22 | axi_item.strobe = new[1]; 23 | axi_item.strobe[0] = rw.byte_en; 24 | end 25 | else begin 26 | axi_item.access_type = TVIP_AXI_READ_ACCESS; 27 | end 28 | 29 | return axi_item; 30 | endfunction 31 | 32 | virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); 33 | tvip_axi_item axi_item; 34 | $cast(axi_item, bus_item); 35 | rw.addr = axi_item.address; 36 | rw.kind = (axi_item.is_write()) ? UVM_WRITE : UVM_READ; 37 | rw.data = axi_item.data[0]; 38 | rw.byte_en = (axi_item.is_write()) ? axi_item.strobe[0] : rw.byte_en; 39 | rw.status = get_status(axi_item); 40 | endfunction 41 | 42 | protected virtual function tvip_axi_id get_axi_id(); 43 | return 0; 44 | endfunction 45 | 46 | protected function uvm_status_e get_status(tvip_axi_item axi_item); 47 | if ($isunknown(axi_item.response[0]) || $isunknown(axi_item.data[0])) begin 48 | return UVM_HAS_X; 49 | end 50 | case (axi_item.response[0]) 51 | TVIP_AXI_OKAY: return UVM_IS_OK; 52 | TVIP_AXI_EXOKAY: return UVM_IS_OK; 53 | TVIP_AXI_SLAVE_ERROR: return UVM_NOT_OK; 54 | TVIP_AXI_DECODE_ERROR: return UVM_NOT_OK; 55 | endcase 56 | endfunction 57 | 58 | `uvm_object_utils(tvip_axi_ral_adapter) 59 | endclass 60 | `endif 61 | -------------------------------------------------------------------------------- /sample/env/tvip_axi_sample_test.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SAMPLE_TEST_SVH 2 | `define TVIP_AXI_SAMPLE_TEST_SVH 3 | class tvip_axi_sample_test extends tue_test #( 4 | .CONFIGURATION (tvip_axi_sample_configuration) 5 | ); 6 | tvip_axi_master_agent master_agent; 7 | tvip_axi_master_sequencer master_sequencer; 8 | tvip_axi_slave_agent slave_agent; 9 | tvip_axi_slave_sequencer slave_sequencer; 10 | 11 | function new(string name = "tvip_axi_sample_test", uvm_component parent = null); 12 | super.new(name, parent); 13 | `ifndef XILINX_SIMULATOR 14 | `uvm_info("SRANDOM", $sformatf("Initial random seed: %0d", $get_initial_random_seed), UVM_NONE) 15 | `endif 16 | endfunction 17 | 18 | function void create_configuration(); 19 | super.create_configuration(); 20 | void'(uvm_config_db #(tvip_axi_vif)::get(null, "", "vif[0]", configuration.axi_cfg[0].vif)); 21 | void'(uvm_config_db #(tvip_axi_vif)::get(null, "", "vif[1]", configuration.axi_cfg[1].vif)); 22 | if (configuration.randomize()) begin 23 | `uvm_info(get_name(), $sformatf("configuration...\n%s", configuration.sprint()), UVM_NONE) 24 | end 25 | else begin 26 | `uvm_fatal(get_name(), "randomization failed !!") 27 | end 28 | endfunction 29 | 30 | function void build_phase(uvm_phase phase); 31 | super.build_phase(phase); 32 | 33 | master_agent = tvip_axi_master_agent::type_id::create("master_agent", this); 34 | master_agent.set_configuration(configuration.axi_cfg[0]); 35 | 36 | slave_agent = tvip_axi_slave_agent::type_id::create("slave_agent", this); 37 | slave_agent.set_configuration(configuration.axi_cfg[1]); 38 | endfunction 39 | 40 | function void connect_phase(uvm_phase phase); 41 | super.connect_phase(phase); 42 | master_sequencer = master_agent.sequencer; 43 | slave_sequencer = slave_agent.sequencer; 44 | endfunction 45 | 46 | function void end_of_elaboration_phase(uvm_phase phase); 47 | super.end_of_elaboration_phase(phase); 48 | uvm_config_db #(uvm_object_wrapper)::set( 49 | master_sequencer, "main_phase", "default_sequence", tvip_axi_sample_write_read_sequence::type_id::get() 50 | ); 51 | uvm_config_db #(uvm_object_wrapper)::set( 52 | slave_sequencer, "run_phase", "default_sequence", tvip_axi_slave_default_sequence::type_id::get() 53 | ); 54 | endfunction 55 | 56 | `uvm_component_utils(tvip_axi_sample_test) 57 | endclass 58 | `endif 59 | -------------------------------------------------------------------------------- /src/tvip_axi_agent_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_AGENT_BASE_SVH 2 | `define TVIP_AXI_AGENT_BASE_SVH 3 | virtual class tvip_axi_agent_base #( 4 | type WRITE_MONITOR = uvm_monitor, 5 | type READ_MONITOR = uvm_monitor, 6 | type SEQUENCER = uvm_sequencer, 7 | type DRIVER = uvm_driver 8 | ) extends tue_agent #( 9 | .CONFIGURATION (tvip_axi_configuration ), 10 | .STATUS (tvip_axi_status ) 11 | ); 12 | uvm_analysis_port #(tvip_axi_item) item_port; 13 | SEQUENCER sequencer; 14 | 15 | protected WRITE_MONITOR write_monitor; 16 | protected READ_MONITOR read_monitor; 17 | protected DRIVER driver; 18 | 19 | function void build_phase(uvm_phase phase); 20 | super.build_phase(phase); 21 | 22 | item_port = new("item_port", this); 23 | if (is_active_agent()) begin 24 | sequencer = SEQUENCER::type_id::create("sequencer", this); 25 | sequencer.set_context(configuration, status); 26 | end 27 | 28 | write_monitor = WRITE_MONITOR::type_id::create("write_monitor", this); 29 | write_monitor.set_context(configuration, status); 30 | 31 | read_monitor = READ_MONITOR::type_id::create("read_monitor", this); 32 | read_monitor.set_context(configuration, status); 33 | 34 | if (is_active_agent()) begin 35 | driver = DRIVER::type_id::create("driver", this); 36 | driver.set_context(configuration, status); 37 | end 38 | endfunction 39 | 40 | function void connect_phase(uvm_phase phase); 41 | super.connect_phase(phase); 42 | 43 | write_monitor.item_port.connect(item_port); 44 | if (is_active_agent()) begin 45 | write_monitor.address_item_port.connect(sequencer.address_item_export); 46 | write_monitor.request_item_port.connect(sequencer.request_item_export); 47 | write_monitor.response_item_port.connect(sequencer.response_item_export); 48 | write_monitor.item_port.connect(sequencer.item_export); 49 | end 50 | 51 | read_monitor.item_port.connect(item_port); 52 | if (is_active_agent()) begin 53 | read_monitor.address_item_port.connect(sequencer.address_item_export); 54 | read_monitor.request_item_port.connect(sequencer.request_item_export); 55 | read_monitor.response_item_port.connect(sequencer.response_item_export); 56 | read_monitor.item_port.connect(sequencer.item_export); 57 | end 58 | 59 | if (is_active_agent()) begin 60 | driver.seq_item_port.connect(sequencer.seq_item_export); 61 | end 62 | endfunction 63 | 64 | `tue_component_default_constructor(tvip_axi_agent_base) 65 | endclass 66 | `endif 67 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | [![ko-fi](https://www.ko-fi.com/img/githubbutton_sm.svg)](https://ko-fi.com/A0A231E3I) 2 | [![Gitter](https://badges.gitter.im/taichi-ishitani/tvip-axi.svg)](https://gitter.im/taichi-ishitani/tvip-axi?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge) 3 | 4 | # TVIP-AXI 5 | 6 | TVIP-AXI is an UVM package of AMBA AXI4 VIP. 7 | 8 | ## Feature 9 | 10 | * Master and slave agent 11 | * Support AXI4 and AXI4-Lite protocols 12 | * Highly configurable 13 | * address width 14 | * data width 15 | * ID width 16 | * etc. 17 | * Support delayed write data and response 18 | * Support gapped write data and read response 19 | * Response ordering 20 | * in-order response 21 | * out of order response 22 | * Support read interleave 23 | * Include UVM RAL adapter and predictor 24 | 25 | ## Sample Environment 26 | 27 | The sample environment is included. The execution procedure is as following. 28 | 29 | ### Preparation 30 | 31 | Before executing the sample environment, you need to clone submodules. Hit command below on the root directory of TVIP-AXI. 32 | 33 | $ ./setup_submodules.sh 34 | 35 | ### Execution 36 | 37 | To execute the sample environment, hit command below on the `sample/work` directory. 38 | 39 | $ make 40 | 41 | Then, all sample test cases will be executed by using Synopsys VCS simulator. 42 | If you want to use Cadence Xcelium simulator, hit command below. 43 | 44 | $ make SIMULATOR=xcelium 45 | 46 | If you want to execute a test case individually, hit command below. 47 | 48 | $ make NAME_OF_TEST_CASE 49 | 50 | Followings are available test cases: 51 | 52 | * default 53 | * request_delay 54 | * sample for delayed request 55 | * sample for gapped write data 56 | * response_delay 57 | * sample for delayed response 58 | * sample for gapped read response 59 | * out_of_order_response 60 | * sample for out of order response 61 | * read_interleave 62 | * sample for read interleave 63 | 64 | ### Supported Simulator 65 | 66 | Supported simulators are below: 67 | 68 | * Synopsys VCS 69 | * Cadence Xcelium 70 | * `-warn_multiple_driver` option may be needed to avoid `E,ICDCBA` error 71 | * Metrics DSim Simulator 72 | 73 | ## Contact 74 | 75 | If you have any questions, problems, feedbacks, etc., you can post them on following ways: 76 | 77 | * [GitHub Issue Tracker](https://github.com/taichi-ishitani/tvip-axi/issues) 78 | * [Chat room](https://gitter.im/taichi-ishitani/tvip-axi) 79 | 80 | ## Copyright 81 | 82 | Copyright (C) 2018 Taichi Ishitani. 83 | TVIP-AXI is licensed under the Apache-2.0 license. See [LICENSE](LICENSE) for further details. 84 | -------------------------------------------------------------------------------- /src/tvip_axi_sequencer_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SEQUENCER_BASE_SVH 2 | `define TVIP_AXI_SEQUENCER_BASE_SVH 3 | class tvip_axi_item_waiter extends tue_item_waiter #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ), 6 | .ITEM (tvip_axi_item ), 7 | .KEY (tvip_axi_id ) 8 | ); 9 | protected function bit match_key(KEY key, ITEM item); 10 | return item.id == key; 11 | endfunction 12 | `tue_component_default_constructor(tvip_axi_item_waiter) 13 | endclass 14 | 15 | class tvip_axi_sequencer_base #( 16 | type BASE = uvm_sequencer 17 | ) extends BASE; 18 | uvm_analysis_export #(tvip_axi_item) address_item_export; 19 | uvm_analysis_export #(tvip_axi_item) request_item_export; 20 | uvm_analysis_export #(tvip_axi_item) response_item_export; 21 | uvm_analysis_export #(tvip_axi_item) item_export; 22 | 23 | protected tvip_axi_item_waiter address_item_waiter; 24 | protected tvip_axi_item_waiter request_item_waiter; 25 | protected tvip_axi_item_waiter response_item_waiter; 26 | protected tvip_axi_item_waiter item_waiter; 27 | 28 | function void build_phase(uvm_phase phase); 29 | super.build_phase(phase); 30 | 31 | address_item_export = new("address_item_export", this); 32 | address_item_waiter = new("address_item_waiter", this); 33 | address_item_waiter.set_context(configuration, status); 34 | 35 | request_item_export = new("request_item_export", this); 36 | request_item_waiter = new("request_item_waiter", this); 37 | request_item_waiter.set_context(configuration, status); 38 | 39 | response_item_export = new("response_item_export", this); 40 | response_item_waiter = new("response_item_waiter", this); 41 | response_item_waiter.set_context(configuration, status); 42 | 43 | item_export = new("item_export", this); 44 | item_waiter = new("item_waiter", this); 45 | item_waiter.set_context(configuration, status); 46 | endfunction 47 | 48 | function void connect_phase(uvm_phase phase); 49 | super.connect_phase(phase); 50 | address_item_export.connect(address_item_waiter.analysis_export); 51 | request_item_export.connect(request_item_waiter.analysis_export); 52 | response_item_export.connect(response_item_waiter.analysis_export); 53 | item_export.connect(item_waiter.analysis_export); 54 | endfunction 55 | 56 | `define tvip_axi_define_item_getter_tasks(ITEM_TYPE) \ 57 | virtual task get_``ITEM_TYPE``(ref tvip_axi_item item); \ 58 | ``ITEM_TYPE``_waiter.get_item(item); \ 59 | endtask \ 60 | virtual task get_``ITEM_TYPE``_by_id(ref tvip_axi_item item, input tvip_axi_id id); \ 61 | ``ITEM_TYPE``_waiter.get_item_by_key(id, item); \ 62 | endtask 63 | 64 | `tvip_axi_define_item_getter_tasks(address_item ) 65 | `tvip_axi_define_item_getter_tasks(request_item ) 66 | `tvip_axi_define_item_getter_tasks(response_item) 67 | `tvip_axi_define_item_getter_tasks(item ) 68 | 69 | `undef tvip_axi_define_item_getter_tasks 70 | 71 | `tue_component_default_constructor(pzvip_ocp_sequencer_base) 72 | endclass 73 | `endif 74 | -------------------------------------------------------------------------------- /src/tvip_axi_slave_default_sequence.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SLAVE_DEFAULT_SEQUENCE_SVH 2 | `define TVIP_AXI_SLAVE_DEFAULT_SEQUENCE_SVH 3 | class tvip_axi_slave_default_sequence extends tvip_axi_slave_sequence_base; 4 | task body(); 5 | fork 6 | process_response_request(TVIP_AXI_WRITE_ACCESS); 7 | process_response_request(TVIP_AXI_READ_ACCESS); 8 | join 9 | endtask 10 | 11 | protected task process_response_request(tvip_axi_access_type access_type); 12 | forever begin 13 | tvip_axi_slave_item item; 14 | get_request(access_type, item); 15 | randomize_response(access_type, item); 16 | execute_response(item); 17 | end 18 | endtask 19 | 20 | protected virtual function void randomize_response( 21 | tvip_axi_access_type access_type, 22 | tvip_axi_slave_item item 23 | ); 24 | int response_size; 25 | 26 | if (!item.randomize()) begin 27 | `uvm_fatal("RNDFLD", "Randomization failed") 28 | end 29 | 30 | overwrite_delay(item.address_ready_delay, get_address_ready_delay(item)); 31 | overwrite_delay(item.start_delay, get_response_start_delay(item)); 32 | 33 | response_size = (item.is_read()) ? item.burst_length : 1; 34 | for (int i = 0;i < response_size;++i) begin 35 | overwrite_delay(item.response_delay[i], get_response_delay(item, i)); 36 | if (item.is_write()) begin 37 | overwrite_delay(item.write_data_ready_delay[i], get_write_data_ready_delay(item, i)); 38 | end 39 | 40 | if (get_response_existence(item, i)) begin 41 | item.response[i] = get_response_status(item, i); 42 | end 43 | if (item.is_read() && get_read_data_existence(item, i)) begin 44 | item.data[i] = get_read_data(item, i); 45 | end 46 | end 47 | endfunction 48 | 49 | protected virtual task execute_response(tvip_axi_slave_item item); 50 | fork 51 | automatic tvip_axi_slave_item __item = item; 52 | `uvm_send(__item); 53 | join_none 54 | endtask 55 | 56 | protected virtual function int get_address_ready_delay(tvip_axi_slave_item item); 57 | return -1; 58 | endfunction 59 | 60 | protected virtual function int get_write_data_ready_delay(tvip_axi_slave_item item, int index); 61 | return -1; 62 | endfunction 63 | 64 | protected virtual function int get_response_start_delay(tvip_axi_slave_item item); 65 | return -1; 66 | endfunction 67 | 68 | protected virtual function int get_response_delay(tvip_axi_slave_item item, int index); 69 | return -1; 70 | endfunction 71 | 72 | protected virtual function tvip_axi_response get_response_status(tvip_axi_slave_item item, int index); 73 | return TVIP_AXI_OKAY; 74 | endfunction 75 | 76 | protected virtual function bit get_response_existence(tvip_axi_slave_item item, int index); 77 | return 0; 78 | endfunction 79 | 80 | protected virtual function tvip_axi_data get_read_data(tvip_axi_slave_item item, int index); 81 | return status.memory.get(item.burst_size, item.address, index); 82 | endfunction 83 | 84 | protected virtual function bit get_read_data_existence(tvip_axi_slave_item item, int index); 85 | return status.memory.exists(item.burst_size, item.address, index); 86 | endfunction 87 | 88 | protected function void overwrite_delay( 89 | ref int delay, 90 | input int new_delay 91 | ); 92 | if (new_delay >= 0) begin 93 | delay = new_delay; 94 | end 95 | endfunction 96 | 97 | `tue_object_default_constructor(tvip_axi_slave_default_sequence) 98 | `uvm_object_utils(tvip_axi_slave_default_sequence) 99 | endclass 100 | `endif 101 | -------------------------------------------------------------------------------- /src/tvip_axi_if.sv: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_IF_SV 2 | `define TVIP_AXI_IF_SV 3 | interface tvip_axi_if ( 4 | input var aclk, 5 | input var areset_n 6 | ); 7 | import tvip_axi_types_pkg::*; 8 | 9 | // Write Address Channel 10 | logic awvalid; 11 | logic awready; 12 | tvip_axi_id awid; 13 | tvip_axi_address awaddr; 14 | tvip_axi_burst_length awlen; 15 | tvip_axi_burst_size awsize; 16 | tvip_axi_burst_type awburst; 17 | tvip_axi_write_cache awcache; 18 | tvip_axi_protection awprot; 19 | tvip_axi_qos awqos; 20 | // Write Data Channel 21 | logic wvalid; 22 | logic wready; 23 | tvip_axi_data wdata; 24 | tvip_axi_strobe wstrb; 25 | logic wlast; 26 | // Write Response Channel 27 | logic bvalid; 28 | logic bready; 29 | tvip_axi_id bid; 30 | tvip_axi_response bresp; 31 | // Read Address Channel 32 | logic arvalid; 33 | logic arready; 34 | tvip_axi_id arid; 35 | tvip_axi_address araddr; 36 | tvip_axi_burst_length arlen; 37 | tvip_axi_burst_size arsize; 38 | tvip_axi_burst_type arburst; 39 | tvip_axi_read_cache arcache; 40 | tvip_axi_protection arprot; 41 | tvip_axi_qos arqos; 42 | // Read Data Channel 43 | logic rvalid; 44 | logic rready; 45 | tvip_axi_id rid; 46 | tvip_axi_data rdata; 47 | tvip_axi_response rresp; 48 | logic rlast; 49 | 50 | clocking master_cb @(posedge aclk, negedge areset_n); 51 | output awvalid; 52 | input awready; 53 | output awid; 54 | output awaddr; 55 | output awlen; 56 | output awsize; 57 | output awburst; 58 | output awprot; 59 | output awcache; 60 | output awqos; 61 | output wvalid; 62 | input wready; 63 | output wdata; 64 | output wstrb; 65 | output wlast; 66 | input bvalid; 67 | output bready; 68 | input bid; 69 | input bresp; 70 | output arvalid; 71 | input arready; 72 | output arid; 73 | output araddr; 74 | output arlen; 75 | output arsize; 76 | output arburst; 77 | output arcache; 78 | output arprot; 79 | output arqos; 80 | input rvalid; 81 | output rready; 82 | input rid; 83 | input rdata; 84 | input rresp; 85 | input rlast; 86 | endclocking 87 | 88 | clocking slave_cb @(posedge aclk, negedge areset_n); 89 | input awvalid; 90 | output awready; 91 | input awid; 92 | input awaddr; 93 | input awlen; 94 | input awsize; 95 | input awburst; 96 | input awcache; 97 | input awprot; 98 | input awqos; 99 | input wvalid; 100 | output wready; 101 | input wdata; 102 | input wstrb; 103 | input wlast; 104 | output bvalid; 105 | input bready; 106 | output bid; 107 | output bresp; 108 | input arvalid; 109 | output arready; 110 | input arid; 111 | input araddr; 112 | input arlen; 113 | input arsize; 114 | input arburst; 115 | input arcache; 116 | input arprot; 117 | input arqos; 118 | output rvalid; 119 | input rready; 120 | output rid; 121 | output rdata; 122 | output rresp; 123 | output rlast; 124 | endclocking 125 | 126 | clocking monitor_cb @(posedge aclk); 127 | input areset_n; 128 | input awvalid; 129 | input awready; 130 | input awid; 131 | input awaddr; 132 | input awlen; 133 | input awsize; 134 | input awburst; 135 | input awcache; 136 | input awprot; 137 | input awqos; 138 | input wvalid; 139 | input wready; 140 | input wdata; 141 | input wstrb; 142 | input wlast; 143 | input bvalid; 144 | input bready; 145 | input bid; 146 | input bresp; 147 | input arvalid; 148 | input arready; 149 | input arid; 150 | input araddr; 151 | input arlen; 152 | input arsize; 153 | input arburst; 154 | input arcache; 155 | input arprot; 156 | input arqos; 157 | input rvalid; 158 | input rready; 159 | input rid; 160 | input rdata; 161 | input rresp; 162 | input rlast; 163 | endclocking 164 | 165 | event at_master_cb_edge; 166 | event at_slave_cb_edge; 167 | event at_monitor_cb_edge; 168 | 169 | always @(master_cb) begin 170 | ->at_master_cb_edge; 171 | end 172 | 173 | always @(slave_cb) begin 174 | ->at_slave_cb_edge; 175 | end 176 | 177 | always @(monitor_cb) begin 178 | ->at_monitor_cb_edge; 179 | end 180 | endinterface 181 | `endif 182 | -------------------------------------------------------------------------------- /sample/env/tvip_axi_sample_write_read_sequence.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SAMPLE_WRITE_READ_SEQUENCE_SVH 2 | `define TVIP_AXI_SAMPLE_WRITE_READ_SEQUENCE_SVH 3 | class tvip_axi_sample_write_read_sequence extends tvip_axi_master_sequence_base; 4 | tvip_axi_address address_mask[int]; 5 | 6 | function new(string name = "tvip_axi_sample_write_read_sequence"); 7 | super.new(name); 8 | set_automatic_phase_objection(1); 9 | endfunction 10 | 11 | task body(); 12 | do_basic_write_read_access(); 13 | 14 | for (int i = 0;i < 20;++i) begin 15 | fork 16 | automatic int ii = i; 17 | do_write_read_access_by_sequence(ii); 18 | join_none 19 | end 20 | wait fork; 21 | 22 | for (int i = 0;i < 20;++i) begin 23 | fork 24 | automatic int ii = i; 25 | do_write_read_access_by_item(ii); 26 | join_none 27 | end 28 | wait fork; 29 | endtask 30 | 31 | task do_basic_write_read_access(); 32 | tvip_axi_master_item write_items[$]; 33 | tvip_axi_master_item read_items[$]; 34 | 35 | for (int i = 0;i < 20;++i) begin 36 | tvip_axi_master_item write_item; 37 | `tue_do_with(write_item, { 38 | access_type == TVIP_AXI_WRITE_ACCESS; 39 | address >= (64'h0001_0000_0000_0000 * (i + 0) - 0); 40 | address <= (64'h0001_0000_0000_0000 * (i + 1) - 1); 41 | (address + burst_size * burst_length) <= (64'h0001_0000_0000_0000 * (i + 1) - 1); 42 | }) 43 | write_items.push_back(write_item); 44 | end 45 | write_items[$].wait_for_done(); 46 | 47 | foreach (write_items[i]) begin 48 | tvip_axi_master_item read_item; 49 | `tue_do_with(read_item, { 50 | access_type == TVIP_AXI_READ_ACCESS; 51 | address == write_items[i].address; 52 | burst_size == write_items[i].burst_size; 53 | burst_length == write_items[i].burst_length; 54 | }) 55 | read_items.push_back(read_item); 56 | end 57 | 58 | foreach (write_items[i]) begin 59 | tvip_axi_item write_item; 60 | tvip_axi_item read_item; 61 | tvip_axi_item response_item; 62 | 63 | write_item = write_items[i]; 64 | read_item = read_items[i]; 65 | wait_for_response(read_item, response_item); 66 | 67 | for (int j = 0;j < write_item.burst_length;++j) begin 68 | if (!compare_data( 69 | j, 70 | write_item.address, write_item.burst_size, 71 | write_item.strobe, write_item.data, 72 | response_item.data 73 | )) begin 74 | `uvm_error("CMPDATA", "write and read data are mismatched !!") 75 | end 76 | end 77 | end 78 | endtask 79 | 80 | task do_write_read_access_by_sequence(int index); 81 | tvip_axi_master_write_sequence write_sequence; 82 | tvip_axi_master_read_sequence read_sequence; 83 | 84 | `tue_do_with(write_sequence, { 85 | address >= (64'h0001_0000_0000_0000 * (index + 0) - 0); 86 | address <= (64'h0001_0000_0000_0000 * (index + 1) - 1); 87 | (address + burst_size * burst_length) <= (64'h0001_0000_0000_0000 * (index + 1) - 1); 88 | }) 89 | `tue_do_with(read_sequence, { 90 | address == write_sequence.address; 91 | burst_size == write_sequence.burst_size; 92 | burst_length >= write_sequence.burst_length; 93 | }) 94 | 95 | for (int i = 0;i < write_sequence.burst_length;++i) begin 96 | if (!compare_data( 97 | i, 98 | write_sequence.address, write_sequence.burst_size, 99 | write_sequence.strobe, write_sequence.data, 100 | read_sequence.data 101 | )) begin 102 | `uvm_error("CMPDATA", "write and read data are mismatched !!") 103 | end 104 | end 105 | endtask 106 | 107 | task do_write_read_access_by_item(int index); 108 | tvip_axi_master_item write_item; 109 | tvip_axi_item write_response; 110 | tvip_axi_master_item read_item; 111 | tvip_axi_item read_response; 112 | 113 | `tue_do_with(write_item, { 114 | need_response == (index < 10); 115 | access_type == TVIP_AXI_WRITE_ACCESS; 116 | address >= (64'h0001_0000_0000_0000 * (index + 0) - 0); 117 | address <= (64'h0001_0000_0000_0000 * (index + 1) - 1); 118 | (address + burst_size * burst_length) <= (64'h0001_0000_0000_0000 * (index + 1) - 1); 119 | }) 120 | wait_for_response(write_item, write_response); 121 | 122 | `tue_do_with(read_item, { 123 | need_response == write_item.need_response; 124 | access_type == TVIP_AXI_READ_ACCESS; 125 | address == write_item.address; 126 | burst_size == write_item.burst_size; 127 | burst_length == write_item.burst_length; 128 | }) 129 | wait_for_response(read_item, read_response); 130 | 131 | for (int i = 0;i < write_response.burst_length;++i) begin 132 | if (!compare_data( 133 | i, 134 | write_response.address, write_response.burst_size, 135 | write_response.strobe, write_response.data, 136 | read_response.data 137 | )) begin 138 | `uvm_error("CMPDATA", "write and read data are mismatched !!") 139 | end 140 | end 141 | endtask 142 | 143 | task wait_for_response( 144 | input tvip_axi_item request, 145 | output tvip_axi_item response 146 | ); 147 | if (request.need_response) begin 148 | int id = request.get_transaction_id(); 149 | get_response(response, id); 150 | end 151 | else begin 152 | request.wait_for_done(); 153 | response = request; 154 | end 155 | endtask 156 | 157 | function bit compare_data( 158 | input int index, 159 | input tvip_axi_address address, 160 | input int burst_size, 161 | ref tvip_axi_strobe strobe[], 162 | ref tvip_axi_data write_data[], 163 | ref tvip_axi_data read_data[] 164 | ); 165 | int byte_width; 166 | int byte_offset; 167 | 168 | byte_width = configuration.data_width / 8; 169 | byte_offset = ((address & get_address_mask(burst_size)) + (burst_size * index)) % byte_width; 170 | for (int i = 0;i < burst_size;++i) begin 171 | int byte_index = byte_offset + i; 172 | byte write_byte; 173 | byte read_byte; 174 | 175 | if (!strobe[index][byte_index]) begin 176 | continue; 177 | end 178 | 179 | write_byte = write_data[index][8*byte_index+:8]; 180 | read_byte = read_data[index][8*byte_index+:8]; 181 | if (write_byte != read_byte) begin 182 | return 0; 183 | end 184 | end 185 | 186 | return 1; 187 | endfunction 188 | 189 | function tvip_axi_address get_address_mask(int burst_size); 190 | if (!address_mask.exists(burst_size)) begin 191 | tvip_axi_address mask; 192 | mask = '1; 193 | mask = (mask >> $clog2(burst_size)) << $clog2(burst_size); 194 | address_mask[burst_size] = mask; 195 | end 196 | return address_mask[burst_size]; 197 | endfunction 198 | 199 | `uvm_object_utils(tvip_axi_sample_write_read_sequence) 200 | endclass 201 | `endif 202 | -------------------------------------------------------------------------------- /sample/env/tvip_axi_sample_configuration.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SAMPLE_CONFIGURATION_SVH 2 | `define TVIP_AXI_SAMPLE_CONFIGURATION_SVH 3 | class tvip_axi_sample_configuration extends tue_configuration; 4 | bit enable_request_start_delay; 5 | bit enable_write_data_delay; 6 | bit enable_response_start_delay; 7 | bit enable_response_delay; 8 | bit enable_ready_delay; 9 | bit enable_out_of_order_response; 10 | bit enable_read_interleave; 11 | rand tvip_axi_configuration axi_cfg[2]; 12 | 13 | constraint c_axi_basic { 14 | foreach (axi_cfg[i]) { 15 | axi_cfg[i].id_width == 8; 16 | axi_cfg[i].address_width == 64; 17 | axi_cfg[i].max_burst_length == 256; 18 | axi_cfg[i].data_width == 64; 19 | axi_cfg[i].qos_range[0] != -1; 20 | axi_cfg[i].qos_range[1] != -1; 21 | } 22 | } 23 | 24 | constraint c_request_start_delay { 25 | if (enable_request_start_delay) { 26 | axi_cfg[0].request_start_delay.min_delay == 0; 27 | axi_cfg[0].request_start_delay.max_delay == 10; 28 | axi_cfg[0].request_start_delay.weight_zero_delay == 6; 29 | axi_cfg[0].request_start_delay.weight_short_delay == 3; 30 | axi_cfg[0].request_start_delay.weight_long_delay == 1; 31 | } 32 | } 33 | 34 | constraint c_write_data_delay { 35 | if (enable_write_data_delay) { 36 | axi_cfg[0].write_data_delay.min_delay == 0; 37 | axi_cfg[0].write_data_delay.max_delay == 10; 38 | axi_cfg[0].write_data_delay.weight_zero_delay == 6; 39 | axi_cfg[0].write_data_delay.weight_short_delay == 3; 40 | axi_cfg[0].write_data_delay.weight_long_delay == 1; 41 | } 42 | } 43 | 44 | constraint c_response_weight { 45 | axi_cfg[1].response_weight_okay == 6; 46 | axi_cfg[1].response_weight_exokay == 2; 47 | axi_cfg[1].response_weight_slave_error == 1; 48 | axi_cfg[1].response_weight_decode_error == 1; 49 | } 50 | 51 | constraint c_response_start_delay { 52 | if (enable_response_start_delay) { 53 | axi_cfg[1].response_start_delay.min_delay == 0; 54 | axi_cfg[1].response_start_delay.max_delay == 10; 55 | axi_cfg[1].response_start_delay.weight_zero_delay == 6; 56 | axi_cfg[1].response_start_delay.weight_short_delay == 3; 57 | axi_cfg[1].response_start_delay.weight_long_delay == 1; 58 | } 59 | } 60 | 61 | constraint c_response_delay { 62 | if (enable_response_delay) { 63 | axi_cfg[1].response_delay.min_delay == 0; 64 | axi_cfg[1].response_delay.max_delay == 10; 65 | axi_cfg[1].response_delay.weight_zero_delay == 6; 66 | axi_cfg[1].response_delay.weight_short_delay == 3; 67 | axi_cfg[1].response_delay.weight_long_delay == 1; 68 | } 69 | } 70 | 71 | constraint c_ready_delay { 72 | if (enable_ready_delay) { 73 | axi_cfg[1].awready_delay.min_delay == 0; 74 | axi_cfg[1].awready_delay.max_delay == 10; 75 | axi_cfg[1].awready_delay.weight_zero_delay == 6; 76 | axi_cfg[1].awready_delay.weight_short_delay == 3; 77 | axi_cfg[1].awready_delay.weight_long_delay == 1; 78 | 79 | axi_cfg[1].wready_delay.min_delay == 0; 80 | axi_cfg[1].wready_delay.max_delay == 10; 81 | axi_cfg[1].wready_delay.weight_zero_delay == 6; 82 | axi_cfg[1].wready_delay.weight_short_delay == 3; 83 | axi_cfg[1].wready_delay.weight_long_delay == 1; 84 | 85 | axi_cfg[0].bready_delay.min_delay == 0; 86 | axi_cfg[0].bready_delay.max_delay == 10; 87 | axi_cfg[0].bready_delay.weight_zero_delay == 6; 88 | axi_cfg[0].bready_delay.weight_short_delay == 3; 89 | axi_cfg[0].bready_delay.weight_long_delay == 1; 90 | 91 | axi_cfg[1].arready_delay.min_delay == 0; 92 | axi_cfg[1].arready_delay.max_delay == 10; 93 | axi_cfg[1].arready_delay.weight_zero_delay == 6; 94 | axi_cfg[1].arready_delay.weight_short_delay == 3; 95 | axi_cfg[1].arready_delay.weight_long_delay == 1; 96 | 97 | axi_cfg[0].rready_delay.min_delay == 0; 98 | axi_cfg[0].rready_delay.max_delay == 10; 99 | axi_cfg[0].rready_delay.weight_zero_delay == 6; 100 | axi_cfg[0].rready_delay.weight_short_delay == 3; 101 | axi_cfg[0].rready_delay.weight_long_delay == 1; 102 | } 103 | } 104 | 105 | constraint c_response_ordering { 106 | if (enable_out_of_order_response || enable_read_interleave) { 107 | axi_cfg[1].response_ordering == TVIP_AXI_OUT_OF_ORDER; 108 | axi_cfg[1].outstanding_responses inside {[2:5]}; 109 | } 110 | else { 111 | axi_cfg[1].response_ordering == TVIP_AXI_IN_ORDER; 112 | } 113 | } 114 | 115 | constraint c_read_interleave { 116 | if (enable_read_interleave) { 117 | axi_cfg[1].enable_response_interleaving == 1; 118 | } 119 | else { 120 | axi_cfg[1].enable_response_interleaving == 0; 121 | } 122 | } 123 | 124 | function new(string name = "tvip_axi_sample_configuration"); 125 | super.new(name); 126 | axi_cfg[0] = tvip_axi_configuration::type_id::create("axi_cfg[0]"); 127 | axi_cfg[1] = tvip_axi_configuration::type_id::create("axi_cfg[1]"); 128 | endfunction 129 | 130 | function void pre_randomize(); 131 | uvm_cmdline_processor clp; 132 | string values[$]; 133 | clp = uvm_cmdline_processor::get_inst(); 134 | if (clp.get_arg_matches("+ENABLE_REQUEST_START_DELAY", values)) begin 135 | enable_request_start_delay = 1; 136 | end 137 | if (clp.get_arg_matches("+ENABLE_WRITE_DATA_DELAY", values)) begin 138 | enable_write_data_delay = 1; 139 | end 140 | if (clp.get_arg_matches("+ENABLE_RESPONSE_START_DELAY", values)) begin 141 | enable_response_start_delay = 1; 142 | end 143 | if (clp.get_arg_matches("+ENABLE_RESPONSE_DELAY", values)) begin 144 | enable_response_delay = 1; 145 | end 146 | if (clp.get_arg_matches("+ENABLE_READY_DELAY", values)) begin 147 | enable_ready_delay = 1; 148 | end 149 | if (clp.get_arg_matches("+ENABLE_OUT_OF_ORDER_RESPONSE", values)) begin 150 | enable_out_of_order_response = 1; 151 | end 152 | if (clp.get_arg_matches("+ENABLE_READ_INTERLEAVE", values)) begin 153 | enable_read_interleave = 1; 154 | end 155 | endfunction 156 | 157 | `uvm_object_utils_begin(tvip_axi_sample_configuration) 158 | `uvm_field_int(enable_write_data_delay, UVM_DEFAULT | UVM_BIN) 159 | `uvm_field_int(enable_response_start_delay, UVM_DEFAULT | UVM_BIN) 160 | `uvm_field_int(enable_response_delay, UVM_DEFAULT | UVM_BIN) 161 | `uvm_field_int(enable_ready_delay, UVM_DEFAULT | UVM_BIN) 162 | `uvm_field_int(enable_out_of_order_response, UVM_DEFAULT | UVM_BIN) 163 | `uvm_field_int(enable_read_interleave, UVM_DEFAULT | UVM_BIN) 164 | `uvm_field_sarray_object(axi_cfg, UVM_DEFAULT) 165 | `uvm_object_utils_end 166 | endclass 167 | `endif 168 | -------------------------------------------------------------------------------- /src/tvip_axi_types_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_TYPES_PKG_SV 2 | `define TVIP_AXI_TYPES_PKG_SV 3 | package tvip_axi_types_pkg; 4 | `include "tvip_axi_defines.svh" 5 | 6 | typedef logic [`TVIP_AXI_MAX_ID_WIDTH-1:0] tvip_axi_id; 7 | typedef logic [`TVIP_AXI_MAX_ADDRESS_WIDTH-1:0] tvip_axi_address; 8 | typedef logic [7:0] tvip_axi_burst_length; 9 | typedef logic [3:0] tvip_axi_cache; 10 | typedef logic [3:0] tvip_axi_qos; 11 | typedef logic [`TVIP_AXI_MAX_DATA_WIDTH-1:0] tvip_axi_data; 12 | typedef logic [`TVIP_AXI_MAX_DATA_WIDTH/8-1:0] tvip_axi_strobe; 13 | 14 | typedef enum logic [2:0] { 15 | TVIP_AXI_BURST_SIZE_1_BYTE = 'b000, 16 | TVIP_AXI_BURST_SIZE_2_BYTES = 'b001, 17 | TVIP_AXI_BURST_SIZE_4_BYTES = 'b010, 18 | TVIP_AXI_BURST_SIZE_8_BYTES = 'b011, 19 | TVIP_AXI_BURST_SIZE_16_BYTES = 'b100, 20 | TVIP_AXI_BURST_SIZE_32_BYTES = 'b101, 21 | TVIP_AXI_BURST_SIZE_64_BYTES = 'b110, 22 | TVIP_AXI_BURST_SIZE_128_BYTES = 'b111 23 | } tvip_axi_burst_size; 24 | 25 | typedef enum logic [1:0] { 26 | TVIP_AXI_FIXED_BURST = 'b00, 27 | TVIP_AXI_INCREMENTING_BURST = 'b01, 28 | TVIP_AXI_WRAPPING_BURST = 'b10 29 | } tvip_axi_burst_type; 30 | 31 | typedef enum { 32 | TVIP_AXI_DEVICE_NON_BUFFERABLE, 33 | TVIP_AXI_DEVICE_BUFFERABLE, 34 | TVIP_AXI_NORMAL_NON_CACHEABLE_NON_BUFFERABLE, 35 | TVIP_AXI_NORMAL_NON_CACHEABLE_BUFFERABLE, 36 | TVIP_AXI_WRITE_THROUGH_NO_ALLOCATE, 37 | TVIP_AXI_WRITE_THROUGH_READ_ALLOCATE, 38 | TVIP_AXI_WRITE_THROUGH_WRITE_ALLOCATE, 39 | TVIP_AXI_WRITE_THROUGH_READ_WRITE_ALLOCATE, 40 | TVIP_AXI_WRITE_BACK_NO_ALLOCATE, 41 | TVIP_AXI_WRITE_BACK_READ_ALLOCATE, 42 | TVIP_AXI_WRITE_BACK_WRITE_ALLOCATE, 43 | TVIP_AXI_WRITE_BACK_READ_WRITE_ALLOCATE 44 | } tvip_axi_memory_type; 45 | 46 | typedef struct packed { 47 | logic allocate; 48 | logic other_allocate; 49 | logic modifiable; 50 | logic bufferable; 51 | } tvip_axi_write_cache; 52 | 53 | typedef struct packed { 54 | logic other_allocate; 55 | logic allocate; 56 | logic modifiable; 57 | logic bufferable; 58 | } tvip_axi_read_cache; 59 | 60 | typedef struct packed { 61 | logic instruction_access; 62 | logic non_secure_access; 63 | logic privileged_access; 64 | } tvip_axi_protection; 65 | 66 | typedef enum logic [1:0] { 67 | TVIP_AXI_OKAY = 'b00, 68 | TVIP_AXI_EXOKAY = 'b01, 69 | TVIP_AXI_SLAVE_ERROR = 'b10, 70 | TVIP_AXI_DECODE_ERROR = 'b11 71 | } tvip_axi_response; 72 | 73 | typedef enum { 74 | TVIP_AXI4, 75 | TVIP_AXI4LITE 76 | } tvip_axi_protocol; 77 | 78 | typedef enum { 79 | TVIP_AXI_IN_ORDER, 80 | TVIP_AXI_OUT_OF_ORDER 81 | } tvip_axi_ordering_mode; 82 | 83 | typedef enum { 84 | TVIP_AXI_WRITE_ACCESS, 85 | TVIP_AXI_READ_ACCESS 86 | } tvip_axi_access_type; 87 | 88 | function automatic tvip_axi_burst_length pack_burst_length(int burst_length); 89 | if (burst_length inside {[1:256]}) begin 90 | return tvip_axi_burst_length'(burst_length - 1); 91 | end 92 | else begin 93 | ; // TBD 94 | end 95 | endfunction 96 | 97 | function automatic int unpack_burst_length(tvip_axi_burst_length burst_length); 98 | return int'(burst_length) + 1; 99 | endfunction 100 | 101 | function automatic tvip_axi_burst_size pack_burst_size(int burst_size); 102 | case (burst_size) 103 | 1: return TVIP_AXI_BURST_SIZE_1_BYTE; 104 | 2: return TVIP_AXI_BURST_SIZE_2_BYTES; 105 | 4: return TVIP_AXI_BURST_SIZE_4_BYTES; 106 | 8: return TVIP_AXI_BURST_SIZE_8_BYTES; 107 | 16: return TVIP_AXI_BURST_SIZE_16_BYTES; 108 | 32: return TVIP_AXI_BURST_SIZE_32_BYTES; 109 | 64: return TVIP_AXI_BURST_SIZE_64_BYTES; 110 | 128: return TVIP_AXI_BURST_SIZE_128_BYTES; 111 | default: ; // TBD 112 | endcase 113 | endfunction 114 | 115 | function automatic int unpack_burst_size(tvip_axi_burst_size burst_size); 116 | case (burst_size) 117 | TVIP_AXI_BURST_SIZE_1_BYTE: return 1; 118 | TVIP_AXI_BURST_SIZE_2_BYTES: return 2; 119 | TVIP_AXI_BURST_SIZE_4_BYTES: return 4; 120 | TVIP_AXI_BURST_SIZE_8_BYTES: return 8; 121 | TVIP_AXI_BURST_SIZE_16_BYTES: return 16; 122 | TVIP_AXI_BURST_SIZE_32_BYTES: return 32; 123 | TVIP_AXI_BURST_SIZE_64_BYTES: return 64; 124 | TVIP_AXI_BURST_SIZE_128_BYTES: return 128; 125 | endcase 126 | endfunction 127 | 128 | function automatic tvip_axi_cache encode_memory_type(tvip_axi_memory_type memory_type, bit read_access); 129 | case (memory_type) 130 | TVIP_AXI_DEVICE_NON_BUFFERABLE: return 4'b0000; 131 | TVIP_AXI_DEVICE_BUFFERABLE: return 4'b0001; 132 | TVIP_AXI_NORMAL_NON_CACHEABLE_NON_BUFFERABLE: return 4'b0010; 133 | TVIP_AXI_NORMAL_NON_CACHEABLE_BUFFERABLE: return 4'b0011; 134 | TVIP_AXI_WRITE_THROUGH_NO_ALLOCATE: return (read_access) ? 4'b1010 : 4'b0110; 135 | TVIP_AXI_WRITE_THROUGH_READ_ALLOCATE: return (read_access) ? 4'b1110 : 4'b0110; 136 | TVIP_AXI_WRITE_THROUGH_WRITE_ALLOCATE: return (read_access) ? 4'b1010 : 4'b1110; 137 | TVIP_AXI_WRITE_THROUGH_READ_WRITE_ALLOCATE: return 4'b1110; 138 | TVIP_AXI_WRITE_BACK_NO_ALLOCATE: return (read_access) ? 4'b1011 : 4'b1110; 139 | TVIP_AXI_WRITE_BACK_READ_ALLOCATE: return (read_access) ? 4'b1111 : 4'b0111; 140 | TVIP_AXI_WRITE_BACK_WRITE_ALLOCATE: return (read_access) ? 4'b1011 : 4'b1111; 141 | TVIP_AXI_WRITE_BACK_READ_WRITE_ALLOCATE: return 4'b1111; 142 | endcase 143 | endfunction 144 | 145 | function automatic tvip_axi_memory_type decode_memory_type(tvip_axi_cache cache, bit read_access); 146 | if (read_access) begin 147 | case (cache) 148 | 4'b0000: return TVIP_AXI_DEVICE_NON_BUFFERABLE; 149 | 4'b0001: return TVIP_AXI_DEVICE_BUFFERABLE; 150 | 4'b0010: return TVIP_AXI_NORMAL_NON_CACHEABLE_NON_BUFFERABLE; 151 | 4'b0011: return TVIP_AXI_NORMAL_NON_CACHEABLE_BUFFERABLE; 152 | 4'b1010: return TVIP_AXI_WRITE_THROUGH_NO_ALLOCATE; 153 | 4'b1110: return TVIP_AXI_WRITE_THROUGH_READ_ALLOCATE; 154 | 4'b1010: return TVIP_AXI_WRITE_THROUGH_WRITE_ALLOCATE; 155 | 4'b1110: return TVIP_AXI_WRITE_THROUGH_READ_WRITE_ALLOCATE; 156 | 4'b1011: return TVIP_AXI_WRITE_BACK_NO_ALLOCATE; 157 | 4'b1111: return TVIP_AXI_WRITE_BACK_READ_ALLOCATE; 158 | 4'b1011: return TVIP_AXI_WRITE_BACK_WRITE_ALLOCATE; 159 | 4'b1111: return TVIP_AXI_WRITE_BACK_READ_WRITE_ALLOCATE; 160 | endcase 161 | end 162 | else begin 163 | case (cache) 164 | 4'b0000: return TVIP_AXI_DEVICE_NON_BUFFERABLE; 165 | 4'b0001: return TVIP_AXI_DEVICE_BUFFERABLE; 166 | 4'b0010: return TVIP_AXI_NORMAL_NON_CACHEABLE_NON_BUFFERABLE; 167 | 4'b0011: return TVIP_AXI_NORMAL_NON_CACHEABLE_BUFFERABLE; 168 | 4'b0110: return TVIP_AXI_WRITE_THROUGH_NO_ALLOCATE; 169 | 4'b0110: return TVIP_AXI_WRITE_THROUGH_READ_ALLOCATE; 170 | 4'b1110: return TVIP_AXI_WRITE_THROUGH_WRITE_ALLOCATE; 171 | 4'b1110: return TVIP_AXI_WRITE_THROUGH_READ_WRITE_ALLOCATE; 172 | 4'b0111: return TVIP_AXI_WRITE_BACK_NO_ALLOCATE; 173 | 4'b0111: return TVIP_AXI_WRITE_BACK_READ_ALLOCATE; 174 | 4'b1111: return TVIP_AXI_WRITE_BACK_WRITE_ALLOCATE; 175 | 4'b1111: return TVIP_AXI_WRITE_BACK_READ_WRITE_ALLOCATE; 176 | endcase 177 | end 178 | endfunction 179 | 180 | function automatic bit compare_memory_type(tvip_axi_memory_type lhs, tvip_axi_memory_type rhs, bit read_access); 181 | bit [3:0] lhs_value; 182 | bit [3:0] rhs_value; 183 | lhs_value = encode_memory_type(lhs, read_access); 184 | rhs_value = encode_memory_type(rhs, read_access); 185 | return lhs_value == rhs_value; 186 | endfunction 187 | endpackage 188 | `endif 189 | -------------------------------------------------------------------------------- /src/tvip_axi_master_access_sequence.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_ACCESS_SEQUENCE_SVH 2 | `define TVIP_AXI_MASTER_ACCESS_SEQUENCE_SVH 3 | class tvip_axi_master_access_sequence extends tvip_axi_master_sequence_base; 4 | rand tvip_axi_access_type access_type; 5 | rand tvip_axi_id id; 6 | rand tvip_axi_address address; 7 | rand int burst_length; 8 | rand int burst_size; 9 | rand tvip_axi_burst_type burst_type; 10 | rand tvip_axi_memory_type memory_type; 11 | rand tvip_axi_protection protection; 12 | rand tvip_axi_qos qos; 13 | rand tvip_axi_data data[]; 14 | rand tvip_axi_strobe strobe[]; 15 | tvip_axi_response response[]; 16 | rand int start_delay; 17 | rand int write_data_delay[]; 18 | rand int response_ready_delay[]; 19 | uvm_event address_done_event; 20 | uvm_event write_data_done_event; 21 | uvm_event response_done_event; 22 | protected tvip_axi_master_item request_item; 23 | protected tvip_axi_master_item response_item; 24 | 25 | constraint c_valid_id { 26 | (id >> this.configuration.id_width) == 0; 27 | } 28 | 29 | constraint c_valid_address { 30 | (address >> this.configuration.address_width) == 0; 31 | } 32 | 33 | constraint c_valid_burst_length { 34 | if (this.configuration.protocol == TVIP_AXI4) { 35 | burst_length inside {[1:this.configuration.max_burst_length]}; 36 | } 37 | else { 38 | burst_length == 1; 39 | } 40 | } 41 | 42 | constraint c_valid_burst_size { 43 | if (this.configuration.protocol == TVIP_AXI4) { 44 | burst_size inside {1, 2, 4, 8, 16, 32, 64, 128}; 45 | (8 * burst_size) <= this.configuration.data_width; 46 | } 47 | else { 48 | (8 * burst_size) == this.configuration.data_width; 49 | } 50 | } 51 | 52 | constraint c_4kb_boundary { 53 | ( 54 | (address & `tvip_axi_4kb_boundary_mask(burst_size)) + 55 | (burst_length * burst_size) 56 | ) <= 4096; 57 | } 58 | 59 | constraint c_default_burst_type { 60 | burst_type == TVIP_AXI_INCREMENTING_BURST; 61 | } 62 | 63 | constraint c_valid_memory_type { 64 | if (this.configuration.protocol == TVIP_AXI4LITE) { 65 | memory_type == TVIP_AXI_DEVICE_NON_BUFFERABLE; 66 | } 67 | } 68 | 69 | constraint c_valid_qos { 70 | qos inside {[ 71 | this.configuration.qos_range[0]: 72 | this.configuration.qos_range[1] 73 | ]}; 74 | } 75 | 76 | constraint c_valid_data { 77 | solve access_type before data; 78 | solve burst_length before data; 79 | (access_type == TVIP_AXI_WRITE_ACCESS) -> data.size() == burst_length; 80 | (access_type == TVIP_AXI_READ_ACCESS ) -> data.size() == 0; 81 | foreach (data[i]) { 82 | (data[i] >> this.configuration.data_width) == 0; 83 | } 84 | } 85 | 86 | constraint c_valid_strobe { 87 | solve access_type before strobe; 88 | solve burst_length before strobe; 89 | (access_type == TVIP_AXI_WRITE_ACCESS) -> strobe.size() == burst_length; 90 | (access_type == TVIP_AXI_READ_ACCESS ) -> strobe.size() == 0; 91 | foreach (strobe[i]) { 92 | (strobe[i] >> this.configuration.strobe_width) == 0; 93 | } 94 | } 95 | 96 | constraint c_start_delay { 97 | `tvip_delay_constraint(start_delay, this.configuration.request_start_delay) 98 | } 99 | 100 | constraint c_write_data_delay { 101 | solve access_type, burst_length before write_data_delay; 102 | 103 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 104 | write_data_delay.size() == burst_length; 105 | } 106 | else { 107 | write_data_delay.size() == 0; 108 | } 109 | 110 | foreach (write_data_delay[i]) { 111 | `tvip_delay_constraint(write_data_delay[i], this.configuration.write_data_delay) 112 | } 113 | } 114 | 115 | constraint c_response_ready { 116 | solve access_type, burst_length before response_ready_delay; 117 | 118 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 119 | response_ready_delay.size() == 1; 120 | } 121 | else { 122 | response_ready_delay.size() == burst_length; 123 | } 124 | 125 | foreach (response_ready_delay[i]) { 126 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 127 | `tvip_delay_constraint(response_ready_delay[i], this.configuration.bready_delay) 128 | } 129 | else { 130 | `tvip_delay_constraint(response_ready_delay[i], this.configuration.rready_delay) 131 | } 132 | } 133 | } 134 | 135 | function new(string name = "tvip_axi_master_access_sequence"); 136 | super.new(name); 137 | request_item = tvip_axi_master_item::type_id::create("request_item"); 138 | address_done_event = request_item.get_event("address_end"); 139 | write_data_done_event = request_item.get_event("write_data_end"); 140 | response_done_event = request_item.get_event("response_end"); 141 | endfunction 142 | 143 | function bit do_compare(uvm_object rhs, uvm_comparer comparer); 144 | tvip_axi_master_access_sequence rhs_sequence; 145 | $cast(rhs_sequence, rhs); 146 | return 147 | super.do_compare(rhs, comparer) && 148 | compare_memory_type(memory_type, rhs_sequence.memory_type, access_type == TVIP_AXI_READ_ACCESS); 149 | endfunction 150 | 151 | task body(); 152 | transmit_request(); 153 | wait_for_response(); 154 | endtask 155 | 156 | local task transmit_request(); 157 | copy_request_info(); 158 | `uvm_send(request_item) 159 | endtask 160 | 161 | local function void copy_request_info(); 162 | request_item.access_type = access_type; 163 | request_item.id = id; 164 | request_item.address = address; 165 | request_item.burst_length = burst_length; 166 | request_item.burst_size = burst_size; 167 | request_item.burst_type = burst_type; 168 | request_item.memory_type = memory_type; 169 | request_item.protection = protection; 170 | request_item.qos = qos; 171 | request_item.start_delay = start_delay; 172 | request_item.response_ready_delay = new[response_ready_delay.size()](response_ready_delay); 173 | request_item.need_response = 1; 174 | if (request_item.is_write()) begin 175 | request_item.data = new[data.size()](data); 176 | request_item.strobe = new[strobe.size()](strobe); 177 | request_item.write_data_delay = new[write_data_delay.size()](write_data_delay); 178 | end 179 | endfunction 180 | 181 | local task wait_for_response(); 182 | int id = request_item.get_transaction_id(); 183 | get_response(response_item, id); 184 | copy_response_info(); 185 | endtask 186 | 187 | local function void copy_response_info(); 188 | response = new[response_item.response.size()](response_item.response); 189 | if (response_item.is_read()) begin 190 | data = new[response_item.data.size()](response_item.data); 191 | end 192 | endfunction 193 | 194 | `uvm_object_utils_begin(tvip_axi_master_access_sequence) 195 | `uvm_field_enum(tvip_axi_access_type, access_type, UVM_DEFAULT) 196 | `uvm_field_int(id, UVM_DEFAULT | UVM_HEX) 197 | `uvm_field_int(address, UVM_DEFAULT | UVM_HEX) 198 | `uvm_field_int(burst_length, UVM_DEFAULT | UVM_DEC) 199 | `uvm_field_int(burst_size, UVM_DEFAULT | UVM_DEC) 200 | `uvm_field_enum(tvip_axi_burst_type, burst_type, UVM_DEFAULT) 201 | `uvm_field_enum(tvip_axi_memory_type, memory_type, UVM_DEFAULT | UVM_NOCOMPARE) 202 | `uvm_field_int(protection, UVM_DEFAULT | UVM_BIN) 203 | `uvm_field_int(qos, UVM_DEFAULT | UVM_DEC) 204 | `uvm_field_array_int(data, UVM_DEFAULT | UVM_HEX) 205 | `uvm_field_array_int(strobe, UVM_DEFAULT | UVM_HEX) 206 | `uvm_field_array_enum(tvip_axi_response, response, UVM_DEFAULT) 207 | `uvm_field_int(start_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 208 | `uvm_field_array_int(write_data_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 209 | `uvm_field_array_int(response_ready_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 210 | `uvm_object_utils_end 211 | endclass 212 | `endif 213 | -------------------------------------------------------------------------------- /src/tvip_axi_configuration.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_CONFIGURATION_SVH 2 | `define TVIP_AXI_CONFIGURATION_SVH 3 | class tvip_axi_configuration extends tue_configuration; 4 | tvip_axi_vif vif; 5 | rand tvip_axi_protocol protocol; 6 | rand int id_width; 7 | rand int address_width; 8 | rand int max_burst_length; 9 | rand int data_width; 10 | rand int strobe_width; 11 | rand int qos_range[2]; 12 | rand tvip_axi_ordering_mode response_ordering; 13 | rand int outstanding_responses; 14 | rand bit enable_response_interleaving; 15 | rand int min_interleave_size; 16 | rand int max_interleave_size; 17 | rand int response_weight_okay; 18 | rand int response_weight_exokay; 19 | rand int response_weight_slave_error; 20 | rand int response_weight_decode_error; 21 | rand tvip_delay_configuration request_start_delay; 22 | rand tvip_delay_configuration write_data_delay; 23 | rand tvip_delay_configuration response_start_delay; 24 | rand tvip_delay_configuration response_delay; 25 | rand bit default_awready; 26 | rand tvip_delay_configuration awready_delay; 27 | rand bit default_wready; 28 | rand tvip_delay_configuration wready_delay; 29 | rand bit default_bready; 30 | rand tvip_delay_configuration bready_delay; 31 | rand bit default_arready; 32 | rand tvip_delay_configuration arready_delay; 33 | rand bit default_rready; 34 | rand tvip_delay_configuration rready_delay; 35 | rand bit reset_by_agent; 36 | 37 | constraint c_default_protocol { 38 | soft protocol == TVIP_AXI4; 39 | } 40 | 41 | constraint c_valid_id_width { 42 | id_width inside {[0:`TVIP_AXI_MAX_ID_WIDTH]}; 43 | } 44 | 45 | constraint c_default_id_width { 46 | solve protocol before id_width; 47 | if (protocol == TVIP_AXI4LITE) { 48 | soft id_width == 0; 49 | } 50 | } 51 | 52 | constraint c_valid_address_width { 53 | address_width inside {[1:`TVIP_AXI_MAX_ADDRESS_WIDTH]}; 54 | } 55 | 56 | constraint c_valid_max_burst_length { 57 | solve protocol before max_burst_length; 58 | max_burst_length inside {[1:256]}; 59 | if (protocol == TVIP_AXI4LITE) { 60 | max_burst_length == 1; 61 | } 62 | } 63 | 64 | constraint c_valid_data_width { 65 | solve protocol before data_width; 66 | data_width inside { 67 | 8, 16, 32, 64, 128, 256, 512, 1024 68 | }; 69 | if (protocol == TVIP_AXI4LITE) { 70 | data_width inside {32, 64}; 71 | } 72 | } 73 | 74 | constraint c_valid_strobe_width { 75 | solve data_width before strobe_width; 76 | strobe_width == (data_width / 8); 77 | } 78 | 79 | constraint c_valid_qos_range { 80 | solve protocol before qos_range; 81 | if (protocol == TVIP_AXI4LITE) { 82 | qos_range[0] == 0; 83 | qos_range[1] == 0; 84 | } 85 | else { 86 | qos_range[0] <= qos_range[1]; 87 | foreach (qos_range[i]) { 88 | qos_range[i] inside {-1, [0:15]}; 89 | } 90 | } 91 | } 92 | 93 | constraint c_default_qos_range { 94 | foreach (qos_range[i]) { 95 | soft qos_range[i] == -1; 96 | } 97 | } 98 | 99 | constraint c_valid_response_ordering { 100 | solve protocol before response_ordering; 101 | if (protocol == TVIP_AXI4LITE) { 102 | response_ordering == TVIP_AXI_IN_ORDER; 103 | } 104 | } 105 | 106 | constraint c_default_response_ordering { 107 | soft response_ordering == TVIP_AXI_OUT_OF_ORDER; 108 | } 109 | 110 | constraint c_valid_outstanding_responses { 111 | outstanding_responses >= 0; 112 | } 113 | 114 | constraint c_default_outstanding_responses { 115 | soft outstanding_responses == 0; 116 | } 117 | 118 | constraint c_default_enable_response_interleaving { 119 | soft enable_response_interleaving == 0; 120 | } 121 | 122 | constraint c_valid_interleave_size { 123 | min_interleave_size >= 0; 124 | max_interleave_size >= 0; 125 | max_interleave_size >= min_interleave_size; 126 | } 127 | 128 | constraint c_default_interleave_size { 129 | soft min_interleave_size == 0; 130 | soft max_interleave_size == 0; 131 | } 132 | 133 | constraint c_valid_response_weight { 134 | response_weight_okay >= -1; 135 | response_weight_exokay >= -1; 136 | response_weight_slave_error >= -1; 137 | response_weight_decode_error >= -1; 138 | } 139 | 140 | constraint c_default_response_weight { 141 | soft response_weight_okay == -1; 142 | soft response_weight_exokay == -1; 143 | soft response_weight_slave_error == -1; 144 | soft response_weight_decode_error == -1; 145 | } 146 | 147 | constraint c_default_reset_by_agent { 148 | soft reset_by_agent == 1; 149 | } 150 | 151 | function new(string name = "tvip_axi_configuration"); 152 | super.new(name); 153 | request_start_delay = tvip_delay_configuration::type_id::create("request_start_delay"); 154 | write_data_delay = tvip_delay_configuration::type_id::create("write_data_delay"); 155 | response_start_delay = tvip_delay_configuration::type_id::create("response_start_delay"); 156 | response_delay = tvip_delay_configuration::type_id::create("response_delay"); 157 | awready_delay = tvip_delay_configuration::type_id::create("awready_delay"); 158 | wready_delay = tvip_delay_configuration::type_id::create("wready_delay"); 159 | bready_delay = tvip_delay_configuration::type_id::create("bready_delay"); 160 | arready_delay = tvip_delay_configuration::type_id::create("arready_delay"); 161 | rready_delay = tvip_delay_configuration::type_id::create("rready_delay"); 162 | endfunction 163 | 164 | function void post_randomize(); 165 | super.post_randomize(); 166 | qos_range[0] = (qos_range[0] >= 0) ? qos_range[0] : 0; 167 | qos_range[1] = (qos_range[1] >= 0) ? qos_range[1] : 0; 168 | response_weight_okay = (response_weight_okay >= 0) ? response_weight_okay : 1; 169 | response_weight_exokay = (response_weight_exokay >= 0) ? response_weight_exokay : 0; 170 | response_weight_slave_error = (response_weight_slave_error >= 0) ? response_weight_slave_error : 0; 171 | response_weight_decode_error = (response_weight_decode_error >= 0) ? response_weight_decode_error : 0; 172 | endfunction 173 | 174 | `uvm_object_utils_begin(tvip_axi_configuration) 175 | `uvm_field_enum(tvip_axi_protocol, protocol, UVM_DEFAULT) 176 | `uvm_field_int(id_width, UVM_DEFAULT | UVM_DEC) 177 | `uvm_field_int(address_width, UVM_DEFAULT | UVM_DEC) 178 | `uvm_field_int(max_burst_length, UVM_DEFAULT | UVM_DEC) 179 | `uvm_field_int(data_width, UVM_DEFAULT | UVM_DEC) 180 | `uvm_field_int(strobe_width, UVM_DEFAULT | UVM_DEC) 181 | `uvm_field_sarray_int(qos_range, UVM_DEFAULT | UVM_DEC) 182 | `uvm_field_enum(tvip_axi_ordering_mode, response_ordering, UVM_DEFAULT) 183 | `uvm_field_int(outstanding_responses, UVM_DEFAULT | UVM_DEC) 184 | `uvm_field_int(enable_response_interleaving, UVM_DEFAULT | UVM_BIN) 185 | `uvm_field_int(min_interleave_size, UVM_DEFAULT | UVM_DEC) 186 | `uvm_field_int(max_interleave_size, UVM_DEFAULT | UVM_DEC) 187 | `uvm_field_int(response_weight_okay, UVM_DEFAULT | UVM_DEC) 188 | `uvm_field_int(response_weight_exokay, UVM_DEFAULT | UVM_DEC) 189 | `uvm_field_int(response_weight_slave_error, UVM_DEFAULT | UVM_DEC) 190 | `uvm_field_int(response_weight_decode_error, UVM_DEFAULT | UVM_DEC) 191 | `uvm_field_object(request_start_delay, UVM_DEFAULT) 192 | `uvm_field_object(write_data_delay, UVM_DEFAULT) 193 | `uvm_field_object(response_start_delay, UVM_DEFAULT) 194 | `uvm_field_object(response_delay, UVM_DEFAULT) 195 | `uvm_field_int(default_awready, UVM_DEFAULT | UVM_BIN) 196 | `uvm_field_object(awready_delay, UVM_DEFAULT) 197 | `uvm_field_int(default_wready, UVM_DEFAULT | UVM_BIN) 198 | `uvm_field_object(wready_delay, UVM_DEFAULT) 199 | `uvm_field_int(default_bready, UVM_DEFAULT | UVM_BIN) 200 | `uvm_field_object(bready_delay, UVM_DEFAULT) 201 | `uvm_field_int(default_arready, UVM_DEFAULT | UVM_BIN) 202 | `uvm_field_object(arready_delay, UVM_DEFAULT) 203 | `uvm_field_int(default_rready, UVM_DEFAULT | UVM_BIN) 204 | `uvm_field_object(rready_delay, UVM_DEFAULT) 205 | `uvm_field_int(reset_by_agent, UVM_DEFAULT | UVM_BIN) 206 | `uvm_object_utils_end 207 | endclass 208 | `endif 209 | -------------------------------------------------------------------------------- /sample/env/tvip_axi_sample_delay.sv: -------------------------------------------------------------------------------- 1 | module tvip_axi_sample_delay_unit #( 2 | parameter int DELAY = 0, 3 | parameter type DATA = logic 4 | )( 5 | input var i_clk, 6 | input var i_rst_n, 7 | input var i_enable, 8 | input var i_valid, 9 | output var o_ready, 10 | input var DATA i_d, 11 | output var o_valid, 12 | input var i_ready, 13 | output var DATA o_d 14 | ); 15 | logic valid[DELAY+1]; 16 | logic ready[DELAY+1]; 17 | DATA data[DELAY+1]; 18 | 19 | always_comb begin 20 | valid[0] = (i_enable) ? i_valid : '0; 21 | o_ready = (i_enable) ? ready[0] : i_ready; 22 | data[0] = (i_enable) ? i_d : '0; 23 | end 24 | 25 | always_comb begin 26 | o_valid = (i_enable) ? valid[DELAY] : i_valid; 27 | ready[DELAY] = (i_enable) ? i_ready : '0; 28 | o_d = (i_enable) ? data[DELAY] : i_d; 29 | end 30 | 31 | for (genvar i = 0;i < DELAY;++i) begin : g 32 | always_ff @(posedge i_clk, negedge i_rst_n) begin 33 | if (!i_rst_n) begin 34 | valid[i+1] <= '0; 35 | data[i+1] <= '0; 36 | end 37 | else if (ready[i]) begin 38 | valid[i+1] <= valid[i]; 39 | data[i+1] <= data[i]; 40 | end 41 | end 42 | 43 | always_comb begin 44 | ready[i] = ready[i+1] || (!valid[i+1]); 45 | end 46 | end 47 | endmodule 48 | 49 | module tvip_axi_sample_delay #( 50 | parameter int WRITE_ADDRESS_DELAY = 0, 51 | parameter int WRITE_DATA_DELAY = 0, 52 | parameter int WRITE_RESPONSE_DELAY = 0, 53 | parameter int READ_ADDRESS_DELAY = 0, 54 | parameter int READ_RESPONSE_DELAY = 0 55 | )( 56 | input var i_clk, 57 | input var i_rst_n, 58 | tvip_axi_if slave_if, 59 | tvip_axi_if master_if 60 | ); 61 | import tvip_axi_types_pkg::*; 62 | 63 | typedef struct packed { 64 | tvip_axi_id awid; 65 | tvip_axi_address awaddr; 66 | tvip_axi_burst_length awlen; 67 | tvip_axi_burst_size awsize; 68 | tvip_axi_burst_type awburst; 69 | tvip_axi_cache awcache; 70 | tvip_axi_protection awprot; 71 | tvip_axi_qos awqos; 72 | } tvip_axi_write_address; 73 | 74 | typedef struct packed { 75 | tvip_axi_data wdata; 76 | tvip_axi_strobe wstrb; 77 | bit wlast; 78 | } tvip_axi_write_data; 79 | 80 | typedef struct packed { 81 | tvip_axi_id bid; 82 | tvip_axi_response bresp; 83 | } tvip_axi_write_response; 84 | 85 | typedef struct packed { 86 | tvip_axi_id arid; 87 | tvip_axi_address araddr; 88 | tvip_axi_burst_length arlen; 89 | tvip_axi_burst_size arsize; 90 | tvip_axi_burst_type arburst; 91 | tvip_axi_cache arcache; 92 | tvip_axi_protection arprot; 93 | tvip_axi_qos arqos; 94 | } tvip_axi_read_address; 95 | 96 | typedef struct packed { 97 | tvip_axi_id rid; 98 | tvip_axi_data rdata; 99 | tvip_axi_response rresp; 100 | bit rlast; 101 | } tvip_axi_read_response; 102 | 103 | bit [4:0] enable_delay; 104 | initial begin 105 | enable_delay[0] = $test$plusargs("write_address_delay"); 106 | enable_delay[1] = $test$plusargs("write_data_delay"); 107 | enable_delay[2] = $test$plusargs("write_response_delay"); 108 | enable_delay[3] = $test$plusargs("read_address_delay"); 109 | enable_delay[4] = $test$plusargs("read_response_delay"); 110 | end 111 | 112 | logic awvalid[2]; 113 | logic awready[2]; 114 | tvip_axi_write_address write_address[2]; 115 | 116 | always @* begin 117 | slave_if.awready = awready[0]; 118 | awvalid[0] = slave_if.awvalid; 119 | write_address[0].awaddr = slave_if.awaddr; 120 | write_address[0].awid = slave_if.awid; 121 | write_address[0].awlen = slave_if.awlen; 122 | write_address[0].awsize = slave_if.awsize; 123 | write_address[0].awburst = slave_if.awburst; 124 | write_address[0].awcache = slave_if.awcache; 125 | write_address[0].awprot = slave_if.awprot; 126 | write_address[0].awqos = slave_if.awqos; 127 | end 128 | 129 | always @* begin 130 | awready[1] = master_if.awready; 131 | master_if.awvalid = awvalid[1]; 132 | master_if.awaddr = write_address[1].awaddr; 133 | master_if.awid = write_address[1].awid; 134 | master_if.awlen = write_address[1].awlen; 135 | master_if.awsize = write_address[1].awsize; 136 | master_if.awburst = write_address[1].awburst; 137 | master_if.awcache = write_address[1].awcache; 138 | master_if.awprot = write_address[1].awprot; 139 | master_if.awqos = write_address[1].awqos; 140 | end 141 | 142 | tvip_axi_sample_delay_unit #( 143 | .DELAY (WRITE_ADDRESS_DELAY ), 144 | .DATA (tvip_axi_write_address ) 145 | ) u_write_address_delay ( 146 | .i_clk (i_clk ), 147 | .i_rst_n (i_rst_n ), 148 | .i_enable (enable_delay[0] ), 149 | .i_valid (awvalid[0] ), 150 | .o_ready (awready[0] ), 151 | .i_d (write_address[0] ), 152 | .o_valid (awvalid[1] ), 153 | .i_ready (awready[1] ), 154 | .o_d (write_address[1] ) 155 | ); 156 | 157 | logic wvalid[2]; 158 | logic wready[2]; 159 | tvip_axi_write_data write_data[2]; 160 | 161 | always @* begin 162 | slave_if.wready = wready[0]; 163 | wvalid[0] = slave_if.wvalid; 164 | write_data[0].wdata = slave_if.wdata; 165 | write_data[0].wstrb = slave_if.wstrb; 166 | write_data[0].wlast = slave_if.wlast; 167 | end 168 | 169 | always @* begin 170 | wready[1] = master_if.wready; 171 | master_if.wvalid = wvalid[1]; 172 | master_if.wdata = write_data[1].wdata; 173 | master_if.wstrb = write_data[1].wstrb; 174 | master_if.wlast = write_data[1].wlast; 175 | end 176 | 177 | tvip_axi_sample_delay_unit #( 178 | .DELAY (WRITE_DATA_DELAY ), 179 | .DATA (tvip_axi_write_data ) 180 | ) u_write_data_delay ( 181 | .i_clk (i_clk ), 182 | .i_rst_n (i_rst_n ), 183 | .i_enable (enable_delay[1] ), 184 | .i_valid (wvalid[0] ), 185 | .o_ready (wready[0] ), 186 | .i_d (write_data[0] ), 187 | .o_valid (wvalid[1] ), 188 | .i_ready (wready[1] ), 189 | .o_d (write_data[1] ) 190 | ); 191 | 192 | logic bvalid[2]; 193 | logic bready[2]; 194 | tvip_axi_write_response write_response[2]; 195 | 196 | always @* begin 197 | master_if.bready = bready[0]; 198 | bvalid[0] = master_if.bvalid; 199 | write_response[0].bid = master_if.bid; 200 | write_response[0].bresp = master_if.bresp; 201 | end 202 | 203 | always @* begin 204 | bready[1] = slave_if.bready; 205 | slave_if.bvalid = bvalid[1]; 206 | slave_if.bid = write_response[1].bid; 207 | slave_if.bresp = write_response[1].bresp; 208 | end 209 | 210 | tvip_axi_sample_delay_unit #( 211 | .DELAY (WRITE_RESPONSE_DELAY ), 212 | .DATA (tvip_axi_write_response ) 213 | ) u_write_response_delay ( 214 | .i_clk (i_clk ), 215 | .i_rst_n (i_rst_n ), 216 | .i_enable (enable_delay[2] ), 217 | .i_valid (bvalid[0] ), 218 | .o_ready (bready[0] ), 219 | .i_d (write_response[0] ), 220 | .o_valid (bvalid[1] ), 221 | .i_ready (bready[1] ), 222 | .o_d (write_response[1] ) 223 | ); 224 | 225 | logic arvalid[2]; 226 | logic arready[2]; 227 | tvip_axi_read_address read_address[2]; 228 | 229 | always @* begin 230 | slave_if.arready = arready[0]; 231 | arvalid[0] = slave_if.arvalid; 232 | read_address[0].araddr = slave_if.araddr; 233 | read_address[0].arid = slave_if.arid; 234 | read_address[0].arlen = slave_if.arlen; 235 | read_address[0].arsize = slave_if.arsize; 236 | read_address[0].arburst = slave_if.arburst; 237 | read_address[0].arcache = slave_if.arcache; 238 | read_address[0].arprot = slave_if.arprot; 239 | read_address[0].arqos = slave_if.arqos; 240 | end 241 | 242 | always @* begin 243 | arready[1] = master_if.arready; 244 | master_if.arvalid = arvalid[1]; 245 | master_if.araddr = read_address[1].araddr; 246 | master_if.arid = read_address[1].arid; 247 | master_if.arlen = read_address[1].arlen; 248 | master_if.arsize = read_address[1].arsize; 249 | master_if.arburst = read_address[1].arburst; 250 | master_if.arcache = read_address[1].arcache; 251 | master_if.arprot = read_address[1].arprot; 252 | master_if.arqos = read_address[1].arqos; 253 | end 254 | 255 | tvip_axi_sample_delay_unit #( 256 | .DELAY (READ_ADDRESS_DELAY ), 257 | .DATA (tvip_axi_read_address ) 258 | ) u_read_address_delay ( 259 | .i_clk (i_clk ), 260 | .i_rst_n (i_rst_n ), 261 | .i_enable (enable_delay[3] ), 262 | .i_valid (arvalid[0] ), 263 | .o_ready (arready[0] ), 264 | .i_d (read_address[0] ), 265 | .o_valid (arvalid[1] ), 266 | .i_ready (arready[1] ), 267 | .o_d (read_address[1] ) 268 | ); 269 | 270 | logic rvalid[2]; 271 | logic rready[2]; 272 | tvip_axi_read_response read_response[2]; 273 | 274 | always @* begin 275 | master_if.rready = rready[0]; 276 | rvalid[0] = master_if.rvalid; 277 | read_response[0].rid = master_if.rid; 278 | read_response[0].rdata = master_if.rdata; 279 | read_response[0].rresp = master_if.rresp; 280 | read_response[0].rlast = master_if.rlast; 281 | end 282 | 283 | always @* begin 284 | rready[1] = slave_if.rready; 285 | slave_if.rvalid = rvalid[1]; 286 | slave_if.rid = read_response[1].rid; 287 | slave_if.rdata = read_response[1].rdata; 288 | slave_if.rresp = read_response[1].rresp; 289 | slave_if.rlast = read_response[1].rlast; 290 | end 291 | 292 | tvip_axi_sample_delay_unit #( 293 | .DELAY (READ_RESPONSE_DELAY ), 294 | .DATA (tvip_axi_read_response ) 295 | ) u_read_response_delay ( 296 | .i_clk (i_clk ), 297 | .i_rst_n (i_rst_n ), 298 | .i_enable (enable_delay[4] ), 299 | .i_valid (rvalid[0] ), 300 | .o_ready (rready[0] ), 301 | .i_d (read_response[0] ), 302 | .o_valid (rvalid[1] ), 303 | .i_ready (rready[1] ), 304 | .o_d (read_response[1] ) 305 | ); 306 | endmodule 307 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /src/tvip_axi_monitor_base.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MONITOR_BASE_SVH 2 | `define TVIP_AXI_MONITOR_BASE_SVH 3 | virtual class tvip_axi_monitor_base #( 4 | type BASE = uvm_monitor, 5 | type ITEM = uvm_sequence_item 6 | ) extends tvip_axi_component_base #(BASE); 7 | uvm_analysis_port #(tvip_axi_item) address_item_port; 8 | uvm_analysis_port #(tvip_axi_item) request_item_port; 9 | uvm_analysis_port #(tvip_axi_item) response_item_port; 10 | 11 | protected tvip_axi_payload_store write_data_stores[2][$]; 12 | protected tvip_axi_payload_store response_stores[tvip_axi_id][$]; 13 | 14 | function void build_phase(uvm_phase phase); 15 | super.build_phase(phase); 16 | address_item_port = new("address_item_port" , this); 17 | request_item_port = new("request_item_port" , this); 18 | response_item_port = new("response_item_port", this); 19 | endfunction 20 | 21 | task run_phase(uvm_phase phase); 22 | forever begin 23 | do_reset(); 24 | fork 25 | main(); 26 | @(negedge vif.areset_n); 27 | join_any 28 | disable fork; 29 | end 30 | endtask 31 | 32 | task end_address(tvip_axi_item item); 33 | super.end_address(item); 34 | address_item_port.write(item); 35 | if (item.request_ended()) begin 36 | request_item_port.write(item); 37 | end 38 | endtask 39 | 40 | task end_write_data(tvip_axi_item item); 41 | super.end_write_data(item); 42 | if (item.request_ended()) begin 43 | request_item_port.write(item); 44 | end 45 | endtask 46 | 47 | task end_response(tvip_axi_item item); 48 | super.end_response(item); 49 | write_item(item); 50 | response_item_port.write(item); 51 | endtask 52 | 53 | protected virtual task do_reset(); 54 | foreach (write_data_stores[i, j]) begin 55 | if (!write_data_stores[i][j].item.finished()) begin 56 | end_tr(write_data_stores[i][j].item); 57 | end 58 | end 59 | write_data_stores[0].delete(); 60 | write_data_stores[1].delete(); 61 | 62 | foreach (response_stores[i, j]) begin 63 | if (!response_stores[i][j].item.finished()) begin 64 | end_tr(response_stores[i][j].item); 65 | end 66 | end 67 | response_stores.delete(); 68 | 69 | @(posedge vif.monitor_cb.areset_n); 70 | endtask 71 | 72 | protected task main(); 73 | fork 74 | address_monitor_thread(); 75 | write_data_monitor_thread(); 76 | response_mointor_thread(); 77 | join 78 | endtask 79 | 80 | protected task address_monitor_thread(); 81 | tvip_axi_item item; 82 | 83 | forever begin 84 | wait_for_address_valid(); 85 | sample_address(item); 86 | 87 | wait_for_address_ready(); 88 | finish_address(item); 89 | end 90 | endtask 91 | 92 | protected task wait_for_address_valid(); 93 | if (is_write_component()) begin 94 | do begin 95 | @(vif.monitor_cb); 96 | end while (!vif.monitor_cb.awvalid); 97 | end 98 | else begin 99 | do begin 100 | @(vif.monitor_cb); 101 | end while (!vif.monitor_cb.arvalid); 102 | end 103 | endtask 104 | 105 | protected virtual task sample_address(ref tvip_axi_item item); 106 | tvip_axi_payload_store store; 107 | 108 | if (is_write_component() && (write_data_stores[1].size() > 0)) begin 109 | store = write_data_stores[1].pop_front(); 110 | item = store.item; 111 | end 112 | if (item == null) begin 113 | item = create_monitor_item(); 114 | store = tvip_axi_payload_store::create(item); 115 | if (is_write_component()) begin 116 | write_data_stores[0].push_back(store); 117 | end 118 | end 119 | 120 | item.access_type = (is_write_component()) ? TVIP_AXI_WRITE_ACCESS : TVIP_AXI_READ_ACCESS; 121 | item.id = get_address_id(); 122 | item.address = get_address(); 123 | item.burst_length = get_burst_length(); 124 | item.burst_size = get_burst_size(); 125 | item.burst_type = get_burst_type(); 126 | item.memory_type = get_memory_type(); 127 | item.protection = get_protection(); 128 | item.qos = get_qos(); 129 | 130 | begin_address(item); 131 | response_stores[item.id].push_back(store); 132 | endtask 133 | 134 | protected function tvip_axi_id get_address_id(); 135 | if (configuration.id_width > 0) begin 136 | return (write_component) ? vif.monitor_cb.awid : vif.monitor_cb.arid; 137 | end 138 | else begin 139 | return 0; 140 | end 141 | endfunction 142 | 143 | protected function tvip_axi_address get_address(); 144 | return (write_component) ? vif.monitor_cb.awaddr : vif.monitor_cb.araddr; 145 | endfunction 146 | 147 | protected function int get_burst_length(); 148 | if (configuration.protocol == TVIP_AXI4) begin 149 | tvip_axi_burst_length burst_length; 150 | burst_length = (write_component) ? vif.monitor_cb.awlen : vif.monitor_cb.arlen; 151 | return unpack_burst_length(burst_length); 152 | end 153 | else begin 154 | return 1; 155 | end 156 | endfunction 157 | 158 | protected function int get_burst_size(); 159 | if (configuration.protocol == TVIP_AXI4) begin 160 | tvip_axi_burst_size burst_size; 161 | burst_size = (write_component) ? vif.monitor_cb.awsize : vif.monitor_cb.arsize; 162 | return unpack_burst_size(burst_size); 163 | end 164 | else begin 165 | return configuration.data_width / 8; 166 | end 167 | endfunction 168 | 169 | protected function tvip_axi_burst_type get_burst_type(); 170 | if (configuration.protocol == TVIP_AXI4) begin 171 | return (write_component) ? vif.monitor_cb.awburst : vif.monitor_cb.arburst; 172 | end 173 | else begin 174 | return TVIP_AXI_FIXED_BURST; 175 | end 176 | endfunction 177 | 178 | protected function tvip_axi_memory_type get_memory_type(); 179 | if (configuration.protocol == TVIP_AXI4LITE) begin 180 | return TVIP_AXI_DEVICE_NON_BUFFERABLE; 181 | end 182 | else if (write_component) begin 183 | return decode_memory_type(vif.monitor_cb.awcache, 0); 184 | end 185 | else begin 186 | return decode_memory_type(vif.monitor_cb.arcache, 1); 187 | end 188 | endfunction 189 | 190 | protected function tvip_axi_protection get_protection(); 191 | return (write_component) ? vif.monitor_cb.awprot : vif.monitor_cb.arprot; 192 | endfunction 193 | 194 | protected function tvip_axi_qos get_qos(); 195 | return (write_component) ? vif.monitor_cb.awqos : vif.monitor_cb.arqos; 196 | endfunction 197 | 198 | protected task wait_for_address_ready(); 199 | if (is_write_component()) begin 200 | while (!vif.monitor_cb.awready) begin 201 | @(vif.monitor_cb); 202 | end 203 | end 204 | else begin 205 | while (!vif.monitor_cb.arready) begin 206 | @(vif.monitor_cb); 207 | end 208 | end 209 | endtask 210 | 211 | protected virtual task finish_address(ref tvip_axi_item item); 212 | end_address(item); 213 | item = null; 214 | endtask 215 | 216 | protected task write_data_monitor_thread(); 217 | tvip_axi_payload_store store; 218 | 219 | if (is_read_component()) begin 220 | return; 221 | end 222 | 223 | forever begin 224 | wait_for_write_data_valid(); 225 | if (store == null) begin 226 | store = get_write_data_store(); 227 | begin_write_data(store.item); 228 | end 229 | 230 | wait_for_write_data_ready(); 231 | sample_write_data(store); 232 | end 233 | endtask 234 | 235 | protected task wait_for_write_data_valid(); 236 | do begin 237 | @(vif.monitor_cb); 238 | end while (!vif.monitor_cb.wvalid); 239 | endtask 240 | 241 | protected function tvip_axi_payload_store get_write_data_store(); 242 | if (write_data_stores[0].size() > 0) begin 243 | return write_data_stores[0].pop_front(); 244 | end 245 | else begin 246 | tvip_axi_item item; 247 | tvip_axi_payload_store store; 248 | item = create_monitor_item(); 249 | store = tvip_axi_payload_store::create(item); 250 | write_data_stores[1].push_back(store); 251 | return store; 252 | end 253 | endfunction 254 | 255 | protected task wait_for_write_data_ready(); 256 | while (!vif.monitor_cb.wready) begin 257 | @(vif.monitor_cb); 258 | end 259 | endtask 260 | 261 | protected virtual task sample_write_data(ref tvip_axi_payload_store store); 262 | store.store_write_data(get_write_data(), get_strobe()); 263 | if (get_write_data_last()) begin 264 | store.pack_write_data(); 265 | end_write_data(store.item); 266 | store = null; 267 | end 268 | endtask 269 | 270 | protected function tvip_axi_data get_write_data(); 271 | return (write_component) ? vif.monitor_cb.wdata : '0; 272 | endfunction 273 | 274 | protected function tvip_axi_strobe get_strobe(); 275 | return (write_component) ? vif.monitor_cb.wstrb : '0; 276 | endfunction 277 | 278 | protected function bit get_write_data_last(); 279 | if (configuration.protocol == TVIP_AXI4) begin 280 | return (write_component) ? vif.monitor_cb.wlast : '0; 281 | end 282 | else begin 283 | return (write_component) ? 1 : '0; 284 | end 285 | endfunction 286 | 287 | protected task response_mointor_thread(); 288 | bit busy; 289 | tvip_axi_id id; 290 | tvip_axi_id current_id; 291 | 292 | forever begin 293 | wait_for_response_valid(); 294 | 295 | id = get_response_id(); 296 | if ((!busy) || (id != current_id)) begin 297 | if (is_valid_response(id)) begin 298 | busy = 1; 299 | current_id = id; 300 | if (!response_stores[current_id][0].item.response_began()) begin 301 | begin_response(response_stores[current_id][0].item); 302 | end 303 | end 304 | else begin 305 | busy = 0; 306 | `uvm_warning("UNEXPECTED_RESPONSE", $sformatf("unexpected response: id %h", id)) 307 | continue; 308 | end 309 | end 310 | 311 | wait_for_response_ready(); 312 | sample_response(current_id, busy); 313 | end 314 | endtask 315 | 316 | protected task wait_for_response_valid(); 317 | if (is_write_component()) begin 318 | do begin 319 | @(vif.monitor_cb); 320 | end while (!vif.monitor_cb.bvalid); 321 | end 322 | else begin 323 | do begin 324 | @(vif.monitor_cb); 325 | end while (!vif.monitor_cb.rvalid); 326 | end 327 | endtask 328 | 329 | protected function bit is_valid_response(tvip_axi_id id); 330 | return 331 | response_stores.exists(id) && 332 | response_stores[id].size() > 0; 333 | endfunction 334 | 335 | protected task wait_for_response_ready(); 336 | if (is_write_component()) begin 337 | while (!vif.monitor_cb.bready) begin 338 | @(vif.monitor_cb); 339 | end 340 | end 341 | else begin 342 | while (!vif.monitor_cb.rready) begin 343 | @(vif.monitor_cb); 344 | end 345 | end 346 | endtask 347 | 348 | protected virtual task sample_response( 349 | input tvip_axi_id id, 350 | ref bit busy 351 | ); 352 | tvip_axi_payload_store store; 353 | 354 | store = response_stores[id][0]; 355 | store.store_response(get_response(), get_read_data()); 356 | if (get_response_last()) begin 357 | store.pack_response(); 358 | end_response(store.item); 359 | void'(response_stores[id].pop_front()); 360 | busy = 0; 361 | end 362 | endtask 363 | 364 | protected function tvip_axi_id get_response_id(); 365 | if (configuration.id_width > 0) begin 366 | return (write_component) ? vif.monitor_cb.bid : vif.monitor_cb.rid; 367 | end 368 | else begin 369 | return 0; 370 | end 371 | endfunction 372 | 373 | protected function tvip_axi_response get_response(); 374 | return (write_component) ? vif.monitor_cb.bresp : vif.monitor_cb.rresp; 375 | endfunction 376 | 377 | protected function tvip_axi_data get_read_data(); 378 | return (write_component) ? '0 : vif.monitor_cb.rdata; 379 | endfunction 380 | 381 | protected function bit get_response_last(); 382 | if (configuration.protocol == TVIP_AXI4) begin 383 | return (write_component) ? '1 : vif.monitor_cb.rlast; 384 | end 385 | else begin 386 | return '1; 387 | end 388 | endfunction 389 | 390 | protected function tvip_axi_item create_monitor_item(); 391 | ITEM item; 392 | item = ITEM::type_id::create("axi_item"); 393 | item.set_context(this.configuration, this.status); 394 | return item; 395 | endfunction 396 | 397 | `tue_component_default_constructor(tvip_axi_monitor_base) 398 | endclass 399 | `endif 400 | -------------------------------------------------------------------------------- /src/tvip_axi_master_driver.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_MASTER_DRIVER_SVH 2 | `define TVIP_AXI_MASTER_DRIVER_SVH 3 | typedef tue_fifo #(tvip_axi_item) tvip_axi_request_item_queue; 4 | 5 | typedef tvip_axi_sub_driver_base #( 6 | .ITEM (tvip_axi_master_item ) 7 | ) tvip_axi_master_sub_driver_base; 8 | 9 | class tvip_axi_master_sub_driver extends tvip_axi_component_base #( 10 | .BASE (tvip_axi_master_sub_driver_base ) 11 | ); 12 | protected tvip_axi_request_item_queue address_queue; 13 | protected tvip_axi_request_item_queue write_data_queue; 14 | protected tvip_axi_payload_store response_stores[tvip_axi_id][$]; 15 | protected bit default_response_ready; 16 | 17 | function void build_phase(uvm_phase phase); 18 | super.build_phase(phase); 19 | address_queue = new("address_queue", 0); 20 | if (is_write_component()) begin 21 | write_data_queue = new("write_data_queue", 0); 22 | end 23 | endfunction 24 | 25 | task run_phase(uvm_phase phase); 26 | forever begin 27 | do_reset(); 28 | fork 29 | main(); 30 | @(negedge vif.areset_n); 31 | join_any 32 | disable fork; 33 | end 34 | endtask 35 | 36 | task end_response(tvip_axi_item item); 37 | super.end_response(item); 38 | if (item.need_response) begin 39 | put_response(item); 40 | end 41 | endtask 42 | 43 | task put_request(tvip_axi_item request); 44 | accept_tr(request); 45 | 46 | address_queue.put(request); 47 | if (write_data_queue != null) begin 48 | write_data_queue.put(request); 49 | end 50 | 51 | response_stores[request.id] 52 | .push_back(tvip_axi_payload_store::create(request)); 53 | endtask 54 | 55 | protected virtual task do_reset(); 56 | tvip_axi_item item; 57 | 58 | while (!address_queue.is_empty()) begin 59 | void'(address_queue.try_get(item)); 60 | if (!item.finished()) begin 61 | end_tr(item); 62 | end 63 | end 64 | 65 | if (write_data_queue != null) begin 66 | while (!write_data_queue.is_empty()) begin 67 | void'(write_data_queue.try_get(item)); 68 | if (!item.finished()) begin 69 | end_tr(item); 70 | end 71 | end 72 | end 73 | 74 | foreach (response_stores[i, j]) begin 75 | if (!response_stores[i][j].item.finished()) begin 76 | end_tr(response_stores[i][j].item); 77 | end 78 | end 79 | response_stores.delete(); 80 | 81 | reset_if(); 82 | @(posedge vif.areset_n); 83 | endtask 84 | 85 | protected virtual task reset_if(); 86 | endtask 87 | 88 | protected task main(); 89 | fork 90 | address_thread(); 91 | write_data_thread(); 92 | response_thread(); 93 | join 94 | endtask 95 | 96 | protected task address_thread(); 97 | tvip_axi_item item; 98 | 99 | forever begin 100 | get_item_from_queue(address_queue, item); 101 | consume_delay(item.start_delay); 102 | begin_address(item); 103 | drive_address(1, item); 104 | wait_for_address_ready(); 105 | drive_address(0, null); 106 | end_address(item); 107 | end 108 | endtask 109 | 110 | protected virtual task drive_address( 111 | bit valid, 112 | tvip_axi_item item 113 | ); 114 | endtask 115 | 116 | protected task wait_for_address_ready(); 117 | do begin 118 | @(vif.master_cb); 119 | end while (!get_address_ready()); 120 | endtask 121 | 122 | protected virtual function bit get_address_ready(); 123 | endfunction 124 | 125 | protected task write_data_thread(); 126 | tvip_axi_item item; 127 | 128 | if (is_read_component()) begin 129 | return; 130 | end 131 | 132 | forever begin 133 | get_item_from_queue(write_data_queue, item); 134 | 135 | for (int i = 0;i < item.get_burst_length();++i) begin 136 | consume_delay(item.write_data_delay[i]); 137 | if (i == 0) begin 138 | begin_write_data(item); 139 | end 140 | drive_write_data(1, item, i); 141 | wait_for_write_data_ready(); 142 | drive_write_data(0, null, 0); 143 | end 144 | 145 | end_write_data(item); 146 | end 147 | endtask 148 | 149 | protected virtual task drive_write_data( 150 | bit valid, 151 | tvip_axi_item item, 152 | int index 153 | ); 154 | vif.master_cb.wvalid <= valid; 155 | if (valid) begin 156 | vif.master_cb.wdata <= item.data[index]; 157 | vif.master_cb.wstrb <= item.strobe[index]; 158 | if (configuration.protocol == TVIP_AXI4) begin 159 | vif.master_cb.wlast <= index == (item.get_burst_length() - 1); 160 | end 161 | end 162 | endtask 163 | 164 | protected task wait_for_write_data_ready(); 165 | do begin 166 | @(vif.master_cb); 167 | end while (!vif.master_cb.wready); 168 | endtask 169 | 170 | protected task response_thread(); 171 | bit busy; 172 | tvip_axi_id id; 173 | tvip_axi_id current_id; 174 | int delay; 175 | 176 | forever begin 177 | wait_for_response_valid(); 178 | 179 | id = get_response_id(); 180 | if ((!busy) || (id != current_id)) begin 181 | if (is_valid_response(id)) begin 182 | busy = 1; 183 | current_id = id; 184 | if (!response_stores[current_id][0].item.response_began()) begin 185 | begin_response(response_stores[current_id][0].item); 186 | end 187 | end 188 | else begin 189 | busy = 0; 190 | `uvm_warning("UNEXPECTED_RESPONSE", $sformatf("unexpected response: id %h", id)) 191 | continue; 192 | end 193 | end 194 | 195 | delay = get_response_ready_delay(current_id); 196 | if (default_response_ready) begin 197 | sample_response(current_id, busy); 198 | if (delay > 0) begin 199 | drive_response_ready(0); 200 | consume_delay(delay); 201 | drive_response_ready(1); 202 | end 203 | end 204 | else begin 205 | consume_delay(delay); 206 | drive_response_ready(1); 207 | consume_delay(1); 208 | sample_response(current_id, busy); 209 | drive_response_ready(0); 210 | end 211 | end 212 | endtask 213 | 214 | protected task wait_for_response_valid(); 215 | do begin 216 | @(vif.master_cb); 217 | end while (!get_response_valid()); 218 | endtask 219 | 220 | protected virtual function bit get_response_valid(); 221 | endfunction 222 | 223 | protected virtual function tvip_axi_id get_response_id(); 224 | endfunction 225 | 226 | protected virtual function tvip_axi_data get_response_data(); 227 | endfunction 228 | 229 | protected virtual function tvip_axi_response get_response_status(); 230 | endfunction 231 | 232 | protected virtual function logic get_response_last(); 233 | endfunction 234 | 235 | protected function bit is_valid_response(tvip_axi_id id); 236 | return response_stores.exists(id) && response_stores[id].size() > 0; 237 | endfunction 238 | 239 | protected function int get_response_ready_delay(tvip_axi_id id); 240 | tvip_axi_payload_store store; 241 | int index; 242 | store = response_stores[id][0]; 243 | index = store.get_stored_response_count(); 244 | return store.item.response_ready_delay[index]; 245 | endfunction 246 | 247 | protected virtual task drive_response_ready(bit ready); 248 | endtask 249 | 250 | protected task sample_response( 251 | input tvip_axi_id id, 252 | ref bit busy 253 | ); 254 | tvip_axi_payload_store store; 255 | 256 | store = response_stores[id][0]; 257 | store.store_response(get_response_status(), get_response_data()); 258 | if (get_response_last()) begin 259 | store.pack_response(); 260 | end_response(store.item); 261 | void'(response_stores[id].pop_front()); 262 | busy = 0; 263 | end 264 | endtask 265 | 266 | protected task get_item_from_queue( 267 | input tvip_axi_request_item_queue queue, 268 | ref tvip_axi_item item 269 | ); 270 | queue.get(item); 271 | if (!vif.at_master_cb_edge.triggered) begin 272 | @(vif.at_master_cb_edge); 273 | end 274 | endtask 275 | 276 | protected task consume_delay(int delay); 277 | repeat (delay) begin 278 | @(vif.master_cb); 279 | end 280 | endtask 281 | 282 | `tue_component_default_constructor(tvip_axi_master_sub_driver) 283 | endclass 284 | 285 | class tvip_axi_master_write_driver extends tvip_axi_master_sub_driver; 286 | function new(string name = "tvip_axi_master_write_driver", uvm_component parent = null); 287 | super.new(name, parent); 288 | write_component = 1; 289 | endfunction 290 | 291 | function void build_phase(uvm_phase phase); 292 | super.build_phase(phase); 293 | default_response_ready = configuration.default_bready; 294 | endfunction 295 | 296 | protected task reset_if(); 297 | vif.master_cb.awvalid <= '0; 298 | vif.master_cb.awid <= '0; 299 | vif.master_cb.awaddr <= '0; 300 | vif.master_cb.awlen <= '0; 301 | vif.master_cb.awsize <= tvip_axi_burst_size'(0); 302 | vif.master_cb.awburst <= tvip_axi_burst_type'(0); 303 | vif.master_cb.awcache <= tvip_axi_write_cache'(0); 304 | vif.master_cb.awprot <= '0; 305 | vif.master_cb.awqos <= '0; 306 | vif.master_cb.wvalid <= '0; 307 | vif.master_cb.wdata <= '0; 308 | vif.master_cb.wstrb <= '0; 309 | vif.master_cb.wlast <= '0; 310 | vif.master_cb.bready <= configuration.default_bready; 311 | endtask 312 | 313 | protected task drive_address( 314 | bit valid, 315 | tvip_axi_item item 316 | ); 317 | vif.master_cb.awvalid <= valid; 318 | if (valid) begin 319 | vif.master_cb.awaddr <= item.address; 320 | vif.master_cb.awid <= item.id; 321 | vif.master_cb.awlen <= item.get_packed_burst_length(); 322 | vif.master_cb.awsize <= item.get_packed_burst_size(); 323 | vif.master_cb.awburst <= item.burst_type; 324 | vif.master_cb.awcache <= item.get_cache(); 325 | vif.master_cb.awprot <= item.protection; 326 | vif.master_cb.awqos <= item.qos; 327 | end 328 | endtask 329 | 330 | protected function bit get_address_ready(); 331 | return vif.master_cb.awready; 332 | endfunction 333 | 334 | protected function bit get_response_valid(); 335 | return vif.master_cb.bvalid; 336 | endfunction 337 | 338 | protected function tvip_axi_id get_response_id(); 339 | return vif.master_cb.bid; 340 | endfunction 341 | 342 | protected function tvip_axi_data get_response_data(); 343 | return '0; 344 | endfunction 345 | 346 | protected function tvip_axi_response get_response_status(); 347 | return vif.master_cb.bresp; 348 | endfunction 349 | 350 | protected function logic get_response_last(); 351 | return '1; 352 | endfunction 353 | 354 | protected task drive_response_ready(bit ready); 355 | vif.master_cb.bready <= ready; 356 | endtask 357 | 358 | `uvm_component_utils(tvip_axi_master_write_driver) 359 | endclass 360 | 361 | class tvip_axi_master_read_driver extends tvip_axi_master_sub_driver; 362 | function new(string name = "tvip_axi_master_read_driver", uvm_component parent = null); 363 | super.new(name, parent); 364 | write_component = 0; 365 | endfunction 366 | 367 | function void build_phase(uvm_phase phase); 368 | super.build_phase(phase); 369 | default_response_ready = configuration.default_rready; 370 | endfunction 371 | 372 | protected task reset_if(); 373 | vif.master_cb.arvalid <= '0; 374 | vif.master_cb.arid <= '0; 375 | vif.master_cb.araddr <= '0; 376 | vif.master_cb.arlen <= '0; 377 | vif.master_cb.arsize <= tvip_axi_burst_size'(0); 378 | vif.master_cb.arburst <= tvip_axi_burst_type'(0); 379 | vif.master_cb.arcache <= tvip_axi_read_cache'(0); 380 | vif.master_cb.arprot <= '0; 381 | vif.master_cb.arqos <= '0; 382 | vif.master_cb.rready <= configuration.default_rready; 383 | endtask 384 | 385 | protected task drive_address( 386 | bit valid, 387 | tvip_axi_item item 388 | ); 389 | vif.master_cb.arvalid <= valid; 390 | if (valid) begin 391 | vif.master_cb.araddr <= item.address; 392 | vif.master_cb.arid <= item.id; 393 | vif.master_cb.arlen <= item.get_packed_burst_length(); 394 | vif.master_cb.arsize <= item.get_packed_burst_size(); 395 | vif.master_cb.arburst <= item.burst_type; 396 | vif.master_cb.arcache <= item.get_cache(); 397 | vif.master_cb.arprot <= item.protection; 398 | vif.master_cb.arqos <= item.qos; 399 | end 400 | endtask 401 | 402 | protected function bit get_address_ready(); 403 | return vif.master_cb.arready; 404 | endfunction 405 | 406 | protected function bit get_response_valid(); 407 | return vif.master_cb.rvalid; 408 | endfunction 409 | 410 | protected function tvip_axi_id get_response_id(); 411 | return vif.master_cb.rid; 412 | endfunction 413 | 414 | protected function tvip_axi_data get_response_data(); 415 | return vif.master_cb.rdata; 416 | endfunction 417 | 418 | protected function tvip_axi_response get_response_status(); 419 | return vif.master_cb.rresp; 420 | endfunction 421 | 422 | protected function logic get_response_last(); 423 | return (configuration.protocol == TVIP_AXI4LITE) || vif.master_cb.rlast; 424 | endfunction 425 | 426 | protected task drive_response_ready(bit ready); 427 | vif.master_cb.rready <= ready; 428 | endtask 429 | 430 | `uvm_component_utils(tvip_axi_master_read_driver) 431 | endclass 432 | 433 | class tvip_axi_master_driver extends tvip_axi_driver_base #( 434 | .ITEM (tvip_axi_master_item ), 435 | .WRITE_DRIVER (tvip_axi_master_write_driver ), 436 | .READ_DRIVER (tvip_axi_master_read_driver ) 437 | ); 438 | `tue_component_default_constructor(tvip_axi_master_driver) 439 | `uvm_component_utils(tvip_axi_master_driver) 440 | endclass 441 | `endif 442 | -------------------------------------------------------------------------------- /src/tvip_axi_item.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_ITEM_SVH 2 | `define TVIP_AXI_ITEM_SVH 3 | class tvip_axi_item extends tue_sequence_item #( 4 | .CONFIGURATION (tvip_axi_configuration ), 5 | .STATUS (tvip_axi_status ) 6 | ); 7 | rand tvip_axi_access_type access_type; 8 | rand tvip_axi_id id; 9 | rand tvip_axi_address address; 10 | rand int burst_length; 11 | rand int burst_size; 12 | rand tvip_axi_burst_type burst_type; 13 | rand tvip_axi_memory_type memory_type; 14 | rand tvip_axi_protection protection; 15 | rand tvip_axi_qos qos; 16 | rand tvip_axi_data data[]; 17 | rand tvip_axi_strobe strobe[]; 18 | rand tvip_axi_response response[]; 19 | rand int start_delay; 20 | rand int write_data_delay[]; 21 | rand int response_delay[]; 22 | rand int address_ready_delay; 23 | rand int write_data_ready_delay[]; 24 | rand int response_ready_delay[]; 25 | uvm_event address_begin_event; 26 | time address_begin_time; 27 | uvm_event address_end_event; 28 | time address_end_time; 29 | uvm_event write_data_begin_event; 30 | time write_data_begin_time; 31 | uvm_event write_data_end_event; 32 | time write_data_end_time; 33 | uvm_event response_begin_event; 34 | time response_begin_time; 35 | uvm_event response_end_event; 36 | time response_end_time; 37 | rand bit need_response; 38 | 39 | function new(string name = "tvip_axi_item"); 40 | super.new(name); 41 | address_begin_event = get_event("address_begin"); 42 | address_end_event = get_event("address_end"); 43 | write_data_begin_event = get_event("write_data_begin"); 44 | write_data_end_event = get_event("write_data_end"); 45 | response_begin_event = get_event("response_begin"); 46 | response_end_event = get_event("response_end"); 47 | endfunction 48 | 49 | function bit do_compare(uvm_object rhs, uvm_comparer comparer); 50 | tvip_axi_item rhs_item; 51 | $cast(rhs_item, rhs); 52 | return 53 | super.do_compare(rhs, comparer) && 54 | compare_memory_type(memory_type, rhs_item.memory_type, is_read()); 55 | endfunction 56 | 57 | function bit is_write(); 58 | return (access_type == TVIP_AXI_WRITE_ACCESS) ? '1 : '0; 59 | endfunction 60 | 61 | function bit is_read(); 62 | return (access_type == TVIP_AXI_READ_ACCESS) ? '1 : '0; 63 | endfunction 64 | 65 | function int get_burst_length(); 66 | if ((configuration != null) && (configuration.protocol == TVIP_AXI4LITE)) begin 67 | return 1; 68 | end 69 | else begin 70 | return burst_length; 71 | end 72 | endfunction 73 | 74 | function tvip_axi_burst_length get_packed_burst_length(); 75 | return pack_burst_length(get_burst_length()); 76 | endfunction 77 | 78 | function void set_packed_burst_length(tvip_axi_burst_length packed_burst_length); 79 | if ((configuration != null) && (configuration.protocol == TVIP_AXI4LITE)) begin 80 | burst_length = 1; 81 | end 82 | else begin 83 | burst_length = unpack_burst_length(packed_burst_length); 84 | end 85 | endfunction 86 | 87 | function int get_burst_size(); 88 | if ((configuration != null) && (configuration.protocol == TVIP_AXI4LITE)) begin 89 | return configuration.data_width / 8; 90 | end 91 | else begin 92 | return burst_size; 93 | end 94 | endfunction 95 | 96 | function tvip_axi_burst_size get_packed_burst_size(); 97 | return pack_burst_size(get_burst_size()); 98 | endfunction 99 | 100 | function void set_packed_burst_size(tvip_axi_burst_size packed_burst_size); 101 | if ((configuration != null) && (configuration.protocol == TVIP_AXI4LITE)) begin 102 | burst_size = configuration.data_width / 8; 103 | end 104 | else begin 105 | burst_size = unpack_burst_size(packed_burst_size); 106 | end 107 | endfunction 108 | 109 | function tvip_axi_cache get_cache(); 110 | if ((configuration != null) && (configuration.protocol == TVIP_AXI4LITE)) begin 111 | return '0; 112 | end 113 | else begin 114 | return encode_memory_type(memory_type, is_read()); 115 | end 116 | endfunction 117 | 118 | function void put_cache(tvip_axi_cache cache); 119 | if ((configuration != null) && (configuration.protocol == TVIP_AXI4LITE)) begin 120 | memory_type = TVIP_AXI_DEVICE_NON_BUFFERABLE; 121 | end 122 | else begin 123 | memory_type = decode_memory_type(cache, is_read()); 124 | end 125 | endfunction 126 | 127 | function void put_data(const ref tvip_axi_data data[$]); 128 | this.data = new[data.size()]; 129 | foreach (data[i]) begin 130 | this.data[i] = data[i]; 131 | end 132 | endfunction 133 | 134 | function tvip_axi_data get_data(int index); 135 | if (index < data.size()) begin 136 | return data[index]; 137 | end 138 | else begin 139 | return '0; 140 | end 141 | endfunction 142 | 143 | function void put_strobe(const ref tvip_axi_strobe strobe[$]); 144 | this.strobe = new[strobe.size()]; 145 | foreach (strobe[i]) begin 146 | this.strobe[i] = strobe[i]; 147 | end 148 | endfunction 149 | 150 | function tvip_axi_strobe get_strobe(int index); 151 | if (index < strobe.size()) begin 152 | return strobe[index]; 153 | end 154 | else begin 155 | return '0; 156 | end 157 | endfunction 158 | 159 | function void put_response(const ref tvip_axi_response response[$]); 160 | this.response = new[response.size()]; 161 | foreach (response[i]) begin 162 | this.response[i] = response[i]; 163 | end 164 | endfunction 165 | 166 | function tvip_axi_response get_response(int index); 167 | if (index < response.size()) begin 168 | return response[index]; 169 | end 170 | else begin 171 | return TVIP_AXI_OKAY; 172 | end 173 | endfunction 174 | 175 | `define tvip_axi_declare_begin_end_event_api(EVENT_TYPE) \ 176 | function void begin_``EVENT_TYPE``(time begin_time = 0); \ 177 | if (``EVENT_TYPE``_begin_event.is_off()) begin \ 178 | ``EVENT_TYPE``_begin_time = (begin_time <= 0) ? $time : begin_time; \ 179 | ``EVENT_TYPE``_begin_event.trigger(); \ 180 | end \ 181 | endfunction \ 182 | function void end_``EVENT_TYPE``(time end_time = 0); \ 183 | if (``EVENT_TYPE``_end_event.is_off()) begin \ 184 | ``EVENT_TYPE``_end_time = (end_time <= 0) ? $time : end_time; \ 185 | ``EVENT_TYPE``_end_event.trigger(); \ 186 | end \ 187 | endfunction \ 188 | function bit ``EVENT_TYPE``_began(); \ 189 | return ``EVENT_TYPE``_begin_event.is_on(); \ 190 | endfunction \ 191 | function bit ``EVENT_TYPE``_ended(); \ 192 | return ``EVENT_TYPE``_end_event.is_on(); \ 193 | endfunction 194 | 195 | `tvip_axi_declare_begin_end_event_api(address ) 196 | `tvip_axi_declare_begin_end_event_api(write_data) 197 | `tvip_axi_declare_begin_end_event_api(response ) 198 | 199 | `undef tvip_axi_declare_begin_end_event_api 200 | 201 | function bit request_began(); 202 | return address_began(); 203 | endfunction 204 | 205 | function bit request_ended(); 206 | if (is_write()) begin 207 | return (address_ended() && write_data_ended()) ? 1 : 0; 208 | end 209 | else begin 210 | return address_ended(); 211 | end 212 | endfunction 213 | 214 | task wait_for_done(); 215 | response_end_event.wait_on(); 216 | endtask 217 | 218 | task wait_for_request_done(); 219 | address_end_event.wait_on(); 220 | if (is_write()) begin 221 | write_data_end_event.wait_on(); 222 | end 223 | endtask 224 | 225 | //-------------------------------------------------------------- 226 | // Random constraints for request 227 | //-------------------------------------------------------------- 228 | constraint c_valid_id { 229 | (id >> this.configuration.id_width) == 0; 230 | } 231 | 232 | constraint c_valid_address { 233 | (address >> this.configuration.address_width) == 0; 234 | } 235 | 236 | constraint c_valid_burst_length { 237 | if (this.configuration.protocol == TVIP_AXI4) { 238 | burst_length inside {[1:this.configuration.max_burst_length]}; 239 | } 240 | else { 241 | burst_length == 1; 242 | } 243 | } 244 | 245 | constraint c_valid_burst_size { 246 | if (this.configuration.protocol == TVIP_AXI4) { 247 | burst_size inside {1, 2, 4, 8, 16, 32, 64, 128}; 248 | (8 * burst_size) <= this.configuration.data_width; 249 | } 250 | else { 251 | (8 * burst_size) == this.configuration.data_width; 252 | } 253 | } 254 | 255 | constraint c_4kb_boundary { 256 | ( 257 | (address & `tvip_axi_4kb_boundary_mask(burst_size)) + 258 | (burst_length * burst_size) 259 | ) <= 4096; 260 | } 261 | 262 | constraint c_valid_memory_type { 263 | if (this.configuration.protocol == TVIP_AXI4LITE) { 264 | memory_type == TVIP_AXI_DEVICE_NON_BUFFERABLE; 265 | } 266 | } 267 | 268 | constraint c_valid_qos { 269 | qos inside {[ 270 | this.configuration.qos_range[0]: 271 | this.configuration.qos_range[1] 272 | ]}; 273 | } 274 | 275 | constraint c_valid_write_data { 276 | solve access_type before data; 277 | solve burst_length before data; 278 | 279 | (access_type == TVIP_AXI_WRITE_ACCESS) -> data.size() == burst_length; 280 | (access_type == TVIP_AXI_READ_ACCESS ) -> data.size() == 0; 281 | 282 | foreach (data[i]) { 283 | (data[i] >> this.configuration.data_width) == 0; 284 | } 285 | } 286 | 287 | constraint c_valid_strobe { 288 | solve access_type before strobe; 289 | solve burst_length before strobe; 290 | 291 | (access_type == TVIP_AXI_WRITE_ACCESS) -> strobe.size() == burst_length; 292 | (access_type == TVIP_AXI_READ_ACCESS ) -> strobe.size() == 0; 293 | 294 | foreach (strobe[i]) { 295 | (strobe[i] >> this.configuration.strobe_width) == 0; 296 | } 297 | } 298 | 299 | constraint c_address_start_delay { 300 | `tvip_delay_constraint(start_delay, this.configuration.request_start_delay) 301 | } 302 | 303 | constraint c_write_data_delay { 304 | solve access_type, burst_length before write_data_delay; 305 | 306 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 307 | write_data_delay.size() == burst_length; 308 | } 309 | else { 310 | write_data_delay.size() == 0; 311 | } 312 | 313 | foreach (write_data_delay[i]) { 314 | `tvip_delay_constraint(write_data_delay[i], this.configuration.write_data_delay) 315 | } 316 | } 317 | 318 | constraint c_response_ready_delay { 319 | solve access_type, burst_length before response_ready_delay; 320 | 321 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 322 | response_ready_delay.size() == 1; 323 | } 324 | else { 325 | response_ready_delay.size() == burst_length; 326 | } 327 | 328 | foreach (response_ready_delay[i]) { 329 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 330 | `tvip_delay_constraint(response_ready_delay[i], this.configuration.bready_delay) 331 | } 332 | else { 333 | `tvip_delay_constraint(response_ready_delay[i], this.configuration.rready_delay) 334 | } 335 | } 336 | } 337 | 338 | //-------------------------------------------------------------- 339 | // Random constraints for response 340 | //-------------------------------------------------------------- 341 | constraint c_valid_read_data { 342 | data.size() == burst_length; 343 | foreach (data[i]) { 344 | (data[i] >> this.configuration.data_width) == 0; 345 | } 346 | } 347 | 348 | constraint c_valid_response { 349 | (access_type == TVIP_AXI_WRITE_ACCESS) -> response.size() == 1; 350 | (access_type == TVIP_AXI_READ_ACCESS ) -> response.size() == burst_length; 351 | foreach (response[i]) { 352 | response[i] dist { 353 | TVIP_AXI_OKAY := this.configuration.response_weight_okay, 354 | TVIP_AXI_EXOKAY := this.configuration.response_weight_exokay, 355 | TVIP_AXI_SLAVE_ERROR := this.configuration.response_weight_slave_error, 356 | TVIP_AXI_DECODE_ERROR := this.configuration.response_weight_decode_error 357 | }; 358 | } 359 | } 360 | 361 | constraint c_address_ready_delay { 362 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 363 | `tvip_delay_constraint(address_ready_delay, this.configuration.awready_delay) 364 | } 365 | else { 366 | `tvip_delay_constraint(address_ready_delay, this.configuration.arready_delay) 367 | } 368 | } 369 | 370 | constraint c_write_data_ready_delay { 371 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 372 | write_data_ready_delay.size() == burst_length; 373 | } 374 | else { 375 | write_data_ready_delay.size() == 0; 376 | } 377 | 378 | foreach (write_data_ready_delay[i]) { 379 | `tvip_delay_constraint(write_data_ready_delay[i], this.configuration.wready_delay) 380 | } 381 | } 382 | 383 | constraint c_response_start_delay { 384 | `tvip_delay_constraint(start_delay, this.configuration.response_start_delay) 385 | } 386 | 387 | constraint c_response_delay { 388 | if (access_type == TVIP_AXI_WRITE_ACCESS) { 389 | response_delay.size() == 1; 390 | } 391 | else { 392 | response_delay.size() == burst_length; 393 | } 394 | 395 | foreach (response_delay[i]) { 396 | `tvip_delay_constraint(response_delay[i], this.configuration.response_delay) 397 | } 398 | } 399 | 400 | `uvm_object_utils_begin(tvip_axi_item) 401 | `uvm_field_enum(tvip_axi_access_type, access_type, UVM_DEFAULT) 402 | `uvm_field_int(id, UVM_DEFAULT | UVM_HEX) 403 | `uvm_field_int(address, UVM_DEFAULT | UVM_HEX) 404 | `uvm_field_int(burst_length, UVM_DEFAULT | UVM_DEC) 405 | `uvm_field_int(burst_size, UVM_DEFAULT | UVM_DEC) 406 | `uvm_field_enum(tvip_axi_burst_type, burst_type, UVM_DEFAULT) 407 | `uvm_field_enum(tvip_axi_memory_type, memory_type, UVM_DEFAULT | UVM_NOCOMPARE) 408 | `uvm_field_int(protection, UVM_DEFAULT | UVM_BIN) 409 | `uvm_field_int(qos, UVM_DEFAULT | UVM_DEC) 410 | `uvm_field_array_int(data, UVM_DEFAULT | UVM_HEX) 411 | `uvm_field_array_int(strobe, UVM_DEFAULT | UVM_HEX) 412 | `uvm_field_array_enum(tvip_axi_response, response, UVM_DEFAULT) 413 | `uvm_field_int(start_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 414 | `uvm_field_array_int(write_data_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 415 | `uvm_field_array_int(response_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 416 | `uvm_field_int(address_ready_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 417 | `uvm_field_array_int(write_data_ready_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 418 | `uvm_field_array_int(response_ready_delay, UVM_DEFAULT | UVM_DEC | UVM_NOCOMPARE) 419 | `uvm_field_int(address_begin_time, UVM_DEFAULT | UVM_TIME | UVM_NOCOMPARE) 420 | `uvm_field_int(address_end_time, UVM_DEFAULT | UVM_TIME | UVM_NOCOMPARE) 421 | `uvm_field_int(write_data_begin_time, UVM_DEFAULT | UVM_TIME | UVM_NOCOMPARE) 422 | `uvm_field_int(write_data_end_time, UVM_DEFAULT | UVM_TIME | UVM_NOCOMPARE) 423 | `uvm_field_int(response_begin_time, UVM_DEFAULT | UVM_TIME | UVM_NOCOMPARE) 424 | `uvm_field_int(response_end_time, UVM_DEFAULT | UVM_TIME | UVM_NOCOMPARE) 425 | `uvm_field_int(need_response, UVM_DEFAULT | UVM_NOCOMPARE | UVM_NOPRINT) 426 | `uvm_object_utils_end 427 | endclass 428 | 429 | class tvip_axi_master_item extends tvip_axi_item; 430 | constraint c_default_need_response { 431 | soft need_response == 0; 432 | } 433 | 434 | function void pre_randomize(); 435 | super.pre_randomize(); 436 | response.rand_mode(0); 437 | response_delay.rand_mode(0); 438 | address_ready_delay.rand_mode(0); 439 | write_data_ready_delay.rand_mode(0); 440 | c_valid_read_data.constraint_mode(0); 441 | c_valid_response.constraint_mode(0); 442 | c_address_ready_delay.constraint_mode(0); 443 | c_write_data_ready_delay.constraint_mode(0); 444 | c_response_start_delay.constraint_mode(0); 445 | c_response_delay.constraint_mode(0); 446 | endfunction 447 | 448 | `tue_object_default_constructor(tvip_axi_master_item) 449 | `uvm_object_utils(tvip_axi_master_item) 450 | endclass 451 | 452 | class tvip_axi_slave_item extends tvip_axi_item; 453 | constraint c_default_need_response { 454 | soft need_response == 1; 455 | } 456 | 457 | function void pre_randomize(); 458 | super.pre_randomize(); 459 | access_type.rand_mode(0); 460 | id.rand_mode(0); 461 | address.rand_mode(0); 462 | burst_length.rand_mode(0); 463 | burst_size.rand_mode(0); 464 | burst_type.rand_mode(0); 465 | protection.rand_mode(0); 466 | qos.rand_mode(0); 467 | data.rand_mode(is_read()); 468 | strobe.rand_mode(0); 469 | write_data_delay.rand_mode(0); 470 | response_ready_delay.rand_mode(0); 471 | c_valid_id.constraint_mode(0); 472 | c_valid_address.constraint_mode(0); 473 | c_valid_burst_length.constraint_mode(0); 474 | c_valid_burst_size.constraint_mode(0); 475 | c_4kb_boundary.constraint_mode(0); 476 | c_valid_qos.constraint_mode(0); 477 | c_valid_write_data.constraint_mode(0); 478 | c_valid_read_data.constraint_mode(is_read()); 479 | c_valid_strobe.constraint_mode(0); 480 | c_address_start_delay.constraint_mode(0); 481 | c_write_data_delay.constraint_mode(0); 482 | c_response_ready_delay.constraint_mode(0); 483 | endfunction 484 | 485 | `tue_object_default_constructor(tvip_axi_slave_item) 486 | `uvm_object_utils(tvip_axi_slave_item) 487 | endclass 488 | `endif 489 | -------------------------------------------------------------------------------- /src/tvip_axi_slave_driver.svh: -------------------------------------------------------------------------------- 1 | `ifndef TVIP_AXI_SLAVE_DRIVER_SVH 2 | `define TVIP_AXI_SLAVE_DRIVER_SVH 3 | typedef tue_fifo #(tvip_axi_item) tvip_axi_slave_driver_item_queue; 4 | 5 | typedef struct { 6 | tvip_axi_item item; 7 | tvip_axi_slave_driver_item_queue queue; 8 | } tvip_axi_start_delay_item; 9 | 10 | class tvip_axi_slave_driver_start_delay_consumer; 11 | protected uvm_component parent; 12 | protected tvip_axi_vif vif; 13 | protected tue_fifo #(tvip_axi_start_delay_item) delay_queue[tvip_axi_id]; 14 | protected event reset; 15 | protected event notifier; 16 | 17 | function new(uvm_component parent, tvip_axi_vif vif); 18 | this.parent = parent; 19 | this.vif = vif; 20 | endfunction 21 | 22 | task consume_start_delay( 23 | tvip_axi_item item, 24 | tvip_axi_id queue_id, 25 | tvip_axi_slave_driver_item_queue queue 26 | ); 27 | tvip_axi_start_delay_item delay_item; 28 | 29 | delay_item.item = item; 30 | delay_item.queue = queue; 31 | if (!delay_queue.exists(queue_id)) begin 32 | start_delay_thread(queue_id); 33 | end 34 | delay_queue[queue_id].put(delay_item); 35 | endtask 36 | 37 | task wait_for_active_response(); 38 | @(notifier); 39 | endtask 40 | 41 | function void do_reset(); 42 | ->reset; 43 | endfunction 44 | 45 | protected task start_delay_thread(tvip_axi_id id); 46 | delay_queue[id] = new("delay_queue", 0); 47 | fork 48 | automatic tvip_axi_id __id = id; 49 | delay_thread(__id); 50 | join_none 51 | endtask 52 | 53 | protected task delay_thread(tvip_axi_id id); 54 | tvip_axi_start_delay_item item; 55 | 56 | forever begin 57 | fork 58 | forever begin 59 | delay_queue[id].get(item); 60 | delay_thread_body(item); 61 | end 62 | @(reset); 63 | join_any 64 | disable fork; 65 | 66 | if ((item.item != null) && (!item.item.finished())) begin 67 | parent.end_tr(item.item); 68 | end 69 | 70 | while (delay_queue[id].try_get(item)) begin 71 | if (!item.item.finished()) begin 72 | parent.end_tr(item.item); 73 | end 74 | end 75 | end 76 | endtask 77 | 78 | protected task delay_thread_body(ref tvip_axi_start_delay_item item); 79 | item.item.wait_for_request_done(); 80 | repeat (item.item.start_delay) begin 81 | @(vif.slave_cb); 82 | end 83 | item.queue.put(item.item); 84 | ->notifier; 85 | endtask 86 | endclass 87 | 88 | class tvip_axi_slave_driver_response_item; 89 | tvip_axi_item item; 90 | int size; 91 | int index; 92 | 93 | function new(tvip_axi_item item); 94 | this.item = item; 95 | endfunction 96 | 97 | function tvip_axi_id get_id(); 98 | return item.id; 99 | endfunction 100 | 101 | function tvip_axi_response get_response_status(); 102 | return item.response[index]; 103 | endfunction 104 | 105 | function tvip_axi_data get_data(); 106 | if (item.is_read()) begin 107 | return item.data[index]; 108 | end 109 | else begin 110 | return '0; 111 | end 112 | endfunction 113 | 114 | function bit get_last(); 115 | if (item.is_read()) begin 116 | return (index + 1) == item.get_burst_length(); 117 | end 118 | else begin 119 | return 1; 120 | end 121 | endfunction 122 | 123 | function int get_delay(); 124 | return item.response_delay[index]; 125 | endfunction 126 | 127 | function bit is_last_response_done(); 128 | return item.is_write() || (index == item.get_burst_length()); 129 | endfunction 130 | 131 | function void next(); 132 | size -= 1; 133 | index += 1; 134 | endfunction 135 | endclass 136 | 137 | typedef tvip_axi_sub_driver_base #( 138 | .ITEM (tvip_axi_slave_item ) 139 | ) tvip_axi_slave_sub_driver_base; 140 | 141 | class tvip_axi_slave_sub_driver extends tvip_axi_component_base #( 142 | .BASE (tvip_axi_slave_sub_driver_base ) 143 | ); 144 | protected int ready_delay_queue[2][$]; 145 | protected int preceded_ready_count[2]; 146 | protected tvip_axi_slave_driver_start_delay_consumer start_delay_consumer; 147 | protected tvip_axi_slave_driver_item_queue response_queue[tvip_axi_id]; 148 | protected tvip_axi_slave_driver_response_item active_responses[$]; 149 | protected tvip_axi_id active_ids[$]; 150 | protected int current_response_index; 151 | 152 | function void build_phase(uvm_phase phase); 153 | super.build_phase(phase); 154 | start_delay_consumer = new(this, vif); 155 | endfunction 156 | 157 | task run_phase(uvm_phase phase); 158 | forever begin 159 | do_reset(); 160 | fork 161 | main(); 162 | @(negedge vif.areset_n); 163 | join_any 164 | disable fork; 165 | end 166 | endtask 167 | 168 | task put_request(tvip_axi_item request); 169 | tvip_axi_id queue_id; 170 | 171 | ready_delay_queue[0].push_back(request.address_ready_delay); 172 | if (is_write_component()) begin 173 | foreach (request.write_data_ready_delay[i]) begin 174 | ready_delay_queue[1].push_back(request.write_data_ready_delay[i]); 175 | end 176 | end 177 | 178 | case (configuration.response_ordering) 179 | TVIP_AXI_OUT_OF_ORDER: queue_id = request.id; 180 | TVIP_AXI_IN_ORDER: queue_id = 0; 181 | endcase 182 | 183 | if (!response_queue.exists(queue_id)) begin 184 | response_queue[queue_id] = new("response_queue", 0); 185 | end 186 | 187 | accept_tr(request); 188 | start_delay_consumer.consume_start_delay(request, queue_id, response_queue[queue_id]); 189 | endtask 190 | 191 | task begin_response(tvip_axi_item item); 192 | super.begin_response(item); 193 | void'(begin_tr(item)); 194 | endtask 195 | 196 | protected task do_reset(); 197 | start_delay_consumer.do_reset(); 198 | 199 | ready_delay_queue[0].delete(); 200 | ready_delay_queue[1].delete(); 201 | preceded_ready_count[0] = 0; 202 | preceded_ready_count[1] = 0; 203 | 204 | foreach (response_queue[i]) begin 205 | tvip_axi_item item; 206 | while (response_queue[i].try_get(item)) begin 207 | if (!item.finished()) begin 208 | end_tr(item); 209 | end 210 | end 211 | end 212 | response_queue.delete(); 213 | 214 | foreach (active_responses[i]) begin 215 | if (active_responses[i].item.finished()) begin 216 | end_tr(active_responses[i].item); 217 | end 218 | end 219 | active_responses.delete(); 220 | active_ids.delete(); 221 | 222 | reset_if(); 223 | @(posedge vif.areset_n); 224 | endtask 225 | 226 | protected virtual task reset_if(); 227 | endtask 228 | 229 | protected task main(); 230 | fork 231 | drive_ready_thread(0); 232 | drive_ready_thread(1); 233 | response_thread(); 234 | join 235 | endtask 236 | 237 | protected task drive_ready_thread(bit write_data_thread); 238 | bit default_ready; 239 | tvip_delay_configuration delay_configuration; 240 | int delay; 241 | 242 | if (write_data_thread && is_read_component()) begin 243 | return; 244 | end 245 | 246 | if (is_read_component()) begin 247 | default_ready = configuration.default_arready; 248 | delay_configuration = configuration.arready_delay; 249 | end 250 | else if (write_data_thread) begin 251 | default_ready = configuration.default_wready; 252 | delay_configuration = configuration.wready_delay; 253 | end 254 | else begin 255 | default_ready = configuration.default_awready; 256 | delay_configuration = configuration.awready_delay; 257 | end 258 | 259 | forever begin 260 | wait_for_request_valid(write_data_thread); 261 | get_ready_delay(write_data_thread, delay_configuration, delay); 262 | 263 | if (default_ready && (delay > 0)) begin 264 | drive_ready(write_data_thread, 0); 265 | consume_delay(delay); 266 | drive_ready(write_data_thread, 1); 267 | end 268 | else if (!default_ready) begin 269 | consume_delay(delay); 270 | drive_ready(write_data_thread, 1); 271 | consume_delay(1); 272 | drive_ready(write_data_thread, 0); 273 | end 274 | end 275 | endtask 276 | 277 | protected task wait_for_request_valid(bit write_data_thread); 278 | do begin 279 | @(vif.slave_cb); 280 | end while (!get_request_valid(write_data_thread)); 281 | endtask 282 | 283 | protected virtual function bit get_request_valid(bit write_data_thread); 284 | endfunction 285 | 286 | protected task get_ready_delay( 287 | input bit write_data_thread, 288 | input tvip_delay_configuration delay_configuration, 289 | ref int delay 290 | ); 291 | int queque_index = int'(write_data_thread); 292 | 293 | if (ready_delay_queue[queque_index].size() == 0) begin 294 | uvm_wait_for_nba_region(); 295 | end 296 | 297 | if (ready_delay_queue[queque_index].size() > 0) begin 298 | while (preceded_ready_count[queque_index] > 0) begin 299 | preceded_ready_count[queque_index] -= 1; 300 | void'(ready_delay_queue[queque_index].pop_front()); 301 | end 302 | delay = ready_delay_queue[queque_index].pop_front(); 303 | end 304 | else begin 305 | preceded_ready_count[queque_index] += 1; 306 | delay = randomize_ready_delay(delay_configuration); 307 | end 308 | endtask 309 | 310 | protected function int randomize_ready_delay(tvip_delay_configuration delay_configuration); 311 | int delay; 312 | 313 | if (!std::randomize(delay) with { 314 | `tvip_delay_constraint(delay, delay_configuration) 315 | }) begin 316 | `uvm_fatal("RNDFLD", "Randomization failed") 317 | end 318 | 319 | return delay; 320 | endfunction 321 | 322 | protected virtual task drive_ready(bit write_data_thread, bit ready); 323 | endtask 324 | 325 | protected task response_thread(); 326 | tvip_axi_slave_driver_response_item item; 327 | int size; 328 | 329 | forever begin 330 | get_next_response_item(item); 331 | if (item == null) begin 332 | continue; 333 | end 334 | 335 | if (!item.item.response_began()) begin 336 | begin_response(item.item); 337 | end 338 | 339 | size = get_response_size(item); 340 | repeat (size) begin 341 | execute_response_item(item); 342 | end 343 | 344 | if (item.is_last_response_done()) begin 345 | active_responses.delete(current_response_index); 346 | active_ids.delete(current_response_index); 347 | end 348 | end 349 | endtask 350 | 351 | protected task get_next_response_item(ref tvip_axi_slave_driver_response_item item); 352 | tvip_axi_item axi_item; 353 | tvip_axi_slave_driver_response_item new_item; 354 | 355 | if (no_response()) begin 356 | start_delay_consumer.wait_for_active_response(); 357 | if (!vif.at_slave_cb_edge.triggered) begin 358 | @(vif.at_slave_cb_edge); 359 | end 360 | end 361 | 362 | foreach (response_queue[id]) begin 363 | if (response_queue[id].used() == 0) begin 364 | continue; 365 | end 366 | if (!is_acceptable_response(id)) begin 367 | continue; 368 | end 369 | 370 | response_queue[id].get(axi_item); 371 | new_item = new(axi_item); 372 | active_responses.push_back(new_item); 373 | active_ids.push_back(id); 374 | end 375 | 376 | if (active_responses.size() == 0) begin 377 | item = null; 378 | return; 379 | end 380 | 381 | current_response_index = select_response(); 382 | item = active_responses[current_response_index]; 383 | endtask 384 | 385 | protected function bit no_response(); 386 | if (active_responses.size() > 0) begin 387 | return 0; 388 | end 389 | foreach (response_queue[i]) begin 390 | if (response_queue[i].used() > 0) begin 391 | return 0; 392 | end 393 | end 394 | return 1; 395 | endfunction 396 | 397 | protected function bit is_acceptable_response(tvip_axi_id id); 398 | if (id inside {active_ids}) begin 399 | return 0; 400 | end 401 | else if (configuration.outstanding_responses > 0) begin 402 | return active_responses.size() < configuration.outstanding_responses; 403 | end 404 | else begin 405 | return 1; 406 | end 407 | endfunction 408 | 409 | protected virtual function int select_response(); 410 | if (configuration.response_ordering == TVIP_AXI_OUT_OF_ORDER) begin 411 | foreach (active_responses[i]) begin 412 | randcase 413 | 1: return i; 414 | 1: continue; 415 | endcase 416 | end 417 | end 418 | 419 | return 0; 420 | endfunction 421 | 422 | protected virtual function int get_response_size(tvip_axi_slave_driver_response_item item); 423 | if (is_write_component()) begin 424 | return 1; 425 | end 426 | else if (!configuration.enable_response_interleaving) begin 427 | return item.item.get_burst_length(); 428 | end 429 | else begin 430 | return randomize_response_size(item); 431 | end 432 | endfunction 433 | 434 | protected virtual function int randomize_response_size(tvip_axi_slave_driver_response_item item); 435 | int size; 436 | int min; 437 | int max; 438 | int remaining; 439 | 440 | remaining = item.item.get_burst_length() - item.index; 441 | min = configuration.min_interleave_size; 442 | max = configuration.max_interleave_size; 443 | if (std::randomize(size) with { 444 | size inside {[1:remaining]}; 445 | if ((min > 0) && (remaining >= min)) { 446 | size >= min; 447 | } 448 | if ((max > 0)) { 449 | size <= max; 450 | } 451 | }) begin 452 | return size; 453 | end 454 | else begin 455 | `uvm_fatal("RNDFLD", "Randomization failed") 456 | end 457 | endfunction 458 | 459 | protected task execute_response_item(tvip_axi_slave_driver_response_item item); 460 | consume_delay(item.get_delay()); 461 | drive_response(1, item); 462 | wait_for_response_ready(); 463 | drive_response(0, null); 464 | 465 | item.next(); 466 | if (item.is_last_response_done()) begin 467 | end_response(item.item); 468 | end 469 | endtask 470 | 471 | protected virtual task drive_response(bit valid, tvip_axi_slave_driver_response_item item); 472 | endtask 473 | 474 | protected task wait_for_response_ready(); 475 | do begin 476 | @(vif.slave_cb); 477 | end while (!get_response_ready()); 478 | endtask 479 | 480 | protected virtual function bit get_response_ready(); 481 | endfunction 482 | 483 | protected task consume_delay(int delay); 484 | repeat (delay) begin 485 | @(vif.slave_cb); 486 | end 487 | endtask 488 | 489 | `tue_component_default_constructor(tvip_axi_slave_sub_driver) 490 | endclass 491 | 492 | class tvip_axi_slave_write_driver extends tvip_axi_slave_sub_driver; 493 | function new(string name = "tvip_axi_slave_write_driver", uvm_component parent = null); 494 | super.new(name, parent); 495 | write_component = 1; 496 | endfunction 497 | 498 | protected task reset_if(); 499 | vif.slave_cb.awready <= configuration.default_awready; 500 | vif.slave_cb.wready <= configuration.default_wready; 501 | vif.slave_cb.bvalid <= '0; 502 | vif.slave_cb.bid <= '0; 503 | vif.slave_cb.bresp <= tvip_axi_response'(0); 504 | endtask 505 | 506 | protected function bit get_request_valid(bit write_data_thread); 507 | if (write_data_thread) begin 508 | return vif.slave_cb.wvalid; 509 | end 510 | else begin 511 | return vif.slave_cb.awvalid; 512 | end 513 | endfunction 514 | 515 | protected task drive_ready(bit write_data_thread, bit ready); 516 | if (write_data_thread) begin 517 | vif.slave_cb.wready <= ready; 518 | end 519 | else begin 520 | vif.slave_cb.awready <= ready; 521 | end 522 | endtask 523 | 524 | protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item); 525 | vif.slave_cb.bvalid <= valid; 526 | if (valid) begin 527 | vif.slave_cb.bid <= item.get_id(); 528 | vif.slave_cb.bresp <= item.get_response_status(); 529 | end 530 | endtask 531 | 532 | protected function bit get_response_ready(); 533 | return vif.slave_cb.bready; 534 | endfunction 535 | 536 | `uvm_component_utils(tvip_axi_slave_write_driver) 537 | endclass 538 | 539 | class tvip_axi_slave_read_driver extends tvip_axi_slave_sub_driver; 540 | function new(string name = "tvip_axi_slave_read_driver", uvm_component parent = null); 541 | super.new(name, parent); 542 | write_component = 0; 543 | endfunction 544 | 545 | protected task reset_if(); 546 | vif.slave_cb.arready <= configuration.default_arready; 547 | vif.slave_cb.rvalid <= '0; 548 | vif.slave_cb.rid <= '0; 549 | vif.slave_cb.rresp <= tvip_axi_response'(0); 550 | vif.slave_cb.rdata <= '0; 551 | vif.slave_cb.rlast <= '0; 552 | endtask 553 | 554 | protected function bit get_request_valid(bit write_data_thread); 555 | return vif.slave_cb.arvalid; 556 | endfunction 557 | 558 | protected task drive_ready(bit write_data_thread, bit ready); 559 | vif.slave_cb.arready <= ready; 560 | endtask 561 | 562 | protected task drive_response(bit valid, tvip_axi_slave_driver_response_item item); 563 | vif.slave_cb.rvalid <= valid; 564 | if (valid) begin 565 | vif.slave_cb.rid <= item.get_id(); 566 | vif.slave_cb.rresp <= item.get_response_status(); 567 | vif.slave_cb.rdata <= item.get_data(); 568 | vif.slave_cb.rlast <= item.get_last(); 569 | end 570 | endtask 571 | 572 | protected function bit get_response_ready(); 573 | return vif.slave_cb.rready; 574 | endfunction 575 | 576 | `uvm_component_utils(tvip_axi_slave_read_driver) 577 | endclass 578 | 579 | class tvip_axi_slave_driver extends tvip_axi_driver_base #( 580 | .ITEM (tvip_axi_slave_item ), 581 | .WRITE_DRIVER (tvip_axi_slave_write_driver ), 582 | .READ_DRIVER (tvip_axi_slave_read_driver ) 583 | ); 584 | `tue_component_default_constructor(tvip_axi_slave_driver) 585 | `uvm_component_utils(tvip_axi_slave_driver) 586 | endclass 587 | `endif 588 | --------------------------------------------------------------------------------