├── sim ├── .gitignore ├── run_add.sh └── run_mul.sh ├── tools ├── .gitignore ├── install-ghdl.sh └── install-verilator.sh ├── src ├── verilog │ ├── .gitignore │ ├── ha.sv │ ├── mutex.sv │ ├── fa.sv │ ├── add.sv │ ├── mul.sv │ └── cla.sv ├── vhdl │ ├── .gitignore │ ├── ha.vhd │ ├── mutex.vhd │ ├── wire.vhd │ ├── fa.vhd │ ├── libs.vhd │ ├── add.vhd │ ├── cla.vhd │ ├── csa.vhd │ ├── mul.vhd │ └── cra.vhd ├── cpp │ ├── .gitignore │ ├── Makefile │ └── multiply_tree.cpp └── tb │ ├── verilog │ ├── test_multiply.sv │ └── test_adder.sv │ └── vhdl │ ├── test_multiply.vhd │ └── test_adder.vhd ├── Makefile ├── README.md └── LICENSE /sim/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !*.sh 3 | !*.diff 4 | !.gitignore 5 | -------------------------------------------------------------------------------- /tools/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !*.sh 3 | !*.diff 4 | !.gitignore 5 | -------------------------------------------------------------------------------- /src/verilog/.gitignore: -------------------------------------------------------------------------------- 1 | configure.sv 2 | dadda.sv 3 | wallace.sv 4 | -------------------------------------------------------------------------------- /src/vhdl/.gitignore: -------------------------------------------------------------------------------- 1 | configure.vhd 2 | dadda.vhd 3 | wallace.vhd 4 | -------------------------------------------------------------------------------- /src/cpp/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !Makefile 3 | !multiply_tree.cpp 4 | !.gitignore 5 | -------------------------------------------------------------------------------- /src/cpp/Makefile: -------------------------------------------------------------------------------- 1 | CXX = g++ 2 | OBJ = multiply_tree 3 | SRC = multiply_tree.cpp 4 | CFLAGS = -O3 5 | 6 | all: 7 | $(CXX) $(CFLAGS) -o $(OBJ) $(SRC) 8 | 9 | debug: 10 | $(CXX) -g -DDEBUG $(CFLAGS) -o $(OBJ) $(SRC) 11 | 12 | clean: 13 | rm -rf $(OBJ) *.vhd 14 | -------------------------------------------------------------------------------- /src/verilog/ha.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | module ha 4 | ( 5 | input logic [0 : 0] a, 6 | input logic [0 : 0] b, 7 | output logic [0 : 0] s, 8 | output logic [0 : 0] c 9 | ); 10 | timeunit 1ps; 11 | timeprecision 1ps; 12 | 13 | assign s = a ^ b; 14 | assign c = a & b; 15 | 16 | endmodule -------------------------------------------------------------------------------- /src/verilog/mutex.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | module mutex 4 | #( 5 | parameter SIZE = 4 6 | ) 7 | ( 8 | input logic [SIZE-1 : 0] data0, 9 | input logic [SIZE-1 : 0] data1, 10 | input logic [0 : 0] sel, 11 | output logic [SIZE-1 : 0] result 12 | ); 13 | timeunit 1ps; 14 | timeprecision 1ps; 15 | 16 | assign result = sel == 0 ? data0 : data1; 17 | 18 | endmodule -------------------------------------------------------------------------------- /src/vhdl/ha.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use work.all; 5 | 6 | entity ha is 7 | port( 8 | a : in std_logic; 9 | b : in std_logic; 10 | s : out std_logic; 11 | c : out std_logic 12 | ); 13 | end ha; 14 | 15 | architecture behavior of ha is 16 | 17 | begin 18 | 19 | s <= a xor b; 20 | c <= a and b; 21 | 22 | end architecture; 23 | -------------------------------------------------------------------------------- /tools/install-ghdl.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | 4 | sudo apt-get -y install git build-essential llvm-dev make gnat clang zlib1g-dev 5 | 6 | if [ -d "$BASEDIR/tools/ghdl" ]; then 7 | rm -rf $BASEDIR/tools/ghdl 8 | fi 9 | 10 | git clone https://github.com/ghdl/ghdl.git $BASEDIR/tools/ghdl 11 | 12 | cd $BASEDIR/tools/ghdl 13 | 14 | ./configure --with-llvm-config --prefix=/usr/local 15 | 16 | make -j$(nproc) 17 | sudo make install -------------------------------------------------------------------------------- /src/verilog/fa.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | module fa 4 | ( 5 | input logic [0 : 0] a, 6 | input logic [0 : 0] b, 7 | input logic [0 : 0] c_i, 8 | output logic [0 : 0] s, 9 | output logic [0 : 0] c_o 10 | ); 11 | timeunit 1ps; 12 | timeprecision 1ps; 13 | 14 | logic s_1,c_1,c_2; 15 | 16 | ha ha_1_comp (.a (a), .b(b), .s(s_1), .c(c_1)); 17 | ha ha_2_comp (.a (s_1), .b(c_i), .s(s), .c(c_2)); 18 | 19 | assign c_o = c_1 | c_2; 20 | 21 | endmodule -------------------------------------------------------------------------------- /src/vhdl/mutex.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.wire.all; 6 | 7 | entity mutex is 8 | generic( 9 | SIZE : natural := 1 10 | ); 11 | port( 12 | data0 : in std_logic_vector(SIZE-1 downto 0); 13 | data1 : in std_logic_vector(SIZE-1 downto 0); 14 | sel : in std_logic; 15 | result : out std_logic_vector(SIZE-1 downto 0) 16 | ); 17 | end mutex; 18 | 19 | architecture behavior of mutex is 20 | 21 | begin 22 | 23 | result <= data0 when sel = '0' else 24 | data1 when sel = '1'; 25 | 26 | end architecture; 27 | -------------------------------------------------------------------------------- /src/verilog/add.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | module add 4 | #( 5 | parameter XLEN = 32 6 | ) 7 | ( 8 | input logic [XLEN-1 : 0] data0, 9 | input logic [XLEN-1 : 0] data1, 10 | input logic [0 : 0] op, 11 | output logic [XLEN-1 : 0] result 12 | ); 13 | timeunit 1ps; 14 | timeprecision 1ps; 15 | 16 | logic [XLEN-1 : 0] data1_xor; 17 | logic [0 : 0] carry; 18 | 19 | assign data1_xor = data1 ^ {XLEN{op}}; 20 | 21 | cla #( 22 | .SIZE (XLEN) 23 | ) cla_comp 24 | ( 25 | .a (data0), 26 | .b (data1_xor), 27 | .c_in (op), 28 | .s (result), 29 | .c_out (carry) 30 | ); 31 | 32 | endmodule -------------------------------------------------------------------------------- /src/verilog/mul.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | module mul 4 | #( 5 | parameter XLEN = 32, 6 | parameter YLEN = 32, 7 | parameter TYP = 0 8 | ) 9 | ( 10 | input logic [XLEN-1 : 0] a, 11 | input logic [YLEN-1 : 0] b, 12 | output logic [XLEN+YLEN-1 : 0] c 13 | ); 14 | timeunit 1ps; 15 | timeprecision 1ps; 16 | 17 | logic [XLEN+YLEN-1 : 0] z0; 18 | logic [XLEN+YLEN-1 : 0] z1; 19 | 20 | generate 21 | if (TYP == 0) begin 22 | dadda dadda_comp(a,b,z0,z1); 23 | end else begin 24 | wallace wallace_comp(a,b,z0,z1); 25 | end 26 | endgenerate 27 | 28 | assign c = z0 + z1; 29 | 30 | endmodule -------------------------------------------------------------------------------- /tools/install-verilator.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | 4 | sudo apt-get -y install git help2man perl python3 make autoconf g++ flex bison ccache \ 5 | libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev \ 6 | zlib1g zlib1g-dev 7 | 8 | if [ -d "$BASEDIR/tools/verilator" ]; then 9 | rm -rf $BASEDIR/tools/verilator 10 | fi 11 | 12 | git clone https://github.com/verilator/verilator.git $BASEDIR/tools/verilator 13 | 14 | unset VERILATOR_ROOT 15 | 16 | cd $BASEDIR/tools/verilator 17 | 18 | git pull 19 | git checkout stable 20 | 21 | autoconf 22 | ./configure --prefix=/usr/local 23 | 24 | make -j$(nproc) 25 | sudo make install 26 | -------------------------------------------------------------------------------- /src/vhdl/wire.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.configure.all; 6 | 7 | package wire is 8 | 9 | type add_in_type is record 10 | data0 : std_logic_vector(XLEN-1 downto 0); 11 | data1 : std_logic_vector(XLEN-1 downto 0); 12 | op : std_logic; 13 | end record; 14 | 15 | type add_out_type is record 16 | result : std_logic_vector(XLEN-1 downto 0); 17 | end record; 18 | 19 | type mul_in_type is record 20 | a : std_logic_vector(XLEN-1 downto 0); 21 | b : std_logic_vector(YLEN-1 downto 0); 22 | end record; 23 | 24 | type mul_out_type is record 25 | c : std_logic_vector(XLEN+YLEN-1 downto 0); 26 | end record; 27 | 28 | end package; 29 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | default: all 2 | 3 | export GHDL ?= /usr/local/bin/ghdl 4 | export VERILATOR ?= /usr/local/bin/verilator 5 | export BASEDIR ?= $(shell dirname $(realpath $(firstword $(MAKEFILE_LIST)))) 6 | 7 | export MAXTIME ?= 1000# duration of simulation 8 | 9 | export N ?= 32# number of bits 10 | export M ?= 64# number of bits 11 | 12 | export VHDL ?= 0# 1 -> enable, 0 -> disable 13 | export VERILOG ?= 0# 1 -> enable, 0 -> disable 14 | 15 | export DADDA ?= 0# 1 -> enable, 0 -> disable 16 | export WALLACE ?= 0# 1 -> enable, 0 -> disable 17 | 18 | export ADD ?= 0# 1 -> enable, 0 -> disable 19 | export SUB ?= 0# 1 -> enable, 0 -> disable 20 | 21 | run_mul: 22 | sim/run_mul.sh 23 | 24 | run_add: 25 | sim/run_add.sh 26 | 27 | tool: 28 | tools/install-ghdl.sh 29 | tools/install-verilator.sh 30 | 31 | all: run_mul run_add 32 | -------------------------------------------------------------------------------- /src/vhdl/fa.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use work.all; 5 | 6 | entity fa is 7 | port( 8 | a : in std_logic; 9 | b : in std_logic; 10 | c_i : in std_logic; 11 | s : out std_logic; 12 | c_o : out std_logic; 13 | p : out std_logic; 14 | g : out std_logic 15 | ); 16 | end fa; 17 | 18 | architecture behavior of fa is 19 | 20 | signal s_1 : std_logic; 21 | signal c_1 : std_logic; 22 | signal c_2 : std_logic; 23 | 24 | component ha 25 | port( 26 | a : in std_logic; 27 | b : in std_logic; 28 | s : out std_logic; 29 | c : out std_logic 30 | ); 31 | end component; 32 | 33 | begin 34 | 35 | HA1 : ha port map(a => a, b => b, s => s_1, c => c_1); 36 | HA2 : ha port map(a => s_1, b => c_i, s => s, c => c_2); 37 | 38 | p <= s_1; 39 | g <= c_1; 40 | c_o <= c_1 or c_2; 41 | 42 | end architecture; 43 | -------------------------------------------------------------------------------- /src/vhdl/libs.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.wire.all; 6 | 7 | package libs is 8 | 9 | component ha is 10 | port( 11 | a : in std_logic; 12 | b : in std_logic; 13 | s : out std_logic; 14 | c : out std_logic 15 | ); 16 | end component; 17 | 18 | component fa is 19 | port( 20 | a : in std_logic; 21 | b : in std_logic; 22 | c_i : in std_logic; 23 | s : out std_logic; 24 | c_o : out std_logic; 25 | p : out std_logic; 26 | g : out std_logic 27 | ); 28 | end component; 29 | 30 | component mutex is 31 | generic( 32 | SIZE : natural := 1 33 | ); 34 | port( 35 | data0 : in std_logic_vector(SIZE-1 downto 0); 36 | data1 : in std_logic_vector(SIZE-1 downto 0); 37 | sel : in std_logic; 38 | result : out std_logic_vector(SIZE-1 downto 0) 39 | ); 40 | end component; 41 | 42 | end package; 43 | -------------------------------------------------------------------------------- /src/verilog/cla.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | module cla 4 | #( 5 | parameter SIZE = 4 6 | ) 7 | ( 8 | input logic [SIZE-1 : 0] a, 9 | input logic [SIZE-1 : 0] b, 10 | input logic [0 : 0] c_in, 11 | output logic [SIZE-1 : 0] s, 12 | output logic [0 : 0] c_out 13 | ); 14 | timeunit 1ps; 15 | timeprecision 1ps; 16 | 17 | /* verilator lint_off UNOPTFLAT */ 18 | 19 | genvar i; 20 | 21 | logic [SIZE-1 : 0] sum; 22 | logic [SIZE-1 : 0] c_g; 23 | logic [SIZE-1 : 0] c_p; 24 | logic [SIZE-1 : 0] c_i; 25 | 26 | assign sum = a ^ b; 27 | assign c_g = a & b; 28 | assign c_p = a | b; 29 | 30 | assign c_i[1] = c_g[0] | (c_p[0] & c_in); 31 | 32 | for (i = 1; i < SIZE-1; i++) begin 33 | assign c_i[i+1] = c_g[i] | (c_p[i] & c_i[i]); 34 | end 35 | 36 | assign c_out = c_g[SIZE-1] | (c_p[SIZE-1] & c_i[SIZE-1]); 37 | 38 | assign s[0] = sum[0] ^ c_in; 39 | assign s[SIZE-1:1] = sum[SIZE-1:1] ^ c_i[SIZE-1:1]; 40 | 41 | /* verilator lint_on UNOPTFLAT */ 42 | 43 | endmodule -------------------------------------------------------------------------------- /src/vhdl/add.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.wire.all; 6 | 7 | entity add is 8 | generic( 9 | XLEN : natural := 32 10 | ); 11 | port( 12 | add_i : in add_in_type; 13 | add_o : out add_out_type 14 | ); 15 | end add; 16 | 17 | architecture behavior of add is 18 | 19 | component cla 20 | generic( 21 | SIZE : natural := 4 22 | ); 23 | port( 24 | a : in std_logic_vector(SIZE-1 downto 0); 25 | b : in std_logic_vector(SIZE-1 downto 0); 26 | c_in : in std_logic; 27 | s : out std_logic_vector(SIZE-1 downto 0); 28 | c_out : out std_logic 29 | ); 30 | end component; 31 | 32 | signal data1_xor : std_logic_vector(XLEN-1 downto 0); 33 | 34 | begin 35 | 36 | for_generate : for i in 0 to XLEN-1 generate 37 | data1_xor(i) <= add_i.data1(i) xor add_i.op; 38 | end generate; 39 | 40 | cla_comp : cla 41 | generic map( 42 | SIZE => XLEN 43 | ) 44 | port map( 45 | a => add_i.data0, 46 | b => data1_xor, 47 | c_in => add_i.op, 48 | s => add_o.result 49 | ); 50 | 51 | end architecture; 52 | -------------------------------------------------------------------------------- /src/vhdl/cla.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.wire.all; 6 | 7 | entity cla is 8 | generic( 9 | SIZE : natural := 4 10 | ); 11 | port( 12 | a : in std_logic_vector(SIZE-1 downto 0); 13 | b : in std_logic_vector(SIZE-1 downto 0); 14 | c_in : in std_logic; 15 | s : out std_logic_vector(SIZE-1 downto 0); 16 | c_out : out std_logic 17 | ); 18 | end cla; 19 | 20 | architecture behavior of cla is 21 | 22 | signal sum : std_logic_vector(SIZE-1 downto 0); 23 | signal c_g : std_logic_vector(SIZE-1 downto 0); 24 | signal c_p : std_logic_vector(SIZE-1 downto 0); 25 | signal c_i : std_logic_vector(SIZE-1 downto 1); 26 | 27 | begin 28 | 29 | sum <= a xor b; 30 | c_g <= a and b; 31 | c_p <= a or b; 32 | 33 | c_i(1) <= c_g(0) or (c_p(0) and c_in); 34 | 35 | for_generate : for i in 1 to SIZE-2 generate 36 | c_i(i+1) <= c_g(i) or (c_p(i) and c_i(i)); 37 | end generate; 38 | 39 | c_out <= c_g(SIZE-1) or (c_p(SIZE-1) and c_i(SIZE-1)); 40 | 41 | s(0) <= sum(0) xor c_in; 42 | s(SIZE-1 downto 1) <= sum(SIZE-1 downto 1) xor c_i(SIZE-1 downto 1); 43 | 44 | end architecture; 45 | -------------------------------------------------------------------------------- /src/vhdl/csa.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.wire.all; 6 | 7 | entity csa is 8 | generic( 9 | XLEN : natural := 32; 10 | STEP : natural := XLEN/4; 11 | SIZE : natural := 4 12 | ); 13 | port( 14 | a : in std_logic_vector(XLEN-1 downto 0); 15 | b : in std_logic_vector(XLEN-1 downto 0); 16 | c_in : in std_logic; 17 | s : out std_logic_vector(XLEN-1 downto 0); 18 | c_out : out std_logic 19 | ); 20 | end csa; 21 | 22 | architecture behavior of csa is 23 | 24 | component cra is 25 | generic( 26 | SIZE : natural := 4 27 | ); 28 | port( 29 | a : in std_logic_vector(SIZE-1 downto 0); 30 | b : in std_logic_vector(SIZE-1 downto 0); 31 | c_in : in std_logic; 32 | s : out std_logic_vector(SIZE-1 downto 0); 33 | c_out : out std_logic 34 | ); 35 | end component; 36 | 37 | signal cc : std_logic_vector(STEP downto 0); 38 | 39 | begin 40 | 41 | cc(0) <= c_in; 42 | 43 | cra_for : for i in 0 to STEP-1 generate 44 | cra_comp : cra 45 | generic map( 46 | SIZE => 4 47 | ) 48 | port map( 49 | a => a(((i+1)*SIZE-1) downto (i*4)), 50 | b => b(((i+1)*SIZE-1) downto (i*4)), 51 | c_in => cc(i), 52 | s => s(((i+1)*SIZE-1) downto (i*4)), 53 | c_out => cc(i+1) 54 | ); 55 | end generate cra_for; 56 | 57 | c_out <= cc(STEP); 58 | 59 | end architecture; 60 | -------------------------------------------------------------------------------- /src/vhdl/mul.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.wire.all; 6 | 7 | entity mul is 8 | generic( 9 | XLEN : natural := 32; 10 | YLEN : natural := 32; 11 | TYP : std_logic := '0' 12 | ); 13 | port( 14 | mul_i : in mul_in_type; 15 | mul_o : out mul_out_type 16 | ); 17 | end mul; 18 | 19 | architecture behavior of mul is 20 | 21 | component dadda 22 | port( 23 | x : in std_logic_vector(XLEN-1 downto 0); 24 | y : in std_logic_vector(YLEN-1 downto 0); 25 | z0 : out std_logic_vector(XLEN+YLEN-1 downto 0); 26 | z1 : out std_logic_vector(XLEN+YLEN-1 downto 0) 27 | ); 28 | end component; 29 | 30 | component wallace 31 | port( 32 | x : in std_logic_vector(XLEN-1 downto 0); 33 | y : in std_logic_vector(YLEN-1 downto 0); 34 | z0 : out std_logic_vector(XLEN+YLEN-1 downto 0); 35 | z1 : out std_logic_vector(XLEN+YLEN-1 downto 0) 36 | ); 37 | end component; 38 | 39 | signal a : std_logic_vector(XLEN-1 downto 0); 40 | signal b : std_logic_vector(YLEN-1 downto 0); 41 | 42 | signal z0 : std_logic_vector(XLEN+YLEN-1 downto 0); 43 | signal z1 : std_logic_vector(XLEN+YLEN-1 downto 0); 44 | 45 | begin 46 | 47 | a <= mul_i.a; 48 | b <= mul_i.b; 49 | 50 | DADDA_TREE : if TYP = '0' generate 51 | dadda_comp : dadda port map(a,b,z0,z1); 52 | end generate DADDA_TREE; 53 | WALLACE_TREE : if TYP = '1' generate 54 | wallace_comp : wallace port map(a,b,z0,z1); 55 | end generate WALLACE_TREE; 56 | 57 | mul_o.c <= std_logic_vector(unsigned(z0)+unsigned(z1)); 58 | 59 | 60 | end architecture; 61 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Tree Multiplier Generator for VHDL and SystemVerilog 2 | 3 | This tool generates **Wallace** and **Dadda** tree multiplier in hardware description language **VHDL** and **SystemVerilog**. 4 | 5 | ## Tools 6 | 7 | The installation scripts of necessary tools are located in directory **tools**. These scripts need **root** permission in order to install packages and tools for simulation. 8 | 9 | ```console 10 | make tool 11 | ``` 12 | 13 | ## Design Files 14 | 15 | After running one of below commands the automatically generated design files are located in **src/verilog** and **src/vhdl**. 16 | 17 | ## Options 18 | 19 | **N**, **M** are for dimension of input vectors and **MAXTIME** is for number of iterations. 20 | 21 | ## Multiplication 22 | 23 | ### Dadda Tree 24 | 25 | #### SystemVerilog 26 | 27 | ```console 28 | make run_mul DADDA=1 VERILOG=1 N=32 M=64 MAXTIME=1000 29 | ``` 30 | 31 | #### VHDL 32 | 33 | ```console 34 | make run_mul DADDA=1 VHDL=1 N=32 M=64 MAXTIME=1000 35 | ``` 36 | 37 | ### Wallace Tree 38 | 39 | #### SystemVerilog 40 | 41 | ```console 42 | make run_mul WALLACE=1 VERILOG=1 N=32 M=64 MAXTIME=1000 43 | ``` 44 | 45 | #### VHDL 46 | 47 | ```console 48 | make run_mul WALLACE=1 VHDL=1 N=32 M=64 MAXTIME=1000 49 | ``` 50 | 51 | ## Addition 52 | 53 | #### SystemVerilog 54 | 55 | ```console 56 | make run_add ADD=1 VERILOG=1 N=32 MAXTIME=1000 57 | ``` 58 | 59 | #### VHDL 60 | 61 | ```console 62 | make run_add ADD=1 VHDL=1 N=32 MAXTIME=1000 63 | ``` 64 | 65 | ## Subtruction 66 | 67 | #### SystemVerilog 68 | 69 | ```console 70 | make run_add SUB=1 VERILOG=1 N=32 MAXTIME=1000 71 | ``` 72 | 73 | #### VHDL 74 | 75 | ```console 76 | make run_add SUB=1 VHDL=1 N=32 MAXTIME=1000 77 | ``` 78 | -------------------------------------------------------------------------------- /src/vhdl/cra.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | use work.wire.all; 6 | 7 | entity cra is 8 | generic( 9 | SIZE : natural := 4 10 | ); 11 | port( 12 | a : in std_logic_vector(SIZE-1 downto 0); 13 | b : in std_logic_vector(SIZE-1 downto 0); 14 | c_in : in std_logic; 15 | s : out std_logic_vector(SIZE-1 downto 0); 16 | c_out : out std_logic 17 | ); 18 | end cra; 19 | 20 | architecture behavior of cra is 21 | 22 | component fa is 23 | port( 24 | a : in std_logic; 25 | b : in std_logic; 26 | c_i : in std_logic; 27 | s : out std_logic; 28 | c_o : out std_logic; 29 | p : out std_logic; 30 | g : out std_logic 31 | ); 32 | end component; 33 | 34 | component mutex is 35 | generic( 36 | SIZE : natural := 1 37 | ); 38 | port( 39 | data0 : in std_logic_vector(SIZE-1 downto 0); 40 | data1 : in std_logic_vector(SIZE-1 downto 0); 41 | sel : in std_logic; 42 | result : out std_logic_vector(SIZE-1 downto 0) 43 | ); 44 | end component; 45 | 46 | signal cc : std_logic_vector(SIZE downto 0); 47 | signal p : std_logic_vector(SIZE-1 downto 0); 48 | signal sel : std_logic; 49 | 50 | begin 51 | 52 | cc(0) <= c_in; 53 | 54 | fa_for : for i in 0 to SIZE-1 generate 55 | fa_comp : fa 56 | port map( 57 | a => a(i), 58 | b => b(i), 59 | c_i => cc(i), 60 | s => s(i), 61 | c_o => cc(i+1), 62 | p => p(i) 63 | ); 64 | end generate fa_for; 65 | 66 | sel <= and(p); 67 | 68 | mutex_comp : mutex 69 | generic map( 70 | SIZE => 1 71 | ) 72 | port map( 73 | data0(0) => cc(SIZE), 74 | data1(0) => c_in, 75 | sel => sel, 76 | result(0) => c_out 77 | ); 78 | 79 | end architecture; 80 | -------------------------------------------------------------------------------- /src/tb/verilog/test_multiply.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | class rng; 4 | rand bit [XLEN-1 : 0] a; 5 | rand bit [YLEN-1 : 0] b; 6 | endclass 7 | 8 | module test_multiply(); 9 | timeunit 1ps; 10 | timeprecision 1ps; 11 | 12 | task check( 13 | input logic [XLEN-1 : 0] aa, 14 | input logic [YLEN-1 : 0] bb, 15 | input logic [XLEN+YLEN-1 : 0] pp, 16 | input logic [XLEN+YLEN-1 : 0] qq, 17 | input logic [XLEN+YLEN-1 : 0] rr, 18 | input logic [0 : 0] ss 19 | ); 20 | begin 21 | if (ss == 0) begin 22 | $write("%c[1;32m",8'h1B); 23 | $display("TEST SUCCEEDED"); 24 | $write("%c[0m",8'h1B); 25 | end else begin 26 | $write("%c[1;31m",8'h1B); 27 | $display("TEST FAILED"); 28 | $write("%c[0m",8'h1B); 29 | end 30 | $display("%h * %h = %h ^ %h == %h",aa,bb,pp,qq,rr); 31 | end 32 | endtask 33 | 34 | logic clock = 0; 35 | 36 | logic op; 37 | 38 | logic [XLEN-1 : 0] a; 39 | logic [YLEN-1 : 0] b; 40 | logic [XLEN+YLEN-1 : 0] p; 41 | logic [XLEN+YLEN-1 : 0] q; 42 | logic [XLEN+YLEN-1 : 0] r; 43 | logic [0 : 0] s; 44 | 45 | rng gen; 46 | 47 | initial begin 48 | gen = new(); 49 | gen.srandom(SEED); 50 | end 51 | 52 | initial begin 53 | if (TYP == 0) begin 54 | $dumpfile("dadda.vcd"); 55 | end else begin 56 | $dumpfile("wallace.vcd"); 57 | end 58 | $dumpvars(0,test_multiply); 59 | end 60 | 61 | initial begin 62 | #(MAXTIME) $finish; 63 | end 64 | 65 | always begin 66 | #1 clock = ~clock; 67 | end 68 | 69 | mul #( 70 | .XLEN (XLEN), 71 | .YLEN (YLEN), 72 | .TYP (TYP) 73 | ) mul_comp 74 | ( 75 | .a (a), 76 | .b (b), 77 | .c (p) 78 | ); 79 | 80 | assign q = a * b; 81 | assign r = p ^ q; 82 | assign s = |(r); 83 | 84 | always begin 85 | /* verilator lint_off IGNOREDRETURN */ 86 | gen.randomize(); 87 | a = gen.a; 88 | b = gen.b; 89 | @(posedge clock); 90 | check(a,b,p,q,r,s); 91 | end 92 | 93 | endmodule -------------------------------------------------------------------------------- /src/tb/verilog/test_adder.sv: -------------------------------------------------------------------------------- 1 | import configure::*; 2 | 3 | class rng; 4 | rand bit [XLEN-1 : 0] a; 5 | rand bit [XLEN-1 : 0] b; 6 | endclass 7 | 8 | module test_adder(); 9 | timeunit 1ps; 10 | timeprecision 1ps; 11 | 12 | task check( 13 | input logic [XLEN-1 : 0] aa, 14 | input logic [XLEN-1 : 0] bb, 15 | input logic [XLEN-1 : 0] pp, 16 | input logic [XLEN-1 : 0] qq, 17 | input logic [XLEN-1 : 0] rr, 18 | input logic [0 : 0] ss, 19 | input logic [0 : 0] tt 20 | ); 21 | begin 22 | if (ss == 0) begin 23 | $write("%c[1;32m",8'h1B); 24 | $display("TEST SUCCEEDED"); 25 | $write("%c[0m",8'h1B); 26 | end else begin 27 | $write("%c[1;31m",8'h1B); 28 | $display("TEST FAILED"); 29 | $write("%c[0m",8'h1B); 30 | end 31 | if (tt == 0) begin 32 | $display("%h + %h = %h ^ %h == %h",aa,bb,pp,qq,rr); 33 | end else begin 34 | $display("%h - %h = %h ^ %h == %h",aa,bb,pp,qq,rr); 35 | end 36 | end 37 | endtask 38 | 39 | logic clock = 0; 40 | 41 | logic op; 42 | 43 | logic [XLEN-1 : 0] a; 44 | logic [XLEN-1 : 0] b; 45 | logic [XLEN-1 : 0] p; 46 | logic [XLEN-1 : 0] q; 47 | logic [XLEN-1 : 0] r; 48 | logic [0 : 0] s; 49 | 50 | rng gen; 51 | 52 | initial begin 53 | gen = new(); 54 | gen.srandom(SEED); 55 | end 56 | 57 | initial begin 58 | if (TYP == 0) begin 59 | $dumpfile("add.vcd"); 60 | end else begin 61 | $dumpfile("sub.vcd"); 62 | end 63 | $dumpvars(0,test_adder); 64 | end 65 | 66 | initial begin 67 | #(MAXTIME) $finish; 68 | end 69 | 70 | always begin 71 | #1 clock = ~clock; 72 | end 73 | 74 | add #( 75 | .XLEN (XLEN) 76 | ) add_comp 77 | ( 78 | .data0 (a), 79 | .data1 (b), 80 | .op (op), 81 | .result (p) 82 | ); 83 | 84 | assign op = TYP == 0 ? 0 : 1; 85 | assign q = TYP == 0 ? a + b : a - b; 86 | assign r = p ^ q; 87 | assign s = |(r); 88 | 89 | always begin 90 | /* verilator lint_off IGNOREDRETURN */ 91 | gen.randomize(); 92 | a = gen.a; 93 | b = gen.b; 94 | @(posedge clock); 95 | check(a,b,p,q,r,s,op); 96 | end 97 | 98 | endmodule -------------------------------------------------------------------------------- /src/tb/vhdl/test_multiply.vhd: -------------------------------------------------------------------------------- 1 | -- args: --std=08 --ieee=synopsys 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | use ieee.numeric_std.all; 6 | use ieee.std_logic_textio.all; 7 | use ieee.math_real.all; 8 | 9 | use work.configure.all; 10 | use work.wire.all; 11 | 12 | library std; 13 | use std.textio.all; 14 | use std.env.all; 15 | 16 | entity test_multiply is 17 | generic( 18 | XLEN : natural := XLEN; 19 | YLEN : natural := YLEN; 20 | TYP : std_logic := TYP 21 | ); 22 | end entity test_multiply; 23 | 24 | architecture behavior of test_multiply is 25 | 26 | impure function rand_slv(len : integer; seed : integer) return std_logic_vector is 27 | variable r : real; 28 | variable s : integer; 29 | variable slv : std_logic_vector(len - 1 downto 0); 30 | begin 31 | s := seed; 32 | for i in slv'range loop 33 | uniform(s, s, r); 34 | slv(i) := '1' when r > 0.5 else '0'; 35 | end loop; 36 | return slv; 37 | end function; 38 | 39 | procedure print( 40 | msg : in string) is 41 | variable buf : line; 42 | begin 43 | write(buf, msg); 44 | writeline(output, buf); 45 | end procedure print; 46 | 47 | signal seed0 : integer := SEED; 48 | signal seed1 : integer := SEED; 49 | 50 | signal reset : std_logic := '0'; 51 | signal clock : std_logic := '0'; 52 | 53 | constant empty_a : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 54 | constant empty_b : std_logic_vector(YLEN-1 downto 0) := (others => '0'); 55 | 56 | signal a : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 57 | signal b : std_logic_vector(YLEN-1 downto 0) := (others => '0'); 58 | signal p : std_logic_vector(XLEN+YLEN-1 downto 0) := (others => '0'); 59 | signal q : std_logic_vector(XLEN+YLEN-1 downto 0) := (others => '0'); 60 | signal r : std_logic_vector(XLEN+YLEN-1 downto 0) := (others => '0'); 61 | signal s : std_logic := '0'; 62 | 63 | component mul 64 | generic( 65 | XLEN : natural := 32; 66 | YLEN : natural := 32; 67 | TYP : std_logic := '0' 68 | ); 69 | port( 70 | mul_i : in mul_in_type; 71 | mul_o : out mul_out_type 72 | ); 73 | end component; 74 | 75 | procedure check( 76 | aa : in std_logic_vector(XLEN-1 downto 0); 77 | bb : in std_logic_vector(YLEN-1 downto 0); 78 | pp : in std_logic_vector(XLEN+YLEN-1 downto 0); 79 | qq : in std_logic_vector(XLEN+YLEN-1 downto 0); 80 | rr : in std_logic_vector(XLEN+YLEN-1 downto 0); 81 | ss : in std_logic) is 82 | variable buf : line; 83 | begin 84 | if ss = '0' then 85 | print(character'val(27) & "[1;32m" & "TEST SUCCEEDED" & character'val(27) & "[0m"); 86 | else 87 | print(character'val(27) & "[1;31m" & "TEST FAILED" & character'val(27) & "[0m"); 88 | end if; 89 | print(to_hstring(aa) & " * " & to_hstring(bb) & " = " & to_hstring(pp) & " ^ " & to_hstring(qq) & " == " & to_hstring(rr)); 90 | end procedure check; 91 | 92 | begin 93 | 94 | reset <= '1' after 10 ps; 95 | clock <= not clock after 1 ps; 96 | 97 | process(reset, clock) 98 | 99 | begin 100 | 101 | if rising_edge(clock) then 102 | 103 | if reset = '0' then 104 | 105 | a <= empty_a; 106 | b <= empty_b; 107 | 108 | else 109 | 110 | a <= rand_slv(XLEN,seed0); 111 | b <= rand_slv(YLEN,seed1); 112 | 113 | seed0 <= seed0-1; 114 | seed1 <= seed1+1; 115 | 116 | end if; 117 | 118 | end if; 119 | 120 | end process; 121 | 122 | mul_comp : mul 123 | generic map( 124 | XLEN => XLEN, 125 | YLEN => YLEN, 126 | TYP => TYP 127 | ) 128 | port map( 129 | mul_i.a => a, 130 | mul_i.b => b, 131 | mul_o.c => p 132 | ); 133 | 134 | q <= std_logic_vector(unsigned(a)*unsigned(b)); 135 | r <= p xor q; 136 | s <= or(r); 137 | 138 | process(clock) 139 | 140 | begin 141 | 142 | if rising_edge(clock) then 143 | 144 | check(a,b,p,q,r,s); 145 | 146 | end if; 147 | 148 | end process; 149 | 150 | end architecture; 151 | -------------------------------------------------------------------------------- /src/tb/vhdl/test_adder.vhd: -------------------------------------------------------------------------------- 1 | -- args: --std=08 --ieee=synopsys 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | use ieee.numeric_std.all; 6 | use ieee.std_logic_textio.all; 7 | use ieee.math_real.all; 8 | 9 | use work.configure.all; 10 | use work.wire.all; 11 | 12 | library std; 13 | use std.textio.all; 14 | use std.env.all; 15 | 16 | entity test_adder is 17 | generic( 18 | XLEN : natural := XLEN; 19 | TYP : std_logic := TYP 20 | ); 21 | end entity test_adder; 22 | 23 | architecture behavior of test_adder is 24 | 25 | impure function rand_slv(len : integer; seed : integer) return std_logic_vector is 26 | variable r : real; 27 | variable s : integer; 28 | variable slv : std_logic_vector(len - 1 downto 0); 29 | begin 30 | s := seed; 31 | for i in slv'range loop 32 | uniform(s, s, r); 33 | slv(i) := '1' when r > 0.5 else '0'; 34 | end loop; 35 | return slv; 36 | end function; 37 | 38 | procedure print( 39 | msg : in string) is 40 | variable buf : line; 41 | begin 42 | write(buf, msg); 43 | writeline(output, buf); 44 | end procedure print; 45 | 46 | signal seed0 : integer := SEED; 47 | signal seed1 : integer := SEED; 48 | 49 | signal reset : std_logic := '0'; 50 | signal clock : std_logic := '0'; 51 | 52 | signal op : std_logic; 53 | 54 | constant empty : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 55 | 56 | signal a : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 57 | signal b : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 58 | signal p : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 59 | signal q : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 60 | signal r : std_logic_vector(XLEN-1 downto 0) := (others => '0'); 61 | signal s : std_logic := '0'; 62 | 63 | component add 64 | generic( 65 | XLEN : natural := 32 66 | ); 67 | port( 68 | add_i : in add_in_type; 69 | add_o : out add_out_type 70 | ); 71 | end component; 72 | 73 | procedure check( 74 | aa : in std_logic_vector(XLEN-1 downto 0); 75 | bb : in std_logic_vector(XLEN-1 downto 0); 76 | pp : in std_logic_vector(XLEN-1 downto 0); 77 | qq : in std_logic_vector(XLEN-1 downto 0); 78 | rr : in std_logic_vector(XLEN-1 downto 0); 79 | ss : in std_logic; 80 | tt : in std_logic) is 81 | variable buf : line; 82 | begin 83 | if ss = '0' then 84 | print(character'val(27) & "[1;32m" & "TEST SUCCEEDED" & character'val(27) & "[0m"); 85 | else 86 | print(character'val(27) & "[1;31m" & "TEST FAILED" & character'val(27) & "[0m"); 87 | end if; 88 | if tt = '0' then 89 | print(to_hstring(aa) & " + " & to_hstring(bb) & " = " & to_hstring(pp) & " ^ " & to_hstring(qq) & " == " & to_hstring(rr)); 90 | else 91 | print(to_hstring(aa) & " - " & to_hstring(bb) & " = " & to_hstring(pp) & " ^ " & to_hstring(qq) & " == " & to_hstring(rr)); 92 | end if; 93 | end procedure check; 94 | 95 | begin 96 | 97 | reset <= '1' after 10 ps; 98 | clock <= not clock after 1 ps; 99 | 100 | process(reset, clock) 101 | 102 | begin 103 | 104 | if rising_edge(clock) then 105 | 106 | if reset = '0' then 107 | 108 | a <= empty; 109 | b <= empty; 110 | 111 | else 112 | 113 | a <= rand_slv(XLEN,seed0); 114 | b <= rand_slv(XLEN,seed1); 115 | 116 | seed0 <= seed0-1; 117 | seed1 <= seed1+1; 118 | 119 | end if; 120 | 121 | end if; 122 | 123 | end process; 124 | 125 | add_comp : add 126 | generic map( 127 | XLEN => XLEN 128 | ) 129 | port map( 130 | add_i.data0 => a, 131 | add_i.data1 => b, 132 | add_i.op => TYP, 133 | add_o.result => p 134 | ); 135 | 136 | op <= '0' when TYP = '0' else '1'; 137 | q <= std_logic_vector(unsigned(a)+unsigned(b)) when TYP = '0' else std_logic_vector(unsigned(a)-unsigned(b)); 138 | r <= p xor q; 139 | s <= or(r); 140 | 141 | process(clock) 142 | 143 | begin 144 | 145 | if rising_edge(clock) then 146 | 147 | check(a,b,p,q,r,s,op); 148 | 149 | end if; 150 | 151 | end process; 152 | 153 | end architecture; 154 | -------------------------------------------------------------------------------- /sim/run_add.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | if [ -d "$BASEDIR/sim/work" ]; then 4 | rm -rf $BASEDIR/sim/work 5 | fi 6 | 7 | mkdir $BASEDIR/sim/work 8 | 9 | if [ "$VHDL" = "1" ] 10 | then 11 | 12 | ANALYS="$GHDL -a --std=08" 13 | ELABOR="$GHDL -e --std=08" 14 | SIMULA="$GHDL -r --std=08" 15 | 16 | TIME=$(date +%s) 17 | 18 | if [ "$ADD" = "1" ] 19 | then 20 | 21 | cd $BASEDIR/sim/work 22 | 23 | if [ -e "configure.vhd" ] 24 | then 25 | rm configure.vhd 26 | fi 27 | 28 | echo "library ieee;" >> configure.vhd 29 | echo "use ieee.std_logic_1164.all;" >> configure.vhd 30 | echo "use ieee.numeric_std.all;" >> configure.vhd 31 | echo "" >> configure.vhd 32 | echo "package configure is" >> configure.vhd 33 | echo " constant XLEN : integer := "$N";" >> configure.vhd 34 | echo " constant YLEN : integer := "$M";" >> configure.vhd 35 | echo " constant SEED : integer := "$TIME";" >> configure.vhd 36 | echo " constant TYP : std_logic := '"0"';" >> configure.vhd 37 | echo "end package;" >> configure.vhd 38 | 39 | mv configure.vhd $BASEDIR/src/vhdl/ 40 | 41 | $ANALYS $BASEDIR/src/vhdl/configure.vhd 42 | 43 | $ANALYS $BASEDIR/src/vhdl/wire.vhd 44 | $ANALYS $BASEDIR/src/vhdl/libs.vhd 45 | $ANALYS $BASEDIR/src/vhdl/mutex.vhd 46 | 47 | $ANALYS $BASEDIR/src/vhdl/ha.vhd 48 | $ANALYS $BASEDIR/src/vhdl/fa.vhd 49 | $ANALYS $BASEDIR/src/vhdl/cla.vhd 50 | $ANALYS $BASEDIR/src/vhdl/cra.vhd 51 | $ANALYS $BASEDIR/src/vhdl/csa.vhd 52 | $ANALYS $BASEDIR/src/vhdl/add.vhd 53 | 54 | $ANALYS $BASEDIR/src/tb/vhdl/test_adder.vhd 55 | 56 | $ELABOR test_adder 57 | $SIMULA test_adder --stop-time=${MAXTIME}ps --wave=add.ghw 58 | 59 | fi 60 | 61 | if [ "$SUB" = "1" ] 62 | then 63 | 64 | cd $BASEDIR/sim/work 65 | 66 | if [ -e "configure.vhd" ] 67 | then 68 | rm configure.vhd 69 | fi 70 | 71 | echo "library ieee;" >> configure.vhd 72 | echo "use ieee.std_logic_1164.all;" >> configure.vhd 73 | echo "use ieee.numeric_std.all;" >> configure.vhd 74 | echo "" >> configure.vhd 75 | echo "package configure is" >> configure.vhd 76 | echo " constant XLEN : integer := "$N";" >> configure.vhd 77 | echo " constant YLEN : integer := "$M";" >> configure.vhd 78 | echo " constant SEED : integer := "$TIME";" >> configure.vhd 79 | echo " constant TYP : std_logic := '"1"';" >> configure.vhd 80 | echo "end package;" >> configure.vhd 81 | 82 | mv configure.vhd $BASEDIR/src/vhdl/ 83 | 84 | $ANALYS $BASEDIR/src/vhdl/configure.vhd 85 | 86 | $ANALYS $BASEDIR/src/vhdl/wire.vhd 87 | $ANALYS $BASEDIR/src/vhdl/libs.vhd 88 | $ANALYS $BASEDIR/src/vhdl/mutex.vhd 89 | 90 | $ANALYS $BASEDIR/src/vhdl/ha.vhd 91 | $ANALYS $BASEDIR/src/vhdl/fa.vhd 92 | $ANALYS $BASEDIR/src/vhdl/cla.vhd 93 | $ANALYS $BASEDIR/src/vhdl/cra.vhd 94 | $ANALYS $BASEDIR/src/vhdl/csa.vhd 95 | $ANALYS $BASEDIR/src/vhdl/add.vhd 96 | 97 | $ANALYS $BASEDIR/src/tb/vhdl/test_adder.vhd 98 | 99 | $ELABOR test_adder 100 | $SIMULA test_adder --stop-time=${MAXTIME}ps --wave=sub.ghw 101 | 102 | fi 103 | 104 | fi 105 | 106 | cd $BASEDIR/src/cpp 107 | 108 | if [ "$VERILOG" = "1" ] 109 | then 110 | 111 | TIME=$(date +%s) 112 | 113 | if [ "$ADD" = "1" ] 114 | then 115 | 116 | cd $BASEDIR/sim/work 117 | 118 | if [ -e "configure.sv" ] 119 | then 120 | rm configure.sv 121 | fi 122 | 123 | echo "package configure;" >> configure.sv 124 | echo " timeunit 1ps;" >> configure.sv 125 | echo " timeprecision 1ps;" >> configure.sv 126 | echo "" >> configure.sv 127 | echo " parameter XLEN = "$N";" >> configure.sv 128 | echo " parameter YLEN = "$M";" >> configure.sv 129 | echo " integer MAXTIME = "$MAXTIME";" >> configure.sv 130 | echo " integer SEED = "$TIME";" >> configure.sv 131 | echo " logic TYP = "0";" >> configure.sv 132 | echo "endpackage" >> configure.sv 133 | 134 | mv configure.sv $BASEDIR/src/verilog/ 135 | 136 | $VERILATOR --binary --trace --trace-structs --top-module test_adder \ 137 | $BASEDIR/src/verilog/configure.sv \ 138 | $BASEDIR/src/verilog/mutex.sv \ 139 | $BASEDIR/src/verilog/ha.sv \ 140 | $BASEDIR/src/verilog/fa.sv \ 141 | $BASEDIR/src/verilog/cla.sv \ 142 | $BASEDIR/src/verilog/add.sv \ 143 | $BASEDIR/src/tb/verilog/test_adder.sv 2>&1 > /dev/null 144 | 145 | make -s -j -C obj_dir/ -f Vtest_adder.mk Vtest_adder 146 | 147 | obj_dir/Vtest_adder 148 | 149 | fi 150 | 151 | if [ "$SUB" = "1" ] 152 | then 153 | 154 | cd $BASEDIR/sim/work 155 | 156 | if [ -e "configure.sv" ] 157 | then 158 | rm configure.sv 159 | fi 160 | 161 | echo "package configure;" >> configure.sv 162 | echo " timeunit 1ps;" >> configure.sv 163 | echo " timeprecision 1ps;" >> configure.sv 164 | echo "" >> configure.sv 165 | echo " parameter XLEN = "$N";" >> configure.sv 166 | echo " parameter YLEN = "$M";" >> configure.sv 167 | echo " integer MAXTIME = "$MAXTIME";" >> configure.sv 168 | echo " integer SEED = "$TIME";" >> configure.sv 169 | echo " logic TYP = "1";" >> configure.sv 170 | echo "endpackage" >> configure.sv 171 | 172 | mv configure.sv $BASEDIR/src/verilog/ 173 | 174 | $VERILATOR --binary --trace --trace-structs --top-module test_adder \ 175 | $BASEDIR/src/verilog/configure.sv \ 176 | $BASEDIR/src/verilog/mutex.sv \ 177 | $BASEDIR/src/verilog/ha.sv \ 178 | $BASEDIR/src/verilog/fa.sv \ 179 | $BASEDIR/src/verilog/cla.sv \ 180 | $BASEDIR/src/verilog/add.sv \ 181 | $BASEDIR/src/tb/verilog/test_adder.sv 2>&1 > /dev/null 182 | 183 | make -s -j -C obj_dir/ -f Vtest_adder.mk Vtest_adder 184 | 185 | obj_dir/Vtest_adder 186 | 187 | fi 188 | 189 | fi -------------------------------------------------------------------------------- /sim/run_mul.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | if [ -d "$BASEDIR/sim/work" ]; then 4 | rm -rf $BASEDIR/sim/work 5 | fi 6 | 7 | mkdir $BASEDIR/sim/work 8 | 9 | cd $BASEDIR/src/cpp 10 | make clean 11 | make 12 | 13 | if [ "$VHDL" = "1" ] 14 | then 15 | 16 | TIME=$(date +%s) 17 | 18 | ./multiply_tree dadda $N $M 19 | ./multiply_tree wallace $N $M 20 | mv dadda.vhd $BASEDIR/src/vhdl/ 21 | mv wallace.vhd $BASEDIR/src/vhdl/ 22 | 23 | ANALYS="$GHDL -a --std=08" 24 | ELABOR="$GHDL -e --std=08" 25 | SIMULA="$GHDL -r --std=08" 26 | 27 | if [ "$DADDA" = "1" ] 28 | then 29 | 30 | cd $BASEDIR/sim/work 31 | 32 | if [ -e "configure.vhd" ] 33 | then 34 | rm configure.vhd 35 | fi 36 | 37 | echo "library ieee;" >> configure.vhd 38 | echo "use ieee.std_logic_1164.all;" >> configure.vhd 39 | echo "use ieee.numeric_std.all;" >> configure.vhd 40 | echo "" >> configure.vhd 41 | echo "package configure is" >> configure.vhd 42 | echo " constant XLEN : integer := "$N";" >> configure.vhd 43 | echo " constant YLEN : integer := "$M";" >> configure.vhd 44 | echo " constant SEED : integer := "$TIME";" >> configure.vhd 45 | echo " constant TYP : std_logic := '"0"';" >> configure.vhd 46 | echo "end package;" >> configure.vhd 47 | 48 | mv configure.vhd $BASEDIR/src/vhdl/ 49 | 50 | $ANALYS $BASEDIR/src/vhdl/configure.vhd 51 | 52 | $ANALYS $BASEDIR/src/vhdl/wire.vhd 53 | $ANALYS $BASEDIR/src/vhdl/libs.vhd 54 | $ANALYS $BASEDIR/src/vhdl/mutex.vhd 55 | 56 | $ANALYS $BASEDIR/src/vhdl/ha.vhd 57 | $ANALYS $BASEDIR/src/vhdl/fa.vhd 58 | 59 | $ANALYS $BASEDIR/src/vhdl/dadda.vhd 60 | $ANALYS $BASEDIR/src/vhdl/wallace.vhd 61 | $ANALYS $BASEDIR/src/vhdl/mul.vhd 62 | 63 | $ANALYS $BASEDIR/src/tb/vhdl/test_multiply.vhd 64 | 65 | $ELABOR test_multiply 66 | $SIMULA test_multiply --stop-time=${MAXTIME}ps --wave=dadda.ghw 67 | 68 | fi 69 | 70 | if [ "$WALLACE" = "1" ] 71 | then 72 | 73 | cd $BASEDIR/sim/work 74 | 75 | if [ -e "configure.vhd" ] 76 | then 77 | rm configure.vhd 78 | fi 79 | 80 | echo "library ieee;" >> configure.vhd 81 | echo "use ieee.std_logic_1164.all;" >> configure.vhd 82 | echo "use ieee.numeric_std.all;" >> configure.vhd 83 | echo "" >> configure.vhd 84 | echo "package configure is" >> configure.vhd 85 | echo " constant XLEN : integer := "$N";" >> configure.vhd 86 | echo " constant YLEN : integer := "$M";" >> configure.vhd 87 | echo " constant SEED : integer := "$TIME";" >> configure.vhd 88 | echo " constant TYP : std_logic := '"1"';" >> configure.vhd 89 | echo "end package;" >> configure.vhd 90 | 91 | mv configure.vhd $BASEDIR/src/vhdl/ 92 | 93 | $ANALYS $BASEDIR/src/vhdl/configure.vhd 94 | 95 | $ANALYS $BASEDIR/src/vhdl/wire.vhd 96 | $ANALYS $BASEDIR/src/vhdl/libs.vhd 97 | $ANALYS $BASEDIR/src/vhdl/mutex.vhd 98 | 99 | $ANALYS $BASEDIR/src/vhdl/ha.vhd 100 | $ANALYS $BASEDIR/src/vhdl/fa.vhd 101 | 102 | $ANALYS $BASEDIR/src/vhdl/dadda.vhd 103 | $ANALYS $BASEDIR/src/vhdl/wallace.vhd 104 | $ANALYS $BASEDIR/src/vhdl/mul.vhd 105 | 106 | $ANALYS $BASEDIR/src/tb/vhdl/test_multiply.vhd 107 | 108 | $ELABOR test_multiply 109 | $SIMULA test_multiply --stop-time=${MAXTIME}ps --wave=wallace.ghw 110 | 111 | fi 112 | 113 | fi 114 | 115 | cd $BASEDIR/src/cpp 116 | 117 | if [ "$VERILOG" = "1" ] 118 | then 119 | 120 | TIME=$(date +%s) 121 | 122 | ./multiply_tree dadda $N $M 123 | ./multiply_tree wallace $N $M 124 | mv dadda.sv $BASEDIR/src/verilog/ 125 | mv wallace.sv $BASEDIR/src/verilog/ 126 | 127 | if [ "$DADDA" = "1" ] 128 | then 129 | 130 | cd $BASEDIR/sim/work 131 | 132 | if [ -e "configure.sv" ] 133 | then 134 | rm configure.sv 135 | fi 136 | 137 | echo "package configure;" >> configure.sv 138 | echo " timeunit 1ps;" >> configure.sv 139 | echo " timeprecision 1ps;" >> configure.sv 140 | echo "" >> configure.sv 141 | echo " parameter XLEN = "$N";" >> configure.sv 142 | echo " parameter YLEN = "$M";" >> configure.sv 143 | echo " parameter TYP = "0";" >> configure.sv 144 | echo " integer MAXTIME = "$MAXTIME";" >> configure.sv 145 | echo " integer SEED = "$TIME";" >> configure.sv 146 | echo "endpackage" >> configure.sv 147 | 148 | mv configure.sv $BASEDIR/src/verilog/ 149 | 150 | $VERILATOR --binary --trace --trace-structs --top-module test_multiply \ 151 | $BASEDIR/src/verilog/configure.sv \ 152 | $BASEDIR/src/verilog/mutex.sv \ 153 | $BASEDIR/src/verilog/ha.sv \ 154 | $BASEDIR/src/verilog/fa.sv \ 155 | $BASEDIR/src/verilog/dadda.sv \ 156 | $BASEDIR/src/verilog/wallace.sv \ 157 | $BASEDIR/src/verilog/mul.sv \ 158 | $BASEDIR/src/tb/verilog/test_multiply.sv 2>&1 > /dev/null 159 | 160 | make -s -j -C obj_dir/ -f Vtest_multiply.mk Vtest_multiply 161 | 162 | obj_dir/Vtest_multiply 163 | 164 | fi 165 | 166 | if [ "$WALLACE" = "1" ] 167 | then 168 | 169 | cd $BASEDIR/sim/work 170 | 171 | if [ -e "configure.sv" ] 172 | then 173 | rm configure.sv 174 | fi 175 | 176 | echo "package configure;" >> configure.sv 177 | echo " timeunit 1ps;" >> configure.sv 178 | echo " timeprecision 1ps;" >> configure.sv 179 | echo "" >> configure.sv 180 | echo " parameter XLEN = "$N";" >> configure.sv 181 | echo " parameter YLEN = "$M";" >> configure.sv 182 | echo " parameter TYP = "1";" >> configure.sv 183 | echo " integer MAXTIME = "$MAXTIME";" >> configure.sv 184 | echo " integer SEED = "$TIME";" >> configure.sv 185 | echo "endpackage" >> configure.sv 186 | 187 | mv configure.sv $BASEDIR/src/verilog/ 188 | 189 | $VERILATOR --binary --trace --trace-structs --top-module test_multiply \ 190 | $BASEDIR/src/verilog/configure.sv \ 191 | $BASEDIR/src/verilog/mutex.sv \ 192 | $BASEDIR/src/verilog/ha.sv \ 193 | $BASEDIR/src/verilog/fa.sv \ 194 | $BASEDIR/src/verilog/dadda.sv \ 195 | $BASEDIR/src/verilog/wallace.sv \ 196 | $BASEDIR/src/verilog/mul.sv \ 197 | $BASEDIR/src/tb/verilog/test_multiply.sv 2>&1 > /dev/null 198 | 199 | make -s -j -C obj_dir/ -f Vtest_multiply.mk Vtest_multiply 200 | 201 | obj_dir/Vtest_multiply 202 | 203 | fi 204 | 205 | fi 206 | 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /src/cpp/multiply_tree.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | 10 | using namespace std; 11 | 12 | string format_account_number(int acct_no) { 13 | ostringstream out; 14 | out << internal << setfill('0') << setw(8) << acct_no; 15 | return out.str(); 16 | } 17 | 18 | class PP 19 | { 20 | public: 21 | int i; 22 | int j; 23 | PP(int i,int j); 24 | string print(string lang); 25 | }; 26 | 27 | PP::PP(int i,int j) 28 | { 29 | this->i = i; 30 | this->j = j; 31 | } 32 | 33 | string PP::print(string lang = "vhdl") 34 | { 35 | string out = ""; 36 | if (lang.compare("vhdl") == 0) 37 | { 38 | if (this->i>=0 && this->j>=0) 39 | out = "P("+to_string(this->i)+")("+to_string(this->j)+")"; 40 | if (this->i>=0 && this->j<0) 41 | out = "S("+to_string(this->i)+")"; 42 | if (this->i<0 && this->j>=0) 43 | out = "C("+to_string(this->j)+")"; 44 | } 45 | else 46 | { 47 | if (this->i>=0 && this->j>=0) 48 | out = "P["+to_string(this->i)+"]["+to_string(this->j)+"]"; 49 | if (this->i>=0 && this->j<0) 50 | out = "S["+to_string(this->i)+"]"; 51 | if (this->i<0 && this->j>=0) 52 | out = "C["+to_string(this->j)+"]"; 53 | } 54 | return out; 55 | } 56 | 57 | class ADD 58 | { 59 | public: 60 | string a; 61 | string b; 62 | string cin; 63 | string s; 64 | string cout; 65 | int type; 66 | ADD(string a,string b,string cin,string s,string cout,int type); 67 | string Print(int id,string lang); 68 | friend ostream &operator<<(ostream &out, const ADD &obj); 69 | }; 70 | 71 | ADD::ADD(string a,string b,string cin,string s,string cout,int type) 72 | { 73 | this->a = a; 74 | this->b = b; 75 | this->cin = cin; 76 | this->s = s; 77 | this->cout = cout; 78 | this->type = type; 79 | } 80 | 81 | string ADD::Print(int id,string lang = "vhdl") 82 | { 83 | stringstream adder; 84 | if (lang.compare("vhdl") == 0) 85 | { 86 | if (this->type==0) 87 | { 88 | adder << " HA_"<< format_account_number(id) <<" : ha port map ("<a<<","<b<<","<s<<","<cout<<");"; 89 | } 90 | else if (this->type==1) 91 | { 92 | adder << " FA_"<< format_account_number(id) <<" : fa port map ("<a<<","<b<<","<cin<<","<s<<","<cout<<");"; 93 | } 94 | } 95 | else 96 | { 97 | if (this->type==0) 98 | { 99 | adder << " ha HA_"<< format_account_number(id) <<" ("<a<<","<b<<","<s<<","<cout<<");"; 100 | } 101 | else if (this->type==1) 102 | { 103 | adder << " fa FA_"<< format_account_number(id) <<" ("<a<<","<b<<","<cin<<","<s<<","<cout<<");"; 104 | } 105 | } 106 | return adder.str(); 107 | } 108 | 109 | ostream &operator<<(ostream &out, const ADD &obj) 110 | { 111 | stringstream adder; 112 | if (obj.type==0) 113 | { 114 | adder << "Half_Adder HA("< Adders; 126 | 127 | void print_matrix(int N, int M) 128 | { 129 | #ifdef DEBUG 130 | int i,j; 131 | int value; 132 | for (i=0; i> value; 148 | #endif 149 | } 150 | 151 | void partial_product_generation_schema(int type, int N, int M) 152 | { 153 | int i,j,k; 154 | int new_i; 155 | PP_Matrix = (PP**) malloc((N+M)*sizeof(PP*)); 156 | for (i=0; i=0 || PP_Matrix[i][j].j>=0) 231 | { 232 | ++local_weight; 233 | } 234 | else 235 | { 236 | break; 237 | } 238 | } 239 | if (weight=0 || PP_Matrix[i][j].j>=0) 280 | { 281 | ++local_weight; 282 | } 283 | else 284 | { 285 | break; 286 | } 287 | } 288 | print_matrix(N,M); 289 | if (desired_hight >= local_weight) 290 | { 291 | num = 0; 292 | if (c_nindex == 0) 293 | { 294 | continue; 295 | } 296 | restart = 0; 297 | } 298 | else if ((desired_hight+1) == local_weight) 299 | { 300 | string a = PP_Matrix[0][j].print(); 301 | string b = PP_Matrix[1][j].print(); 302 | string cin = ""; 303 | string s = "S("+to_string(index)+")"; 304 | string cout = "C("+to_string(index)+")"; 305 | Adders.push_back(ADD(a,b,cin,s,cout,0)); 306 | PP_Matrix[0][j].i = -1; 307 | PP_Matrix[0][j].j = -1; 308 | PP_Matrix[1][j].i = -1; 309 | PP_Matrix[1][j].j = -1; 310 | c_array[c_index] = index; 311 | s_array[s_index] = index; 312 | ++c_index; 313 | ++s_index; 314 | ++index; 315 | num = 2; 316 | restart = 0; 317 | } 318 | else 319 | { 320 | string a = PP_Matrix[0][j].print(); 321 | string b = PP_Matrix[1][j].print(); 322 | string cin = PP_Matrix[2][j].print(); 323 | string s = "S("+to_string(index)+")"; 324 | string cout = "C("+to_string(index)+")"; 325 | Adders.push_back(ADD(a,b,cin,s,cout,1)); 326 | PP_Matrix[0][j].i = -1; 327 | PP_Matrix[0][j].j = -1; 328 | PP_Matrix[1][j].i = -1; 329 | PP_Matrix[1][j].j = -1; 330 | PP_Matrix[2][j].i = -1; 331 | PP_Matrix[2][j].j = -1; 332 | c_array[c_index] = index; 333 | s_array[s_index] = index; 334 | ++c_index; 335 | ++s_index; 336 | ++index; 337 | num = 3; 338 | if (PP_Matrix[3][j].i>=0 || PP_Matrix[3][j].j>=0) 339 | { 340 | restart = 1; 341 | } 342 | } 343 | print_matrix(N,M); 344 | for (k=0; k0; i--) 363 | { 364 | PP_Matrix[i][j].i = PP_Matrix[i-1][j].i; 365 | PP_Matrix[i][j].j = PP_Matrix[i-1][j].j; 366 | PP_Matrix[i-1][j].i = -1; 367 | PP_Matrix[i-1][j].j = -1; 368 | } 369 | } 370 | k = 0; 371 | l = 0; 372 | prior = 0; 373 | while(1) 374 | { 375 | if (k>=(s_index+c_nindex)) 376 | { 377 | break; 378 | } 379 | if (prior == 0 && l=0 || PP_Matrix[i][j].j>=0) 432 | { 433 | ++local_weight; 434 | } 435 | } 436 | if (weight=0 || PP_Matrix[i][j].j>=0) 454 | { 455 | ++current_weight; 456 | } 457 | } 458 | if (local_weight=0; j--) 468 | { 469 | current_weight = 0; 470 | for (i=k; i=0 || PP_Matrix[i][j].j>=0) 473 | { 474 | ++current_weight; 475 | } 476 | } 477 | print_matrix(N,M); 478 | if (current_weight == 1) 479 | { 480 | if (PP_Matrix[k][j].i<0 && PP_Matrix[k][j].j<0 && PP_Matrix[k+1][j].i<0 && PP_Matrix[k+1][j].j<0) 481 | { 482 | if ((PP_Matrix[k][j-1].i>=0 || PP_Matrix[k][j-1].j>=0) || (PP_Matrix[k+1][j-1].i>=0 || PP_Matrix[k+1][j-1].j>=0)) 483 | { 484 | PP_Matrix[k][j].i = PP_Matrix[k+2][j].i; 485 | PP_Matrix[k][j].j = PP_Matrix[k+2][j].j; 486 | PP_Matrix[k+1][j].i = -1; 487 | PP_Matrix[k+1][j].j = -1; 488 | PP_Matrix[k+2][j].i = -1; 489 | PP_Matrix[k+2][j].j = -1; 490 | } 491 | else 492 | { 493 | PP_Matrix[k+1][j].i = PP_Matrix[k+2][j].i; 494 | PP_Matrix[k+1][j].j = PP_Matrix[k+2][j].j; 495 | PP_Matrix[k+2][j].i = -1; 496 | PP_Matrix[k+2][j].j = -1; 497 | } 498 | } 499 | } 500 | else if (current_weight == 2) 501 | { 502 | string a = PP_Matrix[k][j].print(); 503 | string b = PP_Matrix[k+1][j].print(); 504 | if (PP_Matrix[k][j].i < 0 && PP_Matrix[k][j].j < 0) 505 | { 506 | a = PP_Matrix[k+1][j].print(); 507 | b = PP_Matrix[k+2][j].print(); 508 | } 509 | string cin = ""; 510 | string s = "S("+to_string(index)+")"; 511 | string cout = "C("+to_string(index)+")"; 512 | PP_Matrix[k][j].i = index; 513 | PP_Matrix[k][j].j = -1; 514 | PP_Matrix[k+1][j].i = -1; 515 | PP_Matrix[k+1][j].j = -1; 516 | PP_Matrix[k+2][j].i = -1; 517 | PP_Matrix[k+2][j].j = -1; 518 | PP_Matrix[k+1][j+1].i = -1; 519 | PP_Matrix[k+1][j+1].j = index; 520 | Adders.push_back(ADD(a,b,cin,s,cout,0)); 521 | ++index; 522 | } 523 | else if (current_weight == 3) 524 | { 525 | string a = PP_Matrix[k][j].print(); 526 | string b = PP_Matrix[k+1][j].print(); 527 | string cin = PP_Matrix[k+2][j].print(); 528 | string s = "S("+to_string(index)+")"; 529 | string cout = "C("+to_string(index)+")"; 530 | PP_Matrix[k][j].i = index; 531 | PP_Matrix[k][j].j = -1; 532 | PP_Matrix[k+1][j].i = -1; 533 | PP_Matrix[k+1][j].j = -1; 534 | PP_Matrix[k+2][j].i = -1; 535 | PP_Matrix[k+2][j].j = -1; 536 | PP_Matrix[k+1][j+1].i = -1; 537 | PP_Matrix[k+1][j+1].j = index; 538 | Adders.push_back(ADD(a,b,cin,s,cout,1)); 539 | ++index; 540 | } 541 | } 542 | } 543 | print_matrix(N,M); 544 | for (k=0; k<(weight/3); k++) 545 | { 546 | for (i=0; i=0 || PP_Matrix[i][j].j>=0) 552 | { 553 | cond = 1; 554 | break; 555 | } 556 | } 557 | if (cond == 0) 558 | { 559 | for (j=0; j" << " " << " " << endl; 732 | cout << "Valid types: or " << endl; 733 | cout << "Valid N,M: e.g. <32,64> for 32x64 binary multiplication" << endl; 734 | return 0; 735 | } 736 | if (!strcmp(argv[1],"wallace")) 737 | { 738 | cout << "Wallace-Tree choosen!" << endl; 739 | type = 0; 740 | } 741 | else if (!strcmp(argv[1],"dadda")) 742 | { 743 | cout << "Dadda-Tree choosen!" << endl; 744 | type = 1; 745 | } 746 | else 747 | { 748 | cout << "Invalid type choosen!" << endl; 749 | return 0; 750 | } 751 | i=0; 752 | for (; argv[2][i] != 0; i++) 753 | { 754 | if (!isdigit(argv[2][i])) 755 | { 756 | cout << "Invalid N given!" << endl; 757 | return 0; 758 | } 759 | } 760 | i=0; 761 | for (; argv[3][i] != 0; i++) 762 | { 763 | if (!isdigit(argv[3][i])) 764 | { 765 | cout << "Invalid M given!" << endl; 766 | return 0; 767 | } 768 | } 769 | stringstream dimN(argv[2]); 770 | dimN >> N; 771 | stringstream dimM(argv[3]); 772 | dimM >> M; 773 | 774 | cout << "Multipy-Tree N: " << N << " M: " << M << endl; 775 | 776 | partial_product_generation_schema(type,N,M); 777 | print_matrix(N,M); 778 | if (type == 0) 779 | { 780 | wallace_multiplier_reduction_schema(N,M); 781 | } 782 | else if (type == 1) 783 | { 784 | dadda_multiplier_reduction_schema(N,M); 785 | } 786 | vhdl_code_generation_schema(type,N,M); 787 | verilog_code_generation_schema(type,N,M); 788 | } 789 | --------------------------------------------------------------------------------