├── .gitignore ├── 32f429_lcd.c ├── 32f429_lcd.h ├── 32f429_sdram.c ├── 32f429_sdram.h ├── MDK-ARM ├── DebugConfig │ ├── STM32F429_439xx_STM32F429IGTx.dbgconf │ └── STM32F429_439xx_STM32F439II.dbgconf ├── Project.uvguix.Admin ├── Project.uvguix.tarasii ├── Project.uvopt ├── Project.uvoptx ├── Project.uvproj.saved_uv4 ├── Project.uvprojx └── readme.txt ├── OV2640_DSF4.pdf ├── Open429I-C-Schematic.pdf ├── TouchPanel ├── TouchPanel.c ├── TouchPanel.h └── config.h ├── camera ├── DCMI_OV7670_INITTABLE.h ├── SCCB.C ├── SCCB.h ├── config.h ├── dcmi_OV7670.c ├── dcmi_OV7670.h ├── usart.c └── usart.h ├── cmtypes.h ├── dcmi.c ├── dcmi.h ├── i2c.c ├── i2c.h ├── main.c ├── main.h ├── ov2640_lcd.sublime-project ├── ov2640_lcd.sublime-workspace ├── pin.h ├── readme.txt ├── stm32f4xx_conf.h ├── stm32f4xx_it.c ├── stm32f4xx_it.h ├── system_stm32f4xx.c ├── usart.c └── usart.h /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows image file caches 2 | Thumbs.db 3 | ehthumbs.db 4 | 5 | # Folder config file 6 | Desktop.ini 7 | 8 | # Recycle Bin used on file shares 9 | $RECYCLE.BIN/ 10 | 11 | # Windows Installer files 12 | *.cab 13 | *.msi 14 | *.msm 15 | *.msp 16 | 17 | # Windows shortcuts 18 | *.lnk 19 | 20 | # ========================= 21 | # Operating System Files 22 | # ========================= 23 | 24 | # OSX 25 | # ========================= 26 | 27 | .DS_Store 28 | .AppleDouble 29 | .LSOverride 30 | 31 | # Thumbnails 32 | ._* 33 | 34 | # Files that might appear on external disk 35 | .Spotlight-V100 36 | .Trashes 37 | 38 | # Directories potentially created on remote AFP share 39 | .AppleDB 40 | .AppleDesktop 41 | Network Trash Folder 42 | Temporary Items 43 | .apdisk 44 | 45 | # Ivaniv 46 | .lst 47 | .iex 48 | .bak 49 | .dep 50 | .o 51 | .tmp 52 | .crf 53 | .d 54 | MDK-ARM/STM32F429_439xx/* 55 | MDK-ARM/STM32F429_439xx/ -------------------------------------------------------------------------------- /32f429_lcd.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f429i_discovery_lcd.h 4 | * @author MCD Application Team 5 | * @version V1.0.1 6 | * @date 28-October-2013 7 | * @brief This file contains all the functions prototypes for the 8 | * stm32f429i_discovery_lcd.c driver. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32429I_DISCO_SDRAM_H 31 | #define __STM32429I_DISCO_SDRAM_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f4xx.h" 39 | 40 | /** @addtogroup Utilities 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup STM32F4_EVAL 45 | * @{ 46 | */ 47 | 48 | /** @addtogroup STM32F429I_DISCOVERY 49 | * @{ 50 | */ 51 | 52 | /** @addtogroup STM32F429I_DISCOVERY_SDRAM 53 | * @{ 54 | */ 55 | 56 | /** @defgroup STM32429I_DISCO_SDRAM_Private_Defines 57 | * @{ 58 | */ 59 | 60 | /** 61 | * @brief FMC SDRAM Bank address 62 | */ 63 | #define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) 64 | 65 | /** 66 | * @brief FMC SDRAM Memory Width 67 | */ 68 | /* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */ 69 | #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b 70 | 71 | /** 72 | * @brief FMC SDRAM CAS Latency 73 | */ 74 | /* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */ 75 | #define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 76 | 77 | /** 78 | * @brief FMC SDRAM Memory clock period 79 | */ 80 | #define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */ 81 | /* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */ 82 | 83 | /** 84 | * @brief FMC SDRAM Memory Read Burst feature 85 | */ 86 | #define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */ 87 | /* #define SDRAM_READBURST FMC_Read_Burst_Enable */ 88 | 89 | /** 90 | * @brief FMC SDRAM Bank Remap 91 | */ 92 | /* #define SDRAM_BANK_REMAP */ 93 | 94 | 95 | 96 | /** 97 | * @brief Uncomment the line below if you want to use user defined Delay function 98 | * (for precise timing), otherwise default _delay_ function defined within 99 | * this driver is used (less precise timing). 100 | */ 101 | 102 | /* #define USE_Delay */ 103 | 104 | #ifdef USE_Delay 105 | #define __Delay Delay /* User can provide more timing precise __Delay function 106 | (with 10ms time base), using SysTick for example */ 107 | #else 108 | #define __Delay delay /* Default __Delay function with less precise timing */ 109 | #endif 110 | 111 | /** 112 | * @brief FMC SDRAM Mode definition register defines 113 | */ 114 | #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) 115 | #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) 116 | #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) 117 | #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) 118 | #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) 119 | #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) 120 | #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) 121 | #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) 122 | #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) 123 | #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 124 | #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) 125 | 126 | /** 127 | * @} 128 | */ 129 | 130 | /** @defgroup STM32429I_DISCO_SDRAM_Exported_Functions 131 | * @{ 132 | */ 133 | void SDRAM_Init(void); 134 | void SDRAM_GPIOConfig(void); 135 | void SDRAM_InitSequence(void); 136 | void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize); 137 | void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize); 138 | 139 | #ifdef __cplusplus 140 | } 141 | #endif 142 | 143 | #endif /* __STM32429I_DISCO_SDRAM_H */ 144 | 145 | /** 146 | * @} 147 | */ 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** 154 | * @} 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /** 162 | * @} 163 | */ 164 | 165 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 166 | -------------------------------------------------------------------------------- /MDK-ARM/DebugConfig/STM32F429_439xx_STM32F429IGTx.dbgconf: -------------------------------------------------------------------------------- 1 | // <<< Use Configuration Wizard in Context Menu >>> 2 | 3 | // Debug MCU Configuration 4 | // DBG_SLEEP Debug Sleep Mode 5 | // DBG_STOP Debug Stop Mode 6 | // DBG_STANDBY Debug Standby Mode 7 | // 8 | DbgMCU_CR = 0x00000007; 9 | 10 | // Debug MCU APB1 Freeze 11 | // DBG_TIM2_STOP Timer 2 Stopped when Core is halted 12 | // DBG_TIM3_STOP Timer 3 Stopped when Core is halted 13 | // DBG_TIM4_STOP Timer 4 Stopped when Core is halted 14 | // DBG_TIM5_STOP Timer 5 Stopped when Core is halted 15 | // DBG_TIM6_STOP Timer 6 Stopped when Core is halted 16 | // DBG_TIM7_STOP Timer 7 Stopped when Core is halted 17 | // DBG_TIM12_STOP Timer 12 Stopped when Core is halted 18 | // DBG_TIM13_STOP Timer 13 Stopped when Core is halted 19 | // DBG_TIM14_STOP Timer 14 Stopped when Core is halted 20 | // DBG_RTC_STOP RTC Stopped when Core is halted 21 | // DBG_WWDG_STOP Window Watchdog Stopped when Core is halted 22 | // DBG_IWDG_STOP Independent Watchdog Stopped when Core is halted 23 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS Timeout Mode Stopped when Core is halted 24 | // DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS Timeout Mode Stopped when Core is halted 25 | // DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS Timeout Mode Stopped when Core is halted 26 | // DBG_CAN1_STOP CAN1 Stopped when Core is halted 27 | // DBG_CAN2_STOP CAN2 Stopped when Core is halted 28 | // 29 | DbgMCU_APB1_Fz = 0x00000000; 30 | 31 | 32 | // Debug MCU APB2 Freeze 33 | // DBG_TIM1_STOP Timer 1 Stopped when Core is halted 34 | // DBG_TIM8_STOP Timer 8 Stopped when Core is halted 35 | // DBG_TIM9_STOP Timer 9 Stopped when Core is halted 36 | // DBG_TIM10_STOP Timer 10 Stopped when Core is halted 37 | // DBG_TIM11_STOP Timer 11 Stopped when Core is halted 38 | // 39 | DbgMCU_APB2_Fz = 0x00000000; 40 | 41 | // <<< end of configuration section >>> -------------------------------------------------------------------------------- /MDK-ARM/DebugConfig/STM32F429_439xx_STM32F439II.dbgconf: -------------------------------------------------------------------------------- 1 | // <<< Use Configuration Wizard in Context Menu >>> 2 | 3 | // Debug MCU Configuration 4 | // DBG_SLEEP Debug Sleep Mode 5 | // DBG_STOP Debug Stop Mode 6 | // DBG_STANDBY Debug Standby Mode 7 | // 8 | DbgMCU_CR = 0x00000007; 9 | 10 | // Debug MCU APB1 Freeze 11 | // DBG_TIM2_STOP Timer 2 Stopped when Core is halted 12 | // DBG_TIM3_STOP Timer 3 Stopped when Core is halted 13 | // DBG_TIM4_STOP Timer 4 Stopped when Core is halted 14 | // DBG_TIM5_STOP Timer 5 Stopped when Core is halted 15 | // DBG_TIM6_STOP Timer 6 Stopped when Core is halted 16 | // DBG_TIM7_STOP Timer 7 Stopped when Core is halted 17 | // DBG_TIM12_STOP Timer 12 Stopped when Core is halted 18 | // DBG_TIM13_STOP Timer 13 Stopped when Core is halted 19 | // DBG_TIM14_STOP Timer 14 Stopped when Core is halted 20 | // DBG_RTC_STOP RTC Stopped when Core is halted 21 | // DBG_WWDG_STOP Window Watchdog Stopped when Core is halted 22 | // DBG_IWDG_STOP Independent Watchdog Stopped when Core is halted 23 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS Timeout Mode Stopped when Core is halted 24 | // DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS Timeout Mode Stopped when Core is halted 25 | // DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS Timeout Mode Stopped when Core is halted 26 | // DBG_CAN1_STOP CAN1 Stopped when Core is halted 27 | // DBG_CAN2_STOP CAN2 Stopped when Core is halted 28 | // 29 | DbgMCU_APB1_Fz = 0x00000000; 30 | 31 | 32 | // Debug MCU APB2 Freeze 33 | // DBG_TIM1_STOP Timer 1 Stopped when Core is halted 34 | // DBG_TIM8_STOP Timer 8 Stopped when Core is halted 35 | // DBG_TIM9_STOP Timer 9 Stopped when Core is halted 36 | // DBG_TIM10_STOP Timer 10 Stopped when Core is halted 37 | // DBG_TIM11_STOP Timer 11 Stopped when Core is halted 38 | // 39 | DbgMCU_APB2_Fz = 0x00000000; 40 | 41 | // <<< end of configuration section >>> -------------------------------------------------------------------------------- /MDK-ARM/readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tarasii/stm32f429_ov7670_lcd_dcmi/d076d9dd047b62ea97d4777d762e4587c305b195/MDK-ARM/readme.txt -------------------------------------------------------------------------------- /OV2640_DSF4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tarasii/stm32f429_ov7670_lcd_dcmi/d076d9dd047b62ea97d4777d762e4587c305b195/OV2640_DSF4.pdf -------------------------------------------------------------------------------- /Open429I-C-Schematic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tarasii/stm32f429_ov7670_lcd_dcmi/d076d9dd047b62ea97d4777d762e4587c305b195/Open429I-C-Schematic.pdf -------------------------------------------------------------------------------- /TouchPanel/TouchPanel.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tarasii/stm32f429_ov7670_lcd_dcmi/d076d9dd047b62ea97d4777d762e4587c305b195/TouchPanel/TouchPanel.c -------------------------------------------------------------------------------- /TouchPanel/TouchPanel.h: -------------------------------------------------------------------------------- 1 | /********************************************************************************************************* 2 | * 3 | * File : TouchPanel.h 4 | * Hardware Environment: 5 | * Build Environment : RealView MDK-ARM Version: 4.20 6 | * Version : V1.0 7 | * By : 8 | * 9 | * (c) Copyright 2005-2011, WaveShare 10 | * http://www.waveshare.net 11 | * All Rights Reserved 12 | * 13 | *********************************************************************************************************/ 14 | 15 | #ifndef _TOUCHPANEL_H_ 16 | #define _TOUCHPANEL_H_ 17 | 18 | /* Includes ------------------------------------------------------------------*/ 19 | #include "stm32f4xx.h" 20 | 21 | /* Private typedef -----------------------------------------------------------*/ 22 | typedef struct POINT 23 | { 24 | uint16_t x; 25 | uint16_t y; 26 | }Coordinate; 27 | 28 | 29 | typedef struct Matrix 30 | { 31 | long double An, 32 | Bn, 33 | Cn, 34 | Dn, 35 | En, 36 | Fn, 37 | Divider ; 38 | } Matrix ; 39 | 40 | /* Private variables ---------------------------------------------------------*/ 41 | extern Coordinate ScreenSample[3]; 42 | extern Coordinate DisplaySample[3]; 43 | extern Matrix matrix ; 44 | extern Coordinate display ; 45 | 46 | /* Private define ------------------------------------------------------------*/ 47 | 48 | #define CHX 0x90 49 | #define CHY 0xd0 50 | 51 | /* Private function prototypes -----------------------------------------------*/ 52 | void TP_Init(void); 53 | Coordinate *Read_Ads7846(void); 54 | void TouchPanel_Calibrate(void); 55 | void DrawCross(uint16_t Xpos,uint16_t Ypos); 56 | void TP_DrawPoint(uint16_t Xpos,uint16_t Ypos); 57 | FunctionalState setCalibrationMatrix( Coordinate * displayPtr,Coordinate * screenPtr,Matrix * matrixPtr); 58 | FunctionalState getDisplayPoint(Coordinate * displayPtr,Coordinate * screenPtr,Matrix * matrixPtr ); 59 | 60 | #endif 61 | 62 | /********************************************************************************************************* 63 | END FILE 64 | *********************************************************************************************************/ 65 | 66 | 67 | -------------------------------------------------------------------------------- /TouchPanel/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | #include 5 | #include "stm32f4xx.h" 6 | /** 7 | * @brief Definition for TouchPanel 8 | */ 9 | /* Configure TouchPanel pins: TP_CS-> PC4 and TP_IRQ-> PC5 */ 10 | 11 | 12 | #define Open_TP_CS_PIN GPIO_Pin_3 13 | #define Open_TP_CS_PORT GPIOI 14 | #define Open_TP_CS_CLK RCC_AHB1Periph_GPIOI 15 | 16 | #define Open_TP_IRQ_PIN GPIO_Pin_3 17 | #define Open_TP_IRQ_PORT GPIOE 18 | #define Open_TP_IRQ_CLK RCC_AHB1Periph_GPIOE 19 | 20 | 21 | #define TP_CS(x) x ? GPIO_SetBits(Open_TP_CS_PORT,Open_TP_CS_PIN): GPIO_ResetBits(Open_TP_CS_PORT,Open_TP_CS_PIN) 22 | 23 | #define TP_INT_IN GPIO_ReadInputDataBit(Open_TP_IRQ_PORT,Open_TP_IRQ_PIN) 24 | 25 | /** 26 | * @brief Definition for TouchPanel SPI 27 | */ 28 | /* Configure TouchPanel pins: TP_CLK-> PB13 and TP_MISO-> PB14 and TP_MOSI-> PB15 */ 29 | #define Open_RCC_SPI RCC_APB1Periph_SPI2 30 | #define Open_GPIO_AF_SPI GPIO_AF_SPI2 31 | 32 | #define Open_SPI SPI2 33 | #define Open_SPI_CLK_INIT RCC_APB1PeriphClockCmd 34 | #define Open_SPI_IRQn SPI2_IRQn 35 | #define Open_SPI_IRQHANDLER SPI2_IRQHandler 36 | 37 | #define Open_SPI_SCK_PIN GPIO_Pin_13 38 | #define Open_SPI_SCK_GPIO_PORT GPIOB 39 | #define Open_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOB 40 | #define Open_SPI_SCK_SOURCE GPIO_PinSource13 41 | 42 | #define Open_SPI_MISO_PIN GPIO_Pin_14 43 | #define Open_SPI_MISO_GPIO_PORT GPIOB 44 | #define Open_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOB 45 | #define Open_SPI_MISO_SOURCE GPIO_PinSource14 46 | 47 | #define Open_SPI_MOSI_PIN GPIO_Pin_15 48 | #define Open_SPI_MOSI_GPIO_PORT GPIOB 49 | #define Open_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOB 50 | #define Open_SPI_MOSI_SOURCE GPIO_PinSource15 51 | 52 | #endif /*_CONFIG_H*/ 53 | 54 | -------------------------------------------------------------------------------- /camera/DCMI_OV7670_INITTABLE.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tarasii/stm32f429_ov7670_lcd_dcmi/d076d9dd047b62ea97d4777d762e4587c305b195/camera/DCMI_OV7670_INITTABLE.h -------------------------------------------------------------------------------- /camera/SCCB.C: -------------------------------------------------------------------------------- 1 | /* Includes ------------------------------------------------------------------*/ 2 | #include "camera/SCCB.h" 3 | #include "I2C.h" 4 | 5 | 6 | /******************************************************************************* 7 | * Function Name : SCCB_GPIO_Config 8 | * Description : 9 | * Input : None 10 | * Output : None 11 | * Return : None 12 | * Attention : None 13 | *******************************************************************************/ 14 | void SCCB_GPIO_Init(void) 15 | { 16 | I2C_Init_(Open407V_SCCB); 17 | } 18 | 19 | 20 | /** 21 | * @brief Writes a byte at a specific Camera register 22 | * @param Device: OV7670 write address. 23 | * @param Addr: OV7670 register address. 24 | * @param Data: data to be written to the specific register 25 | * @retval 0x00 if write operation is OK. 26 | * 0xFF if timeout condition occured (device not connected or bus error). 27 | */ 28 | uint8_t DCMI_SingleRandomWrite(uint8_t Reg, uint8_t Data) 29 | { 30 | uint8_t buff[2]; 31 | buff[0] = Reg; 32 | buff[1] = Data; 33 | if (I2C_Write(Open407V_SCCB, buff, 2, OV7670_DEVICE_WRITE_ADDRESS) == Error) return 0xFF; 34 | return 0; 35 | } 36 | 37 | /** 38 | * @brief Reads a byte from a specific Camera register 39 | * @param Device: OV7670 write address. 40 | * @param Addr: OV7670 register address. 41 | * @retval data read from the specific register or 0xFF if timeout condition 42 | * occured. 43 | */ 44 | uint8_t DCMI_SingleRandomRead(uint8_t Reg, uint8_t *Data) 45 | { 46 | if (I2C_Write(Open407V_SCCB, &Reg, 1, OV7670_DEVICE_READ_ADDRESS) == Error) return 0xFF; 47 | if (I2C_Read(Open407V_SCCB, Data, 1, OV7670_DEVICE_READ_ADDRESS) == Error) return 0xFF; 48 | return 0; 49 | } 50 | 51 | 52 | -------------------------------------------------------------------------------- /camera/SCCB.h: -------------------------------------------------------------------------------- 1 | /* Define to prevent recursive inclusion -------------------------------------*/ 2 | #ifndef __SCCB_H 3 | #define __SCCB_H 4 | 5 | /* Includes ------------------------------------------------------------------*/ 6 | #include "stm32f4xx.h" 7 | #include "config.h" 8 | 9 | /* Private define ------------------------------------------------------------*/ 10 | 11 | #define OV7670_DEVICE_WRITE_ADDRESS 0x42 12 | #define OV7670_DEVICE_READ_ADDRESS 0x43 13 | 14 | 15 | /* Private function prototypes -----------------------------------------------*/ 16 | void SCCB_GPIO_Init(void); 17 | uint8_t DCMI_SingleRandomWrite(uint8_t Addr, uint8_t Data); 18 | uint8_t DCMI_SingleRandomRead(uint8_t Addr, uint8_t *Data); 19 | 20 | #endif 21 | 22 | /********************************************************************************************************* 23 | END FILE 24 | *********************************************************************************************************/ 25 | -------------------------------------------------------------------------------- /camera/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H 2 | #define _CONFIG_H 3 | 4 | #include 5 | #include "stm32f4xx.h" 6 | 7 | /** 8 | * @brief Definition for COM port4, connected to USART3 9 | */ 10 | #define Open407V_USART USART3 11 | #define Open407V_USART_CLK RCC_APB1Periph_USART3 12 | 13 | #define Open407V_USART_TX_PIN GPIO_Pin_10 14 | #define Open407V_USART_TX_GPIO_PORT GPIOC 15 | #define Open407V_USART_TX_GPIO_CLK RCC_AHB1Periph_GPIOC 16 | #define Open407V_USART_TX_SOURCE GPIO_PinSource10 17 | #define Open407V_USART_TX_AF GPIO_AF_USART3 18 | 19 | #define Open407V_USART_RX_PIN GPIO_Pin_11 20 | #define Open407V_USART_RX_GPIO_PORT GPIOC 21 | #define Open407V_USART_RX_GPIO_CLK RCC_AHB1Periph_GPIOC 22 | #define Open407V_USART_RX_SOURCE GPIO_PinSource11 23 | #define Open407V_USART_RX_AF GPIO_AF_USART3 24 | 25 | #define Open407V_USART_IRQn USART3_IRQn 26 | 27 | 28 | /** 29 | * @brief Definition for LCD 30 | */ 31 | /* Configure LCD pins: PB1->Reset and PB0->Back Light Control */ 32 | #define Open407V_LCD_BackLightControl_PIN GPIO_Pin_0 33 | #define Open407V_LCD_BackLightControl_PORT GPIOB 34 | #define Open407V_LCD_BackLightControl_CLK RCC_AHB1Periph_GPIOB 35 | 36 | #define Open407V_LCD_Reset_PIN GPIO_Pin_1 37 | #define Open407V_LCD_Reset_PORT GPIOB 38 | #define Open407V_LCD_Reset_CLK RCC_AHB1Periph_GPIOB 39 | 40 | /* DCMI Communication boards Interface */ 41 | 42 | /** 43 | * @connected to I2C2 44 | */ 45 | /* Configure I2C1 pins: PB10->SIOC and PB11->SIOD */ 46 | #define Open407V_SCCB I2C2 47 | #define Open407V_SCCB_CLK RCC_APB1Periph_I2C2 48 | 49 | #define Open407V_SCCB_SDA_PIN GPIO_Pin_11 50 | #define Open407V_SCCB_SDA_GPIO_PORT GPIOB 51 | #define Open407V_SCCB_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB 52 | #define Open407V_SCCB_SDA_SOURCE GPIO_PinSource11 53 | #define Open407V_SCCB_SDA_AF GPIO_AF_I2C2 54 | 55 | #define Open407V_SCCB_SCL_PIN GPIO_Pin_10 56 | #define Open407V_SCCB_SCL_GPIO_PORT GPIOB 57 | #define Open407V_SCCB_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB 58 | #define Open407V_SCCB_SCL_SOURCE GPIO_PinSource10 59 | #define Open407V_SCCB_SCL_AF GPIO_AF_I2C2 60 | 61 | #endif /*_CONFIG_H*/ 62 | 63 | -------------------------------------------------------------------------------- /camera/dcmi_OV7670.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file DCMI/OV7670_Camera/dcmi_OV7670.c 4 | * @author MCD Application Team 5 | * @version V1.0.0 6 | * @date 18-April-2011 7 | * @brief This file includes the driver for OV7670 Camera module mounted on 8 | * STM322xG-EVAL board RevA and RevB. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *
© COPYRIGHT 2011 STMicroelectronics
20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes ------------------------------------------------------------------*/ 24 | #include "camera/dcmi_OV7670.h" 25 | #include "camera/DCMI_OV7670_INITTABLE.h" 26 | 27 | /** @addtogroup DCMI_OV7670_Camera 28 | * @{ 29 | */ 30 | 31 | /* Private typedef -----------------------------------------------------------*/ 32 | /* Private define ------------------------------------------------------------*/ 33 | /* Bits definitions ----------------------------------------------------------*/ 34 | /* Private macro -------------------------------------------------------------*/ 35 | /* Private variables ---------------------------------------------------------*/ 36 | /* Private function prototypes -----------------------------------------------*/ 37 | /* Private functions ---------------------------------------------------------*/ 38 | static void Delay(uint32_t nTime); 39 | static void Delay_ms(uint32_t nTime); 40 | 41 | /** 42 | * @brief Configures the DCMI to interface with the OV7670 camera module. 43 | * @param None 44 | * @retval None 45 | */ 46 | void DCMI_Config(void) 47 | { 48 | DCMI_InitTypeDef DCMI_InitStructure; 49 | GPIO_InitTypeDef GPIO_InitStructure; 50 | DMA_InitTypeDef DMA_InitStructure; 51 | NVIC_InitTypeDef NVIC_InitStructure; 52 | 53 | /* Enable DCMI GPIOs clocks */ 54 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOE, ENABLE); 55 | 56 | /* Enable DCMI clock */ 57 | RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); 58 | 59 | /* Connect DCMI pins to AF13 ************************************************/ 60 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource4, GPIO_AF_DCMI);//HSYNC 61 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_DCMI);//PCLK 62 | 63 | GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_DCMI); 64 | GPIO_PinAFConfig(GPIOC, GPIO_PinSource7, GPIO_AF_DCMI); 65 | 66 | GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_DCMI); 67 | GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_DCMI);//VSYNC 68 | GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_DCMI); 69 | GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_DCMI); 70 | 71 | GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_DCMI); 72 | GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_DCMI); 73 | GPIO_PinAFConfig(GPIOE, GPIO_PinSource4, GPIO_AF_DCMI); 74 | 75 | /* DCMI GPIO configuration **************************************************/ 76 | /* 77 | D0 -- PC6 78 | D1 -- PC7 79 | D2 -- PE0 80 | D3 -- PE1 81 | D4 -- PE4 82 | D5 -- PB6 83 | D6 -- PB8 84 | D7 -- PB9 85 | PCK - PA6 86 | HS -- PA4 87 | VS -- PB7 88 | */ 89 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; 90 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 91 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; 92 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 93 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; 94 | GPIO_Init(GPIOA, &GPIO_InitStructure); 95 | 96 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9; 97 | GPIO_Init(GPIOB, &GPIO_InitStructure); 98 | 99 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; 100 | GPIO_Init(GPIOC, &GPIO_InitStructure); 101 | 102 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4; 103 | GPIO_Init(GPIOE, &GPIO_InitStructure); 104 | 105 | /* PCLK(PA6) */ 106 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; 107 | GPIO_Init(GPIOA, &GPIO_InitStructure); 108 | 109 | /* DCMI configuration *******************************************************/ 110 | DCMI_InitStructure.DCMI_CaptureMode = DCMI_CaptureMode_Continuous; 111 | DCMI_InitStructure.DCMI_SynchroMode = DCMI_SynchroMode_Hardware; 112 | DCMI_InitStructure.DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; 113 | DCMI_InitStructure.DCMI_VSPolarity = DCMI_VSPolarity_High; 114 | DCMI_InitStructure.DCMI_HSPolarity = DCMI_HSPolarity_High; 115 | DCMI_InitStructure.DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; 116 | DCMI_InitStructure.DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; 117 | 118 | DCMI_Init(&DCMI_InitStructure); 119 | 120 | /* DCMI Interrupts config ***************************************************/ 121 | DCMI_ITConfig(DCMI_IT_VSYNC, ENABLE); 122 | DCMI_ITConfig(DCMI_IT_LINE, ENABLE); 123 | DCMI_ITConfig(DCMI_IT_FRAME, ENABLE); 124 | DCMI_ITConfig(DCMI_IT_ERR, ENABLE); 125 | 126 | NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); 127 | NVIC_InitStructure.NVIC_IRQChannel = DCMI_IRQn; 128 | NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; 129 | NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; 130 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 131 | NVIC_Init(&NVIC_InitStructure); 132 | 133 | /* Configures the DMA2 to transfer Data from DCMI to the LCD ****************/ 134 | /* Enable DMA2 clock */ 135 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); 136 | 137 | /* DMA2 Stream1 Configuration */ 138 | DMA_DeInit(DMA2_Stream1); 139 | 140 | DMA_InitStructure.DMA_Channel = DMA_Channel_1; 141 | DMA_InitStructure.DMA_PeripheralBaseAddr = DCMI_DR_ADDRESS; 142 | DMA_InitStructure.DMA_Memory0BaseAddr = FSMC_LCD_ADDRESS; 143 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; 144 | //DMA_InitStructure.DMA_BufferSize = 0xfffe; 145 | DMA_InitStructure.DMA_BufferSize = 38400; 146 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 147 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; 148 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; 149 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; 150 | DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; 151 | DMA_InitStructure.DMA_Priority = DMA_Priority_High; 152 | DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; 153 | DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; 154 | DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; 155 | DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; 156 | 157 | DMA_Init(DMA2_Stream1, &DMA_InitStructure); 158 | } 159 | 160 | /** 161 | * @brief Set PA8 Output SYSCLK/2. 162 | * @param None 163 | * @retval None 164 | */ 165 | void MCO1_Init(void) 166 | { 167 | GPIO_InitTypeDef GPIO_InitStructure; 168 | 169 | RCC_ClockSecuritySystemCmd(ENABLE); 170 | 171 | /* Enable GPIOs clocks */ 172 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); 173 | 174 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_MCO); 175 | 176 | /* Configure MCO (PA8) */ 177 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; 178 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; 179 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 180 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 181 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 182 | GPIO_Init(GPIOA, &GPIO_InitStructure); 183 | 184 | RCC_MCO1Config(RCC_MCO1Source_PLLCLK, RCC_MCO1Div_3); 185 | } 186 | 187 | void DCMI_0V7670_PWDN_Init(void) 188 | { 189 | GPIO_InitTypeDef GPIO_InitStructure; 190 | 191 | /* Enable GPIOs clocks */ 192 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); 193 | 194 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 195 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 196 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; 197 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 198 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 199 | GPIO_Init(GPIOB, &GPIO_InitStructure); 200 | /*PWDN*/ 201 | GPIO_ResetBits(GPIOA, GPIO_Pin_2); 202 | Delay_ms(10); 203 | GPIO_SetBits(GPIOA, GPIO_Pin_2); 204 | } 205 | 206 | /** 207 | * @brief Set the VGA size(640*320). 208 | * @param None 209 | * @retval None 210 | */ 211 | uint8_t DCMI_OV7670_Init(void) 212 | { 213 | uint8_t i; 214 | //SCCB_GPIO_Config(); 215 | SCCB_GPIO_Init(); 216 | //DCMI_Config(); 217 | DCMI_GPIO_Init(); 218 | //DCMI_DMA_Init(640*480/8); 219 | DCMI_DMA_Init(320*240/2); 220 | //MCO1_Init(); 221 | //DCMI_0V7670_RST_PWDN_Init(); 222 | 223 | Delay_ms(0xfff); 224 | if(DCMI_SingleRandomWrite(OV7670_COM7, SCCB_REG_RESET)!=0) 225 | return 0xff; 226 | Delay_ms(0xfff); 227 | 228 | for(i=0;iManufacturer_ID1 = temp; 251 | if(DCMI_SingleRandomRead(OV7670_MIDL,&temp)!=0) 252 | return 0xff; 253 | OV7670ID->Manufacturer_ID2 = temp; 254 | if(DCMI_SingleRandomRead(OV7670_VER,&temp)!=0) 255 | return 0xff; 256 | OV7670ID->Version = temp; 257 | if(DCMI_SingleRandomRead(OV7670_PID,&temp)!=0) 258 | return 0xff; 259 | OV7670ID->PID = temp; 260 | 261 | return 0; 262 | } 263 | /** 264 | * @brief config_OV7660_window 265 | * @param //(140,16,640,480) is good for VGA 266 | * //(272,16,320,240) is good for QVGA 267 | * @retval None 268 | */ 269 | void OV7670_config_window(uint16_t startx, uint16_t starty, uint16_t width, uint16_t height) 270 | { 271 | uint16_t endx=(startx+width); 272 | uint16_t endy=(starty+height*2);// must be "height*2" 273 | uint8_t temp_reg1, temp_reg2; 274 | uint8_t state,temp; 275 | 276 | state = state; //Prevent report warning 277 | 278 | state = DCMI_SingleRandomRead(0x03, &temp_reg1 ); 279 | temp_reg1 &= 0xC0; 280 | state = DCMI_SingleRandomRead(0x32, &temp_reg2 ); 281 | temp_reg2 &= 0xC0; 282 | 283 | // Horizontal 284 | temp = temp_reg2|((endx&0x7)<<3)|(startx&0x7); 285 | state = DCMI_SingleRandomWrite(0x32, temp ); 286 | temp = (startx&0x7F8)>>3; 287 | state = DCMI_SingleRandomWrite(0x17, temp ); 288 | temp = (endx&0x7F8)>>3; 289 | state = DCMI_SingleRandomWrite(0x18, temp ); 290 | 291 | // Vertical 292 | temp = temp_reg1|((endy&0x7)<<3)|(starty&0x7); 293 | state = DCMI_SingleRandomWrite(0x03, temp ); 294 | temp = (starty&0x7F8)>>3; 295 | state = DCMI_SingleRandomWrite(0x19, temp ); 296 | temp = (endy&0x7F8)>>3; 297 | state = DCMI_SingleRandomWrite(0x1A, temp ); 298 | } 299 | 300 | /** 301 | * @} 302 | */ 303 | static void Delay(uint32_t nTime) 304 | { 305 | while(nTime--); 306 | } 307 | 308 | static void Delay_ms(uint32_t nTime) 309 | { 310 | while(nTime--) 311 | {Delay(1000);} 312 | 313 | } 314 | 315 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 316 | -------------------------------------------------------------------------------- /camera/dcmi_OV7670.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file DCMI/OV7670_Camera/dcmi_OV7670.h 4 | * @author MCD Application Team 5 | * @version V1.0.0 6 | * @date 18-April-2011 7 | * @brief Header for dcmi_OV7670.c module 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *
© COPYRIGHT 2011 STMicroelectronics
19 | ****************************************************************************** 20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __DCMI_OV7670_H 24 | #define __DCMI_OV7670_H 25 | 26 | /* Includes ------------------------------------------------------------------*/ 27 | #include "stm32f4xx.h" 28 | #include "camera/SCCB.h" 29 | #include "config.h" 30 | 31 | #define DCMI_DR_ADDRESS 0x50050028 32 | #define FSMC_LCD_ADDRESS 0x60020000 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | typedef struct 36 | { 37 | uint8_t Manufacturer_ID1; 38 | uint8_t Manufacturer_ID2; 39 | uint8_t Version; 40 | uint8_t PID; 41 | }OV7670_IDTypeDef; 42 | 43 | /* Exported constants --------------------------------------------------------*/ 44 | 45 | /* Use this define to set the maximum delay timeout for the I2C DCMI_SingleRandomWrite() 46 | and DCMI_SingleRandomRead() operations. Exeeding this timeout delay, the read/write 47 | functions will be aborted and return error code (0xFF). 48 | The period of the delay will depend on the system operating frequency. The following 49 | value has been set for system running at 120MHz. */ 50 | #define DCMI_TIMEOUT_MAX 10000 51 | 52 | /* Uncomment the line corresponding to the camera resolution */ 53 | //#define QVGA_SIZE /*320x240 */ 54 | //#define VGA_SIZE /* 640x480 */ 55 | 56 | 57 | /* OV7670 Registers definition */ 58 | #define OV7670_AGC 0x00 59 | #define OV7670_BLUE 0x01 60 | #define OV7670_RED 0x02 61 | #define OV7670_VREF 0x03 62 | #define OV7670_COM1 0x04 63 | #define OV7670_BAVE 0x05 64 | #define OV7670_GbAVE 0x06 65 | #define OV7670_AECHH 0x07 66 | #define OV7670_RAVE 0x08 67 | #define OV7670_COM2 0x09 68 | #define OV7670_PID 0x0A 69 | #define OV7670_VER 0x0B 70 | #define OV7670_COM3 0x0C 71 | #define OV7670_COM4 0x0D 72 | #define OV7670_COM5 0x0E 73 | #define OV7670_COM6 0x0F 74 | #define OV7670_AECH 0x10 75 | #define OV7670_CLKRC 0x11 76 | #define OV7670_COM7 0x12 77 | #define OV7670_COM8 0x13 78 | #define OV7670_COM9 0x14 79 | #define OV7670_COM10 0x15 80 | //#define OV7670_RSVD 0x16 81 | #define OV7670_HSTART 0x17 82 | #define OV7670_HSTOP 0x18 83 | #define OV7670_VSTART 0x19 84 | #define OV7670_VSTOP 0x1A 85 | #define OV7670_PSHFT 0x1B 86 | #define OV7670_MIDH 0x1C 87 | #define OV7670_MIDL 0x1D 88 | #define OV7670_MVFP 0x1E 89 | #define OV7670_LAEC 0x1F 90 | #define OV7670_ADCCTR0 0x20 91 | #define OV7670_ADCCTR1 0x21 92 | #define OV7670_ADCCTR2 0x22 93 | #define OV7670_ADCCTR3 0x23 94 | #define OV7670_AEW 0x24 95 | #define OV7670_AEB 0x25 96 | #define OV7670_VPT 0x26 97 | #define OV7670_BBIAS 0x27 98 | #define OV7670_GbBIAS 0x28 99 | //#define OV7670_RSVD 0x29 100 | #define OV7670_EXHCH 0x2A 101 | #define OV7670_EXHCL 0x2B 102 | #define OV7670_RBIAS 0x2C 103 | #define OV7670_ADVFL 0x2D 104 | #define OV7670_ADVFH 0x2E 105 | #define OV7670_YAVE 0x2F 106 | #define OV7670_HSYST 0x30 107 | #define OV7670_HSYEN 0x31 108 | #define OV7670_HREF 0x32 109 | #define OV7670_CHLF 0x33 110 | #define OV7670_ARBLM 0x34 111 | //#define OV7670_RSVD 0x35 112 | //#define OV7670_RSVD 0x36 113 | #define OV7670_ADC 0x37 114 | #define OV7670_ACOM 0x38 115 | #define OV7670_OFON 0x39 116 | #define OV7670_TSLB 0x3A 117 | #define OV7670_COM11 0x3B 118 | #define OV7670_COM12 0x3C 119 | #define OV7670_COM13 0x3D 120 | #define OV7670_COM14 0x3E 121 | #define OV7670_EDGE 0x3F 122 | #define OV7670_COM15 0x40 123 | #define OV7670_COM16 0x41 124 | #define OV7670_COM17 0x42 125 | #define OV7670_AWBC1 0x43 126 | #define OV7670_AWBC2 0x44 127 | #define OV7670_AWBC3 0x45 128 | #define OV7670_AWBC4 0x46 129 | #define OV7670_AWBC5 0x47 130 | #define OV7670_AWBC6 0x48 131 | //#define OV7670_RSVD 0x49 132 | //#define OV7670_RSVD 0x4A 133 | #define OV7670_REG4B 0x4B 134 | #define OV7670_DNSTH 0x4C 135 | //#define OV7670_RSVD 0x4D 136 | //#define OV7670_RSVD 0x4E 137 | #define OV7670_MTX1 0x4F 138 | #define OV7670_MTX2 0x50 139 | #define OV7670_MTX3 0x51 140 | #define OV7670_MTX4 0x52 141 | #define OV7670_MTX5 0x53 142 | #define OV7670_MTX6 0x54 143 | #define OV7670_BRTN 0x55 144 | #define OV7670_CONTRAS 0x56 145 | #define OV7670_CONTRASCENTER 0x57 146 | #define OV7670_MTXS 0x58 147 | //#define OV7670_RSVD 0x59 148 | //#define OV7670_RSVD 0x5A 149 | //#define OV7670_RSVD 0x5B 150 | //#define OV7670_RSVD 0x5C 151 | //#define OV7670_RSVD 0x5D 152 | //#define OV7670_RSVD 0x5E 153 | //#define OV7670_RSVD 0x5F 154 | //#define OV7670_RSVD 0x60 155 | //#define OV7670_RSVD 0x61 156 | #define OV7670_LCC1 0x62 157 | #define OV7670_LCC2 0x63 158 | #define OV7670_LCC3 0x64 159 | #define OV7670_LCC4 0x65 160 | #define OV7670_LCC5 0x66 161 | #define OV7670_MANU 0x67 162 | #define OV7670_MANV 0x68 163 | #define OV7670_GFIX 0x69 164 | #define OV7670_GGAIN 0x6A 165 | #define OV7670_DBLV 0x6B 166 | #define OV7670_AWBCTR3 0x6C 167 | #define OV7670_AWBCTR2 0x6D 168 | #define OV7670_AWBCTR1 0x6E 169 | #define OV7670_AWBCTR0 0x6F 170 | #define OV7670_SCALING_XSC 0x70 171 | #define OV7670_SCALING_YSC 0x71 172 | #define OV7670_SCALING_DCWCTR 0x72 173 | #define OV7670_SCALING_PC 0x73 174 | #define OV7670_REG74 0x74 175 | #define OV7670_REG75 0x75 176 | #define OV7670_REG76 0x76 177 | #define OV7670_REG77 0x77 178 | //#define OV7670_RSVD 0x78 179 | //#define OV7670_RSVD 0x79 180 | #define OV7670_SLOP 0x7A 181 | #define OV7670_GAM1 0x7B 182 | #define OV7670_GAM2 0x7C 183 | #define OV7670_GAM3 0x7D 184 | #define OV7670_GAM4 0x7E 185 | #define OV7670_GAM5 0x7F 186 | #define OV7670_GAM6 0x80 187 | #define OV7670_GAM7 0x81 188 | #define OV7670_GAM8 0x82 189 | #define OV7670_GAM9 0x83 190 | #define OV7670_GAM10 0x84 191 | #define OV7670_GAM11 0x85 192 | #define OV7670_GAM12 0x86 193 | #define OV7670_GAM13 0x87 194 | #define OV7670_GAM14 0x88 195 | #define OV7670_GAM15 0x89 196 | //#define OV7670_RSVD 0x8A 197 | //#define OV7670_RSVD 0x8B 198 | #define OV7670_RGB444 0x8C 199 | //#define OV7670_RSVD 0x8D 200 | //#define OV7670_RSVD 0x8E 201 | //#define OV7670_RSVD 0x8F 202 | //#define OV7670_RSVD 0x90 203 | //#define OV7670_RSVD 0x91 204 | #define OV7670_DM_LNL 0x92 205 | #define OV7670_DM_LNH 0x93 206 | #define OV7670_LCC6 0x94 207 | #define OV7670_LCC7 0x95 208 | //#define OV7670_RSVD 0x96 209 | //#define OV7670_RSVD 0x97 210 | //#define OV7670_RSVD 0x98 211 | //#define OV7670_RSVD 0x99 212 | //#define OV7670_RSVD 0x9A 213 | //#define OV7670_RSVD 0x9B 214 | //#define OV7670_RSVD 0x9C 215 | #define OV7670_BD50ST 0x9D 216 | #define OV7670_BD60ST 0x9E 217 | #define OV7670_HAECC1 0x9F 218 | #define OV7670_HAECC2 0xA0 219 | //#define OV7670_RSVD 0xA1 220 | #define OV7670_SCALING_PCLK_DELAY 0xA2 221 | //#define OV7670_RSVD 0xA3 222 | #define OV7670_NT_CTRL 0xA4 223 | #define OV7670_BD50MAX 0xA5 224 | #define OV7670_HAECC3 0xA6 225 | #define OV7670_HAECC4 0xA7 226 | #define OV7670_HAECC5 0xA8 227 | #define OV7670_HAECC6 0xA9 228 | #define OV7670_HAECC7 0xAA 229 | #define OV7670_BD60MAX 0xAB 230 | #define OV7670_STR_OPT 0xAC 231 | #define OV7670_STR_R 0xAD 232 | #define OV7670_STR_G 0xAE 233 | #define OV7670_STR_B 0xAF 234 | //#define OV7670_RSVD 0xB0 235 | #define OV7670_ABLC1 0xB1 236 | //#define OV7670_RSVD 0xB2 237 | #define OV7670_THL_DLT 0xB3 238 | //#define OV7670_RSVD 0xB4 239 | #define OV7670_THL_DLT_AREA 0xB5 240 | //#define OV7670_RSVD 0xB6 241 | //#define OV7670_RSVD 0xB7 242 | //#define OV7670_RSVD 0xB8 243 | //#define OV7670_RSVD 0xBC 244 | //#define OV7670_RSVD 0xBD 245 | #define OV7670_AD_CHB 0xBE 246 | #define OV7670_AD_CHR 0xBF 247 | #define OV7670_AD_CHGb 0xC0 248 | #define OV7670_AD_CHGr 0xC1 249 | //#define OV7670_RSVD 0xC2 250 | //#define OV7670_RSVD 0xC3 251 | //#define OV7670_RSVD 0xC4 252 | //#define OV7670_RSVD 0xC5 253 | //#define OV7670_RSVD 0xC6 254 | //#define OV7670_RSVD 0xC7 255 | //#define OV7670_RSVD 0xC8 256 | #define OV7670_SATCTR 0xC9 257 | 258 | /* Registers bit definition */ 259 | /* COM1 Register */ 260 | #define CCIR656_FORMAT 0x40 261 | #define HREF_SKIP_0 0x00 262 | #define HREF_SKIP_1 0x04 263 | #define HREF_SKIP_3 0x08 264 | 265 | /* COM2 Register */ 266 | #define SOFT_SLEEP_MODE 0x10 267 | #define ODCAP_1x 0x00 268 | #define ODCAP_2x 0x01 269 | #define ODCAP_3x 0x02 270 | #define ODCAP_4x 0x03 271 | 272 | /* COM3 Register */ 273 | #define COLOR_BAR_OUTPUT 0x80 274 | #define OUTPUT_MSB_LAS_SWAP 0x40 275 | #define PIN_REMAP_RESETB_EXPST 0x08 276 | #define RGB565_FORMAT 0x00 277 | #define RGB_OUTPUT_AVERAGE 0x04 278 | #define SINGLE_FRAME 0x01 279 | 280 | /* COM5 Register */ 281 | #define SLAM_MODE_ENABLE 0x40 282 | #define EXPOSURE_NORMAL_MODE 0x01 283 | 284 | /* COM7 Register */ 285 | #define SCCB_REG_RESET 0x80 286 | #define FORMAT_CTRL_15fpsVGA 0x00 287 | #define FORMAT_CTRL_30fpsVGA_NoVArioPixel 0x50 288 | #define FORMAT_CTRL_30fpsVGA_VArioPixel 0x60 289 | #define OUTPUT_FORMAT_RAWRGB 0x00 290 | #define OUTPUT_FORMAT_RAWRGB_DATA 0x00 291 | #define OUTPUT_FORMAT_RAWRGB_INTERP 0x01 292 | #define OUTPUT_FORMAT_YUV 0x02 293 | #define OUTPUT_FORMAT_RGB 0x03 294 | 295 | /* COM9 Register */ 296 | #define GAIN_2x 0x00 297 | #define GAIN_4x 0x10 298 | #define GAIN_8x 0x20 299 | #define GAIN_16x 0x30 300 | #define GAIN_32x 0x40 301 | #define GAIN_64x 0x50 302 | #define GAIN_128x 0x60 303 | #define DROP_VSYNC 0x04 304 | #define DROP_HREF 0x02 305 | 306 | /* COM10 Register */ 307 | #define RESETb_REMAP_SLHS 0x80 308 | #define HREF_CHANGE_HSYNC 0x40 309 | #define PCLK_ON 0x00 310 | #define PCLK_OFF 0x20 311 | #define PCLK_POLARITY_REV 0x10 312 | #define HREF_POLARITY_REV 0x08 313 | #define RESET_ENDPOINT 0x04 314 | #define VSYNC_NEG 0x02 315 | #define HSYNC_NEG 0x01 316 | 317 | /* TSLB Register */ 318 | #define PCLK_DELAY_0 0x00 319 | #define PCLK_DELAY_2 0x40 320 | #define PCLK_DELAY_4 0x80 321 | #define PCLK_DELAY_6 0xC0 322 | #define OUTPUT_BITWISE_REV 0x20 323 | #define UV_NORMAL 0x00 324 | #define UV_FIXED 0x10 325 | #define YUV_SEQ_YUYV 0x00 326 | #define YUV_SEQ_YVYU 0x02 327 | #define YUV_SEQ_VYUY 0x04 328 | #define YUV_SEQ_UYVY 0x06 329 | #define BANDING_FREQ_50 0x02 330 | 331 | #define RGB_NORMAL 0x00 332 | #define RGB_565 0x10 333 | #define RGB_555 0x30 334 | 335 | /* Exported macro ------------------------------------------------------------*/ 336 | /* Exported functions ------------------------------------------------------- */ 337 | 338 | void DCMI_Config(void); 339 | void MCO1_Init(void); 340 | uint8_t DCMI_OV7670_Init(void); 341 | uint8_t DCMI_OV7670_ReadID(OV7670_IDTypeDef* OV7670ID); 342 | void OV7670_config_window(uint16_t startx, uint16_t starty, uint16_t width, uint16_t height); 343 | 344 | #endif /* __DCMI_OV7670_H */ 345 | 346 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 347 | -------------------------------------------------------------------------------- /camera/usart.c: -------------------------------------------------------------------------------- 1 | #include "usart.h" 2 | 3 | #ifdef __GNUC__ 4 | /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf 5 | set to 'Yes') calls __io_putchar() */ 6 | #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) 7 | #else 8 | #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) 9 | #endif /* __GNUC__ */ 10 | 11 | void USART_NVIC_Config(void); 12 | 13 | /******************************************************************************* 14 | * Function Name : USART_Configuration 15 | * Description : Configure Open407V_USART 16 | * Input : None 17 | * Output : None 18 | * Return : None 19 | * Attention : None 20 | *******************************************************************************/ 21 | 22 | void USART3_Transmit(uint8_t ch_data) 23 | { 24 | // Loop until the end of transmission 25 | while (USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET) 26 | { 27 | ; 28 | } 29 | USART_SendData(USART3, (uint8_t)ch_data); 30 | } 31 | 32 | 33 | 34 | void USART_Configuration(void) 35 | { 36 | GPIO_InitTypeDef GPIO_InitStructure; 37 | USART_InitTypeDef USART_InitStructure; 38 | 39 | RCC_AHB1PeriphClockCmd(Open407V_USART_TX_GPIO_CLK,ENABLE); 40 | RCC_AHB1PeriphClockCmd(Open407V_USART_RX_GPIO_CLK,ENABLE); 41 | 42 | RCC_APB1PeriphClockCmd(Open407V_USART_CLK,ENABLE); 43 | 44 | 45 | GPIO_PinAFConfig(Open407V_USART_TX_GPIO_PORT, Open407V_USART_TX_SOURCE, Open407V_USART_TX_AF); 46 | GPIO_PinAFConfig(Open407V_USART_RX_GPIO_PORT, Open407V_USART_RX_SOURCE, Open407V_USART_RX_AF); 47 | 48 | /* 49 | * Open407V_USART_TX -> PC10 , Open407V_USART_RX -PC11 50 | */ 51 | GPIO_InitStructure.GPIO_Pin = Open407V_USART_TX_PIN; 52 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 53 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 54 | 55 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 56 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 57 | GPIO_Init(Open407V_USART_TX_GPIO_PORT, &GPIO_InitStructure); 58 | 59 | GPIO_InitStructure.GPIO_Pin = Open407V_USART_RX_PIN; 60 | GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; 61 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; 62 | GPIO_Init(Open407V_USART_TX_GPIO_PORT, &GPIO_InitStructure); 63 | 64 | /* 65 | USARTx configured as follow: 66 | - BaudRate = 115200 baud 67 | - Word Length = 8 Bits 68 | - One Stop Bit 69 | - No parity 70 | - Hardware flow control disabled (RTS and CTS signals) 71 | - Receive and transmit 72 | */ 73 | 74 | USART_InitStructure.USART_BaudRate = 115200; 75 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 76 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 77 | USART_InitStructure.USART_Parity = USART_Parity_No; 78 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 79 | USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 80 | USART_Init(Open407V_USART, &USART_InitStructure); 81 | /* Enable the Open407V_USART Transmit interrupt: this interrupt is generated when the 82 | Open407V_USART transmit data register is empty */ 83 | // USART_NVIC_Config(); 84 | // USART_ITConfig(Open407V_USART,USART_IT_TC,ENABLE); 85 | 86 | USART_Cmd(Open407V_USART, ENABLE); 87 | 88 | 89 | } 90 | 91 | void USART_NVIC_Config(void) 92 | { 93 | NVIC_InitTypeDef NVIC_InitStructure; 94 | 95 | /* Enable the USARTx Interrupt */ 96 | NVIC_InitStructure.NVIC_IRQChannel = Open407V_USART_IRQn; 97 | NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; 98 | NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; 99 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 100 | NVIC_Init(&NVIC_InitStructure); 101 | } 102 | 103 | /* Use no semihosting */ 104 | #if 1 105 | #pragma import(__use_no_semihosting) 106 | struct __FILE 107 | { 108 | int handle; 109 | }; 110 | FILE __stdout; 111 | 112 | _sys_exit(int x) 113 | { 114 | x = x; 115 | } 116 | #endif 117 | 118 | /** 119 | * @brief Retargets the C library printf function to the USART. 120 | * @param None 121 | * @retval None 122 | */ 123 | PUTCHAR_PROTOTYPE 124 | { 125 | /* Place your implementation of fputc here */ 126 | /* e.g. write a character to the USART */ 127 | USART_SendData(Open407V_USART, (uint8_t) ch); 128 | 129 | /* Loop until the end of transmission */ 130 | while (USART_GetFlagStatus(Open407V_USART, USART_FLAG_TC) == RESET) 131 | {} 132 | 133 | return ch; 134 | } 135 | -------------------------------------------------------------------------------- /camera/usart.h: -------------------------------------------------------------------------------- 1 | #ifndef _USART_H 2 | #define _USART_H 3 | 4 | #include 5 | #include "stm32f4xx.h" 6 | #include "config.h" 7 | 8 | void USART_Configuration(void); 9 | void USART_NVIC_Config(void); 10 | void USART3_Transmit(uint8_t ch_data); 11 | #endif /*_USART_H*/ 12 | -------------------------------------------------------------------------------- /cmtypes.h: -------------------------------------------------------------------------------- 1 | #ifndef __cmtypes_H 2 | #define __cmtypes_H 3 | 4 | #include "stdint.h" 5 | 6 | typedef enum { 7 | DEV_Result_Ok, /*!< Everything OK */ 8 | DEV_Result_Error /*!< Error occurred */ 9 | } DEV_Result_t; 10 | 11 | typedef struct { 12 | int16_t X; /*!< X axis rotation */ 13 | int16_t Y; /*!< Y axis rotation */ 14 | int16_t Z; /*!< Z axis rotation */ 15 | } XYZ_t; 16 | 17 | #define bool _Bool 18 | #define FALSE 0 19 | #define TRUE !FALSE 20 | 21 | //Taras Ivaniv 22 | 23 | #endif /*__ cmtypes_H */ 24 | 25 | -------------------------------------------------------------------------------- /dcmi.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tarasii/stm32f429_ov7670_lcd_dcmi/d076d9dd047b62ea97d4777d762e4587c305b195/dcmi.c -------------------------------------------------------------------------------- /dcmi.h: -------------------------------------------------------------------------------- 1 | /* Define to prevent recursive inclusion -------------------------------------*/ 2 | #ifndef __DCMI_H 3 | #define __DCMI_H 4 | 5 | /* Includes ------------------------------------------------------------------*/ 6 | #include "stm32f4xx.h" 7 | 8 | 9 | #define DCMI_DR_ADDRESS 0x50050028 10 | //#define DCMI_BUF_ADDRESS 0xD0200000 11 | #define DCMI_BUF_ADDRESS 0xD00EA600 12 | //#define DCMI_BUF_ADDRESS 0xD0000000 13 | 14 | #define FSMC_LCD_ADDRESS 0x60020000 15 | 16 | 17 | typedef enum 18 | { 19 | img_160x120 = 0x01, /* Image 160x120 Size */ 20 | img_176x144 = 0x02, /* Image 176x144 Size (QCIF) */ 21 | img_320x240 = 0x03, /* Image 320x240 Size (QVGA) */ 22 | img_352x288 = 0x04, /* Image 352x288 Size (CIF) */ 23 | img_408x304 = 0x05, /* Image 408x304 Size */ 24 | img_480x320 = 0x06, /* Image 480x320 Size (HVGA)*/ 25 | img_640x480 = 0x07, /* Image 640x480 Size (VGA) */ 26 | img_800x600 = 0x08 /* Image 800x600 Size (SVGA) */ 27 | }ImageResolution_TypeDef; 28 | 29 | /* Exported types ------------------------------------------------------------*/ 30 | 31 | 32 | /* Exported constants --------------------------------------------------------*/ 33 | 34 | 35 | /* Uncomment the line corresponding to the camera resolution */ 36 | //#define QVGA_SIZE /*320x240 */ 37 | //#define VGA_SIZE /* 640x480 */ 38 | 39 | 40 | 41 | /* Exported macro ------------------------------------------------------------*/ 42 | /* Exported functions ------------------------------------------------------- */ 43 | 44 | 45 | void DCMI_GPIO_Init(void); 46 | void DCMI_DMA_Init(uint32_t bufsize); 47 | 48 | uint32_t Resolution_GetBufSize(ImageResolution_TypeDef ImageRes); 49 | uint16_t Resolution_GetWidth(ImageResolution_TypeDef ImageRes); 50 | uint16_t Resolution_GetHeight(ImageResolution_TypeDef ImageRes); 51 | 52 | 53 | #endif /* __DCMI_H */ 54 | 55 | -------------------------------------------------------------------------------- /i2c.c: -------------------------------------------------------------------------------- 1 | 2 | #include "I2C.h" 3 | 4 | #define Timed(x) Timeout = I2C_FLAG_TIMEOUT_; while (x) { if (Timeout-- == 0) goto errReturn;} 5 | 6 | /* 7 | * See AN2824 STM32F10xxx I2C optimized examples 8 | * 9 | * This code implements polling based solution 10 | * 11 | */ 12 | 13 | /** 14 | * Names of events used in stdperipheral library 15 | * 16 | * I2C_EVENT_MASTER_MODE_SELECT : EV5 17 | * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 18 | * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 19 | * I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 20 | * I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 21 | * I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 22 | * 23 | **/ 24 | 25 | 26 | 27 | /* 28 | * Read process is documented in RM008 29 | * 30 | * There are three cases -- read 1 byte AN2824 Figure 2 31 | * read 2 bytes AN2824 Figure 2 32 | * read >2 bytes AN2824 Figure 1 33 | */ 34 | 35 | Status I2C_Read(I2C_TypeDef* I2Cx, uint8_t *buf, uint32_t nbyte, uint8_t SlaveAddress) 36 | { 37 | __IO uint32_t Timeout = 0; 38 | 39 | // I2Cx->CR2 |= I2C_IT_ERR; interrupts for errors 40 | 41 | if (!nbyte) 42 | return Success; 43 | 44 | // Wait for idle I2C interface 45 | Timed(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY)); 46 | 47 | // Enable Acknowledgement, clear POS flag 48 | I2C_AcknowledgeConfig(I2Cx, ENABLE); 49 | //I2C_NACKPositionConfig(I2Cx, I2C_NACKPosition_Current); 50 | 51 | // Intiate Start Sequence (wait for EV5 52 | I2C_GenerateSTART(I2Cx, ENABLE); 53 | Timed(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT)); 54 | 55 | // Send Address 56 | I2C_Send7bitAddress(I2Cx, SlaveAddress, I2C_Direction_Receiver); 57 | 58 | // EV6 59 | Timed(!I2C_GetFlagStatus(I2Cx, I2C_FLAG_ADDR)); 60 | //Timed(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)); 61 | 62 | if (nbyte == 1) { 63 | 64 | // Clear Ack bit 65 | I2C_AcknowledgeConfig(I2Cx, DISABLE); 66 | 67 | // EV6_1 -- must be atomic -- Clear ADDR, generate STOP 68 | (void) I2Cx->SR2; 69 | //Timed(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_RECEIVED)); 70 | I2C_GenerateSTOP(I2Cx,ENABLE); 71 | 72 | // Receive data EV7 73 | Timed(!I2C_GetFlagStatus(I2Cx, I2C_FLAG_RXNE)); 74 | 75 | *buf++ = I2C_ReceiveData(I2Cx); 76 | 77 | } 78 | else if (nbyte == 2) { 79 | 80 | // EV6_1 -- must be atomic and in this order 81 | (void) I2Cx->SR2; // Clear ADDR flag 82 | I2C_AcknowledgeConfig(I2Cx, DISABLE); // Clear Ack bit 83 | 84 | // EV7_3 -- Wait for BTF, program stop, read data twice 85 | Timed(!I2C_GetFlagStatus(I2Cx, I2C_FLAG_BTF)); 86 | 87 | I2C_GenerateSTOP(I2Cx,ENABLE); 88 | *buf++ = I2Cx->DR; 89 | 90 | *buf++ = I2Cx->DR; 91 | 92 | } 93 | else { 94 | 95 | 96 | (void) I2Cx->SR2; // Clear ADDR flag 97 | while (nbyte-- != 3) 98 | { 99 | // EV7 -- cannot guarantee 1 transfer completion time, wait for BTF 100 | // instead of RXNE 101 | Timed(!I2C_GetFlagStatus(I2Cx, I2C_FLAG_BTF)); 102 | *buf++ = I2C_ReceiveData(I2Cx); 103 | } 104 | 105 | Timed(!I2C_GetFlagStatus(I2Cx, I2C_FLAG_BTF)); 106 | 107 | // EV7_2 -- Figure 1 has an error, doesn't read N-2 ! 108 | I2C_AcknowledgeConfig(I2Cx, DISABLE); // clear ack bit 109 | 110 | *buf++ = I2C_ReceiveData(I2Cx); // receive byte N-2 111 | I2C_GenerateSTOP(I2Cx,ENABLE); // program stop 112 | 113 | *buf++ = I2C_ReceiveData(I2Cx); // receive byte N-1 114 | 115 | // wait for byte N 116 | Timed(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_RECEIVED)); 117 | *buf++ = I2C_ReceiveData(I2Cx); 118 | 119 | nbyte = 0; 120 | 121 | } 122 | 123 | // Wait for stop 124 | Timed(I2C_GetFlagStatus(I2Cx, I2C_FLAG_STOPF)); 125 | I2C2->SR1 |= (uint16_t)0x0400; 126 | 127 | return Success; 128 | 129 | errReturn: 130 | 131 | // Any cleanup here 132 | return Error; 133 | 134 | } 135 | 136 | /* 137 | * Read buffer of bytes -- AN2824 Figure 3 138 | */ 139 | 140 | Status I2C_Write(I2C_TypeDef* I2Cx, const uint8_t* buf, uint32_t nbyte, uint8_t SlaveAddress) 141 | { 142 | __IO uint32_t Timeout = 0; 143 | __IO uint32_t timeout = 0; 144 | 145 | /* Enable Error IT (used in all modes: DMA, Polling and Interrupts */ 146 | // I2Cx->CR2 |= I2C_IT_ERR; 147 | 148 | if (nbyte){ 149 | Timed(I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY)); 150 | 151 | // Intiate Start Sequence 152 | I2C_GenerateSTART(I2Cx, ENABLE); 153 | Timed(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT)); 154 | 155 | // Send Address EV5 156 | I2C_Send7bitAddress(I2Cx, SlaveAddress, I2C_Direction_Transmitter); 157 | Timed(!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)); 158 | 159 | // EV6 160 | // Write first byte EV8_1 161 | I2C_SendData(I2Cx, *buf++); 162 | 163 | while (--nbyte) { 164 | 165 | // wait on BTF 166 | Timed(!I2C_GetFlagStatus(I2Cx, I2C_FLAG_BTF)); 167 | I2C_SendData(I2Cx, *buf++); 168 | } 169 | 170 | Timed(!I2C_GetFlagStatus(I2Cx, I2C_FLAG_BTF)); 171 | 172 | //I2Cx->SR1 |= (uint16_t)0x0400; 173 | I2C_GenerateSTOP(I2Cx, ENABLE); 174 | Timed(I2C_GetFlagStatus(I2Cx, I2C_FLAG_STOPF)); 175 | 176 | } 177 | 178 | return Success; 179 | errReturn: 180 | return Error; 181 | } 182 | 183 | 184 | void I2C_Init_(I2C_TypeDef* I2Cx) 185 | { 186 | 187 | GPIO_InitTypeDef GPIO_InitStructure; 188 | I2C_InitTypeDef I2C_InitStructure; 189 | 190 | // Enable GPIOB clocks 191 | //RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); 192 | 193 | 194 | // Configure I2C clock and GPIO 195 | GPIO_StructInit(&GPIO_InitStructure); 196 | if (I2Cx == I2C1){ 197 | 198 | /* GPIO clock enable */ 199 | RCC_AHB1PeriphClockCmd(I2C1_GPIO_CLK, ENABLE); 200 | 201 | /* I2C1 clock enable */ 202 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); 203 | 204 | /* I2C1 SDA and SCL configuration */ 205 | GPIO_InitStructure.GPIO_Pin = I2C1_SCL_PIN | I2C1_SDA_PIN; 206 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 207 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 208 | GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; 209 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 210 | GPIO_Init(I2C1_GPIO_PORT, &GPIO_InitStructure); 211 | 212 | GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SDA_SOURCE, GPIO_AF_I2C1); 213 | GPIO_PinAFConfig(I2C1_GPIO_PORT, I2C1_SCL_SOURCE, GPIO_AF_I2C1); 214 | 215 | /* I2C1 Reset */ 216 | //RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); 217 | //RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); 218 | 219 | } else { 220 | 221 | /* GPIO clock enable */ 222 | RCC_AHB1PeriphClockCmd(I2C2_GPIO_CLK, ENABLE); 223 | 224 | /* I2C2 clock enable */ 225 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE); 226 | 227 | /* I2C1 SDA and SCL configuration */ 228 | GPIO_InitStructure.GPIO_Pin = I2C2_SCL_PIN | I2C2_SDA_PIN; 229 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 230 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 231 | GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; 232 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 233 | GPIO_Init(I2C2_GPIO_PORT, &GPIO_InitStructure); 234 | 235 | GPIO_PinAFConfig(I2C2_GPIO_PORT, I2C2_SCL_SOURCE, GPIO_AF_I2C2); 236 | GPIO_PinAFConfig(I2C2_GPIO_PORT, I2C2_SDA_SOURCE, GPIO_AF_I2C2); 237 | 238 | /* I2C2 Reset */ 239 | //RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); 240 | //RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); 241 | 242 | } 243 | 244 | I2C_DeInit(I2Cx); 245 | /* Configure I2Cx */ 246 | I2C_StructInit(&I2C_InitStructure); 247 | I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; 248 | I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; 249 | I2C_InitStructure.I2C_OwnAddress1 = I2C_OWN_ADDRESS7; 250 | I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; 251 | I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; 252 | I2C_InitStructure.I2C_ClockSpeed = I2C_CLK_SPEED; 253 | 254 | I2C_Init(I2Cx, &I2C_InitStructure); 255 | I2C_Cmd(I2Cx, ENABLE); 256 | I2C_AcknowledgeConfig(I2Cx, ENABLE); 257 | 258 | } 259 | 260 | void I2C_DeInit_(I2C_TypeDef* I2Cx) 261 | { 262 | 263 | if (I2Cx == I2C1){ 264 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); 265 | } else { 266 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); 267 | } 268 | 269 | I2C_DeInit(I2Cx); 270 | I2C_Cmd(I2Cx, DISABLE); 271 | I2C_AcknowledgeConfig(I2Cx, DISABLE); 272 | 273 | } 274 | 275 | -------------------------------------------------------------------------------- /i2c.h: -------------------------------------------------------------------------------- 1 | #ifndef I2C_H 2 | #define I2C_H 3 | 4 | #include "stm32f4xx.h" 5 | 6 | //+------+------+------+ 7 | //| I2C1 | 8 | //+------+------+------+ 9 | //| SDA | SLC | SMBA | 10 | //+------+------+------+ 11 | //| PB6 | PB7 | PB5 | 12 | //| PB8 | PB9 | | 13 | //+------+------+------+ 14 | //| I2C2 | 15 | //+------+------+------+ 16 | //| PB10 | PB11 | PB12 | 17 | //+------+------+------+ 18 | 19 | #define I2C1_SDA_PIN GPIO_Pin_6 20 | #define I2C1_SDA_SOURCE GPIO_PinSource6 21 | #define I2C1_SCL_PIN GPIO_Pin_7 22 | #define I2C1_SCL_SOURCE GPIO_PinSource7 23 | 24 | #define I2C1_GPIO_PORT GPIOB 25 | #define I2C1_GPIO_CLK RCC_AHB1Periph_GPIOB 26 | 27 | 28 | #define I2C2_SDA_PIN GPIO_Pin_11 29 | #define I2C2_SDA_SOURCE GPIO_PinSource11 30 | #define I2C2_SCL_PIN GPIO_Pin_10 31 | #define I2C2_SCL_SOURCE GPIO_PinSource10 32 | 33 | #define I2C2_GPIO_PORT GPIOB 34 | #define I2C2_GPIO_CLK RCC_AHB1Periph_GPIOB 35 | 36 | 37 | #define I2C_CLK_SPEED 10000 //100000 38 | #define I2C_OWN_ADDRESS7 0xF 39 | #define I2C_FLAG_TIMEOUT_ 10000 40 | 41 | typedef enum {Error = 0, Success = !Error } Status; 42 | 43 | 44 | Status I2C_Read(I2C_TypeDef* I2Cx, uint8_t* buf, uint32_t nbuf, uint8_t SlaveAddress); 45 | Status I2C_Write(I2C_TypeDef* I2Cx, const uint8_t* buf, uint32_t nbuf, uint8_t SlaveAddress); 46 | void I2C_Init_(I2C_TypeDef* I2Cx); 47 | void I2C_DeInit_(I2C_TypeDef* I2Cx); 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/USART_Printf/main.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief Main program body 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *
© COPYRIGHT 2013 STMicroelectronics
12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | 30 | #include "main.h" 31 | #include "usart.h" 32 | #include "dcmi_OV7670.h" 33 | #include "32f429_lcd.h" 34 | #include "32f429_sdram.h" 35 | #include "pin.h" 36 | 37 | /** @addtogroup STM32F4xx_StdPeriph_Examples 38 | * @{ 39 | */ 40 | 41 | /** @addtogroup USART_Printf 42 | * @{ 43 | */ 44 | 45 | void Delay(__IO uint32_t nTime); 46 | void TimingDelay_Decrement(void); 47 | static __IO uint32_t TimingDelay; 48 | 49 | //void LCD_DisplayByte(uint16_t lnnum, uint16_t pos, uint8_t byte); 50 | //void LCD_DisplayRawLine(uint16_t lnnum, uint8_t *buf); 51 | //void LCD_DisplayBuf(uint8_t *buf, ImageResolution_TypeDef ImageRes); 52 | 53 | 54 | uint8_t jpg_flag=0; 55 | uint8_t key_flag=0; 56 | 57 | uint8_t frame_flag=0; 58 | uint8_t dcim_flag=0; 59 | uint16_t lncnt=0; 60 | uint16_t lnmax=0; 61 | uint16_t fps=0; 62 | 63 | __IO uint16_t systick_ms = 0, toggle_ms = 0; 64 | 65 | 66 | #define GPIO_WAKEUP_CLK RCC_AHB1Periph_GPIOA 67 | #define GPIO_WAKEUP_PORT GPIOA 68 | #define GPIO_WAKEUP_PIN GPIO_Pin_0 69 | 70 | /* Private functions ---------------------------------------------------------*/ 71 | 72 | /** 73 | * @brief Main program 74 | * @param None 75 | * @retval None 76 | */ 77 | int main(void) 78 | { 79 | /*!< At this stage the microcontroller clock setting is already configured, 80 | this is done through SystemInit() function which is called from startup 81 | files (startup_stm32f40_41xxx.s/startup_stm32f427_437xx.s/startup_stm32f429_439xx.s) 82 | before to branch to application main. 83 | To reconfigure the default setting of SystemInit() function, refer to 84 | system_stm32f4xx.c file. 85 | */ 86 | GPIO_InitTypeDef GPIO_InitStructure; 87 | //ImageResolution_TypeDef cur_img_res; 88 | //OV2640_IDTypeDef OV2640ID; 89 | OV7670_IDTypeDef OV7670ID; 90 | RCC_ClocksTypeDef SYS_Clocks; 91 | uint8_t temp, tmp2; 92 | char strDisp[25]; 93 | //uint32_t i=0; 94 | 95 | if (SysTick_Config(SystemCoreClock / 1000)) 96 | { 97 | /* Capture error */ 98 | while (1); 99 | } 100 | /* USART configuration */ 101 | USART_Config(); 102 | 103 | /* Output a message on Hyperterminal using printf function */ 104 | 105 | RCC_GetClocksFreq(&SYS_Clocks); 106 | 107 | USART_SendData(USART1, (uint8_t) 'Z'); 108 | 109 | printf("\r\nHSE:%dM\r\n",HSE_VALUE/1000000); 110 | printf("\r\nSYSCLK:%dM\r\n",SYS_Clocks.SYSCLK_Frequency/1000000); 111 | printf("HCLK:%dM\r\n",SYS_Clocks.HCLK_Frequency/1000000); 112 | printf("PCLK1:%dM\r\n",SYS_Clocks.PCLK1_Frequency/1000000); 113 | printf("PCLK2:%dM\r\n",SYS_Clocks.PCLK2_Frequency/1000000); 114 | printf("\n\r DCMI Example\n\r\n\r"); 115 | 116 | 117 | RCC_APB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); 118 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; 119 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 120 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 121 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 122 | GPIO_InitStructure.GPIO_Pin = GPIO_WAKEUP_PIN; 123 | GPIO_Init(GPIO_WAKEUP_PORT, &GPIO_InitStructure); 124 | 125 | /* leds */ 126 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE); 127 | GPIO_InitStructure.GPIO_Pin = LED1_Pin | LED2_Pin | LED3_Pin | LED4_Pin; 128 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 129 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; 130 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 131 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; 132 | GPIO_Init(LED1_GPIO_Port, &GPIO_InitStructure); 133 | 134 | GPIO_LOW(LED1_GPIO_Port, LED1_Pin); 135 | GPIO_LOW(LED2_GPIO_Port, LED2_Pin); 136 | GPIO_LOW(LED3_GPIO_Port, LED3_Pin); 137 | GPIO_LOW(LED4_GPIO_Port, LED4_Pin); 138 | 139 | LCD_Init(); 140 | 141 | /* LCD Layer initialization */ 142 | LCD_LayerInit(); 143 | 144 | printf("LAYER0:%x (%dx%d)\r\n", LCD_FRAME_BUFFER, LCD_PIXEL_WIDTH, LCD_PIXEL_HEIGHT); 145 | printf("LAYER1:%x (%dx%d)\r\n", LCD_FRAME_BUFFER+BUFFER_OFFSET, LCD_LAYER2_PIXEL_WIDTH, LCD_LAYER2_PIXEL_HEIGHT); 146 | 147 | 148 | /* Enable the LTDC */ 149 | LTDC_Cmd(ENABLE); 150 | 151 | 152 | LCD_SetLayer(LCD_BACKGROUND_LAYER); 153 | //LCD_SetLayer(LCD_FOREGROUND_LAYER); 154 | LCD_Clear(LCD_COLOR_BLACK); 155 | 156 | LCD_SetTextColor(LCD_COLOR_GREEN); 157 | //cur_img_res = img_160x120; 158 | //cur_img_res = img_408x304; 159 | //cur_img_res = img_480x320; 160 | //cur_img_res = img_640x480; 161 | //cur_img_res = img_800x600; 162 | //LCD_DrawRect(196-1, 20-1, Resolution_GetHeight(cur_img_res)+1, Resolution_GetWidth(cur_img_res)+1); 163 | //LCD_DrawRect(LCD_LAYER2_X0-1, LCD_LAYER2_Y0-1, LCD_LAYER2_PIXEL_HEIGHT+1, LCD_LAYER2_PIXEL_WIDTH+1); 164 | 165 | //LCD_SetLayer(LCD_FOREGROUND_LAYER); 166 | LCD_SetFont(&Font8x12); 167 | LCD_SetTextColor(LCD_COLOR_GREEN); 168 | LCD_SetBackColor(LCD_COLOR_BLACK); 169 | LCD_DisplayStringLine(LINE(0), (uint8_t*)"OV7670 test"); 170 | //LCD_DisplayStringLine(LINE(1), (uint8_t*)" test "); 171 | //LCD_DrawRect(0,0,LCD_PIXEL_HEIGHT-1,LCD_PIXEL_WIDTH-1); 172 | 173 | //OV2640_Init(Resolution_GetBufSize(cur_img_res)/4); 174 | //OV2640_Init(Resolution_GetBufSize(cur_img_res)/8); 175 | //OV2640_Init(640*480/8); 176 | //OV2640_Init(800*300/4); 177 | // DCMI_OV7670_Init(); 178 | // 179 | // DCMI_OV7670_ReadID(&OV7670ID); 180 | // printf("OV7670 ID:0x%x 0x%x 0x%x 0x%x\r\n", 181 | // OV7670ID.Manufacturer_ID1, OV7670ID.Manufacturer_ID2, OV7670ID.PID, OV7670ID.Version); 182 | 183 | 184 | Delay(1); 185 | 186 | if(DCMI_OV7670_Init()==0) 187 | { 188 | DCMI_OV7670_ReadID(&OV7670ID); 189 | sprintf(strDisp, "ID:0x%02x%02x ", OV7670ID.Manufacturer_ID1, OV7670ID.Manufacturer_ID2); 190 | LCD_DisplayStringLine(LINE(1), (uint8_t*)strDisp); 191 | 192 | if(OV7670ID.Manufacturer_ID1==0x7f && OV7670ID.Manufacturer_ID2==0xa2 193 | && OV7670ID.Version==0x73 && OV7670ID.PID==0x76){ 194 | printf("OV7670 ID:0x%x 0x%x 0x%x 0x%x\r\n", 195 | OV7670ID.Manufacturer_ID1, OV7670ID.Manufacturer_ID2, OV7670ID.PID, OV7670ID.Version); 196 | 197 | 198 | // OV2640_Config(cur_img_res); 199 | // OV2640_BrightnessConfig(0x20); 200 | // OV2640_AutoExposure(2); 201 | // Delay(10); 202 | // 203 | // DCMI_SingleRandomWrite(OV2640_DSP_RA_DLMT, 0x0); 204 | 205 | // DCMI_SingleRandomRead(OV2640_DSP_CTRL, &temp); 206 | // printf("DCMI DSP_CTRL:%02x\r\n", temp); 207 | // DCMI_SingleRandomRead(OV2640_DSP_VHYX, &tmp2); 208 | // printf("DCMI DSP_VHYX:%02x\r\n", tmp2); 209 | // DCMI_SingleRandomRead(OV2640_DSP_HSIZE, &temp); 210 | // printf("DCMI DSP_HSIZE:%02x %d\r\n", temp, ((tmp2 & 0x08) << 5 | temp)*4); 211 | // DCMI_SingleRandomRead(OV2640_DSP_VSIZE, &temp); 212 | // printf("DCMI DSP_VSIZE:%02x %d\r\n", temp, ((tmp2 & 0x80) << 1 | temp)*4); 213 | 214 | // DCMI_SingleRandomRead(OV2640_DSP_HSIZE8, &temp); 215 | // printf("DCMI DSP_HSIZE8:%02x %d\r\n", temp, temp*8); 216 | // DCMI_SingleRandomRead(OV2640_DSP_VSIZE8, &temp); 217 | // printf("DCMI DSP_VSIZE8:%02x %d\r\n", temp, temp*8); 218 | 219 | // DCMI_SingleRandomRead(OV2640_DSP_ZMOW, &temp); 220 | // printf("DCMI DSP_ZMOW:%02x %d\r\n", temp, temp*4); 221 | // DCMI_SingleRandomRead(OV2640_DSP_ZMOH, &tmp2); 222 | // printf("DCMI DSP_ZMOH:%02x %d\r\n", tmp2, tmp2*4); 223 | 224 | // sprintf(strDisp, "%dx%d ", temp*4, tmp2*4); 225 | // LCD_DisplayStringLine(LINE(2), (uint8_t*)strDisp); 226 | 227 | } 228 | else{ 229 | printf("OV7670 ID is Error!\r\n"); 230 | } 231 | } 232 | 233 | 234 | RCC_APB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); 235 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; 236 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 237 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 238 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 239 | GPIO_InitStructure.GPIO_Pin = GPIO_WAKEUP_PIN; 240 | GPIO_Init(GPIO_WAKEUP_PORT, &GPIO_InitStructure); 241 | 242 | DMA_Cmd(DMA2_Stream1, ENABLE); 243 | DCMI_Cmd(ENABLE); 244 | DCMI_CaptureCmd(ENABLE); 245 | 246 | // DCMI_SingleRandomWrite(0x71, 0x80); 247 | 248 | while (1) 249 | { 250 | 251 | if ((systick_ms - toggle_ms) > 1000) 252 | { 253 | toggle_ms = systick_ms; 254 | sprintf(strDisp, "ln:%d ", lnmax); 255 | LCD_DisplayStringLine(LINE(3), (uint8_t*)strDisp); 256 | 257 | sprintf(strDisp, "fps:%d ", fps); 258 | LCD_DisplayStringLine(LINE(4), (uint8_t*)strDisp); 259 | 260 | fps=0; 261 | } 262 | 263 | // if(GPIO_ReadInputDataBit(GPIO_WAKEUP_PORT,GPIO_WAKEUP_PIN)) 264 | // { 265 | // key_flag = 1; 266 | 267 | // DMA_Cmd(DMA2_Stream1, ENABLE); 268 | // DCMI_Cmd(ENABLE); 269 | // DCMI_CaptureCmd(ENABLE); 270 | // //printf("key_flag =1 \r\n"); 271 | // while(GPIO_ReadInputDataBit(GPIO_WAKEUP_PORT,GPIO_WAKEUP_PIN)); 272 | // } 273 | // 274 | // 275 | // 276 | if(jpg_flag)//&&key_flag 277 | { 278 | // DCMI_Cmd(DISABLE); 279 | // DCMI_CaptureCmd(DISABLE); 280 | // DMA_Cmd(DMA2_Stream1, DISABLE); 281 | 282 | jpg_flag = 0; 283 | // key_flag = 0; 284 | // 285 | //// LCD_Clear(LCD_COLOR_BLACK); 286 | //// //LCD_DisplayStringLine(LINE(0), (uint8_t*)"0001020304050607080910111213141516171819202122232425262728293031"); 287 | 288 | //// for (i = 0; i < 40; i++){ 289 | //// //LCD_DisplayRawLine(LINE(i), JpegBuffer+(16*i)); 290 | //// //LCD_DisplayRawLine(LINE(i+1), (uint8_t *)(DCMI_DR_ADDRESS +32*i)); 291 | //// LCD_DisplayRawLine(LINE(i+1), (uint8_t *)(0xD0200000 +32*i)); 292 | //// } 293 | 294 | // //LCD_DisplayBuf( (uint8_t *) (DCMI_BUF_ADDRESS), cur_img_res); 295 | // printf("Frame!"); 296 | 297 | // DMA_Cmd(DMA2_Stream1, ENABLE); 298 | // DCMI_Cmd(ENABLE); 299 | // DCMI_CaptureCmd(ENABLE); 300 | // 301 | //// jpg_flag = 1; 302 | //// } else { 303 | //// if (key_flag) { 304 | //// }else { 305 | //// key_flag = 1; 306 | //// DMA_Cmd(DMA2_Stream1, ENABLE); 307 | //// DCMI_Cmd(ENABLE); 308 | //// DCMI_CaptureCmd(ENABLE); 309 | //// } 310 | } 311 | if (frame_flag) { 312 | frame_flag = 0; 313 | //LCD_DisplayBuf( (uint8_t *) (DCMI_BUF_ADDRESS), cur_img_res); 314 | } 315 | } 316 | } 317 | 318 | void Delay(__IO uint32_t nTime) 319 | { 320 | TimingDelay = nTime; 321 | 322 | while(TimingDelay != 0) 323 | {} 324 | } 325 | 326 | void TimingDelay_Decrement(void) 327 | { 328 | if (TimingDelay != 0x00) 329 | { 330 | TimingDelay--; 331 | } 332 | systick_ms++; 333 | } 334 | 335 | //void LCD_DisplayByte(uint16_t lnnum, uint16_t pos, uint8_t byte) 336 | //{ 337 | // uint8_t tmp; 338 | // tmp = byte & 0x0f; 339 | // if (tmp > 9){ 340 | // tmp = 0x37 + tmp; 341 | // } else { 342 | // tmp = 0x30 + tmp; 343 | // } 344 | // LCD_DisplayChar(lnnum, pos, tmp); 345 | // tmp = (byte & 0xf0)>>4; 346 | // if (tmp > 9){ 347 | // tmp = 0x37 + tmp; 348 | // } else { 349 | // tmp = 0x30 + tmp; 350 | // } 351 | // LCD_DisplayChar(lnnum, pos+8, tmp); 352 | //} 353 | 354 | //void LCD_DisplayRawLine(uint16_t lnnum, uint8_t *buf) 355 | //{ 356 | // uint8_t i; 357 | // for(i=0;i<32;i++){ 358 | // LCD_DisplayByte(lnnum, i*16, *(buf+i)); 359 | // } 360 | //} 361 | 362 | //void LCD_DisplayBuf(uint8_t *buf, ImageResolution_TypeDef ImageRes) 363 | //{ 364 | // uint16_t i,j; 365 | // __IO uint16_t tmp; 366 | // uint32_t offs, joffs; 367 | // uint16_t xlen = Resolution_GetWidth(ImageRes), ylen = Resolution_GetHeight(ImageRes); 368 | // //uint32_t LCD_ofset_buf = LCD_FRAME_BUFFER + BUFFER_OFFSET; 369 | // uint32_t LCD_ofset_buf = LCD_FRAME_BUFFER; 370 | 371 | // for(j=0; j© COPYRIGHT 2013 STMicroelectronics 12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __MAIN_H 30 | #define __MAIN_H 31 | 32 | /* Includes ------------------------------------------------------------------*/ 33 | #include "stm32f4xx.h" 34 | #include 35 | 36 | #if defined (USE_STM324xG_EVAL) 37 | #include "stm324xg_eval.h" 38 | 39 | #elif defined (USE_STM324x7I_EVAL) 40 | #include "stm324x7i_eval.h" 41 | 42 | #elif defined (USE_STM324x9I_EVAL) 43 | #include "stm324x9i_eval.h" 44 | 45 | #else 46 | #error "Please select first the Evaluation board used in your application (in Project Options)" 47 | #endif 48 | 49 | /* Exported typedef ----------------------------------------------------------*/ 50 | /* Exported define -----------------------------------------------------------*/ 51 | /* Exported types ------------------------------------------------------------*/ 52 | /* Exported constants --------------------------------------------------------*/ 53 | /* Exported macro ------------------------------------------------------------*/ 54 | /* Exported functions ------------------------------------------------------- */ 55 | 56 | #endif /* __MAIN_H */ 57 | 58 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 59 | -------------------------------------------------------------------------------- /ov2640_lcd.sublime-project: -------------------------------------------------------------------------------- 1 | { 2 | "folders": 3 | [ 4 | { 5 | "path": "." 6 | } 7 | ] 8 | } 9 | -------------------------------------------------------------------------------- /ov2640_lcd.sublime-workspace: -------------------------------------------------------------------------------- 1 | { 2 | "auto_complete": 3 | { 4 | "selected_items": 5 | [ 6 | ] 7 | }, 8 | "buffers": 9 | [ 10 | { 11 | "file": "32f429_lcd.c", 12 | "settings": 13 | { 14 | "buffer_size": 50125, 15 | "line_ending": "Windows" 16 | } 17 | } 18 | ], 19 | "build_system": "", 20 | "build_system_choices": 21 | [ 22 | ], 23 | "build_varint": "", 24 | "command_palette": 25 | { 26 | "height": 0.0, 27 | "last_filter": "", 28 | "selected_items": 29 | [ 30 | ], 31 | "width": 0.0 32 | }, 33 | "console": 34 | { 35 | "height": 0.0, 36 | "history": 37 | [ 38 | ] 39 | }, 40 | "distraction_free": 41 | { 42 | "menu_visible": true, 43 | "show_minimap": false, 44 | "show_open_files": false, 45 | "show_tabs": false, 46 | "side_bar_visible": false, 47 | "status_bar_visible": false 48 | }, 49 | "expanded_folders": 50 | [ 51 | "/home/tarasii/stm32/STM32F4xx_DSP_StdPeriph_Lib_V1.6.1/Project/OV2640_LCD" 52 | ], 53 | "file_history": 54 | [ 55 | ], 56 | "find": 57 | { 58 | "height": 34.0 59 | }, 60 | "find_in_files": 61 | { 62 | "height": 0.0, 63 | "where_history": 64 | [ 65 | ] 66 | }, 67 | "find_state": 68 | { 69 | "case_sensitive": false, 70 | "find_history": 71 | [ 72 | ], 73 | "highlight": true, 74 | "in_selection": false, 75 | "preserve_case": false, 76 | "regex": false, 77 | "replace_history": 78 | [ 79 | ], 80 | "reverse": false, 81 | "show_context": true, 82 | "use_buffer2": true, 83 | "whole_word": false, 84 | "wrap": true 85 | }, 86 | "groups": 87 | [ 88 | { 89 | "selected": 0, 90 | "sheets": 91 | [ 92 | { 93 | "buffer": 0, 94 | "file": "32f429_lcd.c", 95 | "semi_transient": true, 96 | "settings": 97 | { 98 | "buffer_size": 50125, 99 | "regions": 100 | { 101 | }, 102 | "selection": 103 | [ 104 | [ 105 | 0, 106 | 0 107 | ] 108 | ], 109 | "settings": 110 | { 111 | "syntax": "Packages/C++/C.sublime-syntax", 112 | "tab_size": 2, 113 | "translate_tabs_to_spaces": true 114 | }, 115 | "translation.x": 0.0, 116 | "translation.y": 4365.0, 117 | "zoom_level": 1.0 118 | }, 119 | "stack_index": 0, 120 | "type": "text" 121 | } 122 | ] 123 | } 124 | ], 125 | "incremental_find": 126 | { 127 | "height": 23.0 128 | }, 129 | "input": 130 | { 131 | "height": 0.0 132 | }, 133 | "layout": 134 | { 135 | "cells": 136 | [ 137 | [ 138 | 0, 139 | 0, 140 | 1, 141 | 1 142 | ] 143 | ], 144 | "cols": 145 | [ 146 | 0.0, 147 | 1.0 148 | ], 149 | "rows": 150 | [ 151 | 0.0, 152 | 1.0 153 | ] 154 | }, 155 | "menu_visible": true, 156 | "output.find_results": 157 | { 158 | "height": 0.0 159 | }, 160 | "pinned_build_system": "", 161 | "project": "ov2640_lcd.sublime-project", 162 | "replace": 163 | { 164 | "height": 42.0 165 | }, 166 | "save_all_on_build": true, 167 | "select_file": 168 | { 169 | "height": 0.0, 170 | "last_filter": "", 171 | "selected_items": 172 | [ 173 | ], 174 | "width": 0.0 175 | }, 176 | "select_project": 177 | { 178 | "height": 0.0, 179 | "last_filter": "", 180 | "selected_items": 181 | [ 182 | ], 183 | "width": 0.0 184 | }, 185 | "select_symbol": 186 | { 187 | "height": 0.0, 188 | "last_filter": "", 189 | "selected_items": 190 | [ 191 | ], 192 | "width": 0.0 193 | }, 194 | "selected_group": 0, 195 | "settings": 196 | { 197 | }, 198 | "show_minimap": true, 199 | "show_open_files": false, 200 | "show_tabs": true, 201 | "side_bar_visible": true, 202 | "side_bar_width": 235.0, 203 | "status_bar_visible": true, 204 | "template_settings": 205 | { 206 | } 207 | } 208 | -------------------------------------------------------------------------------- /pin.h: -------------------------------------------------------------------------------- 1 | #ifndef __pin_H 2 | #define __pin_H 3 | 4 | #define LED1_Pin GPIO_Pin_6 5 | #define LED1_GPIO_Port GPIOF 6 | #define LED2_Pin GPIO_Pin_7 7 | #define LED2_GPIO_Port GPIOF 8 | #define LED3_Pin GPIO_Pin_8 9 | #define LED3_GPIO_Port GPIOF 10 | #define LED4_Pin GPIO_Pin_9 11 | #define LED4_GPIO_Port GPIOF 12 | 13 | #define GPIO_HIGH(GPIOx, GPIO_Pin) GPIOx->BSRRL = GPIO_Pin 14 | #define GPIO_LOW(GPIOx, GPIO_Pin) GPIOx->BSRRH = GPIO_Pin 15 | #define GPIO_TOGGLE(GPIOx, GPIO_Pin) GPIOx->ODR ^= GPIO_Pin 16 | #define GPIO_GETPINVAL(GPIOx, GPIO_Pin) (((GPIOx)->IDR & (GPIO_Pin)) == 0 ? 0 : 1) 17 | 18 | #endif /* __pin_H */ 19 | 20 | -------------------------------------------------------------------------------- /readme.txt: -------------------------------------------------------------------------------- 1 | /** Taras Ivaniv **/ 2 | 3 | @par Example Description 4 | 5 | This example fully based on WaveShare and STMicroelectronics examples 6 | Example shows how to make OV7670 camera 320x200 output on 800x480 LCD with Open429I-C devboard. 7 | Example runs on: 8 | WaveShare Open4X9I-C devboard with STM32F429ITG 8MHz 9 | OV7670 with 50MHz external crystal generator 10 | 11 | Example uses STM32F4xx_DSP_StdPeriph_Lib_V1.6.1 12 | Just git clone in STM32F4xx_DSP_StdPeriph_Lib_V1.6.1\Project\ folder 13 | 14 | The USARTx is configured as follows: 15 | - BaudRate = 115200 baud 16 | - Word Length = 8 Bits 17 | - One Stop Bit 18 | - No parity 19 | - Hardware flow control disabled (RTS and CTS signals) 20 | - Receive and transmit enabled 21 | 22 | 23 | @par Directory contents 24 | 25 | - system_stm32f4xx.c STM32F4xx system clock configuration file 26 | - stm32f4xx_conf.h Library Configuration file 27 | - stm32f4xx_it.c Interrupt handlers 28 | - stm32f4xx_it.h Interrupt handlers header file 29 | - stm32f429_lcd.c LCD config and graphics module 30 | - stm32f429_lcd.h LCD header file 31 | - stm32f429_sdram.c SDRAM config module 32 | - stm32f429_sdram.h SDRAM header file 33 | - main.c Main program 34 | - main.h Main program header file 35 | - dcmi.c DCMI GPIO DMA config module 36 | - dcmi.h DCMI header file 37 | - usart.c USART config module 38 | - usart.h USART header file 39 | - i2c.c I2C module 40 | - i2c.h I2C header file 41 | 42 | 43 | 44 | tarasii@gmail.com 45 | http://www.waveshare.com/product/mcu-tools/stm32/open.htm 46 | http://www.waveshare.com/wiki/Open429I-C 47 | http://org-www.st.com/en/microcontrollers.html 48 | 49 | 50 | -------------------------------------------------------------------------------- /stm32f4xx_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/USART_Printf/stm32f4xx_conf.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *
© COPYRIGHT 2013 STMicroelectronics
12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __STM32F4xx_CONF_H 30 | #define __STM32F4xx_CONF_H 31 | 32 | /* Includes ------------------------------------------------------------------*/ 33 | /* Uncomment the line below to enable peripheral header file inclusion */ 34 | #include "stm32f4xx_adc.h" 35 | #include "stm32f4xx_crc.h" 36 | #include "stm32f4xx_dbgmcu.h" 37 | #include "stm32f4xx_dma.h" 38 | #include "stm32f4xx_exti.h" 39 | #include "stm32f4xx_flash.h" 40 | #include "stm32f4xx_gpio.h" 41 | #include "stm32f4xx_i2c.h" 42 | #include "stm32f4xx_iwdg.h" 43 | #include "stm32f4xx_pwr.h" 44 | #include "stm32f4xx_rcc.h" 45 | #include "stm32f4xx_rtc.h" 46 | #include "stm32f4xx_sdio.h" 47 | #include "stm32f4xx_spi.h" 48 | #include "stm32f4xx_syscfg.h" 49 | #include "stm32f4xx_tim.h" 50 | #include "stm32f4xx_usart.h" 51 | #include "stm32f4xx_wwdg.h" 52 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 53 | 54 | #if defined (STM32F429_439xx) 55 | #include "stm32f4xx_cryp.h" 56 | #include "stm32f4xx_hash.h" 57 | #include "stm32f4xx_rng.h" 58 | #include "stm32f4xx_can.h" 59 | #include "stm32f4xx_dac.h" 60 | #include "stm32f4xx_dcmi.h" 61 | #include "stm32f4xx_dma2d.h" 62 | #include "stm32f4xx_fmc.h" 63 | #include "stm32f4xx_ltdc.h" 64 | #include "stm32f4xx_sai.h" 65 | #endif /* STM32F429_439xx */ 66 | 67 | #if defined (STM32F427_437xx) 68 | #include "stm32f4xx_cryp.h" 69 | #include "stm32f4xx_hash.h" 70 | #include "stm32f4xx_rng.h" 71 | #include "stm32f4xx_can.h" 72 | #include "stm32f4xx_dac.h" 73 | #include "stm32f4xx_dcmi.h" 74 | #include "stm32f4xx_dma2d.h" 75 | #include "stm32f4xx_fmc.h" 76 | #include "stm32f4xx_sai.h" 77 | #endif /* STM32F427_437xx */ 78 | 79 | #if defined (STM32F40_41xxx) 80 | #include "stm32f4xx_cryp.h" 81 | #include "stm32f4xx_hash.h" 82 | #include "stm32f4xx_rng.h" 83 | #include "stm32f4xx_can.h" 84 | #include "stm32f4xx_dac.h" 85 | #include "stm32f4xx_dcmi.h" 86 | #include "stm32f4xx_fsmc.h" 87 | #endif /* STM32F40_41xxx */ 88 | 89 | /* Exported types ------------------------------------------------------------*/ 90 | /* Exported constants --------------------------------------------------------*/ 91 | 92 | /* If an external clock source is used, then the value of the following define 93 | should be set to the value of the external clock source, else, if no external 94 | clock is used, keep this define commented */ 95 | /*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ 96 | 97 | 98 | /* Uncomment the line below to expanse the "assert_param" macro in the 99 | Standard Peripheral Library drivers code */ 100 | /* #define USE_FULL_ASSERT 1 */ 101 | 102 | /* Exported macro ------------------------------------------------------------*/ 103 | #ifdef USE_FULL_ASSERT 104 | 105 | /** 106 | * @brief The assert_param macro is used for function's parameters check. 107 | * @param expr: If expr is false, it calls assert_failed function 108 | * which reports the name of the source file and the source 109 | * line number of the call that failed. 110 | * If expr is true, it returns no value. 111 | * @retval None 112 | */ 113 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 114 | /* Exported functions ------------------------------------------------------- */ 115 | void assert_failed(uint8_t* file, uint32_t line); 116 | #else 117 | #define assert_param(expr) ((void)0) 118 | #endif /* USE_FULL_ASSERT */ 119 | 120 | #endif /* __STM32F4xx_CONF_H */ 121 | 122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 123 | -------------------------------------------------------------------------------- /stm32f4xx_it.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/USART_Printf/stm32f4xx_it.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief Main Interrupt Service Routines. 8 | * This file provides template for all exceptions handler and 9 | * peripherals interrupt service routine. 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *
© COPYRIGHT 2013 STMicroelectronics
14 | * 15 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 16 | * You may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.st.com/software_license_agreement_liberty_v2 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | * 27 | ****************************************************************************** 28 | */ 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f4xx_it.h" 32 | #include "pin.h" 33 | #include "dcmi.h" 34 | 35 | /** @addtogroup STM32F4xx_StdPeriph_Examples 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup USART_Printf 40 | * @{ 41 | */ 42 | 43 | /* Private typedef -----------------------------------------------------------*/ 44 | /* Private define ------------------------------------------------------------*/ 45 | /* Private macro -------------------------------------------------------------*/ 46 | /* Private variables ---------------------------------------------------------*/ 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* Private functions ---------------------------------------------------------*/ 49 | 50 | /******************************************************************************/ 51 | /* Cortex-M4 Processor Exceptions Handlers */ 52 | /******************************************************************************/ 53 | 54 | /** 55 | * @brief This function handles NMI exception. 56 | * @param None 57 | * @retval None 58 | */ 59 | void NMI_Handler(void) 60 | { 61 | } 62 | 63 | /** 64 | * @brief This function handles Hard Fault exception. 65 | * @param None 66 | * @retval None 67 | */ 68 | void HardFault_Handler(void) 69 | { 70 | /* Go to infinite loop when Hard Fault exception occurs */ 71 | while (1) 72 | { 73 | } 74 | } 75 | 76 | /** 77 | * @brief This function handles Memory Manage exception. 78 | * @param None 79 | * @retval None 80 | */ 81 | void MemManage_Handler(void) 82 | { 83 | /* Go to infinite loop when Memory Manage exception occurs */ 84 | while (1) 85 | { 86 | } 87 | } 88 | 89 | /** 90 | * @brief This function handles Bus Fault exception. 91 | * @param None 92 | * @retval None 93 | */ 94 | void BusFault_Handler(void) 95 | { 96 | /* Go to infinite loop when Bus Fault exception occurs */ 97 | while (1) 98 | { 99 | } 100 | } 101 | 102 | /** 103 | * @brief This function handles Usage Fault exception. 104 | * @param None 105 | * @retval None 106 | */ 107 | void UsageFault_Handler(void) 108 | { 109 | /* Go to infinite loop when Usage Fault exception occurs */ 110 | while (1) 111 | { 112 | } 113 | } 114 | 115 | /** 116 | * @brief This function handles SVCall exception. 117 | * @param None 118 | * @retval None 119 | */ 120 | void SVC_Handler(void) 121 | { 122 | } 123 | 124 | /** 125 | * @brief This function handles Debug Monitor exception. 126 | * @param None 127 | * @retval None 128 | */ 129 | void DebugMon_Handler(void) 130 | { 131 | } 132 | 133 | /** 134 | * @brief This function handles PendSVC exception. 135 | * @param None 136 | * @retval None 137 | */ 138 | void PendSV_Handler(void) 139 | { 140 | } 141 | 142 | /** 143 | * @brief This function handles SysTick Handler. 144 | * @param None 145 | * @retval None 146 | */ 147 | extern void TimingDelay_Decrement(void); 148 | void SysTick_Handler(void) 149 | { 150 | TimingDelay_Decrement(); 151 | } 152 | extern uint8_t jpg_flag; 153 | extern uint8_t key_flag; 154 | extern uint8_t dcim_flag; 155 | extern uint8_t frame_flag; 156 | extern uint16_t lncnt; 157 | extern uint16_t lnmax; 158 | extern uint16_t fps; 159 | void DCMI_IRQHandler(void) 160 | { 161 | if (DCMI_GetITStatus(DCMI_IT_FRAME) != RESET) { 162 | DCMI_ClearITPendingBit(DCMI_IT_FRAME); 163 | GPIO_TOGGLE(LED1_GPIO_Port, LED1_Pin); 164 | dcim_flag = 0; 165 | fps++; 166 | frame_flag = 1; 167 | } 168 | 169 | if (DCMI_GetITStatus(DCMI_IT_LINE) != RESET){ 170 | DCMI_ClearFlag(DCMI_FLAG_LINERI); 171 | GPIO_TOGGLE(LED2_GPIO_Port, LED2_Pin); 172 | lncnt++; 173 | } 174 | 175 | if (DCMI_GetITStatus(DCMI_IT_VSYNC) != RESET){ 176 | DCMI_ClearFlag(DCMI_FLAG_VSYNCRI); 177 | GPIO_TOGGLE(LED3_GPIO_Port, LED3_Pin); 178 | lnmax = lncnt; 179 | lncnt = 0; 180 | } 181 | 182 | } 183 | 184 | void DMA2_Stream1_IRQHandler (void) 185 | { 186 | uint32_t cur_mb; 187 | cur_mb = DMA_GetCurrentMemoryTarget(DMA2_Stream1); 188 | if (cur_mb == DMA_Memory_0) cur_mb = DMA_Memory_1; else cur_mb = DMA_Memory_0; 189 | 190 | if (DMA_GetITStatus(DMA2_Stream1, DMA_IT_TCIF1) == SET) 191 | { 192 | DMA_ClearITPendingBit(DMA2_Stream1, DMA_IT_TCIF1); 193 | GPIO_TOGGLE(LED4_GPIO_Port, LED4_Pin); 194 | // if (dcim_flag == 0) { 195 | // //DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS + 640 * 480), cur_mb); 196 | // DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS + 800 * 600), cur_mb); 197 | // } 198 | // if (dcim_flag == 1) { 199 | // //DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS + 640 * 480 * 3 / 2), cur_mb); 200 | // DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS + 800 * 600 * 3 / 2), cur_mb); 201 | // } 202 | // if (dcim_flag == 2) { 203 | // //DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS), cur_mb); 204 | // DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS), cur_mb); 205 | // } 206 | // if (dcim_flag == 3) { 207 | // //DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS + 640 * 480 / 2), cur_mb); 208 | // DMA_MemoryTargetConfig(DMA2_Stream1, (uint32_t) (DCMI_BUF_ADDRESS + 800 * 600 / 2), cur_mb); 209 | // } 210 | // dcim_flag++; 211 | // if (dcim_flag > 3) dcim_flag = 0; 212 | } 213 | } 214 | /******************************************************************************/ 215 | /* STM32F4xx Peripherals Interrupt Handlers */ 216 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ 217 | /* available peripheral interrupt handler's name please refer to the startup */ 218 | /* file (startup_stm32f40xx.s/startup_stm32f427x.s). */ 219 | /******************************************************************************/ 220 | 221 | /** 222 | * @brief This function handles PPP interrupt request. 223 | * @param None 224 | * @retval None 225 | */ 226 | /*void PPP_IRQHandler(void) 227 | { 228 | }*/ 229 | 230 | /** 231 | * @} 232 | */ 233 | 234 | /** 235 | * @} 236 | */ 237 | 238 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 239 | -------------------------------------------------------------------------------- /stm32f4xx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/USART_Printf/stm32f4xx_it.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief This file contains the headers of the interrupt handlers. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *
© COPYRIGHT 2013 STMicroelectronics
12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __STM32F4xx_IT_H 30 | #define __STM32F4xx_IT_H 31 | 32 | #ifdef __cplusplus 33 | extern "C" { 34 | #endif 35 | 36 | /* Includes ------------------------------------------------------------------*/ 37 | #include "stm32f4xx.h" 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /* Exported macro ------------------------------------------------------------*/ 42 | /* Exported functions ------------------------------------------------------- */ 43 | 44 | void NMI_Handler(void); 45 | void HardFault_Handler(void); 46 | void MemManage_Handler(void); 47 | void BusFault_Handler(void); 48 | void UsageFault_Handler(void); 49 | void SVC_Handler(void); 50 | void DebugMon_Handler(void); 51 | void PendSV_Handler(void); 52 | void SysTick_Handler(void); 53 | 54 | #ifdef __cplusplus 55 | } 56 | #endif 57 | 58 | #endif /* __STM32F4xx_IT_H */ 59 | 60 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 61 | -------------------------------------------------------------------------------- /system_stm32f4xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/USART_Printf/system_stm32f4xx.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 8 | * This file contains the system clock configuration for STM32F4xx devices. 9 | * 10 | * 1. This file provides two functions and one global variable to be called from 11 | * user application: 12 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 13 | * and Divider factors, AHB/APBx prescalers and Flash settings), 14 | * depending on the configuration made in the clock xls tool. 15 | * This function is called at startup just after reset and 16 | * before branch to main program. This call is made inside 17 | * the "startup_stm32f4xx.s" file. 18 | * 19 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 20 | * by the user application to setup the SysTick 21 | * timer or configure other parameters. 22 | * 23 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 24 | * be called whenever the core clock is changed 25 | * during program execution. 26 | * 27 | * 2. After each device reset the HSI (16 MHz) is used as system clock source. 28 | * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to 29 | * configure the system clock before to branch to main program. 30 | * 31 | * 3. If the system clock source selected by user fails to startup, the SystemInit() 32 | * function will do nothing and HSI still used as system clock source. User can 33 | * add some code to deal with this issue inside the SetSysClock() function. 34 | * 35 | * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define 36 | * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or 37 | * through PLL, and you are using different crystal you have to adapt the HSE 38 | * value to your own configuration. 39 | * 40 | * 5. This file configures the system clock as follows: 41 | *============================================================================= 42 | *============================================================================= 43 | * Supported STM32F40xxx/41xxx devices 44 | *----------------------------------------------------------------------------- 45 | * System Clock source | PLL (HSE) 46 | *----------------------------------------------------------------------------- 47 | * SYSCLK(Hz) | 168000000 48 | *----------------------------------------------------------------------------- 49 | * HCLK(Hz) | 168000000 50 | *----------------------------------------------------------------------------- 51 | * AHB Prescaler | 1 52 | *----------------------------------------------------------------------------- 53 | * APB1 Prescaler | 4 54 | *----------------------------------------------------------------------------- 55 | * APB2 Prescaler | 2 56 | *----------------------------------------------------------------------------- 57 | * HSE Frequency(Hz) | 25000000 58 | *----------------------------------------------------------------------------- 59 | * PLL_M | 25 60 | *----------------------------------------------------------------------------- 61 | * PLL_N | 336 62 | *----------------------------------------------------------------------------- 63 | * PLL_P | 2 64 | *----------------------------------------------------------------------------- 65 | * PLL_Q | 7 66 | *----------------------------------------------------------------------------- 67 | * PLLI2S_N | NA 68 | *----------------------------------------------------------------------------- 69 | * PLLI2S_R | NA 70 | *----------------------------------------------------------------------------- 71 | * I2S input clock | NA 72 | *----------------------------------------------------------------------------- 73 | * VDD(V) | 3.3 74 | *----------------------------------------------------------------------------- 75 | * Main regulator output voltage | Scale1 mode 76 | *----------------------------------------------------------------------------- 77 | * Flash Latency(WS) | 5 78 | *----------------------------------------------------------------------------- 79 | * Prefetch Buffer | ON 80 | *----------------------------------------------------------------------------- 81 | * Instruction cache | ON 82 | *----------------------------------------------------------------------------- 83 | * Data cache | ON 84 | *----------------------------------------------------------------------------- 85 | * Require 48MHz for USB OTG FS, | Disabled 86 | * SDIO and RNG clock | 87 | *----------------------------------------------------------------------------- 88 | *============================================================================= 89 | *============================================================================= 90 | * Supported STM32F42xxx/43xxx devices 91 | *----------------------------------------------------------------------------- 92 | * System Clock source | PLL (HSE) 93 | *----------------------------------------------------------------------------- 94 | * SYSCLK(Hz) | 180000000 95 | *----------------------------------------------------------------------------- 96 | * HCLK(Hz) | 180000000 97 | *----------------------------------------------------------------------------- 98 | * AHB Prescaler | 1 99 | *----------------------------------------------------------------------------- 100 | * APB1 Prescaler | 4 101 | *----------------------------------------------------------------------------- 102 | * APB2 Prescaler | 2 103 | *----------------------------------------------------------------------------- 104 | * HSE Frequency(Hz) | 25000000 105 | *----------------------------------------------------------------------------- 106 | * PLL_M | 25 107 | *----------------------------------------------------------------------------- 108 | * PLL_N | 360 109 | *----------------------------------------------------------------------------- 110 | * PLL_P | 2 111 | *----------------------------------------------------------------------------- 112 | * PLL_Q | 7 113 | *----------------------------------------------------------------------------- 114 | * PLLI2S_N | NA 115 | *----------------------------------------------------------------------------- 116 | * PLLI2S_R | NA 117 | *----------------------------------------------------------------------------- 118 | * I2S input clock | NA 119 | *----------------------------------------------------------------------------- 120 | * VDD(V) | 3.3 121 | *----------------------------------------------------------------------------- 122 | * Main regulator output voltage | Scale1 mode 123 | *----------------------------------------------------------------------------- 124 | * Flash Latency(WS) | 5 125 | *----------------------------------------------------------------------------- 126 | * Prefetch Buffer | ON 127 | *----------------------------------------------------------------------------- 128 | * Instruction cache | ON 129 | *----------------------------------------------------------------------------- 130 | * Data cache | ON 131 | *----------------------------------------------------------------------------- 132 | * Require 48MHz for USB OTG FS, | Disabled 133 | * SDIO and RNG clock | 134 | *----------------------------------------------------------------------------- 135 | *============================================================================= 136 | *============================================================================= 137 | * Supported STM32F401xx devices 138 | *----------------------------------------------------------------------------- 139 | * System Clock source | PLL (HSE) 140 | *----------------------------------------------------------------------------- 141 | * SYSCLK(Hz) | 84000000 142 | *----------------------------------------------------------------------------- 143 | * HCLK(Hz) | 84000000 144 | *----------------------------------------------------------------------------- 145 | * AHB Prescaler | 1 146 | *----------------------------------------------------------------------------- 147 | * APB1 Prescaler | 2 148 | *----------------------------------------------------------------------------- 149 | * APB2 Prescaler | 1 150 | *----------------------------------------------------------------------------- 151 | * HSE Frequency(Hz) | 25000000 152 | *----------------------------------------------------------------------------- 153 | * PLL_M | 25 154 | *----------------------------------------------------------------------------- 155 | * PLL_N | 336 156 | *----------------------------------------------------------------------------- 157 | * PLL_P | 4 158 | *----------------------------------------------------------------------------- 159 | * PLL_Q | 7 160 | *----------------------------------------------------------------------------- 161 | * PLLI2S_N | NA 162 | *----------------------------------------------------------------------------- 163 | * PLLI2S_R | NA 164 | *----------------------------------------------------------------------------- 165 | * I2S input clock | NA 166 | *----------------------------------------------------------------------------- 167 | * VDD(V) | 3.3 168 | *----------------------------------------------------------------------------- 169 | * Main regulator output voltage | Scale1 mode 170 | *----------------------------------------------------------------------------- 171 | * Flash Latency(WS) | 2 172 | *----------------------------------------------------------------------------- 173 | * Prefetch Buffer | ON 174 | *----------------------------------------------------------------------------- 175 | * Instruction cache | ON 176 | *----------------------------------------------------------------------------- 177 | * Data cache | ON 178 | *----------------------------------------------------------------------------- 179 | * Require 48MHz for USB OTG FS, | Disabled 180 | * SDIO and RNG clock | 181 | *----------------------------------------------------------------------------- 182 | *============================================================================= 183 | ****************************************************************************** 184 | * @attention 185 | * 186 | *
© COPYRIGHT 2013 STMicroelectronics
187 | * 188 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 189 | * You may not use this file except in compliance with the License. 190 | * You may obtain a copy of the License at: 191 | * 192 | * http://www.st.com/software_license_agreement_liberty_v2 193 | * 194 | * Unless required by applicable law or agreed to in writing, software 195 | * distributed under the License is distributed on an "AS IS" BASIS, 196 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 197 | * See the License for the specific language governing permissions and 198 | * limitations under the License. 199 | * 200 | ****************************************************************************** 201 | */ 202 | 203 | /** @addtogroup CMSIS 204 | * @{ 205 | */ 206 | 207 | /** @addtogroup stm32f4xx_system 208 | * @{ 209 | */ 210 | 211 | /** @addtogroup STM32F4xx_System_Private_Includes 212 | * @{ 213 | */ 214 | 215 | #include "stm32f4xx.h" 216 | 217 | /** 218 | * @} 219 | */ 220 | 221 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions 222 | * @{ 223 | */ 224 | 225 | /** 226 | * @} 227 | */ 228 | 229 | /** @addtogroup STM32F4xx_System_Private_Defines 230 | * @{ 231 | */ 232 | 233 | 234 | /************************* Miscellaneous Configuration ************************/ 235 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted 236 | on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */ 237 | 238 | #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) 239 | /* #define DATA_IN_ExtSRAM */ 240 | #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */ 241 | 242 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) 243 | /* #define DATA_IN_ExtSDRAM */ 244 | #endif /* STM32F427_437x || STM32F429_439xx */ 245 | 246 | /*!< Uncomment the following line if you need to relocate your vector Table in 247 | Internal SRAM. */ 248 | /* #define VECT_TAB_SRAM */ 249 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. 250 | This value must be a multiple of 0x200. */ 251 | /******************************************************************************/ 252 | 253 | /************************* PLL Parameters *************************************/ 254 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ 255 | #define PLL_M 8 256 | /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ 257 | #define PLL_Q 4 258 | 259 | #if defined (STM32F40_41xxx) 260 | #define PLL_N 336 261 | /* SYSCLK = PLL_VCO / PLL_P */ 262 | #define PLL_P 2 263 | #endif /* STM32F40_41xxx */ 264 | 265 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) 266 | #define PLL_N 360 267 | /* SYSCLK = PLL_VCO / PLL_P */ 268 | #define PLL_P 2 269 | #endif /* STM32F427_437x || STM32F429_439xx */ 270 | 271 | #if defined (STM32F401xx) 272 | #define PLL_N 336 273 | /* SYSCLK = PLL_VCO / PLL_P */ 274 | #define PLL_P 4 275 | #endif /* STM32F401xx */ 276 | 277 | /******************************************************************************/ 278 | 279 | /** 280 | * @} 281 | */ 282 | 283 | /** @addtogroup STM32F4xx_System_Private_Macros 284 | * @{ 285 | */ 286 | 287 | /** 288 | * @} 289 | */ 290 | 291 | /** @addtogroup STM32F4xx_System_Private_Variables 292 | * @{ 293 | */ 294 | 295 | #if defined (STM32F40_41xxx) 296 | uint32_t SystemCoreClock = 168000000; 297 | #endif /* STM32F40_41xxx */ 298 | 299 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) 300 | uint32_t SystemCoreClock = 180000000; 301 | #endif /* STM32F427_437x || STM32F429_439xx */ 302 | 303 | #if defined (STM32F401xx) 304 | uint32_t SystemCoreClock = 84000000; 305 | #endif /* STM32F401xx */ 306 | 307 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 308 | 309 | /** 310 | * @} 311 | */ 312 | 313 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes 314 | * @{ 315 | */ 316 | 317 | static void SetSysClock(void); 318 | 319 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 320 | static void SystemInit_ExtMemCtl(void); 321 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 322 | 323 | /** 324 | * @} 325 | */ 326 | 327 | /** @addtogroup STM32F4xx_System_Private_Functions 328 | * @{ 329 | */ 330 | 331 | /** 332 | * @brief Setup the microcontroller system 333 | * Initialize the Embedded Flash Interface, the PLL and update the 334 | * SystemFrequency variable. 335 | * @param None 336 | * @retval None 337 | */ 338 | void SystemInit(void) 339 | { 340 | /* FPU settings ------------------------------------------------------------*/ 341 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 342 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 343 | #endif 344 | /* Reset the RCC clock configuration to the default reset state ------------*/ 345 | /* Set HSION bit */ 346 | RCC->CR |= (uint32_t)0x00000001; 347 | 348 | /* Reset CFGR register */ 349 | RCC->CFGR = 0x00000000; 350 | 351 | /* Reset HSEON, CSSON and PLLON bits */ 352 | RCC->CR &= (uint32_t)0xFEF6FFFF; 353 | 354 | /* Reset PLLCFGR register */ 355 | RCC->PLLCFGR = 0x24003010; 356 | 357 | /* Reset HSEBYP bit */ 358 | RCC->CR &= (uint32_t)0xFFFBFFFF; 359 | 360 | /* Disable all interrupts */ 361 | RCC->CIR = 0x00000000; 362 | 363 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 364 | SystemInit_ExtMemCtl(); 365 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 366 | 367 | /* Configure the System clock source, PLL Multiplier and Divider factors, 368 | AHB/APBx prescalers and Flash settings ----------------------------------*/ 369 | SetSysClock(); 370 | 371 | /* Configure the Vector Table location add offset address ------------------*/ 372 | #ifdef VECT_TAB_SRAM 373 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 374 | #else 375 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 376 | #endif 377 | } 378 | 379 | /** 380 | * @brief Update SystemCoreClock variable according to Clock Register Values. 381 | * The SystemCoreClock variable contains the core clock (HCLK), it can 382 | * be used by the user application to setup the SysTick timer or configure 383 | * other parameters. 384 | * 385 | * @note Each time the core clock (HCLK) changes, this function must be called 386 | * to update SystemCoreClock variable value. Otherwise, any configuration 387 | * based on this variable will be incorrect. 388 | * 389 | * @note - The system frequency computed by this function is not the real 390 | * frequency in the chip. It is calculated based on the predefined 391 | * constant and the selected clock source: 392 | * 393 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 394 | * 395 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 396 | * 397 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 398 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 399 | * 400 | * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 401 | * 16 MHz) but the real value may vary depending on the variations 402 | * in voltage and temperature. 403 | * 404 | * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 405 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real 406 | * frequency of the crystal used. Otherwise, this function may 407 | * have wrong result. 408 | * 409 | * - The result of this function could be not correct when using fractional 410 | * value for HSE crystal. 411 | * 412 | * @param None 413 | * @retval None 414 | */ 415 | void SystemCoreClockUpdate(void) 416 | { 417 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; 418 | 419 | /* Get SYSCLK source -------------------------------------------------------*/ 420 | tmp = RCC->CFGR & RCC_CFGR_SWS; 421 | 422 | switch (tmp) 423 | { 424 | case 0x00: /* HSI used as system clock source */ 425 | SystemCoreClock = HSI_VALUE; 426 | break; 427 | case 0x04: /* HSE used as system clock source */ 428 | SystemCoreClock = HSE_VALUE; 429 | break; 430 | case 0x08: /* PLL used as system clock source */ 431 | 432 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 433 | SYSCLK = PLL_VCO / PLL_P 434 | */ 435 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 436 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 437 | 438 | if (pllsource != 0) 439 | { 440 | /* HSE used as PLL clock source */ 441 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 442 | } 443 | else 444 | { 445 | /* HSI used as PLL clock source */ 446 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 447 | } 448 | 449 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 450 | SystemCoreClock = pllvco/pllp; 451 | break; 452 | default: 453 | SystemCoreClock = HSI_VALUE; 454 | break; 455 | } 456 | /* Compute HCLK frequency --------------------------------------------------*/ 457 | /* Get HCLK prescaler */ 458 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 459 | /* HCLK frequency */ 460 | SystemCoreClock >>= tmp; 461 | } 462 | 463 | /** 464 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, 465 | * AHB/APBx prescalers and Flash settings 466 | * @Note This function should be called only once the RCC clock configuration 467 | * is reset to the default reset state (done in SystemInit() function). 468 | * @param None 469 | * @retval None 470 | */ 471 | static void SetSysClock(void) 472 | { 473 | /******************************************************************************/ 474 | /* PLL (clocked by HSE) used as System clock source */ 475 | /******************************************************************************/ 476 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 477 | 478 | /* Enable HSE */ 479 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 480 | 481 | /* Wait till HSE is ready and if Time out is reached exit */ 482 | do 483 | { 484 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 485 | StartUpCounter++; 486 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 487 | 488 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 489 | { 490 | HSEStatus = (uint32_t)0x01; 491 | } 492 | else 493 | { 494 | HSEStatus = (uint32_t)0x00; 495 | } 496 | 497 | if (HSEStatus == (uint32_t)0x01) 498 | { 499 | /* Select regulator voltage output Scale 1 mode */ 500 | RCC->APB1ENR |= RCC_APB1ENR_PWREN; 501 | PWR->CR |= PWR_CR_VOS; 502 | 503 | /* HCLK = SYSCLK / 1*/ 504 | RCC->CFGR |= RCC_CFGR_HPRE_DIV1; 505 | 506 | #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) 507 | /* PCLK2 = HCLK / 2*/ 508 | RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; 509 | 510 | /* PCLK1 = HCLK / 4*/ 511 | RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; 512 | #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */ 513 | 514 | #if defined (STM32F401xx) 515 | /* PCLK2 = HCLK / 2*/ 516 | RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; 517 | 518 | /* PCLK1 = HCLK / 4*/ 519 | RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; 520 | #endif /* STM32F401xx */ 521 | 522 | /* Configure the main PLL */ 523 | RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | 524 | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); 525 | 526 | /* Enable the main PLL */ 527 | RCC->CR |= RCC_CR_PLLON; 528 | 529 | /* Wait till the main PLL is ready */ 530 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 531 | { 532 | } 533 | 534 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) 535 | /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ 536 | PWR->CR |= PWR_CR_ODEN; 537 | while((PWR->CSR & PWR_CSR_ODRDY) == 0) 538 | { 539 | } 540 | PWR->CR |= PWR_CR_ODSWEN; 541 | while((PWR->CSR & PWR_CSR_ODSWRDY) == 0) 542 | { 543 | } 544 | /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ 545 | FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; 546 | #endif /* STM32F427_437x || STM32F429_439xx */ 547 | 548 | #if defined (STM32F40_41xxx) 549 | /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ 550 | FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; 551 | #endif /* STM32F40_41xxx */ 552 | 553 | #if defined (STM32F401xx) 554 | /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ 555 | FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; 556 | #endif /* STM32F401xx */ 557 | 558 | /* Select the main PLL as system clock source */ 559 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 560 | RCC->CFGR |= RCC_CFGR_SW_PLL; 561 | 562 | /* Wait till the main PLL is used as system clock source */ 563 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); 564 | { 565 | } 566 | } 567 | else 568 | { /* If HSE fails to start-up, the application will have wrong clock 569 | configuration. User can add here some code to deal with this error */ 570 | } 571 | 572 | } 573 | 574 | /** 575 | * @brief Setup the external memory controller. Called in startup_stm32f4xx.s 576 | * before jump to __main 577 | * @param None 578 | * @retval None 579 | */ 580 | #ifdef DATA_IN_ExtSRAM 581 | /** 582 | * @brief Setup the external memory controller. 583 | * Called in startup_stm32f4xx.s before jump to main. 584 | * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards 585 | * This SRAM will be used as program data memory (including heap and stack). 586 | * @param None 587 | * @retval None 588 | */ 589 | void SystemInit_ExtMemCtl(void) 590 | { 591 | /*-- GPIOs Configuration -----------------------------------------------------*/ 592 | /* 593 | +-------------------+--------------------+------------------+--------------+ 594 | + SRAM pins assignment + 595 | +-------------------+--------------------+------------------+--------------+ 596 | | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | 597 | | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | 598 | | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 | 599 | | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 | 600 | | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 | 601 | | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 | 602 | | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 | 603 | | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+ 604 | | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 | 605 | | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 | 606 | | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+ 607 | | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 | 608 | | | PE15 <-> FMC_D12 | 609 | +------------------+------------------+ 610 | */ 611 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 612 | RCC->AHB1ENR |= 0x00000078; 613 | 614 | /* Connect PDx pins to FMC Alternate function */ 615 | GPIOD->AFR[0] = 0x00cc00cc; 616 | GPIOD->AFR[1] = 0xcccccccc; 617 | /* Configure PDx pins in Alternate function mode */ 618 | GPIOD->MODER = 0xaaaa0a0a; 619 | /* Configure PDx pins speed to 100 MHz */ 620 | GPIOD->OSPEEDR = 0xffff0f0f; 621 | /* Configure PDx pins Output type to push-pull */ 622 | GPIOD->OTYPER = 0x00000000; 623 | /* No pull-up, pull-down for PDx pins */ 624 | GPIOD->PUPDR = 0x00000000; 625 | 626 | /* Connect PEx pins to FMC Alternate function */ 627 | GPIOE->AFR[0] = 0xcccccccc; 628 | GPIOE->AFR[1] = 0xcccccccc; 629 | /* Configure PEx pins in Alternate function mode */ 630 | GPIOE->MODER = 0xaaaaaaaa; 631 | /* Configure PEx pins speed to 100 MHz */ 632 | GPIOE->OSPEEDR = 0xffffffff; 633 | /* Configure PEx pins Output type to push-pull */ 634 | GPIOE->OTYPER = 0x00000000; 635 | /* No pull-up, pull-down for PEx pins */ 636 | GPIOE->PUPDR = 0x00000000; 637 | 638 | /* Connect PFx pins to FMC Alternate function */ 639 | GPIOF->AFR[0] = 0x00cccccc; 640 | GPIOF->AFR[1] = 0xcccc0000; 641 | /* Configure PFx pins in Alternate function mode */ 642 | GPIOF->MODER = 0xaa000aaa; 643 | /* Configure PFx pins speed to 100 MHz */ 644 | GPIOF->OSPEEDR = 0xff000fff; 645 | /* Configure PFx pins Output type to push-pull */ 646 | GPIOF->OTYPER = 0x00000000; 647 | /* No pull-up, pull-down for PFx pins */ 648 | GPIOF->PUPDR = 0x00000000; 649 | 650 | /* Connect PGx pins to FMC Alternate function */ 651 | GPIOG->AFR[0] = 0x00cccccc; 652 | GPIOG->AFR[1] = 0x000000c0; 653 | /* Configure PGx pins in Alternate function mode */ 654 | GPIOG->MODER = 0x00080aaa; 655 | /* Configure PGx pins speed to 100 MHz */ 656 | GPIOG->OSPEEDR = 0x000c0fff; 657 | /* Configure PGx pins Output type to push-pull */ 658 | GPIOG->OTYPER = 0x00000000; 659 | /* No pull-up, pull-down for PGx pins */ 660 | GPIOG->PUPDR = 0x00000000; 661 | 662 | /*-- FMC Configuration ------------------------------------------------------*/ 663 | /* Enable the FMC/FSMC interface clock */ 664 | RCC->AHB3ENR |= 0x00000001; 665 | 666 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) 667 | /* Configure and enable Bank1_SRAM2 */ 668 | FMC_Bank1->BTCR[2] = 0x00001011; 669 | FMC_Bank1->BTCR[3] = 0x00000201; 670 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 671 | #endif /* STM32F427_437xx || STM32F429_439xx */ 672 | 673 | #if defined (STM32F40_41xxx) 674 | /* Configure and enable Bank1_SRAM2 */ 675 | FSMC_Bank1->BTCR[2] = 0x00001011; 676 | FSMC_Bank1->BTCR[3] = 0x00000201; 677 | FSMC_Bank1E->BWTR[2] = 0x0fffffff; 678 | #endif /* STM32F40_41xxx */ 679 | 680 | /* 681 | Bank1_SRAM2 is configured as follow: 682 | In case of FSMC configuration 683 | NORSRAMTimingStructure.FSMC_AddressSetupTime = 1; 684 | NORSRAMTimingStructure.FSMC_AddressHoldTime = 0; 685 | NORSRAMTimingStructure.FSMC_DataSetupTime = 2; 686 | NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0; 687 | NORSRAMTimingStructure.FSMC_CLKDivision = 0; 688 | NORSRAMTimingStructure.FSMC_DataLatency = 0; 689 | NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A; 690 | 691 | FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; 692 | FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; 693 | FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; 694 | FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; 695 | FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; 696 | FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; 697 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; 698 | FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; 699 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; 700 | FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; 701 | FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; 702 | FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; 703 | FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; 704 | FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; 705 | FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure; 706 | 707 | In case of FMC configuration 708 | NORSRAMTimingStructure.FMC_AddressSetupTime = 1; 709 | NORSRAMTimingStructure.FMC_AddressHoldTime = 0; 710 | NORSRAMTimingStructure.FMC_DataSetupTime = 2; 711 | NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0; 712 | NORSRAMTimingStructure.FMC_CLKDivision = 0; 713 | NORSRAMTimingStructure.FMC_DataLatency = 0; 714 | NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A; 715 | 716 | FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2; 717 | FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable; 718 | FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM; 719 | FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b; 720 | FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; 721 | FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; 722 | FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; 723 | FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable; 724 | FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; 725 | FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable; 726 | FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable; 727 | FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable; 728 | FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable; 729 | FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly; 730 | FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; 731 | FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure; 732 | */ 733 | 734 | } 735 | #endif /* DATA_IN_ExtSRAM */ 736 | 737 | #ifdef DATA_IN_ExtSDRAM 738 | /** 739 | * @brief Setup the external memory controller. 740 | * Called in startup_stm32f4xx.s before jump to main. 741 | * This function configures the external SDRAM mounted on STM324x9I_EVAL board 742 | * This SDRAM will be used as program data memory (including heap and stack). 743 | * @param None 744 | * @retval None 745 | */ 746 | void SystemInit_ExtMemCtl(void) 747 | { 748 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 749 | register uint32_t index; 750 | 751 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 752 | clock */ 753 | RCC->AHB1ENR |= 0x000001FC; 754 | 755 | /* Connect PCx pins to FMC Alternate function */ 756 | GPIOC->AFR[0] = 0x0000000c; 757 | GPIOC->AFR[1] = 0x00007700; 758 | /* Configure PCx pins in Alternate function mode */ 759 | GPIOC->MODER = 0x00a00002; 760 | /* Configure PCx pins speed to 50 MHz */ 761 | GPIOC->OSPEEDR = 0x00a00002; 762 | /* Configure PCx pins Output type to push-pull */ 763 | GPIOC->OTYPER = 0x00000000; 764 | /* No pull-up, pull-down for PCx pins */ 765 | GPIOC->PUPDR = 0x00500000; 766 | 767 | /* Connect PDx pins to FMC Alternate function */ 768 | GPIOD->AFR[0] = 0x000000CC; 769 | GPIOD->AFR[1] = 0xCC000CCC; 770 | /* Configure PDx pins in Alternate function mode */ 771 | GPIOD->MODER = 0xA02A000A; 772 | /* Configure PDx pins speed to 50 MHz */ 773 | GPIOD->OSPEEDR = 0xA02A000A; 774 | /* Configure PDx pins Output type to push-pull */ 775 | GPIOD->OTYPER = 0x00000000; 776 | /* No pull-up, pull-down for PDx pins */ 777 | GPIOD->PUPDR = 0x00000000; 778 | 779 | /* Connect PEx pins to FMC Alternate function */ 780 | GPIOE->AFR[0] = 0xC00000CC; 781 | GPIOE->AFR[1] = 0xCCCCCCCC; 782 | /* Configure PEx pins in Alternate function mode */ 783 | GPIOE->MODER = 0xAAAA800A; 784 | /* Configure PEx pins speed to 50 MHz */ 785 | GPIOE->OSPEEDR = 0xAAAA800A; 786 | /* Configure PEx pins Output type to push-pull */ 787 | GPIOE->OTYPER = 0x00000000; 788 | /* No pull-up, pull-down for PEx pins */ 789 | GPIOE->PUPDR = 0x00000000; 790 | 791 | /* Connect PFx pins to FMC Alternate function */ 792 | GPIOF->AFR[0] = 0xcccccccc; 793 | GPIOF->AFR[1] = 0xcccccccc; 794 | /* Configure PFx pins in Alternate function mode */ 795 | GPIOF->MODER = 0xAA800AAA; 796 | /* Configure PFx pins speed to 50 MHz */ 797 | GPIOF->OSPEEDR = 0xAA800AAA; 798 | /* Configure PFx pins Output type to push-pull */ 799 | GPIOF->OTYPER = 0x00000000; 800 | /* No pull-up, pull-down for PFx pins */ 801 | GPIOF->PUPDR = 0x00000000; 802 | 803 | /* Connect PGx pins to FMC Alternate function */ 804 | GPIOG->AFR[0] = 0xcccccccc; 805 | GPIOG->AFR[1] = 0xcccccccc; 806 | /* Configure PGx pins in Alternate function mode */ 807 | GPIOG->MODER = 0xaaaaaaaa; 808 | /* Configure PGx pins speed to 50 MHz */ 809 | GPIOG->OSPEEDR = 0xaaaaaaaa; 810 | /* Configure PGx pins Output type to push-pull */ 811 | GPIOG->OTYPER = 0x00000000; 812 | /* No pull-up, pull-down for PGx pins */ 813 | GPIOG->PUPDR = 0x00000000; 814 | 815 | /* Connect PHx pins to FMC Alternate function */ 816 | GPIOH->AFR[0] = 0x00C0CC00; 817 | GPIOH->AFR[1] = 0xCCCCCCCC; 818 | /* Configure PHx pins in Alternate function mode */ 819 | GPIOH->MODER = 0xAAAA08A0; 820 | /* Configure PHx pins speed to 50 MHz */ 821 | GPIOH->OSPEEDR = 0xAAAA08A0; 822 | /* Configure PHx pins Output type to push-pull */ 823 | GPIOH->OTYPER = 0x00000000; 824 | /* No pull-up, pull-down for PHx pins */ 825 | GPIOH->PUPDR = 0x00000000; 826 | 827 | /* Connect PIx pins to FMC Alternate function */ 828 | GPIOI->AFR[0] = 0xCCCCCCCC; 829 | GPIOI->AFR[1] = 0x00000CC0; 830 | /* Configure PIx pins in Alternate function mode */ 831 | GPIOI->MODER = 0x0028AAAA; 832 | /* Configure PIx pins speed to 50 MHz */ 833 | GPIOI->OSPEEDR = 0x0028AAAA; 834 | /* Configure PIx pins Output type to push-pull */ 835 | GPIOI->OTYPER = 0x00000000; 836 | /* No pull-up, pull-down for PIx pins */ 837 | GPIOI->PUPDR = 0x00000000; 838 | 839 | /*-- FMC Configuration ------------------------------------------------------*/ 840 | /* Enable the FMC interface clock */ 841 | RCC->AHB3ENR |= 0x00000001; 842 | 843 | /* Configure and enable SDRAM bank1 */ 844 | FMC_Bank5_6->SDCR[0] = 0x000029D0; 845 | FMC_Bank5_6->SDTR[0] = 0x01115351; 846 | 847 | /* SDRAM initialization sequence */ 848 | /* Clock enable command */ 849 | FMC_Bank5_6->SDCMR = 0x00000011; 850 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 851 | while((tmpreg != 0) & (timeout-- > 0)) 852 | { 853 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 854 | } 855 | 856 | /* Delay */ 857 | for (index = 0; index<1000; index++); 858 | 859 | /* PALL command */ 860 | FMC_Bank5_6->SDCMR = 0x00000012; 861 | timeout = 0xFFFF; 862 | while((tmpreg != 0) & (timeout-- > 0)) 863 | { 864 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 865 | } 866 | 867 | /* Auto refresh command */ 868 | FMC_Bank5_6->SDCMR = 0x00000073; 869 | timeout = 0xFFFF; 870 | while((tmpreg != 0) & (timeout-- > 0)) 871 | { 872 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 873 | } 874 | 875 | /* MRD register program */ 876 | FMC_Bank5_6->SDCMR = 0x00046014; 877 | timeout = 0xFFFF; 878 | while((tmpreg != 0) & (timeout-- > 0)) 879 | { 880 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 881 | } 882 | 883 | /* Set refresh count */ 884 | tmpreg = FMC_Bank5_6->SDRTR; 885 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 886 | 887 | /* Disable write protection */ 888 | tmpreg = FMC_Bank5_6->SDCR[0]; 889 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 890 | 891 | /* 892 | Bank1_SDRAM is configured as follow: 893 | 894 | FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; 895 | FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6; 896 | FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; 897 | FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6; 898 | FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; 899 | FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; 900 | FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; 901 | 902 | FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK; 903 | FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; 904 | FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b; 905 | FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; 906 | FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; 907 | FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; 908 | FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; 909 | FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; 910 | FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable; 911 | FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; 912 | FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; 913 | */ 914 | 915 | } 916 | #endif /* DATA_IN_ExtSDRAM */ 917 | 918 | 919 | /** 920 | * @} 921 | */ 922 | 923 | /** 924 | * @} 925 | */ 926 | 927 | /** 928 | * @} 929 | */ 930 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 931 | -------------------------------------------------------------------------------- /usart.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/USART_Printf/main.c 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief Main program body 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *
© COPYRIGHT 2013 STMicroelectronics
12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "usart.h" 30 | 31 | /** @addtogroup STM32F4xx_StdPeriph_Examples 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup USART_Printf 36 | * @{ 37 | */ 38 | 39 | /* Private typedef -----------------------------------------------------------*/ 40 | /* Private define ------------------------------------------------------------*/ 41 | /* Private macro -------------------------------------------------------------*/ 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* Private function prototypes -----------------------------------------------*/ 44 | 45 | 46 | #ifdef __GNUC__ 47 | /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf 48 | set to 'Yes') calls __io_putchar() */ 49 | #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) 50 | #else 51 | #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) 52 | #endif /* __GNUC__ */ 53 | 54 | 55 | 56 | void USART_Config(void) 57 | { 58 | USART_InitTypeDef USART_InitStructure; 59 | 60 | /* USARTx configured as follows: 61 | - BaudRate = 115200 baud 62 | - Word Length = 8 Bits 63 | - One Stop Bit 64 | - No parity 65 | - Hardware flow control disabled (RTS and CTS signals) 66 | - Receive and transmit enabled 67 | */ 68 | USART_InitStructure.USART_BaudRate = 115200; 69 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 70 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 71 | USART_InitStructure.USART_Parity = USART_Parity_No; 72 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS; 73 | USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 74 | 75 | STM_EVAL_COMInit(COM1, &USART_InitStructure); 76 | 77 | 78 | // USART1->BRR = 0x0fa; 79 | // USART1->BRR = 0x030d; 80 | 81 | } 82 | 83 | void USART_Transmit(uint8_t ch_data) 84 | { 85 | // Loop until the end of transmission 86 | while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) 87 | { 88 | ; 89 | } 90 | USART_SendData(EVAL_COM1, (uint8_t)ch_data); 91 | } 92 | 93 | /** 94 | * @brief Retargets the C library printf function to the USART. 95 | * @param None 96 | * @retval None 97 | */ 98 | PUTCHAR_PROTOTYPE 99 | { 100 | /* Place your implementation of fputc here */ 101 | /* e.g. write a character to the USART */ 102 | USART_SendData(EVAL_COM1, (uint8_t) ch); 103 | 104 | /* Loop until the end of transmission */ 105 | while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) 106 | {} 107 | 108 | return ch; 109 | } 110 | 111 | #ifdef USE_FULL_ASSERT 112 | 113 | /** 114 | * @brief Reports the name of the source file and the source line number 115 | * where the assert_param error has occurred. 116 | * @param file: pointer to the source file name 117 | * @param line: assert_param error line source number 118 | * @retval None 119 | */ 120 | void assert_failed(uint8_t* file, uint32_t line) 121 | { 122 | /* User can add his own implementation to report the file name and line number, 123 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 124 | 125 | /* Infinite loop */ 126 | while (1) 127 | { 128 | } 129 | } 130 | #endif 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 141 | -------------------------------------------------------------------------------- /usart.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file USART/USART_Printf/main.h 4 | * @author MCD Application Team 5 | * @version V1.3.0 6 | * @date 13-November-2013 7 | * @brief Header for main.c module 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *
© COPYRIGHT 2013 STMicroelectronics
12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __usart_H 30 | #define __usart_H 31 | 32 | /* Includes ------------------------------------------------------------------*/ 33 | #include "stm32f4xx.h" 34 | #include 35 | 36 | 37 | #include "stm324x9i_eval.h" 38 | void USART_Config(void); 39 | void USART_Transmit(uint8_t ch_data); 40 | 41 | /* Exported typedef ----------------------------------------------------------*/ 42 | /* Exported define -----------------------------------------------------------*/ 43 | /* Exported types ------------------------------------------------------------*/ 44 | /* Exported constants --------------------------------------------------------*/ 45 | /* Exported macro ------------------------------------------------------------*/ 46 | /* Exported functions ------------------------------------------------------- */ 47 | 48 | #endif /* __MAIN_H */ 49 | 50 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 51 | --------------------------------------------------------------------------------