├── README.md ├── types └── 4 - mass storage.txt ├── template.md ├── CPU ├── ROM.md ├── clock.md ├── cpu-control.md └── DCPU.md ├── Simple Outputs ├── speaker.md ├── Luxul-pi.md └── HSDP-1D.md ├── Storage ├── DecaSys-EEPROM.md ├── m525hd.md └── m35fd.txt ├── Navigation ├── TalonNav-LPS.md ├── tracking.txt ├── pps.txt └── radar.txt ├── device-type.md ├── Input ├── keyboard.md └── daca.md ├── TC-IDs.md ├── IO Data ├── KaiComm-SSI.md ├── KaiComm-RACM.md ├── KaiComm-HIC.md └── KaiComm-RCI.md ├── Sensors └── LifeSYS-GCA3623.md ├── Displays ├── LEM1802.txt ├── IMVA.md ├── PIXIE.txt └── EDC.md ├── CraftComponents └── VTACI.md └── HIC-Misc └── elevator.md /README.md: -------------------------------------------------------------------------------- 1 | # TC-Specs 2 | -------------------------------------------------------------------------------- /types/4 - mass storage.txt: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /template.md: -------------------------------------------------------------------------------- 1 | Spec Template 2 | ---- 3 | 4 | ``` 5 | ASCII LOGO 6 | ``` 7 | 8 | | Item | Value | Comment 9 | | -------------: | ---------- | ---------------- 10 | | Vendor code | 0x0000 | (NAME) 11 | | Device ID | 0x0000 | (DEVICEID) 12 | | Device type | 0x0000 | (Highest 16 bits from Device ID) 13 | | Version | 0x0000 | Version Code 14 | 15 | Device Description 16 | 17 | Interrupt Commands 18 | ---- 19 | 20 | - **0x0000**: Friendly name of command 21 | 22 | 23 | Behaviours 24 | ---- 25 | List any unquie behaviours that should be simulated. 26 | -------------------------------------------------------------------------------- /CPU/ROM.md: -------------------------------------------------------------------------------- 1 | ROM 2 | ---- 3 | 4 | | Item | Value | Comment 5 | | -------------: | ---------- | ---------------- 6 | | Device type ID | 0x17400011 | Flashable ROM 7 | | Version | 1 | dictates size 8 | 9 | Device Description 10 | ---- 11 | The default built in ROM that provides bootloading capacity. 12 | 13 | Interrupt Commands 14 | ---- 15 | 16 | - **0x0000**: INIT 17 | - 0: Copy the boot sector of the installed disk to memory and execute it. 18 | - **0x0001**: FLASH 19 | - B: Flash ROM. B is offset to source 20 | 21 | 22 | Behaviours 23 | ---- 24 | Interrupt 0 occurs at boot. 25 | 26 | -------------------------------------------------------------------------------- /Simple Outputs/speaker.md: -------------------------------------------------------------------------------- 1 | Speaker Hardware 2 | ---- 3 | 4 | ``` 5 | No ASCII logo yet 6 | ``` 7 | 8 | | Item | Value | Comment 9 | | -------------: | ---------- | ---------------- 10 | | Vendor code | 0x5672746B | VARTOK_HW 11 | | Device ID | 0xC0F00001 | Speaker 12 | | Device type | 0xC0F0 | Fixed-amplitude speaker 13 | | Version | 0x0001 | Version Code 14 | 15 | This hardware can generate beeps on two separate channels with variable frequency. The amplitude is fixed for both of them with the second channel being slightly quieter. 16 | 17 | Interrupt Commands 18 | ---- 19 | 20 | - **0x0000**: SET_FREQUENCY_CHANNEL_1 21 | - Set frequency of first channel to value read from register B in Hz. 22 | 23 | - **0x0001**: SET_FREQUENCY_CHANNEL_2 24 | - Set frequency of first channel to value read from register B in Hz. 25 | 26 | Behaviours 27 | ---- 28 | If the value in B is 0, that channel is turned off (which is the default state assumed at start-up). 29 | -------------------------------------------------------------------------------- /Storage/DecaSys-EEPROM.md: -------------------------------------------------------------------------------- 1 | EEPROM 2 | ---- 3 | ``` 4 | ______ ______ 5 | |_ _ `..' ____ \ 6 | | | `. | (___ \_| 7 | | | | |_.____`. 8 | _| |_.' | \____) | 9 | |______.' \______.' 10 | 11 | ``` 12 | Device Description 13 | ---- 14 | The DecaSys EEPROM can be built into various devices to store supplementary data. Holds 16 words, that can only be read or written a single word at a time. 15 | Due to constraints in trying to build this capability into such a small package, bits in a single word can only be CLEARED. In order to SET a bit, you have to reset the entire device to all 1's, and then set individual words to their new values. 16 | 17 | Interrupt Commands 18 | ---- 19 | All interrupt commands are done with A set to 0xFFF0, sent to the same device as the EEPROM is attached to. Register B is used to select the command, and X and Y are used for address and data. 20 | - A - **0xFFF0**: 21 | - B - **0x0001**: READ 22 | - Reads word from address X and stores it in register Y. 23 | - Takes 1ms to read a word 24 | - B - **0x0002**: WRITE 25 | - Writes word from register Y to address X. Note that writing to the EEPROM can only clear bits, not set them, so you may need to clear the EEPROM to write new values. 26 | - Takes 5ms to write a word 27 | - B - **0x0003**: RESET 28 | - Resets all words to 0xFFFF 29 | - Takes 10ms to reset 30 | 31 | -------------------------------------------------------------------------------- /Navigation/TalonNav-LPS.md: -------------------------------------------------------------------------------- 1 | ``` 2 | 3 | \\ TALON NAVIGATION // 4 | "walk among the stars" 5 | 6 | ``` 7 | 8 | DCPU-16 Hardware Info: 9 | 10 | | Item | Value | Comment 11 | | -------------: | ---------- | ---------------- 12 | | Vendor code | 0x982d3e46 | TALON NAVIGATION SYSTEMS 13 | | Device ID | 0xfce24728 | Local Positioning System (navigator) 14 | | Version | 0xc59f | 15 | 16 | 17 | Description: 18 | LPS is an entirely local positioning system, using a beacon and receiver 19 | setup. This device will lock onto the nearest beacon with a specified ID, 20 | using a doppler reciever to triangulate both position and velocity relative 21 | to the beacon. 22 | 23 | The Talon LPS has a massive range of 16km, and is accurate to the nearest mm. 24 | Guaranteed to lock on in under 5 seconds or your money back! 25 | (Note: Guarantee applies only in free space with fully functioning Talon Navigation 26 | Systems LPS Beacon within 16km of receiver, presence of multiple beacons with same ID 27 | may lead to undefined behaivour and voids warranty.) 28 | 29 | Interrupt behavior: 30 | When a HWI is received by the LPS, it reads the A register and does one 31 | of the following actions: 32 | 33 | 0: SET_TARGET_ID 34 | Sets the target beacon ID to the value of the B register. 35 | 36 | 1: GET_LOCAL_COORDINATES 37 | Stores the current position data to DCPU-16 registers X and Y. 38 | 39 | Depending on the value of the B register, stores a value in X and Y, 40 | encoded as an INT32 with least significant part in X. 41 | 42 | B value: Value returned 43 | 0: Relative x-coordinate position in mm 44 | 1: Relative y-coordinate position in mm 45 | 2: Relative z-coordinate position in mm 46 | 47 | 3: Relative x-coordinate velocity in mm/s 48 | 4: Relative y-coordinate velocity in mm/s 49 | 5: Relative z-coordinate velocity in mm/s 50 | 51 | 52 | Register C is set with the operation status: 53 | 0x0000 : Success 54 | 0x0001 : Success, but reduced accuracy 55 | 0x8000 : No fix 56 | 0xffff : Equipment malfunction 57 | 58 | -------------------------------------------------------------------------------- /CPU/clock.md: -------------------------------------------------------------------------------- 1 | Generic Clock 2 | ---- 3 | 4 | | Item | Value | Comment 5 | | -------------: | ---------- | ---------------- 6 | | Vendor code | 0x1c6c8b36 | NYA Elektriska 7 | | Compatible ID | 0x12d0b402 | Generic Clock (Older models) 8 | | Device type ID | 0x12d1b402 | Generic Timer 9 | | Version | 2 | Fixed Version 10 | 11 | Device Description 12 | ---- 13 | 14 | Generic clock that can be used to time short periods, and can report the 15 | absolute time and date. 16 | 17 | This device is backwards compatible with the original version 1 clock. 18 | 19 | 20 | Interrupt Commands 21 | ---- 22 | 23 | - **0x0000**: `SET_SPEED` 24 | - B: Clock is set to 60/B ticks per second. Set B to zero to disable. 25 | - **0x0001**: `GET_TICKS` 26 | - C: Number of ticks since last call in C 27 | - **0x0002**: `SET_INT` 28 | - B: Interrupt message set to B. Zero to disable. 29 | - **0x0010**: `REAL_TIME` 30 | - Returns the absolute time in the Common Era, in the format below. 31 | - **0x0011**: `RUN_TIME` 32 | - Returns the elapsed time since power was applied, in the format below. 33 | - **0x0012**: `SET_REAL_TIME` 34 | - Sets the absolute time, based on the format below. 35 | - **0xffff**: `RESET` 36 | - Resets to initial state, as though the DCPU was restarted. (Timer 37 | disabled, elapsed run time reset to 0.) 38 | 39 | 40 | Real Time Format 41 | ---- 42 | The REAL_TIME interrupt returns time in the following format: 43 | 44 | - `B`: Year (Earth year, CE/AD) 45 | - `C`: Month and date 46 | - Month is high byte; 1 = January, 12 = December 47 | - Date is low byte; days into the month, 1-31. 48 | - `X`: Hours and Minutes 49 | - Hours are high byte; 0-23, where 0 is midnight, 12 is noon. 50 | - Minutes are low byte; 0-59 51 | - `Y`: Seconds; 0-59 52 | - `Z`: Milliseconds; 0-999 53 | 54 | Run Time Format 55 | ---- 56 | The RUN_TIME interrupt returns time in the following format: 57 | 58 | - `C`: Days 59 | - Number of days 60 | - `X`: Hours and Minutes 61 | - Hours are high byte; 0-23 62 | - Minutes are low byte; 0-59 63 | - `Y`: Seconds; 0-59 64 | - `Z`: Milliseconds; 0-999 65 | 66 | Frame of Reference 67 | ---- 68 | The time returned by a brand new clock device is undefined. The clock must be 69 | set from an outside source. 70 | 71 | Implementors are encouraged to include a clock battery, to hold the time even 72 | when power is disconnected. Consult your system's documentation. 73 | 74 | Behaviours 75 | ---- 76 | When interrupts are enabled, the clock will trigger an interrupt on each tick. 77 | 78 | -------------------------------------------------------------------------------- /device-type.md: -------------------------------------------------------------------------------- 1 | 2 | Device Type Codes 3 | ----- 4 | 5 | ``` 6 | /-------- Hardware class 7 | | /--- Hardware sub-class 8 | | | /--- vendor unique device ID 9 | ---- ---- ------------------- 10 | 0100 1111 1101 0001 0111 1110 1001 0001 11 | ---- |||| 12 | | |||\-- can generate interrupts 13 | | ||\--- reset with 0xffff interrupt supported 14 | | |\---- memory mapped 15 | | \----- supports extended API 16 | \--- Hardware class API 17 | ``` 18 | 19 | ## Hardware Class API 20 | 21 | For every hardware class, there may exist a hardware class API. 22 | All devices with the same hardware class and standard API ID can be used in the same generic way. 23 | * Standard API IDs are 0x0 - 0xD. 24 | * 0xE means a standard API based on sub-class is used. 25 | * 0xF means the device does not support standard API 26 | 27 | 28 | ## Hardware Classes and Sub-classes 29 | 30 | * 0 - expansion buses 31 | * 1 - integrated devices 32 | * 1 - CPU or interrupt controllers 33 | * 2 - timers 34 | * 3 - RNG 35 | * 4 - real time clocks 36 | * 7 - ROMs and EEPROMs 37 | * 2 - sensors (input only devices) 38 | * 3 - human interfacing specific devices 39 | * 0 - keyboards 40 | * 1 - Game Controllers 41 | * 4 - mass storage 42 | * 0-7 32+ bit addressable 43 | * 8-F 16 bit addressable 44 | * 4 - 32 bit, fixed disk drives 45 | * A - 16 bit, fixed disk drives 46 | * F - 16 bit, floppy drives 47 | * 5 - memory controllers 48 | * 1 DMA 49 | * 4 non-volatile memory devices 50 | * 6 - multimedia capture 51 | * 7 - raster display (2D) 52 | * 0 - text cell based, command driven, monochrome display 53 | * 1 - text cell based, memory mapped, monochrome display 54 | * 2 - text cell based, command driven, color display 55 | * 3 - text cell based, memory mapped, color display 56 | * 4 - pixel based, command driven, monochrome display 57 | * 5 - pixel based, memory mapped, monochrome display 58 | * 6 - pixel based, command driven, color display 59 | * 7 - pixel based, memory mapped, color display 60 | * 8 - pixel based, memory mapped, color/monochrome video card 61 | * 8 - vector display 62 | * 2 - 2D vector 63 | * 3 - 3D holographic 64 | * 9 - co-processors/other CPUs/microcontrollers 65 | * A - reserved/future use 66 | * B - reserved/future use 67 | * C - generic output only devices 68 | * D - wireless devices 69 | * 0 - Packet radio transceivers 70 | * E - wired network/communication 71 | * 0 - parallel port 72 | * 1 - serial port 73 | * F - non-standard devices 74 | * 7 - thrust controllers 75 | 76 | -------------------------------------------------------------------------------- /Input/keyboard.md: -------------------------------------------------------------------------------- 1 | Generic Keyboard 2 | ---- 3 | 4 | ``` 5 | ---=I NEED A LOGO=--- 6 | ``` 7 | 8 | | Item | Value | Comment 9 | | -------------: | ---------- | ---------------- 10 | | Vendor code | 0x1c6c8b36 | NYA Elektriska 11 | | Compatible ID | 0x30cf7406 | Generic Keyboard (older models) 12 | | Device type ID | 0x30c17406 | Generic ASCII Keyboard 13 | | Version | 1 | Fixed Version 14 | 15 | A generic input keyboard. All input is buffered in an 8 item queue, excess keys presses push the earliest keypress off the queue. In addition, the "CHECK_KEY" functionality will only work with up to 8 keys pressed simultaneously. 16 | 17 | Interrupt Commands 18 | ---- 19 | 20 | - **0x0000**: CLEAR_BUFFER 21 | - 0: Clears the keyboard buffer 22 | - **0x0001**: GET_NEXT 23 | - C: Store next key from buffer to C register, or 0 if the buffer is empty 24 | - **0x0002**: CHECK_KEY 25 | - B+C: Check if key in B is current pressed. Set C to result (1 = true, 0 =false) 26 | - **0x0003**: SET_INT 27 | - B: Interrupt message set to B. Zero to disable 28 | - **0x0004**: SET_MODE 29 | - B: Keyboard mode set to B(0 = smart text, 1=generic keycode). Buffer is cleared. 30 | 31 | Behaviours 32 | ---- 33 | The keyboard driver is capable of operating in 2 distinct modes: Smart text input, and generic keycode input. The keyboard driver defaults to Smart text input, but can be switched to either mode via interrupt 0x0004. 34 | 35 | Smart Text Mode 36 | =============== 37 | While in smart text mode, the keyboard driver will automatically parse incoming keypresses, and yield a stream of character events. These events will be fully translated, so "shift-a" will be sent as "A". Unfortunately, the keyboard driver is unable to give keydown/up status for more then a few specific keys in this state, notably the "modifier" keys: ctrl, shift, alt. The interrupt will fire only when a new event is added to the key buffer. 38 | 39 | In addition to standard alphanumerics and symbols, the keyboard driver will also encode specific additional keys as follows: 40 | - 0x10: Backspace 41 | - 0x11: Return 42 | - 0x12: Insert 43 | - 0x13: Delete 44 | - 0x20-0x7f: ASCII characters 45 | - 0x80: Arrow up 46 | - 0x81: Arrow down 47 | - 0x82: Arrow left 48 | - 0x83: Arrow right 49 | - 0x90: Shift 50 | - 0x91: Control 51 | - 0x92: Alt 52 | 53 | - ASCII letters are uppercase when shift is held down. 54 | 55 | Generic Keycode Mode 56 | ==================== 57 | While in generic keycode mode, the keyboard driver will not parse incoming key events, and instead will queue them unmodified to the key buffer. It will encode both key down and key up events, with the highest bit, 0x8000, set if the event is a key up, with the interrupt firing on every addition to the buffer. 58 | -------------------------------------------------------------------------------- /TC-IDs.md: -------------------------------------------------------------------------------- 1 | Currently used IDs 2 | ================== 3 | * `0x1C6C8B36` - Nya Elektriska 4 | * `0x12D1B402` - ver `0x0001` - [Generic Timer](CPU/clock.md) 5 | * `0x30C17406` - ver `0x0001` - [Generic ASCII Keyboard](Input/keyboard.md) 6 | * `0x734DF615` - ver `0x1802` - [Low Energy Monitor](Displays/LEM1802.txt) 7 | 8 | * `0x1EB37E91` - Mackapar Media 9 | * `0x4AC5525D` - ver `0x0001` - [Mackapar 5.25" Hard Disk Drive](Storage/m525hd.md) 10 | * `0x4FD524C5` - ver `0x000B` - [Mackapar 3.5" Floppy Drive](Storage/m35fd.txt) 11 | 12 | * `0x4c534453` - LifeSys 13 | * `0x2FF23233` - ver `~ ` - [LifeSys GCA](Sensors/LifeSYS-GCA3623.md) 14 | 15 | * `0x59EA5742` - Meisaka Engineering and Integration 16 | * `0x70E3E4FF` - ver `~ ` - [Embedded Display Controller](Displays/EDC.md) 17 | * `0x75F6A113` - ver `0x0538` - [IMVA](Displays/IMVA.md) 18 | 19 | * `0x83610EC5` - Agnus Micro Devices 20 | * `0x774df615` - ver `0x1802` - [PIXIE](Displays/PIXIE.txt) 21 | 22 | * `0x982D3E46` - Talon Navigation Systems 23 | * `0xFCE24728` - ver `0xC59F` - [Local Positioning System](Navigation/TalonNav-LPS.md) 24 | * `0XFCE26509` - ver `0xB01E` - [Pulsar Positioning System](Navigation/pps.txt) 25 | 26 | * `0xA87C900E` - Kai Communications 27 | * `0xD0F090C0` - ver `0x0001` - [Remote Activity Control Module](IO%20Data/KaiComm-RACM.md) 28 | * `0xD00590A5` - ver `0x0010` - [Radiofrequency Communication Interface](IO%20Data/KaiComm-RCI.md) 29 | * `0xE0239088` - ver `~ ` - [Hardware Interface Card](IO%20Data/KaiComm-HIC.md) 30 | * `0xE57D9027` - ver `0x0103` - [Synchronous Serial Interface](IO%20Data/KaiComm-SSI.md) 31 | 32 | * `0xB8BADDE8` - Otec 33 | * `0x3846BC64` - ver `0x6673` - [FF32-EM Radar](Navigation/radar.txt) 34 | * `0x3846BC64` - ver `0x6673` - [Tracking Theodolite TT-Z80](Navigation/tracking.txt) 35 | 36 | * `0xC2200311` - Rin Yu Research 37 | * `0xF7F7EE03` - ver `0x0400` - [Vectored Thruster Array Control Interface](CraftComponents/VTACI.md) 38 | 39 | * `0x5672746B` - Vartok hardware 40 | * `0xC0F00001` - ver `0x0001` - [Speaker Hardware](Simple%20Outputs/speaker.md) 41 | 42 | * `0x621CAF3A` - VeXXaN Performance Peripherals 43 | * `0x31E1DACA` - ver `0x0001` - [Digital/Analog Control Adapter](Input/daca.md) 44 | 45 | * Various Vendors 46 | * `0x11E0DACC` - ver `0x0004` - [Integrated Activity Control Module](CPU/cpu-control.md) 47 | * `0x17400011` - ver `~ ` - [Flashable ROM](CPU/ROM.md) 48 | 49 | * `0xf6976d00` - Chartronics, Inc. 50 | * `0xcff2a11d` - ver `0x0001` - [HSDP-1D High Speed Data Printer](Simple%20Outputs/HSDP-1D.md) 51 | 52 | Peripherals (HIC/SSI) 53 | ===================== 54 | 55 | * `0x010C337D` - Luxul 56 | * `0x41F20003` - ver `0x002A` - [Photon Indicator](Simple%20Outputs/Luxul-pi.md) 57 | 58 | * `0x59EA5742` - Meisaka Engineering and Integration 59 | * `0x70E3E4FF` - ver `~ ` - [Embedded Display Controller](Displays/EDC.md) 60 | -------------------------------------------------------------------------------- /Input/daca.md: -------------------------------------------------------------------------------- 1 | VeXXaN Digital/Analog Control Adapter 2 | ---- 3 | 4 | ``` 5 | __ ____ __ __ _ __ 6 | /\ /\___\ \/ /\ \/ /__ \ / \ /_/ 7 | \ \ / / _ \\ / \ // _ / ^ \ 8 | __ \ V / __// \ / \\___/ / \ \ 9 | /_/ \_/ \___/_/\_\/_/\_\ \/ \/ 10 | 11 | ``` 12 | 13 | 14 | | Item | Value | Comment 15 | | -------------: | ---------- | ---------------- 16 | | Vendor code | 0x621CAF3A | VeXXaN Performance Peripherals 17 | | Device ID | 0x31E1DACA | Digital/Analog Control Adapter 18 | | Device type | 0x31E1 | Human Interface Device, Game Controller, Can Generate Interrupts 19 | | Version | 0x0001 | Version 1 20 | 21 | Device Description 22 | 23 | VeXXaN Performance Peripherals(tm) is proud to announce the only control adapter you will ever need! With the ability to connect up to 4(!) 8-bit joysticks* and 16 buttons using a standard DB25 connection, the days of direct attached game controllers ARE! IN! THE! PAST! I personally guarantee that you will find more uses for this adapter than you ever thought possible! Remote control vehicles? Done! Arcade Machines? Sure! Spacecraft controls? You Betcha!** Order within the next 5 Minutes and we'll throw in our patented No-Slip rubberized joystick base and a full set of our low-travel digital buttons! (just pay seperate processing and handling)*** And, Best of all, If you're not 100,000% satisfied with your brand new DACA, simply return it for a full refund.**** 24 | 25 | \*The DACA supports 4 single axis joysticks, 2 2-axis joysticks, or 1 3-axis joystick and 1 single axis joystick. 26 | \*\*VeXXaN Performance Peripherals(tm) does in no way certify our Digital/Analog Control Adapter for use in spacecraft control. VeXXaN Performance Peripherals(tm) will not be held liable for such uses. 27 | \*\*\*Offer not available in the greater megallenic cloud. 28 | \*\*\*\*Just pay return processing and handling. 29 | 30 | 31 | Interrupt Commands 32 | ---- 33 | On Interrupt, Register A holds a command 34 | 35 | - **0x0000**: Poll Device 36 | 37 | - Loads the state of the device into registers A, B, and C in the following format: 38 | - A:[Axis 0][Axis 1] 39 | - B:[Axis 2][Axis 3] 40 | - C:[button 15 - 1 ] 41 | 42 | - **0x0001**: Poll Analog 43 | 44 | - Loads the state of the analog ports into registers A and B in the following format: 45 | - A:[Axis 0][Axis 1] 46 | - B:[Axis 2][Axis 3] 47 | 48 | 49 | - **0x0002**: Poll Digital 50 | 51 | - Loads the state of the digital ports into register C in the following format: 52 | 53 | - C:[ Button 15-1 ] 54 | 55 | - **0x0003**: Enable Interrupts 56 | 57 | - Enable interrupts on the device. Interrupt message is set to B. 58 | 59 | Behaviours 60 | ---- 61 | When interrupts are enabled, the device will interrupt on any button press. Changes in the state of any of the analog ports will not trigger an interrupt (To prevent large amounts of interrupts being generated by low quality hardware). The analog axis will give an unsigned value betwen 0x01 and 0xFE. Self centering joysticks will hover around 0x7F. If any port is empty it will report 0x00. Buttons are active-high and will report 1 when pressed, 0 otherwise. 62 | -------------------------------------------------------------------------------- /IO Data/KaiComm-SSI.md: -------------------------------------------------------------------------------- 1 | KaiComm Synchronous Serial Interface 2 | ---- 3 | 4 | ``` 5 | | \ Kai 6 | >| \\ Communications 7 | >| \\\ 8 | >| /// 9 | >| // 10 | | / 11 | ``` 12 | 13 | | Item | Value | Comment 14 | | -------------: | ---------- | ---------------- 15 | | Vendor code | 0xA87C900E | (KaiComm) 16 | | Device type | 0x02 | (Communications) 17 | | Device Subtype | 0x03 | (Sync serial) 18 | | Device ID | 0x20 | (SSI) 19 | | DCPU Device ID | 0xE57D9027 | (KaiComm SSI 2) 20 | | Version | 0x0103 | 21 | 22 | The KaiComm SSI is a bi-directional data port. 23 | Transmissions in either direction are independent of each other and can operate at different bauds. 24 | The size of the data primitive is selectable ranging from 1 to 4 octets. 25 | All data are assumed to be sent MSB first. 26 | 27 | Commands 28 | ---- 29 | 30 | On interrupt, register A holds a command that the SPI will perform: 31 | 32 | - **0x0000**: Query status 33 | Sets Register A with status, bits will be set/clear as follows: 34 | - Bit 0 - Line is busy/not-connected (1), or idle (0) 35 | - Bit 1 - Receiving Active (1), or idle (0) 36 | - Bit 2 - Data available (1), or not (0) 37 | - Bit 3 - Transmitting Active (1), or idle (0) 38 | - Bit 4 - Transmit buffer is free (1), or full (0) 39 | - Bit 5-13 Reserved always set to 0 40 | - Bit 14 - Receive interrupts enabled: yes (1), no (0) 41 | - Bit 15 - Transmit done interrupts enabled: yes(1), no (0) 42 | - **0x0001**: Configure port 43 | Register B holds the octet size minus 1 in bits 0-1, other bits are ignored. 44 | Register C holds the baud selection in bits 0-7, giving a range of 0-255. 45 | The baud is calculated like so: baud = 3125 * (b+1) 46 | Possible bauds range from 3125 to 800,000 bits per second, in steps of 3125 bits per second. 47 | - **0x0002**: Receive data 48 | Register A is set to the lower 16 bits, register B is set to the upper 16 bits. 49 | Register C is set with the error status, receive error status is cleared when read. 50 | when configured for less than 4 octets unused bits are set to 0. 51 | Receive Error status codes: 52 | - 0x0000 - No error 53 | - 0x0001 - Receive buffer overflow 54 | - 0x0002 - Transmission was not a multiple of 8 bits 55 | - 0x0003 - No data available 56 | - **0x0003**: Transmit data 57 | Register B contains the lower 16 bits, register C contains the upper 16 bits. 58 | when configured for less than 4 octets unused bits are ignored. 59 | Register C is set with error status. 60 | Transmit Error status codes: 61 | - 0x0000 - No error 62 | - 0x0001 - Transmit buffer overflow (data will not be sent) 63 | - 0x0002 - Line is busy or not connected (data will be queued) 64 | - **0x0004**: Configure interrupts 65 | Register B defines which interrupts to enable. 66 | - Bit 0 - Interrupt on Receive enabled: yes (1), no (0) 67 | - Bit 1 - Interrupt on Transmit done enabled: yes(1), no (0) 68 | - Bit 2-15 Ignored. 69 | Register C contains message for Interrupt on Receive. 70 | Register X contains message for Interrupt on Transmit. 71 | 72 | ---- 73 | 74 | 2014 Meisaka Yukara (CC-BY-SA 4.0) 75 | -------------------------------------------------------------------------------- /Navigation/tracking.txt: -------------------------------------------------------------------------------- 1 | 2 | O TTT EEE C 3 | O O T E C C 4 | O O T E C 5 | O O T EE C 6 | O O T E C 7 | O O T E C C 8 | O T EEE C - LEAVE FAR FIELD TO US! 9 | 10 | DCPU-16 Hardware Info: 11 | Name: Tracking Theodolite TT-Z80 12 | Version: 0x6673 13 | ID: 0x3846bc64 14 | Manufacturer: 0xb8badde8 (Otec) 15 | 16 | Description: 17 | Otec's premium Tracking Theodolite model TT-Z80 can accurately track a specified 18 | target with a modern interferometric techniques and light tracking motors. Advanced 19 | signal processing ensures data accuracy and reliability. 20 | 21 | Otec's Tracking Theodolite can operate at 20km range and is capable of tracking a 22 | single target with high accuracy and refresh rate. Refresh rate is close to 5HZ 23 | and refresh can be used to trigger an interrupt. 24 | 25 | NOTE: Tracking can be detected with Otec's tracking sensor array - sold separately. 26 | 27 | Interrupt behavior: 28 | 29 | When a HWI is received by the Theodolite, it reads the A register and does one of 30 | the following actions: 31 | 32 | 0: GET_STATUS 33 | Register B is set to hold tracking target's signal ID or 0 if no tracking in 34 | progress. 35 | 36 | Register C is set to TT-Z80 status 37 | 0x0000 Idle 38 | 0x0001 Tracking 39 | 0x0002 Target lost 40 | 0xffff Equipment malfunction 41 | 42 | 1: SET_TARGET 43 | Register B contains the target's signal ID (available e.g. from radar data). 44 | TT-Z80 will acquire target lock in less than 2 seconds and start providing tracking 45 | data. 46 | 47 | Signal ID 0 will stop tracking. 48 | 49 | Register C is set to status code for operation: 50 | 0x0000 Tracking starting 51 | 0x8000 Failure, unknown target 52 | 0xffff Failure, equipment malfunction 53 | 54 | 2: GET_TARGET_POSITION 55 | B: is set to contain a timestamp for the position data. Timestamp is 16 bit counter 56 | that increments every data refresh cycle and resets to zero at every 2^16 seconds. 57 | 58 | X: Target X-coordinate relative to theodolite (m) 59 | Y: target Y-coordinate relative to theodolite (m) 60 | Z: target Z-coordinate relative to theodolite (m) 61 | 62 | Register C is set to status code for operation: 63 | 0x0000 Success 64 | 0x8001 No target 65 | 0xffff Equipment malfunction 66 | 67 | Halts DCPU for 3 cycles. 68 | 69 | 3: GET_TARGET_VELOCITY 70 | B: is set to contain a timestamp for the velocity data. Timestamp is 16 bit counter 71 | that increments every data refresh cycle and resets to zero at every 2^16 seconds. 72 | 73 | X: Target velocity along X-axis relative to theodolite (m/s) 74 | Y: Target velocity along Y-axis relative to theodolite (m/s) 75 | Z: Target velocity along Z-axis relative to theodolite (m/s) 76 | 77 | Register C is set to status code for operation: 78 | 0x0000 Success 79 | 0x8001 No target 80 | 0xffff Equipment malfunction 81 | 82 | Halts DCPU for 3 cycles. 83 | 84 | 4: CONFIGURE_INTERRUPTS 85 | Register B contains message for Interrupt on target data refreshed, 0 means disable interrupt. 86 | -------------------------------------------------------------------------------- /CPU/cpu-control.md: -------------------------------------------------------------------------------- 1 | Integrated Activity Control Module 2 | ---- 3 | 4 | | Item | Value | Comment 5 | | -------------: | ---------- | ---------------- 6 | | Vendor code | | (Various) 7 | | Device ID | 0x11E0DACC | IACM 8 | | Device type | 0x11E0 | Integrated CPU controller 9 | | Version | 0x0004 | Version/highest mode supported 10 | 11 | Device Description 12 | ---- 13 | 14 | The integrated activity control module (or *IACM*) allows software to control on the processor: clock rate, interrupts, and power consumption. 15 | The IACM has 2 control buttons called "Power" and "Mode"; they are physically distinct and may be labelled various ways depending on the chassis. 16 | 17 | The IACM can be in one of several different modes determining the effects on the CPU: 18 | - Mode 0 - CPU runs at full rate/power as normal. 19 | - Mode 1 - CPU runs at reduced rate/power as normal. 20 | - Mode 2 - CPU runs at reduced rate/power, and is periodically put to sleep. 21 | - Mode 3 - CPU is put to sleep, interrupts to the CPU will cause the IACM to switch to mode 1. 22 | - Mode 4 - Power off the CPU, memory, and any internal hardware. 23 | 24 | Interrupt Commands 25 | ---- 26 | 27 | when interrupting the device, register A will act as a command index as follows: 28 | 29 | - **0x0000**: Set Mode - Change mode to the mode number in B, unsupported modes may cause undefined behaviour. 30 | - **0x0001**: Set RunTime - Set the amount of time to run while in mode 2. Register B holds the amount of time in 100 millisecond increments. Setting to zero resets to default. 31 | - **0x0002**: Set SleepTime - Set the amount of time to sleep while in mode 2. Register B holds the amount of time in 100 millisecond increments. Setting to zero resets to default. 32 | - **0x0003**: Set interrupt message - Sets the message to the value in B for the interrupt type in C. 33 | - Type 0: If message is non-zero, generate an interrupt when the "Power" button is pressed. 34 | - Type 1: If message is non-zero, generate an interrupt when the "Mode" button is pressed. 35 | - **0x0004**: Get clock rate - gets the normal CPU clock rate in Hz as a 32 bit number, B holds the lower 16 bits, C holds the upper 16 bits. 36 | - **0x0005**: Get r-clock rate - gets the reduced CPU clock rate Hz as a 32 bit number, B holds the lower 16 bits, C holds the upper 16 bits. 37 | - **0x0505**: Force the system to reset everything (including the IACM) 38 | 39 | Behaviour Details 40 | ---- 41 | 42 | When power is applied to the system or if the CPU resets, the IACM defaults to mode 0, powering up the CPU and running at full rate. 43 | While in mode 4, pressing the "Power" button will switch to mode 0, powering up the CPU. 44 | Holding the "Power" button for 4 seconds while in any mode other than 4, will force the IACM to enter mode 4 and power off the CPU, memory, etc. 45 | 46 | The reduced clock rate for CPUs is CPU specific, but usually 10th the normal rate. 47 | 48 | #### Mode 2 49 | The CPU will run for the amount of time set by "RunTime", then be put to sleep for the amount of time set by "SleepTime". 50 | If the CPU gets any interrupts from hardware (including the IACM), then it will be switched to running. 51 | The transition between run and sleep is controlled by a free running timer in the IACM; if the CPU switches to running because an interrupt during SleepTime, the CPU will run for the remainder of SleepTime plus the following RunTime. 52 | The default for RunTime and SleepTime is 5 (500 milliseconds), and is set at power on or CPU reset. 53 | 54 | -------------------------------------------------------------------------------- /Sensors/LifeSYS-GCA3623.md: -------------------------------------------------------------------------------- 1 | GCA3623 and GCA1823 2 | ---- 3 | ``` 4 | _____ ______ 5 | |_ _| .' ____ \ 6 | | | | (___ \_| 7 | | | _ _.____`. 8 | _| |__/ || \____) | 9 | |________| \______.' 10 | LifeSys, a wholly owned subsidiary of DecaSys 11 | ``` 12 | 13 | | Item | Value | Comment 14 | | -------------: | ---------- | ---------------- 15 | | Vendor code | 0x4c534453 | (LifeSys) 16 | | DCPU Device ID | 0x2FF23233 | (LifeSys GCA) 17 | | Version | 0x1823 | GCA1823 PDA Module 18 | | Version | 0x3623 | GCA3623 Standalone Unit 19 | 20 | Device Description 21 | ---- 22 | The LifeSys GCA3623 and GCA1823 are fully automated Gas Chromotography Analyzers, capable of analyzing any gas piped into them. 23 | The GCAs use only a very minute amount of gas, and are capable of determining the exact nature of the gases, as well as their concentrations. 24 | The GCA must be told to start an analysis operation, and thereafter takes approximately 10~20 seconds (15~30 seconds for the GCA1823) to fully analyze the gasses, depending on the number of gasses to analyze. In addition, the GCA will need 10 seconds to flush and recover from the analysis. 25 | 26 | Control 27 | ---- 28 | The GCA3623 and the GCA1823 use the same control protocol, though the GCA3623 runs over HIC and the GCA1823 runs off of interrupts from the DCPU. 29 | For the GCA3623, the commands are passed via HIC, and needs 1 or 2 words, the first being the command number, and the second being the parameter, if required. 30 | For the GCA1823, the commands use the HWI interrupt interface. The command number should be in register A, and the parameter, if one is needed, should be in register B. 31 | 32 | Commands 33 | ---- 34 | - **0x0000**: GET DEVICE STATUS 35 | - Gets the devices current status. 2 words, the first being the status code, and the second being the number of gasses identified in the latest run. Status Codes: 36 | - 0x0000: Device in standby, ready to perform an analysis. 37 | - 0x0001: Device performing an analysis. 38 | - 0x0002: Analysis complete, device flushing and recovery in progress. 39 | - 0xFFFF: Device malfunctioning. 40 | - **0x0001**: START ANALYSIS 41 | - Commands the device to begin an analysis. Analysis time varies depending on multiple factors. 42 | - Once analysis has begun, prior results are no longer accessible. 43 | - **0x0002**: GET GAS 44 | - This command uses the second paramter to specify which gas index to get information on. This parameter must be between 0 and the number of gasses minus 1. 45 | - Returns 2 words, the first being an identifier for the specific gas, and the second being it's relative concentration, between 1 and 65535. All of the gasses in the gas index will add up to a total concentration of 65535. 46 | - Gas Identifiers: 47 | - 0x0001: Oxygen (O2) 48 | - 0x0002: Carbon Dioxide (CO2) 49 | - 0x0003: Nitrogen (N2) 50 | - **0x0003**: GET PRESSURE 51 | - This command returns the total pressure of the gasses at the start of the latest completed analysis cycle. 52 | - Return is in decapascals 53 | - **0xFFFE**: DEVICE QUERY 54 | - For serial connections: Causes the display to transmit 5 words containing vendor code, device ID and version 55 | - For direct DCPU connections: Has the same effect as an HWQ instruction. 56 | - **0xFFFF**: DEVICE RESET 57 | - Resets the device, removing the latest test results, and canceling any analysis in progress. If an analysis is in progress, the device will need to flush and recover before being able to perform another analysis. 58 | -------------------------------------------------------------------------------- /Navigation/pps.txt: -------------------------------------------------------------------------------- 1 | 2 | \\ TALON NAVIGATION // 3 | "walk among the stars" 4 | 5 | 6 | DCPU-16 Hardware Info: 7 | Name: Pulsar Positioning System (navigator) 8 | ID: 0xfce26509 9 | Version: 0xb01e 10 | Manufacturer: 0x982d3e46 (TALON NAVIGATION SYSTEMS) 11 | 12 | Description: 13 | PPS can determine it's position using radio-wave and x-ray signals 14 | from pulsars. PPS can function anywhere in Milky Way galaxy, but it 15 | requires a dish antenna of 2m in diameter. Talon is the only provider 16 | of PPS systems that can utilize over 2000 beacon pulsars for 17 | measuring position. 18 | 19 | Talon PPS hardware provides the fastest signal acquisition on market. 20 | It can cold start (no time, no position, no ephemeris) in <55 seconds 21 | and measure new position data every 8-25 seconds. 22 | 23 | Talon provides both global and local coordinate systems. Global 24 | coordinates are represented as 64bit integers. Local coordinates are 25 | represented as 16bit integers with configurable origin. 26 | 27 | Talon PPS functions by storing latest position measurement results in 28 | internal memory array. Interrupts GET_LOCAL_COORDINATES and 29 | STORE_GLOBAL_COORDINATES can be used to access the data. 30 | 31 | Interrupt behavior: 32 | When a HWI is received by the PPS, it reads the A register and does one 33 | of the following actions: 34 | 35 | 0: CONFIGURE_LOCAL_ORIGIN 36 | Reads Global Coordinate Array pointed by register B from ram and uses 37 | it as the new origin for local coordinates. 38 | 39 | Halts the DCPU-16 for 12 cycles. 40 | 41 | Register C is set with the operation status: 42 | 0x0000 : Success 43 | 0xffff : Equipment malfunction 44 | 45 | 1: GET_LOCAL_COORDINATES 46 | Stores the latest measured position -relative to Local Origin, to 47 | DCPU-16 registers X, Y and Z. 48 | 49 | X: (UINT16) x-coordinate (unit 1km) 50 | Y: (UINT16) y-coordinate (unit 1km) 51 | Z: (UINT16) z-coordinate (unit 1km) 52 | 53 | Coordinates that are outside the UINT16 range are replaced with 54 | the closest presentable value (0x0000 or 0xffff) and operation status 55 | in register C is set to 0x0002. 56 | 57 | Register C is set with the operation status: 58 | 0x0000 : Success 59 | 0x0001 : Success, but reduced accuracy 60 | 0x0002 : Success, but out of range 61 | 0x8000 : Failure, no pulsar fix 62 | 0xffff : Failure, equipment malfunction 63 | 64 | 2: STORE_GLOBAL_COORDINATES 65 | Register B is used as the target address to write the latest measured 66 | position as Global Coordinate Array to DCPU ram. 67 | 68 | Halts the DCPU-16 for 12 cycles. 69 | 70 | Register C is set with the operation status: 71 | 0x0000 : Success 72 | 0x0001 : Success, but reduced accuracy 73 | 0x8000 : Failure, no pulsar fix 74 | 0xffff : Failure, equipment malfunction 75 | 76 | 4: CONFIGURE_INTERRUPTS 77 | Enables interrupts and sets the message to X if X is anything other 78 | than 0, disables interrupts if X is 0. When interrupts are enabled, 79 | the PPS will trigger an interrupt on the DCPU-16 whenever new position 80 | data is available in PPS's internal memory. 81 | 82 | Global Coordinate Array: 83 | word 0 - 3: UINT64 X-Coordinate 84 | word 4 - 7: UINT64 Y-Coordinate 85 | word 8 - 11: UINT64 Z-Coordinate 86 | 87 | Values are stored from MSB to LSB. 88 | -------------------------------------------------------------------------------- /Simple Outputs/Luxul-pi.md: -------------------------------------------------------------------------------- 1 | Luxul Photon Indicator 2 | ---- 3 | 4 | ``` 5 | 6 | ^ 7 | !!! 8 | !!!!! 9 | !!!!!!!!!!!!! 10 | !!!!!!! !!!!!!! 11 | !!!! ! !!!! 12 | ! !!! ! 13 | !!!!!!! 14 | !!!!!!! 15 | !!!!! 16 | !!! 17 | ! 18 | L U X U L 19 | 20 | ``` 21 | 22 | | Item | Value | Comment 23 | | ----------------: | ---------- | ---------------- 24 | | Vendor code | 0x010C337D | (LUXUL) 25 | | Device ID | 0x0003 | (PI) 26 | | Luxul Device type | 0x41F2 | LED, multi color, wired, indicator 27 | | Version | 0x002A | Version Code 28 | 29 | The Luxul Photon Indicator is a small command driven LED. It is ideal for physical interfaces and giving notification to users. It is capable of displaying 16 different colors. Commands are given through a KaiComm SSI compatible port. 30 | 31 | Commands 32 | ---- 33 | - **0x0000**: Query Device Info: Sends Vendor Code, Device ID, Device Type, and Version over SSI. 34 | - **0x0001**: Get status: Sends current color status in the standard pi word format. -Shown below- 35 | - **0x0002**: Set status: Sets color status in the standard pi word format. -Shown below- 36 | 37 | Standard pi word format 38 | ---- 39 | The second and third groups of bits are ignored if power ≠ 2. If the most significant bits are set higher than 2, the device assumes the off state. 40 | 41 | 42 | | Bit Significance | Most Significant | Second Most Significant | Second Least Significant | Least Significant | 43 | |------------------|----------------------|----------------------------------------------|-----------------------------------------------|----------------------------------------------------| 44 | | Range: | 0-2 | 0-F | 0-F | 0-F | 45 | | Holds | Power State | Blink On | Blink Off | Color | 46 | | | 0=off, 1=on, 2=blink | How many decaseconds to stay on during blink | How many decaseconds to stay off during blink | Hex representation of color (Same spec as LEM1802) | 47 | 48 | Examples 49 | ---- 50 | ` 0x0002 0x0FFF ` - 51 | Turn pi off 52 | 53 | ` 0x0002 0x2AAF ` - 54 | Blink white. One second on, one second off. 55 | 56 | ` 0x0002 0x1FF0 ` - 57 | Turn on. Set color to black. 58 | 59 | ` 0x0000 ` - pi responds ` 0x010C 0x337D 0x0003 0x41F2 0x002A ` 60 | 61 | 62 | A note from Luxul 63 | ---- 64 | Although this device is fully functional, it has been recalled. A faulty capacitor occasionally discharges and can lead to combustion. If you own a Luxul pi 2A, we advise you send it to the following address for a free replacement unit. 65 | > Sector: C-137 66 | 67 | > SHID: ZZ8-A1426 Berling Hall 68 | -------------------------------------------------------------------------------- /IO Data/KaiComm-RACM.md: -------------------------------------------------------------------------------- 1 | KaiComm Remote Activity Control Module 2 | ---- 3 | 4 | ``` 5 | | \ Kai 6 | >| \\ Communications 7 | >| \\\ 8 | >| /// 9 | >| // 10 | | / 11 | ``` 12 | 13 | | Item | Value | Comment 14 | | -------------: | ---------- | ---------------- 15 | | Vendor code | 0xA87C900E | (KaiComm) 16 | | Device type | 0x02 | (Communications) 17 | | Device Subtype | 0x05 | (Remote Control) 18 | | Device ID | 0x30 | 19 | | DCPU Device ID | 0xD0F090C0 | (KaiComm RACM) 20 | | Version | 0x0001 | 21 | 22 | The KaiComm RACM is a Remote Activity Control Module designed for satellites and other unattended DCPU-based systems. 23 | The device monitors the state of the system by means of a configurable watchdog timer. If the DCPU does not periodically reset the timer, or upon wireless recipt of a configurable PIN, the device enters safe mode. While in safe mode, a remote reset command will reboot the attached DCPU system. While in safe mode, upon recipt of a rescue program, the device will reset the DCPU and execute the program at address 0x0000. 24 | 25 | **Note** - Radiofrequency communication can be interfered with by physical obstructions, solar flares, and other radio transmissions. Datagrams received may have been truncated, partially replaced, or otherwise corrupted in transit. 26 | 27 | The integrated radio covers the band from 902 MHz to 927.6 MHz, which is divided into 256 channels of 100 KHz bandwidth. 28 | 29 | The default channel is 0x0000, or 902.0 MHz. 30 | 31 | The default safe mode PIN is: 0x1234 32 | 33 | The default watchdog timer value is: 0xffff 34 | 35 | Commands 36 | ---- 37 | 38 | On interrupt, register A holds a command that the RACM will perform: 39 | 40 | - **0x0000**: Query status: 41 | Sets Register A with watchdog timer value, in number of milliseconds until safe mode is activated. A value of 0 indicates that safe mode is currently active, and that the device is accepting reset and upload commands. 42 | Sets register B with safe mode PIN. 43 | - **0x0001**: Reset watchdog timer value: 44 | Register B gives the number of milliseconds until the watchdog timer should trigger and put the device into safe mode. If the device is currently in safe mode, resetting the watchdog timer will leave safe mode. 45 | - **0x0002**: Configure PIN: 46 | Register B selects new safe mode PIN. 47 | - **0x0003**: Configure radio: 48 | Register B holds the channel to tune to, from 0x0000 through 0x00FF. 49 | Register C will be set to 0 if the settings are accepted an applied, and 1 if the proposed settings are invalid. 50 | 51 | Remote Commands 52 | ---- 53 | 54 | The RACM accepts commands wirelessly from compatible wireless transmitters. All commands have the two-word KaiComm command header, 0xA87C, 0x900E. These commands are structured as follows: 55 | 56 | - **PIN Command**: 0xA87C, 0x900E, 0x0001, <1-word PIN> 57 | Submits a PIN code to the device. If the PIN code matches the configured safe mode PIN, the device will enter safe mode. 58 | - **Reset Command**: 0xA87C, 0x900E, 0x0002 59 | Reboots the attached DCPU system. If the device is in safe mode, the DCPU and all attached hardware will be reset to their default states, memory will be cleared, and the system boot process will proceed as normal. 60 | - **Upload Command**: 0xA87C, 0x900E, 0x0003, <128-word rescue program> 61 | Uploads a rescue program. If the device is in safe mode, the DCPU will be stopped, the uploaded 128-word program will be coppied to memory address 0 (leaving all other memory contents unchanged), the DCPU registers and all attached hardware will be reset to their default configurations, and execution will resume from address 0. **Note** - Wireless communication can be unreliable! There is some probability that the rescue program will be truncated or contain errors. KaiComm is not responsible for any damage that may result from the use of this feature. 62 | 63 | ---- 64 | 65 | -------------------------------------------------------------------------------- /Navigation/radar.txt: -------------------------------------------------------------------------------- 1 | 2 | O TTT EEE C 3 | O O T E C C 4 | O O T E C 5 | O O T EE C 6 | O O T E C 7 | O O T E C C 8 | O T EEE C - LEAVE FAR FIELD TO US! 9 | 10 | DCPU-16 Hardware Info: 11 | Name: FF32-EM Radar 12 | Version: 0x6673 13 | ID: 0x3846bc64 14 | Manufacturer: 0xb8badde8 (Otec) 15 | 16 | Description: 17 | FF32-EM Radar is a far field electromagnetic pulse generator-detector. FF32-EM 18 | system can detect the presence, distance and signature of spacecraft, ships, and 19 | other objects, by sending out pulses of high-frequency electromagnetic waves 20 | that are reflected off the object back to the source. 21 | 22 | Otec's FF32-EM can operate at 32km range and is capable of spherical radar 23 | sweep in only 7200ms. FF32-EM holds internal target listed that is refreshed 24 | during radar sweep and can be queried with Otec's advanced interrupt API specified 25 | below. 26 | 27 | Interrupt behavior: 28 | 29 | When a HWI is received by the Radar, it reads the A register and 30 | does one of the following actions: 31 | 32 | 0: GET_STATUS 33 | Register B is set to hold the number of targets left in FF32-EM internal 34 | memory. This target list is repopulated every time that radar sweep completes 35 | and target is removed from the list when POP_TARGET returns it. 36 | 37 | Register C is set FF32-EM general status 38 | 0x0000 Idle 39 | 0x0001 Sweep in progress 40 | 0xffff Equipment malfunction 41 | 42 | 1: START_RADAR_SWEEP 43 | Starts the radar sweep. Sweep will take exactly 7200ms to complete. At sweep startup 44 | the internal target list is cleared and new list is build during the sweep. 45 | 46 | Register C is set to return status code for START_RADAR_SWEEP operation. 47 | 0x0000 Sweep initiated succesfully 48 | 0x8000 Sweep already in progress 49 | 0xffff Equipment malfunction 50 | 51 | 2: POP_TARGET 52 | Pop target provides information about a target detected during previous radar sweep. 53 | Targets are returned in the distance order - closest first. 54 | 55 | GET_STATUS returns (in register B) how many times POP_TARGET can be called before all 56 | detected targets are processed. 57 | 58 | Information 59 | A: Target signature 60 | 16 bit signature that is typically unique to a target, but uniqueness is not quaranteed 61 | B: Target data vector 00000000 00wwwwtt 62 | bits tt: Target type 63 | 00: Radar echo is untypical 64 | 10: Radar echo is typical for manmade object 65 | 01: Radar echo is typical for natural object 66 | 11: NA 67 | bit wwww: Target mass 68 | 0000: 0 kg - 10e2 kg 69 | 0001: 10e2 kg - 10e3 kg 70 | 0010: 10e3 kg - 10e4 kg 71 | 0011: 10e4 kg - 10e5 kg 72 | 0100: 10e5 kg - 10e6 kg 73 | 0101: 10e6 kg - 10e7 kg 74 | 0110: 10e7 kg - 10e8 kg 75 | 0111: 10e8 kg - 10e9 kg 76 | 1000: 10e9 kg - 10e10 kg 77 | 1001: 10e10 kg - 10e11 kg 78 | 1010: 10e11 kg - 10e15 kg 79 | 1011: 10e15 kg - 10e20 kg 80 | 1100: 10e20 kg - 10e25 kg 81 | 1101: 10e25 kg - 10e35 kg 82 | 1110: 10e35 kg - 10e40 kg 83 | 1111: 10e40 kg - 84 | 85 | X: Target X-coordinate relative to radar (m) 86 | Y: target Y-coordinate relative to radar (m) 87 | Z: target Z-coordinate relative to radar (m) 88 | 89 | Register C is set to status code for POP_TARGET operation. 90 | 0x0000 Success 91 | 0x0001 No target available 92 | 0x8000 Sweep in progress 93 | 0xffff Equipment malfunction 94 | 95 | Halts DCPU for 6 cycles. 96 | 97 | 3: CONFIGURE_INTERRUPTS 98 | Register B contains message for Interrupt on sweep completed, 0 means disable interrupt. 99 | -------------------------------------------------------------------------------- /IO Data/KaiComm-HIC.md: -------------------------------------------------------------------------------- 1 | KaiComm Hardware Interface Card 2 | ---- 3 | 4 | ``` 5 | | \ Kai 6 | >| \\ Communications 7 | >| \\\ 8 | >| /// 9 | >| // 10 | | / 11 | ``` 12 | 13 | | Item | Value | Comment 14 | | -------------: | ---------- | ---------------- 15 | | Vendor code | 0xA87C900E | (KaiComm) 16 | | DCPU Device ID | 0xE0239088 | (KaiComm HIC) 17 | | Version | 0x0442 | 8 Port card 18 | | Version | 0x0444 | 16 Port card 19 | | Version | 0x0448 | 32 Port card 20 | 21 | The KaiComm HIC (model 44) is a bi-directional multifunction data interface, with multiple ports per card. 22 | An integrated out-of-band (OOB) signalling function provides additional information about connected devices. 23 | 24 | Transmissions in either direction are independent of each other and can operate asynchronously of one another. 25 | Each port contains a 2 word receive buffer, allowing it to receive on multiple ports simultaneously. 26 | The HIC device contains a single transmitter and 2 word buffer used by all ports, the HIC can only send on a single port at a time. 27 | 28 | The low bits of the version can be used to determine the maximum number of ports available on the card. 29 | 30 | Commands 31 | ---- 32 | 33 | On interrupt, register A holds a command that the HIC will perform: 34 | 35 | - **0x0000**: Query status 36 | - On interrupt, register C should hold a port number to get status about. 37 | - Only the lowest 4 bits can be different per port, as the HIC has a single transmitter. 38 | 39 | - Sets Register A with info status, bits will be set or cleared as follows: 40 | - Bit 0 - Port is busy receiving (1), or idle/not receiving (0) 41 | - Bit 1 - Port is not connected (1), or connected (0) 42 | - Bit 2 - Data available on port (1), or not (0) 43 | - Bit 3 - Port number is invalid (1), or valid (0) 44 | - Bit 4 - Transmit buffer is free (1), or full (0) 45 | - Bit 5 - Transmitter is idle/empty (1), or sending (0) 46 | - Bit 6 - At least one port has data available (1), or none (0) 47 | - Bit 7-13 are reserved and always set to 0 48 | - Bit 14 - Receive interrupts are: enabled (1), disabled (0) 49 | - Bit 15 - Transmit complete interrupts are: enabled (1), disabled (0) 50 | - Sets Register C to lowest port which has data available (or 0xFFFF if no data is available) 51 | 52 | - **0x0001**: Receive data 53 | - On interrupt, register C should hold the port number to receive from. 54 | - Register B will be set to the data received, or 0 on error. 55 | - Register C is set with the error status, receive error status is cleared when read. 56 | 57 | Receive Error status codes: 58 | - 0x0000 - Success, No error 59 | - 0x0001 - Success, Receive buffer overflowed (B is still set with buffer data) 60 | - 0x0002 - Fail, Receive error 61 | - 0x0003 - Fail, No data available 62 | 63 | - **0x0002**: Transmit data 64 | - On interrupt, Register B should contain 16 bit value to send, register C should be set to the port number to send on. 65 | - Register C will be set with a transmit Error status code: 66 | - 0x0000 - No error 67 | - 0x0001 - Port is busy (data will be queued) 68 | - 0x0002 - Transmit buffer overflow (data will not be sent) 69 | - 0x0003 - Port is not connected (data will not be sent) 70 | - 0x0004 - The HIC is busy sending on another port (data will not be sent) 71 | 72 | - **0x0003**: Configure interrupts: 73 | - Register B contains message for Interrupt on Receive. 74 | - Register C contains message for Interrupt on Transmit. 75 | - A message value of 0 means disable interrupt. 76 | 77 | - **0x0004**: Load port name 78 | - On interrupt, register B should be set to the starting memory address to populate. 79 | - Register C should be set to the port number to get the name of. 80 | 81 | The memory starting at the address held in B is filled with the 8 words containing name of the port. In the case of shorter names, the additional words will be 0. A port name may not exceed 8 words. 82 | 83 | Register C will be set to the error status: 84 | - 0x0000 - No error 85 | - 0x0001 - Port number out of bounds - The port number selected is too high for number of built-in ports 86 | - 0x0002 - Invalid memory address - The starting address + 8 exceeds 0xFFFF 87 | 88 | ---- 89 | 90 | 2014-2016 Meisaka Yukara (CC-BY-SA 4.0) 91 | 92 | -------------------------------------------------------------------------------- /Displays/LEM1802.txt: -------------------------------------------------------------------------------- 1 | NE_LEM1802 2 | 3 | \ | ___ 4 | |\ \| ___ 5 | | \ 6 | 7 | NYA ELEKTRISKA 8 | innovation information 9 | 10 | 11 | 12 | 13 | DCPU-16 Hardware Info: 14 | Name: LEM1802 - Low Energy Monitor 15 | ID: 0x7349f615 (Older models), version: 0x1802 16 | ID: 0x734df615 (Newer models), version: 0x1802 17 | Manufacturer: 0x1c6c8b36 (NYA_ELEKTRISKA) 18 | 19 | 20 | Description: 21 | The LEM1802 is a 128x96 pixel color display compatible with the DCPU-16. 22 | The display is made up of 32x12 16 bit cells. Each cell displays one 23 | monochrome 4x8 pixel character out of 128 available. Each cell has its own 24 | foreground and background color out of a palette of 16 colors. 25 | 26 | The LEM1802 is fully backwards compatible with LEM1801 (0x7349f615/0x1801), 27 | and adds support for custom palettes and fixes the double buffer color 28 | bleed bug. 29 | 30 | 31 | Interrupt behavior: 32 | When a HWI is received by the LEM1802, it reads the A register and does one 33 | of the following actions: 34 | 35 | 0: MEM_MAP_SCREEN 36 | Reads the B register, and maps the video ram to DCPU-16 ram starting 37 | at address B. See below for a description of video ram. 38 | If B is 0, the screen is disconnected. 39 | 1: MEM_MAP_FONT 40 | Reads the B register, and maps the font ram to DCPU-16 ram starting 41 | at address B. See below for a description of font ram. 42 | If B is 0, the default font is used instead. 43 | 2: MEM_MAP_PALETTE 44 | Reads the B register, and maps the palette ram to DCPU-16 ram starting 45 | at address B. See below for a description of palette ram. 46 | If B is 0, the default palette is used instead. 47 | 3: SET_BORDER_COLOR 48 | Reads the B register, and sets the border color to palette index B&0xF 49 | 4: MEM_DUMP_FONT 50 | Reads the B register, and writes the default font data to DCPU-16 ram 51 | starting at address B. 52 | Halts the DCPU-16 for 256 cycles 53 | 5: MEM_DUMP_PALETTE 54 | Reads the B register, and writes the default palette data to DCPU-16 55 | ram starting at address B. 56 | Halts the DCPU-16 for 16 cycles 57 | 58 | Video ram: 59 | The LEM1802 has no internal video ram, but rather relies on being assigned 60 | an area of the DCPU-16 ram. The size of this area is 386 words, and is 61 | made up of 32x12 cells of the following bit format (in LSB-0): 62 | ffffbbbbBccccccc 63 | The lowest 7 bits (ccccccc) select define character to display. 64 | ffff and bbbb select which foreground and background color to use. 65 | If B (bit 7) is set the character color will blink slowly. 66 | 67 | 68 | Font ram: 69 | The LEM1802 has a default built in font. If the user chooses, they may 70 | supply their own font by mapping a 256 word memory region with two words 71 | per character in the 128 character font. 72 | By setting bits in these words, different characters and graphics can be 73 | achieved. For example, the character F looks like this: 74 | word0 = 1111111100001001 75 | word1 = 0000100100000000 76 | Or, split into octets: 77 | word0 = 11111111 / 78 | 00001001 79 | word1 = 00001001 / 80 | 00000000 81 | 82 | 83 | Palette ram: 84 | The LEM1802 has a default built in palette. If the user chooses, they may 85 | supply their own palette by mapping a 16 word memory region with one word 86 | per palette entry in the 16 color palette. 87 | Each color entry has the following bit format (in LSB-0): 88 | 0000rrrrggggbbbb 89 | Where r, g, b are the red, green and blue channels. A higher value means a 90 | lighter color. 91 | 92 | 93 | A message from Ola: 94 | Hello! 95 | 96 | It is fun to see that so many people use our products. When I was a small 97 | boy, my dad used to tell me "Ola, take care of those who understand less 98 | than you. Lack of knowledge is dangerous, but too much is worse". 99 | Here at Nya Elektriska have we always tried to improve mankind by showing 100 | them the tools required to improve and reach their true potential. 101 | Together, you will wake up in time. 102 | 103 | - Ola Kristian Carlsson 104 | -------------------------------------------------------------------------------- /IO Data/KaiComm-RCI.md: -------------------------------------------------------------------------------- 1 | KaiComm Radiofrequency Communication Interface 2 | ---- 3 | 4 | ``` 5 | | \ Kai 6 | >| \\ Communications 7 | >| \\\ 8 | >| /// 9 | >| // 10 | | / 11 | ``` 12 | 13 | | Item | Value | Comment 14 | | -------------: | ---------- | ---------------- 15 | | Vendor code | 0xA87C900E | (KaiComm) 16 | | DCPU Device ID | 0xD00590A5 | (KaiComm RCI) 17 | | Version | 0x0010 | 18 | 19 | The KaiComm RCI is a half-duplex datagram-based radiofrequency communications device. 20 | Datagrams of up to 256 words can be transmitted, at a rate of 3,125 bits per second. This is approximately 195 words per second; the longest possible datagram takes approximately 1.31 seconds to transmit. 21 | Datagrams are framed and length-prefixed by the hardware. 22 | 23 | **Note** - Radiofrequency communication can be interfered with by physical obstructions, solar flares, and other radio transmissions. Datagrams received may have been truncated, partially replaced, or otherwise corrupted in transit. 24 | 25 | The integrated radio covers the band from 902 MHz to 927.6 MHz, which is divided into 256 channels of 100 KHz bandwidth. The radio also supports 8 transmit power levels. 26 | 27 | The default channel is 0x0000, or 902.0 MHz, and the default transmit power level is 7. 28 | 29 | All datagrams are broadcast to all stations in range that are tuned to the same channel. 30 | 31 | The RCI can buffer a single incoming datagram. If a new datagram is received while a datagram is currently in the buffer, the new datagram is discarded. 32 | 33 | The RCI can buffer a single outgoing datagram. Any attempts to transmit another datagram while the buffered datagram is being transmitted will fail. 34 | 35 | The RCI cannot transmit and receive simultaneously. If a datagram arrives while a datagram is being transmitted, the arriving datagram will be lost. If a datagram is transmitted while a datagram is being received, the datagram being received will be discarded. Moreover, it is likely that the two datagrams will overlap and that neither will be received by any station. 36 | 37 | Commands 38 | ---- 39 | 40 | On interrupt, register A holds a command that the RCI will perform: 41 | 42 | - **0x0000**: Query Status Datagram: 43 | - Register A will be set to the current channel, from 0x0000 to 0x00FF. 44 | - Register B will be set to the current transmit power level, from 0x0000 to 0x0007. 45 | - Register C will be set to transmit/receive status 46 | The lower 3 bits of status are interdependant as follows: 47 | - XX0 receive buffer is empty. 48 | - XX1 receive buffer has a datagram. 49 | - 00X radio is idle. 50 | - 01X radio detected a receive carrier or is receiving. 51 | - 10X radio is transmitting. 52 | - 11X radio detected a receive carrier collision. 53 | 54 | - The RCI device can also return these error codes in C instead: 55 | - 0xffe0 if the RCI device has detected an antenna failure - the radiofrequency antenna may require service. 56 | - 0xfff0 if the RCI device has detected an internal hardware failure - the RCI may require service. 57 | 58 | - **0x0001**: Receive Datagram: 59 | Register B gives the address of a 256-word buffer which will be populated with the received datagram. 60 | Register B will be set to the length of the datagram placed in the receive buffer, or 0 if no buffered datagram was available. 61 | Register C will be set with a status: 62 | - 0 if a datagram was successfully retrieved from the receive buffer. 63 | - 1 if no buffered datagram was available. 64 | - 2 if no buffered datagram was available and last receive attempt was corrupt and discarded. 65 | 66 | - **0x0002**: Send Datagram: 67 | Register B holds the address of a buffer containing the datagram to send. 68 | Register C holds the length of the datagram to transmit (up to 256 words). 69 | Register C will be set to 0 if the datagram is successfully queued for transmission, or set to 1 if there is already a datagram being transmitted. 70 | 71 | - **0x0003**: Configure radio: 72 | Register B holds the channel to tune to, from 0x0000 through 0x00FF. 73 | Register C holds the transmit power level to use, from 0x0000 through 0x0007. 74 | Register C will be set to 0 if the settings are accepted an applied, and 1 if the proposed settings are invalid. 75 | 76 | - **0x0004**: Configure interrupts: 77 | Register B contains the interrupt message to send when a datagram is received, or 0x0000 to disable receive interrupts. 78 | Register C contains the interrupt message to send when a datagram transmission completes, or 0x0000 to disable transmit interrupts. 79 | 80 | -------------------------------------------------------------------------------- /Storage/m525hd.md: -------------------------------------------------------------------------------- 1 | Mackapar Media m525hd 2 | ---- 3 | 4 | ``` 5 | .!. 6 | !!!!!. 7 | . '!!!!!. 8 | .!!!. '!!!!!. 9 | .!!!!!!!. '!!!!!. 10 | .!!!!!!!!!' .!!!!!!!. 11 | '!!!!!!!' .!!!!!!!!!' 12 | '!!!!!. '!!!!!!!' 13 | '!!!!!. '!!!' 14 | '!!!!!. ' 15 | '!!!!! 16 | '!' 17 | 18 | 19 | M A C K A P A R M E D I A 20 | ``` 21 | 22 | | Item | Value | Comment 23 | | -------------: | ---------- | ---------------- 24 | | Vendor code | 0x1eb37e91 | Mackapar Media 25 | | Device ID | 0x4ac5525d | 5.25" Hard Disk Drive 26 | | Device type | 0x4ac5 | 16 bit fixed Disk Drive 27 | | Version | 0x0001 | Dictates Size (5MB, 10MB) 28 | 29 | Device Description 30 | 31 | Mackapar Medias first foray into fixed storage resulted in the Mackapar Media m525hd. 32 | When formatted in 16 bit mode the m525hd has a capacity of 5MB. Data is saved on 4 33 | surfaces each containing 64 20-sector tracks. Each sector contains a total of 34 | 512 words, resulting in a total of 5120 sectors. 35 | Reads and writes are performed asynchronously, at a read/write speed of 327.7kw/s 36 | and a Track-to-Track seek time of around 3ms. The average seek time is 80ms with a 37 | maximum of 200ms (200 cycles). 38 | 39 | Interrupt Commands 40 | ---- 41 | 42 | - **0x0000**: POLL_DEVICE 43 | - Sets B to the current state (see below) and C to the latest error since the 44 | last device poll 45 | - **0x0001**: SET_INTERRUPT 46 | - Enables interrupts and sets the message to X if X is anything other than 0, 47 | disables interrupts if X is 0. When interrupts are enabled the m525hd will 48 | trigger an interrupt on the DCPU-16 whenever the state or error message 49 | changes 50 | - **0x0002**: READ_SECTOR 51 | - Reads sector X to DCPU ram starting at Y. Sets B to 1 if reading is possible 52 | and has been started, anything else if reading fails. Reading is only possible 53 | if the state is STATE_READY or STATE_READY_WP. Protects against partial reads. 54 | - **0x0003**: WRITE_SECTOR 55 | - Writes sector X from DCPU ram starting at Y. Sets B to 1 if writing is possible 56 | and has been started, anything else if writing fails. Writing is only possible 57 | if the state is STATE_READY. Protects against partial writes. 58 | - **0x0004**: SPIN_DOWN 59 | - Parks the heads and spins down the drive to conserve power. 60 | - **0x0005**: SPIN_UP 61 | - Spins up the drive to make ready for reading/writing. The drive will need a 15 62 | second interval to reach the proper speed. 63 | 64 | State Codes 65 | ---- 66 | | Value | Code | Description 67 | | --------: | -------------- | ------------------ 68 | | 0x0001 | STATE_READY | The drive is ready to accept commands. 69 | | 0x0002 | STATE_READY_WP | The drive is ready but read only. 70 | | 0x0003 | STATE_BUSY | The drive is busy either reading, writing or seeking. 71 | | 0x0004 | STATE_PARKED | The drive has been spun down and needs to be restarted. 72 | | 0x0005 | STATE_PARKED_WP| The drive has been spun down and is write protected. 73 | | 0x0006 | STATE_INIT | The drive is still spinning up. 74 | | 0x0007 | STATE_INIT_WP | The drive is still spinning up and is write protected. 75 | Error Codes 76 | ---- 77 | | Value | Code | Description 78 | | --------: | ---------------- | ------------------ 79 | | 0x0000 | ERROR_NONE | There has been no error since the last poll. 80 | | 0x0001 | ERROR_BUSY | The drive is busy performing an action. 81 | | 0x0002 | ERROR_BAD_ADDRESS | Attempted to read from a sector this drive doesn't contain 82 | | 0x0003 | ERROR_PROTECTED | Tried to write to read only drive. 83 | | 0x0004 | ERROR_PARKED | Attempted to read/write from a spun down drive. 84 | | 0x0005 | ERROR_BAD_SECTOR | The requested sector is broken, the data on it is lost. 85 | | 0xFFFF | ERROR_BROKEN | Theres been some major software or hardware problem. 86 | 87 | Behaviours 88 | ---- 89 | When first powered on (or after being spun down) the m525hd requires a 15 second interval in which to spin up. 90 | Attempting to access the drive during this time should return a state code of STATE_INIT(_WP) and an Error Code of 91 | ERROR_BUSY. At the end of these 15 seconds the drive should report STATE_READY(_WP). 92 | 93 | Maximum seek time is observed when seeking from track 0,1,2,3 (rest) to track 252,253,254,255 (center of drive). 94 | Minimum seek time is observed when seeking between adjacent tracks. 95 | 96 | -------------------------------------------------------------------------------- /Displays/IMVA.md: -------------------------------------------------------------------------------- 1 | Interlaced Monochrome Videographic Adaptor 2 | ---- 3 | 4 | ``` 5 | ____ _____________ _____ 6 | / | / / ____/ _____ / 7 | / |/ / /________ / 8 | / /| /|/ __/_ __/ 9 | /___/ |____/ /__/|__/__/ ___ 10 | /___/ |___/ /______/__/ ___ / 11 | /___/__________|___|/__/__ / 12 | /_________________/_______/ 13 | 14 | ``` 15 | 16 | | Item | Value | Comment 17 | | -------------: | ---------- | ---------------- 18 | | Vendor code | 0x59EA5742 | Meisaka Engineering and Integration 19 | | Device ID | 0x75F6A113 | IMVA 20 | | Device type | 0x75F6 | Memory mapped monochrome display 21 | | Version | 0x0538 | 22 | 23 | The Interlaced Monochromatic Videographic Adaptor (the device), offers a unique and powerful ocean of monochrome pixels for all of your graphics needs. 24 | At 320 by 200 pixels, the device can accommodate a wide array of graphical functions and display more information at once than ever thought possible. Yes, it only offers two colors, but you can customize them! 25 | 26 | The device also includes a mini-compositor overlay to display a simple prompt or achieve other effects. 27 | 28 | Interrupt Functionality 29 | ---- 30 | When the device is interrupted, the A register will be interpreted as a command 31 | 32 | - **0x0000**: Activate Display 33 | 34 | Register B should be set to the base memory address for the main display area. 35 | - The display requires 4000 words of memory. 36 | - Setting the base to zero will disable output and put the connected display in standby. 37 | 38 | - **0x0001**: Set overlay 39 | 40 | - Register B should be set to the base memory address for the overlay. 41 | - Register C should be set to the word offset for the overlay. 42 | - Setting B to zero disables overlay 43 | 44 | - **0x0002**: Set Effects 45 | 46 | - Register B adjusts display colors: 47 | - bits 0-3 are the red level, 4-7 are the green level, 8-11 are the blue level. 48 | - bits 12-15 adjusts contrast between on/off pixels (0 is most contrasting, 0xF is least contrasting). 49 | 50 | - Register C adjusts overlay effect 51 | - bits 0-3 adjust blink rate, in 10ths of a second. (zero means no blink) 52 | - bits 4-5 select the overlay pixel combine mode: 53 | - 00: OR mode - default 54 | - 01: XOR mode 55 | - 10: AND mode 56 | - 11: COPY mode (only overlay pixels are used) 57 | 58 | Raster Function 59 | ---- 60 | 61 | The device uses each word for 2 lines and 8 pixel columns, while scanning left to right and top down. 62 | This results in 40 columns across the display 8 pixels wide each. 63 | Each word is divided into 8 bits for each line, the lower 8 bits are used for odd lines, and the higher 8 bits for even lines. 64 | Bits are read high to low, left to right, meaning bit 7 of word 0, is at line 1 column 1. 65 | 66 | *Layout Example* 67 | 68 | ``` 69 | ---------------------------------------------------- 70 | | Word 0 bits | Word 1 bits | 71 | Line 1 | 7| 6| 5| 4| 3| 2| 1| 0| 7| 6| 5| 4| 3| 2| 1| 0| etc. 72 | Line 2 |15|14|13|12|11|10| 9| 8|15|14|13|12|11|10| 9| 8| 73 | |-----------------------|-----------------------|--- 74 | | Word 40 bits | Word 41 bits | 75 | Line 3 | 7| 6| 5| 4| 3| 2| 1| 0| 7| 6| 5| 4| 3| 2| 1| 0| etc. 76 | Line 4 |15|14|13|12|11|10| 9| 8|15|14|13|12|11|10| 9| 8| 77 | 78 | ``` 79 | 80 | Overlay Function 81 | ---- 82 | 83 | The overlay (if enabled) is a small segment rasterized similar to the main display, only it is 16x16 pixels, and additionally combined with the main display. 84 | The overlay is set with the *Set Overlay* function, the offset passed with this interrupt function determines where the upper left of the overlay begins. 85 | The remaining overlay addresses are computed by hardware, which treats the overlay like a 16x16 block of screen that is displayed over the main screen content. 86 | 87 | - Note that the overlay only effects what is displayed, not the backing memory. 88 | - If the overlay is set to the right most column, the 8 bits that would be at column 41 are not displayed. 89 | - Likewise, Lines of the overlay that would go past the bottom of the display are not visible either. 90 | - Setting the overlay offset past the visible display area hides it. 91 | - The effects setting controls if the overlay blinks, and how it is combined with the main display. 92 | - For blink effect: on and off times are equal. 93 | - The offset function of the overlay, allows it to only be placed on odd lines. 94 | 95 | 96 | Revision Notes 97 | ---- 98 | 99 | Version 5.25: Made the heat sink bigger - device no longer catches fire. 100 | Version 5.10: Fix overlay corruption is some cases... 101 | Version 5.00: Added 16x16 overlay. 102 | Version 3.12: Customizable color, number 1 most demanded feature added. 103 | Version 2.56: Added timing control for blink function. 104 | 105 | -------------------------------------------------------------------------------- /Storage/m35fd.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .!. 5 | !!!!!. 6 | . '!!!!!. 7 | .!!!. '!!!!!. 8 | .!!!!!!!. '!!!!!. 9 | .!!!!!!!!!' .!!!!!!!. 10 | '!!!!!!!' .!!!!!!!!!' 11 | '!!!!!. '!!!!!!!' 12 | '!!!!!. '!!!' 13 | '!!!!!. ' 14 | '!!!!! 15 | '!' 16 | 17 | 18 | M A C K A P A R M E D I A 19 | 20 | 21 | 22 | 23 | 24 | 25 | .---------------------. 26 | ----! DCPU-16 INFORMATION !----------------------------------------------------- 27 | '---------------------' 28 | 29 | Name: Mackapar 3.5" Floppy Drive (M35FD) 30 | ID: 0x4fd524c5, version: 0x000b 31 | Manufacturer: 0x1eb37e91 (MACKAPAR) 32 | 33 | 34 | 35 | .-------------. 36 | ----! DESCRIPTION !------------------------------------------------------------- 37 | '-------------' 38 | 39 | The Mackapar 3.5" Floppy Drive is compatible with all standard 3.5" floppy disks. 40 | 3.5" floppies are available in multiple various sizes, ranging from 40 kw to 41 | 224 kw. The M35FD is asynchronous in both read and write modes, spins at 300 42 | RPM, and has a raw read/write speed of 17.5kw/s with high density disks, and 43 | 10kw/s with lower density disks. Track to track seek times range from 38~52ms, 44 | and full stroke seek is no more then 550ms. 45 | 46 | 47 | .-----------------. 48 | ----! DISK GEOMETRIES !--------------------------------------------------------- 49 | '-----------------' 50 | 51 | Low Density Single Sided - 40kw/80kb disk 52 | 53 | 80 sectors of 512 words each 54 | 1 side at 20 tracks of 4 sectors each 55 | 56 | Low Density Double Sided - 80kw/160kb disk 57 | 58 | 160 sectors of 512 words each 59 | 2 sides at 20 tracks of 4 sectors each 60 | 61 | High Density Single Sided - 112kw/224kb disk 62 | 63 | 224 sectors of 512 words each 64 | 1 side at 32 tracks of 7 sectors each 65 | 66 | High Density Double Sided - 224kw/448kb disk 67 | 68 | 448 sectors of 512 words each 69 | 2 sides at 32 tracks of 7 sectors each 70 | 71 | 72 | .--------------------. 73 | ----! INTERRUPT BEHAVIOR !------------------------------------------------------ 74 | '--------------------' 75 | 76 | A, B, C, X, Y, Z, I, J below refer to the registers on the DCPU 77 | 78 | A: Behavior: 79 | 80 | 0 Poll device. Sets B to the current state (see below) and C to the last error 81 | since the last device poll. 82 | 83 | 1 Set interrupt. Enables interrupts and sets the message to X if X is anything 84 | other than 0, disables interrupts if X is 0. When interrupts are enabled, 85 | the M35FD will trigger an interrupt on the DCPU-16 whenever the state or 86 | error message changes. 87 | 88 | 2 Read sector. Reads sector X to DCPU ram starting at Y. 89 | Sets B to 1 if reading is possible and has been started, anything else if it 90 | fails. Reading is only possible if the state is STATE_READY or 91 | STATE_READY_WP. 92 | Protects against partial reads. Accessing beyond the valid sector count of 93 | the current floppy may cause damage to the disk, the drive, or both. 94 | 95 | 3 Write sector. Writes sector X from DCPU ram starting at Y. 96 | Sets B to 1 if writing is possible and has been started, anything else if it 97 | fails. Writing is only possible if the state is STATE_READY. 98 | Protects against partial writes. Accessing beyond the valid sector count of 99 | the current floppy may cause damage to the disk, the drive, or both. 100 | 101 | 4 Disk Geometry. Sets X to number of sides, Y to number of tracks, and Z to 102 | number of sectors. If no disk is present, values are undefined. 103 | 104 | .-------------. 105 | ----! STATE CODES !------------------------------------------------------------- 106 | '-------------' 107 | 108 | 0x0000 STATE_NO_MEDIA There's no floppy in the drive. 109 | 0x0001 STATE_READY The drive is ready to accept commands. 110 | 0x0002 STATE_READY_WP Same as ready, except the floppy is write protected. 111 | 0x0003 STATE_BUSY The drive is busy either reading or writing a sector. 112 | 113 | 114 | 115 | .-------------. 116 | ----! ERROR CODES !------------------------------------------------------------- 117 | '-------------' 118 | 119 | 0x0000 ERROR_NONE There's been no error since the last poll. 120 | 0x0001 ERROR_BUSY Drive is busy performing an action 121 | 0x0002 ERROR_NO_MEDIA Attempted to read or write with no floppy inserted. 122 | 0x0003 ERROR_PROTECTED Attempted to write to write protected floppy. 123 | 0x0004 ERROR_EJECT The floppy was removed while reading or writing. 124 | 0x0005 ERROR_BAD_SECTOR The requested sector is broken, the data on it is lost. 125 | 0xffff ERROR_BROKEN There's been some major software or hardware problem, 126 | try turning off and turning on the device again. 127 | 128 | 129 | 130 | COPYRIGHT 1987 MACKAPAR MEDIA ALL RIGHTS RESERVED DO NOT DISTRIBUTE 131 | -------------------------------------------------------------------------------- /Displays/PIXIE.txt: -------------------------------------------------------------------------------- 1 | PIXIE 2 | 3 | 4 | DCPU-16 Hardware Info: 5 | Name: PIXIE - Compatible Video Generator 6 | ID: 0x774df615, version: 0x1802 7 | Manufacturer: 0x83610EC5 (Agnus Micro Devices) 8 | 9 | 10 | Description: 11 | The PIXIE is a 128x96 pixel color display fully compatible with the 12 | famous Nya Elektriska's LEM1802. PIXIE is a perfect way to upgrade 13 | your DCPU and start enjoying the latest games and graphics. 14 | 15 | PIXIE has the same interrupt behavior as LEM1802, but it also supports 16 | a 128x96 resolution graphics mode with 2-16 colors. Graphics mode is 17 | enabled with a new interrupt that specifies the number of colors. 18 | If using less then 16 color palette, the lowest colors in LEM1802 text 19 | mode palette are used. 20 | 21 | 22 | Interrupt behavior: 23 | When a HWI is received by the PIXIE, it reads the A register and does one 24 | of the following actions: 25 | 26 | Interrupts 0 to 5 are compatible with LEM1802. 27 | 28 | 0: MEM_MAP_SCREEN 29 | Reads the B register, and maps the video ram to DCPU-16 ram starting 30 | at address B. See below for a description of video ram. 31 | If B is 0, the screen is disconnected. 32 | 1: MEM_MAP_FONT 33 | Reads the B register, and maps the font ram to DCPU-16 ram starting 34 | at address B. See below for a description of font ram. 35 | If B is 0, the default font is used instead. 36 | 2: MEM_MAP_PALETTE 37 | Reads the B register, and maps the palette ram to DCPU-16 ram starting 38 | at address B. See below for a description of palette ram. 39 | If B is 0, the default palette is used instead. 40 | 3: SET_BORDER_COLOR 41 | Reads the B register, and sets the border color to palette index B&0xF 42 | 4: MEM_DUMP_FONT 43 | Reads the B register, and writes the default font data to DCPU-16 ram 44 | starting at address B. 45 | Halts the DCPU-16 for 256 cycles 46 | 5: MEM_DUMP_PALETTE 47 | Reads the B register, and writes the default palette data to DCPU-16 48 | ram starting at address B. 49 | Halts the DCPU-16 for 16 cycles 50 | 51 | 16: SET_VIDEO_MODE 52 | Reads the B register, and changes to specified video mode: 53 | 54 | 0: Text mode (LEM1802 standard) 55 | 1: Graphics mode, 2 colors 56 | 2: Graphics mode, 4 colors 57 | 3: Graphics mode, 8 colors 58 | 4: Graphics mode, 16 colors 59 | 60 | Graphics mode will use the same video ram starting address as text mode, 61 | but video ram size and layout are different. Graphics mode will also use 62 | the same palette as text mode, but only the colors 0-n (depending on the 63 | color depth) are used. Font ram is not relevant in graphics mode. 64 | 65 | 66 | Graphics mode video ram: 67 | a 128 by 96 screen is organized in 1-4 bitplanes of 768 words each. 68 | Each bitplane consists of 96 rows of 8 words. Number of bitplanes 69 | depends on the number of colors. 2 color mode has only one bitplane, 70 | while 16 color mode has four bitplanes. 71 | 72 | memory total 73 | bitplane offset memory 74 | -------- ------ ------ 75 | 0 0 768 2, 4, 8 and 16 color modes 76 | 1 768 1536 4, 8 and 16 color modes 77 | 2 1536 2304 8 and 16 color modes 78 | 3 2304 3072 16 color mode 79 | 80 | Bitplane number is used as a bit position to refer the color palette. 81 | The bitplane 0 bit is the least significant bit in LEM palette. 82 | e.g. if bitplane 0 is clear, but bitplanes 1-3 are set, 83 | the palette color would be 0b1110 -> 0xE -> 14 84 | 85 | Graphics are stored to bitplane in a linear fashion; each word of data 86 | on a line is located at an address that is one greater than the word on 87 | its left. i.e. Each line is a "plus one" continuation of the previous 88 | line. 89 | 90 | Following table illustrates the graphics mode video ram if start address 91 | is set to 20 with MEM_MAP_SCREEN interrupt. 92 | _______________________________________ 93 | | | | | | | | | | 94 | | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 95 | |____|____|____|____|____|____|____|____| 96 | | | | | | | | | | 97 | | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 98 | |____|____|____|____|____|____|____|____| 99 | | | | | | | | | | 100 | | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 101 | |____|____|____|____|____|____|____|____| 102 | 92 more rows like these 103 | | | | | | | | | | 104 | | 780| 781| 782| 783| 784| 785| 786| 787| 105 | |____|____|____|____|____|____|____|____| 106 | 107 | The map represents a single bitplane (one bit of color) image at 108 | word addresses 20 through 787. Each of these addresses accesses 109 | one word (16 pixels) of a single bitplane. Image with 16 colors 110 | has four bitplanes like this. 111 | 112 | 113 | Hardware ID 114 | PIXIE hardware id is 0x774df615, while LEM1802 hardware id is 115 | 0x734df615. To guarantee full compatibility with all LEM1802 116 | software, PIXIE has a dip switch located in the control panel. 117 | 118 | Dip switch has two positions that can be used to change the 119 | PIXIE's hardware id: 120 | 121 | 0: 0x734df615 (LEM1802) 122 | 1: 0x774df615 (PIXIE) 123 | 124 | This setting changes only the hardware ID. Graphics mode is 125 | available in both positions. 126 | 127 | -------------------------------------------------------------------------------- /Simple Outputs/HSDP-1D.md: -------------------------------------------------------------------------------- 1 | ``` 2 | __ 3 | ____________ ____ 4 | _______________ _________ 5 | _________________ ______________ 6 | ___________________ __________________ __________________ 7 | _____________________ ________________________ ________________________ 8 | _______________________ ______________ _____ _______ __________ 9 | _________________________ ________________ __ ________________ ________ 10 | ___________________________ ____ _______ _______ ________ _______ 11 | ____________________ _ ___ ________ _____ ______ 12 | _________________ _________ _____ ______ 13 | ________________ _________ _____ ______ 14 | ________________ ___________ ____ ______ 15 | ________________ ______________ ____ ______ 16 | _________________ _________________ ___ _____ 17 | ____________________ ______________________ __ ____ 18 | __________________________________________________________ 19 | _______________________________________________________ 20 | __________________________________________________ 21 | ____________________________________________ 22 | ____________________________________ 23 | _______________________ 24 | 25 | ``` 26 | 27 | # HSDP-1D High Speed Data Printer 28 | 29 | | Item | Value | Comment | 30 | | :--- | :--- | :--- | 31 | | Vendor code | 0xf6976d00 | Chartronics, Inc. | 32 | | Device ID | 0xcff2a11d | HSDP-1D High Speed Data Printer | 33 | | Device Type | 0xcff2 | Generic, nonstandard output device | 34 | | Version | 0x1 | | 35 | 36 | ## Description 37 | 38 | The HSDP line is all about printing the data you need as fast as possible. 39 | 40 | The HSDP line offers you the best way to store your data, in terms of cost 41 | efficency. 42 | 43 | Paper, power and data is all you need to run a HSDP. Its clever design combining 44 | the speed of the line matrix and the ink-free design of a spark printer will 45 | really cut the cost of your radio survey by orders of magnitude. 46 | 47 | The HSDP line is also very quiet - Chartronics guarantees less than 95dB of noise 48 | at full speed! 49 | 50 | The HSDP-1D is a Data version of the model 1. Equipped with cutting edge memory 51 | chips and buses, this printer will be able to log everything you throw at it. 52 | It is built to print large amounts of data in a smaller amount of time, though 53 | it lacks the typesetting possibilities of the -1T Typesetting variant. 54 | 55 | ## Paper Format 56 | 57 | The paper used by the HSDP-1D is a continuous reel without natural "pages". 58 | 59 | Interrupt `2` can order the printer to cut the page after any line. 60 | 61 | Lines hold a maximum of 80 printed characters. 62 | 63 | ## Speed 64 | 65 | The HSPD-1D prints 4 lines per second. (The content of the line doesn't matter, 66 | blank lines are not "skipped".) 67 | 68 | This works out to 240 lines per minute, or 4 pages per minute at 60 lines per 69 | page. (The HSPD-1D doesn't use pages, this is just for comparison with inferior 70 | printers from other manufacturers.) 71 | 72 | 73 | ## Printing Modes 74 | 75 | The HSDP line is built around modes. The model 1D has three modes: 76 | 77 | | ID | Mode Name | Content of one line | Line Size | 78 | | :--- | :--- | :--- | :--- | 79 | | 0 | Text Mode | 80 ASCII characters | 80 words | 80 | | 1 | Data Mode | 16 words | 16 words | 81 | | 2 | Hex Mode | 8 words | 8 words | 82 | 83 | When ordered to print a line (see the interrupts below), the HSDP will read 80 84 | words (mode 0), 16 words (mode 1) or 8 words (mode 2) from the DCPU memory, and 85 | print a line containing that data. 86 | 87 | ### Mode 0 88 | 89 | Mode 0 prints standard ASCII text. Only the lower 7 bits of each word are 90 | actually respected when printing. Control characters (including newlines, 91 | carriage returns and tabs) are ignored. 92 | 93 | ### Mode 1 94 | 95 | Mode 1 prints 16 words formatted as hex with spaces between: 96 | 97 | ``` 98 | 0000 1111 2222 3333 4444 5555 6666 7777 8888 9999 aaaa bbbb cccc dddd eeee ffff 99 | ``` 100 | 101 | ### Mode 2 102 | 103 | Mode 2 prints 8 words formatted as hex, in a "hex dump" style: 104 | 105 | ``` 106 | 80b0: 0000 1111 2222 3333 4444 5555 6666 7777 01234567 107 | ```` 108 | 109 | Where the rightmost block of text is the ASCII equivalents (where defined) or 110 | `.` if non-printing. 111 | 112 | As with Mode 0 ASCII text, the upper 9 bits of each word are ignored for ASCII 113 | purposes. 114 | 115 | 116 | ## Interrupt Behavior 117 | 118 | - **0x0000: Set Mode** - Reads register `B` and sets the mode to `B`. 119 | (Undefined modes will result in undefined behavior.) 120 | - **0x0001: Get Mode** - Sets register `A` to the current mode. 121 | - **0x0002: Cut Page** - Cuts the text at this point. Blocks until all buffered 122 | data is printed (see below on buffering). 123 | - **0x0003: Print single line** - Reads `B` and prints a full line (according to the 124 | current mode) from the DCPU memory starting at `B`. 125 | - **0x0004: Print multiple lines** - Reads `B` and `C`, and prints `C` full lines 126 | (according to the current mode) from memory starting at `B`. 127 | - **0x0005: Full dump** - Halts the DCPU and prints the entire memory in the current 128 | mode. Note that this takes quite a while! 129 | - Mode 0: 410 seconds (3 minutes, 25 seconds) 130 | - Mode 1: 2048 seconds (17 minutes, 4 seconds) 131 | - Mode 2: 4906 seconds (34 minutes, 8 seconds) 132 | - **0x0006: Buffer status** - Sets `A` to the number of lines worth of data 133 | currently buffered. If this returns 0, then calls to `2`, `3` or `4` won't 134 | block (unless you tell `4` to print more than will fit in the buffer). Note 135 | that the number of lines depends on the mode. 136 | - **0xFFFF: Reset** - The standard reset interrupt. Resets the mode to 0, and 137 | cuts the current page, if any. 138 | 139 | ## Buffers and Speed 140 | 141 | The HSDP-1D has an internal buffer that allows it to quickly copy memory from 142 | the DCPU and let the DCPU continue while printing is still in progress. That 143 | memory can hold 640 words of data. 144 | 145 | 640 words is enough for 8 lines in mode 0, 40 lines in mode 1, and 80 lines in 146 | mode 2. 147 | 148 | If ordered to print more than will fit in this buffer, the HSPD-1D will halt the 149 | DCPU until all data to be printed is either on paper or in the buffer, and then 150 | the DCPU proceeds. 151 | 152 | When interrupt `2` orders the page to be cut, and the buffer is nonempty, the 153 | DCPU is halted until the buffered data is completely printed, then the page is 154 | cut and control is returned to the DCPU. 155 | 156 | ## Other Models 157 | 158 | - The HSDP-1T (Typesetting) model supports customized fonts. Indeed, since the 159 | font contains more characters than the line, and the font can be changed for 160 | each line, the -1T can print an arbitrary dot matrix. The cost is that the -1T 161 | prints only 2 lines per second, and only has ASCII mode. 162 | 163 | -------------------------------------------------------------------------------- /CraftComponents/VTACI.md: -------------------------------------------------------------------------------- 1 | Vectored Truster Array Control Interface 2 | ----- 3 | 4 | ``` 5 | \ \\ Rin Yu Research Group 6 | /\ / 凜羽研究小組 7 | 8 | ``` 9 | 10 | | Item | Value | Comment 11 | | -------------: | ---------- | ---------------- 12 | | Vendor code | 0xC2200311 | Rin Yu Research 13 | | Device ID | 0xF7F7EE03 | VTACI 14 | | Device type | 0xF7F7 | Trust Control Card 15 | | Version | 0x0400 | Version 4.0 16 | 17 | VTACI is advanced control of vector impulse trusters, many thruster are support 18 | on each device with full or automatic control of thruster in groups. 19 | 20 | VTACI have two control mode for operation of thrusters 21 | - Direct Group Mode - Software on DCPU control each thruster. 22 | - Vector Process Mode - Software on DCPU sends moment/force and VTACI controls. 23 | 24 | New installs of VTACI and thruster are calibrated, if add more thrusters, VTACI 25 | must be re-run calibration process for proper function. Calibrate is require 26 | for correct operation of VTACI in any mode, recommended always calibrate device. 27 | 28 | Interrupt Commands 29 | ---- 30 | 31 | DCPU HWI Interrupts VTACI and makes use of register A in DCPU to select action: 32 | 33 | - **0x0000**: Stop All Thrust 34 | 35 | Disable all thruster and turn off all memory map control. 36 | 37 | - **0x0001**: Calibrate Thrusters 38 | 39 | Important to do when installed, takes 10 seconds plus 2 for each thruster. 40 | Only need to do one time or when thrusters added. 41 | 42 | - **0x0002**: Calibrate Status 43 | 44 | Will set DCPU register A to value for status: 45 | - 0 - device is OK and Calibrate 46 | - 1 - device is busy run calibrate process 47 | - 2 - device is need calibrate run 48 | - 0xffff - device is damage or crashed, need to power off and on to fix. 49 | 50 | Will set DCPU register B to number of attach thrusters. 51 | Will set DCPU register C to number of attach gimbles. 52 | 53 | - **0x0003**: Set Thrust mode 54 | 55 | DCPU register C value is use to pick mode: 56 | - 0 - disable mode, turn off all thruster 57 | - 1 - force and moment mode, use memory at address from DCPU register B 58 | - 2 - group control mode, use memory at address from DCPU register B 59 | - other values are not correct and VTACI will do nothing different. 60 | - more detail is later, B is *base address*. 61 | 62 | - **0x0004**: Get Information of Thrusters 63 | 64 | store information at memory at address from DCPU register B. 65 | 5 memory words are need for each thruster and is stored information: 66 | - N+0 - X vector in mm from center of mass or VTACI. 67 | - N+1 - Y vector in mm from center of mass or VTACI. 68 | - N+2 - Z vector in mm from center of mass or VTACI. 69 | - N+3 - Hex number of direction, 0xWZYX, 0 = -1, 8 = 0, F = +1; 70 | W = 0: from center of mass, W = 1: from center of VTACI. 71 | - N+4 - Hex number of thrust rated, 0xETTT, Thrust = (TTT x 10 ^ ( -6 + E )) 72 | newtons. 73 | 74 | DCPU register A will get set to number of thrust information. 75 | Memory use is A x 5. 76 | DCPU register C will set to 0 if OK, or set to 1 if not calibrate. 77 | No memory will set if C is not 0 and OK, and A will set to 0. 78 | 79 | - **0x0005**: Get Information of Gimbles 80 | 81 | store information at memory at address from DCPU register B. 82 | 2 memory words are need for each gimble and is stored information: 83 | - N+0 - Hex number 0xYYXX, XX and YY are range of motion 00=0, FF=90 degree. 84 | - N+1 - Number of thruster attached to gimble. 85 | 86 | - **0x0006**: Set Truster Groups 87 | 88 | read information at memory at address from DCPU register B. 89 | 1 memory word are need for each thruster, offset (group) for thruster. 90 | This only need for thrust group mode. 91 | Each thruster will use 1 word at offset + base for control. 92 | 93 | Largest offset number is amount of memory read for control. 94 | 95 | **IMPORTANT** *Larger max offset number reduce response time.* 96 | 97 | - **0x0007**: Set Gimble Groups 98 | 99 | read information at memory at address from DCPU register B. 100 | 1 memory word are need for each gimble: offset (group*2) for gimble. 101 | Each gimble will use 2 words at offset + base for control. 102 | 103 | Largest offset number + 1 is amount of memory read for control. 104 | 105 | **IMPORTANT** *Larger max offset number reduce response time.* 106 | 107 | - **0x0008**: Thrusters Status 108 | 109 | write information at memory at address from DCPU register B. 110 | 1 memory word are need for each thruster, the status of thruster. 111 | 112 | - 0 - Thruster off and OK. 113 | - 1 - Thruster firing and OK. 114 | - 0x100 - Thruster not respond to VTACI command. 115 | - 0x101 - Thruster overheat. 116 | - 0x102 - Thruster on malfunction gimble. 117 | 118 | **IMPORTANT** *Use of 10+N DCPU cycle for interrupt, N=number thrusters* 119 | 120 | Will set DCPU register A equal number of error thrusters. 121 | 122 | - **0xffff**: Reset 123 | 124 | Reset offset groups, disable all thrusters, disable mode. 125 | Will cancel in progress calibrate, but will not delete already calibrate data. 126 | 127 | Behaviours 128 | ---- 129 | 130 | VTACI have 3 mode of operation: 131 | - Disable mode - thrusters off 132 | - Group Control - memory control of individual thruster or group of thruster 133 | - Moment+Force Mode - memory control of automatic group of thruster 134 | 135 | **IMPORTANT** *VTACI must run calibrate before first use or if thruster added.* 136 | 137 | **IMPORTANT** *Thruster should not be attach more than 32m from center of mass* 138 | *for Moment+Force mode. or 32m from VTACI in total.* 139 | 140 | VTACI will calibrate for thrusters offset from center of mass if possible, 141 | otherwise calibrate for thrusters offset from center of VTACI. 142 | 143 | ##### Moment+Force Mode 144 | 145 | VTACI will automatically compute what thrusters should fire for moment or force. 146 | Output rate for force and moment are added and clamped to maximum. 147 | 148 | VTACI will read 6 words of memory at *base address* for this mode: 149 | - B+0: X vector of force 150 | - B+1: Y vector of force 151 | - B+2: Z vector of force 152 | - B+3: X vector of moment 153 | - B+4: Y vector of moment 154 | - B+5: Z vector of moment 155 | 156 | For force: X+ is "right", Y+ is "forward", Z+ is "up". 157 | For moment: vector+ is clockwise towards axis+. 158 | 159 | Each force vector will fire all thrusters with opposite axis direction. 160 | 161 | Each moment vector will fire all thrusters on all side of axis that will contribute 162 | moment force. 163 | 164 | As example: Y+ moment would apply to: 165 | - X+ thrusters below Z plane 166 | - X- thrusters above Z plane 167 | - Z+ thrusters right X plane 168 | - Z- thrusters left X plane 169 | 170 | All vectors can scale thrust output levels from 0% to 100%. 171 | Force+Moment mode will center all gimbles and not use them. 172 | 173 | 174 | ##### Group Control Mode 175 | 176 | Mode for larger craft using VTACI, gimble control, or just more direct control. 177 | 178 | VTACI will read *max offset* memory words starting at *base address*. 179 | Each thruster will read 1 word at assigned offset, that is scaler output level. 180 | 0 = Off, 65535 = Full On. all thruster with same offset get same value. 181 | Each gimble will read 2 words, that is vector direction, X then Y. 182 | Numbers -32767 is full axis minus, 0 is center, 32767 is axis plus. 183 | Number -32768 is also full axis minus. 184 | All gimble with same offset get same vector direction. 185 | 186 | **IMPORTANT** *base address is use for both gimble and thrusters. Offset* 187 | *of gimble and thruster overlapping can be undesired.* 188 | 189 | **IMPORTANT** *not setting offsets before using this mode can be undesired.* 190 | 191 | **IMPORTANT** *Larger max offset will reduce respone time.* 192 | 193 | ----- 194 | 195 | Distributed for VTACI devices by Rin Yu Research Group. 196 | 197 | **WARNING** *Use of device for any non-research activity may void any warrenty.* 198 | 199 | ``` 200 | "Knowledge helps you make a living; wisdom helps you make a life." 201 | -- Director Rin Yu. 202 | ``` 203 | 204 | -------------------------------------------------------------------------------- /HIC-Misc/elevator.md: -------------------------------------------------------------------------------- 1 | 2 | Lift Control Module 3 | ---- 4 | 5 | **WARNING** 6 | *Improper use and servicing of lift equipment may cause severe injury,* 7 | *electric shock, or death. To be serviced by licensed lift technicians only.* 8 | 9 | #### Overview 10 | 11 | The lift control module is an automated system to control passenger elevation 12 | equipment. The LCM is designed as a drop-in control for stand-alone unattended 13 | automated lifts, while also providing features for more advanced external control. 14 | 15 | #### Basic operation 16 | 17 | The lift control provides an easy to use external interface to allow passengers 18 | to safely control the device. The interface consists of the button control 19 | panel in the lift car, and one or two *call* buttons outside each lift stop 20 | (floor) for up/down as applicable. 21 | 22 | Pressing either of the *call* buttons at a lift stop will send a request to 23 | the lift car to travel to that floor. 24 | 25 | Pressing a *floor select* button on the interface inside the lift car will 26 | request it travel to the corresponding floor. 27 | 28 | When idle, any request will cause the lift to immediately begin travelling to 29 | the requested floor. When the lift reaches any requested floor (or is already 30 | at the requested floor), it will stop; open the access doors; attempt to close 31 | the access doors after a delay; and once closed, either travel to the next 32 | requested floor or return to idle state. 33 | 34 | All lift requests are by default processed according to this priority: 35 | 36 | 1. Any lift stop in the travel path currently internally requested or calling 37 | in the same travel direction. 38 | 2. A first-in first-out (FIFO) queue of floors requested by the internal panel. 39 | 3. A first-in first-out (FIFO) queue of external lift stop requests 40 | (that have not been visited yet). 41 | 42 | ##### Example 43 | - Lift is at F1 44 | - F3 calls lift to go up (3) 45 | - Lift begins travel (up) 46 | - Lift stops at F3 47 | - F7 then F5 requested by internal panel (2) 48 | - Lift begins travel (up) 49 | - F4 calls lift to go up (3) 50 | - F6 calls lift to go down (3) 51 | - Lift stops at F4 (1) 52 | - Lift stops at F5 (1) 53 | - Lift stops at F7 (2) 54 | - Lift begins travel (down) 55 | - Lift stops at F6 (3) 56 | - F2 is requested internally (2) 57 | - Lift stops at F2 (2) 58 | - Lift returns to idle. 59 | 60 | #### Override Mode 61 | 62 | The LCM can be put in *override* mode, using a key or override command. 63 | In this mode, the LCM will ignore/cancel all lift calls and requests, the lift 64 | car may move up and down and stop freely (at points other than lift stops), 65 | and the doors may open and close freely. 66 | 67 | **WARNING** 68 | *Having the lift travel with the doors open will void the installation* 69 | *warranty and may cause damage to the lift car, internal/external doors.* 70 | *Improper operation in override mode may cause injury or death.* 71 | 72 | #### External Control Mode 73 | 74 | For advanced use cases, the LCM can be put in External control mode. While in 75 | this mode requests and calls will not be added to FIFOs unless no command is 76 | received in 30 seconds. If the 30 second timeout is reached the device returns 77 | to the default operation mode. 78 | 79 | #### Modes summary 80 | 81 | | Mode | Description | 82 | | -------: | -------------------------------------------------------------- | 83 | | Default | Follows Basic Operation semantics | 84 | | External | Sends progess/status messages, if times out returns to Default | 85 | | Override | Lift motion unrestricted, inputs ignored, unsafe actions allowed | 86 | | External + Override | Sends/progess status messages, inputs sent messages, but do not trigger timeout. | 87 | 88 | Diagnostic Interface 89 | ---- 90 | 91 | The Lift control module features an external signalling interface to provide 92 | advanced control. Commands can be sent over this interface to control the lift, 93 | queue, doors, and a number of other things. 94 | 95 | ##### Control Commands 96 | | Sequence | Name | Description | 97 | | ------------- | ----------- | ------------------------------------- | 98 | | 0x0000 0x00nn | CALL_EXT | Call lift to floor *nn* using external FIFO (both directions) | 99 | | 0x0001 0x00nn | CALL_INT | Request lift to floor *nn* using internal FIFO | 100 | | 0x0002 0x00nn | CALL_PRI | Send lift to directly to floor *nn* with out stopping at other floors | 101 | | 0x0003 0x00nn | SET_ACC_R | Set floor *nn* to *restricted* access, ignore all internal requests for it | 102 | | 0x0004 | LIFT_STOP | Stop at next floor (if travelling), chime, and/or open door | 103 | | 0x0005 | DOOR_CLOSE | Safely close the lift door, if open. | 104 | | 0x0006 | CHIME_1 | Sound the arrival chime. | 105 | | 0x0007 | CHIME_2 | Sound the progress chime. | 106 | | 0x0008 | CHIME_3 | Sound the alert chime. | 107 | | 0x0009 0x00nn | DISPLAY | Change the current floor status display to *nn* | 108 | | 0x000A 0x00nn | CALL_CNCL | Remove all calls/requests for *nn* from FIFOs | 109 | | 0x000B 0x000N | CAR_CNTL | Bits turn devices on/off (see Device control) | 110 | | 0x000C | SET_EXT | Put the LCM in external control mode | 111 | | 0x000D | DIAG | LCM sends 0xADXN - X is status bits (see below), N is devices status | 112 | | 0x000E | ECHO | LCM sends 0xA00E | 113 | | 0x000F | MODE_RESET | Return to default mode, external mode is disabled, performs **COVERRIDE** if override mode was active | 114 | | 0x0010 | GET_LSTOP | LCM sends 0xAAnn where *nn* is the current floor or last floor passed while travelling | 115 | | 0x0011 0x00nn | GET_ACC_R | LCM sends 0xA001 if *nn* is *restricted* access or 0xA000 if not. | 116 | | 0x0020 | OVERRIDE | Put LCM in override mode. | 117 | | 0x0021 0x000n | TRAVEL_UP | Begin moving up at speed *n*, 0 means stop | 118 | | 0x0022 0x000n | TRAVEL_DN | Begin moving down at speed *n*, 0 means stop | 119 | | 0x0023 | DOOR_OPEN | Force doors to open. | 120 | | 0x0024 | FDOOR_CLOSE | Force doors to close **without safety checks** (use DOOR_CLOSE instead where possible) | 121 | | 0x002F | COVERRIDE | Disable override mode, safely close doors and travel to nearest lift stop. | 122 | 123 | ##### Progress Messages 124 | The LCM will send progress messages while in external control mode. 125 | 126 | | Action | Sent Sequence | Detail | 127 | | ----------------- | ------------- | ------------------------------------------ | 128 | | Generic No | 0xA000 | Sent by any GET_* for simple Yes/No status | 129 | | Generic Yes | 0xA001 | Sent by any GET_* for simple Yes/No status | 130 | | Lift Travelling | 0xA002 | Lift has begun moving | 131 | | Generic Acknowledge | 0xA003 | Sent by any command that does not send other status | 132 | | Lift Parking | 0xA004 | Sent before Lift parks and opens door | 133 | | Door Closed | 0xA005 | Door safely closed successfully | 134 | | Request Timeout | 0xA006 | A command was not sent in the external control mode timeout, and the default action is being taken. | 135 | | Echo Response | 0xA00E | Sent in response to ECHO command | 136 | | Door Forced Open | 0xA023 | Door forced open by command or physical action | 137 | | Lift Stop Passed/Reached | 0xAANN | NN=Floor | 138 | | Diagnostic | 0xADXN | Sent in response to DIAG command, X/N are status bit fields. | 139 | | External Call | 0xCLNN | L=direction up(1)/down(0) NN=Calling floor | 140 | | Internal Request | 0xC2NN | NN=Requested floor | 141 | 142 | ##### System status bits 143 | - Bit 0 - Stopped (0) / Travelling (1) 144 | - Bit 1 - Door Closed (0) / Door Open (1) 145 | - Bit 2 - Last travel direction: Down (0) / Up (1) 146 | - Bit 3 - Queues Empty (0) / Busy (1) 147 | 148 | ##### Device Control/Status Bits 149 | Setting to 1 enables a device, a status of 1 means enabled AND *working*. 150 | Setting to 0 disables, a status of 0 means disabled OR broken. 151 | - Bit 0: Main lights 152 | - Bit 1: Emergency lights 153 | - Bit 2: Vent fan 154 | - Bit 3: Chime 155 | 156 | -------------------------------------------------------------------------------- /Displays/EDC.md: -------------------------------------------------------------------------------- 1 | Embedded Display Controller 2 | ---- 3 | 4 | ``` 5 | ____ _____________ _____ 6 | / | / / ____/ _____ / 7 | / |/ / /________ / 8 | / /| /|/ __/_ __/ 9 | /___/ |____/ /__/|__/__/ ___ 10 | /___/ |___/ /______/__/ ___ / 11 | /___/__________|___|/__/__ / 12 | /_________________/_______/ 13 | 14 | ``` 15 | 16 | | Item | Value | Comment 17 | | -------------: | ---------- | ---------------- 18 | | Vendor code | 0x59EA5742 | Meisaka Engineering and Integration 19 | | Device ID | 0x70E3E4FF | EDC 20 | | Device type | 0x70E3 | Text cell based, command driven, monochrome display 21 | | Version | various | Determines display characteristics, see below. 22 | 23 | The EDC or *Embedded Display Controller* is a small, command based controller and driver for small cell based text screens. 24 | Several models of EDC are available to drive both low power liquid crystal displays (LCD), as well as brighter vacuum fluorescent display (VFD) screens. 25 | 26 | The EDC comes in two different feature sets: 27 | - Basic module feature set EDC: only acts as a display driver. 28 | - Advanced modules feature set EDC: includes both the display controller/driver and input controller. 29 | 30 | Basic/Advanced EDC display driver/controller features: 31 | - 128 programmable glyphs. 32 | - 8 x 5 pixel text characters with built-in ASCII compatible character set. 33 | - Automatic blinking prompt control. 34 | - up to 4 lines and 124 column display modules supported. 35 | - built-in display RAM (write only by host device) 36 | - simple command driven interface with both serial and DCPU options available. 37 | 38 | Advanced EDC input controller features: 39 | - full 4 x 4 matrix keypad decoder with automatic scanning. 40 | - 3 line accessory function/power control bits. 41 | - 16 word multiplex registers for extended/more advanced accessories. 42 | - utilizes the same simple command driven interface as the display. 43 | - programmable transmit/interrupt for keypad. 44 | 45 | Interrupt Commands 46 | ---- 47 | 48 | The display controller may be interfaced directly to a DCPU or connected via a serial interface. 49 | When connected to a DCPU, register A will hold the command index, and register B will hold the first parameter value, C and X hold parameters 2 and 3 respectively for advanced mode commands. 50 | When connected to a serial interface, the first word (or high word of 32 bit message) sent to the EDC acts as the command index, and the second word (or 32 bit low word) sent is the parameter value (if required). 51 | 52 | - **0x0000**: DISPLAY_CONTROL 53 | - Display options depend on each individual bit of the parameter. 54 | ``` 55 | MSB ---- ---- LSB 56 | ....0000 ...00000 57 | |||| ||||\ 58 | |||| |||\ Display power: 0 is off, 1 is on 59 | |||| ||\ Backlight power: 0 is off, 1 is on (ignored if no backlight present) 60 | |||| |\ Cursor display: 0 is off, 1 is on 61 | |||| \ Cursor blink: 0 is steady, 1 is blink 62 | |||\ Cursor style: 0 is block, 1 is underscore 63 | ||\ Keypad enable (Advanced module) 64 | |\ Accessory 1 enable (Advanced module) 65 | \ Accessory 2 enable (Advanced module) 66 | Accessory 3 enable (Advanced module) 67 | 68 | Other bits are ignored by the display. 69 | ``` 70 | - **0x0001**: CURSOR_ADDRESS 71 | - Sets the cursor address to the value of the parameter. 72 | - Line 0 always starts at 0x0000 73 | - Line 1 always starts at 0x0080 74 | - Line 2 always starts at 0x0100 75 | - Line 3 always starts at 0x0180 76 | - Glyph RAM starts at 0x0200 and ends at 0x0400 77 | - Values above 0x03FF are ignored and do not affect the display 78 | - Values beyond line length will put the cursor offscreen, the next character written will not be visible, and will reset the cursor to the beginning of the next line 79 | - When the cursor is set to glyph RAM, it will count up each write until it reaches the end of glyph RAM at 0x0400, at that point it will return to 0x0000. 80 | - **0x0002**: RESET_CONTROL 81 | - The parameter controls what action to take: 82 | - Bit 0: Clear screen if set 83 | - Bit 1: Home cursor to address 0 if set. 84 | - **0x0003**: WRITE_DISPLAY 85 | - The parameter controls what to display: 86 | - Bits 0-7: Character to display: 87 | - 0x00-0x7F: built-in font glyphs 88 | - 0x80-0xFF: character RAM glyphs. 89 | - Bit 8: Do not advance cursor (overwrite), cursor advances if not set. 90 | - When cursor is in glyph RAM, writes the entire 16 bit value and advances. 91 | - **0x0080**: READ_KEYPAD (Advanced modules only) 92 | - reads the state of all keys on the keypad, a 16 bit value represents the keypad matrix, 1 = pressed, 0 = not pressed. 93 | - All bits will read as 0 when the keypad is disabled, even if the keys are pressed. 94 | - for consistency, the columns should be wired left to right ascending, rows top to bottom ascending: 95 | - bit 0 would be the top left most key. 96 | - bit 3 would be the top right most key. 97 | - bit 15 would be the bottom right most key. 98 | - in DCPU mode, this is stored in A. 99 | - in serial mode, the 16 bit value is simply transmitted. 100 | - **0x0081**: SET_KEYPAD_NOTIFY (Advanced modules only) 101 | - this function takes a word parameter and saves it as the notification word. 102 | - if the parameter is zero: disable keypad notification 103 | - if the parameter is non-zero: enable keypad notification 104 | - when notification is enabled and the keypad state changes (key press/release) the EDC will notify: 105 | - for a DCPU interface, the EDC will send an interrupt with the saved word. 106 | - for serial interface, the EDC will transmit the saved word followed by the new 16 bit keypad state. 107 | - **0x0082**: READ_ACCESSORY (Advanced modules only) 108 | - takes a word parameter, and uses it as an index to a pair of the accessory registers. 109 | - index 0 would be the first two registers, 1 would be the next two, and so on. 110 | - only the lowest 3 bits are used as an index, (0-7 access all 16 registers in pairs), the upper bits are ignored, but should be set to 0 for compatibility. 111 | - accessory registers are bi-directional, but are not memory: they all read as all ones if no accessory is attached. 112 | - For DCPU connections: first accessory register value is stored in A, second in B. 113 | - For serial connections: transmits the first accessory register, hollowed by the second. 114 | - **0x0083**: WRITE_ACCESSORY (Advanced modules only) 115 | - takes 3 word parameters, the first parameter is an index to a pair of the accessory registers, parameter 2 and 3 are the first and second values (respectively) to write to the accessory registers. 116 | - index 0 would be the first two registers, 1 would be the next two, and so on. 117 | - only the lowest 3 bits are used as an index, (0-7 access all 16 registers in pairs), the upper bits are ignored, but should be set to 0 for compatibility. 118 | - **0xFFFE**: QUERY_DISPLAY 119 | - For serial connections: Causes the display to transmit 5 words containing vendor code, device ID and version 120 | - For direct DCPU connections: Has the same effect as an HWQ instruction. 121 | - **0xFFFF**: RESTART_DISPLAY 122 | - Resets all display settings and zeroes RAM. 123 | 124 | 125 | Behaviours 126 | ---- 127 | 128 | ### Version code 129 | Version code determines the display size and characteristics. 130 | ``` 131 | MSB ---- ---- LSB 132 | XXXXMMVI FRRCCCCC 133 | ``` 134 | * X: Reserved bits (always 0) 135 | * MM: Cell size, always 01: 8x5 pixel cells, with 1 pixel spacing 136 | * VI: Media type: 137 | * 11: Inverted LCD with backlight (active pixels are backlight color) 138 | * 10: VFD (active pixels glow VFD color) 139 | * 01: LCD with backlight (active pixels are dark) 140 | * 00: Reflective LCD (active pixels are dark). 141 | * F: Firmware version: 142 | * 0: Basic display module. 143 | * 1: Advanced display and input module. 144 | * RR: Text cell line count, lines = RR + 1 145 | * CCCCC: Text cell column count, columns = CCCCC * 4. 146 | 147 | Common values: 148 | * 0x0402: 1x8 cell, reflective LCD 149 | * 0x052A: 2x40 cell, backlit LCD 150 | * 0x0534: 2x80 cell, backlit LCD 151 | * 0x0625: 2x20 cell, VFD. 152 | 153 | ### Glyph RAM 154 | * The glyph RAM holds up to 128 custom raster glyphs; each glyph is 4 words 155 | * Glyphs are rasterized by the display horizontally, 8 bits per cell row 156 | * On the standard 5x8 cell this is: 157 | * Word 0: Bits 0-4 are row 1, columns 1-5 158 | * Word 0: Bits 8-12 are row 2, columns 1-5 159 | * Word 1: Bits 0-4 are row 3, columns 1-5 160 | * Word 1: Bits 8-12 are row 4, columns 1-5 161 | * Word 2: Bits 0-4 are row 5, columns 1-5 162 | * Word 2: Bits 8-12 are row 6, columns 1-5 163 | * Word 3: Bits 0-4 are row 7, columns 1-5 164 | * Word 3: Bits 8-12 are row 8, columns 1-5. 165 | * When a WRITE_DISPLAY query is called while the cursor is in the glyph RAM, the entire 16-bit value is written, allowing for a custom font. 166 | 167 | ### Cursor 168 | The cursor, when visible, always appears over the glyph (logical OR). 169 | 170 | ### ASCII 171 | The standard glyph font represents visible ASCII characters from 0x20 to 0x7F, glyphs from 0x00-0x1F are supplemental graphic characters. The display does not follow the concept of ASCII control characters. 172 | 173 | ---- 174 | 175 | Copyright 2016 Meisaka Yukara (CC BY 4.0) 176 | -------------------------------------------------------------------------------- /CPU/DCPU.md: -------------------------------------------------------------------------------- 1 | # DCPU-TC Spec - Preliminary draft 2 | 3 | ## Overview 4 | 5 | Memory consists of 216 (65536) 16-bit words. 6 | 7 | Registers are also 16-bit: 8 | - 8 general purpose registers: `A`, `B`, `C`, `X`, `Y`, `Z`, `I` and `J`. 9 | - Program counter: `PC` 10 | - Stack pointer: `SP` 11 | - Excess: `EX` 12 | - Interrupt address: `IA` 13 | 14 | ## Operands 15 | 16 | An operand is either a literal value, or a source/destination location where a value is stored. 17 | Locations are either a register, or a memory location, denoted `[address]`. 18 | 19 | Operands are represented as follows: 20 | 21 | | Cycles | Value | Description 22 | | -------|-------------|------------ 23 | | 0 | 0x00 - 0x07 | `A`, `B`, `C`, `X`, `Y`, `Z`, `I`, `J` 24 | | 0 | 0x08 - 0x0F | `[register as above]` 25 | | 1 | 0x10 - 0x17 | `[register + additional word]` 26 | | 0 | 0x18 | `[--SP]` or `PUSH` when writing, `[SP++]` or `POP` when reading 27 | | 0 | 0x19 | `[SP]` or `PEEK` 28 | | 1 | 0x1A | `[SP + additional word]`, also written `PICK n` 29 | | 0 | 0x1B | `SP` 30 | | 0 | 0x1C | `PC` 31 | | 0 | 0x1D | `EX` 32 | | 1 | 0x1E | `[additional word]` 33 | | 1 | 0x1F | additional word (literal) 34 | | 0 | 0x20 - 0x3F | literal value 0xFFFF - 0x1E (-1 to 30) (literal) 35 | 36 | ### Notes 37 | 38 | - Trying to write to a literal silently does nothing. 39 | - `PICK 0` is equivalent to `PEEK`, but takes an extra word and cycle. 40 | - Inline literals (0x20 - 0x3F) are only possible in the 6-bit `a` operand; see below. 41 | - Instructions that ignore their operand (eg. `RFI`) treat it as a read, and discard the value. 42 | - See the [Errata](https://github.com/techcompliant/TC-Specs/wiki/DCPU-Errata#operand-combinations) for details on obscure combinations, like what `SET SP, POP` does. 43 | 44 | 45 | ## Instructions 46 | 47 | An instruction consists of one to three words. The first word contains the opcode and two operands, in the format above. This first word is followed by the extra word required by the `a` operand, if any, then the extra word for the `b` operand, if any. 48 | 49 | If the lower 5 bits are all 0, then it is a single-operand instruction, otherwise it is a dual-operand instruction. 50 | 51 | The number of cycles taken to execute an instruction is equal to the cycles”of the instruction as given in the below tables, plus the sum of the cycles”of the operands as given in the above table. 52 | Even when the `b` operand is being read and written, its cycle cost is only paid once. 53 | 54 | ### Dual-operand instructions: 55 | 56 | Dual-operand instructions have the following format (MSB->LSB): 57 | 58 | “a” operand | “b” operand” | opcode 59 | ------------|--------------|------- 60 | 6 bits | 5 bits | 5 bits 61 | 62 | Note that only the 6-bit `a` operand can hold inline literals (0x20-0x3f). 63 | 64 | | Cycles | Opcode | Mnemonic | Description 65 | | -------|--------|------------|------------ 66 | | | 0x00 | | (Single-operand instruction) 67 | | 1 | 0x01 | `SET b, a` | `b = a` 68 | | 2 | 0x02 | `ADD b, a` | `b = b + a`, `EX = 1` if overflow, `0` otherwise 69 | | 2 | 0x03 | `SUB b, a` | `b = b - a`, `EX = 0xFFFF` if underflow, `0` otherwise 70 | | 2 | 0x04 | `MUL b, a` | `b = b * a`, `EX = ((b*a)>>16)&0xFFFF`, `a` and `b` are unsigned 71 | | 2 | 0x05 | `MLI b, a` | `b = b * a`, `EX = ((b*a)>>16)&0xFFFF`, `a` and `b` are signed 72 | | 3 | 0x06 | `DIV b, a` | `b = b / a`, `EX = ((b<<16)/a)0xFFFF`, if `a == 0` sets `b` and `EX` to 0; `a` and `b` are unsigned 73 | | 3 | 0x07 | `DVI b, a` | As `DIV`, with `a` and `b` signed. Rounds towards 0 (see below). 74 | | 3 | 0x08 | `MOD b, a` | `b = b % a`, if `a == 0` sets `b` to 0, never sets `EX`; `a` and `b` are unsigned 75 | | 3 | 0x09 | `MDI b, a` | As `MOD`, with `a` and `b` signed. Rounds towards 0 (see below). 76 | | 1 | 0x0A | `AND b, a` | `b = b & a` 77 | | 1 | 0x0B | `BOR b, a` | `b = b \| a` 78 | | 1 | 0x0C | `XOR b, a` | `b = b ^ a` 79 | | 1 | 0x0D | `SHR b, a` | `b = b >>> a`, `EX = ((b << 16) >> a) & 0xFFFF`, logical shift (`b` unsigned) 80 | | 1 | 0x0E | `ASR b, a` | `b = b >> a`, `EX = ((b << 16) >>> a) & 0xFFFF`, arithmetic shift (`b` signed) 81 | | 1 | 0x0F | `SHL b, a` | `b = b << a`, `EX = ((b << a) >> 16) & 0xFFFF` 82 | | 2\* | 0x10 | `IFB b, a` | skip next instruction unless `b & a != 0` 83 | | 2\* | 0x11 | `IFC b, a` | skip next instruction unless `b & a == 0` 84 | | 2\* | 0x12 | `IFE b, a` | skip next instruction unless `b == a` 85 | | 2\* | 0x13 | `IFN b, a` | skip next instruction unless `b != a` 86 | | 2\* | 0x14 | `IFG b, a` | skip next instruction unless `b > a`, `a` and `b` unsigned 87 | | 2\* | 0x15 | `IFA b, a` | skip next instruction unless `b > a`, `a` and `b` signed 88 | | 2\* | 0x16 | `IFL b, a` | skip next instruction unless `b < a`, `a` and `b` unsigned 89 | | 2\* | 0x17 | `IFU b, a` | skip next instruction unless `b < a`, `a` and `b` signed 90 | | | 0x18 | | 91 | | | 0x19 | | 92 | | 3 | 0x1A | `ADX b, a` | `b = b + a + EX`, `EX = 1` if overflow, 0 otherwise 93 | | 3 | 0x1B | `SBX b, a` | `b = b - a + EX`, `EX = 0xffff` if underflow, 0 otherwise 94 | | | 0x1C | | 95 | | | 0x1D | | 96 | | 2 | 0x1E | `STI b, a` | `b = a`, `I++`, `J++` (does not change `EX`) 97 | | 2 | 0x1F | `STD b, a` | `b = a`, `I--`, `J--` (does not change `EX`) 98 | 99 | #### Branching instructions 100 | 101 | \* Branching instructions take 2 cycles when the check passes, and 3 when skipping. 102 | 103 | When skipping, if the next instruction is also a branching instruction, skipping 104 | continues at the cost of 1 extra cycle. This allows branching instructions to be 105 | "chained", with the next non-branching instruction executed only if all the 106 | conditions are true. 107 | 108 | #### On Signed Division 109 | 110 | Short answer: Quotients are always rounded toward 0. 111 | 112 | For example, `-7 / 2` is `-3.5`, which rounds to `-3`. `-3 * 2 = -6`, so the 113 | remainder is `-1`. 114 | 115 | For a more detailed discussion with extra examples, see the [Errata](https://github.com/techcompliant/TC-Specs/wiki/DCPU-Errata#signed-division). 116 | 117 | #### EX 118 | 119 | Note that `EX` is written last, for operations that set it. This is important 120 | when `EX` is also an argument. 121 | 122 | The general order is: read `a`, read `b`, write `b`, write `EX`. 123 | 124 | See the [Errata](https://github.com/techcompliant/TC-Specs/wiki/DCPU-Errata#operand-combinations) for examples. 125 | 126 | 127 | ### Single-operand instructions: 128 | 129 | Single-operand instructions have the following format (MSB->LSB): 130 | 131 | “a” operand | opcode | 00000 132 | ------------|--------|------- 133 | 6 bits | 5 bits | 5 bits 134 | 135 | | Cycles | Opcode | Mnemonic | Description 136 | | -------|--------|----------|------------- 137 | | | 0x00 | | Reserved 138 | | 3 | 0x01 | `JSR a` | Pushes `PC`, then sets `PC = a` 139 | | | 0x02 | | 140 | | | 0x03 | | 141 | | | 0x04 | | 142 | | | 0x05 | | 143 | | | 0x06 | | 144 | | | 0x07 | | 145 | | 4 | 0x08 | `INT a` | Software interrupt with message `a` 146 | | 1 | 0x09 | `IAG a` | Sets `a = IA` 147 | | 1 | 0x0A | `IAS a` | Sets `IA = a` 148 | | 3 | 0x0B | `RFI a` | Return from interrupt: Pop `A`, pop `PC`, disable interrupt queuing (note `a` is not actually used) 149 | | 2 | 0x0C | `IAQ a` | `a != 0`: interrupts are queued; `a == 0`: interrupts trigger normally 150 | | | 0x0D | | 151 | | | 0x0E | | 152 | | | 0x0F | | 153 | | 2 | 0x10 | `HWN a` | Sets `a` to the number of connected hardware devices 154 | | 4 | 0x11 | `HWQ a` | Queries hardware device `a` for information. `A+(B<<16)` = hardware ID, `C` = hardware version, `X+(Y<<16)` = manufacturer ID 155 | | 4+ | 0x12 | `HWI a` | Send interrupt to hardware device `a` 156 | | 1 | 0x13 | `LOG a` | Send value `a` to the log system 157 | | | 0x14 | `BRK a` | Send value `a` to the’conditional break system 158 | | | 0x15 | `HLT a` | Halts execution of code until resumed by hardware interrupt (note a is ignored; see section on Interrupts) 159 | | | 0x16 | | 160 | | | 0x17 | | 161 | | | 0x18 | | 162 | | | 0x19 | | 163 | | | 0x1A | | 164 | | | 0x1B | | 165 | | | 0x1C | | 166 | | | 0x1D | | 167 | | | 0x1E | | 168 | | | 0x1F | | 169 | 170 | ## Interrupts: 171 | 172 | Interrupts are generated by hardware, or by `SWI`. An interrupt has a 16-bit *message*. 173 | When an interrupt is generated, it goes into the queue (even if queueing is off). 174 | This allows for multiple devices to generate interrupts at the same time, 175 | without dropping any. 176 | 177 | When the DCPU goes to execute an instruction, it first checks for interrupts. If 178 | interrupt queueing is off, and there is at least one interrupt in the queue, 179 | that interrupt is triggered. 180 | 181 | When an interrupt is triggered, the DCPU checks `IA`. If `IA = 0`, the interrupt 182 | is discarded and execution continues normally. If `IA != 0`, the DCPU processes 183 | the interrupt as follows: 184 | 185 | 1. Turn on interrupt queueing 186 | 2. Push `PC` (the instruction we were about to execute) 187 | 3. Push register `A` 188 | 4. Set `PC = IA` 189 | 5. Set `A` to the interrupt message 190 | 191 | Execution then continues at `IA`. 192 | 193 | ### Notes 194 | 195 | - The `RFI` instruction is designed to neatly reverse the process above: 196 | it pops `A` and `PC`, and turns interrupt queuing off. 197 | - Conversely, `RFI` is not magic: you can return manually from an interrupt 198 | handler with other instructions. 199 | - Only one interrupt is popped at a time. If `IA = 0`, one interrupt is 200 | discarded for each instruction executed. 201 | - The maximum length of the interrupt queue is 256. When the 257th interrupt is 202 | added, the DCPU's behavior is undefined. (Generally, memory is corrupted 203 | unpredictably.) 204 | - Note that older models often caught fire in this condition; that hardware 205 | fault has been corrected, but the behavior is still undefined. 206 | - Interrupts are not checked while "skipping" due to a branch instruction, even 207 | if several instructions are skipped. Interrupts only trigger when instructions 208 | are actually executed. 209 | - Entering an interrupt does not cost any extra cycles. 210 | 211 | ### Nesting Interrupts 212 | 213 | Possible, with care. You are free to turn interrupt queueing off from inside an 214 | interrupt handler. 215 | 216 | Similarly, you are free to return from an interrupt without turning queueing 217 | off. 218 | 219 | ## Hardware 220 | 221 | A DCPU-TC can have up to 0xFFFF (65535) attached hardware devices. Devices are 222 | numbered from 0. Communication with these devices is achieved with interrupts. 223 | 224 | Upon receiving an interrupt with `HWI`, a hardware device can read/write to the 225 | DCPU-TC’s memory and registers. A device may not send an interrupt to the DCPU-TC 226 | or modify its memory and registers before it has received at least one interrupt 227 | from the DCPU-TC. 228 | 229 | ## Debugging 230 | 231 | DCPU-TC provides two main provisions for debugging - `LOG` and `BRK`. 232 | 233 | `LOG` will output a value to the computer's logging system, which is 234 | generally some output buffer displayed using an external device. 235 | 236 | `BRK` outputs a value to the computer's break system. This system 237 | performs some test on the value (eg, equality to some other value) 238 | and conditionally halts the DCPU-TC’s execution to allow for 239 | inspection of memory etc. 240 | 241 | Exactly how this debugging instructions work is dependent on the exact 242 | configuration of the DCPU system. In the simplest case, they may do nothing at 243 | all. 244 | 245 | ## Halt and Interrupt Queueing 246 | 247 | What happens when `HLT` is executed while interrupt queueing is on? 248 | 249 | Short answer: the DCPU is blocked forever, and must be hardware reset. 250 | 251 | In more detail, `HLT` blocks the DCPU until an interupt is *triggered*, not 252 | *generated*. Hardware devices and `SWI` *generate* interrupts that go in the 253 | queue, but it's only when interrupts *trigger* on the way out of the queue that 254 | the DCPU breaks out of `HLT` state. 255 | 256 | Since interrupts are never *triggered* when queueing is on, the DCPU is halted 257 | forever. 258 | 259 | Note that `HLT` state ends when an interrupt is triggered, even if `IA = 0` and 260 | the triggered interrupt gets discarded. 261 | 262 | 263 | ## Initial State 264 | 265 | On startup, the DCPU is in the following state: 266 | 267 | - All registers are 0 - including `PC`, `IA` and `SP`. 268 | - This implies that the first instruction to be executed is at 0. 269 | - Note that `SP` is decremented before storing, so the first value pushed 270 | goes in `[0xffff]`. 271 | - ROM is copied to the begining of memory. 272 | - All other memory is undefined - it may be 0, but it also may not. 273 | - Interrupt queueing is off (interrupts will flow, but `IA` is 0 so they'll be 274 | discarded). 275 | - All hardware devices are in their initial state (no memory mapped, etc.) 276 | 277 | That's true on a cold start, or a reset. 278 | 279 | --------------------------------------------------------------------------------