├── README.md ├── UART_IP_CORE_16550A_Verification_Plan.png ├── UART_sef.pdf ├── agt_top ├── agt.sv ├── agt_config.sv ├── agt_top.sv ├── drv.sv ├── mon.sv ├── seqr.sv ├── seqs.sv ├── temp.sv └── xtn.sv ├── rtl ├── raminfr.v ├── timescale.v ├── uart_debug_if.v ├── uart_defines.v ├── uart_if.sv ├── uart_receiver.v ├── uart_regs.v ├── uart_rfifo.v ├── uart_sync_flops.v ├── uart_tfifo.v ├── uart_top.v ├── uart_transmitter.v └── uart_wb.v ├── sim ├── Makefile ├── modelsim.ini ├── test1.log ├── test2.log ├── test3.log ├── test4.log ├── test5.log ├── test6.log ├── test7.log ├── test8.log ├── test9.log ├── uart_cov ├── uart_cov1 ├── uart_cov2 ├── uart_cov3 ├── uart_cov4 ├── uart_cov5 ├── uart_cov6 ├── uart_cov7 ├── uart_cov8 ├── uart_cov9 ├── wave_file1.wlf ├── wave_file2.wlf ├── wave_file3.wlf ├── wave_file4.wlf ├── wave_file5.wlf ├── wave_file6.wlf ├── wave_file7.wlf ├── wave_file8.wlf ├── wave_file9.wlf └── work │ ├── @_opt │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── 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