├── .circleci ├── README.md ├── build-run-csmith-tests.sh ├── build-toolchains.sh ├── clean-old-files.sh ├── config.yml ├── create-hash.sh ├── defaults.sh ├── do-rtl-build.sh ├── firesim-afi-failed.sh ├── firesim-build-afi.sh ├── firesim-build-workload.sh ├── firesim-configs │ └── firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3 │ │ ├── buildroot │ │ ├── config_runtime.ini │ │ └── firemarshal_config │ │ ├── config_build.ini │ │ ├── config_build_recipes.ini │ │ ├── coremark │ │ ├── config_runtime.ini │ │ └── firemarshal_config │ │ ├── fedora │ │ ├── config_runtime.ini │ │ └── firemarshal_config │ │ └── spec17-intspeed-test-600 │ │ ├── config_runtime.ini │ │ └── firemarshal_config ├── firesim-init-manager.sh ├── firesim-instance-resize-root.json ├── firesim-run-finished.sh ├── firesim-run-workload.sh ├── install-verilator.sh ├── prepare-for-rtl-build.sh └── run-tests.sh ├── .github ├── ISSUE_TEMPLATE.md └── PULL_REQUEST_TEMPLATE.md ├── .gitignore ├── CHIPYARD.hash ├── CONTRIB_AND_STYLE.md ├── LICENSE ├── LICENSE.HardFloat ├── LICENSE.OVI ├── LICENSE.SiFive ├── LICENSE.TT ├── Makefile ├── README-TT.md ├── README.md ├── TODO.md ├── chipstack_artifacts └── app_state │ └── 0.59.3 │ └── latest.json ├── compare_files.sh ├── docs ├── .gitignore ├── Bobcat_Final_Presentation.pdf ├── Bobtail-Final-Presentation.pdf ├── Makefile ├── conf.py ├── figures │ ├── 1w-rrd-bypass-pipeline.pdf │ ├── 1w-rrd-bypass-pipeline.png │ ├── 2bc-fsm.svg │ ├── 2bc-prediction.pdf │ ├── 2bc-prediction.png │ ├── abstract-functional-unit.pdf │ ├── abstract-functional-unit.png │ ├── boom-pipeline-detailed.png │ ├── boom-pipeline.svg │ ├── bpd.pdf │ ├── bpd.png │ ├── br-prediction-pipeline.svg │ ├── btb.pdf │ ├── btb.png │ ├── chip.pdf │ ├── chip.png │ ├── evolution.png │ ├── execution-pipeline-2w.pdf │ ├── execution-pipeline-2w.png │ ├── execution-unit.pdf │ ├── execution-unit.png │ ├── front-end.svg │ ├── functional-unit-fpu.pdf │ ├── functional-unit-fpu.png │ ├── functional-unit-hierarchy.pdf │ ├── functional-unit-hierarchy.png │ ├── gshare.svg │ ├── issue_slot.pdf │ ├── issue_slot.png │ ├── lsu.pdf │ ├── lsu.png │ ├── prf-and-arf.pdf │ ├── prf-and-arf.png │ ├── proj_bobtail │ │ ├── Bobtail_architecture.png │ │ └── Bobtail_architecture.svg │ ├── rename-pipeline.pdf │ ├── rename-pipeline.png │ ├── rob.pdf │ ├── rob.png │ ├── rvv │ │ ├── Bobcat_Design_Overview_Simplified.png │ │ ├── Bobcat_Design_VPU.png │ │ ├── VFP_EX_Unit.png │ │ ├── VFP_Encoder_256b.png │ │ ├── VFP_Encoder_Lane.png │ │ ├── VFP_Lane.png │ │ ├── VFP_Scalar_Unit.png │ │ └── VFP_Unit_Overview.png │ ├── tage.pdf │ ├── tage.png │ └── uarch.png ├── index.rst ├── pdf_to_png.sh ├── requirements.txt └── sections │ ├── bibliography │ └── bibliography.bib │ ├── boom-ecosystem.rst │ ├── branch-prediction │ ├── backing-predictor.rst │ ├── index.rst │ └── nl-predictor.rst │ ├── debugging.rst │ ├── decode-stage.rst │ ├── execution-stages.rst │ ├── faq.rst │ ├── future-work.rst │ ├── instruction-fetch-stage.rst │ ├── intro-overview │ ├── boom-pipeline.rst │ ├── boom.rst │ ├── chisel.rst │ ├── riscv-isa.rst │ └── rocket-chip.rst │ ├── issue-units.rst │ ├── load-store-unit.rst │ ├── memory-system.rst │ ├── parameterization.rst │ ├── physical-realization.rst │ ├── reg-file-bypass-network.rst │ ├── rename-stage.rst │ ├── reorder-buffer.rst │ ├── terminology.rst │ ├── uarch-counters.rst │ └── verification.rst ├── filecomp.txt ├── lsu_prev.temp ├── project ├── build.properties └── plugins.sbt ├── scalastyle-config.xml ├── src ├── main │ ├── resources │ │ ├── bootrom │ │ │ ├── Makefile │ │ │ ├── bootrom.S │ │ │ ├── bootrom.rv32.img │ │ │ ├── bootrom.rv64.img │ │ │ └── linker.ld │ │ ├── csrc │ │ │ ├── btb_sw.cc │ │ │ └── predictor_sw.cc │ │ └── vsrc │ │ │ ├── HardFloat │ │ │ ├── COPYING.txt │ │ │ ├── README.html │ │ │ ├── README.txt │ │ │ ├── doc │ │ │ │ ├── HardFloat-Verilog.html │ │ │ │ ├── HardFloat-test-Verilator.html │ │ │ │ └── HardFloat-test-Verilog.html │ │ │ ├── source │ │ │ │ ├── 8086-SSE │ │ │ │ │ ├── HardFloat_specialize.v │ │ │ │ │ └── HardFloat_specialize.vi │ │ │ │ ├── ARM-VFPv2 │ │ │ │ │ ├── HardFloat_specialize.v │ │ │ │ │ └── HardFloat_specialize.vi │ │ │ │ ├── HardFloat_consts.vi │ │ │ │ ├── HardFloat_localFuncs.vi │ │ │ │ ├── HardFloat_primitives.v │ │ │ │ ├── HardFloat_rawFN.v │ │ │ │ ├── RISCV │ │ │ │ │ ├── HardFloat_specialize.v │ │ │ │ │ └── HardFloat_specialize.vi │ │ │ │ ├── addRecFN.v │ │ │ │ ├── compareRecFN.v │ │ │ │ ├── divSqrtRecFN_small.v │ │ │ │ ├── fNToRecFN.v │ │ │ │ ├── iNToRecFN.v │ │ │ │ ├── isSigNaNRecFN.v │ │ │ │ ├── mulAddRecFN.v │ │ │ │ ├── mulRecFN.v │ │ │ │ ├── recFNToFN.v │ │ │ │ ├── recFNToIN.v │ │ │ │ └── recFNToRecFN.v │ │ │ └── test │ │ │ │ ├── build │ │ │ │ ├── IcarusVerilog │ │ │ │ │ ├── Makefile │ │ │ │ │ └── config.make │ │ │ │ └── Verilator-GCC │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── config.h │ │ │ │ │ └── config.make │ │ │ │ └── source │ │ │ │ ├── Verilator │ │ │ │ ├── testCommon.c │ │ │ │ ├── testCommon.h │ │ │ │ ├── test_abz_recF128.cpp │ │ │ │ ├── test_abz_recF16.cpp │ │ │ │ ├── test_abz_recF32.cpp │ │ │ │ ├── test_abz_recF64.cpp │ │ │ │ ├── test_compareRecF128.cpp │ │ │ │ ├── test_compareRecF16.cpp │ │ │ │ ├── test_compareRecF32.cpp │ │ │ │ ├── test_compareRecF64.cpp │ │ │ │ ├── test_divSqrtRecF128_small_div.cpp │ │ │ │ ├── test_divSqrtRecF128_small_sqrt.cpp │ │ │ │ ├── test_divSqrtRecF16_small_div.cpp │ │ │ │ ├── test_divSqrtRecF16_small_sqrt.cpp │ │ │ │ ├── test_divSqrtRecF32_small_div.cpp │ │ │ │ ├── test_divSqrtRecF32_small_sqrt.cpp │ │ │ │ ├── test_divSqrtRecF64_small_div.cpp │ │ │ │ ├── test_divSqrtRecF64_small_sqrt.cpp │ │ │ │ ├── test_f128ToRecF128.cpp │ │ │ │ ├── test_f16ToRecF16.cpp │ │ │ │ ├── test_f32ToRecF32.cpp │ │ │ │ ├── test_f64ToRecF64.cpp │ │ │ │ ├── test_i32ToRecF128.cpp │ │ │ │ ├── test_i32ToRecF16.cpp │ │ │ │ ├── test_i32ToRecF32.cpp │ │ │ │ ├── test_i32ToRecF64.cpp │ │ │ │ ├── test_i64ToRecF128.cpp │ │ │ │ ├── test_i64ToRecF16.cpp │ │ │ │ ├── test_i64ToRecF32.cpp │ │ │ │ ├── test_i64ToRecF64.cpp │ │ │ │ ├── test_mulAddRecF128.cpp │ │ │ │ ├── test_mulAddRecF16.cpp │ │ │ │ ├── test_mulAddRecF32.cpp │ │ │ │ ├── test_mulAddRecF64.cpp │ │ │ │ ├── test_recF128ToF128.cpp │ │ │ │ ├── test_recF128ToI32.cpp │ │ │ │ ├── test_recF128ToI64.cpp │ │ │ │ ├── test_recF128ToRecF16.cpp │ │ │ │ ├── test_recF128ToRecF32.cpp │ │ │ │ ├── test_recF128ToRecF64.cpp │ │ │ │ ├── test_recF128ToUi32.cpp │ │ │ │ ├── test_recF128ToUi64.cpp │ │ │ │ ├── test_recF16ToF16.cpp │ │ │ │ ├── test_recF16ToI32.cpp │ │ │ │ ├── test_recF16ToI64.cpp │ │ │ │ ├── test_recF16ToRecF128.cpp │ │ │ │ ├── test_recF16ToRecF32.cpp │ │ │ │ ├── test_recF16ToRecF64.cpp │ │ │ │ ├── test_recF16ToUi32.cpp │ │ │ │ ├── test_recF16ToUi64.cpp │ │ │ │ ├── test_recF32ToF32.cpp │ │ │ │ ├── test_recF32ToI32.cpp │ │ │ │ ├── test_recF32ToI64.cpp │ │ │ │ ├── test_recF32ToRecF128.cpp │ │ │ │ ├── test_recF32ToRecF16.cpp │ │ │ │ ├── test_recF32ToRecF64.cpp │ │ │ │ ├── test_recF32ToUi32.cpp │ │ │ │ ├── test_recF32ToUi64.cpp │ │ │ │ ├── test_recF64ToF64.cpp │ │ │ │ ├── test_recF64ToI32.cpp │ │ │ │ ├── test_recF64ToI64.cpp │ │ │ │ ├── test_recF64ToRecF128.cpp │ │ │ │ ├── test_recF64ToRecF16.cpp │ │ │ │ ├── test_recF64ToRecF32.cpp │ │ │ │ ├── test_recF64ToUi32.cpp │ │ │ │ ├── test_recF64ToUi64.cpp │ │ │ │ ├── test_ui32ToRecF128.cpp │ │ │ │ ├── test_ui32ToRecF16.cpp │ │ │ │ ├── test_ui32ToRecF32.cpp │ │ │ │ ├── test_ui32ToRecF64.cpp │ │ │ │ ├── test_ui64ToRecF128.cpp │ │ │ │ ├── test_ui64ToRecF16.cpp │ │ │ │ ├── test_ui64ToRecF32.cpp │ │ │ │ └── test_ui64ToRecF64.cpp │ │ │ │ ├── addRecFN_spec.v │ │ │ │ ├── compareRecFN_spec.v │ │ │ │ ├── divSqrtRecFN_small_spec.v │ │ │ │ ├── fNToRecFN_spec.v │ │ │ │ ├── finish_fail-IcarusVerilog.vi │ │ │ │ ├── iNToRecFN_spec.v │ │ │ │ ├── mulAddRecFN_spec.v │ │ │ │ ├── mulRecFN_spec.v │ │ │ │ ├── recFNToFN_spec.v │ │ │ │ ├── recFNToIN_spec.v │ │ │ │ ├── recFNToRecFN_spec.v │ │ │ │ ├── sameRecFN.v │ │ │ │ ├── test_addRecFN_add.v │ │ │ │ ├── test_addRecFN_sub.v │ │ │ │ ├── test_compareRecFN.v │ │ │ │ ├── test_divSqrtRecFN_small_div.v │ │ │ │ ├── test_divSqrtRecFN_small_sqrt.v │ │ │ │ ├── test_iNToRecFN.v │ │ │ │ ├── test_mulAddRecFN.v │ │ │ │ ├── test_mulAddRecFN_add.v │ │ │ │ ├── test_mulAddRecFN_mul.v │ │ │ │ ├── test_mulRecFN.v │ │ │ │ ├── test_recFNToFN.v │ │ │ │ ├── test_recFNToIN.v │ │ │ │ └── test_recFNToRecFN.v │ │ │ ├── btb_harness.v │ │ │ ├── core_harness.v │ │ │ ├── core_harness_interface.v │ │ │ ├── core_harness_wrapper_1.v │ │ │ ├── core_harness_wrapper_2.v │ │ │ ├── core_harness_wrapper_3.v │ │ │ ├── core_harness_wrapper_4.v │ │ │ ├── core_harness_wrapper_6.v │ │ │ ├── core_harness_wrapper_8.v │ │ │ ├── predictor_harness.v │ │ │ └── vpu │ │ │ ├── VecFP16rec7.sv │ │ │ ├── VecFP16rsqrt7.sv │ │ │ ├── VecFP32rec7.sv │ │ │ ├── VecFP32rsqrt7.sv │ │ │ ├── autogen_defines.h │ │ │ ├── autogen_riscv_imabfv.v │ │ │ ├── briscv_defines.h │ │ │ ├── lrm.sv │ │ │ ├── lrm.tcl │ │ │ ├── lrm_assertions.sv │ │ │ ├── lrm_model.sv │ │ │ ├── tt_ascii_instrn_decode.sv │ │ │ ├── tt_briscv_pkg.svh │ │ │ ├── tt_cam_buffer.sv │ │ │ ├── tt_compare.sv │ │ │ ├── tt_decoded_mux.sv │ │ │ ├── tt_decoder.sv │ │ │ ├── tt_ex.sv │ │ │ ├── tt_ffs.sv │ │ │ ├── tt_fifo.sv │ │ │ ├── tt_fifo_assert.sv │ │ │ ├── tt_fp16_div.sv │ │ │ ├── tt_fp32_div.sv │ │ │ ├── tt_id.sv │ │ │ ├── tt_idxldst_fsm.sv │ │ │ ├── tt_int_div_r2.sv │ │ │ ├── tt_int_div_simple.sv │ │ │ ├── tt_lq.sv │ │ │ ├── tt_mask_fsm.sv │ │ │ ├── tt_mem.sv │ │ │ ├── tt_memop_fsm.sv │ │ │ ├── tt_pipe_stage.sv │ │ │ ├── tt_popcnt.sv │ │ │ ├── tt_reshape.sv │ │ │ ├── tt_rts_rtr_pipe_stage.sv │ │ │ ├── tt_scoreboard_ovi.sv │ │ │ ├── tt_skid_buffer.sv │ │ │ ├── tt_store_buffer.sv │ │ │ ├── tt_vec.sv │ │ │ ├── tt_vec_div_unit.sv │ │ │ ├── tt_vec_iadd.sv │ │ │ ├── tt_vec_idp.sv │ │ │ ├── tt_vec_imul.sv │ │ │ ├── tt_vec_mul_dp.sv │ │ │ ├── tt_vec_regfile.sv │ │ │ ├── tt_vfp_encoder.sv │ │ │ ├── tt_vfp_encoder_lane.sv │ │ │ ├── tt_vfp_ex_unit.sv │ │ │ ├── tt_vfp_fma.sv │ │ │ ├── tt_vfp_lane.sv │ │ │ ├── tt_vfp_red.sv │ │ │ ├── tt_vfp_unit.sv │ │ │ ├── tt_vpu_ovi.sv │ │ │ ├── tt_vpu_ovi_assert.sv │ │ │ └── vpu.tcl │ └── scala │ │ ├── common │ │ ├── config-mixins.scala │ │ ├── consts.scala │ │ ├── micro-op.scala │ │ ├── package.scala │ │ ├── parameters.scala │ │ ├── tile.scala │ │ └── types.scala │ │ ├── exu │ │ ├── core.scala │ │ ├── decode.scala │ │ ├── dispatch.scala │ │ ├── execution-units │ │ │ ├── execution-unit.scala │ │ │ ├── execution-units.scala │ │ │ ├── fdiv.scala │ │ │ ├── fpu.scala │ │ │ ├── functional-unit.scala │ │ │ ├── ovi.scala │ │ │ └── rocc.scala │ │ ├── fp-pipeline.scala │ │ ├── issue-units │ │ │ ├── issue-slot.scala │ │ │ ├── issue-unit-age-ordered.scala │ │ │ ├── issue-unit-ordered.scala │ │ │ ├── issue-unit-unordered.scala │ │ │ └── issue-unit.scala │ │ ├── ovi_wrapper │ │ │ ├── ls_decode.scala │ │ │ ├── lsgen │ │ │ │ ├── loadgen.scala │ │ │ │ ├── loadpacker.scala │ │ │ │ ├── loadskipper.scala │ │ │ │ ├── loadwalker.scala │ │ │ │ ├── storegen.scala │ │ │ │ ├── storepacker.scala │ │ │ │ ├── storeskipper.scala │ │ │ │ └── storewalker.scala │ │ │ ├── mask_idx_buff.scala │ │ │ ├── ovi.scala │ │ │ ├── ovi_sb.scala │ │ │ └── vdb.scala │ │ ├── register-read │ │ │ ├── func-unit-decode.scala │ │ │ ├── regfile.scala │ │ │ └── register-read.scala │ │ ├── rename │ │ │ ├── rename-busytable.scala │ │ │ ├── rename-freelist.scala │ │ │ ├── rename-maptable.scala │ │ │ └── rename-stage.scala │ │ └── rob.scala │ │ ├── ifu │ │ ├── bpd │ │ │ ├── bim.scala │ │ │ ├── btb.scala │ │ │ ├── composer.scala │ │ │ ├── faubtb.scala │ │ │ ├── hbim.scala │ │ │ ├── local.scala │ │ │ ├── loop.scala │ │ │ ├── predictor.scala │ │ │ ├── ras.scala │ │ │ ├── sw_predictor.scala │ │ │ ├── tage.scala │ │ │ ├── tourney.scala │ │ │ └── ubtb.scala │ │ ├── fetch-buffer.scala │ │ ├── fetch-target-queue.scala │ │ ├── frontend.scala │ │ └── icache.scala │ │ ├── lsu │ │ ├── dcache.scala │ │ ├── lsu.scala │ │ ├── mshrs.scala │ │ ├── prefetcher.scala │ │ ├── tlb.scala │ │ └── tracegen.scala │ │ └── util │ │ ├── elastic-reg.scala │ │ ├── elastic-sram.scala │ │ ├── seqmem-transformable.scala │ │ └── util.scala └── test │ └── scala │ ├── RegFileTest.scala │ └── TestUtils.scala └── util ├── branch-processor.py ├── csmith ├── install-csmith.sh ├── run-csmith.sh └── sources │ ├── crt.S │ ├── encoding.h │ ├── link.ld │ ├── syscalls.c │ └── util.h ├── memtracer ├── Makefile └── memtracer.c └── pipeview-helper.py /.circleci/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/README.md -------------------------------------------------------------------------------- /.circleci/build-run-csmith-tests.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/build-run-csmith-tests.sh -------------------------------------------------------------------------------- /.circleci/build-toolchains.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/build-toolchains.sh -------------------------------------------------------------------------------- /.circleci/clean-old-files.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/clean-old-files.sh -------------------------------------------------------------------------------- /.circleci/config.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/config.yml -------------------------------------------------------------------------------- /.circleci/create-hash.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/create-hash.sh -------------------------------------------------------------------------------- /.circleci/defaults.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/defaults.sh -------------------------------------------------------------------------------- /.circleci/do-rtl-build.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/do-rtl-build.sh -------------------------------------------------------------------------------- /.circleci/firesim-afi-failed.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-afi-failed.sh -------------------------------------------------------------------------------- /.circleci/firesim-build-afi.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-build-afi.sh -------------------------------------------------------------------------------- /.circleci/firesim-build-workload.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-build-workload.sh -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/buildroot/config_runtime.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/buildroot/config_runtime.ini -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/buildroot/firemarshal_config: -------------------------------------------------------------------------------- 1 | chipyard/software/firemarshal/test 2 | command 3 | -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/config_build.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/config_build.ini -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/config_build_recipes.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/config_build_recipes.ini -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/coremark/config_runtime.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/coremark/config_runtime.ini -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/coremark/firemarshal_config: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/coremark/firemarshal_config -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/fedora/config_runtime.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/fedora/config_runtime.ini -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/fedora/firemarshal_config: -------------------------------------------------------------------------------- 1 | chipyard/software/firemarshal/test 2 | fed-run 3 | -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/spec17-intspeed-test-600/config_runtime.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/spec17-intspeed-test-600/config_runtime.ini -------------------------------------------------------------------------------- /.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/spec17-intspeed-test-600/firemarshal_config: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-configs/firesim-boom-singlecore-no-nic-l2-llc4mb-ddr3/spec17-intspeed-test-600/firemarshal_config -------------------------------------------------------------------------------- /.circleci/firesim-init-manager.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-init-manager.sh -------------------------------------------------------------------------------- /.circleci/firesim-instance-resize-root.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-instance-resize-root.json -------------------------------------------------------------------------------- /.circleci/firesim-run-finished.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-run-finished.sh -------------------------------------------------------------------------------- /.circleci/firesim-run-workload.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/firesim-run-workload.sh -------------------------------------------------------------------------------- /.circleci/install-verilator.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/install-verilator.sh -------------------------------------------------------------------------------- /.circleci/prepare-for-rtl-build.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/prepare-for-rtl-build.sh -------------------------------------------------------------------------------- /.circleci/run-tests.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.circleci/run-tests.sh -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.github/ISSUE_TEMPLATE.md -------------------------------------------------------------------------------- /.github/PULL_REQUEST_TEMPLATE.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/.github/PULL_REQUEST_TEMPLATE.md -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | *.dump 3 | target 4 | *.out 5 | lib 6 | *# 7 | *~ 8 | .nfs* 9 | -------------------------------------------------------------------------------- /CHIPYARD.hash: -------------------------------------------------------------------------------- 1 | 4180463d52bc0a6b4c004530601ccdabebf0ab7d 2 | -------------------------------------------------------------------------------- /CONTRIB_AND_STYLE.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/CONTRIB_AND_STYLE.md -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/LICENSE -------------------------------------------------------------------------------- /LICENSE.HardFloat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/LICENSE.HardFloat -------------------------------------------------------------------------------- /LICENSE.OVI: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/LICENSE.OVI -------------------------------------------------------------------------------- /LICENSE.SiFive: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/LICENSE.SiFive -------------------------------------------------------------------------------- /LICENSE.TT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/LICENSE.TT -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/Makefile -------------------------------------------------------------------------------- /README-TT.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/README-TT.md -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/README.md -------------------------------------------------------------------------------- /TODO.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/TODO.md -------------------------------------------------------------------------------- /chipstack_artifacts/app_state/0.59.3/latest.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/chipstack_artifacts/app_state/0.59.3/latest.json -------------------------------------------------------------------------------- /compare_files.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/compare_files.sh -------------------------------------------------------------------------------- /docs/.gitignore: -------------------------------------------------------------------------------- 1 | _build 2 | -------------------------------------------------------------------------------- /docs/Bobcat_Final_Presentation.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/Bobcat_Final_Presentation.pdf -------------------------------------------------------------------------------- /docs/Bobtail-Final-Presentation.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/Bobtail-Final-Presentation.pdf -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/Makefile -------------------------------------------------------------------------------- /docs/conf.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/conf.py -------------------------------------------------------------------------------- /docs/figures/1w-rrd-bypass-pipeline.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/1w-rrd-bypass-pipeline.pdf -------------------------------------------------------------------------------- /docs/figures/1w-rrd-bypass-pipeline.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/1w-rrd-bypass-pipeline.png -------------------------------------------------------------------------------- /docs/figures/2bc-fsm.svg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/2bc-fsm.svg -------------------------------------------------------------------------------- /docs/figures/2bc-prediction.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/2bc-prediction.pdf -------------------------------------------------------------------------------- /docs/figures/2bc-prediction.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/2bc-prediction.png -------------------------------------------------------------------------------- /docs/figures/abstract-functional-unit.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/abstract-functional-unit.pdf -------------------------------------------------------------------------------- /docs/figures/abstract-functional-unit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/abstract-functional-unit.png -------------------------------------------------------------------------------- /docs/figures/boom-pipeline-detailed.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/boom-pipeline-detailed.png -------------------------------------------------------------------------------- /docs/figures/boom-pipeline.svg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/boom-pipeline.svg -------------------------------------------------------------------------------- /docs/figures/bpd.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/bpd.pdf -------------------------------------------------------------------------------- /docs/figures/bpd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/bpd.png -------------------------------------------------------------------------------- /docs/figures/br-prediction-pipeline.svg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/br-prediction-pipeline.svg -------------------------------------------------------------------------------- /docs/figures/btb.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/btb.pdf -------------------------------------------------------------------------------- /docs/figures/btb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/btb.png -------------------------------------------------------------------------------- /docs/figures/chip.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/chip.pdf -------------------------------------------------------------------------------- /docs/figures/chip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/chip.png -------------------------------------------------------------------------------- /docs/figures/evolution.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/evolution.png -------------------------------------------------------------------------------- /docs/figures/execution-pipeline-2w.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/execution-pipeline-2w.pdf -------------------------------------------------------------------------------- /docs/figures/execution-pipeline-2w.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/execution-pipeline-2w.png -------------------------------------------------------------------------------- /docs/figures/execution-unit.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/execution-unit.pdf -------------------------------------------------------------------------------- /docs/figures/execution-unit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/execution-unit.png -------------------------------------------------------------------------------- /docs/figures/front-end.svg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/front-end.svg -------------------------------------------------------------------------------- /docs/figures/functional-unit-fpu.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/functional-unit-fpu.pdf -------------------------------------------------------------------------------- /docs/figures/functional-unit-fpu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/functional-unit-fpu.png -------------------------------------------------------------------------------- /docs/figures/functional-unit-hierarchy.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/functional-unit-hierarchy.pdf -------------------------------------------------------------------------------- /docs/figures/functional-unit-hierarchy.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/functional-unit-hierarchy.png -------------------------------------------------------------------------------- /docs/figures/gshare.svg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/gshare.svg -------------------------------------------------------------------------------- /docs/figures/issue_slot.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/issue_slot.pdf -------------------------------------------------------------------------------- /docs/figures/issue_slot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/issue_slot.png -------------------------------------------------------------------------------- /docs/figures/lsu.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/lsu.pdf -------------------------------------------------------------------------------- /docs/figures/lsu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/lsu.png -------------------------------------------------------------------------------- /docs/figures/prf-and-arf.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/prf-and-arf.pdf -------------------------------------------------------------------------------- /docs/figures/prf-and-arf.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/prf-and-arf.png -------------------------------------------------------------------------------- /docs/figures/proj_bobtail/Bobtail_architecture.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/proj_bobtail/Bobtail_architecture.png -------------------------------------------------------------------------------- /docs/figures/proj_bobtail/Bobtail_architecture.svg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/proj_bobtail/Bobtail_architecture.svg -------------------------------------------------------------------------------- /docs/figures/rename-pipeline.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rename-pipeline.pdf -------------------------------------------------------------------------------- /docs/figures/rename-pipeline.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rename-pipeline.png -------------------------------------------------------------------------------- /docs/figures/rob.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rob.pdf -------------------------------------------------------------------------------- /docs/figures/rob.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rob.png -------------------------------------------------------------------------------- /docs/figures/rvv/Bobcat_Design_Overview_Simplified.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/Bobcat_Design_Overview_Simplified.png -------------------------------------------------------------------------------- /docs/figures/rvv/Bobcat_Design_VPU.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/Bobcat_Design_VPU.png -------------------------------------------------------------------------------- /docs/figures/rvv/VFP_EX_Unit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/VFP_EX_Unit.png -------------------------------------------------------------------------------- /docs/figures/rvv/VFP_Encoder_256b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/VFP_Encoder_256b.png -------------------------------------------------------------------------------- /docs/figures/rvv/VFP_Encoder_Lane.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/VFP_Encoder_Lane.png -------------------------------------------------------------------------------- /docs/figures/rvv/VFP_Lane.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/VFP_Lane.png -------------------------------------------------------------------------------- /docs/figures/rvv/VFP_Scalar_Unit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/VFP_Scalar_Unit.png -------------------------------------------------------------------------------- /docs/figures/rvv/VFP_Unit_Overview.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/rvv/VFP_Unit_Overview.png -------------------------------------------------------------------------------- /docs/figures/tage.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/tage.pdf -------------------------------------------------------------------------------- /docs/figures/tage.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/tage.png -------------------------------------------------------------------------------- /docs/figures/uarch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/figures/uarch.png -------------------------------------------------------------------------------- /docs/index.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/index.rst -------------------------------------------------------------------------------- /docs/pdf_to_png.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/pdf_to_png.sh -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/requirements.txt -------------------------------------------------------------------------------- /docs/sections/bibliography/bibliography.bib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/bibliography/bibliography.bib -------------------------------------------------------------------------------- /docs/sections/boom-ecosystem.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/boom-ecosystem.rst -------------------------------------------------------------------------------- /docs/sections/branch-prediction/backing-predictor.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/branch-prediction/backing-predictor.rst -------------------------------------------------------------------------------- /docs/sections/branch-prediction/index.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/branch-prediction/index.rst -------------------------------------------------------------------------------- /docs/sections/branch-prediction/nl-predictor.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/branch-prediction/nl-predictor.rst -------------------------------------------------------------------------------- /docs/sections/debugging.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/debugging.rst -------------------------------------------------------------------------------- /docs/sections/decode-stage.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/decode-stage.rst -------------------------------------------------------------------------------- /docs/sections/execution-stages.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/execution-stages.rst -------------------------------------------------------------------------------- /docs/sections/faq.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/faq.rst -------------------------------------------------------------------------------- /docs/sections/future-work.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/future-work.rst -------------------------------------------------------------------------------- /docs/sections/instruction-fetch-stage.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/instruction-fetch-stage.rst -------------------------------------------------------------------------------- /docs/sections/intro-overview/boom-pipeline.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/intro-overview/boom-pipeline.rst -------------------------------------------------------------------------------- /docs/sections/intro-overview/boom.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/intro-overview/boom.rst -------------------------------------------------------------------------------- /docs/sections/intro-overview/chisel.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/intro-overview/chisel.rst -------------------------------------------------------------------------------- /docs/sections/intro-overview/riscv-isa.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/intro-overview/riscv-isa.rst -------------------------------------------------------------------------------- /docs/sections/intro-overview/rocket-chip.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/intro-overview/rocket-chip.rst -------------------------------------------------------------------------------- /docs/sections/issue-units.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/issue-units.rst -------------------------------------------------------------------------------- /docs/sections/load-store-unit.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/load-store-unit.rst -------------------------------------------------------------------------------- /docs/sections/memory-system.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/memory-system.rst -------------------------------------------------------------------------------- /docs/sections/parameterization.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/parameterization.rst -------------------------------------------------------------------------------- /docs/sections/physical-realization.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/physical-realization.rst -------------------------------------------------------------------------------- /docs/sections/reg-file-bypass-network.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/reg-file-bypass-network.rst -------------------------------------------------------------------------------- /docs/sections/rename-stage.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/rename-stage.rst -------------------------------------------------------------------------------- /docs/sections/reorder-buffer.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/reorder-buffer.rst -------------------------------------------------------------------------------- /docs/sections/terminology.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/terminology.rst -------------------------------------------------------------------------------- /docs/sections/uarch-counters.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/uarch-counters.rst -------------------------------------------------------------------------------- /docs/sections/verification.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/docs/sections/verification.rst -------------------------------------------------------------------------------- /filecomp.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/filecomp.txt -------------------------------------------------------------------------------- /lsu_prev.temp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/lsu_prev.temp -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.3.13 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/project/plugins.sbt -------------------------------------------------------------------------------- /scalastyle-config.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/scalastyle-config.xml -------------------------------------------------------------------------------- /src/main/resources/bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/bootrom/Makefile -------------------------------------------------------------------------------- /src/main/resources/bootrom/bootrom.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/bootrom/bootrom.S -------------------------------------------------------------------------------- /src/main/resources/bootrom/bootrom.rv32.img: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/bootrom/bootrom.rv32.img -------------------------------------------------------------------------------- /src/main/resources/bootrom/bootrom.rv64.img: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/bootrom/bootrom.rv64.img -------------------------------------------------------------------------------- /src/main/resources/bootrom/linker.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/bootrom/linker.ld -------------------------------------------------------------------------------- /src/main/resources/csrc/btb_sw.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/csrc/btb_sw.cc -------------------------------------------------------------------------------- /src/main/resources/csrc/predictor_sw.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/csrc/predictor_sw.cc -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/COPYING.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/COPYING.txt -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/README.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/README.html -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/README.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/README.txt -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/doc/HardFloat-Verilog.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/doc/HardFloat-Verilog.html -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/doc/HardFloat-test-Verilator.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/doc/HardFloat-test-Verilator.html -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/doc/HardFloat-test-Verilog.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/doc/HardFloat-test-Verilog.html -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/8086-SSE/HardFloat_specialize.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/8086-SSE/HardFloat_specialize.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/8086-SSE/HardFloat_specialize.vi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/8086-SSE/HardFloat_specialize.vi -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/ARM-VFPv2/HardFloat_specialize.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/ARM-VFPv2/HardFloat_specialize.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/ARM-VFPv2/HardFloat_specialize.vi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/ARM-VFPv2/HardFloat_specialize.vi -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/HardFloat_consts.vi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/HardFloat_consts.vi -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/HardFloat_localFuncs.vi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/HardFloat_localFuncs.vi -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/HardFloat_primitives.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/HardFloat_primitives.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/HardFloat_rawFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/HardFloat_rawFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/RISCV/HardFloat_specialize.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/RISCV/HardFloat_specialize.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/RISCV/HardFloat_specialize.vi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/RISCV/HardFloat_specialize.vi -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/addRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/addRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/compareRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/compareRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/divSqrtRecFN_small.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/divSqrtRecFN_small.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/fNToRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/fNToRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/iNToRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/iNToRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/isSigNaNRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/isSigNaNRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/mulAddRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/mulAddRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/mulRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/mulRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/recFNToFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/recFNToFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/recFNToIN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/recFNToIN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/source/recFNToRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/source/recFNToRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/build/IcarusVerilog/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/build/IcarusVerilog/Makefile -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/build/IcarusVerilog/config.make: -------------------------------------------------------------------------------- 1 | 2 | SPECIALIZE_TYPE ?= 8086-SSE 3 | 4 | -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/build/Verilator-GCC/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/build/Verilator-GCC/Makefile -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/build/Verilator-GCC/config.h: -------------------------------------------------------------------------------- 1 | 2 | enum { maxNumErrors = 20 }; 3 | 4 | -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/build/Verilator-GCC/config.make: -------------------------------------------------------------------------------- 1 | 2 | SPECIALIZE_TYPE ?= 8086-SSE 3 | 4 | -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/testCommon.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/testCommon.c -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/testCommon.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/testCommon.h -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_abz_recF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_compareRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF128_small_div.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF128_small_div.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF128_small_sqrt.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF128_small_sqrt.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF16_small_div.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF16_small_div.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF16_small_sqrt.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF16_small_sqrt.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF32_small_div.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF32_small_div.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF32_small_sqrt.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF32_small_sqrt.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF64_small_div.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF64_small_div.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF64_small_sqrt.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_divSqrtRecF64_small_sqrt.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f128ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f128ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f16ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f16ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f32ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f32ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f64ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_f64ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i32ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_i64ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_mulAddRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToI32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToI32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToI64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToI64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToUi32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToUi32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToUi64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF128ToUi64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToI32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToI32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToI64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToI64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToUi32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToUi32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToUi64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF16ToUi64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToI32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToI32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToI64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToI64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToUi32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToUi32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToUi64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF32ToUi64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToI32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToI32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToI64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToI64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToUi32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToUi32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToUi64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_recF64ToUi64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui32ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF128.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF128.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF16.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF16.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF32.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF32.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF64.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/Verilator/test_ui64ToRecF64.cpp -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/addRecFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/addRecFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/compareRecFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/compareRecFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/divSqrtRecFN_small_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/divSqrtRecFN_small_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/fNToRecFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/fNToRecFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/finish_fail-IcarusVerilog.vi: -------------------------------------------------------------------------------- 1 | 2 | `define finish_fail $stop 3 | 4 | -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/iNToRecFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/iNToRecFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/mulAddRecFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/mulAddRecFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/mulRecFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/mulRecFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/recFNToFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/recFNToFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/recFNToIN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/recFNToIN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/recFNToRecFN_spec.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/recFNToRecFN_spec.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/sameRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/sameRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_addRecFN_add.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_addRecFN_add.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_addRecFN_sub.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_addRecFN_sub.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_compareRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_compareRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_divSqrtRecFN_small_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_divSqrtRecFN_small_div.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_divSqrtRecFN_small_sqrt.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_divSqrtRecFN_small_sqrt.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_iNToRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_iNToRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_mulAddRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_mulAddRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_mulAddRecFN_add.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_mulAddRecFN_add.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_mulAddRecFN_mul.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_mulAddRecFN_mul.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_mulRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_mulRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_recFNToFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_recFNToFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_recFNToIN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_recFNToIN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/HardFloat/test/source/test_recFNToRecFN.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/HardFloat/test/source/test_recFNToRecFN.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/btb_harness.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/btb_harness.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness_interface.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness_interface.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness_wrapper_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness_wrapper_1.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness_wrapper_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness_wrapper_2.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness_wrapper_3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness_wrapper_3.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness_wrapper_4.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness_wrapper_4.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness_wrapper_6.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness_wrapper_6.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/core_harness_wrapper_8.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/core_harness_wrapper_8.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/predictor_harness.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/predictor_harness.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/VecFP16rec7.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/VecFP16rec7.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/VecFP16rsqrt7.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/VecFP16rsqrt7.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/VecFP32rec7.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/VecFP32rec7.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/VecFP32rsqrt7.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/VecFP32rsqrt7.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/autogen_defines.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/autogen_defines.h -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/autogen_riscv_imabfv.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/autogen_riscv_imabfv.v -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/briscv_defines.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/briscv_defines.h -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/lrm.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/lrm.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/lrm.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/lrm.tcl -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/lrm_assertions.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/lrm_assertions.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/lrm_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/lrm_model.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_ascii_instrn_decode.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_ascii_instrn_decode.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_briscv_pkg.svh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_briscv_pkg.svh -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_cam_buffer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_cam_buffer.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_compare.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_compare.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_decoded_mux.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_decoded_mux.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_decoder.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_decoder.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_ex.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_ex.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_ffs.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_ffs.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_fifo.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_fifo.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_fifo_assert.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_fifo_assert.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_fp16_div.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_fp16_div.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_fp32_div.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_fp32_div.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_id.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_id.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_idxldst_fsm.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_idxldst_fsm.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_int_div_r2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_int_div_r2.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_int_div_simple.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_int_div_simple.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_lq.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_lq.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_mask_fsm.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_mask_fsm.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_mem.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_mem.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_memop_fsm.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_memop_fsm.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_pipe_stage.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_pipe_stage.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_popcnt.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_popcnt.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_reshape.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_reshape.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_rts_rtr_pipe_stage.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_rts_rtr_pipe_stage.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_scoreboard_ovi.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_scoreboard_ovi.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_skid_buffer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_skid_buffer.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_store_buffer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_store_buffer.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vec.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vec.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vec_div_unit.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vec_div_unit.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vec_iadd.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vec_iadd.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vec_idp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vec_idp.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vec_imul.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vec_imul.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vec_mul_dp.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vec_mul_dp.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vec_regfile.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vec_regfile.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vfp_encoder.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vfp_encoder.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vfp_encoder_lane.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vfp_encoder_lane.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vfp_ex_unit.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vfp_ex_unit.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vfp_fma.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vfp_fma.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vfp_lane.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vfp_lane.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vfp_red.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vfp_red.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vfp_unit.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vfp_unit.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vpu_ovi.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vpu_ovi.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/tt_vpu_ovi_assert.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/tt_vpu_ovi_assert.sv -------------------------------------------------------------------------------- /src/main/resources/vsrc/vpu/vpu.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/resources/vsrc/vpu/vpu.tcl -------------------------------------------------------------------------------- /src/main/scala/common/config-mixins.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/common/config-mixins.scala -------------------------------------------------------------------------------- /src/main/scala/common/consts.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/common/consts.scala -------------------------------------------------------------------------------- /src/main/scala/common/micro-op.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/common/micro-op.scala -------------------------------------------------------------------------------- /src/main/scala/common/package.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/common/package.scala -------------------------------------------------------------------------------- /src/main/scala/common/parameters.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/common/parameters.scala -------------------------------------------------------------------------------- /src/main/scala/common/tile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/common/tile.scala -------------------------------------------------------------------------------- /src/main/scala/common/types.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/common/types.scala -------------------------------------------------------------------------------- /src/main/scala/exu/core.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/core.scala -------------------------------------------------------------------------------- /src/main/scala/exu/decode.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/decode.scala -------------------------------------------------------------------------------- /src/main/scala/exu/dispatch.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/dispatch.scala -------------------------------------------------------------------------------- /src/main/scala/exu/execution-units/execution-unit.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/execution-units/execution-unit.scala -------------------------------------------------------------------------------- /src/main/scala/exu/execution-units/execution-units.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/execution-units/execution-units.scala -------------------------------------------------------------------------------- /src/main/scala/exu/execution-units/fdiv.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/execution-units/fdiv.scala -------------------------------------------------------------------------------- /src/main/scala/exu/execution-units/fpu.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/execution-units/fpu.scala -------------------------------------------------------------------------------- /src/main/scala/exu/execution-units/functional-unit.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/execution-units/functional-unit.scala -------------------------------------------------------------------------------- /src/main/scala/exu/execution-units/ovi.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/execution-units/ovi.scala -------------------------------------------------------------------------------- /src/main/scala/exu/execution-units/rocc.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/execution-units/rocc.scala -------------------------------------------------------------------------------- /src/main/scala/exu/fp-pipeline.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/fp-pipeline.scala -------------------------------------------------------------------------------- /src/main/scala/exu/issue-units/issue-slot.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/issue-units/issue-slot.scala -------------------------------------------------------------------------------- /src/main/scala/exu/issue-units/issue-unit-age-ordered.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/issue-units/issue-unit-age-ordered.scala -------------------------------------------------------------------------------- /src/main/scala/exu/issue-units/issue-unit-ordered.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/issue-units/issue-unit-ordered.scala -------------------------------------------------------------------------------- /src/main/scala/exu/issue-units/issue-unit-unordered.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/issue-units/issue-unit-unordered.scala -------------------------------------------------------------------------------- /src/main/scala/exu/issue-units/issue-unit.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/issue-units/issue-unit.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/ls_decode.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/ls_decode.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/loadgen.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/loadgen.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/loadpacker.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/loadpacker.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/loadskipper.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/loadskipper.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/loadwalker.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/loadwalker.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/storegen.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/storegen.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/storepacker.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/storepacker.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/storeskipper.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/storeskipper.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/lsgen/storewalker.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/lsgen/storewalker.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/mask_idx_buff.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/mask_idx_buff.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/ovi.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/ovi.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/ovi_sb.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/ovi_sb.scala -------------------------------------------------------------------------------- /src/main/scala/exu/ovi_wrapper/vdb.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/ovi_wrapper/vdb.scala -------------------------------------------------------------------------------- /src/main/scala/exu/register-read/func-unit-decode.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/register-read/func-unit-decode.scala -------------------------------------------------------------------------------- /src/main/scala/exu/register-read/regfile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/register-read/regfile.scala -------------------------------------------------------------------------------- /src/main/scala/exu/register-read/register-read.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/register-read/register-read.scala -------------------------------------------------------------------------------- /src/main/scala/exu/rename/rename-busytable.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/rename/rename-busytable.scala -------------------------------------------------------------------------------- /src/main/scala/exu/rename/rename-freelist.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/rename/rename-freelist.scala -------------------------------------------------------------------------------- /src/main/scala/exu/rename/rename-maptable.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/rename/rename-maptable.scala -------------------------------------------------------------------------------- /src/main/scala/exu/rename/rename-stage.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/rename/rename-stage.scala -------------------------------------------------------------------------------- /src/main/scala/exu/rob.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/exu/rob.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/bim.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/bim.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/btb.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/btb.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/composer.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/composer.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/faubtb.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/faubtb.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/hbim.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/hbim.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/local.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/local.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/loop.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/loop.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/predictor.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/predictor.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/ras.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/ras.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/sw_predictor.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/sw_predictor.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/tage.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/tage.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/tourney.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/tourney.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/bpd/ubtb.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/bpd/ubtb.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/fetch-buffer.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/fetch-buffer.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/fetch-target-queue.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/fetch-target-queue.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/frontend.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/frontend.scala -------------------------------------------------------------------------------- /src/main/scala/ifu/icache.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/ifu/icache.scala -------------------------------------------------------------------------------- /src/main/scala/lsu/dcache.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/lsu/dcache.scala -------------------------------------------------------------------------------- /src/main/scala/lsu/lsu.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/lsu/lsu.scala -------------------------------------------------------------------------------- /src/main/scala/lsu/mshrs.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/lsu/mshrs.scala -------------------------------------------------------------------------------- /src/main/scala/lsu/prefetcher.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/lsu/prefetcher.scala -------------------------------------------------------------------------------- /src/main/scala/lsu/tlb.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/lsu/tlb.scala -------------------------------------------------------------------------------- /src/main/scala/lsu/tracegen.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/lsu/tracegen.scala -------------------------------------------------------------------------------- /src/main/scala/util/elastic-reg.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/util/elastic-reg.scala -------------------------------------------------------------------------------- /src/main/scala/util/elastic-sram.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/util/elastic-sram.scala -------------------------------------------------------------------------------- /src/main/scala/util/seqmem-transformable.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/util/seqmem-transformable.scala -------------------------------------------------------------------------------- /src/main/scala/util/util.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/main/scala/util/util.scala -------------------------------------------------------------------------------- /src/test/scala/RegFileTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/test/scala/RegFileTest.scala -------------------------------------------------------------------------------- /src/test/scala/TestUtils.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/src/test/scala/TestUtils.scala -------------------------------------------------------------------------------- /util/branch-processor.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/branch-processor.py -------------------------------------------------------------------------------- /util/csmith/install-csmith.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/csmith/install-csmith.sh -------------------------------------------------------------------------------- /util/csmith/run-csmith.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/csmith/run-csmith.sh -------------------------------------------------------------------------------- /util/csmith/sources/crt.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/csmith/sources/crt.S -------------------------------------------------------------------------------- /util/csmith/sources/encoding.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/csmith/sources/encoding.h -------------------------------------------------------------------------------- /util/csmith/sources/link.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/csmith/sources/link.ld -------------------------------------------------------------------------------- /util/csmith/sources/syscalls.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/csmith/sources/syscalls.c -------------------------------------------------------------------------------- /util/csmith/sources/util.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/csmith/sources/util.h -------------------------------------------------------------------------------- /util/memtracer/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/memtracer/Makefile -------------------------------------------------------------------------------- /util/memtracer/memtracer.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/memtracer/memtracer.c -------------------------------------------------------------------------------- /util/pipeview-helper.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tenstorrent/riscv-ocelot/HEAD/util/pipeview-helper.py --------------------------------------------------------------------------------