├── boards ├── tf330r1 │ ├── Makefile │ ├── tf330r1.xise │ ├── tf330r1_main.ucf │ └── tf330r1_main_top.v ├── tf330r2 │ ├── Makefile │ ├── tf330r2_main_top.v │ └── tf330r2_main.ucf ├── tf330r3 │ ├── Makefile │ ├── tf330r3_main.ucf │ └── tf330r3_main_top.v ├── tf1230r1 │ ├── Makefile │ ├── tf1230r1_main.ucf │ └── tf1230r1_main_top.v ├── Makefile ├── Makefile.inc ├── validate.py └── Makefile.cpld ├── rtl ├── arb.v ├── clocks.v ├── mkzorro ├── sdram_defines.v ├── autoconfig.v ├── sdram_init.v ├── ata.v ├── gayle.v ├── fastata.v ├── main_top.v └── sdram.v ├── README.md └── LICENSE /boards/tf330r1/Makefile: -------------------------------------------------------------------------------- 1 | REVISION=1 2 | BOARD:=tf330 3 | all: $(BOARD)r$(REVISION) 4 | 5 | include ../Makefile.inc -------------------------------------------------------------------------------- /boards/tf330r2/Makefile: -------------------------------------------------------------------------------- 1 | REVISION=2 2 | BOARD:=tf330 3 | SERIALNO?=330 4 | all: $(BOARD)r$(REVISION) 5 | 6 | include ../Makefile.inc -------------------------------------------------------------------------------- /boards/tf330r3/Makefile: -------------------------------------------------------------------------------- 1 | REVISION=3 2 | BOARD:=tf330 3 | SERIALNO?=330 4 | all: $(BOARD)r$(REVISION) 5 | 6 | include ../Makefile.inc -------------------------------------------------------------------------------- /boards/tf1230r1/Makefile: -------------------------------------------------------------------------------- 1 | REVISION=1 2 | BOARD:=tf1230 3 | SERIALNO?=1230 4 | TARGET?=A1200 5 | all: $(BOARD)r$(REVISION) 6 | 7 | include ../Makefile.inc 8 | -------------------------------------------------------------------------------- /boards/Makefile: -------------------------------------------------------------------------------- 1 | PREFIX:=tf330 2 | BOARDS:=$(PREFIX)r2 $(PREFIX)r3 $(PREFIX)r1 3 | .PHONY: $(BOARDS) 4 | FOLDER:=$(PREFIX)_`date +"%Y_%m_%d"` 5 | all: clean 6 | rm -rf ./$(PREFIX)_* 7 | mkdir ./$(FOLDER) 8 | @- $(foreach BOARD,$(BOARDS), make -C $(BOARD); \ 9 | cp $(BOARD)/*.jed ./$(FOLDER);) 10 | zip $(FOLDER)_alpha.zip ./$(FOLDER)/* 11 | rm -rf $(FOLDER) 12 | clean: 13 | @- $(foreach BOARD,$(BOARDS), make -C $(BOARD) clean;) 14 | distclean: 15 | @- $(foreach BOARD,$(BOARDS), make -C $(BOARD) distclean;) 16 | rm -rf $(BOARD)_20* 17 | -------------------------------------------------------------------------------- /boards/Makefile.inc: -------------------------------------------------------------------------------- 1 | RTLFOLDER=../../rtl/ 2 | SOURCES="./$(BOARD)r$(REVISION)_main_top.v $(RTLFOLDER)/main_top.v $(RTLFOLDER)/ata.v $(RTLFOLDER)/arb.v $(RTLFOLDER)/clocks.v $(RTLFOLDER)/autoconfig.v $(RTLFOLDER)/gayle.v $(RTLFOLDER)/sdram.v $(RTLFOLDER)/sdram_init.v" 3 | 4 | $(BOARD)r$(REVISION): clean $(BOARD)r$(REVISION)_main $(BOARD)r$(REVISION)_main_288 5 | $(BOARD)r$(REVISION)_main: 6 | make -f ../Makefile.cpld BOARD=$(BOARD) SOURCES=$(SOURCES) SUBPROJ=main REVISION=$(REVISION) OPTMODE=speed OPTIMISE=speed TARGET=$(TARGET) SERIALNO=$(SERIALNO) 7 | $(BOARD)r$(REVISION)_main_288: 8 | make -f ../Makefile.cpld BOARD=$(BOARD) SOURCES=$(SOURCES) SUBPROJ=main REVISION=$(REVISION) OPTMODE=speed OPTIMISE=speed TARGET=$(TARGET) SERIALNO=$(SERIALNO) PART=XC95288XL-10-TQ144 JEDEXTRA=_288 9 | 10 | zip: distclean $(BOARD)r$(REVISION) 11 | zip $(BOARD)r$(REVISION)_`date +"%Y_%m_%d"`_alpha.zip *.jed 12 | clean: 13 | rm -rf work _xmsgs *.zip 14 | validate: 15 | ../validate.py --board=$(BOARD) --rev=$(REVISION) --chip=main 16 | distclean: clean 17 | rm -f *.jed *~ *.svf -------------------------------------------------------------------------------- /rtl/arb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | Copyright (C) 2019, Stephen J. Leary 4 | All rights reserved. 5 | 6 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 7 | 8 | Attribution-NoDerivs 3.0 Unported 9 | 10 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 11 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 12 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 13 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 14 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 15 | DAMAGES RESULTING FROM ITS USE. 16 | 17 | */ 18 | 19 | module arb( 20 | 21 | input CLK, 22 | input CLK100M, 23 | input DISABLE, 24 | 25 | input AS30, 26 | 27 | // 020 ARB 28 | output BR20, 29 | input BG20, 30 | 31 | // 030 ARB 32 | output reg BR30, 33 | output reg BGACK30, 34 | input BG30, 35 | 36 | // AKIKO ARB 37 | input EXP_BR, 38 | output EXP_BG 39 | 40 | ); 41 | 42 | reg BGACK_INT; 43 | 44 | always @(posedge CLK) begin 45 | 46 | BGACK_INT <= ((BG30 | ~AS30) & (BGACK_INT | EXP_BR) | EXP_BR) & ~DISABLE; 47 | 48 | end 49 | 50 | always @(posedge CLK100M) begin 51 | 52 | BR30 <= EXP_BR & ~DISABLE; 53 | BGACK30 <= BGACK_INT; 54 | 55 | end 56 | 57 | assign BR20 = DISABLE; 58 | assign EXP_BG = DISABLE ? 1'bz : BGACK_INT; 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /rtl/clocks.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | Copyright (C) 2016-2017, Stephen J. Leary 4 | All rights reserved. 5 | 6 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 7 | 8 | Attribution-NoDerivs 3.0 Unported 9 | 10 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 11 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 12 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 13 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 14 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 15 | DAMAGES RESULTING FROM ITS USE. 16 | 17 | */ 18 | 19 | 20 | module clocks( 21 | input CLK100M, 22 | input CLK14M, 23 | input SPEED, 24 | output CLKCPU 25 | ); 26 | 27 | localparam CLOCK_SMOOTHING = 2; 28 | localparam CLOCK_SMOOTH = 10; 29 | 30 | reg CLK50MI; 31 | reg [4:0] CLK14M_D; 32 | reg [CLOCK_SMOOTH:0] SPEED_D; 33 | 34 | wire can_change = (&CLK14M_D[CLOCK_SMOOTHING:0] == 1'b1) || (|CLK14M_D[CLOCK_SMOOTHING:0] == 1'b0); 35 | 36 | always @(posedge CLK100M) begin 37 | 38 | SPEED_D <= {SPEED_D[CLOCK_SMOOTH-1:0], SPEED}; 39 | 40 | if (can_change == 1) begin 41 | CLK14M_D <= {CLK14M_D[3:0], ~CLK14M}; 42 | end else begin 43 | CLK14M_D <= {CLK14M_D[3:0], CLK14M_D[0]}; 44 | end 45 | 46 | if (SPEED) begin 47 | CLK50MI <= CLK14M_D[2] & (&SPEED_D); 48 | end else begin 49 | CLK50MI <= ~CLK50MI; 50 | end 51 | 52 | end 53 | 54 | assign CLKCPU = CLK50MI; 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /rtl/mkzorro: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | address = 0 4 | default = 0xF 5 | 6 | def outNybble(x): 7 | global address 8 | global default 9 | if (address >= 2): 10 | x = ~x & 0xF 11 | if (x != default): 12 | print "'h%02x: data_out[7:4] <= 4'h%x;" % (address, x & 0x0F) 13 | address+=1 14 | 15 | def outByte(x): 16 | outNybble(x >> 4) 17 | outNybble(x & 0x0F) 18 | 19 | def outShort(x): 20 | outByte(x >> 8) 21 | outByte(x & 0xFF) 22 | 23 | def outLong(x): 24 | outShort(x >> 16) 25 | outShort(x & 0xFFFF) 26 | 27 | rom = "0xE6 0x51 0x80 0x00 0x07 0xDB 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00" 28 | 29 | memavailable = 0x20 30 | related_to_next = 0x08; 31 | versions = {"Z2": 0xC0, "Z3": 0x80} 32 | sizes = {"64K": 0x01, "128K": 0x02, "256K": 0x03, "512K": 0x04, "1M": 0x05, "2M": 0x06, "4M": 0x07, "8M": 0x00} 33 | extended_sizes = {"16M": 0x00, "32M": 0x01, "64M": 0x02, "128M": 0x03, "256M": 0x04, "512M": 0x05, "1G": 0x06} 34 | 35 | eFlags = 0x80 36 | eManuID = 5080 37 | eSerial = 330 38 | eRomVector = 0 39 | 40 | def ramConfig(size): 41 | global address 42 | address = 0 43 | eType = 0xa4 44 | eProduct = 0x01 45 | eFlags = 0xb1 46 | print "case (zaddr)" 47 | outByte(eType) 48 | outByte(eProduct) 49 | outByte(eFlags) 50 | outByte(0x00) #reserved 51 | outShort(eManuID) 52 | outLong(eSerial) 53 | outShort(eRomVector) 54 | outLong(0x00) #reserved 55 | print "default: data_out[7:4] <= 4'h%x;" % (default) 56 | print "endcase" 57 | 58 | 59 | def sdCardConfig(): 60 | global address 61 | address = 0 62 | eType = versions["Z2"] | sizes["64K"] 63 | eProduct = 0x81 64 | print "case (zaddr)" 65 | outByte(eType) 66 | outByte(eProduct) 67 | outByte(eFlags) 68 | outByte(0x00) #reserved 69 | outShort(eManuID) 70 | outLong(eSerial) 71 | outShort(eRomVector) 72 | outLong(0x00) #reserved 73 | print "default: data_out[7:4] <= 4'h%x;" % (default) 74 | print "endcase" 75 | 76 | 77 | ramConfig("256M") 78 | #sdCardConfig() 79 | -------------------------------------------------------------------------------- /rtl/sdram_defines.v: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2013-2021, Stephen J. Leary 3 | All rights reserved. 4 | 5 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 6 | 7 | Attribution-NoDerivs 3.0 Unported 8 | 9 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 10 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 11 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 12 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 13 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 14 | DAMAGES RESULTING FROM ITS USE. 15 | 16 | */ 17 | 18 | localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@100MHz 19 | localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8, 111 = continuous. 20 | localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved 21 | localparam CAS_LATENCY = 3'd2; // 2/3 allowed 22 | localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed 23 | localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write 24 | localparam WRITE_BURST = 1'b0; // 0= write burst enabled, 1=only single access write 25 | localparam RFC_DELAY = 4'd6; // tRFC=66ns -> 6 cycles@100MHz 26 | localparam RP_DELAY = 'd4; 27 | 28 | // all possible commands 29 | localparam CMD_INHIBIT = 4'b1111; 30 | localparam CMD_NOP = 4'b0111; 31 | localparam CMD_ACTIVE = 4'b0011; 32 | localparam CMD_READ = 4'b0101; 33 | localparam CMD_WRITE = 4'b0100; 34 | localparam CMD_BURST_TERMINATE = 4'b0110; 35 | localparam CMD_PRECHARGE = 4'b0010; 36 | localparam CMD_AUTO_REFRESH = 4'b0001; 37 | localparam CMD_LOAD_MODE = 4'b0000; 38 | 39 | // ======================================================== 40 | // Convert cmd into ascii name 41 | // ======================================================== 42 | function [(12*8)-1:0] cmd_name; 43 | input [3:0] cmd; 44 | begin 45 | cmd_name = 46 | cmd == CMD_INHIBIT ? "CMD_INHIBIT " : 47 | cmd == CMD_NOP ? "CMD_NOP " : 48 | cmd == CMD_ACTIVE ? "CMD_ACTIVE " : 49 | cmd == CMD_READ ? "CMD_READ " : 50 | cmd == CMD_WRITE ? "CMD_WRITE " : 51 | cmd == CMD_BURST_TERMINATE ? "CMD_BRSTTERM" : 52 | cmd == CMD_PRECHARGE ? "CMD_PRECHRGE" : 53 | cmd == CMD_AUTO_REFRESH ? "CMD_AREFRESH" : 54 | cmd == CMD_LOAD_MODE ? "CMD_LOAD_MDE" : 55 | "UNKNOWN "; 56 | end 57 | endfunction 58 | -------------------------------------------------------------------------------- /boards/validate.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import argparse 4 | 5 | def parsePins(f): 6 | pins = {} 7 | for line in f: 8 | tokens = line.split() 9 | if len(tokens) == 2 and tokens[1].startswith("S:PIN"): 10 | pin = tokens[1][5:] 11 | pins[pin] = tokens[0] 12 | return pins 13 | 14 | def parseUcf(f): 15 | pins = {} 16 | for line in f: 17 | if line.startswith('NET'): 18 | line = line.replace('"','').replace(";","") 19 | tokens = line.split() 20 | # remove the leading NET 21 | tokens = tokens[1:] 22 | for item in tokens[1:]: 23 | if item.lower().startswith('loc'): 24 | pin=item[4:] 25 | pins[pin] = tokens[0] 26 | return pins 27 | 28 | def validateCpld(CHIP="bus", REV="2", BOARD="tf534"): 29 | valid = True 30 | PINFILE="""work/{board}r{rev}_{chip}_top.gyd""".format(board=BOARD,rev=REV,chip=CHIP) 31 | UCFFILE="""./{board}r{rev}_{chip}.ucf""".format(board=BOARD,rev=REV,chip=CHIP) 32 | 33 | print "Parsing Pinfreeze File:",PINFILE,"....", 34 | with open(PINFILE) as f: 35 | pins = parsePins(f) 36 | print "Done" 37 | 38 | print "Parsing UCF File",UCFFILE,"....", 39 | with open(UCFFILE) as f: 40 | locs = parseUcf(f) 41 | print "Done" 42 | 43 | print "Comparing pincounts...", 44 | 45 | if len(pins) != len(locs): 46 | print "Mismatch!" 47 | valid = False 48 | else: 49 | print "Done" 50 | 51 | for pin in pins.keys(): 52 | 53 | try: 54 | print "Checking pin", pin, "PIN:", pins[pin], "UCF:",locs[pin], 55 | if locs[pin] == pins[pin]: 56 | print "Correct" 57 | else: 58 | print "Error" 59 | valid = False 60 | except KeyError: 61 | print "Error - PIN NOT IN UCF FILE!" 62 | valid = False 63 | 64 | for pin in locs.keys(): 65 | try: 66 | print "Checking pin", pin, "UCF:", locs[pin], "PIN:", pins[pin], 67 | if locs[pin] == pins[pin]: 68 | print "Correct" 69 | else: 70 | print "Error" 71 | valid = False 72 | except KeyError: 73 | valid = False 74 | print "Error - Pin not found in design" 75 | 76 | 77 | parser = argparse.ArgumentParser(description='Validate a ucf file against a pinfreeze file.') 78 | parser.add_argument('--rev', help='board revision', default='2') 79 | parser.add_argument('--chip', help='chip name', default='bus') 80 | parser.add_argument('--board', help='board version', default='tf534') 81 | args = parser.parse_args() 82 | 83 | validateCpld(args.chip, args.rev, args.board) 84 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # tf1230 2 | 3 | TF1230 source files. 4 | 5 | Released in Creative Commons CC-BY-ND license. 6 | 7 | This is a NO DERIVATIVES LICENSE. You cannot modify it and distribute the modified version. 8 | 9 | TF1230 is distributed with absolutely no warranty. If you make a mistake you could blow up your A1200. I take no responsibility for this. 10 | 11 | The TF1230 is an 030 accelerator fixed at 50Mhz with 64Mb of SDRAM (128Mb possible), and is intended to work with CF cards or IDE2SD card type devices. The IDE interface does not work with long cables. It is intended to be CHEAP Because thats pretty much all Amiga users care about. You need the ehide.device to use the onboard ide. 12 | 13 | There was a design decision to make with the TF ide. Do we make it work as the default ide device and break PCMCIA support, do we add a rom on the card (and more expense) or do we just provide a driver that you can put in a cheap rom and run that way (or just run from disk). I figured the cheapest and least invasive option was the best for a home build solution. 14 | 15 | **Before you start building :- You can buy these from Supaduper & AlenPPC (AmiBay) completely built for less than it will cost you to buy the parts and the time it will take you if you bill your time at minimum wage.** 16 | 17 | Also do not ask me to reroute the board to a different DRC so you can use your local boardhouse. I dont feel like spending 100 hours of my time to save you $10. The DRC on this board is 7-7-7 and any boardhouse that doesnt totally suck can do this. Also it 4 layer and dont ask if i can be made 2 layer. The answer is no. 18 | 19 | If you need help with this the best place to get it is the exxos forum https://www.exxoshost.co.uk/forum/ 20 | 21 | The SDRAM Controller is derived from my Archie core and the clock controller code is designed to simulate a PLL with adjustable phase. 22 | 23 | This is not an exercise in German over engineering. Its engineered to do an exact task and nothing more. You will need to do the timing fixes or put a clock buffer on the clock line on this board. I didnt do this because i believe that the timing changes are needed on Amigas and not doing them is bad for them long term. Cards that let you get away without doing it are doing you a diservice. It would be like cards letting you go longer without a recap. Its 24 | 25 | That said you are free to sell this on your webshop provided you give credit and do not vastly overprice it. However CE marking is your own issue not mine. AmigaKit may not sell this ever... anyone else can. 26 | 27 | On the other hand if you have an actual firmware bugfix send me a pull request with testing evidence. It will be appreciated greatly. 28 | 29 | For crashes please check that the crash doesnt happen in WinUAE for a A1200 with A1200 IDE and 64MB ZIII Ram before making a bug report. Most of the crashes we have seen over the years are repeatable in that environment. 30 | 31 | The purpose of this card is for you to get more enjoyment from your Amiga for very little money. Please do that. 32 | 33 | 34 | -------------------------------------------------------------------------------- /rtl/autoconfig.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | Copyright (C) 2018-2021, Stephen J. Leary 4 | All rights reserved. 5 | 6 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 7 | 8 | Attribution-NoDerivs 3.0 Unported 9 | 10 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 11 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 12 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 13 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 14 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 15 | DAMAGES RESULTING FROM ITS USE. 16 | 17 | */ 18 | 19 | 20 | module autoconfig( 21 | 22 | input RESET, 23 | input AS20, 24 | input RW20, 25 | input DS20, 26 | 27 | input [31:0] A, 28 | 29 | output [7:4] DOUT, 30 | 31 | output ACCESS, 32 | output DECODE 33 | 34 | ); 35 | 36 | reg config_out = 'd0; 37 | reg configured = 'd0; 38 | reg shutup = 'd0; 39 | reg [7:4] data_out = 'd0; 40 | 41 | // 0xE80000 42 | wire Z2_ACCESS = ({A[31:16]} != {16'h00E8}) | (&config_out); 43 | wire Z2_WRITE = (Z2_ACCESS | RW20); 44 | wire [5:0] zaddr = {A[6:1]}; 45 | 46 | always @(posedge AS20 or negedge RESET) begin 47 | 48 | if (RESET == 1'b0) begin 49 | 50 | config_out <= 'd0; 51 | 52 | end else begin 53 | 54 | config_out <= configured | shutup; 55 | 56 | end 57 | 58 | end 59 | 60 | always @(negedge DS20 or negedge RESET) begin 61 | 62 | if (RESET == 1'b0) begin 63 | 64 | configured <= 'd0; 65 | shutup <= 'd0; 66 | data_out[7:4] <= 4'hf; 67 | 68 | end else begin 69 | 70 | if (Z2_WRITE == 1'b0) begin 71 | 72 | case (zaddr) 73 | 'h22: begin //configure logic 74 | configured <= 1'b1; 75 | end 76 | 'h26: begin // shutup logic 77 | shutup <= 1'b1; 78 | end 79 | endcase 80 | 81 | end 82 | 83 | // autoconfig ROMs 84 | case (zaddr) 85 | 'h00: data_out[7:4] <= 4'ha; 86 | 'h01: data_out[7:4] <= 4'h2; 87 | 'h03: data_out[7:4] <= 4'hc; 88 | 'h04: data_out[7:4] <= 4'h4; 89 | 'h08: data_out[7:4] <= 4'he; 90 | 'h09: data_out[7:4] <= 4'hc; 91 | 'h0a: data_out[7:4] <= 4'h2; 92 | 'h0b: data_out[7:4] <= 4'h7; 93 | 'h11: data_out[7:4] <= 4'he; 94 | 'h12: data_out[7:4] <= 4'hb; 95 | 'h13: data_out[7:4] <= 4'h5; 96 | default: data_out[7:4] <= 4'hf; 97 | endcase 98 | 99 | end 100 | end 101 | 102 | // decode the base addresses 103 | // these are hardcoded to the address they always get assigned to. 104 | assign DECODE = ({A[31:26]} != {6'b0100_00}) | shutup; 105 | 106 | assign ACCESS = Z2_ACCESS; 107 | assign DOUT = data_out; 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /rtl/sdram_init.v: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (C) 2013-2021, Stephen J. Leary 3 | All rights reserved. 4 | 5 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 6 | 7 | Attribution-NoDerivs 3.0 Unported 8 | 9 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 10 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 11 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 12 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 13 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 14 | DAMAGES RESULTING FROM ITS USE. 15 | 16 | */ 17 | 18 | 19 | 20 | module sdram_init( 21 | 22 | input CLK, 23 | output reg CLKE, 24 | input RESET, 25 | output reg [3:0] CMD, 26 | output reg [12:0] ARAM, // 13 bit multiplexed address bus 27 | output reg READY, 28 | output reg [13:0] COUNTER, // single counter used to save space 29 | output reg REFRESH 30 | 31 | ); 32 | 33 | `include "sdram_defines.v" 34 | 35 | initial begin 36 | COUNTER = 'd0; 37 | end 38 | 39 | parameter MODE = 0; 40 | 41 | // startup timing 42 | wire LOAD_MODE = {COUNTER[13:9]} == 5'b11000; // x2 load mode commands 43 | wire AUTO_REFRESH = {COUNTER[13:9]} == 5'b10110; // x2 auto refresh cmds 44 | wire PRECHARGE = {COUNTER[13:8]} == 6'b101000; // x1 precharge command 45 | 46 | always @(posedge CLK or negedge RESET) begin 47 | 48 | if (RESET == 1'b0) begin 49 | COUNTER <= 'd0; 50 | end else begin 51 | COUNTER <= COUNTER + 'd1; 52 | end 53 | 54 | end 55 | 56 | always @(posedge CLK or negedge RESET) begin 57 | 58 | if (RESET == 1'b0) begin 59 | 60 | READY <= 'b1; 61 | REFRESH <= 'b1; 62 | CLKE <= 'b0; 63 | 64 | ARAM <= 'd0; 65 | CMD <= CMD_INHIBIT; 66 | 67 | end else begin 68 | 69 | REFRESH <= ~COUNTER[7] | READY; 70 | CMD <= CMD_NOP; 71 | 72 | if (READY == 1'b1) begin 73 | 74 | if (COUNTER[7:0] == 8'h00) begin 75 | 76 | if(PRECHARGE == 1'b1) begin 77 | $display("precharging all banks"); 78 | CMD <= CMD_PRECHARGE; 79 | ARAM[10] <= 1'b1; // precharge all banks 80 | end 81 | 82 | if(AUTO_REFRESH == 1'b1) begin 83 | $display("issuing auto refresh command"); 84 | CMD <= CMD_AUTO_REFRESH; 85 | end 86 | 87 | // last two cycles are mode loads 88 | if(LOAD_MODE == 1'b1) begin 89 | $display("loading mode register: %b", MODE); 90 | CMD <= CMD_LOAD_MODE; 91 | ARAM <= MODE; 92 | end 93 | 94 | // latch when the refresh period is complete 95 | READY <= ~(&COUNTER[13:11]); 96 | 97 | // Starting at some point during this 100μs period, bring CKE HIGH. Continuing at 98 | // least through the end of this period, 1 or more COMMAND INHIBIT or NOP commands 99 | // must be applied. 100 | if (COUNTER[13] == 1'b1) begin 101 | 102 | CLKE <= 1'b1; 103 | 104 | end 105 | 106 | end 107 | 108 | end 109 | 110 | end 111 | 112 | end 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /boards/Makefile.cpld: -------------------------------------------------------------------------------- 1 | # Project name 2 | ifndef BOARD 3 | $(error BOARD must be defined) 4 | endif 5 | 6 | ifndef REVISION 7 | $(error REVISION must be defined) 8 | endif 9 | 10 | ifndef SUBPROJ 11 | $(error SUBPROJ must be defined) 12 | endif 13 | 14 | ifndef SOURCES 15 | $(error SOURCES must be defined) 16 | endif 17 | 18 | ifndef OPTIMIZE 19 | OPTIMIZE:=speed 20 | endif 21 | 22 | ifndef OPTMODE 23 | OPTMODE:=Area 24 | endif 25 | 26 | ifndef TARGET 27 | TARGET=CD32 28 | endif 29 | 30 | ifndef SERIALNO 31 | SERIALNO=330 32 | endif 33 | 34 | PROJECT=$(BOARD)r$(REVISION)_$(SUBPROJ)_top 35 | 36 | ifndef TOP 37 | TOP=$(PROJECT) 38 | endif 39 | 40 | # Part number 41 | ifndef PART 42 | PART=XC95144XL-10-TQ144 43 | endif 44 | 45 | # Constraints file 46 | UCF=./$(BOARD)r$(REVISION)_$(SUBPROJ).ucf 47 | 48 | # Path to Xilinx tools, blank if in $PATH, must end in / 49 | #XILINX=/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/ 50 | #XILINX=/opt/Xilinx/10.1/ISE_DS/ISE/bin/lin64/ 51 | XILINX=/opt/Xilinx/10.1/ISE/bin/lin64/ 52 | WD=work 53 | PN=$(PROJECT)$(JEDEXTRA) 54 | PB=$(WD)/$(PN) 55 | # Output configuration file 56 | OUTPUT=$(PN).svf 57 | 58 | XSTFLAGS=-define {$(TARGET) SERIALNO=$(SERIALNO)} -opt_mode $(OPTMODE) -opt_level 2 -verilog2001 YES -keep_hierarchy No -netlist_hierarchy As_Optimized -rtlview Yes -hierarchy_separator / -bus_delimiter <> -case Maintain -fsm_extract NO -fsm_encoding Auto -safe_implementation YES -mux_extract Yes -resource_sharing YES -iobuf YES -pld_mp YES -pld_xp YES -pld_ce YES -wysiwyg NO -equivalent_register_removal YES 59 | CPLDFITFLAGS=-slew slow -power std -terminate float -unused float -optimize $(OPTIMIZE) -pterms 50 -loc on -keepio -exhaust -init low 60 | 61 | .PHONY: all clean 62 | 63 | all: $(PB).tim $(OUTPUT) 64 | cp $(PB).jed $(PN).jed 65 | $(WD): 66 | mkdir $(WD)/ 67 | 68 | $(PB).ngc: $(SOURCES) 69 | @[ ! -e $(WD) ] && mkdir $(WD) || true 70 | @echo "Generating $(PB).prj..." 71 | @rm -f $(PB).prj 72 | @for i in $(SOURCES); do \ 73 | echo "verilog $(PROJECT) $$i" >> $(PB).prj; \ 74 | done 75 | @echo "DEFAULT_SEARCH_ORDER" > $(PB).lso 76 | @echo "set -tmpdir $(WD) -xsthdpdir $(WD)" > $(PB).xst 77 | @echo "run -ifn $(PB).prj -ifmt mixed -top $(TOP) -ofn $@ -ofmt NGC -p $(PART) $(XSTFLAGS) $(PARAMS) -lso $(PB).lso" >> $(PB).xst 78 | $(XILINX)xst -ifn $(PB).xst -ofn $(PB)_xst.log 79 | 80 | $(PB).ngd: $(PB).ngc $(UCF) 81 | cd $(WD) ; $(XILINX)ngdbuild -p $(PART) -uc ../$(UCF) ../$< ../$@ 82 | 83 | 84 | $(PB).vm6: $(PB).ngd 85 | cd $(WD) ; $(XILINX)cpldfit $(CPLDFITFLAGS) -p $(PART) ../$< 86 | 87 | $(PB).tim: $(PB).vm6 88 | cd $(WD) ; $(XILINX)taengine -l ../$@ -detail -f $(PN) ../$< 89 | 90 | $(PB).jed: $(PB).vm6 91 | cd $(WD) ; $(XILINX)hprep6 -i ../$< 92 | @cp $(PB).jed $(OUTPUT) 93 | 94 | $(PB).svf: $(PB).jed 95 | @echo "Generating $(PB).cmd..." 96 | @echo "setmode -bscan" > $(PB).cmd 97 | @echo "setcable -p svf -file ../$@" >> $(PB).cmd 98 | @echo "addDevice -p 1 -file ../$<" >> $(PB).cmd 99 | @echo "erase -p 1 -o" >> $(PB).cmd 100 | @echo "program -p 1" >> $(PB).cmd 101 | @echo "quit" >> $(PB).cmd 102 | cd $(WD) ; $(XILINX)impact -batch $(PN).cmd 103 | 104 | %: $(WD)/% 105 | @sed -e 's/FREQUENCY .* HZ/FREQUENCY 5E5 HZ/' $< >$@ 106 | @echo "Output $@ is ready" 107 | 108 | clean: 109 | rm -rf $(WD) $(OUTPUT) _xmsgs 110 | distclean: clean 111 | rm -rf *~ 112 | -------------------------------------------------------------------------------- /rtl/ata.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | Copyright (C) 2016-2017, Stephen J. Leary 4 | All rights reserved. 5 | 6 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 7 | 8 | Attribution-NoDerivs 3.0 Unported 9 | 10 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 11 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 12 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 13 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 14 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 15 | DAMAGES RESULTING FROM ITS USE. 16 | 17 | */ 18 | 19 | module ata ( 20 | input CLK, 21 | input AS, 22 | input RW, 23 | input [31:0] A, 24 | input WAIT, 25 | 26 | output [1:0] IDECS, 27 | output IOR, 28 | output IOW, 29 | output DTACK, 30 | output ACCESS 31 | ); 32 | 33 | /* Timing Diagram 34 | S0 S1 S2 S3 S4 S5 W W S6 S7 35 | __ __ __ __ __ __ __ __ __ __ __ __ 36 | CLK | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__ 37 | _________________ _____________________________ 38 | AS \\\_____________________/ 39 | _______________ _____________________________ 40 | CS \__________________________/ 41 | ______________________ _____________________________ 42 | IOR \___________________/ 43 | _____________________________ ___________________________________ 44 | IOW \______/ 45 | _____________________________ ___________________________________ 46 | DTACK \______/ 47 | _________________________ ________________________________________ 48 | WAIT \_____/ 49 | 50 | */ 51 | 52 | `ifndef A1200 53 | wire GAYLE_IDE = ({A[31:15]} != {16'h00DA,1'b0}); 54 | `else 55 | wire GAYLE_IDE = ({A[31:14]} != {16'h00DA,2'b01}); 56 | `endif 57 | 58 | reg [7:0] ASDLY = 8'hff; 59 | reg DTACK_INT = 1'b1; 60 | 61 | reg IOR_INT = 1'b1; 62 | reg IOW_INT = 1'b1; 63 | 64 | always @(posedge CLK or posedge AS) begin 65 | 66 | if (AS == 1'b1) begin 67 | 68 | ASDLY <= 8'hff; 69 | 70 | end else begin 71 | 72 | ASDLY <= {ASDLY[6:0], AS | (GAYLE_IDE)}; 73 | 74 | end 75 | 76 | end 77 | 78 | always @(negedge CLK or posedge AS) begin 79 | 80 | if (AS == 1'b1) begin 81 | 82 | IOR_INT <= 1'b1; 83 | IOW_INT <= 1'b1; 84 | DTACK_INT <= 1'b1; 85 | 86 | end else begin 87 | 88 | IOR_INT <= ~RW | ASDLY[0]; 89 | IOW_INT <= RW | ASDLY[1]; 90 | DTACK_INT <= ASDLY[1] | ~WAIT; 91 | 92 | end 93 | 94 | end 95 | 96 | reg [1:0] IDECS_INT; 97 | reg RTC_CS_INT; 98 | reg SPARE_CS_INT; 99 | 100 | always @(posedge CLK) begin 101 | 102 | IDECS_INT <= A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE}; 103 | 104 | end 105 | 106 | assign IOR = IOR_INT; 107 | assign IOW = IOW_INT; 108 | assign DTACK = DTACK_INT; 109 | assign IDECS = IDECS_INT; 110 | assign ACCESS = GAYLE_IDE; 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /rtl/gayle.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | Copyright (C) 2016-2017, Stephen J. Leary 4 | All rights reserved. 5 | 6 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 7 | 8 | Attribution-NoDerivs 3.0 Unported 9 | 10 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 11 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 12 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 13 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 14 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 15 | DAMAGES RESULTING FROM ITS USE. 16 | 17 | */ 18 | 19 | module gayle( 20 | input CLKCPU, 21 | input RESET, 22 | input DS20, 23 | input AS20, 24 | input RW, 25 | input IDE_INT, 26 | output INT2, 27 | input [31:0] A, 28 | input DIN, 29 | output DOUT, 30 | output ACCESS 31 | ); 32 | 33 | parameter GAYLE_ID_VAL = 4'hd; 34 | 35 | `ifndef A1200 36 | wire GAYLE_REGS = (A[31:15] != {16'h00DA, 1'b1}); 37 | wire GAYLE_ID = (A[31:15] != {16'h00DE, 1'b0}); 38 | `else 39 | wire GAYLE_REGS = (A[31:14] != {16'h00DA, 2'b11}); 40 | wire GAYLE_ID = 1'b1; 41 | `endif 42 | 43 | wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS); 44 | 45 | reg data_out = 1'b0; 46 | 47 | reg [3:0] gayleid = GAYLE_ID_VAL; 48 | 49 | reg intena = 1'b0; 50 | reg intlast = 1'b0; 51 | 52 | // $DE1000 53 | localparam GAYLE_ID_RD = {1'b1,2'h1,1'b1}; 54 | localparam GAYLE_ID_WR = {1'b1,2'h1,1'b0}; 55 | 56 | // $DA8000 57 | localparam GAYLE_STAT_RD = {3'h0,1'b1}; 58 | localparam GAYLE_STAT_WR = {3'h0,1'b0}; 59 | 60 | // $DA9000 61 | localparam GAYLE_INTCHG_RD = {3'h1,1'b1}; 62 | localparam GAYLE_INTCHG_WR = {3'h1,1'b0}; 63 | 64 | // $DAA000 65 | localparam GAYLE_INTENA_RD = {3'h2,1'b1}; 66 | localparam GAYLE_INTENA_WR = {3'h2,1'b0}; 67 | 68 | wire INT_CHNG; 69 | wire INT_CHNG_ACCESS = {(GAYLE_ACCESS | AS20),A[18],{A[13:12]},RW} != {1'b0,GAYLE_INTCHG_WR}; 70 | 71 | wire DS = DS20 | GAYLE_ACCESS | AS20; 72 | 73 | FDCPE #(.INIT(1'b1)) 74 | INT_CHNG_FF ( 75 | .Q(INT_CHNG), // Data output 76 | .C(~DS), // Clock input 77 | .CE(~INT_CHNG_ACCESS), // CLOCK ENABLE 78 | .CLR(~RESET), // Asynchronous clear input 79 | .D(DIN & INT_CHNG), // Data input 80 | .PRE(({IDE_INT, intlast} == 2'b10) & intena) // Asynchronous set input 81 | ); 82 | 83 | 84 | always @(posedge CLKCPU) begin 85 | 86 | intlast <= IDE_INT; 87 | 88 | end 89 | 90 | always @(negedge DS or negedge RESET) begin 91 | 92 | if (RESET == 1'b0) begin 93 | 94 | // resetting to low ensures that the next cycle 95 | intena <= 1'b0; 96 | gayleid <= 4'hD; 97 | 98 | end else begin 99 | 100 | case ({A[18],{A[13:12]},RW}) 101 | GAYLE_STAT_RD: data_out <= IDE_INT; 102 | GAYLE_INTCHG_RD: data_out <= INT_CHNG; 103 | GAYLE_ID_RD: begin 104 | data_out <= gayleid[3]; 105 | gayleid <= {gayleid[2:0],1'b1}; 106 | end 107 | GAYLE_ID_WR: gayleid <= 4'hD; 108 | GAYLE_INTENA_RD: data_out <= intena; 109 | GAYLE_INTENA_WR: intena <= DIN; 110 | default: data_out <= 'b0; 111 | endcase 112 | 113 | end 114 | end 115 | 116 | assign INT2 = ~(INT_CHNG & intena); 117 | assign DOUT = data_out; 118 | assign ACCESS = GAYLE_ACCESS; 119 | 120 | endmodule 121 | -------------------------------------------------------------------------------- /boards/tf1230r1/tf1230r1_main.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2016-2017, Stephen J. Leary 2 | # All rights reserved. 3 | # 4 | # This file is part of TF330/TF120 (Terrible Fire 030 Accelerator) 5 | # 6 | # TF330/TF120 is free software: you can redistribute it and/or modify 7 | # it under the terms of the GNU General Public License as published by 8 | # the Free Software Foundation, either version 3 of the License, or 9 | # (at your option) any later version. 10 | # 11 | # TF330/TF120 is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | # You should have received a copy of the GNU General Public License 17 | # along with TF1230. If not, see . 18 | 19 | #Clocks 20 | NET "CLK100M" LOC="32"; 21 | NET "CLK100M" BUFG=CLK; 22 | NET "CLK100M" TNM_NET = "CLK100M"; # gives the net clk a group name as CLK100M 23 | 24 | NET "A<0>" LOC="87"; 25 | NET "A<1>" LOC="95"; 26 | NET "A<2>" LOC="128"; 27 | NET "A<3>" LOC="126"; 28 | NET "A<4>" LOC="125"; 29 | NET "A<5>" LOC="124"; 30 | NET "A<6>" LOC="121"; 31 | NET "A<7>" LOC="120"; 32 | NET "A<8>" LOC="119"; 33 | NET "A<9>" LOC="118"; 34 | NET "A<10>" LOC="117"; 35 | NET "A<11>" LOC="116"; 36 | NET "A<12>" LOC="113"; 37 | NET "A<13>" LOC="115"; 38 | NET "A<14>" LOC="112"; 39 | NET "A<15>" LOC="111"; 40 | NET "A<16>" LOC="110"; 41 | NET "A<17>" LOC="107"; 42 | NET "A<18>" LOC="106"; 43 | NET "A<19>" LOC="105"; 44 | NET "A<20>" LOC="104"; 45 | NET "A<21>" LOC="103"; 46 | NET "A<22>" LOC="102"; 47 | NET "A<23>" LOC="101"; 48 | NET "A<24>" LOC="100"; 49 | NET "A<25>" LOC="98"; 50 | NET "A<26>" LOC="97"; 51 | NET "A<27>" LOC="96"; 52 | NET "A<28>" LOC="94"; 53 | NET "A<29>" LOC="93"; 54 | NET "A<30>" LOC="91"; 55 | NET "A<31>" LOC="88"; 56 | NET "AB<2>" LOC="59"; 57 | NET "AB<3>" LOC="58"; 58 | NET "AB<4>" LOC="60"; 59 | NET "ARAM<0>" LOC="25"; 60 | NET "ARAM<1>" LOC="26"; 61 | NET "ARAM<2>" LOC="27"; 62 | NET "ARAM<3>" LOC="28"; 63 | NET "ARAM<4>" LOC="14"; 64 | NET "ARAM<5>" LOC="13"; 65 | NET "ARAM<6>" LOC="12"; 66 | NET "ARAM<7>" LOC="11"; 67 | NET "ARAM<8>" LOC="10"; 68 | NET "ARAM<9>" LOC="9"; 69 | NET "ARAM<10>" LOC="24"; 70 | NET "ARAM<11>" LOC="7"; 71 | NET "ARAM<12>" LOC="6"; 72 | NET "AS20" LOC="140"; 73 | NET "AS30" LOC="132"; 74 | NET "BA<0>" LOC="23"; 75 | NET "BA<1>" LOC="22"; 76 | NET "BERR" LOC="75"; 77 | NET "BG30" LOC="86"; 78 | NET "BGACK30" LOC="92"; 79 | NET "BR20" LOC="33"; 80 | NET "BR30" LOC="83"; 81 | NET "CAS" LOC="19"; 82 | NET "CBACK" LOC="74"; 83 | NET "CBREQ" LOC="68"; 84 | NET "CFGOUT" LOC="34"; 85 | NET "CIIN" LOC="69"; 86 | NET "CLK14M" LOC="71"; 87 | NET "CLKCPU" LOC="80"; 88 | NET "CLKRAM" LOC="4"; 89 | NET "CLKRAME" LOC="5"; 90 | NET "D<24>" LOC="52"; 91 | NET "D<25>" LOC="51"; 92 | NET "D<26>" LOC="50"; 93 | NET "D<27>" LOC="49"; 94 | NET "D<28>" LOC="48"; 95 | NET "D<29>" LOC="46"; 96 | NET "D<30>" LOC="45"; 97 | NET "D<31>" LOC="44"; 98 | NET "DQM<0>" LOC="16"; 99 | NET "DQM<1>" LOC="31"; 100 | NET "DQM<2>" LOC="15"; 101 | NET "DQM<3>" LOC="3"; 102 | NET "DS20" LOC="139"; 103 | NET "DS30" LOC="133"; 104 | NET "DS30ACK<0>" LOC="79"; 105 | NET "DS30ACK<1>" LOC="78"; 106 | NET "DSACK<0>" LOC="135"; 107 | NET "DSACK<1>" LOC="136"; 108 | NET "FC<0>" LOC="85"; 109 | NET "FC<1>" LOC="82"; 110 | NET "FC<2>" LOC="81"; 111 | NET "HALT" LOC="76"; 112 | NET "IDECS<0>" LOC="64"; 113 | NET "IDECS<1>" LOC="61"; 114 | NET "IDEINT" LOC="57"; 115 | NET "IDEWAIT" LOC="56"; 116 | NET "INT2" LOC="143"; 117 | NET "IOR" LOC="54"; 118 | NET "IOW" LOC="53"; 119 | NET "PUNT" LOC="142"; 120 | NET "RAMOE" LOC="2"; 121 | NET "RAMCS" LOC="21"; 122 | NET "RAMWE" LOC="17"; 123 | NET "RAS" LOC="20"; 124 | NET "RESET" LOC="43"; 125 | NET "RSTO" LOC="129"; 126 | NET "RW20" LOC="138"; 127 | NET "RW30" LOC="134"; 128 | NET "SIZ<0>" LOC="66"; 129 | NET "SIZ<1>" LOC="70"; 130 | NET "STERM" LOC="77"; 131 | -------------------------------------------------------------------------------- /boards/tf330r2/tf330r2_main_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | Copyright (C) 2016-2017, Stephen J. Leary 5 | All rights reserved. 6 | 7 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 8 | 9 | TF330/TF120 is free software: you can redistribute it and/or modify 10 | it under the terms of the GNU General Public License as published by 11 | the Free Software Foundation, either version 3 of the License, or 12 | (at your option) any later version. 13 | 14 | TF330/TF120 is distributed in the hope that it will be useful, 15 | but WITHOUT ANY WARRANTY; without even the implied warranty You should have received a copy of the GNU General Public Licenseof 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | GNU General Public License for more details. 18 | 19 | 20 | along with TF330/TF120. If not, see . 21 | */ 22 | 23 | module tf330r2_main_top( 24 | 25 | inout RESET, 26 | inout HALT, 27 | 28 | inout DISABLE, 29 | output AUXGND, 30 | 31 | // all clock lines. 32 | inout CLK14M, 33 | inout CLK100M, 34 | inout CLKCPU, 35 | inout CLKRAM, 36 | 37 | inout [31:0] A, 38 | inout [31:24] D, 39 | 40 | // SDRAM Control 41 | inout CLKRAME, 42 | inout [12:0] ARAM, 43 | inout [1:0] BA, 44 | inout CAS, 45 | inout [3:0] DQM, 46 | inout RAMWE, 47 | inout RAS, 48 | inout RAMCS, 49 | inout RAMOE, 50 | 51 | // transfer control lines 52 | inout [1:0] SIZ, 53 | inout [2:0] FC, 54 | inout[2:0] IPL, 55 | 56 | // cache control lines. 57 | inout CBREQ, 58 | inout CBACK, 59 | inout CIIN, 60 | 61 | // 68030 control lines 62 | inout AS30, 63 | inout DS30, 64 | inout RW30, 65 | 66 | inout [1:0] DS30ACK, 67 | inout STERM, 68 | 69 | inout BGACK30, 70 | inout BR30, 71 | inout BG30, 72 | 73 | // CD32 / 68020 control lines 74 | inout AS20, 75 | inout DS20, 76 | inout RW20, 77 | 78 | inout BR20, 79 | inout BG20, 80 | inout BGACK20, 81 | 82 | inout [1:0] DSACK, 83 | 84 | inout IOW, 85 | inout IOR, 86 | 87 | inout IDEINT, 88 | inout IDEWAIT, 89 | inout [1:0] IDECS, 90 | inout PUNT, 91 | inout BERR, 92 | 93 | inout EXP_BR, 94 | inout EXP_BG, 95 | 96 | inout INT2, 97 | inout IDELED, 98 | inout ACTIVE, 99 | 100 | inout RXD, 101 | inout RXD_EXT, 102 | 103 | inout TXD, 104 | inout TXD_EXT 105 | ); 106 | 107 | // Instantiate the module 108 | main_top MAIN ( 109 | .RESET(RESET), 110 | .HALT(HALT), 111 | .DISABLE(DISABLE), 112 | .CLK14M(CLK14M), 113 | .CLK100M(CLK100M), 114 | .CLKCPU(CLKCPU), 115 | .CLKRAM(CLKRAM), 116 | .A(A), 117 | .D(D), 118 | .CLKRAME(CLKRAME), 119 | .ARAM(ARAM), 120 | .BA(BA), 121 | .CAS(CAS), 122 | .DQM(DQM), 123 | .RAMWE(RAMWE), 124 | .RAS(RAS), 125 | .RAMCS(RAMCS), 126 | .RAMOE(RAMOE), 127 | .SIZ(SIZ), 128 | .FC(FC), 129 | .IPL(IPL), 130 | .CBREQ(CBREQ), 131 | .CBACK(CBACK), 132 | .CIIN(CIIN), 133 | .AS30(AS30), 134 | .DS30(DS30), 135 | .RW30(RW30), 136 | .DS30ACK(DS30ACK), 137 | .STERM(STERM), 138 | .BGACK30(BGACK30), 139 | .BR30(BR30), 140 | .BG30(BG30), 141 | .AS20(AS20), 142 | .DS20(DS20), 143 | .RW20(RW20), 144 | .BR20(BR20), 145 | .BG20(BG20), 146 | .BGACK20(BGACK20), 147 | .DSACK(DSACK), 148 | .IOW(IOW), 149 | .IOR(IOR), 150 | .IDEINT(IDEINT), 151 | .IDEWAIT(IDEWAIT), 152 | .IDECS(IDECS), 153 | .PUNT(PUNT), 154 | .BERR(BERR), 155 | .EXP_BR(EXP_BR), 156 | .EXP_BG(EXP_BG), 157 | .INT2(INT2), 158 | .IDELED(IDELED), 159 | .ACTIVE(ACTIVE), 160 | .RXD(RXD), 161 | .RXD_EXT(RXD_EXT), 162 | .TXD(TXD), 163 | .TXD_EXT(TXD_EXT) 164 | ); 165 | 166 | assign AUXGND = 1'b0; 167 | 168 | endmodule 169 | -------------------------------------------------------------------------------- /boards/tf1230r1/tf1230r1_main_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | Copyright (C) 2020-2021, Stephen J. Leary 5 | All rights reserved. 6 | 7 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 8 | 9 | TF330/TF120 is free software: you can redistribute it and/or modify 10 | it under the terms of the GNU General Public License as published by 11 | the Free Software Foundation, either version 3 of the License, or 12 | (at your option) any later version. 13 | 14 | TF330/TF120 is distributed in the hope that it will be useful, 15 | but WITHOUT ANY WARRANTY; without even the implied warranty You should have received a copy of the GNU General Public Licenseof 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | GNU General Public License for more details. 18 | 19 | 20 | along with TF330/TF120. If not, see . 21 | */ 22 | 23 | module tf1230r1_main_top( 24 | 25 | inout RESET, 26 | inout HALT, 27 | 28 | // all clock lines. 29 | inout CLK14M, 30 | inout CLK100M, 31 | inout CLKCPU, 32 | inout CLKRAM, 33 | 34 | inout [31:0] A, 35 | inout [31:24] D, 36 | 37 | // SDRAM Control 38 | inout CLKRAME, 39 | inout [12:0] ARAM, 40 | inout [1:0] BA, 41 | inout CAS, 42 | inout [3:0] DQM, 43 | inout RAMWE, 44 | inout RAS, 45 | inout RAMCS, 46 | inout RAMOE, 47 | 48 | // transfer control lines 49 | inout [1:0] SIZ, 50 | input [2:0] FC, 51 | inout [2:0] IPL, 52 | 53 | // cache control lines. 54 | inout CBREQ, 55 | inout CBACK, 56 | inout CIIN, 57 | 58 | // 68030 control lines 59 | inout AS30, 60 | inout DS30, 61 | inout RW30, 62 | 63 | inout [1:0] DS30ACK, 64 | inout STERM, 65 | 66 | inout BGACK30, 67 | inout BR30, 68 | inout BG30, 69 | 70 | // A1200 / 68020 control lines 71 | inout AS20, 72 | inout DS20, 73 | inout RW20, 74 | 75 | input BR20, 76 | input BG20, 77 | 78 | inout [1:0] DSACK, 79 | 80 | output [5:2] AB, 81 | inout IOW, 82 | inout IOR, 83 | 84 | inout IDEINT, 85 | inout IDEWAIT, 86 | inout [1:0] IDECS, 87 | inout PUNT, 88 | inout BERR, 89 | 90 | output CFGOUT, 91 | input RSTO, 92 | inout INT2 93 | 94 | ); 95 | 96 | // Instantiate the module 97 | main_top MAIN ( 98 | .RESET ( RESET ), 99 | .HALT ( HALT ), 100 | .CLK14M ( CLK14M ), 101 | .CLK100M ( CLK100M), 102 | .CLKCPU ( CLKCPU ), 103 | .CLKRAM ( CLKRAM ), 104 | .A ( A ), 105 | .D ( D ), 106 | .CLKRAME ( CLKRAME), 107 | .ARAM ( ARAM ), 108 | .BA ( BA ), 109 | .CAS ( CAS ), 110 | .DQM ( DQM ), 111 | .RAMWE ( RAMWE ), 112 | .RAS ( RAS ), 113 | .RAMCS ( RAMCS ), 114 | .RAMOE ( RAMOE ), 115 | .SIZ ( SIZ ), 116 | .FC ( FC ), 117 | .IPL ( IPL ), 118 | .CBREQ ( CBREQ ), 119 | .CBACK ( CBACK ), 120 | .CIIN ( CIIN ), 121 | .AS30 ( AS30 ), 122 | .DS30 ( DS30 ), 123 | .RW30 ( RW30 ), 124 | .DS30ACK ( DS30ACK), 125 | .STERM ( STERM ), 126 | .BGACK30 ( BGACK30), 127 | .BR30 ( BR30 ), 128 | .BG30 ( BG30 ), 129 | .AS20 ( AS20 ), 130 | .DS20 ( DS20 ), 131 | .RW20 ( RW20 ), 132 | .BG20 ( BG20 ), 133 | .DSACK ( DSACK ), 134 | .IOW ( IOW ), 135 | .IOR ( IOR ), 136 | .IDEINT ( IDEINT ), 137 | .IDEWAIT ( IDEWAIT), 138 | 139 | .IDECS ( IDECS ), 140 | .PUNT ( PUNT ), 141 | .BERR ( BERR ), 142 | .INT2 ( INT2 ), 143 | 144 | .EXP_BR ( 1'b1 ), 145 | .EXP_BG ( ), 146 | 147 | .IDELED ( 1'b1 ), 148 | .ACTIVE ( ), 149 | 150 | .DISABLE ( BR20 ), 151 | 152 | // Serial port not present. 153 | .RXD_EXT ( ), 154 | .RXD ( ), 155 | .TXD_EXT ( ), 156 | .TXD ( ) 157 | ); 158 | 159 | assign AB[5:2] = {A[5:2]}; 160 | assign CFGOUT = 1'b1; 161 | 162 | endmodule 163 | -------------------------------------------------------------------------------- /boards/tf330r2/tf330r2_main.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2016-2017, Stephen J. Leary 2 | # All rights reserved. 3 | # 4 | # This file is part of TF330/TF120 (Terrible Fire 030 Accelerator) 5 | # 6 | # TF330/TF120 is free software: you can redistribute it and/or modify 7 | # it under the terms of the GNU General Public License as published by 8 | # the Free Software Foundation, either version 3 of the License, or 9 | # (at your option) any later version. 10 | # 11 | # TF330/TF120 is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | # You should have received a copy of the GNU General Public License 17 | # along with TF330. If not, see . 18 | 19 | #Clocks 20 | NET "CLK100M" LOC="32"; 21 | NET "CLK100M" BUFG=CLK; 22 | NET "CLK100M" TNM_NET = "CLK100M"; # gives the net clk a group name as CLK100M 23 | 24 | NET "CLK14M" LOC="30"; 25 | NET "CLK14M" BUFG=CLK; 26 | NET "CLK14M" TNM_NET = "CLK14M"; # gives the net clk a group name as CLK14M 27 | 28 | NET "A<0>" LOC="87"; 29 | NET "A<1>" LOC="95"; 30 | NET "A<2>" LOC="128"; 31 | NET "A<3>" LOC="126"; 32 | NET "A<4>" LOC="125"; 33 | NET "A<5>" LOC="124"; 34 | NET "A<6>" LOC="121"; 35 | NET "A<7>" LOC="120"; 36 | NET "A<8>" LOC="119"; 37 | NET "A<9>" LOC="118"; 38 | NET "A<10>" LOC="117"; 39 | NET "A<11>" LOC="116"; 40 | NET "A<12>" LOC="113"; 41 | NET "A<13>" LOC="115"; 42 | NET "A<14>" LOC="112"; 43 | NET "A<15>" LOC="111"; 44 | NET "A<16>" LOC="110"; 45 | NET "A<17>" LOC="107"; 46 | NET "A<18>" LOC="106"; 47 | NET "A<19>" LOC="105"; 48 | NET "A<20>" LOC="104"; 49 | NET "A<21>" LOC="103"; 50 | NET "A<22>" LOC="102"; 51 | NET "A<23>" LOC="101"; 52 | NET "A<24>" LOC="100"; 53 | NET "A<25>" LOC="98"; 54 | NET "A<26>" LOC="97"; 55 | NET "A<27>" LOC="96"; 56 | NET "A<28>" LOC="94"; 57 | NET "A<29>" LOC="93"; 58 | NET "A<30>" LOC="91"; 59 | NET "A<31>" LOC="88"; 60 | NET "ACTIVE" LOC="35"; 61 | NET "ARAM<0>" LOC="25"; 62 | NET "ARAM<1>" LOC="26"; 63 | NET "ARAM<2>" LOC="27"; 64 | NET "ARAM<3>" LOC="28"; 65 | NET "ARAM<4>" LOC="14"; 66 | NET "ARAM<5>" LOC="13"; 67 | NET "ARAM<6>" LOC="12"; 68 | NET "ARAM<7>" LOC="11"; 69 | NET "ARAM<8>" LOC="10"; 70 | NET "ARAM<9>" LOC="9"; 71 | NET "ARAM<10>" LOC="24"; 72 | NET "ARAM<11>" LOC="7"; 73 | NET "ARAM<12>" LOC="6"; 74 | NET "AS20" LOC="132"; 75 | NET "AS30" LOC="74"; 76 | NET "DISABLE" LOC="39"; 77 | NET AUXGND LOC="38"; 78 | #NET "AUX<2>" LOC="40"; 79 | NET "BA<0>" LOC="23"; 80 | NET "BA<1>" LOC="22"; 81 | NET "BERR" LOC="75"; 82 | NET "BG20" LOC="138"; 83 | NET "BG30" LOC="86"; 84 | NET "BGACK30" LOC="92"; 85 | NET "BR20" LOC="137"; 86 | NET "BR30" LOC="83"; 87 | NET "CAS" LOC="19"; 88 | NET "CBACK" LOC="70"; 89 | NET "CBREQ" LOC="66"; 90 | NET "CIIN" LOC="60"; 91 | NET "CLKCPU" LOC="80"; 92 | NET "CLKRAM" LOC="4"; 93 | NET "CLKRAME" LOC="5"; 94 | NET "D<24>" LOC="52"; 95 | NET "D<25>" LOC="51"; 96 | NET "D<26>" LOC="50"; 97 | NET "D<27>" LOC="49"; 98 | NET "D<28>" LOC="48"; 99 | NET "D<29>" LOC="46"; 100 | NET "D<30>" LOC="45"; 101 | NET "D<31>" LOC="44"; 102 | NET "DQM<0>" LOC="16"; 103 | NET "DQM<1>" LOC="31"; 104 | NET "DQM<2>" LOC="15"; 105 | NET "DQM<3>" LOC="3"; 106 | NET "DS20" LOC="133"; 107 | NET "DS30" LOC="68"; 108 | NET "DS30ACK<0>" LOC="79"; 109 | NET "DS30ACK<1>" LOC="78"; 110 | NET "DSACK<0>" LOC="135"; 111 | NET "DSACK<1>" LOC="136"; 112 | NET "EXP_BG" LOC="139"; 113 | NET "EXP_BR" LOC="140"; 114 | NET "FC<0>" LOC="85"; 115 | NET "FC<1>" LOC="82"; 116 | NET "FC<2>" LOC="81"; 117 | NET "HALT" LOC="76"; 118 | NET "IDECS<0>" LOC="58"; 119 | NET "IDECS<1>" LOC="59"; 120 | NET "IDEINT" LOC="57"; 121 | NET "IDELED" LOC="71"; 122 | NET "IDEWAIT" LOC="56"; 123 | NET "INT2" LOC="143"; 124 | NET "IOR" LOC="54"; 125 | NET "IOW" LOC="53"; 126 | NET "PUNT" LOC="142"; 127 | NET "RAMCS" LOC="21"; 128 | NET "RAMOE" LOC="2"; 129 | NET "RAMWE" LOC="17"; 130 | NET "RAS" LOC="20"; 131 | NET "RESET" LOC="129"; 132 | NET "RW20" LOC="134"; 133 | NET "RW30" LOC="64"; 134 | NET "RXD" LOC="34"; 135 | NET "RXD_EXT" LOC="43"; 136 | NET "SIZ<0>" LOC="61"; 137 | NET "SIZ<1>" LOC="69"; 138 | NET "STERM" LOC="77"; 139 | NET "TXD" LOC="33"; 140 | NET "TXD_EXT" LOC="41"; 141 | -------------------------------------------------------------------------------- /boards/tf330r3/tf330r3_main.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2016-2017, Stephen J. Leary 2 | # All rights reserved. 3 | # 4 | # This file is part of TF330/TF120 (Terrible Fire 030 Accelerator) 5 | # 6 | # TF330/TF120 is free software: you can redistribute it and/or modify 7 | # it under the terms of the GNU General Public License as published by 8 | # the Free Software Foundation, either version 3 of the License, or 9 | # (at your option) any later version. 10 | # 11 | # TF330/TF120 is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | # You should have received a copy of the GNU General Public License 17 | # along with TF330. If not, see . 18 | 19 | #Clocks 20 | NET "CLK100M" LOC="32"; 21 | NET "CLK100M" BUFG=CLK; 22 | NET "CLK100M" TNM_NET = "CLK100M"; # gives the net clk a group name as CLK100M 23 | 24 | NET "CLK14M" LOC="30"; 25 | NET "CLK14M" BUFG=CLK; 26 | NET "CLK14M" TNM_NET = "CLK14M"; # gives the net clk a group name as CLK14M 27 | 28 | NET "A<0>" LOC="87"; 29 | NET "A<1>" LOC="95"; 30 | NET "A<2>" LOC="128"; 31 | NET "A<3>" LOC="126"; 32 | NET "A<4>" LOC="125"; 33 | NET "A<5>" LOC="124"; 34 | NET "A<6>" LOC="121"; 35 | NET "A<7>" LOC="120"; 36 | NET "A<8>" LOC="119"; 37 | NET "A<9>" LOC="118"; 38 | NET "A<10>" LOC="117"; 39 | NET "A<11>" LOC="116"; 40 | NET "A<12>" LOC="113"; 41 | NET "A<13>" LOC="115"; 42 | NET "A<14>" LOC="112"; 43 | NET "A<15>" LOC="111"; 44 | NET "A<16>" LOC="110"; 45 | NET "A<17>" LOC="107"; 46 | NET "A<18>" LOC="106"; 47 | NET "A<19>" LOC="105"; 48 | NET "A<20>" LOC="104"; 49 | NET "A<21>" LOC="103"; 50 | NET "A<22>" LOC="102"; 51 | NET "A<23>" LOC="101"; 52 | NET "A<24>" LOC="100"; 53 | NET "A<25>" LOC="98"; 54 | NET "A<26>" LOC="97"; 55 | NET "A<27>" LOC="96"; 56 | NET "A<28>" LOC="94"; 57 | NET "A<29>" LOC="93"; 58 | NET "A<30>" LOC="91"; 59 | NET "A<31>" LOC="88"; 60 | NET "ACTIVE" LOC="35"; 61 | NET "ARAM<0>" LOC="25"; 62 | NET "ARAM<1>" LOC="26"; 63 | NET "ARAM<2>" LOC="27"; 64 | NET "ARAM<3>" LOC="28"; 65 | NET "ARAM<4>" LOC="14"; 66 | NET "ARAM<5>" LOC="13"; 67 | NET "ARAM<6>" LOC="12"; 68 | NET "ARAM<7>" LOC="11"; 69 | NET "ARAM<8>" LOC="10"; 70 | NET "ARAM<9>" LOC="9"; 71 | NET "ARAM<10>" LOC="24"; 72 | NET "ARAM<11>" LOC="7"; 73 | NET "ARAM<12>" LOC="6"; 74 | NET "AS20" LOC="132"; 75 | NET "AS30" LOC="74"; 76 | NET "DISABLE" LOC="39"; 77 | NET AUXGND LOC="38"; 78 | #NET "AUX<2>" LOC="40"; 79 | NET "BA<0>" LOC="23"; 80 | NET "BA<1>" LOC="22"; 81 | NET "BERR" LOC="75"; 82 | NET "BG20" LOC="138"; 83 | NET "BG30" LOC="86"; 84 | NET "BGACK30" LOC="92"; 85 | NET "BR20" LOC="137"; 86 | NET "BR30" LOC="83"; 87 | NET "CAS" LOC="19"; 88 | NET "CBACK" LOC="70"; 89 | NET "CBREQ" LOC="66"; 90 | NET "CIIN" LOC="60"; 91 | NET "CLKCPU" LOC="80"; 92 | NET "CLKRAM" LOC="4"; 93 | NET "CLKRAME" LOC="5"; 94 | NET "D<24>" LOC="52"; 95 | NET "D<25>" LOC="51"; 96 | NET "D<26>" LOC="50"; 97 | NET "D<27>" LOC="49"; 98 | NET "D<28>" LOC="48"; 99 | NET "D<29>" LOC="46"; 100 | NET "D<30>" LOC="45"; 101 | NET "D<31>" LOC="44"; 102 | NET "DQM<0>" LOC="16"; 103 | NET "DQM<1>" LOC="31"; 104 | NET "DQM<2>" LOC="15"; 105 | NET "DQM<3>" LOC="3"; 106 | NET "DS20" LOC="133"; 107 | NET "DS30" LOC="68"; 108 | NET "DS30ACK<0>" LOC="79"; 109 | NET "DS30ACK<1>" LOC="78"; 110 | NET "DSACK<0>" LOC="135"; 111 | NET "DSACK<1>" LOC="136"; 112 | NET "EXP_BG" LOC="139"; 113 | NET "EXP_BR" LOC="140"; 114 | NET "FC<0>" LOC="85"; 115 | NET "FC<1>" LOC="82"; 116 | NET "FC<2>" LOC="81"; 117 | NET "HALT" LOC="76"; 118 | NET "IDECS<0>" LOC="58"; 119 | NET "IDECS<1>" LOC="59"; 120 | NET "IDEINT" LOC="57"; 121 | NET "IDELED" LOC="71"; 122 | NET "IDEWAIT" LOC="56"; 123 | NET "INT2" LOC="143"; 124 | NET "IOR" LOC="54"; 125 | NET "IOW" LOC="53"; 126 | NET "PUNT" LOC="142"; 127 | NET "RAMCS" LOC="21"; 128 | NET "RAMOE" LOC="2"; 129 | NET "RAMWE" LOC="17"; 130 | NET "RAS" LOC="20"; 131 | NET "RESET" LOC="40"; 132 | NET "RW20" LOC="134"; 133 | NET "RW30" LOC="64"; 134 | NET "RXD" LOC="34"; 135 | NET "RXD_EXT" LOC="43"; 136 | NET "SIZ<0>" LOC="61"; 137 | NET "SIZ<1>" LOC="69"; 138 | NET "STERM" LOC="77"; 139 | NET "TXD" LOC="33"; 140 | NET "TXD_EXT" LOC="41"; 141 | -------------------------------------------------------------------------------- /boards/tf330r1/tf330r1.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /boards/tf330r1/tf330r1_main.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2016-2017, Stephen J. Leary 2 | # All rights reserved. 3 | # 4 | # This file is part of TF330/TF120 (Terrible Fire 030 Accelerator) 5 | # 6 | # TF330/TF120 is free software: you can redistribute it and/or modify 7 | # it under the terms of the GNU General Public License as published by 8 | # the Free Software Foundation, either version 3 of the License, or 9 | # (at your option) any later version. 10 | # 11 | # TF330/TF120 is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | # You should have received a copy of the GNU General Public License 17 | # along with TF330/TF120. If not, see . 18 | #Clocks 19 | NET "CLK100M" LOC="32"; 20 | NET "CLK100M" BUFG=CLK; 21 | NET "CLK100M" TNM_NET = "CLK100M"; # gives the net clk a group name as CLK100M 22 | 23 | NET "CLK14M" LOC="30"; 24 | NET "CLK14M" BUFG=CLK; 25 | NET "CLK14M" TNM_NET = "CLK14M"; # gives the net clk a group name as CLK14M 26 | 27 | NET "A<0>" LOC="87"; 28 | NET "A<1>" LOC="95"; 29 | NET "A<2>" LOC="128"; 30 | NET "A<3>" LOC="126"; 31 | NET "A<4>" LOC="125"; 32 | NET "A<5>" LOC="124"; 33 | NET "A<6>" LOC="121"; 34 | NET "A<7>" LOC="120"; 35 | NET "A<8>" LOC="119"; 36 | NET "A<9>" LOC="118"; 37 | NET "A<10>" LOC="117"; 38 | NET "A<11>" LOC="116"; 39 | NET "A<12>" LOC="113"; 40 | NET "A<13>" LOC="115"; 41 | NET "A<14>" LOC="112"; 42 | NET "A<15>" LOC="111"; 43 | NET "A<16>" LOC="110"; 44 | NET "A<17>" LOC="107"; 45 | NET "A<18>" LOC="106"; 46 | NET "A<19>" LOC="105"; 47 | NET "A<20>" LOC="104"; 48 | NET "A<21>" LOC="103"; 49 | NET "A<22>" LOC="102"; 50 | NET "A<23>" LOC="101"; 51 | NET "A<24>" LOC="100"; 52 | NET "A<25>" LOC="98"; 53 | NET "A<26>" LOC="97"; 54 | NET "A<27>" LOC="96"; 55 | NET "A<28>" LOC="94"; 56 | NET "A<29>" LOC="93"; 57 | NET "A<30>" LOC="91"; 58 | NET "A<31>" LOC="88"; 59 | NET "ACTIVE" LOC="35"; 60 | NET "ARAM<0>" LOC="25"; 61 | NET "ARAM<1>" LOC="26"; 62 | NET "ARAM<2>" LOC="27"; 63 | NET "ARAM<3>" LOC="28"; 64 | NET "ARAM<4>" LOC="14"; 65 | NET "ARAM<5>" LOC="13"; 66 | NET "ARAM<6>" LOC="12"; 67 | NET "ARAM<7>" LOC="11"; 68 | NET "ARAM<8>" LOC="10"; 69 | NET "ARAM<9>" LOC="9"; 70 | NET "ARAM<10>" LOC="24"; 71 | NET "ARAM<11>" LOC="7"; 72 | NET "ARAM<12>" LOC="6"; 73 | NET "AS20" LOC="133"; 74 | NET "AS30" LOC="74"; 75 | NET "EXP_BG" LOC="39"; 76 | NET "EXP_BR" LOC="38"; 77 | NET "BA<0>" LOC="23"; 78 | NET "BA<1>" LOC="22"; 79 | NET "BERR" LOC="75"; 80 | NET "BG20" LOC="139"; 81 | NET "BG30" LOC="86"; 82 | NET "BGACK20" LOC="140"; 83 | NET "BGACK30" LOC="92"; 84 | NET "BR20" LOC="138"; 85 | NET "BR30" LOC="83"; 86 | NET "CAS" LOC="19"; 87 | NET "CBACK" LOC="70"; 88 | NET "CBREQ" LOC="66"; 89 | NET "CIIN" LOC="60"; 90 | #NET "CLK14M" LOC="30"; 91 | #NET "CLK100M" LOC="32"; 92 | NET "CLKCPU" LOC="80"; 93 | NET "CLKRAM" LOC="4"; 94 | NET "CLKRAME" LOC="5"; 95 | NET "D<24>" LOC="52"; 96 | NET "D<25>" LOC="51"; 97 | NET "D<26>" LOC="50"; 98 | NET "D<27>" LOC="49"; 99 | NET "D<28>" LOC="48"; 100 | NET "D<29>" LOC="46"; 101 | NET "D<30>" LOC="45"; 102 | NET "D<31>" LOC="44"; 103 | NET "DQM<0>" LOC="16"; 104 | NET "DQM<1>" LOC="31"; 105 | NET "DQM<2>" LOC="15"; 106 | NET "DQM<3>" LOC="3"; 107 | NET "DS20" LOC="134"; 108 | NET "DS30" LOC="68"; 109 | NET "DS30ACK<0>" LOC="79"; 110 | NET "DS30ACK<1>" LOC="78"; 111 | NET "DSACK<0>" LOC="136"; 112 | NET "DSACK<1>" LOC="137"; 113 | NET "FC<0>" LOC="85"; 114 | NET "FC<1>" LOC="82"; 115 | NET "FC<2>" LOC="81"; 116 | NET "HALT" LOC="76"; 117 | NET "IDECS<0>" LOC="58"; 118 | NET "IDECS<1>" LOC="59"; 119 | NET "IDEINT" LOC="57"; 120 | NET "IDELED" LOC="71"; 121 | NET "IDEWAIT" LOC="56"; 122 | NET "INT2" LOC="143"; 123 | NET "IOR" LOC="54"; 124 | NET "IOW" LOC="53"; 125 | NET "IPL<0>" LOC="132"; 126 | NET "IPL<1>" LOC="131"; 127 | NET "IPL<2>" LOC="130"; 128 | NET "PUNT" LOC="142"; 129 | NET "RAMCS" LOC="21"; 130 | NET "RAMOE" LOC="2"; 131 | NET "RAMWE" LOC="17"; 132 | NET "RAS" LOC="20"; 133 | NET "RESET" LOC="129"; 134 | NET "RW20" LOC="135"; 135 | NET "RW30" LOC="64"; 136 | NET "RXD" LOC="34"; 137 | NET "RXD_EXT" LOC="43"; 138 | NET "SIZ<0>" LOC="61"; 139 | NET "SIZ<1>" LOC="69"; 140 | NET "STERM" LOC="77"; 141 | NET "TXD" LOC="33"; 142 | NET "TXD_EXT" LOC="41"; 143 | -------------------------------------------------------------------------------- /boards/tf330r1/tf330r1_main_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | Copyright (c) 2018, Stephen J. Leary 5 | All rights reserved. 6 | 7 | Redistribution and use in source and binary forms, with or without 8 | modification, are permitted provided that the following conditions are met: 9 | 1. Redistributions of source code must retain the above copyright 10 | notice, this list of conditions and the following disclaimer. 11 | 2. Redistributions in binary form must reproduce the above copyright 12 | notice, this list of conditions and the following disclaimer in the 13 | documentation and/or other materials provided with the distribution. 14 | 3. All advertising materials mentioning features or use of this software 15 | must display the following acknowledgement: 16 | This product includes software developed by the . 17 | 4. Neither the name of the nor the 18 | names of its contributors may be used to endorse or promote products 19 | derived from this software without specific prior written permission. 20 | 21 | THIS SOFTWARE IS PROVIDED BY ''AS IS'' AND ANY 22 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 | DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY 25 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | 32 | */ 33 | 34 | module tf330r1_main_top( 35 | 36 | inout RESET, 37 | inout HALT, 38 | 39 | // all clock lines. 40 | inout CLK14M, 41 | inout CLK100M, 42 | inout CLKCPU, 43 | inout CLKRAM, 44 | 45 | inout [31:0] A, 46 | inout [31:24] D, 47 | 48 | // SDRAM Control 49 | inout CLKRAME, 50 | inout [12:0] ARAM, 51 | inout [1:0] BA, 52 | inout CAS, 53 | inout [3:0] DQM, 54 | inout RAMWE, 55 | inout RAS, 56 | inout RAMCS, 57 | inout RAMOE, 58 | 59 | // transfer control lines 60 | inout [1:0] SIZ, 61 | inout [2:0] FC, 62 | inout[2:0] IPL, 63 | 64 | // cache control lines. 65 | inout CBREQ, 66 | inout CBACK, 67 | inout CIIN, 68 | 69 | // 68030 control lines 70 | inout AS30, 71 | inout DS30, 72 | inout RW30, 73 | 74 | inout [1:0] DS30ACK, 75 | inout STERM, 76 | 77 | inout BGACK30, 78 | inout BR30, 79 | inout BG30, 80 | 81 | // CD32 / 68020 control lines 82 | inout AS20, 83 | inout DS20, 84 | inout RW20, 85 | 86 | inout BR20, 87 | inout BG20, 88 | inout BGACK20, 89 | 90 | inout [1:0] DSACK, 91 | 92 | inout IOW, 93 | inout IOR, 94 | 95 | inout IDEINT, 96 | inout IDEWAIT, 97 | inout [1:0] IDECS, 98 | inout PUNT, 99 | inout BERR, 100 | 101 | inout EXP_BR, 102 | inout EXP_BG, 103 | 104 | inout INT2, 105 | inout IDELED, 106 | inout ACTIVE, 107 | 108 | inout RXD, 109 | inout RXD_EXT, 110 | 111 | inout TXD, 112 | inout TXD_EXT 113 | ); 114 | 115 | // Instantiate the module 116 | main_top MAIN ( 117 | .RESET(RESET), 118 | .DISABLE(1'b0), 119 | .HALT(HALT), 120 | .CLK14M(CLK14M), 121 | .CLK100M(CLK100M), 122 | .CLKCPU(CLKCPU), 123 | .CLKRAM(CLKRAM), 124 | .A(A), 125 | .D(D), 126 | .CLKRAME(CLKRAME), 127 | .ARAM(ARAM), 128 | .BA(BA), 129 | .CAS(CAS), 130 | .DQM(DQM), 131 | .RAMWE(RAMWE), 132 | .RAS(RAS), 133 | .RAMCS(RAMCS), 134 | .RAMOE(RAMOE), 135 | .SIZ(SIZ), 136 | .FC(FC), 137 | .IPL(IPL), 138 | .CBREQ(CBREQ), 139 | .CBACK(CBACK), 140 | .CIIN(CIIN), 141 | .AS30(AS30), 142 | .DS30(DS30), 143 | .RW30(RW30), 144 | .DS30ACK(DS30ACK), 145 | .STERM(STERM), 146 | .BGACK30(BGACK30), 147 | .BR30(BR30), 148 | .BG30(BG30), 149 | .AS20(AS20), 150 | .DS20(DS20), 151 | .RW20(RW20), 152 | .BR20(BR20), 153 | .BG20(BG20), 154 | .BGACK20(BGACK20), 155 | .DSACK(DSACK), 156 | .IOW(IOW), 157 | .IOR(IOR), 158 | .IDEINT(IDEINT), 159 | .IDEWAIT(IDEWAIT), 160 | .IDECS(IDECS), 161 | .PUNT(PUNT), 162 | .BERR(BERR), 163 | .EXP_BR(EXP_BR), 164 | .EXP_BG(EXP_BG), 165 | .INT2(INT2), 166 | .IDELED(IDELED), 167 | .ACTIVE(ACTIVE), 168 | .RXD(RXD), 169 | .RXD_EXT(RXD_EXT), 170 | .TXD(TXD), 171 | .TXD_EXT(TXD_EXT) 172 | ); 173 | 174 | 175 | endmodule 176 | -------------------------------------------------------------------------------- /boards/tf330r3/tf330r3_main_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | Copyright (c) 2018, Stephen J. Leary 5 | All rights reserved. 6 | 7 | Redistribution and use in source and binary forms, with or without 8 | modification, are permitted provided that the following conditions are met: 9 | 1. Redistributions of source code must retain the above copyright 10 | notice, this list of conditions and the following disclaimer. 11 | 2. Redistributions in binary form must reproduce the above copyright 12 | notice, this list of conditions and the following disclaimer in the 13 | documentation and/or other materials provided with the distribution. 14 | 3. All advertising materials mentioning features or use of this software 15 | must display the following acknowledgement: 16 | This product includes software developed by the . 17 | 4. Neither the name of the nor the 18 | names of its contributors may be used to endorse or promote products 19 | derived from this software without specific prior written permission. 20 | 21 | THIS SOFTWARE IS PROVIDED BY ''AS IS'' AND ANY 22 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 | DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY 25 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | 32 | */ 33 | 34 | module tf330r3_main_top( 35 | 36 | inout RESET, 37 | inout HALT, 38 | 39 | inout DISABLE, 40 | output AUXGND, 41 | 42 | // all clock lines. 43 | inout CLK14M, 44 | inout CLK100M, 45 | inout CLKCPU, 46 | inout CLKRAM, 47 | 48 | inout [31:0] A, 49 | inout [31:24] D, 50 | 51 | // SDRAM Control 52 | inout CLKRAME, 53 | inout [12:0] ARAM, 54 | inout [1:0] BA, 55 | inout CAS, 56 | inout [3:0] DQM, 57 | inout RAMWE, 58 | inout RAS, 59 | inout RAMCS, 60 | inout RAMOE, 61 | 62 | // transfer control lines 63 | inout [1:0] SIZ, 64 | inout [2:0] FC, 65 | inout[2:0] IPL, 66 | 67 | // cache control lines. 68 | inout CBREQ, 69 | inout CBACK, 70 | inout CIIN, 71 | 72 | // 68030 control lines 73 | inout AS30, 74 | inout DS30, 75 | inout RW30, 76 | 77 | inout [1:0] DS30ACK, 78 | inout STERM, 79 | 80 | inout BGACK30, 81 | inout BR30, 82 | inout BG30, 83 | 84 | // CD32 / 68020 control lines 85 | inout AS20, 86 | inout DS20, 87 | inout RW20, 88 | 89 | inout BR20, 90 | inout BG20, 91 | inout BGACK20, 92 | 93 | inout [1:0] DSACK, 94 | 95 | inout IOW, 96 | inout IOR, 97 | 98 | inout IDEINT, 99 | inout IDEWAIT, 100 | inout [1:0] IDECS, 101 | inout PUNT, 102 | inout BERR, 103 | 104 | inout EXP_BR, 105 | inout EXP_BG, 106 | 107 | inout INT2, 108 | inout IDELED, 109 | inout ACTIVE, 110 | 111 | inout RXD, 112 | inout RXD_EXT, 113 | 114 | inout TXD, 115 | inout TXD_EXT 116 | ); 117 | 118 | // Instantiate the module 119 | main_top MAIN ( 120 | .RESET(RESET), 121 | .HALT(HALT), 122 | .DISABLE(DISABLE), 123 | .CLK14M(CLK14M), 124 | .CLK100M(CLK100M), 125 | .CLKCPU(CLKCPU), 126 | .CLKRAM(CLKRAM), 127 | .A(A), 128 | .D(D), 129 | .CLKRAME(CLKRAME), 130 | .ARAM(ARAM), 131 | .BA(BA), 132 | .CAS(CAS), 133 | .DQM(DQM), 134 | .RAMWE(RAMWE), 135 | .RAS(RAS), 136 | .RAMCS(RAMCS), 137 | .RAMOE(RAMOE), 138 | .SIZ(SIZ), 139 | .FC(FC), 140 | .IPL(IPL), 141 | .CBREQ(CBREQ), 142 | .CBACK(CBACK), 143 | .CIIN(CIIN), 144 | .AS30(AS30), 145 | .DS30(DS30), 146 | .RW30(RW30), 147 | .DS30ACK(DS30ACK), 148 | .STERM(STERM), 149 | .BGACK30(BGACK30), 150 | .BR30(BR30), 151 | .BG30(BG30), 152 | .AS20(AS20), 153 | .DS20(DS20), 154 | .RW20(RW20), 155 | .BR20(BR20), 156 | .BG20(BG20), 157 | .BGACK20(BGACK20), 158 | .DSACK(DSACK), 159 | .IOW(IOW), 160 | .IOR(IOR), 161 | .IDEINT(IDEINT), 162 | .IDEWAIT(IDEWAIT), 163 | .IDECS(IDECS), 164 | .PUNT(PUNT), 165 | .BERR(BERR), 166 | .EXP_BR(EXP_BR), 167 | .EXP_BG(EXP_BG), 168 | .INT2(INT2), 169 | .IDELED(IDELED), 170 | .ACTIVE(ACTIVE), 171 | .RXD(RXD), 172 | .RXD_EXT(RXD_EXT), 173 | .TXD(TXD), 174 | .TXD_EXT(TXD_EXT) 175 | ); 176 | 177 | assign AUXGND = 1'b0; 178 | 179 | endmodule 180 | -------------------------------------------------------------------------------- /rtl/fastata.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | Copyright (C) 2016-2017, Stephen J. Leary 4 | All rights reserved. 5 | 6 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 7 | 8 | Attribution-NoDerivs 3.0 Unported 9 | 10 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 11 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 12 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 13 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 14 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 15 | DAMAGES RESULTING FROM ITS USE. 16 | 17 | */ 18 | 19 | module fastata ( 20 | input CLK, 21 | input RESET, 22 | input TS, 23 | input RW, 24 | input [31:0] A, 25 | input IDEWAIT, 26 | 27 | output [1:0] IDECS, 28 | output IOR, 29 | output IOW, 30 | output TA, 31 | output ACCESS 32 | ); 33 | 34 | /* Timing Diagram 35 | S0 S1 S2 S3 S4 S5 W W S6 S7 36 | __ __ __ __ __ __ __ __ __ __ __ __ 37 | CLK | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__ 38 | _________________ _____________________________ 39 | AS \\\_____________________/ 40 | _______________ _____________________________ 41 | CS \__________________________/ 42 | ______________________ _____________________________ 43 | IOR \___________________/ 44 | _____________________________ ___________________________________ 45 | IOW \______/ 46 | _____________________________ ___________________________________ 47 | DTACK \______/ 48 | _________________________ ________________________________________ 49 | WAIT \_____/ 50 | 51 | */ 52 | 53 | parameter IDE_DOUBLER = 0; 54 | 55 | `ifndef A1200 56 | wire IDE_ACCESS = ({A[31:15]} != {16'h00DA,1'b0}); 57 | `else 58 | wire IDE_ACCESS = ({A[31:14]} != {16'h00DA,2'b01}); 59 | `endif 60 | 61 | parameter PIO_MODE0_T1 = 2; // 70ns 62 | parameter PIO_MODE0_T2 = 5; // 290ns 63 | parameter PIO_MODE0_T4 = 1; // 30ns 64 | parameter PIO_MODE0_Teoc = 1; // 240ns 65 | 66 | reg [7:0] T = 0; 67 | 68 | localparam T0 = 'd0; 69 | localparam T1 = PIO_MODE0_T1; 70 | localparam T2 = PIO_MODE0_T1 + PIO_MODE0_T2; 71 | localparam T4 = PIO_MODE0_T1 + PIO_MODE0_T2 + PIO_MODE0_T4; 72 | localparam TEOC = PIO_MODE0_T1 + PIO_MODE0_T2 + PIO_MODE0_T4 + PIO_MODE0_Teoc; 73 | 74 | reg TS_HOLD = 1'b1; 75 | reg IOR_INT = 1'b1; 76 | reg IOW_INT = 1'b1; 77 | reg TA_INT = 1'b1; 78 | 79 | wire START = TS | IDE_ACCESS; 80 | 81 | reg t1_done; 82 | reg t2_done; 83 | reg t4_done; 84 | reg te_done; 85 | 86 | always @(posedge CLK or negedge RESET) begin 87 | 88 | if (RESET == 1'b0) begin 89 | 90 | T <= 0; 91 | TS_HOLD <= 1'b1; 92 | 93 | t1_done <= 1'b1; 94 | t2_done <= 1'b1; 95 | t4_done <= 1'b1; 96 | te_done <= 1'b1; 97 | 98 | end else begin 99 | 100 | if (|T) begin 101 | T <= T + 'd1; 102 | if ((START|t4_done) == 1'b0) begin 103 | TS_HOLD <= 1'b0; 104 | end 105 | end 106 | 107 | // current cycle or last cycle is in progress. 108 | case (T) 109 | 110 | T0: begin // 111 | 112 | if ((START & TS_HOLD) == 1'b0) begin 113 | T <= 'd1; 114 | TS_HOLD <= 1'b1; 115 | t1_done <= 1'b1; 116 | t2_done <= 1'b1; 117 | t4_done <= 1'b1; 118 | te_done <= 1'b1; 119 | end 120 | 121 | end 122 | 123 | T1: t1_done <= 1'b0; 124 | T2: t2_done <= 1'b0; 125 | T4: t4_done <= 1'b0; 126 | TEOC: begin 127 | te_done <= 1'b0; 128 | T <= T0; 129 | end 130 | 131 | endcase 132 | 133 | end 134 | 135 | end 136 | 137 | 138 | reg [1:0] IDECS_INT; 139 | reg t4_done_d; 140 | reg t4_done_d2; 141 | 142 | always @(posedge CLK or negedge RESET) begin 143 | 144 | if (RESET == 1'b0) begin 145 | 146 | IDECS_INT <= 2'b11; 147 | IOR_INT <= 1'b1; 148 | IOW_INT <= 1'b1; 149 | TA_INT <= 1'b1; 150 | t4_done_d <= 1'b1; 151 | t4_done_d2 <= 1'b1; 152 | 153 | end else begin 154 | 155 | IDECS_INT <= A[12] ? {IDE_ACCESS, 1'b1} : {1'b1, IDE_ACCESS}; 156 | IOR_INT <= (~RW | t1_done | ~t2_done); 157 | IOW_INT <= ( RW | t1_done | ~t2_done); 158 | TA_INT <= t4_done | ~t4_done_d2; 159 | t4_done_d <= t4_done; 160 | t4_done_d2 <= t4_done_d; 161 | 162 | end 163 | 164 | end 165 | 166 | assign TA = TA_INT; 167 | assign IOR = IOR_INT; 168 | assign IOW = IOW_INT; 169 | assign IDECS = IDECS_INT; 170 | assign ACCESS = IDE_ACCESS; 171 | 172 | endmodule 173 | -------------------------------------------------------------------------------- /rtl/main_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | Copyright (C) 2016-2017, Stephen J. Leary 5 | All rights reserved. 6 | 7 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 8 | 9 | Attribution-NoDerivs 3.0 Unported 10 | 11 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 12 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 13 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 14 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 15 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 16 | DAMAGES RESULTING FROM ITS USE. 17 | 18 | */ 19 | 20 | module main_top( 21 | 22 | input RESET, 23 | output HALT, 24 | 25 | input DISABLE, 26 | 27 | // all clock lines. 28 | input CLK14M, 29 | input CLK100M, 30 | output CLKCPU, 31 | output CLKRAM, 32 | 33 | input [31:0] A, 34 | inout [31:24] D, 35 | 36 | // SDRAM Control 37 | output CLKRAME, 38 | output [12:0] ARAM, 39 | output [1:0] BA, 40 | output CAS, 41 | output [3:0] DQM, 42 | output RAMWE, 43 | output RAS, 44 | output RAMCS, 45 | output RAMOE, 46 | 47 | // transfer control lines 48 | input [1:0] SIZ, 49 | input [2:0] FC, 50 | output[2:0] IPL, 51 | 52 | // cache control lines. 53 | input CBREQ, 54 | output CBACK, 55 | output CIIN, 56 | 57 | // 68030 control lines 58 | input AS30, 59 | input DS30, 60 | input RW30, 61 | 62 | output [1:0] DS30ACK, 63 | output STERM, 64 | 65 | output BGACK30, 66 | output BR30, 67 | input BG30, 68 | 69 | // CD32 / 68020 control lines 70 | output AS20, 71 | output DS20, 72 | output RW20, 73 | 74 | output BR20, 75 | input BG20, 76 | 77 | input [1:0] DSACK, 78 | 79 | output IOW, 80 | output IOR, 81 | 82 | input IDEINT, 83 | input IDEWAIT, 84 | output [1:0] IDECS, 85 | output PUNT, 86 | output BERR, 87 | 88 | input EXP_BR, 89 | output EXP_BG, 90 | 91 | output INT2, 92 | input IDELED, 93 | output ACTIVE, 94 | 95 | output RXD, 96 | output RXD_EXT, 97 | 98 | input TXD, 99 | input TXD_EXT 100 | ); 101 | 102 | reg HIGHZ; 103 | reg BGACK_INT; 104 | 105 | reg ram_access; 106 | reg PUNT_INT; 107 | wire CPUSPACE = &FC; 108 | wire FPUOP = CPUSPACE & ({A[19:16]} == {4'b0010}); 109 | wire IACK = CPUSPACE & ({A[19:16]} == {4'b1111}); 110 | wire ram_decode = ({A[31:27]} != {5'b0000_1}) & ({A[31:27]} != {5'b0001_0}) ; 111 | 112 | wire GAYLE_IDE; 113 | wire DTACK_IDE; 114 | 115 | reg SPEED_D; 116 | 117 | clocks CLOCKS( 118 | .CLK100M ( CLK100M ), 119 | .CLK14M ( CLK14M ), 120 | .SPEED ( SPEED_D ), 121 | .CLKCPU ( CLKCPU ) 122 | ); 123 | 124 | 125 | arb ARB ( 126 | 127 | .CLK ( CLKCPU ), 128 | .CLK100M ( CLK100M ), 129 | .DISABLE ( DISABLE ), 130 | 131 | .AS30 ( AS30 ), 132 | 133 | .BR20 ( BR20 ), 134 | .BG20 ( BG20 ), 135 | 136 | .BG30 ( BG30 ), 137 | .BR30 ( BR30 ), 138 | .BGACK30 ( BGACK30 ), 139 | 140 | .EXP_BG ( EXP_BG ), 141 | .EXP_BR ( EXP_BR ) 142 | 143 | ); 144 | 145 | 146 | // module to control IDE timings. 147 | ata ATA ( 148 | 149 | .CLK ( CLKCPU ), 150 | .AS ( AS30 ), 151 | .RW ( RW30 ), 152 | .A ( A ), 153 | // IDEWait not connected on TF328. 154 | .WAIT ( IDEWAIT ), 155 | 156 | .IDECS ( IDECS ), 157 | .IOR ( IOR ), 158 | .IOW ( IOW ), 159 | .DTACK ( DTACK_IDE ), 160 | .ACCESS ( GAYLE_IDE ) 161 | 162 | ); 163 | 164 | 165 | // produce an internal data strobe 166 | wire GAYLE_INT2; 167 | wire GAYLE_ACCESS; 168 | 169 | wire gayle_dout; 170 | 171 | reg GAYLE_DS; 172 | 173 | gayle GAYLE( 174 | 175 | .CLKCPU ( CLKCPU ), 176 | .RESET ( RESET ), 177 | 178 | .AS20 ( AS30 ), 179 | .DS20 ( GAYLE_DS ), 180 | .RW ( RW30 ), 181 | 182 | .A ( A ), 183 | 184 | .IDE_INT( IDEINT ), 185 | .INT2 ( GAYLE_INT2 ), 186 | .DIN ( D[31] ), 187 | 188 | .DOUT ( gayle_dout ), 189 | .ACCESS ( GAYLE_ACCESS ) 190 | 191 | ); 192 | 193 | 194 | wire [7:4] zii_dout; 195 | wire zii_decode = 1'b1; 196 | 197 | wire WAIT; 198 | 199 | 200 | sdram SDRAM ( 201 | 202 | .RESET(RESET), 203 | 204 | .CLKCPU (CLKCPU), 205 | .CLK (~CLKRAM), 206 | .CLKRAME(CLKRAME), 207 | 208 | .ACCESS(ram_access), 209 | 210 | .A(A), 211 | .SIZ(SIZ), 212 | 213 | .AS30(AS30), 214 | .RW30(RW30), 215 | .DS30(DS30), 216 | 217 | .CBACK(CBACK), 218 | .CIIN(CIIN), 219 | .CBREQ(CBREQ), 220 | 221 | .STERM(STERM), 222 | 223 | .ARAM(ARAM), 224 | .BA(BA), 225 | 226 | .CAS(CAS), 227 | .RAS(RAS), 228 | 229 | .DQM(DQM), 230 | 231 | .RAMWE(RAMWE), 232 | 233 | .WAIT ( WAIT ), 234 | .RAMCS(RAMCS) 235 | //.RAMOE(RAMOE) 236 | ); 237 | 238 | 239 | reg intcycle_dout = 1'b0; 240 | reg fastcycle_int; 241 | reg FASTCYCLE; 242 | 243 | always @(negedge CLKCPU or posedge AS30) begin 244 | 245 | if (AS30 == 1'b1) begin 246 | 247 | intcycle_dout <= 1'b0; 248 | fastcycle_int <= 1'b1; 249 | FASTCYCLE <= 1'b1; 250 | 251 | end else begin 252 | 253 | intcycle_dout <= ~(GAYLE_ACCESS & zii_decode) & RW30; 254 | fastcycle_int <= GAYLE_ACCESS & zii_decode; 255 | FASTCYCLE <= fastcycle_int; 256 | 257 | end 258 | end 259 | 260 | reg AS20_D; 261 | reg DS20_D; 262 | 263 | always @(negedge CLK100M or posedge AS30) begin 264 | 265 | if (AS30 == 1'b1) begin 266 | 267 | AS20_D <= 1'b1; 268 | DS20_D <= 1'b1; 269 | ram_access <= 1'b1; 270 | 271 | end else begin 272 | 273 | ram_access <= AS30 | ram_decode; 274 | AS20_D <= AS30 | ~SPEED_D; 275 | DS20_D <= DS30 | ~SPEED_D; 276 | GAYLE_DS <= DS30 | GAYLE_ACCESS | AS30; 277 | 278 | end 279 | 280 | end 281 | 282 | wire PUNT_COMB = GAYLE_ACCESS & ram_access & GAYLE_IDE & zii_decode; 283 | 284 | always @(posedge CLK100M) begin 285 | 286 | BGACK_INT <= (BG30 | ~AS30) & (BGACK_INT | EXP_BR) | EXP_BR; 287 | HIGHZ <= PUNT_INT & BGACK30; 288 | PUNT_INT <= PUNT_COMB; 289 | SPEED_D <= ~AS30 & ram_decode & GAYLE_IDE & GAYLE_ACCESS | ~RESET; 290 | 291 | end 292 | 293 | assign PUNT = PUNT_INT ? 1'bz : 1'b0; 294 | assign INT2 = GAYLE_INT2 ? 1'bz : 1'b0; 295 | 296 | wire [7:0] data_out; 297 | assign data_out = GAYLE_ACCESS ? 8'bzzzz_zzzz : {gayle_dout,7'b000_0000}; 298 | assign data_out = zii_decode ? 8'bzzzz_zzzz : {zii_dout, zii_dout}; 299 | 300 | assign D[31:24] = (intcycle_dout) ? data_out : 8'bzzzzzzzz; 301 | 302 | assign CLKRAM = CLK100M; 303 | assign DS30ACK = {FASTCYCLE & DTACK_IDE, 1'b1} & (DSACK) | {2{IACK}}; 304 | 305 | assign AS20 = HIGHZ ? AS20_D : 1'bz; 306 | assign DS20 = HIGHZ ? DS20_D : 1'bz; 307 | assign RW20 = HIGHZ ? RW30 : 1'bz; 308 | 309 | assign HALT = 1'b1; 310 | assign BERR = 1'bz; 311 | 312 | // setup the serial port pass through 313 | assign RXD_EXT = TXD; 314 | assign RXD = TXD_EXT ? 1'bz : 1'b0; 315 | 316 | assign D[31:24] = 8'bzzzzzzzz; 317 | assign IPL = 3'bzzz; 318 | 319 | assign RAMOE = 1'b0; 320 | assign ACTIVE = IDELED ? 1'bz : 1'b0; 321 | 322 | endmodule 323 | -------------------------------------------------------------------------------- /rtl/sdram.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | Copyright (C) 2016-2017, Stephen J. Leary 4 | All rights reserved. 5 | 6 | This file is part of TF330/TF120 (Terrible Fire 030 Accelerator). 7 | 8 | Attribution-NoDerivs 3.0 Unported 9 | 10 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 11 | LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN 12 | ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS 13 | INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES 14 | REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR 15 | DAMAGES RESULTING FROM ITS USE. 16 | 17 | */ 18 | 19 | 20 | module sdram( 21 | 22 | input RESET, 23 | input CLKCPU, 24 | input CLK, 25 | input ACCESS, 26 | 27 | input [31:0] A, 28 | input [1:0] SIZ, 29 | 30 | input AS30, 31 | input RW30, 32 | input DS30, 33 | 34 | // cache and burst control 35 | output CBACK, 36 | output CIIN, 37 | input CBREQ, 38 | output STERM, 39 | output WAIT, 40 | 41 | // ram chip control 42 | // SDRAM Control 43 | output CLKRAME, 44 | output [12:0] ARAM, 45 | output [1:0] BA, 46 | output CAS, 47 | output [3:0] DQM, 48 | output RAMWE, 49 | output RAS, 50 | output RAMCS, 51 | output RAMOE, 52 | output [(12*8)-1:0] COMMANDNAME 53 | 54 | 55 | ); 56 | 57 | `include "sdram_defines.v" 58 | 59 | wire ready; 60 | 61 | wire init_clke; 62 | wire [3:0] init_command; 63 | wire [12:0] init_address; 64 | 65 | reg STERM_D; 66 | reg WAITSTATE; 67 | 68 | reg [3:0] command = CMD_NOP; 69 | reg [3:0] cycle = 'd0; 70 | reg [1:0] bank = 0; 71 | reg [12:0] address = 0; 72 | 73 | wire refresh; 74 | 75 | assign COMMANDNAME = cmd_name(ready ? init_command : command); 76 | 77 | localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 78 | 79 | sdram_init # 80 | ( 81 | .MODE(MODE) 82 | ) 83 | INIT( 84 | 85 | .CLK ( CLK ), 86 | .CLKE ( init_clke ), 87 | .RESET ( RESET ), 88 | 89 | .CMD ( init_command ), 90 | .ARAM ( init_address ), 91 | .READY ( ready ), 92 | .REFRESH( refresh ) 93 | 94 | ); 95 | 96 | reg refresh_d; 97 | reg refresh_req; 98 | 99 | localparam CYCLE_ACCESS = 'b0; 100 | localparam CYCLE_REFRESH = 'b1; 101 | 102 | localparam CYCLE_REFRESH_PRECHARGE = 5'b10001; 103 | localparam CYCLE_REFRESH_AUTOREFRESH = CYCLE_REFRESH_PRECHARGE + RP_DELAY; 104 | localparam CYCLE_REFRESH_COMPLETE = CYCLE_REFRESH_AUTOREFRESH + RFC_DELAY; 105 | localparam CYCLE_ACCESS_START = 5'b00000; 106 | localparam CYCLE_ACCESS_RW = CYCLE_ACCESS_START + RASCAS_DELAY; 107 | localparam CYCLE_ACCESS_COMPLETE = CYCLE_ACCESS_RW + 'd1; 108 | localparam CYCLE_ACCESS_BW1 = CYCLE_ACCESS_COMPLETE + 1'd1; 109 | localparam CYCLE_ACCESS_BW2 = CYCLE_ACCESS_BW1 + 1'd1; 110 | 111 | reg BURSTING = 1'b0; 112 | reg [1:0] BCOUNT = 2'b11; 113 | 114 | // a read cycle at a tag aligned address. 115 | wire CAN_BURST = ({A[3:2]} != 2'b00) | CBREQ | ACCESS | ~RW30; 116 | wire [1:0] RAMA = BURSTING ? {A[3:2]} : BCOUNT; 117 | 118 | wire BURST_ENDING = (BCOUNT == 2'b11) | BURSTING; 119 | 120 | reg cycle_type; 121 | reg can_start; 122 | 123 | reg WAIT_BLOCK = 1'b1; 124 | reg [3:0] DQM_D; 125 | 126 | always @(posedge CLK or negedge RESET) begin 127 | 128 | if (RESET == 1'b0) begin 129 | 130 | command <= CMD_NOP; 131 | address <= 'd0; 132 | bank <= 'd0; 133 | refresh_req <= 'b1; 134 | refresh_d <= 'b0; 135 | cycle <= 'd0; 136 | cycle_type <= 'd0; 137 | 138 | end else begin 139 | 140 | command <= CMD_NOP; 141 | 142 | DQM_D[3] <= ACCESS | ~RW30 & (A[1] | A[0]); 143 | DQM_D[2] <= ACCESS | ~RW30 & ((~SIZ[1] & SIZ[0] & ~A[0]) | A[1]); 144 | DQM_D[1] <= ACCESS | ~RW30 & ((SIZ[1] & ~SIZ[0] & ~A[1] & ~A[0]) | (~SIZ[1] & SIZ[0] & ~A[1]) |(A[1] & A[0])); 145 | DQM_D[0] <= ACCESS | ~RW30 & ((~SIZ[1] & SIZ[0] & ~A[1] ) | (~SIZ[1] & SIZ[0] & ~A[0] ) | (SIZ[1] & ~A[1] & ~A[0] ) | (SIZ[1] & ~SIZ[0] & ~A[1])); 146 | 147 | if (AS30 == 1'b1) begin 148 | 149 | can_start <= 1'b0; 150 | 151 | end 152 | 153 | // is a refresh required? 154 | refresh_d <= refresh; 155 | if ({refresh, refresh_d} == 2'b01) refresh_req <= 1'b0; 156 | 157 | if (cycle == 'd0) begin 158 | 159 | WAIT_BLOCK <= 1'b1; 160 | BURSTING <= 1'b1; 161 | BCOUNT <= 'd0; 162 | 163 | if ((ready | can_start) == 1'b0) begin 164 | 165 | address <= { A[23:11] }; 166 | 167 | if (refresh_req == 1'b0) begin 168 | 169 | cycle_type <= CYCLE_REFRESH; 170 | cycle[0] <= 'd1; 171 | 172 | end else if ((ACCESS | AS30) == 1'b0) begin 173 | 174 | BURSTING <= CAN_BURST; 175 | cycle_type <= CYCLE_ACCESS; 176 | can_start <= 1'b1; 177 | cycle[0] <= 'd1; 178 | 179 | address <= { A[23:11] }; 180 | command <= CMD_ACTIVE; 181 | bank <= A[25:24]; 182 | 183 | end 184 | 185 | end 186 | 187 | end else begin 188 | 189 | // process the in progress cycle. 190 | cycle <= cycle + 'd1; 191 | 192 | casez ({cycle_type, cycle}) 193 | 194 | CYCLE_REFRESH_PRECHARGE: begin 195 | command <= CMD_PRECHARGE; 196 | address[10] <= 1'b1; // precharge all banks 197 | end 198 | 199 | CYCLE_REFRESH_AUTOREFRESH: begin 200 | address[12:9] <= { 3'b001, A[26] }; 201 | command <= CMD_AUTO_REFRESH; 202 | end 203 | 204 | CYCLE_REFRESH_COMPLETE: begin 205 | refresh_req <= 1'b1; 206 | cycle <= 'd0; 207 | end 208 | 209 | CYCLE_ACCESS_RW: begin 210 | 211 | address[9:0] <= { A[26], A[10:4], RAMA }; 212 | address[12:10] <= RW30 ? 3'b000 : 3'b001; 213 | command <= RW30 ? CMD_READ : CMD_WRITE; 214 | WAIT_BLOCK <= 'b0; 215 | end 216 | 217 | CYCLE_ACCESS_COMPLETE: begin 218 | 219 | address[9:0] <= { A[26], A[10:4], RAMA }; 220 | address[12:10] <= BURST_ENDING ? 3'b001 : 3'b000; // AUTO PRECHARGE ? 221 | command <= RW30 ? CMD_READ : CMD_NOP; 222 | BCOUNT <= BCOUNT + 'd1; 223 | cycle <= BURST_ENDING ? 'd0 : CYCLE_ACCESS_BW1[3:0]; 224 | 225 | end 226 | 227 | CYCLE_ACCESS_BW1: begin 228 | WAIT_BLOCK <= 'b1; 229 | end 230 | 231 | CYCLE_ACCESS_BW2: begin 232 | cycle <= CYCLE_ACCESS_RW[3:0]; 233 | end 234 | 235 | default: begin 236 | command <= CMD_NOP; 237 | end 238 | 239 | endcase 240 | 241 | end 242 | 243 | end 244 | 245 | end 246 | 247 | always @(posedge CLKCPU or posedge AS30) begin 248 | 249 | if (AS30 == 1'b1) begin 250 | 251 | WAITSTATE <= 1'b1; 252 | STERM_D <= 1'b1; 253 | 254 | end else begin 255 | 256 | WAITSTATE <= ACCESS | DS30 | WAIT_BLOCK; 257 | STERM_D <= WAIT_BLOCK; 258 | 259 | end 260 | end 261 | 262 | assign RAMOE = ACCESS; 263 | assign DQM = DQM_D; 264 | 265 | assign CIIN = ~ACCESS; 266 | assign CBACK = BURSTING | CBREQ; 267 | 268 | assign RAMCS = 1'b0; 269 | assign RAS = ready ? init_command[2] : command[2]; 270 | assign CAS = ready ? init_command[1] : command[1]; 271 | assign RAMWE = ready ? init_command[0] : command[0]; 272 | 273 | assign ARAM = ready ? init_address : address; 274 | assign BA = ready ? 2'b00 : bank; 275 | assign CLKRAME = 1'b1; 276 | 277 | assign STERM = STERM_D; 278 | 279 | endmodule 280 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Creative Commons Legal Code 2 | 3 | Attribution-NoDerivs 3.0 Unported 4 | 5 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 6 | LEGAL SERVICES. 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