├── .gitignore ├── ALU.v ├── ALU_tb.v ├── BCDtoHEX.v ├── DATA_RAM.v ├── FPGA based Multi-Core Processor_Final_Report.pdf ├── INS_RAM.v ├── RAM.v ├── RAM_tb.v ├── README.md ├── SSeg.v ├── binaryToBCD.v ├── controlUnit.v ├── controlUnit_tb.v ├── cr_ie_info.json ├── hex_display.v ├── images └── speed_comparison.png ├── incRegister.v ├── incRegister_tb.v ├── matrix_generation_for_tb ├── 11_data_mem_out.txt ├── 12_convert_back.py ├── 13_answer_matrix_from_processor.txt ├── 14_compare_2_answers.py ├── 1_create_matrix.py ├── 2_matrix_in.txt ├── 3_dataCode_translate_for_tb.py ├── 4_data_mem_tb.txt ├── 5_multiply.py ├── 6_multiply_answer.txt ├── 7_assembly_code.txt ├── 8_machinecode_translation_for_tb.py └── 9_ins_mem_tb.txt ├── matrix_multiply.qpf ├── matrix_multiply.qsf ├── matrix_multiply.qws ├── matrix_multiply.sdc ├── matrix_multiply_assignment_defaults.qdf ├── matrix_multiply_nativelink_simulation.rpt ├── multi_core_processor.v ├── multi_core_processor_tb.v ├── multiplexer.v ├── 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