├── .gitignore ├── Catalog ├── .gitignore ├── AND4.cell ├── AOI21.cell ├── AOI31.cell ├── ASYNC1.cell ├── ASYNC2.cell ├── ASYNC3.cell ├── GNUmakefile ├── INV.cell ├── NAND2.cell ├── NAND3.cell ├── NOR2.cell ├── NOR3.cell ├── OAI21.cell ├── OAI31.cell ├── OR4.cell ├── doc │ ├── GNUmakefile │ ├── StdCellLib.tex │ └── docu.sh ├── popcorn │ └── INV.cell ├── stacked2_cells.mk ├── stacked3_cells.mk ├── stacked4_cells.mk └── stacked5_cells.mk ├── Docker ├── Dockerfile ├── bash.sh └── build.sh ├── Documents ├── LaTeX │ ├── AAAO222_circuit.tex │ ├── AAAO222_manpage.tex │ ├── AAAO322_circuit.tex │ ├── AAAO322_manpage.tex │ ├── AAAO332_circuit.tex │ ├── AAAO332_manpage.tex │ ├── AAAO333_circuit.tex │ ├── AAAO333_manpage.tex │ ├── AAAO432_circuit.tex │ ├── AAAO432_manpage.tex │ ├── AAAOI222_circuit.tex │ ├── AAAOI222_manpage.tex │ ├── AAAOI222_schematic.tex │ ├── AAAOI222_truthtable.tex │ ├── AAAOI322_circuit.tex │ ├── AAAOI322_manpage.tex │ ├── AAAOI322_schematic.tex │ ├── AAAOI322_truthtable.tex │ ├── AAAOI332_circuit.tex │ ├── AAAOI332_manpage.tex │ ├── AAAOI332_schematic.tex │ ├── AAAOI332_truthtable.tex │ ├── AAAOI333_circuit.tex │ ├── AAAOI333_manpage.tex │ ├── AAAOI333_schematic.tex │ ├── AAAOI333_truthtable.tex │ ├── AAAOI432_circuit.tex │ ├── AAAOI432_manpage.tex │ ├── AAO221_circuit.tex │ ├── AAO221_manpage.tex │ ├── AAO22_circuit.tex │ ├── AAO22_manpage.tex │ ├── AAO321_circuit.tex │ ├── AAO321_manpage.tex │ ├── AAO32_circuit.tex │ ├── AAO32_manpage.tex │ ├── AAO331_circuit.tex │ ├── AAO331_manpage.tex │ ├── AAO33_circuit.tex │ ├── AAO33_manpage.tex │ ├── AAO421_circuit.tex │ ├── AAO421_manpage.tex │ ├── AAO42_circuit.tex │ ├── AAO42_manpage.tex │ ├── AAO431_circuit.tex │ ├── AAO431_manpage.tex │ ├── AAO43_circuit.tex │ ├── AAO43_manpage.tex │ ├── AAO44_circuit.tex │ ├── AAO44_manpage.tex │ ├── AAOA221_circuit.tex │ ├── AAOA221_manpage.tex │ ├── AAOA321_circuit.tex │ ├── AAOA321_manpage.tex │ ├── AAOA331_circuit.tex │ ├── AAOA331_manpage.tex │ ├── AAOAI221_circuit.tex │ ├── AAOAI221_manpage.tex │ ├── AAOAI321_circuit.tex │ ├── AAOAI321_manpage.tex │ ├── AAOAI331_circuit.tex │ ├── AAOAI331_manpage.tex │ ├── AAOI221_circuit.tex │ ├── AAOI221_manpage.tex │ ├── AAOI221_schematic.tex │ ├── AAOI221_truthtable.tex │ ├── AAOI22_circuit.tex │ ├── AAOI22_manpage.tex │ ├── AAOI22_schematic.tex │ ├── AAOI22_truthtable.tex │ ├── AAOI321_circuit.tex │ ├── AAOI321_manpage.tex │ ├── AAOI321_schematic.tex │ ├── AAOI321_truthtable.tex │ ├── AAOI32_circuit.tex │ ├── AAOI32_manpage.tex │ ├── AAOI32_schematic.tex │ ├── AAOI32_truthtable.tex │ ├── AAOI331_circuit.tex │ ├── AAOI331_manpage.tex │ ├── AAOI331_schematic.tex │ ├── AAOI331_truthtable.tex │ ├── AAOI33_circuit.tex │ ├── AAOI33_manpage.tex │ ├── AAOI33_schematic.tex │ ├── AAOI33_truthtable.tex │ ├── AAOI421_circuit.tex │ ├── AAOI421_manpage.tex │ ├── AAOI42_circuit.tex │ ├── AAOI42_manpage.tex │ ├── AAOI431_circuit.tex │ ├── AAOI431_manpage.tex │ ├── AAOI43_circuit.tex │ ├── AAOI43_manpage.tex │ ├── AAOI44_circuit.tex │ ├── AAOI44_manpage.tex │ ├── AAOOA222_circuit.tex │ ├── AAOOA222_manpage.tex │ ├── AAOOAI222_circuit.tex │ ├── AAOOAI222_manpage.tex │ ├── AND2_circuit.tex │ ├── AND2_manpage.tex │ ├── AND3_circuit.tex │ ├── AND3_manpage.tex │ ├── AND4_circuit.tex │ ├── AND4_manpage.tex │ ├── AND4_schematic.tex │ ├── AND4_truthtable.tex │ ├── AO21_circuit.tex │ ├── AO21_manpage.tex │ ├── AO22_circuit.tex │ ├── AO22_manpage.tex │ ├── AO23_circuit.tex │ ├── AO23_manpage.tex │ ├── AO31_circuit.tex │ ├── AO31_manpage.tex │ ├── AO32_circuit.tex │ ├── AO32_manpage.tex │ ├── AO33_circuit.tex │ ├── AO33_manpage.tex │ ├── AO33_truthtable.tex │ ├── AO41_circuit.tex │ ├── AO41_manpage.tex │ ├── AO42_circuit.tex │ ├── AO42_manpage.tex │ ├── AO43_circuit.tex │ ├── AO43_manpage.tex │ ├── AOA211_circuit.tex │ ├── AOA211_manpage.tex │ ├── AOA212_circuit.tex │ ├── AOA212_manpage.tex │ ├── AOA221_circuit.tex │ ├── AOA221_manpage.tex │ ├── AOA311_circuit.tex │ ├── AOA311_manpage.tex │ ├── AOAI211_circuit.tex │ ├── AOAI211_manpage.tex │ ├── AOAI212_circuit.tex │ ├── AOAI212_manpage.tex │ ├── AOAI221_circuit.tex │ ├── AOAI221_manpage.tex │ ├── AOAI311_circuit.tex │ ├── AOAI311_manpage.tex │ ├── AOAO2111_circuit.tex │ ├── AOAO2111_manpage.tex │ ├── AOAO2211_circuit.tex │ ├── AOAO2211_manpage.tex │ ├── AOAO3211_circuit.tex │ ├── AOAO3211_manpage.tex │ ├── AOAOAO211111_circuit.tex │ ├── AOAOAO211111_manpage.tex │ ├── AOAOAOI211111_circuit.tex │ ├── AOAOAOI211111_manpage.tex │ ├── AOAOI2111_circuit.tex │ ├── AOAOI2111_manpage.tex │ ├── AOAOI2211_circuit.tex │ ├── AOAOI2211_manpage.tex │ ├── AOAOI3211_circuit.tex │ ├── AOAOI3211_manpage.tex │ ├── AOI21_circuit.tex │ ├── AOI21_manpage.tex │ ├── AOI21_schematic.tex │ ├── AOI21_truthtable.tex │ ├── AOI22_circuit.tex │ ├── AOI22_manpage.tex │ ├── AOI23_circuit.tex │ ├── AOI23_manpage.tex │ ├── AOI31_circuit.tex │ ├── AOI31_manpage.tex │ ├── AOI31_schematic.tex │ ├── AOI31_truthtable.tex │ ├── AOI32_circuit.tex │ ├── AOI32_manpage.tex │ ├── AOI32_schematic.tex │ ├── AOI32_truthtable.tex │ ├── AOI33_circuit.tex │ ├── AOI33_manpage.tex │ ├── AOI41_circuit.tex │ ├── AOI41_manpage.tex │ ├── AOI42_circuit.tex │ ├── AOI42_manpage.tex │ ├── AOI43_circuit.tex │ ├── AOI43_manpage.tex │ ├── AOOA212_circuit.tex │ ├── AOOA212_manpage.tex │ ├── AOOA312_circuit.tex │ ├── AOOA312_manpage.tex │ ├── AOOAI212_circuit.tex │ ├── AOOAI212_manpage.tex │ ├── AOOAI312_circuit.tex │ ├── AOOAI312_manpage.tex │ ├── BUF2_circuit.tex │ ├── BUF2_manpage.tex │ ├── BUF2_schematic.tex │ ├── BUF2_truthtable.tex │ ├── CGN2_circuit.tex │ ├── CGN2_manpage.tex │ ├── CGP2_circuit.tex │ ├── CGP2_manpage.tex │ ├── DFFEN_circuit.tex │ ├── DFFEN_manpage.tex │ ├── DFFEP_circuit.tex │ ├── DFFEP_manpage.tex │ ├── DFFERN_circuit.tex │ ├── DFFERN_manpage.tex │ ├── DFFERP_circuit.tex │ ├── DFFERP_manpage.tex │ ├── DFFESN_circuit.tex │ ├── DFFESN_manpage.tex │ ├── DFFESP_circuit.tex │ ├── DFFESP_manpage.tex │ ├── DFFN_circuit.tex │ ├── DFFN_manpage.tex │ ├── DFFP_circuit.tex │ ├── DFFP_manpage.tex │ ├── EQ2_circuit.tex │ ├── EQ2_files.tex │ ├── EQ2_manpage.tex │ ├── EQ2_schematic.tex │ ├── EQ2_truthtable.tex │ ├── FILL_manpage.tex │ ├── FILL_schematic.tex │ ├── GNUmakefile │ ├── INV_circuit.tex │ ├── INV_manpage.tex │ ├── INV_schematic.tex │ ├── INV_truthtable.tex │ ├── LATEN_circuit.tex │ ├── LATEN_manpage.tex │ ├── LATEP_circuit.tex │ ├── LATEP_manpage.tex │ ├── LATERN_circuit.tex │ ├── LATERN_manpage.tex │ ├── LATERP_circuit.tex │ ├── LATERP_manpage.tex │ ├── LATESN_circuit.tex │ ├── LATESN_manpage.tex │ ├── LATESP_circuit.tex │ ├── LATESP_manpage.tex │ ├── LATN_circuit.tex │ ├── LATN_manpage.tex │ ├── LATP_circuit.tex │ ├── LATP_manpage.tex │ ├── LATRN_circuit.tex │ ├── LATRN_manpage.tex │ ├── LATRP_circuit.tex │ ├── LATRP_manpage.tex │ ├── LATSN_circuit.tex │ ├── LATSN_manpage.tex │ ├── LATSP_circuit.tex │ ├── LATSP_manpage.tex │ ├── MUXI2_circuit.tex │ ├── MUXI2_manpage.tex │ ├── MUXI2_schematic.tex │ ├── MUXI2_truthtable.tex │ ├── MUXI4_schematic.tex │ ├── NAND2_circuit.tex │ ├── NAND2_manpage.tex │ ├── NAND2_schematic.tex │ ├── NAND2_truthtable.tex │ ├── NAND3_circuit.tex │ ├── NAND3_manpage.tex │ ├── NAND3_schematic.tex │ ├── NAND3_truthtable.tex │ ├── NAND4_circuit.tex │ ├── NAND4_manpage.tex │ ├── NOR2_circuit.tex │ ├── NOR2_manpage.tex │ ├── NOR2_schematic.tex │ ├── NOR2_truthtable.tex │ ├── NOR3_circuit.tex │ ├── NOR3_manpage.tex │ ├── NOR3_schematic.tex │ ├── NOR3_truthtable.tex │ ├── NOR4_circuit.tex │ ├── NOR4_manpage.tex │ ├── OA21_circuit.tex │ ├── OA21_manpage.tex │ ├── OA22_circuit.tex │ ├── OA22_manpage.tex │ ├── OA23_circuit.tex │ ├── OA23_manpage.tex │ ├── OA23_truthtable.tex │ ├── OA31_circuit.tex │ ├── OA31_manpage.tex │ ├── OA32_circuit.tex │ ├── OA32_manpage.tex │ ├── OA33_circuit.tex │ ├── OA33_manpage.tex │ ├── OA41_circuit.tex │ ├── OA41_manpage.tex │ ├── OA43_circuit.tex │ ├── OA43_manpage.tex │ ├── OAAAO2232_circuit.tex │ ├── OAAAO2232_manpage.tex │ ├── OAAAOI2232_circuit.tex │ ├── OAAAOI2232_manpage.tex │ ├── OAAO2121_circuit.tex │ ├── OAAO2121_manpage.tex │ ├── OAAO212_circuit.tex │ ├── OAAO212_manpage.tex │ ├── OAAO2221_circuit.tex │ ├── OAAO2221_manpage.tex │ ├── OAAO222_circuit.tex │ ├── OAAO222_manpage.tex │ ├── OAAO2231_circuit.tex │ ├── OAAO2231_manpage.tex │ ├── OAAO223_circuit.tex │ ├── OAAO223_manpage.tex │ ├── OAAO232_circuit.tex │ ├── OAAO232_manpage.tex │ ├── OAAO233_circuit.tex │ ├── OAAO233_manpage.tex │ ├── OAAO234_circuit.tex │ ├── OAAO234_manpage.tex │ ├── OAAO312_circuit.tex │ ├── OAAO312_manpage.tex │ ├── OAAOI2121_circuit.tex │ ├── OAAOI2121_manpage.tex │ ├── OAAOI212_circuit.tex │ ├── OAAOI212_manpage.tex │ ├── OAAOI2221_circuit.tex │ ├── OAAOI2221_manpage.tex │ ├── OAAOI222_circuit.tex │ ├── OAAOI222_manpage.tex │ ├── OAAOI2231_circuit.tex │ ├── OAAOI2231_manpage.tex │ ├── OAAOI223_circuit.tex │ ├── OAAOI223_manpage.tex │ ├── OAAOI232_circuit.tex │ ├── OAAOI232_manpage.tex │ ├── OAAOI233_circuit.tex │ ├── OAAOI233_manpage.tex │ ├── OAAOI234_circuit.tex │ ├── OAAOI234_manpage.tex │ ├── OAAOI312_circuit.tex │ ├── OAAOI312_manpage.tex │ ├── OAI21_circuit.tex │ ├── OAI21_manpage.tex │ ├── OAI21_schematic.tex │ ├── OAI21_truthtable.tex │ ├── OAI22_circuit.tex │ ├── OAI22_manpage.tex │ ├── OAI22_schematic.tex │ ├── OAI22_truthtable.tex │ ├── OAI23_circuit.tex │ ├── OAI23_manpage.tex │ ├── OAI31_circuit.tex │ ├── OAI31_manpage.tex │ ├── OAI31_schematic.tex │ ├── OAI31_truthtable.tex │ ├── OAI32_circuit.tex │ ├── OAI32_manpage.tex │ ├── OAI33_circuit.tex │ ├── OAI33_manpage.tex │ ├── OAI41_circuit.tex │ ├── OAI41_manpage.tex │ ├── OAI43_circuit.tex │ ├── OAI43_manpage.tex │ ├── OAO211_circuit.tex │ ├── OAO211_manpage.tex │ ├── OAO212_circuit.tex │ ├── OAO212_manpage.tex │ ├── OAO221_circuit.tex │ ├── OAO221_manpage.tex │ ├── OAO222_circuit.tex │ ├── OAO222_manpage.tex │ ├── OAO232_circuit.tex │ ├── OAO232_manpage.tex │ ├── OAO311_circuit.tex │ ├── OAO311_manpage.tex │ ├── OAOA2111_circuit.tex │ ├── OAOA2111_manpage.tex │ ├── OAOA2211_circuit.tex │ ├── OAOA2211_manpage.tex │ ├── OAOA3211_circuit.tex │ ├── OAOA3211_manpage.tex │ ├── OAOAI2111_circuit.tex │ ├── OAOAI2111_manpage.tex │ ├── OAOAI2211_circuit.tex │ ├── OAOAI2211_manpage.tex │ ├── OAOAI3211_circuit.tex │ ├── OAOAI3211_manpage.tex │ ├── OAOI211_circuit.tex │ ├── OAOI211_manpage.tex │ ├── OAOI212_circuit.tex │ ├── OAOI212_manpage.tex │ ├── OAOI221_circuit.tex │ ├── OAOI221_manpage.tex │ ├── OAOI222_circuit.tex │ ├── OAOI222_manpage.tex │ ├── OAOI232_circuit.tex │ ├── OAOI232_manpage.tex │ ├── OAOI311_circuit.tex │ ├── OAOI311_manpage.tex │ ├── OOA221_circuit.tex │ ├── OOA221_manpage.tex │ ├── OOA22_circuit.tex │ ├── OOA22_manpage.tex │ ├── OOA321_circuit.tex │ ├── OOA321_manpage.tex │ ├── OOA32_circuit.tex │ ├── OOA32_manpage.tex │ ├── OOA331_circuit.tex │ ├── OOA331_manpage.tex │ ├── OOA33_circuit.tex │ ├── OOA33_manpage.tex │ ├── OOA42_circuit.tex │ ├── OOA42_manpage.tex │ ├── OOA43_circuit.tex │ ├── OOA43_manpage.tex │ ├── OOA44_circuit.tex │ ├── OOA44_manpage.tex │ ├── OOAAO222_circuit.tex │ ├── OOAAO222_manpage.tex │ ├── OOAAOI222_circuit.tex │ ├── OOAAOI222_manpage.tex │ ├── OOAI221_circuit.tex │ ├── OOAI221_manpage.tex │ ├── OOAI221_schematic.tex │ ├── OOAI221_truthtable.tex │ ├── OOAI22_circuit.tex │ ├── OOAI22_manpage.tex │ ├── OOAI22_schematic.tex │ ├── OOAI22_truthtable.tex │ ├── OOAI321_circuit.tex │ ├── OOAI321_manpage.tex │ ├── OOAI321_schematic.tex │ ├── OOAI321_truthtable.tex │ ├── OOAI32_circuit.tex │ ├── OOAI32_manpage.tex │ ├── OOAI32_schematic.tex │ ├── OOAI32_truthtable.tex │ ├── OOAI331_circuit.tex │ ├── OOAI331_manpage.tex │ ├── OOAI331_schematic.tex │ ├── OOAI331_truthtable.tex │ ├── OOAI33_circuit.tex │ ├── OOAI33_manpage.tex │ ├── OOAI33_schematic.tex │ ├── OOAI33_truthtable.tex │ ├── OOAI42_circuit.tex │ ├── OOAI42_manpage.tex │ ├── OOAI43_circuit.tex │ ├── OOAI43_manpage.tex │ ├── OOAI44_circuit.tex │ ├── OOAI44_manpage.tex │ ├── OOAO221_circuit.tex │ ├── OOAO221_manpage.tex │ ├── OOAO321_circuit.tex │ ├── OOAO321_manpage.tex │ ├── OOAO331_circuit.tex │ ├── OOAO331_manpage.tex │ ├── OOAOI221_circuit.tex │ ├── OOAOI221_manpage.tex │ ├── OOAOI321_circuit.tex │ ├── OOAOI321_manpage.tex │ ├── OOAOI331_circuit.tex │ ├── OOAOI331_manpage.tex │ ├── OOOA222_circuit.tex │ ├── OOOA222_manpage.tex │ ├── OOOA322_circuit.tex │ ├── OOOA322_manpage.tex │ ├── OOOA332_circuit.tex │ ├── OOOA332_manpage.tex │ ├── OOOA333_circuit.tex │ ├── OOOA333_manpage.tex │ ├── OOOAI222_circuit.tex │ ├── OOOAI222_manpage.tex │ ├── OOOAI222_schematic.tex │ ├── OOOAI222_truthtable.tex │ ├── OOOAI322_circuit.tex │ ├── OOOAI322_manpage.tex │ ├── OOOAI322_schematic.tex │ ├── OOOAI322_truthtable.tex │ ├── OOOAI332_circuit.tex │ ├── OOOAI332_manpage.tex │ ├── OOOAI332_schematic.tex │ ├── OOOAI332_truthtable.tex │ ├── OOOAI333_circuit.tex │ ├── OOOAI333_manpage.tex │ ├── OOOAI333_schematic.tex │ ├── OOOAI333_truthtable.tex │ ├── OR2_circuit.tex │ ├── OR2_manpage.tex │ ├── OR3_circuit.tex │ ├── OR3_manpage.tex │ ├── OR4_circuit.tex │ ├── OR4_manpage.tex │ ├── OR4_schematic.tex │ ├── OR4_truthtable.tex │ ├── StdCellLib.tex │ ├── TIE0_circuit.tex │ ├── TIE0_manpage.tex │ ├── TIE0_truthtable.tex │ ├── TIE1_circuit.tex │ ├── TIE1_manpage.tex │ ├── TIE1_truthtable.tex │ ├── XOR2_circuit.tex │ ├── XOR2_files.tex │ ├── XOR2_manpage.tex │ ├── XOR2_schematic.tex │ ├── XOR2_truthtable.tex │ ├── cmos_in_a_nutshell.tex │ ├── global_color_scheme.tex │ ├── readings.bib │ └── revision.tex └── StdCellLib.pdf ├── GNUmakefile ├── LICENSE ├── README.md ├── Simulation └── verilog │ ├── EQ2.do │ └── XOR2.do ├── Sources ├── geda │ ├── BUF2.sch │ ├── BUF2.sym │ ├── CGN2.sch │ ├── CGN2.sym │ ├── CGP2.sch │ ├── CGP2.sym │ ├── DFFN.sch │ ├── DFFN.sym │ ├── DFFP.sch │ ├── DFFP.sym │ ├── FO4.sch │ ├── FO4.sym │ ├── LATEN.sch │ ├── LATEN.sym │ ├── LATEP.sch │ ├── LATEP.sym │ ├── LATERN.sch │ ├── LATERN.sym │ ├── LATERP.sch │ ├── LATERP.sym │ ├── LATESN.sch │ ├── LATESN.sym │ ├── LATESP.sch │ ├── LATESP.sym │ ├── LATN.sch │ ├── LATN.sym │ ├── LATP.sch │ ├── LATP.sym │ ├── LATRN.sch │ ├── LATRN.sym │ ├── LATRP.sch │ ├── LATRP.sym │ ├── LATSN.sch │ ├── LATSN.sym │ ├── LATSP.sch │ └── LATSP.sym └── verilog │ ├── EQ2.v │ ├── EQ2_switch.v │ ├── MUXI2.v │ ├── MUXI2_switch.v │ ├── XOR2.v │ ├── XOR2_switch.v │ └── timescale.v ├── Synthesis └── liberty │ └── ls1u_Ptyp_V5_T25.lib ├── TBench ├── geda │ ├── BUF2_tb.sch │ ├── DFFN_tb.sch │ ├── DFFP_tb.sch │ ├── LATN_tb.sch │ └── LATP_tb.sch ├── spice │ ├── BUF2_tb.cmd │ ├── DFFN_tb.cmd │ ├── DFFP_tb.cmd │ ├── LATN_tb.cmd │ ├── LATP_tb.cmd │ └── ls1u_models.lib └── verilog │ ├── XOR2_stim.v │ ├── tb_EQ2.v │ └── tb_MUXI2.v ├── Tech ├── Tech.CDTA ├── .gitignore ├── librecell_tech.py ├── libresilicon.m ├── libresilicon.tech ├── nmos.sp ├── pmos.sp └── template.lef ├── Tech.GF180MCU ├── .gitignore ├── 08_Topological_Truth_Table15.csv ├── Makefile ├── caravel-env.sh ├── design.ngspice ├── librecell_tech.py ├── libresilicon.m ├── libresilicon.tech ├── nmos.sp ├── pmos.sp ├── sm141064.ngspice ├── template.lef └── tracks.txt ├── Tech.LS1UM ├── .gitignore ├── SpiceParameterFiles.zip ├── bad │ ├── libresilicon.m1 │ ├── libresilicon.m10 │ ├── libresilicon.m11 │ ├── libresilicon.m2 │ ├── libresilicon.m3 │ ├── libresilicon.m5 │ ├── libresilicon.m6 │ ├── libresilicon.m7 │ └── libresilicon.m8 ├── drc.lydrc ├── dummy_tech.py ├── good │ ├── libresilicon.m │ ├── libresilicon.m13 │ ├── libresilicon.m4 │ └── libresilicon.m9 ├── librecell_tech.py ├── libresilicon.m ├── libresilicon.m13 ├── libresilicon.m4 ├── libresilicon.m9 ├── libresilicon.tech ├── nmos.sp ├── pmos.sp └── template.lef ├── Tech.SKY130 ├── .gitignore ├── caravel-env.sh ├── librecell_tech.py ├── libresilicon.m ├── libresilicon.tech ├── nmos.sp ├── pmos.sp └── template.lef ├── Technology └── spice │ ├── ls1unmos.mod │ └── ls1upmos.mod ├── Tools ├── caravel │ ├── cells.pl │ ├── configgen.pl │ ├── deploy2caravel.sh │ ├── drcexpander.pl │ ├── feedback2mag.pl │ ├── fixup_lef.pl │ ├── fixup_mag.pl │ ├── fixup_sp.pl │ ├── generator.pl │ ├── gitpush.sh │ ├── iogenerator.pl │ ├── placement.pl │ ├── removeDRCcells.pl │ ├── removenl.pl │ ├── scale10.py │ ├── stdcells_tb.v │ ├── testgen.pl │ └── viewer.pl ├── cell.5 ├── perl │ ├── annotate.pl │ ├── bisect.pl │ ├── buildreport.pl │ ├── cell2circle.pl │ ├── cell2sch.pl │ ├── cell2spice.pl │ ├── charter2caravel.pl │ ├── demoboard.pl │ ├── disp2svg.pl │ ├── dorest.pl │ ├── draw.pl │ ├── drccheck.pl │ ├── drcexpander.pl │ ├── drcfix.pl │ ├── drcfix.tcl │ ├── drcfixall.pl │ ├── dummychar.pl │ ├── essential.pl │ ├── euler.pl │ ├── flatten.pl │ ├── funclist.pl │ ├── gencharlibyml.pl │ ├── lefgen.pl │ ├── lefsize.pl │ ├── libgen.pl │ ├── libgenall.pl │ ├── librecells.pl │ ├── ltspice2lclayout.pl │ ├── mag2siliwiz.pl │ ├── mag2svg.pl │ ├── magscale.pl │ ├── muxgen.pl │ ├── painter.pl │ ├── paintgridusage.pl │ ├── parasitics.pl │ ├── popcorn.pl │ ├── report.pl │ ├── searchTechRules.pl │ ├── spice2cell.pl │ ├── testgen.pl │ └── truthtable.pl ├── popcorn.1 ├── popcorn │ ├── GNUmakefile │ ├── README.md │ ├── popcorn │ ├── popcorn-cell.scm │ ├── popcorn-lib.scm │ ├── popcorn-sch.scm │ ├── popcorn-verilog.scm │ └── popcorn.scm ├── python │ ├── concat4gds.py │ └── gen_CharLib.py ├── reporter.sh ├── table.5 └── tcl │ ├── _manpage │ ├── _schematic │ ├── _switch │ ├── kino.pl │ └── popcorn ├── gafrc ├── gnetlistrc ├── include.mk ├── simulation.mk └── tools.sh /.gitignore: -------------------------------------------------------------------------------- 1 | StdCellLib*.tgz 2 | -------------------------------------------------------------------------------- /Catalog/.gitignore: -------------------------------------------------------------------------------- 1 | *.mag 2 | *.cell 3 | *.svg 4 | *.sp 5 | *.pxi 6 | !INV.cell 7 | __pycache__ 8 | libresilicon.lib 9 | libresilicon.lef 10 | -------------------------------------------------------------------------------- /Catalog/AND4.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A B C D 3 | .outputs Z 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y vdd 6 | pmos B Y vdd 7 | pmos C Y vdd 8 | pmos D Y vdd 9 | pmos Y Z vdd 10 | nmos A Y 1 11 | nmos B 1 2 12 | nmos C 2 3 13 | nmos D 3 gnd 14 | nmos Y Z gnd 15 | -------------------------------------------------------------------------------- /Catalog/AOI21.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A A1 3 | .outputs Y 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y vdd 6 | pmos A1 Y vdd 7 | nmos A Y 1 8 | nmos A1 1 gnd 9 | -------------------------------------------------------------------------------- /Catalog/AOI31.cell: -------------------------------------------------------------------------------- 1 | .DESCRIPTION "a 3-1-input AND-OR-Invert gate" 2 | .SEE_ALSO "AOI31 - a 3-1-input AND-OR-Invert gate" 3 | .inputs A B B1 B2 4 | .outputs Y 5 | .ORDER "MOSFET Gate Drain Source" 6 | pmos A Y 1 7 | pmos B 1 vdd 8 | pmos B1 1 vdd 9 | pmos B2 1 vdd 10 | nmos A Y gnd 11 | nmos B Y 2 12 | nmos B1 2 3 13 | nmos B2 3 gnd 14 | -------------------------------------------------------------------------------- /Catalog/ASYNC1.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by spice2cell script from ASYNC1.spice 2 | .inputs A B 3 | .outputs C CN 4 | .ORDER "MOSFET Gate Drain Source" 5 | nmos B CN net3 6 | pmos A net4 VDD 7 | pmos B CN net4 8 | pmos A net1 VDD 9 | pmos B net1 VDD 10 | pmos C CN net1 11 | pmos CN C VDD 12 | nmos C CN net2 13 | nmos A net3 GND 14 | nmos B net2 GND 15 | nmos A net2 GND 16 | nmos CN C GND 17 | -------------------------------------------------------------------------------- /Catalog/ASYNC2.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by spice2cell script from ASYNC2.spice 2 | .inputs A B 3 | .outputs C CN 4 | .ORDER "MOSFET Gate Drain Source" 5 | nmos C CN GND 6 | pmos A net1 VDD 7 | pmos B CN net1 8 | pmos CN C VDD 9 | pmos C CN VDD 10 | nmos B CN net2 11 | nmos A net2 GND 12 | nmos CN C GND 13 | -------------------------------------------------------------------------------- /Catalog/ASYNC3.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by spice2cell script from ASYNC3.spice 2 | .inputs A B 3 | .outputs C CN 4 | .ORDER "MOSFET Gate Drain Source" 5 | nmos B CN net2 6 | nmos A net2 GND 7 | nmos A CN net1 8 | nmos CN C GND 9 | nmos B net1 GND 10 | nmos C net2 net1 11 | pmos B CN net3 12 | pmos A net3 VDD 13 | pmos B net4 VDD 14 | pmos A CN net4 15 | pmos CN C VDD 16 | pmos C net4 net3 17 | -------------------------------------------------------------------------------- /Catalog/INV.cell: -------------------------------------------------------------------------------- 1 | Not (or Inverter) gate 2 | .cell INV 3 | .inputs A 4 | .outputs Y 5 | # ^ Vdd 6 | # | 7 | # | +-' 8 | # A --o| | g 9 | # | +-. 10 | # | 11 | # | 12 | # *---- Y 13 | # | 14 | # | 15 | # | +-' 16 | # A ---| | 1 17 | # | +-. 18 | # | 19 | # _|_ Gnd 20 | pmos A Y vdd vdd g 1 1 +1 21 | nmos A Y gnd gnd 1 1 1 -1 22 | .end 23 | -------------------------------------------------------------------------------- /Catalog/NAND2.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A B 3 | .outputs Y 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y vdd 6 | pmos B Y vdd 7 | nmos A Y 1 8 | nmos B 1 gnd 9 | -------------------------------------------------------------------------------- /Catalog/NAND3.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A B C 3 | .outputs Y 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y vdd 6 | pmos B Y vdd 7 | pmos C Y vdd 8 | nmos A Y 1 9 | nmos B 1 2 10 | nmos C 2 gnd 11 | -------------------------------------------------------------------------------- /Catalog/NOR2.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A B 3 | .outputs Y 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y 1 6 | pmos B 1 vdd 7 | nmos A Y gnd 8 | nmos B Y gnd 9 | -------------------------------------------------------------------------------- /Catalog/NOR3.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A B C 3 | .outputs Y 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y 1 6 | pmos B 1 2 7 | pmos C 2 vdd 8 | nmos A Y gnd 9 | nmos B Y gnd 10 | nmos C Y gnd 11 | -------------------------------------------------------------------------------- /Catalog/OAI21.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A A1 3 | .outputs Y 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y 1 6 | pmos A1 1 vdd 7 | nmos A Y gnd 8 | nmos A1 Y gnd 9 | -------------------------------------------------------------------------------- /Catalog/OAI31.cell: -------------------------------------------------------------------------------- 1 | .DESCRIPTION "a 3-1-input OR-AND-Invert gate" 2 | .SEE_ALSO "OAI31 - a 3-1-input OR-AND-Invert gate" 3 | .inputs A B B1 B2 4 | .outputs Y 5 | .ORDER "MOSFET Gate Drain Source" 6 | pmos A Y vdd 7 | pmos B Y 1 8 | pmos B1 1 3 9 | pmos B2 3 vdd 10 | nmos A Y 2 11 | nmos B 2 gnd 12 | nmos B1 2 gnd 13 | nmos B2 2 gnd 14 | -------------------------------------------------------------------------------- /Catalog/OR4.cell: -------------------------------------------------------------------------------- 1 | .AUTOGENERATED by Popcorn Tcl Script 2 | .inputs A B C D 3 | .outputs Z 4 | .ORDER "MOSFET Gate Drain Source" 5 | pmos A Y 1 6 | pmos B 1 2 7 | pmos C 2 3 8 | pmos D 3 vdd 9 | pmos Y Z vdd 10 | nmos A Y gnd 11 | nmos B Y gnd 12 | nmos C Y gnd 13 | nmos D Y gnd 14 | nmos Y Z gnd 15 | -------------------------------------------------------------------------------- /Catalog/doc/GNUmakefile: -------------------------------------------------------------------------------- 1 | all: 2 | ./docu.sh 3 | 4 | clean: 5 | rm -f *_schematic.tex cells.tex 6 | rm -f *.aux *.idx *.log *.toc *.pdf *.png *.svg *_svg.tex 7 | killall -q pdflatex || true 8 | 9 | -------------------------------------------------------------------------------- /Catalog/doc/docu.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | #cd .. 4 | for a in *.cell 5 | do 6 | ../Tools/tcl/_schematic -i . -o doc $a 7 | done 8 | cd doc 9 | echo "" >cells.tex 10 | for a in *_schematic.tex 11 | do 12 | echo \\clearpage >>cells.tex 13 | echo \\section{Cell ${a//_schematic\.tex/}} >>cells.tex 14 | echo \\input{$a} >>cells.tex 15 | #echo "Text below the schematic" >>cells.tex 16 | 17 | echo \\documentclass{article} >${a//_schematic/_svg} 18 | echo \\usepackage[digital,srcmeas,semicon]{circdia} >>${a//_schematic/_svg} 19 | echo \\begin{document} >>${a//_schematic/_svg} 20 | echo \\thispagestyle{empty} >>${a//_schematic/_svg} 21 | echo \\input {$a} >>${a//_schematic/_svg} 22 | echo \\end{document} >>${a//_schematic/_svg} 23 | pdflatex ${a//_schematic/_svg} 24 | pdfcrop ${a//_schematic.tex/_svg.pdf} 25 | pdf2svg ${a//_schematic.tex/_svg.pdf} ${a//_schematic.tex/_svg.svg} 26 | convert -trim ${a//_schematic.tex/_svg.svg} ${a//_schematic.tex/_svg.png} 27 | done 28 | pdflatex StdCellLib.tex 29 | pdflatex StdCellLib.tex 30 | cp StdCellLib.pdf ../../Documents/StdCellLib.pdf 31 | echo "You can view the generated documentation by calling:" 32 | echo "evince doc/StdCellLib.pdf" 33 | -------------------------------------------------------------------------------- /Catalog/popcorn/INV.cell: -------------------------------------------------------------------------------- 1 | Not (or Inverter) gate 2 | .cell INV 3 | .inputs A 4 | .outputs Y 5 | # ^ Vdd 6 | # | 7 | # | +-' 8 | # A --o| | g 9 | # | +-. 10 | # | 11 | # | 12 | # *---- Y 13 | # | 14 | # | 15 | # | +-' 16 | # A ---| | 1 17 | # | +-. 18 | # | 19 | # _|_ Gnd 20 | pmos A Y vdd vdd g 1 1 +1 21 | nmos A Y gnd gnd 1 1 1 -1 22 | .end 23 | -------------------------------------------------------------------------------- /Docker/bash.sh: -------------------------------------------------------------------------------- 1 | docker run -it thesourcerer8/stdcelllib /bin/bash 2 | -------------------------------------------------------------------------------- /Docker/build.sh: -------------------------------------------------------------------------------- 1 | docker build --tag thesourcerer8/stdcelllib . 2 | -------------------------------------------------------------------------------- /Documents/LaTeX/AND2_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AND2_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for AND2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{17}{6} 40 | \usgate 41 | \gate[\inputs{2}]{nand}{5}{3}{R}{}{} % NAND 42 | \gate{not}{12}{3}{R}{}{} % NOT 43 | \pin{1}{1}{L}{A} % pin A 44 | \pin{1}{5}{L}{A1} % pin A1 45 | \pin{16}{3}{R}{Z} % pin Z 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/AND2_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AND2_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AND2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AND2 - a 2-input AND gate} \label{logical:AND2} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AND2 (Z A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AND2_circuit.tex} 44 | %\input{AND2_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AND2_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AND3_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AND3_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AND3 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AND3 - a 3-input AND gate} \label{logical:AND3} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AND3 (Z A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AND3_circuit.tex} 44 | %\input{AND3_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AND3_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO21_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO21_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AO21 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AO21 - a 2-1-input AND-OR gate} \label{logical:AO21} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AO21 (Z B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AO21_circuit.tex} 44 | %\input{AO21_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AO21_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO22_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO22_manpage.tex 13 | %% 14 | %% Purpose: Manual Page File for AO22 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \label{AO22} 36 | \paragraph{Cell} 37 | \begin{quote} 38 | \textbf{AO22} - a 2-2-input AND-OR gate 39 | \end{quote} 40 | 41 | \paragraph{Synopsys} 42 | \begin{quote} 43 | AO22(Z, B1, B, A1, A) 44 | \end{quote} 45 | 46 | \paragraph{Description} 47 | \input{AO22_circuit.tex} 48 | %\input{AO22_schematic.tex} 49 | 50 | \paragraph{Truth Table} 51 | %\input{AO22_truthtable.tex} 52 | 53 | \paragraph{Usage} 54 | 55 | \paragraph{Fan-in / Fan-out} 56 | 57 | \paragraph{Layout} 58 | 59 | \paragraph{Files} 60 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO23_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO23_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AO23 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AO23 - a 2-3-input AND-OR gate} \label{logical:AO23} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AO23 (Z B1 B A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AO23_circuit.tex} 44 | %\input{AO23_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AO23_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO31_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO31_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AO31 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AO31 - a 3-1-input AND-OR gate} \label{logical:AO31} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AO31 (Z B2 B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AO31_circuit.tex} 44 | %\input{AO31_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AO31_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO32_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO32_manpage.tex 13 | %% 14 | %% Purpose: Manual Page File for AO32 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \label{AO32} 36 | \paragraph{Cell} 37 | \begin{quote} 38 | \textbf{AO32} - a 3-2-input AND-OR gate 39 | \end{quote} 40 | 41 | \paragraph{Synopsys} 42 | \begin{quote} 43 | AO32(Z, B2, B1, B, A1, A) 44 | \end{quote} 45 | 46 | \paragraph{Description} 47 | \input{AO32_circuit.tex} 48 | %\input{AO32_schematic.tex} 49 | 50 | \paragraph{Truth Table} 51 | %\input{AO32_truthtable.tex} 52 | 53 | \paragraph{Usage} 54 | 55 | \paragraph{Fan-in / Fan-out} 56 | 57 | \paragraph{Layout} 58 | 59 | \paragraph{Files} 60 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO33_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO33_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AO33 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AO33 - a 3-3-input AND-OR-Invert gate} \label{logical:AO33} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AO33 (Z B2 B1 B A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AO33_circuit.tex} 44 | %\input{AO33_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AO33_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO41_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO41_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AO41 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AO41 - a 4-1-input AND-OR gate} \label{logical:AO41} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AO41 (Z B3 B2 B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AO41_circuit.tex} 44 | %\input{AO41_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AO41_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AO43_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AO43_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AO43 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AO43 - a 4-3-input AND-OR-Invert gate} \label{logical:AO43} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AO43 (Z, B3, B2, B1, B, A2, A1, A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AO43_circuit.tex} 44 | %\input{AO43_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AO43_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AOI23_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AOI23_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AOI23 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AOI23 - a 2-3-input AND-OR-Invert gate} \label{logical:AOI23} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AOI23 (Z B1 B A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AOI23_circuit.tex} 44 | %\input{AOI23_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AOI23_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AOI33_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AOI33_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AOI33 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AOI33 - a 3-3-input AND-OR-Invert gate} \label{logical:AOI33} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AOI33 (Y B2 B1 B A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AOI33_circuit.tex} 44 | %\input{AOI33_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AOI33_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AOI41_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AOI41_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AOI41 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AOI41 - a 4-1-input AND-OR-Invert gate} \label{logical:AOI41} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AOI41 (Z B3 B2 B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AOI41_circuit.tex} 44 | %\input{AOI41_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AOI41_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/AOI43_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/AOI43_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for AOI43 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{AOI43 - a 4-3-input AND-OR-Invert gate} \label{logical:AOI43} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | AOI43 (Y, B3, B2, B1, B, A2, A1, A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{AOI43_circuit.tex} 44 | %\input{AOI43_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{AOI43_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/BUF2_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/BUF2_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for BUF2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{14}{6} 40 | \pin{1}{3}{L}{A} % pin A 41 | \gate{not}{5}{3}{R}{}{} % 1st buffer 42 | \gate{not}{11}{3}{Rc}{}{2x} % 2nd buffer 43 | \pin{15}{3}{R}{Z} % pin Z 44 | \end{circuitdiagram} 45 | \end{center} 46 | \end{figure} 47 | \end{center} 48 | -------------------------------------------------------------------------------- /Documents/LaTeX/BUF2_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_BUF.tex 13 | %% 14 | %% Purpose: Truth Table File for BUF 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | {\(Z = A \)} 37 | \begin{table}[h] %\caption{\(Z = A \)} 38 | \begin{center} 39 | \begin{tabular}{|c||c|} \hline 40 | A & Z \\ \hline\hline 41 | 0 & 0 \\ \hline 42 | 1 & 1 \\ \hline 43 | \end{tabular} 44 | \end{center} 45 | \end{table} 46 | \end{center} 47 | -------------------------------------------------------------------------------- /Documents/LaTeX/DFFN_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/DFFN_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for DFFN 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{8} 40 | \usgate 41 | \flipflop[\clockin{nd}]{d}{6}{4}{R}{}{} 42 | \pin{1}{4}{L}{XN} % pin XN 43 | \pin{1}{6}{L}{D} % pin D 44 | \pin{11}{6}{R}{Q} % pin Q 45 | \end{circuitdiagram} 46 | \end{center} 47 | \end{figure} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/DFFN_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/DFFN_manpage.tex 13 | %% 14 | %% Purpose: Manual Page File for DFFN 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \label{DFFN} 36 | \paragraph{Cell} 37 | \begin{quote} 38 | \textbf{DFFN} - a Negative edge-triggered D-FlipFlop 39 | \end{quote} 40 | 41 | \paragraph{Synopsys} 42 | \begin{quote} 43 | DFFN(Q, D, XN) 44 | \end{quote} 45 | 46 | \paragraph{Description} 47 | \input{DFFN_circuit.tex} 48 | %\input{DFFN_schematic.tex} 49 | 50 | \paragraph{Truth Table} 51 | %\input{DFFN_truthtable.tex} 52 | 53 | \paragraph{Usage} 54 | 55 | \paragraph{Fan-in / Fan-out} 56 | 57 | \paragraph{Layout} 58 | 59 | \paragraph{Files} 60 | -------------------------------------------------------------------------------- /Documents/LaTeX/DFFP_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/DFFP_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for DFFP 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{8} 40 | \usgate 41 | \flipflop[\clockin{pd}]{d}{6}{4}{R}{}{} 42 | \pin{1}{4}{L}{X} % pin X 43 | \pin{1}{6}{L}{D} % pin D 44 | \pin{11}{6}{R}{Q} % pin Q 45 | \end{circuitdiagram} 46 | \end{center} 47 | \end{figure} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/DFFP_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/DFFP_manpage.tex 13 | %% 14 | %% Purpose: Manual Page File for DFFP 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \label{DFFP} 36 | \paragraph{Cell} 37 | \begin{quote} 38 | \textbf{DFFP} - a Positive edge-triggered D-FlipFlop 39 | \end{quote} 40 | 41 | \paragraph{Synopsys} 42 | \begin{quote} 43 | DFFP(Q, D, X) 44 | \end{quote} 45 | 46 | \paragraph{Description} 47 | \input{DFFP_circuit.tex} 48 | %\input{DFFP_schematic.tex} 49 | 50 | \paragraph{Truth Table} 51 | %\input{DFFP_truthtable.tex} 52 | 53 | \paragraph{Usage} 54 | 55 | \paragraph{Fan-in / Fan-out} 56 | 57 | \paragraph{Layout} 58 | 59 | \paragraph{Files} 60 | -------------------------------------------------------------------------------- /Documents/LaTeX/EQ2_files.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/files_EQ2.tex 13 | %% 14 | %% Purpose: File list for EQ2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Simulation 37 | \begin{itemize} 38 | \item[$\square$] \texttt{./Sources/verilog/EQ2.v} - Verilog-95 Cell Model 39 | \item[$\square$] \texttt{./Sources/verilog/EQ2\_switch.v} - Verilog-2001 Switch-Level Model 40 | \item[$\square$] \texttt{./TBench/verilog/tb\_EQ2.v} - Verilog-2001 Self-checking Testbench 41 | \end{itemize} 42 | Physical Layout 43 | \begin{itemize} 44 | \item[\checkmark] \texttt{?} 45 | \end{itemize} 46 | \end{center} 47 | -------------------------------------------------------------------------------- /Documents/LaTeX/EQ2_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_EQ2.tex 13 | %% 14 | %% Purpose: Truth Table File for EQ2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | 36 | \begin{center} 37 | {\(Z = \lnot (B \oplus A) \)} 38 | \begin{table}[h] %\caption{\(Z = \lnot (B \oplus A) \)} 39 | \begin{center} 40 | \begin{tabular}{|c|c||c|} \hline 41 | B & A & Z \\ \hline\hline 42 | 0 & 0 & 1 \\ \hline 43 | 0 & 1 & 0 \\ \hline 44 | 1 & 0 & 0 \\ \hline 45 | 1 & 1 & 1 \\ \hline 46 | \end{tabular} 47 | \end{center} 48 | \end{table} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/INV_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/circuit_INV.tex 13 | %% 14 | %% Purpose: Circuit File for INV 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] %\caption{Circuit} 38 | \begin{center} 39 | \begin{circuitdiagram}{11}{6} 40 | \pin{1}{3}{L}{A} % pin A 41 | \gate{not}{5}{3}{R}{}{} % NOT gate -> right 42 | \pin{9}{3}{R}{Y} % pin Y 43 | \end{circuitdiagram} 44 | \end{center} 45 | \end{figure} 46 | \end{center} 47 | -------------------------------------------------------------------------------- /Documents/LaTeX/INV_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_INV.tex 13 | %% 14 | %% Purpose: Truth Table File for INV 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | 36 | \begin{center} 37 | {\(Z = \lnot A \)} 38 | \begin{table}[h] %\caption{\(Z = \lnot A \)} 39 | \begin{center} 40 | \begin{tabular}{|c||c|} \hline 41 | A & Z \\ \hline\hline 42 | 0 & 1 \\ \hline 43 | 1 & 0 \\ \hline 44 | \end{tabular} 45 | \end{center} 46 | \end{table} 47 | \end{center} 48 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATN_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATN_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for LATN 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{8} 40 | \usgate 41 | \flipflop[\clockin{n}]{d}{6}{4}{R}{}{} 42 | \pin{1}{4}{L}{XN} % pin XN 43 | \pin{1}{6}{L}{D} % pin D 44 | \pin{11}{6}{R}{Q} % pin Q 45 | \end{circuitdiagram} 46 | \end{center} 47 | \end{figure} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATN_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATN_manpage.tex 13 | %% 14 | %% Purpose: Manual Page File for LATN 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \label{LATN} 36 | \paragraph{Cell} 37 | \begin{quote} 38 | \textbf{LATN} - a Low-active D-Latch 39 | \end{quote} 40 | 41 | \paragraph{Synopsys} 42 | \begin{quote} 43 | LATN(Q, D, XN) 44 | \end{quote} 45 | 46 | \paragraph{Description} 47 | \input{LATN_circuit.tex} 48 | %\input{LATN_schematic.tex} 49 | 50 | \paragraph{Truth Table} 51 | %\input{LATP_truthtable.tex} 52 | 53 | \paragraph{Usage} 54 | 55 | \paragraph{Fan-in / Fan-out} 56 | 57 | \paragraph{Layout} 58 | 59 | \paragraph{Files} 60 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATP_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATP_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for LATP 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{8} 40 | \usgate 41 | \flipflop[\clockin{p}]{d}{6}{4}{R}{}{} 42 | \pin{1}{4}{L}{X} % pin X 43 | \pin{1}{6}{L}{D} % pin D 44 | \pin{11}{6}{R}{Q} % pin Q 45 | \end{circuitdiagram} 46 | \end{center} 47 | \end{figure} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATP_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATP_manpage.tex 13 | %% 14 | %% Purpose: Manual Page File for LATP 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \label{LATP} 36 | \paragraph{Cell} 37 | \begin{quote} 38 | \textbf{LATP} - a High-active D-Latch 39 | \end{quote} 40 | 41 | \paragraph{Synopsys} 42 | \begin{quote} 43 | LATP(Q, D, X) 44 | \end{quote} 45 | 46 | \paragraph{Description} 47 | \input{LATP_circuit.tex} 48 | %\input{LATP_schematic.tex} 49 | 50 | \paragraph{Truth Table} 51 | %\input{LATP_truthtable.tex} 52 | 53 | \paragraph{Usage} 54 | 55 | \paragraph{Fan-in / Fan-out} 56 | 57 | \paragraph{Layout} 58 | 59 | \paragraph{Files} 60 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATRN_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATRN_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for LATRN 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{10} 40 | \usgate 41 | \flipflop[\clockin{n}\resetin{p}]{d}{6}{6}{R}{}{} 42 | \pin{1}{6}{L}{XN} % pin XN 43 | \pin{1}{8}{L}{D} % pin D 44 | \pin{6}{1}{D}{R} % pin R 45 | \pin{11}{8}{R}{Q} % pin Q 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATRP_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATRP_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for LATRP 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{10} 40 | \usgate 41 | \flipflop[\clockin{p}\resetin{p}]{d}{6}{6}{R}{}{} 42 | \pin{1}{6}{L}{X} % pin X 43 | \pin{1}{8}{L}{D} % pin D 44 | \pin{6}{1}{D}{R} % pin R 45 | \pin{11}{8}{R}{Q} % pin Q 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATSN_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATSN_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for LATSN 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{10} 40 | \usgate 41 | \flipflop[\clockin{n}\setin{n}]{d}{6}{4}{R}{}{} 42 | \pin{1}{4}{L}{XN} % pin XN 43 | \pin{1}{6}{L}{D} % pin D 44 | \pin{6}{9}{U}{SN} % pin SN 45 | \pin{11}{6}{R}{Q} % pin Q 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/LATSP_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/LATSP_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for LATSP 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{12}{10} 40 | \usgate 41 | \flipflop[\clockin{p}\setin{n}]{d}{6}{4}{R}{}{} 42 | \pin{1}{4}{L}{X} % pin X 43 | \pin{1}{6}{L}{D} % pin D 44 | \pin{6}{9}{U}{SN} % pin SN 45 | \pin{11}{6}{R}{Q} % pin Q 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/MUXI2_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_MUXI2.tex 13 | %% 14 | %% Purpose: Truth Table File for MUXI2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | 36 | \begin{center} 37 | {\(Z = \lnot (A1 \land S) \lor \lnot(A0 \land \lnot S)) \)} 38 | \begin{table}[h] 39 | \begin{center} 40 | \begin{tabular}{|c|c|c||c|} \hline 41 | S & A1 & A0 & Z \\ \hline\hline 42 | 0 & X & 0 & 1 \\ \hline 43 | 0 & X & 1 & 0 \\ \hline 44 | 1 & 0 & X & 1 \\ \hline 45 | 1 & 1 & X & 0 \\ \hline 46 | \end{tabular} 47 | \end{center} 48 | \end{table} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/NAND2_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NAND2_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for NAND2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{11}{6} 40 | \usgate 41 | \gate[\inputs{2}]{nand}{5}{3}{R}{}{} % NAND 42 | \pin{1}{1}{L}{A} % pin A 43 | \pin{1}{5}{L}{A1} % pin A1 44 | \pin{10}{3}{R}{Y} % pin Y 45 | \end{circuitdiagram} 46 | \end{center} 47 | \end{figure} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/NAND2_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NAND2_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for NAND2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{NAND2 - a 2-input Not-AND (or NAND) gate} \label{logical:NAND2} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | NAND2 (Z A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{NAND2_circuit.tex} 44 | \input{NAND2_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | \input{NAND2_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/NAND2_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_NAND2.tex 13 | %% 14 | %% Purpose: Truth Table File for NAND2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | 36 | \begin{center} 37 | {\(Z = \lnot (B \land A) \)} 38 | \begin{table}[h] %\caption{\(Z = \lnot (B \land A) \)} 39 | \begin{center} 40 | \begin{tabular}{|c|c||c|} \hline 41 | B & A & Z \\ \hline\hline 42 | 0 & X & 1 \\ \hline 43 | 1 & 1 & 0 \\ \hline 44 | X & 0 & 1 \\ \hline 45 | \end{tabular} 46 | \end{center} 47 | \end{table} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/NAND3_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NAND3_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for NAND3 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{11}{6} 40 | \usgate 41 | \gate[\inputs{3}]{nand}{5}{3}{R}{}{} % NAND 42 | \pin{1}{1}{L}{A} % pin A 43 | \pin{1}{3}{L}{A1} % pin A1 44 | \pin{1}{5}{L}{A2} % pin A2 45 | \pin{10}{3}{R}{Y} % pin Y 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/NAND3_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NAND3_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for NAND3 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{NAND3 - a 3-input Not-AND (or NAND) gate} \label{logical:NAND3} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | NAND3 (Z A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{NAND3_circuit.tex} 44 | \input{NAND3_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | \input{NAND3_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/NOR2_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NOR2_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for NOR2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] %\caption{Circuit} 38 | \begin{center} 39 | \begin{circuitdiagram}{11}{6} 40 | \usgate 41 | \gate[\inputs{2}]{nor}{5}{3}{R}{}{} % NOR 42 | \pin{1}{1}{L}{A} % pin A 43 | \pin{1}{5}{L}{A1} % pin A1 44 | \pin{10}{3}{R}{Y} % pin Y 45 | \end{circuitdiagram} 46 | \end{center} 47 | \end{figure} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/NOR2_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NOR2_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for NOR2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{NOR2 - a 2-input Not-OR (or NOR) gate} \label{logical:NOR2} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | NOR2 (Z A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{NOR2_circuit.tex} 44 | \input{NOR2_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | \input{NOR2_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/NOR2_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_NOR2.tex 13 | %% 14 | %% Purpose: Truth Table File for NOR2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | 36 | \begin{center} 37 | {\(Z = \lnot (B \lor A) \)} 38 | \begin{table}[h] %\caption{\(Z = \lnot (B \lor A) \)} 39 | \begin{center} 40 | \begin{tabular}{|c|c||c|} \hline 41 | B & A & Z \\ \hline\hline 42 | 0 & 0 & 1 \\ \hline 43 | 1 & X & 0 \\ \hline 44 | X & 1 & 0 \\ \hline 45 | \end{tabular} 46 | \end{center} 47 | \end{table} 48 | \end{center} 49 | -------------------------------------------------------------------------------- /Documents/LaTeX/NOR3_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NOR3_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for NOR3 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{11}{6} 40 | \usgate 41 | \gate[\inputs{3}]{nor}{5}{3}{R}{}{} % NOR 42 | \pin{1}{1}{L}{A} % pin A 43 | \pin{1}{3}{L}{A1} % pin A1 44 | \pin{1}{5}{L}{A2} % pin A2 45 | \pin{10}{3}{R}{Y} % pin Y 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/NOR3_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/NOR3_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for NOR3 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{NOR3 - a 3-input Not-OR (or NOR) gate} \label{logical:NOR3} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | NOR3 (Z A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{NOR3_circuit.tex} 44 | \input{NOR3_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | \input{NOR3_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/OA21_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OA21_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for OA21 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{OA21 - a 2-1-input OR-AND gate} \label{logical:OA21} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | OA21 (Z B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{OA21_circuit.tex} 44 | %\input{OA21_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{OA21_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/OA22_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OA22_manpage.tex 13 | %% 14 | %% Purpose: Manual Page File for OA22 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \label{OA22} 36 | \paragraph{Cell} 37 | \begin{quote} 38 | \textbf{OA22} - a 2-2-input OR-AND gate 39 | \end{quote} 40 | 41 | \paragraph{Synopsys} 42 | \begin{quote} 43 | OA22(Z, B1, B, A1, A) 44 | \end{quote} 45 | 46 | \paragraph{Description} 47 | \input{OA22_circuit.tex} 48 | %\input{OA22_schematic.tex} 49 | 50 | \paragraph{Truth Table} 51 | %\input{OA22_truthtable.tex} 52 | 53 | \paragraph{Usage} 54 | 55 | \paragraph{Fan-in / Fan-out} 56 | 57 | \paragraph{Layout} 58 | 59 | \paragraph{Files} 60 | -------------------------------------------------------------------------------- /Documents/LaTeX/OA31_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OA31_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for OA31 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{OA31 - a 3-1-input OR-AND gate} \label{logical:OA31} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | OA31 (Z B2 B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{OA31_circuit.tex} 44 | %\input{OA31_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{OA31_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/OA41_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OA41_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for OA41 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{OA41 - a 4-1-input OR-AND gate} \label{logical:OA41} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | OA41 (Z B3 B2 B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{OA41_circuit.tex} 44 | %\input{OA41_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{OA41_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/OAI21_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OAI21_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for OAI21 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{OAI21 - a 2-1-input OR-AND-Invert gate} \label{logical:OAI21} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | OAI21 (Z B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{OAI21_circuit.tex} 44 | \input{OAI21_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | \input{OAI21_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/OAI41_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OAI41_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for OAI41 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{OAI41 - a 4-1-input OR-AND-Invert gate} \label{logical:OAI41} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | OAI41 (Z B3 B2 B1 B A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{OAI41_circuit.tex} 44 | %\input{OAI41_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{OAI41_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/OR2_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OR2_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for OR2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{17}{6} 40 | \usgate 41 | \gate[\inputs{2}]{nor}{5}{3}{R}{}{} % NOR 42 | \gate{not}{12}{3}{R}{}{} % NOT 43 | \pin{1}{1}{L}{A} % pin A 44 | \pin{1}{5}{L}{A1} % pin A1 45 | \pin{16}{3}{R}{Z} % pin Z 46 | \end{circuitdiagram} 47 | \end{center} 48 | \end{figure} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/OR2_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OR2_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for OR2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{OR2 - a 2-input OR gate} \label{logical:OR2} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | OR2 (Z A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{OR2_circuit.tex} 44 | %\input{OR2_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{OR2_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/OR3_manpage.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/OR3_manpage.tex 13 | %% 14 | %% Purpose: Auto-generated Manual Page for OR3 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \subsection{OR3 - a 3-input OR gate} \label{logical:OR3} 36 | 37 | \paragraph{Synopsys} 38 | \begin{quote} 39 | OR3 (Z A2 A1 A) 40 | \end{quote} 41 | 42 | \paragraph{Description} 43 | \input{OR3_circuit.tex} 44 | %\input{OR3_schematic.tex} 45 | 46 | \paragraph{Truth Table} 47 | %\input{OR3_truthtable.tex} 48 | 49 | \paragraph{Usage} 50 | 51 | \paragraph{Fan-in / Fan-out} 52 | 53 | \paragraph{Layout} 54 | 55 | \paragraph{Files} 56 | 57 | \clearpage 58 | -------------------------------------------------------------------------------- /Documents/LaTeX/TIE0_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/TIE0_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for TIE0 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{8}{8} 40 | \resis{2}{4}{V}{R}{} % pull down R 41 | \ground{2}{0.5}{D} 42 | \wire{2}{7}{6}{7} % pin Y 43 | \pin{7}{7}{R}{Y} % pin Y 44 | \end{circuitdiagram} 45 | \end{center} 46 | \end{figure} 47 | \end{center} 48 | -------------------------------------------------------------------------------- /Documents/LaTeX/TIE0_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_TIE0.tex 13 | %% 14 | %% Purpose: Truth Table File for TIE0 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | {\(Z = 0 \)} 37 | \begin{table}[h] %\caption{\(Z = 0 \)} 38 | \begin{center} 39 | \begin{tabular}{||c|} \hline 40 | Z \\ \hline\hline 41 | 0 \\ \hline 42 | \end{tabular} 43 | \end{center} 44 | \end{table} 45 | \end{center} 46 | -------------------------------------------------------------------------------- /Documents/LaTeX/TIE1_circuit.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/TIE1_circuit.tex 13 | %% 14 | %% Purpose: Circuit File for TIE1 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2019 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Circuit 37 | \begin{figure}[h] 38 | \begin{center} 39 | \begin{circuitdiagram}{8}{8} 40 | \resis{2}{4}{V}{R}{} % pull up R 41 | \power{2}{7.5}{U}{} 42 | \wire{2}{1}{6}{1} % pin Y 43 | \pin{7}{1}{R}{Y} % pin Y 44 | \end{circuitdiagram} 45 | \end{center} 46 | \end{figure} 47 | \end{center} 48 | -------------------------------------------------------------------------------- /Documents/LaTeX/TIE1_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_TIE1.tex 13 | %% 14 | %% Purpose: Truth Table File for TIE1 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | {\(Z = 1 \)} 37 | \begin{table}[h] %\caption{\(Z = 1 \)} 38 | \begin{center} 39 | \begin{tabular}{||c|} \hline 40 | Z \\ \hline\hline 41 | 1 \\ \hline 42 | \end{tabular} 43 | \end{center} 44 | \end{table} 45 | \end{center} 46 | -------------------------------------------------------------------------------- /Documents/LaTeX/XOR2_files.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/files_XOR2.tex 13 | %% 14 | %% Purpose: File list for XOR2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | \begin{center} 36 | Simulation 37 | \begin{itemize} 38 | \item[$\square$] \texttt{./Sources/verilog/XOR2.v} - Verilog-95 Cell Model \\ 39 | \item[$\square$] \texttt{./Sources/verilog/XOR2\_switch.v} - Verilog-2001 Switch-Level Model \\ 40 | \item[$\square$] \texttt{./TBench/verilog/tb\_XOR2.v} - Verilog-2001 Self-checking Testbench 41 | \end{itemize} 42 | Physical Layout 43 | \begin{itemize} 44 | \item[\checkmark] \texttt{?} 45 | \end{itemize} 46 | \end{center} 47 | -------------------------------------------------------------------------------- /Documents/LaTeX/XOR2_truthtable.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/truthtable_XOR2.tex 13 | %% 14 | %% Purpose: Truth Table File for XOR2 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | 36 | \begin{center} 37 | {\(Z = B \oplus A \)} 38 | \begin{table}[h] %\caption{\(Z = B \oplus A \)} 39 | \begin{center} 40 | \begin{tabular}{|c|c||c|} \hline 41 | B & A & Z \\ \hline\hline 42 | 0 & 0 & 0 \\ \hline 43 | 0 & 1 & 1 \\ \hline 44 | 1 & 0 & 1 \\ \hline 45 | 1 & 1 & 0 \\ \hline 46 | \end{tabular} 47 | \end{center} 48 | \end{table} 49 | \end{center} 50 | -------------------------------------------------------------------------------- /Documents/LaTeX/global_color_scheme.tex: -------------------------------------------------------------------------------- 1 | \usepackage[dvipsnames]{xcolor} 2 | \definecolor{substrate}{rgb}{0.82, 0.41, 0.12} 3 | \definecolor{nitride}{rgb}{1.0, 0.03, 0.0} 4 | \definecolor{pimplant}{rgb}{0.93, 0.23, 0.51} 5 | \definecolor{nimplant}{rgb}{0.0, 0.72, 0.92} 6 | \definecolor{gateoxide}{rgb}{0.8, 0.8, 0.8} 7 | \definecolor{isolationoxide}{rgb}{0.5, 0.5, 0.5} 8 | \definecolor{metal1}{rgb}{0.0, 0.55, 0.55} 9 | \definecolor{resist}{rgb}{1.0, 0.5, 0.31} 10 | \definecolor{nwell}{rgb}{0.98, 0.93, 0.36} -------------------------------------------------------------------------------- /Documents/LaTeX/revision.tex: -------------------------------------------------------------------------------- 1 | %% ************ LibreSilicon's StdCellLibrary ******************* 2 | %% 3 | %% Organisation: Chipforge 4 | %% Germany / European Union 5 | %% 6 | %% Profile: Chipforge focus on fine System-on-Chip Cores in 7 | %% Verilog HDL Code which are easy understandable and 8 | %% adjustable. For further information see 9 | %% www.chipforge.org 10 | %% there are projects from small cores up to PCBs, too. 11 | %% 12 | %% File: StdCellLib/Documents/LaTeX/revisio.tex 13 | %% 14 | %% Purpose: Revision History File 15 | %% 16 | %% ************ LaTeX with circdia.sty package *************** 17 | %% 18 | %% /////////////////////////////////////////////////////////////////// 19 | %% 20 | %% Copyright (c) 2018 by chipforge 21 | %% All rights reserved. 22 | %% 23 | %% This Standard Cell Library is licensed under the Libre Silicon 24 | %% public license; you can redistribute it and/or modify it under 25 | %% the terms of the Libre Silicon public license as published by 26 | %% the Libre Silicon alliance, either version 1 of the License, or 27 | %% (at your option) any later version. 28 | %% 29 | %% This design is distributed in the hope that it will be useful, 30 | %% but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | %% See the Libre Silicon Public License for more details. 33 | %% 34 | %% /////////////////////////////////////////////////////////////////// 35 | Document Revision History 36 | \begin{table}[h] %\caption{Document Revision History} 37 | \begin{tabular}{|l|c|ll|} \hline 38 | VERSION & DATE & DESCRIPTION & TRACKING NOTES\\ \hline\hline 39 | Draft 0.0 & 2018-02-01 & START with empty document, ADD many cells & -\\ \hline 40 | \end{tabular} 41 | \end{table} 42 | 43 | 44 | -------------------------------------------------------------------------------- /Documents/StdCellLib.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/thesourcerer8/StdCellLib/76d19180b1b7de90035ed1d3de1ae25aeea5ef3b/Documents/StdCellLib.pdf -------------------------------------------------------------------------------- /Simulation/verilog/EQ2.do: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Sun Feb 18 15:28:18 2018 4 | [*] 5 | [dumpfile_mtime] "Sun Feb 18 15:27:20 2018" 6 | [dumpfile_size] 1647 7 | [timestart] 0 8 | [size] 1318 671 9 | [pos] -1 -1 10 | *-16.225574 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [treeopen] tb_EQ2. 12 | [sst_width] 196 13 | [signals_width] 78 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 175 16 | @28 17 | tb_EQ2.dut_switch.B 18 | tb_EQ2.dut_switch.A 19 | tb_EQ2.dut_switch.Z 20 | tb_EQ2.dut_cell.B 21 | tb_EQ2.dut_cell.A 22 | tb_EQ2.dut_cell.Z 23 | @23 24 | tb_EQ2.failed 25 | [pattern_trace] 1 26 | [pattern_trace] 0 27 | -------------------------------------------------------------------------------- /Simulation/verilog/XOR2.do: -------------------------------------------------------------------------------- 1 | @28 2 | XOR2_stim.r_stimuli[1:0] 3 | @29 4 | XOR2_stim.w_response 5 | -------------------------------------------------------------------------------- /Sources/geda/BUF2.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | L 300 100 300 700 3 0 0 0 -1 -1 3 | L 300 100 800 400 3 0 0 0 -1 -1 4 | L 300 700 800 400 3 0 0 0 -1 -1 5 | P 1100 400 800 400 1 0 0 6 | { 7 | T 800 450 5 10 0 0 0 6 1 8 | pintype=out 9 | T 800 450 5 10 0 0 0 6 1 10 | pinseq=1 11 | T 742 392 9 10 0 1 0 6 1 12 | pinlabel=Z 13 | T 892 442 5 10 0 1 0 0 1 14 | pinnumber=1 15 | } 16 | P 0 400 300 400 1 0 0 17 | { 18 | T 100 450 5 10 0 0 0 0 1 19 | pintype=in 20 | T 100 450 5 10 0 0 0 0 1 21 | pinseq=2 22 | T 358 392 9 10 0 1 0 0 1 23 | pinlabel=A 24 | T 208 442 5 10 0 1 0 6 1 25 | pinnumber=2 26 | } 27 | P 600 800 600 500 1 0 0 28 | { 29 | T 650 700 5 10 0 0 270 0 1 30 | pintype=pwr 31 | T 650 700 5 10 0 0 270 0 1 32 | pinseq=3 33 | T 600 445 9 10 0 1 90 6 1 34 | pinlabel=VDD 35 | T 550 595 5 10 0 1 90 0 1 36 | pinnumber=3 37 | } 38 | P 600 0 600 300 1 0 0 39 | { 40 | T 550 100 5 10 0 0 90 0 1 41 | pintype=pwr 42 | T 550 100 5 10 0 0 90 0 1 43 | pinseq=4 44 | T 600 355 9 10 0 1 90 0 1 45 | pinlabel=GND 46 | T 550 205 5 10 0 1 90 6 1 47 | pinnumber=4 48 | } 49 | T 292 292 5 16 1 1 0 0 1 50 | device=BUF2 51 | T 1292 2092 8 10 0 1 0 0 1 52 | description=BUF2 - Non-inverting Buffer (2x) 53 | T 292 789 5 10 1 1 0 0 1 54 | refdes=X? 55 | T 1892 1192 8 10 0 0 0 0 1 56 | footprint=none 57 | T -8 -208 8 10 0 1 0 0 1 58 | source=BUF2.sch 59 | T 600 -100 9 10 0 0 0 0 1 60 | numslots=0 61 | -------------------------------------------------------------------------------- /Sources/geda/CGN2.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | P 1800 1600 1500 1600 1 0 0 4 | { 5 | T 1500 1650 5 10 0 0 0 6 1 6 | pintype=out 7 | T 1442 1592 9 10 1 1 0 6 1 8 | pinlabel=XO 9 | T 1592 1642 5 10 0 1 0 0 1 10 | pinnumber=1 11 | T 1500 1650 5 10 0 0 0 6 1 12 | pinseq=1 13 | } 14 | P 0 1600 300 1600 1 0 0 15 | { 16 | T 100 1650 5 10 0 0 0 0 1 17 | pintype=in 18 | T 100 1650 5 10 0 0 0 0 1 19 | pinseq=2 20 | T 358 1592 9 10 1 1 0 0 1 21 | pinlabel=EN 22 | T 208 1542 5 10 0 1 0 6 1 23 | pinnumber=2 24 | } 25 | P 0 600 300 600 1 0 0 26 | { 27 | T 100 650 5 10 0 0 0 0 1 28 | pintype=clk 29 | T 100 650 5 10 0 0 0 0 1 30 | pinseq=3 31 | T 358 592 9 10 1 1 0 0 1 32 | pinlabel=XI 33 | T 208 642 5 10 0 1 0 6 1 34 | pinnumber=3 35 | } 36 | P 1200 2200 1200 1900 1 0 0 37 | { 38 | T 1150 1900 5 10 0 0 90 6 1 39 | pintype=pwr 40 | T 1200 1845 9 10 1 1 90 6 1 41 | pinlabel=VDD 42 | T 1150 1995 5 10 0 1 90 0 1 43 | pinnumber=4 44 | T 1150 1900 5 10 0 0 90 6 1 45 | pinseq=4 46 | } 47 | P 1200 0 1200 300 1 0 0 48 | { 49 | T 1250 300 5 10 0 0 270 6 1 50 | pintype=pwr 51 | T 1200 355 9 10 1 1 90 0 1 52 | pinlabel=GND 53 | T 1150 205 5 10 0 1 90 6 1 54 | pinnumber=5 55 | T 1250 300 5 10 0 0 270 6 1 56 | pinseq=5 57 | } 58 | T 492 992 5 16 1 1 0 0 1 59 | device=CGN2 60 | T 1292 2292 8 10 0 1 0 0 1 61 | description=Clock Gating Buffer for negative Clock, Drive 2x 62 | T 292 1989 5 10 1 1 0 0 1 63 | refdes=X? 64 | T 1892 1392 8 10 0 0 0 0 1 65 | footprint=none 66 | T -8 -8 8 10 0 1 0 0 1 67 | source=CGN2.sch 68 | T 600 100 9 10 0 0 0 0 1 69 | numslots=0 70 | -------------------------------------------------------------------------------- /Sources/geda/CGP2.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | P 1800 1600 1500 1600 1 0 0 4 | { 5 | T 1500 1650 5 10 0 0 0 6 1 6 | pintype=out 7 | T 1442 1592 9 10 1 1 0 6 1 8 | pinlabel=XO 9 | T 1592 1642 5 10 0 1 0 0 1 10 | pinnumber=1 11 | T 1500 1650 5 10 0 0 0 6 1 12 | pinseq=1 13 | } 14 | P 0 1600 300 1600 1 0 0 15 | { 16 | T 100 1650 5 10 0 0 0 0 1 17 | pintype=in 18 | T 100 1650 5 10 0 0 0 0 1 19 | pinseq=2 20 | T 358 1592 9 10 1 1 0 0 1 21 | pinlabel=E 22 | T 208 1542 5 10 0 1 0 6 1 23 | pinnumber=2 24 | } 25 | P 0 600 300 600 1 0 0 26 | { 27 | T 100 650 5 10 0 0 0 0 1 28 | pintype=clk 29 | T 100 650 5 10 0 0 0 0 1 30 | pinseq=3 31 | T 358 592 9 10 1 1 0 0 1 32 | pinlabel=XI 33 | T 208 642 5 10 0 1 0 6 1 34 | pinnumber=3 35 | } 36 | P 1200 2200 1200 1900 1 0 0 37 | { 38 | T 1150 1900 5 10 0 0 90 6 1 39 | pintype=pwr 40 | T 1200 1845 9 10 1 1 90 6 1 41 | pinlabel=VDD 42 | T 1150 1995 5 10 0 1 90 0 1 43 | pinnumber=4 44 | T 1150 1900 5 10 0 0 90 6 1 45 | pinseq=4 46 | } 47 | P 1200 0 1200 300 1 0 0 48 | { 49 | T 1250 300 5 10 0 0 270 6 1 50 | pintype=pwr 51 | T 1200 355 9 10 1 1 90 0 1 52 | pinlabel=GND 53 | T 1150 205 5 10 0 1 90 6 1 54 | pinnumber=5 55 | T 1250 300 5 10 0 0 270 6 1 56 | pinseq=5 57 | } 58 | T 492 992 5 16 1 1 0 0 1 59 | device=CGP2 60 | T 1292 2292 8 10 0 1 0 0 1 61 | description=Clock Gating Buffer for positive Clock, Drive 2x 62 | T 292 1989 5 10 1 1 0 0 1 63 | refdes=X? 64 | T 1892 1392 8 10 0 0 0 0 1 65 | footprint=none 66 | T -8 -8 8 10 0 1 0 0 1 67 | source=CGP2.sch 68 | T 600 100 9 10 0 0 0 0 1 69 | numslots=0 70 | -------------------------------------------------------------------------------- /Sources/geda/DFFN.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | L 300 700 400 600 3 0 0 0 -1 -1 5 | L 400 600 300 500 3 0 0 0 -1 -1 6 | P 1800 1600 1500 1600 1 0 0 7 | { 8 | T 1500 1650 5 10 0 0 0 6 1 9 | pintype=out 10 | T 1442 1592 9 10 1 1 0 6 1 11 | pinlabel=Q 12 | T 1592 1642 5 10 0 1 0 0 1 13 | pinnumber=1 14 | T 1500 1650 5 10 0 0 0 6 1 15 | pinseq=1 16 | } 17 | P 0 1600 300 1600 1 0 0 18 | { 19 | T 100 1650 5 10 0 0 0 0 1 20 | pintype=in 21 | T 100 1650 5 10 0 0 0 0 1 22 | pinseq=2 23 | T 358 1592 9 10 1 1 0 0 1 24 | pinlabel=D 25 | T 208 1542 5 10 0 1 0 6 1 26 | pinnumber=2 27 | } 28 | P 0 600 200 600 1 0 0 29 | { 30 | T 100 650 5 10 0 0 0 0 1 31 | pintype=clk 32 | T 100 650 5 10 0 0 0 0 1 33 | pinseq=3 34 | T 450 550 9 10 1 1 0 0 1 35 | pinlabel=XN 36 | T 208 642 5 10 0 1 0 6 1 37 | pinnumber=3 38 | } 39 | P 1200 2200 1200 1900 1 0 0 40 | { 41 | T 1150 1900 5 10 0 0 90 6 1 42 | pintype=pwr 43 | T 1200 1845 9 10 1 1 90 6 1 44 | pinlabel=VDD 45 | T 1150 1995 5 10 0 1 90 0 1 46 | pinnumber=4 47 | T 1150 1900 5 10 0 0 90 6 1 48 | pinseq=4 49 | } 50 | P 1200 0 1200 300 1 0 0 51 | { 52 | T 1250 300 5 10 0 0 270 6 1 53 | pintype=pwr 54 | T 1200 355 9 10 1 1 90 0 1 55 | pinlabel=GND 56 | T 1150 205 5 10 0 1 90 6 1 57 | pinnumber=5 58 | T 1250 300 5 10 0 0 270 6 1 59 | pinseq=5 60 | } 61 | T 492 992 5 16 1 1 0 0 1 62 | device=DFFN 63 | T 1292 2292 8 10 0 1 0 0 1 64 | description=Low-active D-FLipFlop 65 | T 292 1989 5 10 1 1 0 0 1 66 | refdes=X? 67 | T 1892 1392 8 10 0 0 0 0 1 68 | footprint=none 69 | T -8 -8 8 10 0 1 0 0 1 70 | source=LATN.sch 71 | T 600 100 9 10 0 0 0 0 1 72 | numslots=0 73 | -------------------------------------------------------------------------------- /Sources/geda/DFFP.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | L 300 700 400 600 3 0 0 0 -1 -1 4 | L 400 600 300 500 3 0 0 0 -1 -1 5 | P 1800 1600 1500 1600 1 0 0 6 | { 7 | T 1500 1650 5 10 0 0 0 6 1 8 | pintype=out 9 | T 1442 1592 9 10 1 1 0 6 1 10 | pinlabel=Q 11 | T 1592 1642 5 10 0 1 0 0 1 12 | pinnumber=1 13 | T 1500 1650 5 10 0 0 0 6 1 14 | pinseq=1 15 | } 16 | P 0 1600 300 1600 1 0 0 17 | { 18 | T 100 1650 5 10 0 0 0 0 1 19 | pintype=in 20 | T 100 1650 5 10 0 0 0 0 1 21 | pinseq=2 22 | T 358 1592 9 10 1 1 0 0 1 23 | pinlabel=D 24 | T 208 1542 5 10 0 1 0 6 1 25 | pinnumber=2 26 | } 27 | P 0 600 300 600 1 0 0 28 | { 29 | T 100 650 5 10 0 0 0 0 1 30 | pintype=clk 31 | T 100 650 5 10 0 0 0 0 1 32 | pinseq=3 33 | T 450 550 9 10 1 1 0 0 1 34 | pinlabel=X 35 | T 208 642 5 10 0 1 0 6 1 36 | pinnumber=3 37 | } 38 | P 1200 2200 1200 1900 1 0 0 39 | { 40 | T 1150 1900 5 10 0 0 90 6 1 41 | pintype=pwr 42 | T 1200 1845 9 10 1 1 90 6 1 43 | pinlabel=VDD 44 | T 1150 1995 5 10 0 1 90 0 1 45 | pinnumber=4 46 | T 1150 1900 5 10 0 0 90 6 1 47 | pinseq=4 48 | } 49 | P 1200 0 1200 300 1 0 0 50 | { 51 | T 1250 300 5 10 0 0 270 6 1 52 | pintype=pwr 53 | T 1200 355 9 10 1 1 90 0 1 54 | pinlabel=GND 55 | T 1150 205 5 10 0 1 90 6 1 56 | pinnumber=5 57 | T 1250 300 5 10 0 0 270 6 1 58 | pinseq=5 59 | } 60 | T 492 992 5 16 1 1 0 0 1 61 | device=DFFP 62 | T 1292 2292 8 10 0 1 0 0 1 63 | description=High-active D-FlipFlop 64 | T 292 1989 5 10 1 1 0 0 1 65 | refdes=X? 66 | T 1892 1392 8 10 0 0 0 0 1 67 | footprint=none 68 | T -8 -8 8 10 0 1 0 0 1 69 | source=LATP.sch 70 | T 600 100 9 10 0 0 0 0 1 71 | numslots=0 72 | -------------------------------------------------------------------------------- /Sources/geda/FO4.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | L 300 100 300 700 3 0 0 0 -1 -1 3 | L 300 100 800 400 3 0 0 0 -1 -1 4 | L 300 700 800 400 3 0 0 0 -1 -1 5 | P 1100 400 800 400 1 0 0 6 | { 7 | T 800 450 5 10 0 0 0 6 1 8 | pintype=out 9 | T 800 450 5 10 0 0 0 6 1 10 | pinseq=1 11 | T 742 392 9 10 0 1 0 6 1 12 | pinlabel=Z 13 | T 892 442 5 10 0 1 0 0 1 14 | pinnumber=1 15 | } 16 | P 0 400 300 400 1 0 0 17 | { 18 | T 100 450 5 10 0 0 0 0 1 19 | pintype=in 20 | T 100 450 5 10 0 0 0 0 1 21 | pinseq=2 22 | T 358 392 9 10 0 1 0 0 1 23 | pinlabel=A 24 | T 208 442 5 10 0 1 0 6 1 25 | pinnumber=2 26 | } 27 | P 600 800 600 500 1 0 0 28 | { 29 | T 650 700 5 10 0 0 270 0 1 30 | pintype=pwr 31 | T 650 700 5 10 0 0 270 0 1 32 | pinseq=3 33 | T 600 445 9 10 0 1 90 6 1 34 | pinlabel=VDD 35 | T 550 595 5 10 0 1 90 0 1 36 | pinnumber=3 37 | } 38 | P 600 0 600 300 1 0 0 39 | { 40 | T 550 100 5 10 0 0 90 0 1 41 | pintype=pwr 42 | T 550 100 5 10 0 0 90 0 1 43 | pinseq=4 44 | T 600 355 9 10 0 1 90 0 1 45 | pinlabel=GND 46 | T 550 205 5 10 0 1 90 6 1 47 | pinnumber=4 48 | } 49 | T 292 292 5 16 1 1 0 0 1 50 | device=FO4 51 | T 1292 2092 8 10 0 1 0 0 1 52 | description=FO4 - TBench Load with high (4x) fan-in 53 | T 292 789 5 10 1 1 0 0 1 54 | refdes=X? 55 | T 1892 1192 8 10 0 0 0 0 1 56 | footprint=none 57 | T -8 -208 8 10 0 1 0 0 1 58 | source=FO4.sch 59 | T 600 -100 9 10 0 0 0 0 1 60 | numslots=0 61 | -------------------------------------------------------------------------------- /Sources/geda/LATEN.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | P 1800 1600 1500 1600 1 0 0 5 | { 6 | T 1500 1650 5 10 0 0 0 6 1 7 | pintype=out 8 | T 1442 1592 9 10 1 1 0 6 1 9 | pinlabel=Q 10 | T 1592 1642 5 10 0 1 0 0 1 11 | pinnumber=1 12 | T 1500 1650 5 10 0 0 0 6 1 13 | pinseq=1 14 | } 15 | P 0 1600 300 1600 1 0 0 16 | { 17 | T 100 1650 5 10 0 0 0 0 1 18 | pintype=in 19 | T 100 1650 5 10 0 0 0 0 1 20 | pinseq=2 21 | T 358 1592 9 10 1 1 0 0 1 22 | pinlabel=D 23 | T 208 1542 5 10 0 1 0 6 1 24 | pinnumber=2 25 | } 26 | P 0 1300 200 1300 1 0 0 27 | { 28 | T 100 1350 5 10 0 0 0 0 1 29 | pintype=in 30 | T 100 1350 5 10 0 0 0 0 1 31 | pinseq=3 32 | T 358 1292 9 10 1 1 0 0 1 33 | pinlabel=EN 34 | T 208 1242 5 10 0 1 0 6 1 35 | pinnumber=3 36 | } 37 | P 0 600 200 600 1 0 0 38 | { 39 | T 100 650 5 10 0 0 0 0 1 40 | pintype=clk 41 | T 100 650 5 10 0 0 0 0 1 42 | pinseq=4 43 | T 358 592 9 10 1 1 0 0 1 44 | pinlabel=XN 45 | T 208 642 5 10 0 1 0 6 1 46 | pinnumber=4 47 | } 48 | P 1200 2200 1200 1900 1 0 0 49 | { 50 | T 1150 1900 5 10 0 0 90 6 1 51 | pintype=pwr 52 | T 1200 1845 9 10 1 1 90 6 1 53 | pinlabel=VDD 54 | T 1150 1995 5 10 0 1 90 0 1 55 | pinnumber=5 56 | T 1150 1900 5 10 0 0 90 6 1 57 | pinseq=5 58 | } 59 | P 1200 0 1200 300 1 0 0 60 | { 61 | T 1250 300 5 10 0 0 270 6 1 62 | pintype=pwr 63 | T 1200 355 9 10 1 1 90 0 1 64 | pinlabel=GND 65 | T 1150 205 5 10 0 1 90 6 1 66 | pinnumber=6 67 | T 1250 300 5 10 0 0 270 6 1 68 | pinseq=6 69 | } 70 | T 492 992 5 16 1 1 0 0 1 71 | device=LATEN 72 | T 1292 2292 8 10 0 1 0 0 1 73 | description=High-active D-Latch 74 | T 292 1989 5 10 1 1 0 0 1 75 | refdes=X? 76 | T 1892 1392 8 10 0 0 0 0 1 77 | footprint=none 78 | T -8 -8 8 10 0 1 0 0 1 79 | source=LATEN.sch 80 | T 600 100 9 10 0 0 0 0 1 81 | numslots=0 82 | V 250 1300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 83 | -------------------------------------------------------------------------------- /Sources/geda/LATEP.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | P 1800 1600 1500 1600 1 0 0 4 | { 5 | T 1500 1650 5 10 0 0 0 6 1 6 | pintype=out 7 | T 1442 1592 9 10 1 1 0 6 1 8 | pinlabel=Q 9 | T 1592 1642 5 10 0 1 0 0 1 10 | pinnumber=1 11 | T 1500 1650 5 10 0 0 0 6 1 12 | pinseq=1 13 | } 14 | P 0 1600 300 1600 1 0 0 15 | { 16 | T 100 1650 5 10 0 0 0 0 1 17 | pintype=in 18 | T 100 1650 5 10 0 0 0 0 1 19 | pinseq=2 20 | T 358 1592 9 10 1 1 0 0 1 21 | pinlabel=D 22 | T 208 1542 5 10 0 1 0 6 1 23 | pinnumber=2 24 | } 25 | P 0 1300 300 1300 1 0 0 26 | { 27 | T 100 1350 5 10 0 0 0 0 1 28 | pintype=in 29 | T 100 1350 5 10 0 0 0 0 1 30 | pinseq=3 31 | T 358 1292 9 10 1 1 0 0 1 32 | pinlabel=E 33 | T 208 1242 5 10 0 1 0 6 1 34 | pinnumber=3 35 | } 36 | P 0 600 300 600 1 0 0 37 | { 38 | T 100 650 5 10 0 0 0 0 1 39 | pintype=clk 40 | T 100 650 5 10 0 0 0 0 1 41 | pinseq=4 42 | T 358 592 9 10 1 1 0 0 1 43 | pinlabel=X 44 | T 208 642 5 10 0 1 0 6 1 45 | pinnumber=4 46 | } 47 | P 1200 2200 1200 1900 1 0 0 48 | { 49 | T 1150 1900 5 10 0 0 90 6 1 50 | pintype=pwr 51 | T 1200 1845 9 10 1 1 90 6 1 52 | pinlabel=VDD 53 | T 1150 1995 5 10 0 1 90 0 1 54 | pinnumber=5 55 | T 1150 1900 5 10 0 0 90 6 1 56 | pinseq=5 57 | } 58 | P 1200 0 1200 300 1 0 0 59 | { 60 | T 1250 300 5 10 0 0 270 6 1 61 | pintype=pwr 62 | T 1200 355 9 10 1 1 90 0 1 63 | pinlabel=GND 64 | T 1150 205 5 10 0 1 90 6 1 65 | pinnumber=6 66 | T 1250 300 5 10 0 0 270 6 1 67 | pinseq=6 68 | } 69 | T 492 992 5 16 1 1 0 0 1 70 | device=LATEP 71 | T 1292 2292 8 10 0 1 0 0 1 72 | description=High-active D-Latch w/ high-active Enable 73 | T 292 1989 5 10 1 1 0 0 1 74 | refdes=X? 75 | T 1892 1392 8 10 0 0 0 0 1 76 | footprint=none 77 | T -8 -8 8 10 0 1 0 0 1 78 | source=LATEP.sch 79 | T 600 100 9 10 0 0 0 0 1 80 | numslots=0 81 | -------------------------------------------------------------------------------- /Sources/geda/LATERN.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | P 1800 1600 1500 1600 1 0 0 5 | { 6 | T 1500 1650 5 10 0 0 0 6 1 7 | pintype=out 8 | T 1442 1592 9 10 1 1 0 6 1 9 | pinlabel=Q 10 | T 1592 1642 5 10 0 1 0 0 1 11 | pinnumber=1 12 | T 1500 1650 5 10 0 0 0 6 1 13 | pinseq=1 14 | } 15 | P 0 1600 300 1600 1 0 0 16 | { 17 | T 100 1650 5 10 0 0 0 0 1 18 | pintype=in 19 | T 100 1650 5 10 0 0 0 0 1 20 | pinseq=2 21 | T 358 1592 9 10 1 1 0 0 1 22 | pinlabel=D 23 | T 208 1542 5 10 0 1 0 6 1 24 | pinnumber=2 25 | } 26 | P 700 0 700 300 1 0 0 27 | { 28 | T 750 300 5 10 0 0 270 6 1 29 | pintype=in 30 | T 700 355 9 10 1 1 90 0 1 31 | pinlabel=R 32 | T 650 205 5 10 0 1 90 6 1 33 | pinnumber=3 34 | T 750 300 5 10 0 0 270 6 1 35 | pinseq=3 36 | } 37 | P 0 1300 200 1300 1 0 0 38 | { 39 | T 100 1350 5 10 0 0 0 0 1 40 | pintype=in 41 | T 100 1350 5 10 0 0 0 0 1 42 | pinseq=4 43 | T 358 1292 9 10 1 1 0 0 1 44 | pinlabel=EN 45 | T 208 1242 5 10 0 1 0 6 1 46 | pinnumber=4 47 | } 48 | P 0 600 200 600 1 0 0 49 | { 50 | T 100 650 5 10 0 0 0 0 1 51 | pintype=clk 52 | T 100 650 5 10 0 0 0 0 1 53 | pinseq=5 54 | T 358 592 9 10 1 1 0 0 1 55 | pinlabel=XN 56 | T 208 642 5 10 0 1 0 6 1 57 | pinnumber=5 58 | } 59 | P 1200 2200 1200 1900 1 0 0 60 | { 61 | T 1150 1900 5 10 0 0 90 6 1 62 | pintype=pwr 63 | T 1200 1845 9 10 1 1 90 6 1 64 | pinlabel=VDD 65 | T 1150 1995 5 10 0 1 90 0 1 66 | pinnumber=6 67 | T 1150 1900 5 10 0 0 90 6 1 68 | pinseq=6 69 | } 70 | P 1200 0 1200 300 1 0 0 71 | { 72 | T 1250 300 5 10 0 0 270 6 1 73 | pintype=pwr 74 | T 1200 355 9 10 1 1 90 0 1 75 | pinlabel=GND 76 | T 1150 205 5 10 0 1 90 6 1 77 | pinnumber=7 78 | T 1250 300 5 10 0 0 270 6 1 79 | pinseq=7 80 | } 81 | T 392 992 5 16 1 1 0 0 1 82 | device=LATERN 83 | T 1292 2292 8 10 0 1 0 0 1 84 | description=Low-active D-Latch w/ clock-enable + high-active Reset 85 | T 292 1989 5 10 1 1 0 0 1 86 | refdes=X? 87 | T 1892 1392 8 10 0 0 0 0 1 88 | footprint=none 89 | T -8 -8 8 10 0 1 0 0 1 90 | source=LATERN.sch 91 | T 600 100 9 10 0 0 0 0 1 92 | numslots=0 93 | V 250 1300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 94 | -------------------------------------------------------------------------------- /Sources/geda/LATERP.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | P 1800 1600 1500 1600 1 0 0 4 | { 5 | T 1500 1650 5 10 0 0 0 6 1 6 | pintype=out 7 | T 1442 1592 9 10 1 1 0 6 1 8 | pinlabel=Q 9 | T 1592 1642 5 10 0 1 0 0 1 10 | pinnumber=1 11 | T 1500 1650 5 10 0 0 0 6 1 12 | pinseq=1 13 | } 14 | P 0 1600 300 1600 1 0 0 15 | { 16 | T 100 1650 5 10 0 0 0 0 1 17 | pintype=in 18 | T 100 1650 5 10 0 0 0 0 1 19 | pinseq=2 20 | T 358 1592 9 10 1 1 0 0 1 21 | pinlabel=D 22 | T 208 1542 5 10 0 1 0 6 1 23 | pinnumber=2 24 | } 25 | P 700 0 700 300 1 0 0 26 | { 27 | T 750 300 5 10 0 0 270 6 1 28 | pintype=in 29 | T 700 355 9 10 1 1 90 0 1 30 | pinlabel=R 31 | T 650 205 5 10 0 1 90 6 1 32 | pinnumber=3 33 | T 750 300 5 10 0 0 270 6 1 34 | pinseq=3 35 | } 36 | P 0 1300 300 1300 1 0 0 37 | { 38 | T 100 1350 5 10 0 0 0 0 1 39 | pintype=in 40 | T 100 1350 5 10 0 0 0 0 1 41 | pinseq=4 42 | T 358 1292 9 10 1 1 0 0 1 43 | pinlabel=E 44 | T 208 1242 5 10 0 1 0 6 1 45 | pinnumber=4 46 | } 47 | P 0 600 300 600 1 0 0 48 | { 49 | T 100 650 5 10 0 0 0 0 1 50 | pintype=clk 51 | T 100 650 5 10 0 0 0 0 1 52 | pinseq=5 53 | T 358 592 9 10 1 1 0 0 1 54 | pinlabel=X 55 | T 208 642 5 10 0 1 0 6 1 56 | pinnumber=5 57 | } 58 | P 1200 2200 1200 1900 1 0 0 59 | { 60 | T 1150 1900 5 10 0 0 90 6 1 61 | pintype=pwr 62 | T 1200 1845 9 10 1 1 90 6 1 63 | pinlabel=VDD 64 | T 1150 1995 5 10 0 1 90 0 1 65 | pinnumber=6 66 | T 1150 1900 5 10 0 0 90 6 1 67 | pinseq=6 68 | } 69 | P 1200 0 1200 300 1 0 0 70 | { 71 | T 1250 300 5 10 0 0 270 6 1 72 | pintype=pwr 73 | T 1200 355 9 10 1 1 90 0 1 74 | pinlabel=GND 75 | T 1150 205 5 10 0 1 90 6 1 76 | pinnumber=7 77 | T 1250 300 5 10 0 0 270 6 1 78 | pinseq=7 79 | } 80 | T 392 992 5 16 1 1 0 0 1 81 | device=LATERP 82 | T 1292 2292 8 10 0 1 0 0 1 83 | description=High-active D-Latch w/ clock-enable + low-active Set 84 | T 292 1989 5 10 1 1 0 0 1 85 | refdes=X? 86 | T 1892 1392 8 10 0 0 0 0 1 87 | footprint=none 88 | T -8 -8 8 10 0 1 0 0 1 89 | source=LATESP.sch 90 | T 600 100 9 10 0 0 0 0 1 91 | numslots=0 92 | -------------------------------------------------------------------------------- /Sources/geda/LATESP.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 700 1950 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | P 1800 1600 1500 1600 1 0 0 5 | { 6 | T 1500 1650 5 10 0 0 0 6 1 7 | pintype=out 8 | T 1442 1592 9 10 1 1 0 6 1 9 | pinlabel=Q 10 | T 1592 1642 5 10 0 1 0 0 1 11 | pinnumber=1 12 | T 1500 1650 5 10 0 0 0 6 1 13 | pinseq=1 14 | } 15 | P 0 1600 300 1600 1 0 0 16 | { 17 | T 100 1650 5 10 0 0 0 0 1 18 | pintype=in 19 | T 100 1650 5 10 0 0 0 0 1 20 | pinseq=2 21 | T 358 1592 9 10 1 1 0 0 1 22 | pinlabel=D 23 | T 208 1542 5 10 0 1 0 6 1 24 | pinnumber=2 25 | } 26 | P 700 2200 700 2000 1 0 0 27 | { 28 | T 650 1900 5 10 0 0 90 6 1 29 | pintype=in 30 | T 700 1845 9 10 1 1 90 6 1 31 | pinlabel=SN 32 | T 650 1995 5 10 0 1 90 0 1 33 | pinnumber=3 34 | T 650 1900 5 10 0 0 90 6 1 35 | pinseq=3 36 | } 37 | P 0 1300 300 1300 1 0 0 38 | { 39 | T 100 1350 5 10 0 0 0 0 1 40 | pintype=in 41 | T 100 1350 5 10 0 0 0 0 1 42 | pinseq=4 43 | T 358 1292 9 10 1 1 0 0 1 44 | pinlabel=E 45 | T 208 1242 5 10 0 1 0 6 1 46 | pinnumber=4 47 | } 48 | P 0 600 300 600 1 0 0 49 | { 50 | T 100 650 5 10 0 0 0 0 1 51 | pintype=clk 52 | T 100 650 5 10 0 0 0 0 1 53 | pinseq=5 54 | T 358 592 9 10 1 1 0 0 1 55 | pinlabel=X 56 | T 208 642 5 10 0 1 0 6 1 57 | pinnumber=5 58 | } 59 | P 1200 2200 1200 1900 1 0 0 60 | { 61 | T 1150 1900 5 10 0 0 90 6 1 62 | pintype=pwr 63 | T 1200 1845 9 10 1 1 90 6 1 64 | pinlabel=VDD 65 | T 1150 1995 5 10 0 1 90 0 1 66 | pinnumber=6 67 | T 1150 1900 5 10 0 0 90 6 1 68 | pinseq=6 69 | } 70 | P 1200 0 1200 300 1 0 0 71 | { 72 | T 1250 300 5 10 0 0 270 6 1 73 | pintype=pwr 74 | T 1200 355 9 10 1 1 90 0 1 75 | pinlabel=GND 76 | T 1150 205 5 10 0 1 90 6 1 77 | pinnumber=7 78 | T 1250 300 5 10 0 0 270 6 1 79 | pinseq=7 80 | } 81 | T 392 992 5 16 1 1 0 0 1 82 | device=LATESP 83 | T 1292 2292 8 10 0 1 0 0 1 84 | description=High-active D-Latch w/ clock-enable + low-active Set 85 | T 292 1989 5 10 1 1 0 0 1 86 | refdes=X? 87 | T 1892 1392 8 10 0 0 0 0 1 88 | footprint=none 89 | T -8 -8 8 10 0 1 0 0 1 90 | source=LATESP.sch 91 | T 600 100 9 10 0 0 0 0 1 92 | numslots=0 93 | -------------------------------------------------------------------------------- /Sources/geda/LATN.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | P 1800 1600 1500 1600 1 0 0 5 | { 6 | T 1500 1650 5 10 0 0 0 6 1 7 | pintype=out 8 | T 1442 1592 9 10 1 1 0 6 1 9 | pinlabel=Q 10 | T 1592 1642 5 10 0 1 0 0 1 11 | pinnumber=1 12 | T 1500 1650 5 10 0 0 0 6 1 13 | pinseq=1 14 | } 15 | P 0 1600 300 1600 1 0 0 16 | { 17 | T 100 1650 5 10 0 0 0 0 1 18 | pintype=in 19 | T 100 1650 5 10 0 0 0 0 1 20 | pinseq=2 21 | T 358 1592 9 10 1 1 0 0 1 22 | pinlabel=D 23 | T 208 1542 5 10 0 1 0 6 1 24 | pinnumber=2 25 | } 26 | P 0 600 200 600 1 0 0 27 | { 28 | T 100 650 5 10 0 0 0 0 1 29 | pintype=clk 30 | T 100 650 5 10 0 0 0 0 1 31 | pinseq=3 32 | T 350 550 9 10 1 1 0 0 1 33 | pinlabel=XN 34 | T 208 642 5 10 0 1 0 6 1 35 | pinnumber=3 36 | } 37 | P 1200 2200 1200 1900 1 0 0 38 | { 39 | T 1150 1900 5 10 0 0 90 6 1 40 | pintype=pwr 41 | T 1200 1845 9 10 1 1 90 6 1 42 | pinlabel=VDD 43 | T 1150 1995 5 10 0 1 90 0 1 44 | pinnumber=4 45 | T 1150 1900 5 10 0 0 90 6 1 46 | pinseq=4 47 | } 48 | P 1200 0 1200 300 1 0 0 49 | { 50 | T 1250 300 5 10 0 0 270 6 1 51 | pintype=pwr 52 | T 1200 355 9 10 1 1 90 0 1 53 | pinlabel=GND 54 | T 1150 205 5 10 0 1 90 6 1 55 | pinnumber=5 56 | T 1250 300 5 10 0 0 270 6 1 57 | pinseq=5 58 | } 59 | T 492 992 5 16 1 1 0 0 1 60 | device=LATN 61 | T 1292 2292 8 10 0 1 0 0 1 62 | description=Low-active D-Latch 63 | T 292 1989 5 10 1 1 0 0 1 64 | refdes=X? 65 | T 1892 1392 8 10 0 0 0 0 1 66 | footprint=none 67 | T -8 -8 8 10 0 1 0 0 1 68 | source=LATN.sch 69 | T 600 100 9 10 0 0 0 0 1 70 | numslots=0 71 | -------------------------------------------------------------------------------- /Sources/geda/LATP.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | P 1800 1600 1500 1600 1 0 0 4 | { 5 | T 1500 1650 5 10 0 0 0 6 1 6 | pintype=out 7 | T 1442 1592 9 10 1 1 0 6 1 8 | pinlabel=Q 9 | T 1592 1642 5 10 0 1 0 0 1 10 | pinnumber=1 11 | T 1500 1650 5 10 0 0 0 6 1 12 | pinseq=1 13 | } 14 | P 0 1600 300 1600 1 0 0 15 | { 16 | T 100 1650 5 10 0 0 0 0 1 17 | pintype=in 18 | T 100 1650 5 10 0 0 0 0 1 19 | pinseq=2 20 | T 358 1592 9 10 1 1 0 0 1 21 | pinlabel=D 22 | T 208 1542 5 10 0 1 0 6 1 23 | pinnumber=2 24 | } 25 | P 0 600 300 600 1 0 0 26 | { 27 | T 100 650 5 10 0 0 0 0 1 28 | pintype=clk 29 | T 100 650 5 10 0 0 0 0 1 30 | pinseq=3 31 | T 350 550 9 10 1 1 0 0 1 32 | pinlabel=X 33 | T 208 642 5 10 0 1 0 6 1 34 | pinnumber=3 35 | } 36 | P 1200 2200 1200 1900 1 0 0 37 | { 38 | T 1150 1900 5 10 0 0 90 6 1 39 | pintype=pwr 40 | T 1200 1845 9 10 1 1 90 6 1 41 | pinlabel=VDD 42 | T 1150 1995 5 10 0 1 90 0 1 43 | pinnumber=4 44 | T 1150 1900 5 10 0 0 90 6 1 45 | pinseq=4 46 | } 47 | P 1200 0 1200 300 1 0 0 48 | { 49 | T 1250 300 5 10 0 0 270 6 1 50 | pintype=pwr 51 | T 1200 355 9 10 1 1 90 0 1 52 | pinlabel=GND 53 | T 1150 205 5 10 0 1 90 6 1 54 | pinnumber=5 55 | T 1250 300 5 10 0 0 270 6 1 56 | pinseq=5 57 | } 58 | T 492 992 5 16 1 1 0 0 1 59 | device=LATP 60 | T 1292 2292 8 10 0 1 0 0 1 61 | description=High-active D-Latch 62 | T 292 1989 5 10 1 1 0 0 1 63 | refdes=X? 64 | T 1892 1392 8 10 0 0 0 0 1 65 | footprint=none 66 | T -8 -8 8 10 0 1 0 0 1 67 | source=LATP.sch 68 | T 600 100 9 10 0 0 0 0 1 69 | numslots=0 70 | -------------------------------------------------------------------------------- /Sources/geda/LATRN.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | P 1800 1600 1500 1600 1 0 0 5 | { 6 | T 1500 1650 5 10 0 0 0 6 1 7 | pintype=out 8 | T 1442 1592 9 10 1 1 0 6 1 9 | pinlabel=Q 10 | T 1592 1642 5 10 0 1 0 0 1 11 | pinnumber=1 12 | T 1500 1650 5 10 0 0 0 6 1 13 | pinseq=1 14 | } 15 | P 0 1600 300 1600 1 0 0 16 | { 17 | T 100 1650 5 10 0 0 0 0 1 18 | pintype=in 19 | T 100 1650 5 10 0 0 0 0 1 20 | pinseq=2 21 | T 358 1592 9 10 1 1 0 0 1 22 | pinlabel=D 23 | T 208 1542 5 10 0 1 0 6 1 24 | pinnumber=2 25 | } 26 | P 700 0 700 300 1 0 0 27 | { 28 | T 750 300 5 10 0 0 270 6 1 29 | pintype=in 30 | T 700 355 9 10 1 1 90 0 1 31 | pinlabel=R 32 | T 650 205 5 10 0 1 90 6 1 33 | pinnumber=3 34 | T 750 300 5 10 0 0 270 6 1 35 | pinseq=3 36 | } 37 | P 0 600 200 600 1 0 0 38 | { 39 | T 100 650 5 10 0 0 0 0 1 40 | pintype=clk 41 | T 100 650 5 10 0 0 0 0 1 42 | pinseq=4 43 | T 358 592 9 10 1 1 0 0 1 44 | pinlabel=XN 45 | T 208 642 5 10 0 1 0 6 1 46 | pinnumber=4 47 | } 48 | P 1200 2200 1200 1900 1 0 0 49 | { 50 | T 1150 1900 5 10 0 0 90 6 1 51 | pintype=pwr 52 | T 1200 1845 9 10 1 1 90 6 1 53 | pinlabel=VDD 54 | T 1150 1995 5 10 0 1 90 0 1 55 | pinnumber=5 56 | T 1150 1900 5 10 0 0 90 6 1 57 | pinseq=5 58 | } 59 | P 1200 0 1200 300 1 0 0 60 | { 61 | T 1250 300 5 10 0 0 270 6 1 62 | pintype=pwr 63 | T 1200 355 9 10 1 1 90 0 1 64 | pinlabel=GND 65 | T 1150 205 5 10 0 1 90 6 1 66 | pinnumber=6 67 | T 1250 300 5 10 0 0 270 6 1 68 | pinseq=6 69 | } 70 | T 492 992 5 16 1 1 0 0 1 71 | device=LATRN 72 | T 1292 2292 8 10 0 1 0 0 1 73 | description=Low-active D-Latch w/ high-active Reset 74 | T 292 1989 5 10 1 1 0 0 1 75 | refdes=X? 76 | T 1892 1392 8 10 0 0 0 0 1 77 | footprint=none 78 | T -8 -8 8 10 0 1 0 0 1 79 | source=LATRN.sch 80 | T 600 100 9 10 0 0 0 0 1 81 | numslots=0 82 | -------------------------------------------------------------------------------- /Sources/geda/LATRP.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | P 1800 1600 1500 1600 1 0 0 4 | { 5 | T 1500 1650 5 10 0 0 0 6 1 6 | pintype=out 7 | T 1442 1592 9 10 1 1 0 6 1 8 | pinlabel=Q 9 | T 1592 1642 5 10 0 1 0 0 1 10 | pinnumber=1 11 | T 1500 1650 5 10 0 0 0 6 1 12 | pinseq=1 13 | } 14 | P 0 1600 300 1600 1 0 0 15 | { 16 | T 100 1650 5 10 0 0 0 0 1 17 | pintype=in 18 | T 100 1650 5 10 0 0 0 0 1 19 | pinseq=2 20 | T 358 1592 9 10 1 1 0 0 1 21 | pinlabel=D 22 | T 208 1542 5 10 0 1 0 6 1 23 | pinnumber=2 24 | } 25 | P 700 0 700 300 1 0 0 26 | { 27 | T 750 300 5 10 0 0 270 6 1 28 | pintype=in 29 | T 700 355 9 10 1 1 90 0 1 30 | pinlabel=R 31 | T 650 205 5 10 0 1 90 6 1 32 | pinnumber=3 33 | T 750 300 5 10 0 0 270 6 1 34 | pinseq=3 35 | } 36 | P 0 600 300 600 1 0 0 37 | { 38 | T 100 650 5 10 0 0 0 0 1 39 | pintype=clk 40 | T 100 650 5 10 0 0 0 0 1 41 | pinseq=4 42 | T 358 592 9 10 1 1 0 0 1 43 | pinlabel=X 44 | T 208 642 5 10 0 1 0 6 1 45 | pinnumber=4 46 | } 47 | P 1200 2200 1200 1900 1 0 0 48 | { 49 | T 1150 1900 5 10 0 0 90 6 1 50 | pintype=pwr 51 | T 1200 1845 9 10 1 1 90 6 1 52 | pinlabel=VDD 53 | T 1150 1995 5 10 0 1 90 0 1 54 | pinnumber=5 55 | T 1150 1900 5 10 0 0 90 6 1 56 | pinseq=5 57 | } 58 | P 1200 0 1200 300 1 0 0 59 | { 60 | T 1250 300 5 10 0 0 270 6 1 61 | pintype=pwr 62 | T 1200 355 9 10 1 1 90 0 1 63 | pinlabel=GND 64 | T 1150 205 5 10 0 1 90 6 1 65 | pinnumber=6 66 | T 1250 300 5 10 0 0 270 6 1 67 | pinseq=6 68 | } 69 | T 492 992 5 16 1 1 0 0 1 70 | device=LATRP 71 | T 1292 2292 8 10 0 1 0 0 1 72 | description=High-active D-Latch w/ high-active Reset 73 | T 292 1989 5 10 1 1 0 0 1 74 | refdes=X? 75 | T 1892 1392 8 10 0 0 0 0 1 76 | footprint=none 77 | T -8 -8 8 10 0 1 0 0 1 78 | source=LATRP.sch 79 | T 600 100 9 10 0 0 0 0 1 80 | numslots=0 81 | -------------------------------------------------------------------------------- /Sources/geda/LATSN.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | V 700 1950 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 5 | P 1800 1600 1500 1600 1 0 0 6 | { 7 | T 1500 1650 5 10 0 0 0 6 1 8 | pintype=out 9 | T 1442 1592 9 10 1 1 0 6 1 10 | pinlabel=Q 11 | T 1592 1642 5 10 0 1 0 0 1 12 | pinnumber=1 13 | T 1500 1650 5 10 0 0 0 6 1 14 | pinseq=1 15 | } 16 | P 0 1600 300 1600 1 0 0 17 | { 18 | T 100 1650 5 10 0 0 0 0 1 19 | pintype=in 20 | T 100 1650 5 10 0 0 0 0 1 21 | pinseq=2 22 | T 358 1592 9 10 1 1 0 0 1 23 | pinlabel=D 24 | T 208 1542 5 10 0 1 0 6 1 25 | pinnumber=2 26 | } 27 | P 700 2200 700 2000 1 0 0 28 | { 29 | T 650 1900 5 10 0 0 90 6 1 30 | pintype=in 31 | T 700 1845 9 10 1 1 90 6 1 32 | pinlabel=SN 33 | T 650 1995 5 10 0 1 90 0 1 34 | pinnumber=3 35 | T 650 1900 5 10 0 0 90 6 1 36 | pinseq=3 37 | } 38 | P 0 600 200 600 1 0 0 39 | { 40 | T 100 650 5 10 0 0 0 0 1 41 | pintype=clk 42 | T 100 650 5 10 0 0 0 0 1 43 | pinseq=4 44 | T 358 592 9 10 1 1 0 0 1 45 | pinlabel=XN 46 | T 208 642 5 10 0 1 0 6 1 47 | pinnumber=4 48 | } 49 | P 1200 2200 1200 1900 1 0 0 50 | { 51 | T 1150 1900 5 10 0 0 90 6 1 52 | pintype=pwr 53 | T 1200 1845 9 10 1 1 90 6 1 54 | pinlabel=VDD 55 | T 1150 1995 5 10 0 1 90 0 1 56 | pinnumber=5 57 | T 1150 1900 5 10 0 0 90 6 1 58 | pinseq=5 59 | } 60 | P 1200 0 1200 300 1 0 0 61 | { 62 | T 1250 300 5 10 0 0 270 6 1 63 | pintype=pwr 64 | T 1200 355 9 10 1 1 90 0 1 65 | pinlabel=GND 66 | T 1150 205 5 10 0 1 90 6 1 67 | pinnumber=6 68 | T 1250 300 5 10 0 0 270 6 1 69 | pinseq=6 70 | } 71 | T 492 992 5 16 1 1 0 0 1 72 | device=LATSN 73 | T 1292 2292 8 10 0 1 0 0 1 74 | description=Low-active D-Latch w/ low-active Set 75 | T 292 1989 5 10 1 1 0 0 1 76 | refdes=X? 77 | T 1892 1392 8 10 0 0 0 0 1 78 | footprint=none 79 | T -8 -8 8 10 0 1 0 0 1 80 | source=LATSN.sch 81 | T 600 100 9 10 0 0 0 0 1 82 | numslots=0 83 | -------------------------------------------------------------------------------- /Sources/geda/LATSP.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 3 | V 700 1950 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 4 | P 1800 1600 1500 1600 1 0 0 5 | { 6 | T 1500 1650 5 10 0 0 0 6 1 7 | pintype=out 8 | T 1442 1592 9 10 1 1 0 6 1 9 | pinlabel=Q 10 | T 1592 1642 5 10 0 1 0 0 1 11 | pinnumber=1 12 | T 1500 1650 5 10 0 0 0 6 1 13 | pinseq=1 14 | } 15 | P 0 1600 300 1600 1 0 0 16 | { 17 | T 100 1650 5 10 0 0 0 0 1 18 | pintype=in 19 | T 100 1650 5 10 0 0 0 0 1 20 | pinseq=2 21 | T 358 1592 9 10 1 1 0 0 1 22 | pinlabel=D 23 | T 208 1542 5 10 0 1 0 6 1 24 | pinnumber=2 25 | } 26 | P 700 2200 700 2000 1 0 0 27 | { 28 | T 650 1900 5 10 0 0 90 6 1 29 | pintype=in 30 | T 700 1845 9 10 1 1 90 6 1 31 | pinlabel=SN 32 | T 650 1995 5 10 0 1 90 0 1 33 | pinnumber=3 34 | T 650 1900 5 10 0 0 90 6 1 35 | pinseq=3 36 | } 37 | P 0 600 300 600 1 0 0 38 | { 39 | T 100 650 5 10 0 0 0 0 1 40 | pintype=clk 41 | T 100 650 5 10 0 0 0 0 1 42 | pinseq=4 43 | T 358 592 9 10 1 1 0 0 1 44 | pinlabel=X 45 | T 208 642 5 10 0 1 0 6 1 46 | pinnumber=4 47 | } 48 | P 1200 2200 1200 1900 1 0 0 49 | { 50 | T 1150 1900 5 10 0 0 90 6 1 51 | pintype=pwr 52 | T 1200 1845 9 10 1 1 90 6 1 53 | pinlabel=VDD 54 | T 1150 1995 5 10 0 1 90 0 1 55 | pinnumber=5 56 | T 1150 1900 5 10 0 0 90 6 1 57 | pinseq=5 58 | } 59 | P 1200 0 1200 300 1 0 0 60 | { 61 | T 1250 300 5 10 0 0 270 6 1 62 | pintype=pwr 63 | T 1200 355 9 10 1 1 90 0 1 64 | pinlabel=GND 65 | T 1150 205 5 10 0 1 90 6 1 66 | pinnumber=6 67 | T 1250 300 5 10 0 0 270 6 1 68 | pinseq=6 69 | } 70 | T 492 992 5 16 1 1 0 0 1 71 | device=LATSP 72 | T 1292 2292 8 10 0 1 0 0 1 73 | description=High-active D-Latch w/ low-active Set 74 | T 292 1989 5 10 1 1 0 0 1 75 | refdes=X? 76 | T 1892 1392 8 10 0 0 0 0 1 77 | footprint=none 78 | T -8 -8 8 10 0 1 0 0 1 79 | source=LATSP.sch 80 | T 600 100 9 10 0 0 0 0 1 81 | numslots=0 82 | -------------------------------------------------------------------------------- /Sources/verilog/timescale.v: -------------------------------------------------------------------------------- 1 | // ************ LibreSilicon's StdCellLibrary ******************* 2 | // 3 | // Organisation: Chipforge 4 | // Germany / European Union 5 | // 6 | // Profile: Chipforge focus on fine System-on-Chip Cores in 7 | // Verilog HDL Code which are easy understandable and 8 | // adjustable. For further information see 9 | // www.chipforge.org 10 | // there are projects from small cores up to PCBs, too. 11 | // 12 | // File: StdCellLib/Sources/verilog/timescale.v 13 | // 14 | // Purpose: Timescale statement centralized 15 | // 16 | // ************ IEEE Std 1364-2001 (Verilog HDL) *************** 17 | // 18 | // /////////////////////////////////////////////////////////////////// 19 | // 20 | // Copyright (c) 2018 by chipforge 21 | // All rights reserved. 22 | // 23 | // This Standard Cell Library is licensed under the Libre Silicon 24 | // public license; you can redistribute it and/or modify it under 25 | // the terms of the Libre Silicon public license as published by 26 | // the Libre Silicon alliance, either version 1 of the License, or 27 | // (at your option) any later version. 28 | // 29 | // This design is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | // See the Libre Silicon Public License for more details. 33 | // 34 | // /////////////////////////////////////////////////////////////////// 35 | 36 | `ifdef __TIMESCALE__ 37 | `else 38 | 39 | `define __TIMESCALE__ 40 | // synthesis translate_off 41 | `timescale 1 ns / 1 ps 42 | // synthesis translate_on 43 | 44 | `endif //__TIMESCALE__ 45 | -------------------------------------------------------------------------------- /TBench/spice/BUF2_tb.cmd: -------------------------------------------------------------------------------- 1 | 2 | .tran 100p 30n 3 | .plot tran v(Z) v(A) 4 | 5 | * rising edge propagation delay 6 | .measure tran tpdr 7 | + TRIG v(A) VAL='SUPPLY/2' RISE=1 8 | + TARG v(Z) VAL='SUPPLY/2' CROSS=1 9 | 10 | * falling edge propagation delay 11 | .measure tran tpdf 12 | + TRIG v(A) VAL='SUPPLY/2' FALL=1 13 | + TARG v(Z) VAL='SUPPLY/2' FALL=1 14 | 15 | * average propagation delay 16 | *.measure tran tpd param='(tpdr+tpdf)/2' 17 | 18 | * delta progagation delay 19 | *.measure tran delta param='tpdr-tpdf' goal=0 20 | 21 | * measure rise time 22 | .measure tran trise 23 | + TRIG v(Z) VAL='0.1*SUPPLY' RISE=1 24 | + TARG v(Z) VAL='0.9*SUPPLY' RISE=1 25 | 26 | * measure fall time 27 | .measure tran tfall 28 | + TRIG v(Z) VAL='0.9*SUPPLY' FALL=1 29 | + TARG v(Z) VAL='0.1*SUPPLY' FALL=1 30 | 31 | -------------------------------------------------------------------------------- /TBench/spice/DFFN_tb.cmd: -------------------------------------------------------------------------------- 1 | 2 | .tran 100p 70n 3 | .plot tran v(Q) v(XN) v(D) 4 | 5 | -------------------------------------------------------------------------------- /TBench/spice/DFFP_tb.cmd: -------------------------------------------------------------------------------- 1 | 2 | .tran 100p 70n 3 | .plot tran v(Q) v(X) v(D) 4 | 5 | -------------------------------------------------------------------------------- /TBench/spice/LATN_tb.cmd: -------------------------------------------------------------------------------- 1 | 2 | .tran 100p 70n 3 | * .plot tran v(Q) v(X) v(D) 4 | 5 | -------------------------------------------------------------------------------- /TBench/spice/LATP_tb.cmd: -------------------------------------------------------------------------------- 1 | 2 | .tran 100p 70n 3 | .plot tran v(Q) v(X) v(D) 4 | 5 | -------------------------------------------------------------------------------- /Tech: -------------------------------------------------------------------------------- 1 | Tech.GF180MCU/ -------------------------------------------------------------------------------- /Tech.CDTA/.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ 2 | -------------------------------------------------------------------------------- /Tech.CDTA/libresilicon.m: -------------------------------------------------------------------------------- 1 | * This is a template NMOS model that should be further improved 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | .model PMOS_VTL pmos level = 54 6 | 7 | .model nmos nmos level = 54 8 | 9 | .model pmos pmos level = 54 10 | 11 | .model nfet nmos level = 54 12 | 13 | .model pfet pmos level = 54 14 | 15 | -------------------------------------------------------------------------------- /Tech.CDTA/nmos.sp: -------------------------------------------------------------------------------- 1 | w=1.0u l=1.0u 2 | -------------------------------------------------------------------------------- /Tech.CDTA/pmos.sp: -------------------------------------------------------------------------------- 1 | w=2.7u l=1.0u 2 | -------------------------------------------------------------------------------- /Tech.GF180MCU/.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ 2 | -------------------------------------------------------------------------------- /Tech.GF180MCU/Makefile: -------------------------------------------------------------------------------- 1 | libresilicon.tech: /usr/local/share/pdk/gf180mcuD/libs.tech/magic/gf180mcuD.tech 2 | perl ../Tools/perl/drcexpander.pl /usr/local/share/pdk/gf180mcuD/libs.tech/magic/gf180mcuD.tech >libresilicon.tech 3 | 4 | 5 | -------------------------------------------------------------------------------- /Tech.GF180MCU/caravel-env.sh: -------------------------------------------------------------------------------- 1 | export STDCELLLIB="../" 2 | #e#xport OPENLANE_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1/dependencies/openlane_src" 3 | #e#xport CARAVEL="/home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1" 4 | #e#xport CARAVEL_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1/caravel" 5 | export PDK_ROOT=/home/philipp/.volare 6 | export PDK="gf180mcuD" 7 | export STD_CELL_LIBRARY="gf180mcu_fd_sc_mcu9t5v0" 8 | export STD_CELL_LIBRARY_OPT="gf180mcu_fd_sc_mcu9t5v0" 9 | export CARAVEL_BRANCH="gfmpw-1c" 10 | export KLAYOUT_HOME=/home/philipp/.volare/gf180mcuD/libs.tech/klayout 11 | -------------------------------------------------------------------------------- /Tech.GF180MCU/libresilicon.m: -------------------------------------------------------------------------------- 1 | * This is a template NMOS model that should be further improved 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | .model PMOS_VTL pmos level = 54 6 | 7 | .model nmos nmos level = 54 8 | 9 | .model pmos pmos level = 54 10 | 11 | .model nfet nmos level = 54 12 | 13 | .model pfet pmos level = 54 14 | 15 | -------------------------------------------------------------------------------- /Tech.GF180MCU/nmos.sp: -------------------------------------------------------------------------------- 1 | w=1.83u l=0.5u 2 | -------------------------------------------------------------------------------- /Tech.GF180MCU/pmos.sp: -------------------------------------------------------------------------------- 1 | w=1.32u l=0.6u 2 | -------------------------------------------------------------------------------- /Tech.GF180MCU/tracks.txt: -------------------------------------------------------------------------------- 1 | 1 Track: 0.56 um 2 | 3 | Tracks per Cell 7 4 | Cell Height (um) 3.92 5 | 6 | Tracks per Cell 9 7 | Cell Height (um) 5.04 8 | 9 | Tracks per Cell 11 10 | Cell Height (um) 6.16 11 | 12 | Tracks per Cell 13 13 | Cell Height (um) 7.28 14 | 15 | -------------------------------------------------------------------------------- /Tech.LS1UM/.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ 2 | -------------------------------------------------------------------------------- /Tech.LS1UM/SpiceParameterFiles.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/thesourcerer8/StdCellLib/76d19180b1b7de90035ed1d3de1ae25aeea5ef3b/Tech.LS1UM/SpiceParameterFiles.zip -------------------------------------------------------------------------------- /Tech.LS1UM/bad/libresilicon.m10: -------------------------------------------------------------------------------- 1 | .MODEL NMOS_VTL NMOS LEVEL = 39 2 | + TOX = 2.000000E-02 TEMP = 2.500000E+01 3 | + VDD = 5.000000E+00 VGG = 5.000000E+00 VBB =-5.000000E+00 4 | + DL = 0.000000E+00 DW = 0.000000E+00 5 | + VGHIGH = 1.270000E-01 LVGHIGH= 0.000000E+00 WVGHIGH= 0.000000E+00 6 | + VGLOW =-7.820000E-02 LVGLOW = 0.000000E+00 WVGLOW= 0.000000E+00 7 | 8 | -------------------------------------------------------------------------------- /Tech.LS1UM/bad/libresilicon.m2: -------------------------------------------------------------------------------- 1 | .SUBCKT NMOS4 D G S B 2 | + PARAMS: 3 | + W=15E-7 4 | + L=10E-7 5 | + PD=25E-7 6 | + PS=25E-7 7 | 8 | M1 D G S B NMOS W={W} L={L} PD={PD} PS={PS} 9 | 10 | .MODEL NMOS NMOS ( 11 | + LEVEL = 8 12 | + VERSION = 3.3.1 13 | + TNOM = 27 14 | + U0 = 1160.761537104032 15 | + TOX = 40E-9 16 | + XT = 2E-6 17 | + XJ = 100E-9 18 | + NCH = 1.7E17 19 | + NSUB = 1.7E17 20 | + VTH0 = -0.7 21 | + W0 = 1.280703E-8 22 | + NLX = 0 23 | + Lmin = 5E-7 24 | + Lmax = 15E-7 25 | + Wmin = 10E-7 26 | + Wmax = 20E-7 27 | + ) 28 | 29 | * NGATE has to be measured! 30 | 31 | .ENDS NMOS4 32 | .SUBCKT PMOS4 D G S B 33 | + PARAMS: 34 | + W=30E-7 35 | + L=10E-7 36 | + PD=30E-7 37 | + PS=30E-7 38 | 39 | M1 D G S B PMOS W={W} L={L} PD={PD} PS={PS} 40 | 41 | .MODEL PMOS PMOS ( 42 | + LEVEL = 8 43 | + VERSION = 3.3.1 44 | + TNOM = 27 45 | + U0 = 439.9319659030368 46 | + TOX = 40E-9 47 | + XT = 2E-6 48 | + XJ = 100E-9 49 | + NCH = 1.7E17 50 | + NSUB = 1.7E17 51 | + VTH0 = -0.7 52 | + W0 = 1.280703E-8 53 | + NLX = 0 54 | + Lmin = 5E-7 55 | + Lmax = 15E-7 56 | + Wmin = 25E-7 57 | + Wmax = 35E-7 58 | + ) 59 | 60 | * PGATE has to be measured! 61 | 62 | .ENDS PMOS4 63 | -------------------------------------------------------------------------------- /Tech.LS1UM/bad/libresilicon.m3: -------------------------------------------------------------------------------- 1 | .MODEL NMOS NMOS ( 2 | + LEVEL = 8 3 | + VERSION = 3.3.1 4 | + TNOM = 27 5 | + U0 = 1160.761537104032 6 | + TOX = 40E-9 7 | + XT = 2E-6 8 | + XJ = 100E-9 9 | + NCH = 1.7E17 10 | + NSUB = 1.7E17 11 | + VTH0 = -0.7 12 | + W0 = 1.280703E-8 13 | + NLX = 0 14 | + Lmin = 5E-7 15 | + Lmax = 15E-7 16 | + Wmin = 10E-7 17 | + Wmax = 20E-7 18 | + ) 19 | 20 | .MODEL PMOS PMOS ( 21 | + LEVEL = 8 22 | + VERSION = 3.3.1 23 | + TNOM = 27 24 | + U0 = 439.9319659030368 25 | + TOX = 40E-9 26 | + XT = 2E-6 27 | + XJ = 100E-9 28 | + NCH = 1.7E17 29 | + NSUB = 1.7E17 30 | + VTH0 = -0.7 31 | + W0 = 1.280703E-8 32 | + NLX = 0 33 | + Lmin = 5E-7 34 | + Lmax = 15E-7 35 | + Wmin = 25E-7 36 | + Wmax = 35E-7 37 | + ) 38 | 39 | 40 | -------------------------------------------------------------------------------- /Tech.LS1UM/bad/libresilicon.m5: -------------------------------------------------------------------------------- 1 | .MODEL NMOS_VTL NMOS ( 2 | + LEVEL = 8 3 | + VERSION = 3.3.1 4 | + TNOM = 27 5 | + U0 = 1160.761537104032 6 | + TOX = 40E-9 7 | + XT = 2E-6 8 | + XJ = 100E-9 9 | + NCH = 1.7E17 10 | + NSUB = 1.7E17 11 | + VTH0 = -0.7 12 | + W0 = 1.280703E-8 13 | + NLX = 0 14 | + Lmin = 5E-7 15 | + Lmax = 15E-7 16 | + Wmin = 10E-7 17 | + Wmax = 20E-7 18 | + ) 19 | 20 | .MODEL PMOS_VTL PMOS ( 21 | + LEVEL = 8 22 | + VERSION = 3.3.1 23 | + TNOM = 27 24 | + U0 = 439.9319659030368 25 | + TOX = 40E-9 26 | + XT = 2E-6 27 | + XJ = 100E-9 28 | + NCH = 1.7E17 29 | + NSUB = 1.7E17 30 | + VTH0 = -0.7 31 | + W0 = 1.280703E-8 32 | + NLX = 0 33 | + Lmin = 5E-7 34 | + Lmax = 15E-7 35 | + Wmin = 25E-7 36 | + Wmax = 35E-7 37 | + ) 38 | 39 | 40 | -------------------------------------------------------------------------------- /Tech.LS1UM/bad/libresilicon.m7: -------------------------------------------------------------------------------- 1 | .MODEL NMOS_VTL NMOS LEVEL=27 SOSLEV=2 2 | +VTO=0.814 TOX=0.34E-7 THETA=0.55E-1 3 | +FB=0.15 EC=0.3E7 A=0.1E-6 4 | +UO=370 CGSO=0.46E-9 CGDO=0.46E-9 5 | +RSH=25 LD=0.3E-6 6 | * 7 | 8 | .MODEL PMOS_VTL PMOS LEVEL=27 SOSLEV=2 9 | +VTO=-0.7212 TOX=0.34E-7 THETA=0.75E-1 10 | +FB=0.0 EC=0.75E7 A=0.1E-6 11 | +UO=215 CGSO=0.36E-9 CGDO=0.36E-9 12 | +RSH=80 LD=0.2E-6i 13 | * 14 | -------------------------------------------------------------------------------- /Tech.LS1UM/good/libresilicon.m: -------------------------------------------------------------------------------- 1 | * This is a template NMOS model that should be further improved 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | .model PMOS_VTL pmos level = 54 6 | 7 | -------------------------------------------------------------------------------- /Tech.LS1UM/good/libresilicon.m9: -------------------------------------------------------------------------------- 1 | * Long channel models from CMOS Circuit Design, Layout, and Simulation, 2 | * Level=3 models VDD=5V, see CMOSedu.com 3 | * 4 | .MODEL NMOS_VTL NMOS LEVEL = 3 5 | + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 6 | + PHI = 0.7 VTO = 0.8 DELTA = 3.0 7 | + UO = 650 ETA = 3.0E-6 THETA = 0.1 8 | + KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 9 | + RSH = 0 NFS = 1E12 TPG = 1 10 | + XJ = 500E-9 LD = 100E-9 11 | + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 12 | + CJ = 400E-6 PB = 1 MJ = 0.5 13 | + CJSW = 300E-12 MJSW = 0.5 14 | * 15 | .MODEL PMOS_VTL PMOS LEVEL = 3 16 | + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 17 | + PHI = 0.7 VTO = -0.9 DELTA = 0.1 18 | + UO = 250 ETA = 0 THETA = 0.1 19 | + KP = 40E-6 VMAX = 5E4 KAPPA = 1 20 | + RSH = 0 NFS = 1E12 TPG = -1 21 | + XJ = 500E-9 LD = 100E-9 22 | + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 23 | + CJ = 400E-6 PB = 1 MJ = 0.5 24 | + CJSW = 300E-12 MJSW = 0.5 25 | -------------------------------------------------------------------------------- /Tech.LS1UM/libresilicon.m: -------------------------------------------------------------------------------- 1 | * This is a template NMOS model that should be further improved 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | .model PMOS_VTL pmos level = 54 6 | 7 | .model nmos nmos level = 54 8 | 9 | .model pmos pmos level = 54 10 | 11 | .model nfet nmos level = 54 12 | 13 | .model pfet pmos level = 54 14 | 15 | -------------------------------------------------------------------------------- /Tech.LS1UM/libresilicon.m9: -------------------------------------------------------------------------------- 1 | * Long channel models from CMOS Circuit Design, Layout, and Simulation, 2 | * Level=3 models VDD=5V, see CMOSedu.com 3 | * 4 | .MODEL NMOS_VTL NMOS LEVEL = 3 5 | + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 6 | + PHI = 0.7 VTO = 0.8 DELTA = 3.0 7 | + UO = 650 ETA = 3.0E-6 THETA = 0.1 8 | + KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 9 | + RSH = 0 NFS = 1E12 TPG = 1 10 | + XJ = 500E-9 LD = 100E-9 11 | + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 12 | + CJ = 400E-6 PB = 1 MJ = 0.5 13 | + CJSW = 300E-12 MJSW = 0.5 14 | * 15 | .MODEL PMOS_VTL PMOS LEVEL = 3 16 | + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 17 | + PHI = 0.7 VTO = -0.9 DELTA = 0.1 18 | + UO = 250 ETA = 0 THETA = 0.1 19 | + KP = 40E-6 VMAX = 5E4 KAPPA = 1 20 | + RSH = 0 NFS = 1E12 TPG = -1 21 | + XJ = 500E-9 LD = 100E-9 22 | + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 23 | + CJ = 400E-6 PB = 1 MJ = 0.5 24 | + CJSW = 300E-12 MJSW = 0.5 25 | -------------------------------------------------------------------------------- /Tech.LS1UM/nmos.sp: -------------------------------------------------------------------------------- 1 | w=1.0u l=1.0u 2 | -------------------------------------------------------------------------------- /Tech.LS1UM/pmos.sp: -------------------------------------------------------------------------------- 1 | w=2.7u l=1.0u 2 | -------------------------------------------------------------------------------- /Tech.SKY130/.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ 2 | -------------------------------------------------------------------------------- /Tech.SKY130/caravel-env.sh: -------------------------------------------------------------------------------- 1 | export STDCELLLIB="../" 2 | #e#xport OPENLANE_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/sky130_stdcelllib_1/dependencies/openlane_src" 3 | #e#xport CARAVEL="/home/philipp/libresilicon/StdCellLib/Catalog/sky130_stdcelllib_1" 4 | #e#xport CARAVEL_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/sky130_stdcelllib_1/caravel" 5 | export PDK_ROOT=/home/philipp/.volare 6 | export PDK="sky130A" 7 | export STD_CELL_LIBRARY="sky130_fd_sc_lp" 8 | export STD_CELL_LIBRARY_OPT="sky130_fd_sc_lp" 9 | export CARAVEL_BRANCH="skympw-8d" 10 | export KLAYOUT_HOME=/home/philipp/.volare/sky130A/libs.tech/klayout 11 | -------------------------------------------------------------------------------- /Tech.SKY130/libresilicon.m: -------------------------------------------------------------------------------- 1 | * This is a template NMOS model that should be further improved 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | .model PMOS_VTL pmos level = 54 6 | 7 | .model nmos nmos level = 54 8 | 9 | .model pmos pmos level = 54 10 | 11 | .model nfet nmos level = 54 12 | 13 | .model pfet pmos level = 54 14 | 15 | -------------------------------------------------------------------------------- /Tech.SKY130/nmos.sp: -------------------------------------------------------------------------------- 1 | w=0.420u l=0.150u 2 | -------------------------------------------------------------------------------- /Tech.SKY130/pmos.sp: -------------------------------------------------------------------------------- 1 | w=0.840u l=0.150u 2 | -------------------------------------------------------------------------------- /Technology/spice/ls1unmos.mod: -------------------------------------------------------------------------------- 1 | * 2 | * Long channel models from CMOS Circuit Design, Layout, and Simulation, 3 | * Level=3 models VDD=5V, see CMOSedu.com 4 | * 5 | .MODEL NMOS4 NMOS LEVEL = 3 6 | + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 7 | + PHI = 0.7 VTO = 0.8 DELTA = 3.0 8 | + UO = 650 ETA = 3.0E-6 THETA = 0.1 9 | + KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 10 | + RSH = 0 NFS = 1E12 TPG = 1 11 | + XJ = 500E-9 LD = 100E-9 12 | + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 13 | + CJ = 400E-6 PB = 1 MJ = 0.5 14 | + CJSW = 300E-12 MJSW = 0.5 15 | 16 | -------------------------------------------------------------------------------- /Technology/spice/ls1upmos.mod: -------------------------------------------------------------------------------- 1 | * 2 | * Long channel models from CMOS Circuit Design, Layout, and Simulation, 3 | * Level=3 models VDD=5V, see CMOSedu.com 4 | * 5 | .MODEL PMOS4 PMOS LEVEL = 3 6 | + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 7 | + PHI = 0.7 VTO = -0.9 DELTA = 0.1 8 | + UO = 250 ETA = 0 THETA = 0.1 9 | + KP = 40E-6 VMAX = 5E4 KAPPA = 1 10 | + RSH = 0 NFS = 1E12 TPG = -1 11 | + XJ = 500E-9 LD = 100E-9 12 | + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 13 | + CJ = 400E-6 PB = 1 MJ = 0.5 14 | + CJSW = 300E-12 MJSW = 0.5 15 | -------------------------------------------------------------------------------- /Tools/caravel/feedback2mag.pl: -------------------------------------------------------------------------------- 1 | print STDERR "Convert feedback to a .mag file\n"; 2 | my $example=<>\n"; 21 | while() 22 | { 23 | if(m/box (-?\d+) (-?\d+) (-?\d+) (-?\d+)/) 24 | { 25 | print "rect ".int($1/1)." ".int($2/1)." ".int($3/1)." ".int($4/1)."\n"; 26 | } 27 | if(m/(\d+\.?\d*)um (\d+\.?\d*)um (\d+\.\d*)um (\d+\.?\d*)um/) 28 | { 29 | print "rect ".int($1*200)." ".int($2*200)." ".int($3*200)." ".int($4*200)."\n"; 30 | } 31 | } 32 | print "<< end >>\n"; 33 | -------------------------------------------------------------------------------- /Tools/caravel/fixup_sp.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | 4 | print STDERR "Fixing up .SP files for a Caravel\n"; 5 | 6 | sub readfile($) 7 | { 8 | if(open MYRIN,"<$_[0]") 9 | { 10 | my $old=$/; 11 | undef $/; 12 | my $content=; 13 | close MYRIN; 14 | $/=$old; 15 | return $content; 16 | } 17 | return undef; 18 | } 19 | 20 | foreach my $sp (<*.sp>) 21 | { 22 | my $content=readfile($sp); 23 | $content=~s/\bvdd\b/VPWR/g; 24 | $content=~s/\bgnd\b/VGND/g; 25 | open OUT,">$sp"; 26 | print OUT $content; 27 | close OUT; 28 | } 29 | -------------------------------------------------------------------------------- /Tools/caravel/gitpush.sh: -------------------------------------------------------------------------------- 1 | git add cells/ def/user_proj_example.def lef/user_proj_example.lef openlane/user_proj_example/config.tcl openlane/user_proj_example/macro_placement.cfg signoff/user_proj_example/final_summary_report.csv verilog/rtl/user_proj_cells.v verilog/rtl/user_proj_example.v 2 | git add gds/user_proj_example.gds.gz 3 | git add gds/user_project_wrapper.gds.gz 4 | git add mag/user_project_wrapper.mag 5 | git add maglef/user_proj_example.mag spi/lvs/user_proj_example.spice verilog/gl/user_proj_example.v verilog/dv 6 | -------------------------------------------------------------------------------- /Tools/caravel/placement.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | print STDERR "Generates macro placement file for all cells - not needed\n"; 4 | 5 | my $width=0.48; 6 | my $height=3.33; 7 | 8 | 9 | my $row=8; 10 | 11 | my $xpos=($row%2)? $width*80 : 44.640+0.480; 12 | 13 | our $nextla=$height*$row; 14 | 15 | 16 | 17 | my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib"; 18 | 19 | foreach my $mag(sort ) 20 | { 21 | next if((-s $mag)<=50); 22 | #print `ls -la $mag`; 23 | my $cell=$mag; $cell=~s/\.mag$/.cell/; $cell=~s/\/mag\//\/cell\//; 24 | next unless(-f $cell); 25 | my $lib=$mag; $lib=~s/\.mag$/.lib/; $lib=~s/\/mag\//\/lib\//; 26 | #next unless(-f $lib); 27 | my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/); 28 | next unless(-f $ENV{'CARAVEL'}."/cells/mag/$name.mag"); 29 | 30 | print "$name $xpos $nextla N\n"; 31 | $nextla+=$height*2; 32 | } 33 | -------------------------------------------------------------------------------- /Tools/caravel/removeDRCcells.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | print STDERR "Remove cells that have DRC errors from the Caravel so that we only have good cells on the Caravel\n"; 4 | 5 | foreach my $mag (<*.mag>) 6 | { 7 | my $cell=$mag; $cell=~s/\.mag$//; 8 | #print "Checking $cell\n"; 9 | my $STDCELLLIB=$ENV{'STDCELLLIB'}; 10 | my $drc=0; 11 | if(open(IN,"<$STDCELLLIB/Catalog/$cell.drc")) 12 | { 13 | while() 14 | { 15 | $drc=$1 if(m/Number of DRC errors: (\d+)/); 16 | } 17 | close IN; 18 | } 19 | else 20 | { 21 | print "Warning: Could not find DRC: $STDCELLLIB/$cell.drc $!\n"; 22 | $drc=1; 23 | } 24 | $drc=1 if(!-f "$STDCELLLIB/Catalog/$cell.mag"); 25 | if($drc) 26 | { 27 | print "Removing cell with $drc DRC issues: $cell\n"; 28 | unlink $mag; 29 | unlink "../lef/orig/$cell.lef"; 30 | unlink "../lef/$cell.lef"; 31 | unlink "../gds/$cell.gds"; 32 | unlink "../lib/$cell.lib"; 33 | unlink "../cell/$cell.cell"; 34 | unlink "../sp/$cell.sp"; 35 | } 36 | 37 | } 38 | 39 | -------------------------------------------------------------------------------- /Tools/caravel/removenl.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | print STDERR "Fixups for the LIBERTY files\n"; 4 | 5 | open IN,"; 8 | $content=~s/area/pg_pin (VPWR) { voltage_name : "VPWR"; pg_type : "primary_power"; } pg_pin (VGND) { voltage_name : "VGND"; pg_type : "primary_ground"; } area/g; 9 | 10 | #$content=~s/"\s*\n/"/gs; 11 | #$content=~s/;\s*\n/;/gs; 12 | #$content=~s/\n//gs; # Why did we remove the newlines? - it now works without removing them 13 | $content=~s/\\//gs; 14 | 15 | 16 | 17 | print $content; 18 | -------------------------------------------------------------------------------- /Tools/caravel/scale10.py: -------------------------------------------------------------------------------- 1 | import glob 2 | import gdsfactory as gf 3 | 4 | # Rescale GDS files 5 | 6 | for a in glob.glob("*.gds"): 7 | print(a) 8 | b=gf.read.import_gds(a,read_metadata=True) 9 | b.write_gds(a,unit=1e-07) 10 | 11 | -------------------------------------------------------------------------------- /Tools/caravel/testgen.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | 4 | print STDERR "Generating testbench firmware file for Caravel to test all the functions (this is a ATPG)\n"; 5 | 6 | open IN,"<$ARGV[0]"; 7 | 8 | print <; 15 | my @l=split "->",$header; 16 | my @ins=sort split " ",$l[0]; 17 | my @outs=sort split " ",$l[1]; 18 | my %map=(); 19 | 20 | my $reg=0; 21 | my @io=(); 22 | print " printf(\"Initializing the Inputs of the cell:\\n\");\n"; 23 | foreach(@ins) 24 | { 25 | print " reg_mprj_io_$reg = GPIO_MODE_MGMT_STD_INPUT; // $_\n"; 26 | $io[$reg>>5]|=1<<($reg&31); 27 | $reg++; 28 | } 29 | print " printf(\"Initializing the Outputs of the cell:\\n\");\n"; 30 | foreach(@outs) 31 | { 32 | $map{$_}=$reg++; 33 | 34 | print " reg_mprj_io_$reg = GPIO_MODE_USER_STD_OUTPUT; // $_\n"; 35 | } 36 | 37 | print " reg_mprj_xfer=1;\n"; 38 | print " while (reg_mprj_xfer == 1);\n"; 39 | 40 | foreach(0 .. 3) 41 | { 42 | print "reg_la".$_."_ena=".sprintf("0x%08X",$io[$_]).";\n" if(defined($io[$_])); 43 | } 44 | 45 | my $counter=0; 46 | print " printf(\"Starting the tests:\\n\");\n"; 47 | 48 | while() 49 | { 50 | last if(m/^function:/); 51 | @l=split " ",$_; 52 | my $if=0; 53 | foreach(@l) 54 | { 55 | if(m/(\w+)=(\d)/) 56 | { 57 | print " assert(reg_la".$map{$1}."_data==$2); //$1\n"; 58 | } 59 | else 60 | { 61 | print " reg_la".$if."_data=$_; //$ins[$if]\n"; 62 | } 63 | $if++; 64 | } 65 | print " printf(\"Test $counter successful\\n\");\n\n"; 66 | 67 | $counter++; 68 | } 69 | -------------------------------------------------------------------------------- /Tools/caravel/viewer.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib"; 4 | my $CARAVEL=$ENV{'CARAVEL'} || "/media/philipp/Daten/skywater/caravel-stdcelllib-stdcells"; 5 | my $magictech=$ARGV[0] || "sky130A"; 6 | 7 | 8 | open OUT,"|magic -noconsole -T $magictech"; 9 | foreach(<$CARAVEL/cells/lef/*.lef>) 10 | { 11 | print OUT "lef read $_\n"; 12 | } 13 | print OUT "def read ".$ARGV[0]."\n"; 14 | #print OUT "select top\n"; 15 | close OUT; 16 | -------------------------------------------------------------------------------- /Tools/perl/annotate.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | foreach() 4 | { 5 | next if(-f "$_.ann"); 6 | system "klayout -l librecell.lyp $_"; 7 | print "Is it good?\n"; 8 | my $val=; 9 | print "So you think $val?\n"; 10 | if($val=~m/[eq]/i) 11 | { 12 | exit; 13 | } 14 | if($val=~m/[yn]/) 15 | { 16 | open OUT,">$_.ann"; 17 | print OUT $val; 18 | close OUT; 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /Tools/perl/bisect.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | 4 | my $cellname=$ARGV[0] || "INV"; 5 | my $placer=""; 6 | my $deb=0; 7 | 8 | open IN,"<../Tech/librecell_tech.py.bad"; 9 | my @bad=; 10 | close IN; 11 | 12 | open IN,"<../Tech/librecell_tech.py.good"; 13 | my @good=; 14 | close IN; 15 | 16 | my $ndiffs=0; 17 | 18 | foreach(0 .. scalar(@bad)-1) 19 | { 20 | $ndiffs++ if($bad[$_] ne $good[$_]); 21 | } 22 | 23 | print "Different lines between librecell_tech.py.good and librecell_tech.py.bad: $ndiffs\n"; 24 | 25 | my $prev=undef; 26 | 27 | my %badlist=(); 28 | 29 | foreach my $variant (0 .. $ndiffs+1) 30 | { 31 | open OUT,">../Tech/librecell_tech.$variant.py"; 32 | my $counter=0; 33 | foreach(0 .. scalar(@bad)-1) 34 | { 35 | if($bad[$_] ne $good[$_]) 36 | { 37 | $counter++; 38 | print OUT defined($badlist{$counter})?$good[$_]:($counter>$variant)?$good[$_]:$bad[$_]; 39 | } 40 | else 41 | { 42 | print OUT $good[$_]; 43 | } 44 | 45 | } 46 | close OUT; 47 | my $ret=system "lclayout --output-dir debuglib --tech ../Tech/librecell_tech.$variant.py --netlist $cellname.sp --cell $cellname -v $placer --placement-file $cellname.place --ignore-lvs ".($deb?"--debug-routing-graph ":"")." >>$cellname.$variant.log 2>>$cellname.$variant.err "; 48 | print "Variant: $variant Return: $ret\n"; 49 | 50 | if($ret != 0) # indicates an error 51 | { 52 | print "Bad Line found: \n"; 53 | system "diff ../Tech/librecell_tech.$variant.py ../Tech/librecell_tech.".($variant-1).".py"; 54 | $badlist{$variant}=1; 55 | } 56 | 57 | } 58 | 59 | print "Activating the best option:\n"; 60 | system "cp -f ../Tech/librecell_tech.".($ndiffs+1).".py ../Tech/librecell_tech.py"; 61 | 62 | -------------------------------------------------------------------------------- /Tools/perl/disp2svg.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | 4 | my $data=<' 12 | 16 | 17 | EOF 18 | ; 19 | # 20 | while($a=) #foreach my $a(split "\n",$data) 21 | { 22 | if($a=~m/routing_nodes: \{(.*?)\}/) 23 | { 24 | foreach my $c (split('\), \(',$1)) 25 | { 26 | if($c=~m/(\d+), (\d+)/) 27 | { 28 | print "\n"; 29 | } 30 | } 31 | } 32 | if($a=~m/terminal_region: \((.*?)\)/) 33 | { 34 | my $d=$1; $d=~s/,/;/g; 35 | my @l=split(';',$d); 36 | print ""; 37 | } 38 | } 39 | 40 | print ""; 41 | -------------------------------------------------------------------------------- /Tools/perl/dorest.pl: -------------------------------------------------------------------------------- 1 | foreach (<*.cell>) 2 | { 3 | my $cellname=$_; 4 | $cellname=~s/\.cell$//; 5 | next if(-f "$cellname.mag"); 6 | print "We should do $_\n"; 7 | system "touch $_"; 8 | $ENV{'CELL'}=$cellname; 9 | system "make layout"; 10 | } 11 | -------------------------------------------------------------------------------- /Tools/perl/drccheck.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | my $mag=$ARGV[0] || ""; $mag=~s/\.mag$//i; 4 | 5 | my $tech=$ARGV[1] || "../Tech/libresilicon.tech"; 6 | 7 | print "drccheck.pl - Check DRC rules with magic\n"; 8 | print "Usage: drccheck.pl input.mag\n" if(scalar(@ARGV)<1); 9 | 10 | my $style="drc(fast)"; # "drc(full)"; 11 | 12 | if(-f "$mag.mag") 13 | { 14 | open OUT,"|magic -dnull -noconsole -T $tech $mag.mag"; 15 | my $outfile="$mag.drc"; 16 | 17 | print OUT <) 11 | { 12 | next if($magfile=~m/^corr_/); # Ignore correction files 13 | next if($magfile eq "demoboard.mag"); 14 | my $cellname=$magfile; $cellname=~s/\.mag$//; 15 | 16 | step("NEXT STEP: DRC Check with Magic"); 17 | system "../Tools/perl/drccheck.pl $cellname.mag $tech"; 18 | 19 | step("NEXT STEP: DRC Fix"); 20 | system "../Tools/perl/drcfix.pl $cellname.drc $tech"; 21 | 22 | step("NEXT STEP: DRC Check with Magic"); 23 | system "../Tools/perl/drccheck.pl $cellname.mag $tech"; 24 | 25 | if(-f "corr_$cellname.mag") 26 | { 27 | unlink "$cellname.mag"; 28 | rename "corr_$cellname.mag","$cellname.mag"; 29 | print "DRC errors in $cellname corrected. Now running final DRC check:\n"; 30 | step("NEXT STEP: Final DRC check"); 31 | system "../Tools/perl/drccheck.pl $cellname.mag $tech"; 32 | } 33 | 34 | # exit; 35 | } 36 | 37 | -------------------------------------------------------------------------------- /Tools/perl/essential.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | my @cells=qw(AAAOI222.cell AAAOI333.cell AAOI22.cell AOAI221.cell AOI21.cell ASYNC1.cell ASYNC2.cell ASYNC3.cell INV.cell MARTIN1989.cell MUX2.cell MUX3.cell MUX4.cell MUX8.cell NAND2.cell NAND3.cell NAND4.cell NOR2.cell NOR3.cell NOR4.cell OAAAOI2132.cell OAAOI224.cell OAI41.cell OOOOAI3332.cell OR4.cell sutherland1989.cell vanberkel1991.cell); 4 | 5 | foreach my $cell(@cells) 6 | { 7 | my $CELL=$cell; $CELL=~s/\.cell$//; 8 | $ENV{'CELL'}=$CELL; 9 | if(!-f $cell) 10 | { 11 | print "Cell $CELL existiert nicht!\n"; 12 | next; 13 | } 14 | system "touch $cell" if(-f $cell); 15 | system "make layout"; 16 | } 17 | -------------------------------------------------------------------------------- /Tools/perl/flatten.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | my $mag=$ARGV[0]; $mag=~s/\.mag$//i; 4 | my $sp=$mag; $sp.=".flat.mag"; 5 | my $flat=$ARGV[1] || $sp; 6 | my $tech=$ARGV[2] || "../Tech/libresilicon.tech"; 7 | 8 | print "flatten.pl - Flatten a hierarchical .mag file into a flattened .mag file\n"; 9 | print "Usage: flatten.pl input.mag output.mag [Technology]\n"; 10 | 11 | if(-f "$mag.mag") 12 | { 13 | open MAGIC,"|magic -dnull -noconsole -T $tech $mag"; 14 | unlink $flat; 15 | $flat=~s/\.mag$//i; # We need to remove the extension otherwise load will not work 16 | print MAGIC "select top cell\nexpand\nflatten $flat\nload $flat\nsave\n"; 17 | print MAGIC "exit\n"; 18 | close MAGIC; 19 | } 20 | else 21 | { 22 | print STDERR "Error: Could not load magic file $mag.mag\n"; 23 | } 24 | -------------------------------------------------------------------------------- /Tools/perl/funclist.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | print "Writing functions.html\n"; 4 | open OUT,">functions.html"; 5 | print OUT < 7 | Cell Functions 8 | 9 | 10 |

Cell functions:

11 | 12 | 13 | EOF 14 | ; 15 | 16 | foreach(<*.cell>) 17 | { 18 | my $func1=`../Tools/perl/truthtable.pl --format=text $_`; 19 | my $func2=""; $func2=$1 if($func1=~m/FUNCTION: (.*)/); $func2=~s/FUNCTION://; 20 | print OUT ""; 21 | } 22 | 23 | print OUT "
CellFunction
$_$func2
\n"; 24 | close OUT; 25 | 26 | print "You can now execute:\nfirefox functions.html\n"; 27 | -------------------------------------------------------------------------------- /Tools/perl/lefgen.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | 4 | # This tool compiles a single LEF from a template for the header and the LEF snippets for each cell 5 | 6 | open IN,"<../Tech/template.lef"; 7 | print $_ while(); 8 | close IN; 9 | 10 | foreach(@ARGV) 11 | { 12 | if(open IN,"<$_") 13 | { 14 | while() 15 | { 16 | print $_; 17 | } 18 | close IN; 19 | } 20 | else 21 | { 22 | print STDERR "Error: Could not open file $_ for reading: $!\n"; 23 | } 24 | print "\n"; 25 | } 26 | 27 | 28 | print "\nEND LIBRARY\n"; 29 | -------------------------------------------------------------------------------- /Tools/perl/lefsize.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | 4 | 5 | 6 | sub mymin($$) 7 | { 8 | return $_[1] unless(defined($_[0])); 9 | return ($_[0]>$_[1])?$_[1]:$_[0]; 10 | } 11 | 12 | sub mymax($$) 13 | { 14 | return $_[1] unless(defined($_[0])); 15 | return ($_[0]>$_[1])?$_[0]:$_[1]; 16 | } 17 | 18 | foreach my $mag(<*.mag>) 19 | { 20 | my $cellname=$mag; $cellname=~s/\.mag$//; 21 | next if(defined($ENV{'CELL'}) && $ENV{'CELL'} ne $cellname); 22 | next unless(-f "$cellname.cell"); # We only want generated cells, no demoboards or other stuff 23 | 24 | my @mins=(); 25 | my @maxs=(); 26 | 27 | if(open(IN,"<$mag")) 28 | { 29 | while() 30 | { 31 | if(m/^rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/) 32 | { 33 | my @a=split " ",$_; 34 | foreach(1 .. 4) 35 | { 36 | $mins[$_&1]=mymin($mins[$_&1],$a[$_]); 37 | $maxs[$_&1]=mymax($maxs[$_&1],$a[$_]); 38 | } 39 | } 40 | } 41 | close IN; 42 | } 43 | my @inputs=(); 44 | my @outputs=(); 45 | if(open(IN,"<$cellname.cell")) 46 | { 47 | #print STDERR "Reading $cellname.cell\n"; 48 | while() 49 | { 50 | @inputs=split " ",$1 if(m/^\.inputs (.*)/); 51 | @outputs=split " ",$1 if(m/^\.outputs (.*)/); 52 | } 53 | close IN; 54 | } 55 | else 56 | { 57 | print STDERR "Could not read cell $cellname.cell: $!\n"; 58 | } 59 | my $area=defined($maxs[0])?"SIZE ".($maxs[0]-$mins[0])." BY ".($maxs[1]-$mins[1])." ;":""; 60 | 61 | print "$cellname\n$area\n"; 62 | } 63 | 64 | -------------------------------------------------------------------------------- /Tools/perl/ltspice2lclayout.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | use strict; 3 | 4 | if(scalar(@ARGV) != 2) 5 | { 6 | print "Usage: $0 \n"; 7 | print "All VDD, GND and all inputs/output nets to the cell must be labled in LTspice.\n"; 8 | exit; 9 | } 10 | 11 | my $circuitname=uc $ARGV[1]; $circuitname=~s/\.\w+$//; $circuitname=~s/.*\///; 12 | if(open(IN,"<$ARGV[0]")) 13 | { 14 | if(open(OUT,">$ARGV[1]")) 15 | { 16 | my $head=; $head=~s/\r//g; 17 | print OUT "* converted by $0 : $head"; 18 | my %ports=(); 19 | my $circ=""; 20 | while() 21 | { 22 | s/\r//g; 23 | s/ 0 / GND /g; 24 | s/ 0 / GND /g; # This needs to be done 2 times since they are overlapping! 25 | my @a=split(" ",$_); 26 | $circ.=$_ if(m/^[MR]/); 27 | $ports{$a[1]}=1 if(m/^[MR]/ && $a[1]!~m/^(N\d\d\d|\d+)$/); 28 | $ports{$a[2]}=1 if(m/^[MR]/ && $a[2]!~m/^(N\d\d\d|\d+)$/); 29 | $ports{$a[3]}=1 if(m/^[M]/ && $a[3]!~m/^(N\d\d\d|\d+)$/); 30 | $ports{$a[4]}=1 if(m/^[M]/ && $a[4]!~m/^(N\d\d\d|\d+)$/); 31 | } 32 | print OUT "\n.subckt $circuitname ".join(" ",sort keys %ports)."\n"; 33 | print OUT $circ; 34 | print OUT ".ends $circuitname\n"; 35 | close OUT; 36 | print "$ARGV[1] has been written.\n"; 37 | } 38 | else 39 | { 40 | print "Could not open $ARGV[1] for writing: $!\n"; 41 | } 42 | close IN; 43 | } 44 | else 45 | { 46 | print "Could not open $ARGV[0] for reading: $!\n"; 47 | } 48 | 49 | 50 | -------------------------------------------------------------------------------- /Tools/perl/mag2siliwiz.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | # Converting MAGIC files to JSON for https://app.siliwiz.com/ 4 | 5 | my $scale=3; # Scale 1 would be technically correct, but the result is so small that you cannot see much, so Scale 3 is usually better 6 | my $movex=15; 7 | my $movey=25; 8 | 9 | print <; 42 | my $layer="undef"; 43 | my $count=0; 44 | foreach(@lines) 45 | { 46 | if(m/^<< (\w+) >>/) 47 | { 48 | $layer=layername($1); 49 | } 50 | if(m/^rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/) 51 | { 52 | print ", " if($count); 53 | print " { \"x\": ".($1*$scale+$movex).", \"y\": ".($2*$scale+$movey).", \"width\": ".(($3-$1)*$scale).", \"height\": ".(($4-$2)*$scale).", \"layer\": \"$layer\" }\n"; 54 | $count++; 55 | } 56 | if(m/^rlabel (\w+) (-?\d+) (-?\d+) (-?\d+) (-?\d+) (-?\d+) (\w+)/) 57 | { 58 | print ", " if($count); 59 | print " { \"x\": ".($2*$scale+$movex).", \"y\": ".($3*$scale+$movey).", \"width\": ".(($4-$2)*$scale).", \"height\": ".(($5-$3)*$scale).", \"layer\": \"".layername($1)."\", \"label\": \"".ioname($7)."\" }\n"; 60 | $count++; 61 | } 62 | } 63 | 64 | print <) 4 | { 5 | print; 6 | print "magscale 1 2\n" if(m/^tech/); 7 | } 8 | -------------------------------------------------------------------------------- /Tools/perl/muxgen.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | 4 | foreach my $n(2 .. 10) 5 | { 6 | open OUT,">MUX$n.cell"; 7 | print OUT ".AUTOGENERATED by muxgen Perl Script\n"; 8 | my @ins=(); 9 | push @ins,"IN$_" foreach(0 .. $n-1); 10 | push @ins,"S$_" foreach(0 .. $n-1); 11 | print OUT ".inputs ".join(" ",@ins)."\n"; 12 | print OUT ".outputs Z\n"; 13 | print OUT ".ORDER \"MOSFET Gate Drain Source\"\n"; 14 | foreach(0 .. $n-1) 15 | { 16 | print OUT "pmos IN$_ INT$_ vdd\n"; 17 | print OUT "nmos IN$_ INT$_ gnd\n"; 18 | print OUT "pmos S$_ INT$_ Y\n"; 19 | print OUT "nmos S$_ INT$_ Y\n"; 20 | } 21 | print OUT "pmos Y Z vdd\n"; 22 | print OUT "nmos Y Z gnd\n"; 23 | close OUT; 24 | 25 | 26 | } 27 | -------------------------------------------------------------------------------- /Tools/perl/paintgridusage.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | print "This tool analyzes the available, used and unused grid:\n"; 4 | my $cellname=$ARGV[0] || "INV"; 5 | open MAGIN,"<$cellname.mag"; 6 | open REPORT,"<$cellname.err"; 7 | #open REPIN,"<$cellname.log"; 8 | open MAGOUT,">$cellname.grid.mag"; 9 | my $fac=5; 10 | my $s=5; 11 | my $t=2; 12 | while() 13 | { 14 | if(/<< labels >>/) 15 | { 16 | # Unused tracks 17 | while (my $line=) 18 | { 19 | if($line=~m/Unused tracks \(x coordinates\): \[(.*?)\]/) 20 | { 21 | foreach(split(",",$1)) 22 | { 23 | $_=int($_/$fac); 24 | print MAGOUT "<< met1 >>\nrect $_ -100 ".($_+$s)." $t\n"; 25 | } 26 | } 27 | if($line=~m/Unused tracks \(y coordinates\): \[(.*?)\]/) 28 | { 29 | foreach(split(",",$1)) 30 | { 31 | $_=int($_/$fac); 32 | print MAGOUT "<< met1 >>\nrect -100 $_ $t ".($_+$s)."\n"; 33 | } 34 | } 35 | if($line=~m/grid_xs: \[(.*?)\]/) 36 | { 37 | foreach(split(",",$1)) 38 | { 39 | $_=int($_/$fac); 40 | print MAGOUT "<< met2 >>\nrect $_ -200 ".($_+$s)." -110\n"; 41 | } 42 | } 43 | if($line=~m/grid_ys: \[(.*?)\]/) 44 | { 45 | foreach(split(",",$1)) 46 | { 47 | $_=int($_/$fac); 48 | print MAGOUT "<< met2 >>\nrect -200 $_ -100 ".($_+$s)."\n"; 49 | } 50 | } 51 | if($line=~m/via cost: (\d+) \((-?\d+),(-?\d+)\) (\w+)/) 52 | { 53 | my $x=int($2/$fac); 54 | my $y=int($3/$fac); 55 | next unless($4 eq "pdiff_contact"); 56 | print "via cost $1 $2 $3 $4\n"; 57 | print MAGOUT "<< ".($1?"via3":"met3")." >>\nrect $x $y ".($x+$s)." ".($y+$s)."\n"; 58 | } 59 | 60 | } 61 | } 62 | print MAGOUT $_; 63 | } 64 | close MAGIN; 65 | close REPORT; 66 | #close REPIN; 67 | close MAGOUT; 68 | print "Writing to $cellname.grid.mag\n"; 69 | -------------------------------------------------------------------------------- /Tools/perl/parasitics.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | my $mag=$ARGV[0] || ""; $mag=~s/\.mag$//i; 4 | my $sp=$mag; $sp.=".par.sp"; 5 | my $par=$ARGV[1] || $sp; 6 | 7 | my $tech=$ARGV[2] || "../Tech/libresilicon.tech"; 8 | 9 | print "parasitics.pl - Extract parasitics from a .mag file for characterization into a .par.sp (PARasitics-SPice) file\n"; 10 | print "Usage: parasitics.pl input.mag output.par.sp\n"; 11 | 12 | if(-f "$mag.mag") 13 | { 14 | unlink "$mag.nodes"; 15 | unlink "$mag.res.ext"; 16 | unlink "$mag.spice"; 17 | unlink "$mag.ext"; 18 | unlink "$mag.al"; 19 | unlink "$mag.res.lump"; 20 | unlink "$mag.sim"; 21 | 22 | print "First magic call:\n"; 23 | open OUT,"|magic -dnull -noconsole -T $tech $mag.mag"; 24 | print OUT <>$cellname.ext"; 72 | # #system "cat $cellname.ext"; 73 | # print "Second magic call:\n"; 74 | # open OUT,"|magic -dnull -noconsole -T $tech $mag.mag"; 75 | # print OUT <graph.g"; 6 | 7 | our $ncells=0; 8 | 9 | sub handleRecursive($$) 10 | { 11 | my $output1=$_[0]; $output1=~s/^Catalog/Pool/; 12 | print "Handling $_[0]\n"; 13 | foreach("nand","nor","aoi","oai") 14 | { 15 | my $output=$output1; 16 | $output=~s/\.cell$/-$_.cell/; 17 | my $pop=$output; $pop=~s/\.cell$//; $pop=~s/^Pool\///; $pop=~s/^Catalog\///; 18 | 19 | 20 | my $cmd="Tools/tcl/popcorn -o Pool -c $pop $_[0] -n $_ $_[0]"; 21 | print "\n\n$cmd\n"; 22 | system $cmd; 23 | if(-f $output) 24 | { 25 | print G "$_[0] -> $output\n"; 26 | $ncells++; 27 | handleRecursive($output,$_[1]+1) if($_[1]<2); 28 | } 29 | else 30 | { 31 | last; 32 | } 33 | } 34 | } 35 | 36 | foreach() 37 | { 38 | handleRecursive($_,0); 39 | } 40 | 41 | close G; 42 | 43 | print "Total cells generated: $ncells\n"; 44 | 45 | -------------------------------------------------------------------------------- /gafrc: -------------------------------------------------------------------------------- 1 | ;; ************ LibreSilicon's StdCellLibrary ******************* 2 | ;; 3 | ;; Organisation: Chipforge 4 | ;; Germany / European Union 5 | ;; 6 | ;; Profile: Chipforge focus on fine System-on-Chip Cores in 7 | ;; Verilog HDL Code which are easy understandable and 8 | ;; adjustable. For further information see 9 | ;; www.chipforge.org 10 | ;; there are projects from small cores up to PCBs, too. 11 | ;; 12 | ;; File: StdCellLib/gafrc 13 | ;; 14 | ;; Purpose: gEDA / gaf (lepton-EDA?) configuration file 15 | ;; 16 | ;; ************ gEDA/gaf 1.8.2 **************************** 17 | ;; 18 | ;; //////////////////////////////////////////////////////////////// 19 | ;; 20 | ;; Copyright (c) 2019 by chipforge 21 | ;; All rights reserved. 22 | ;; 23 | ;; This Standard Cell Library is licensed under the Libre Silicon 24 | ;; public license; you can redistribute it and/or modify it under 25 | ;; the terms of the Libre Silicon public license as published by 26 | ;; the Libre Silicon alliance, either version 1 of the License, or 27 | ;; (at your option) any later version. 28 | ;; 29 | ;; This design is distributed in the hope that it will be useful, 30 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | ;; See the Libre Silicon Public License for more details. 33 | ;; 34 | ;; //////////////////////////////////////////////////////////////////// 35 | 36 | ;; ---------------------------------------------------------------- 37 | ;; LIBRARY DEFINITIONS 38 | ;; ---------------------------------------------------------------- 39 | 40 | (source-library "Sources/geda") 41 | (component-library "Sources/geda") 42 | ;(component-library "Library/spice") 43 | -------------------------------------------------------------------------------- /gnetlistrc: -------------------------------------------------------------------------------- 1 | ;; ************ LibreSilicon's StdCellLibrary ******************* 2 | ;; 3 | ;; Organisation: Chipforge 4 | ;; Germany / European Union 5 | ;; 6 | ;; Profile: Chipforge focus on fine System-on-Chip Cores in 7 | ;; Verilog HDL Code which are easy understandable and 8 | ;; adjustable. For further information see 9 | ;; www.chipforge.org 10 | ;; there are projects from small cores up to PCBs, too. 11 | ;; 12 | ;; File: StdCellLib/gnetlistrc 13 | ;; 14 | ;; Purpose: gEDA / gaf (lepton-EDA?) netlister file 15 | ;; 16 | ;; ************ gEDA/gaf 1.8.2 **************************** 17 | ;; 18 | ;; //////////////////////////////////////////////////////////////// 19 | ;; 20 | ;; Copyright (c) 2019 by chipforge 21 | ;; All rights reserved. 22 | ;; 23 | ;; This Standard Cell Library is licensed under the Libre Silicon 24 | ;; public license; you can redistribute it and/or modify it under 25 | ;; the terms of the Libre Silicon public license as published by 26 | ;; the Libre Silicon alliance, either version 1 of the License, or 27 | ;; (at your option) any later version. 28 | ;; 29 | ;; This design is distributed in the hope that it will be useful, 30 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 32 | ;; See the Libre Silicon Public License for more details. 33 | ;; 34 | ;; //////////////////////////////////////////////////////////////////// 35 | 36 | ;; ---------------------------------------------------------------- 37 | ;; SWITCHES 38 | ;; ---------------------------------------------------------------- 39 | 40 | (hierarchy-netattrib-mangle "disabled") 41 | (hierarchy-netname-mangle "enabled") 42 | (hierarchy-traversal "disabled") 43 | 44 | --------------------------------------------------------------------------------