├── 0.c_call_py_only ├── Makefile ├── c_call_py.c └── py_gen.py ├── 1.systemverilog_demo ├── gen_pkt_tb.sv ├── makefile.irun ├── makefile.questa ├── makefile.vcs ├── soft │ ├── c_call_py.c │ └── py_gen.py └── vsim.do ├── 2.systemverilog_with_python_module_code ├── Makefile ├── c_call_py.c ├── gen_pkt_tb.sv ├── py_gen.py └── scapy-2.4.4.tar.gz ├── 3.systemverilog_with_installed_python_module ├── Makefile ├── c_call_py.c ├── gen_pkt_tb.sv └── py_gen.py ├── LICENSE └── README.md /0.c_call_py_only/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: clean comp run 3 | 4 | clean: 5 | rm -rf main __pycache__ 6 | comp: 7 | gcc c_call_py.c -o main -I/usr/include/python3.6m -lpython3.6m -lpthread -ldl -lutil -lm 8 | run: 9 | export PYTHONPATH=. && ./main 10 | -------------------------------------------------------------------------------- /0.c_call_py_only/c_call_py.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | static PyObject *pModule = NULL; 5 | static PyObject *pFunc = NULL; 6 | static PyObject *pDict = NULL; 7 | static PyObject *pReturn = NULL; 8 | static PyObject *ArgList = NULL; 9 | static PyGILState_STATE py_state; 10 | 11 | extern void c_py_init(){ 12 | int i; 13 | double cArray[] = {1,2,3,4,5,6,}; 14 | Py_Initialize(); 15 | 16 | py_state = PyGILState_Ensure(); 17 | 18 | pModule = PyImport_ImportModule("py_gen"); 19 | pDict = PyModule_GetDict(pModule); 20 | pFunc = PyDict_GetItemString(pDict,"gen_pkt"); 21 | 22 | PyObject *PyList = PyList_New(6); 23 | ArgList = PyTuple_New(1); 24 | 25 | for(i = 0; i < PyList_Size(PyList); i++){ 26 | PyList_SetItem(PyList, i, PyFloat_FromDouble(cArray[i])); 27 | } 28 | 29 | PyTuple_SetItem(ArgList, 0, PyList); 30 | printf("initialize Python runtime !\n"); 31 | } 32 | 33 | extern void c_py_final(){ 34 | Py_DECREF(pModule); 35 | Py_DECREF(pFunc ); 36 | Py_DECREF(pDict ); 37 | Py_DECREF(pReturn); 38 | Py_DECREF(ArgList); 39 | PyGILState_Release(py_state); 40 | Py_Finalize(); 41 | printf("finalize Python runtime !\n"); 42 | } 43 | 44 | //static unsigned char tmp[256] = {0}; 45 | extern void c_py_gen_packet(){ 46 | int num; 47 | int i; 48 | char *result; 49 | 50 | pReturn = PyObject_CallObject(pFunc, ArgList); 51 | 52 | if(PyBytes_Check(pReturn)){ 53 | num = PyBytes_Size(pReturn); 54 | result = PyBytes_AsString(pReturn); 55 | //memcpy(pkt,result,num); 56 | for( i = 0; i < num; i++){ 57 | printf("%02X ", result[i]); 58 | } 59 | 60 | printf("\n"); 61 | } else { 62 | printf("Get No Bytes Form Python !!!\n"); 63 | } 64 | } 65 | 66 | int main( int argc, char* args[] ){ 67 | 68 | c_py_init(); 69 | 70 | c_py_gen_packet(); 71 | 72 | c_py_final(); 73 | 74 | return 0; 75 | } 76 | -------------------------------------------------------------------------------- /0.c_call_py_only/py_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | def gen_pkt(List): 4 | print("C to Python :") 5 | print(List) 6 | p = "This is Python Data !" 7 | print("python print :"+p) 8 | byte = p.encode() 9 | return byte 10 | -------------------------------------------------------------------------------- /1.systemverilog_demo/gen_pkt_tb.sv: -------------------------------------------------------------------------------- 1 | module hello_world; 2 | 3 | import "DPI-C" function void c_py_init(); 4 | import "DPI-C" function void c_py_final(); 5 | import "DPI-C" function void c_py_gen_packet(input bit[63:0] mode, output bit[2047:0] pkt, output bit [7:0] len); 6 | 7 | bit [2047:0] data; 8 | bit [7 :0] len ; 9 | bit [63 :0] mode; 10 | 11 | initial begin 12 | mode = 64'h11_13011112; 13 | c_py_init(); 14 | c_py_gen_packet(mode,data,len); 15 | 16 | $display("print data in systemverilog !"); 17 | 18 | $display("get len ='h%h",len ); 19 | $display("get data ='h%h",data); 20 | $display("get data = %s",data); 21 | 22 | c_py_final(); 23 | $finish(); 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /1.systemverilog_demo/makefile.irun: -------------------------------------------------------------------------------- 1 | PYTHON_PATH := $(abspath ./soft) 2 | SOFT_INC := $(abspath ./soft) 3 | SOFT_SRC := $(shell echo `pwd`)/soft 4 | 5 | IRUN_CFLAG := -ccargs -lpython3.6m -ccargs -I/usr/include/python3.6m -ccargs -I$(SOFT_INC) -D'PYTHON_PATH=\"$(PYTHON_PATH)\"' 6 | IRUN_LDFLAG := -Wld,-lpython3.6m 7 | 8 | all: clean comp run 9 | 10 | clean: 11 | rm -rf INCA_libs irun.* *.log $(SOFT_SRC)/__pycache__ 12 | comp: 13 | irun -sv -64bit -c $(IRUN_CFLAG) $(IRUN_LDFLAG) $(SOFT_SRC)/c_call_py.c gen_pkt_tb.sv -top hello_world 14 | run: 15 | irun -R -64bit 16 | -------------------------------------------------------------------------------- /1.systemverilog_demo/makefile.questa: -------------------------------------------------------------------------------- 1 | PYTHON_PATH := $(abspath ./soft) 2 | SOFT_INC := $(abspath ./soft) 3 | SOFT_SRC := $(shell echo `pwd`)/soft 4 | 5 | VLOG_CFLAG := -ccflags -lpython3.6m -ccflags -I/usr/include/python3.6m -ccflags -I$(SOFT_INC) -ccflags -D'PYTHON_PATH=\"$(PYTHON_PATH)\"' 6 | VLOG_LDFLAG := -ldflags -lpython3.6m 7 | 8 | all: clean comp run 9 | 10 | clean: 11 | rm -rf transcript *.log $(SOFT_SRC)/__pycache__ work* 12 | comp: 13 | vlib work 14 | vlog -64 $(VLOG_CFLAG) $(SOFT_SRC)/c_call_py.c gen_pkt_tb.sv 15 | run: 16 | vsim -64 $(VLOG_LDFLAG) -do vsim.do -novopt -c hello_world 17 | -------------------------------------------------------------------------------- /1.systemverilog_demo/makefile.vcs: -------------------------------------------------------------------------------- 1 | PYTHON_PATH := $(abspath ./soft) 2 | SOFT_INC := $(abspath ./soft) 3 | SOFT_SRC := $(shell echo `pwd`)/soft 4 | 5 | VCS_CFLAG := -CC -lpython3.6m -CC -I/usr/include/python3.6m -CC -I$(SOFT_INC) -CC -D'PYTHON_PATH=\"$(PYTHON_PATH)\"' 6 | VCS_LDFLAG := -LDFLAGS -Wl,--no-as-needed -LDFLAGS -lpython3.6m 7 | 8 | all: clean comp run 9 | 10 | clean: 11 | rm -rf simv* csrc* *.log $(SOFT_SRC)/__pycache__ ucli.key vc_hdrs.h stack.info.* 12 | comp: 13 | vcs -full64 $(VCS_CFLAG) $(VCS_LDFLAG) $(SOFT_SRC)/c_call_py.c -sverilog gen_pkt_tb.sv -l comp.log 14 | run: 15 | ./simv -l run.log 16 | -------------------------------------------------------------------------------- /1.systemverilog_demo/soft/c_call_py.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #ifndef PYTHON_PATH 6 | #error You must define the PYTHONPATH to the python file in gcc compiler with -D 7 | #endif 8 | 9 | static PyObject *pModule = NULL; 10 | static PyObject *pFunc = NULL; 11 | static PyObject *pDict = NULL; 12 | static PyObject *pReturn = NULL; 13 | static PyObject *PyList = NULL; 14 | static PyObject *ArgList = NULL; 15 | static PyGILState_STATE py_state; 16 | 17 | extern void c_py_init(){ 18 | char *append_path = malloc(sizeof(char) * 1000); 19 | append_path = PYTHON_PATH":."; 20 | setenv("PYTHONPATH",append_path,1);//Set PYTHONPATH TO working directory https://www.ibm.com/support/knowledgecenter/en/SSLTBW_2.1.0/com.ibm.zos.v2r1.bpxbd00/setenv.htm 21 | printf("PYTHONPATH is:%s !\n", append_path); 22 | 23 | Py_Initialize(); 24 | 25 | py_state = PyGILState_Ensure(); 26 | 27 | pModule = PyImport_ImportModule("py_gen"); 28 | printf("Import python script is py_gen.py !\n"); 29 | pDict = PyModule_GetDict(pModule); 30 | pFunc = PyDict_GetItemString(pDict,"gen_pkt"); 31 | printf("Python function is gen_pkt !\n"); 32 | 33 | PyList = PyList_New(2); 34 | ArgList = PyTuple_New(1); 35 | printf("initialize Python runtime !\n"); 36 | } 37 | 38 | extern void c_py_final(){ 39 | Py_DECREF(pModule); 40 | Py_DECREF(pFunc ); 41 | Py_DECREF(pDict ); 42 | Py_DECREF(pReturn); 43 | Py_DECREF(ArgList); 44 | Py_DECREF(PyList ); 45 | PyGILState_Release(py_state); 46 | Py_Finalize(); 47 | printf("finalize Python runtime !\n"); 48 | } 49 | 50 | static unsigned char tmp[256] = {0}; 51 | extern void c_py_gen_packet( /*input*/const svBitVecVal *mode ,/*output*/ svBitVecVal *pkt, /*output*/ svBitVecVal *len){ 52 | int num; 53 | int i; 54 | char *result; 55 | 56 | PyList_SetItem(PyList, 0, PyLong_FromLong(mode[0]) ); 57 | PyList_SetItem(PyList, 1, PyLong_FromLong(mode[1]) ); 58 | 59 | PyTuple_SetItem(ArgList, 0, PyList); 60 | 61 | pReturn = PyObject_CallObject(pFunc, ArgList); 62 | 63 | if(PyBytes_Check(pReturn)){ 64 | num = PyBytes_Size(pReturn); 65 | result = PyBytes_AsString(pReturn); 66 | //memcpy(pkt,result,num); 67 | for( i = 0; i < num; i++){ 68 | tmp[255-i] = result[i]; 69 | printf("%02X ",result[i]); 70 | } 71 | memcpy(pkt, tmp, 256); 72 | 73 | *len = num; 74 | printf("\n"); 75 | } else { 76 | printf("Get No Bytes Form Python !!!\n"); 77 | } 78 | } 79 | -------------------------------------------------------------------------------- /1.systemverilog_demo/soft/py_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | def gen_pkt(List): 4 | print("C to Python :") 5 | print(List) 6 | p = "This is Python Data !" 7 | print("python print :"+p) 8 | byte = p.encode() 9 | return byte -------------------------------------------------------------------------------- /1.systemverilog_demo/vsim.do: -------------------------------------------------------------------------------- 1 | run 2 | -------------------------------------------------------------------------------- /2.systemverilog_with_python_module_code/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: clean comp run 3 | 4 | clean: 5 | \rm -rf simv* csrc* *.log __pycache__ ucli.key vc_hdrs.h stack.info.* 6 | comp: 7 | vcs -full64 -LDFLAGS -Wl,--no-as-needed -CC -lpython3.6m -lpthread -ldl -lutil -lm -LDFLAGS -lpython3.6m -CC -I/usr/include/python3.6m -CC -I. -sverilog gen_pkt_tb.sv c_call_py.c -l comp.log 8 | run: 9 | export PYTHONPATH=.:./scapy-2.4.4 && ./simv -l run.log 10 | -------------------------------------------------------------------------------- /2.systemverilog_with_python_module_code/c_call_py.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | static PyObject *pModule = NULL; 6 | static PyObject *pFunc = NULL; 7 | static PyObject *pDict = NULL; 8 | static PyObject *pReturn = NULL; 9 | static PyObject *ArgList = NULL; 10 | static PyGILState_STATE py_state; 11 | 12 | extern void c_py_init(){ 13 | int i; 14 | double cArray[] = {1,2,3,4,5,6,}; 15 | Py_Initialize(); 16 | 17 | py_state = PyGILState_Ensure(); 18 | 19 | pModule = PyImport_ImportModule("py_gen"); 20 | pDict = PyModule_GetDict(pModule); 21 | pFunc = PyDict_GetItemString(pDict,"gen_pkt"); 22 | 23 | PyObject *PyList = PyList_New(6); 24 | ArgList = PyTuple_New(1); 25 | 26 | for(i = 0; i < PyList_Size(PyList); i++){ 27 | PyList_SetItem(PyList, i, PyFloat_FromDouble(cArray[i])); 28 | } 29 | 30 | PyTuple_SetItem(ArgList, 0, PyList); 31 | printf("initialize Python runtime !\n"); 32 | } 33 | 34 | extern void c_py_final(){ 35 | PyGILState_Release(py_state); 36 | Py_Finalize(); 37 | printf("finalize Python runtime !\n"); 38 | } 39 | 40 | static unsigned char tmp[256] = {0}; 41 | extern void c_py_gen_packet(/*output*/ svBitVecVal *pkt, /*output*/ svBitVecVal *len){ 42 | int num; 43 | int i; 44 | unsigned char *result; 45 | 46 | pReturn = PyObject_CallObject(pFunc, ArgList); 47 | 48 | if(PyBytes_Check(pReturn)){ 49 | num = PyBytes_Size(pReturn); 50 | result = PyBytes_AsString(pReturn); 51 | //memcpy(pkt,result,num); 52 | for( i = 0; i < num; i++){ 53 | tmp[255-i] = result[i]; 54 | printf("%02X ",result[i]); 55 | } 56 | memcpy(pkt, tmp, 256); 57 | 58 | *len = num; 59 | printf("\n"); 60 | } else { 61 | printf("Get No Bytes Form Python !!!\n"); 62 | } 63 | } 64 | -------------------------------------------------------------------------------- /2.systemverilog_with_python_module_code/gen_pkt_tb.sv: -------------------------------------------------------------------------------- 1 | 2 | module hello_world; 3 | 4 | import "DPI-C" function void c_py_init(); 5 | import "DPI-C" function void c_py_final(); 6 | import "DPI-C" function void c_py_gen_packet(output bit[2047:0] pkt, output bit [7:0] len); 7 | 8 | bit [15:0][127:0] data; 9 | bit [7 :0] len ; 10 | 11 | initial begin 12 | c_py_init(); 13 | c_py_gen_packet(data,len); 14 | 15 | $display("print data in systemverilog !"); 16 | 17 | $display("get len ='h%h",len ); 18 | $display("get data ='h%h",data); 19 | $display("get data = %s",data); 20 | 21 | c_py_final(); 22 | $finish(); 23 | end 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /2.systemverilog_with_python_module_code/py_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from scapy.all import * 3 | 4 | def gen_pkt(List): 5 | p=Ether(dst='33:32:33:44:55:66',src='33:22:22:34:56:33')/IP(ihl=5)/UDP(dport=0x4a00)/'This is Python Data !' 6 | p.show() 7 | return raw(p) 8 | -------------------------------------------------------------------------------- /2.systemverilog_with_python_module_code/scapy-2.4.4.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/thinkoco/systemverilog-python/02f4443a59608d4dac8513bcc2b21919d82a08db/2.systemverilog_with_python_module_code/scapy-2.4.4.tar.gz -------------------------------------------------------------------------------- /3.systemverilog_with_installed_python_module/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: clean comp run 3 | 4 | clean: 5 | \rm -rf simv* csrc* *.log __pycache__ ucli.key vc_hdrs.h stack.info.* 6 | comp: 7 | vcs -full64 -LDFLAGS -Wl,--no-as-needed -CC -lpython3.6m -lpthread -ldl -lutil -lm -LDFLAGS -lpython3.6m -CC -I/usr/include/python3.6m -CC -I. -sverilog gen_pkt_tb.sv c_call_py.c -l comp.log 8 | run: 9 | export PYTHONPATH=. && ./simv -l run.log 10 | -------------------------------------------------------------------------------- /3.systemverilog_with_installed_python_module/c_call_py.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | static PyObject *pModule = NULL; 6 | static PyObject *pFunc = NULL; 7 | static PyObject *pDict = NULL; 8 | static PyObject *pReturn = NULL; 9 | static PyObject *ArgList = NULL; 10 | static PyGILState_STATE py_state; 11 | 12 | extern void c_py_init(){ 13 | int i; 14 | double cArray[] = {1,2,3,4,5,6,}; 15 | Py_Initialize(); 16 | 17 | py_state = PyGILState_Ensure(); 18 | 19 | pModule = PyImport_ImportModule("py_gen"); 20 | pDict = PyModule_GetDict(pModule); 21 | pFunc = PyDict_GetItemString(pDict,"gen_pkt"); 22 | 23 | PyObject *PyList = PyList_New(6); 24 | ArgList = PyTuple_New(1); 25 | 26 | for(i = 0; i < PyList_Size(PyList); i++){ 27 | PyList_SetItem(PyList, i, PyFloat_FromDouble(cArray[i])); 28 | } 29 | 30 | PyTuple_SetItem(ArgList, 0, PyList); 31 | printf("initialize Python runtime !\n"); 32 | } 33 | 34 | extern void c_py_final(){ 35 | PyGILState_Release(py_state); 36 | Py_Finalize(); 37 | printf("finalize Python runtime !\n"); 38 | } 39 | 40 | static unsigned char tmp[256] = {0}; 41 | extern void c_py_gen_packet(/*output*/ svBitVecVal *pkt, /*output*/ svBitVecVal *len){ 42 | int num; 43 | int i; 44 | unsigned char *result; 45 | 46 | pReturn = PyObject_CallObject(pFunc, ArgList); 47 | 48 | if(PyBytes_Check(pReturn)){ 49 | num = PyBytes_Size(pReturn); 50 | result = PyBytes_AsString(pReturn); 51 | //memcpy(pkt,result,num); 52 | for( i = 0; i < num; i++){ 53 | tmp[255-i] = result[i]; 54 | printf("%02X ",result[i]); 55 | } 56 | memcpy(pkt, tmp, 256); 57 | 58 | *len = num; 59 | printf("\n"); 60 | } else { 61 | printf("Get No Bytes Form Python !!!\n"); 62 | } 63 | } 64 | -------------------------------------------------------------------------------- /3.systemverilog_with_installed_python_module/gen_pkt_tb.sv: -------------------------------------------------------------------------------- 1 | 2 | module hello_world; 3 | 4 | import "DPI-C" function void c_py_init(); 5 | import "DPI-C" function void c_py_final(); 6 | import "DPI-C" function void c_py_gen_packet(output bit[2047:0] pkt, output bit [7:0] len); 7 | 8 | bit [15:0][127:0] data; 9 | bit [7 :0] len ; 10 | 11 | initial begin 12 | c_py_init(); 13 | c_py_gen_packet(data,len); 14 | 15 | $display("print data in systemverilog !"); 16 | 17 | $display("get len ='h%h",len ); 18 | $display("get data ='h%h",data); 19 | $display("get data = %s",data); 20 | 21 | c_py_final(); 22 | $finish(); 23 | end 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /3.systemverilog_with_installed_python_module/py_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from scapy.all import * 3 | 4 | def gen_pkt(List): 5 | p=Ether(dst='33:32:33:44:55:66',src='33:22:22:34:56:33')/IP(ihl=5)/UDP(dport=0x4a00)/'This is Python Data !' 6 | p.show() 7 | return raw(p) 8 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. 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Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | , 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # systemverilog-python 2 | Systemverilog DPI-C call Python function 3 | 4 | 5 | SystemVerilog C Python 6 | ___________________ __________________ _________________ 7 | | | | | | | 8 | | | | py_initial(){}; | | import module | 9 | | DPI-C func1(a,b); | | | | | 10 | | DPI-C func2(c,d); | | func1(a,b){ | | | 11 | | | | py_func1_wrap | | | 12 | | py_initial(); | | }; | | | 13 | | | <---> | | <---> | def py_func1() | 14 | | func1(x,x); | | func2(c,d){ | | | 15 | | func2(x,x); | | py_func2_wrap | | def py_func2() | 16 | | | | }; | | | 17 | | py_final(); | | | | | 18 | | | | py_final(){}; | | | 19 | |___________________| |__________________| |_________________| 20 | 21 | 22 | ## Feature 23 | - Synopsys,Mentor Graphics,Cadence EDA Tools 24 | - Python Function Call 25 | - Python modules e.g. Scapy 26 | - systemverilog data form/to python 27 | 28 | ## Use Guide 29 | ### 0.c_call_py_only 30 | ``` 31 | cd 0.c_call_py_only 32 | make 33 | ``` 34 | ### 1.systemverilog_demo 35 | ``` 36 | cd 0.systemverilog_demo 37 | make -f makefile.vcs #for Synopsys VCS 38 | make -f makefile.questa #for Mentor Graphics Questa 39 | make -f makefile.irun #for Cadence INCISIVE 40 | ``` 41 | 42 | ### 1.systemverilog_with_python_module_code 43 | ``` 44 | cd 1.systemverilog_with_python_module_code 45 | tar xvf scapy-2.4.4.tar.gz 46 | make 47 | ``` 48 | ## 2.systemverilog_with_installed_python_module 49 | ``` 50 | python3 -m pip install scapy 51 | cd 2.systemverilog_with_installed_python_module 52 | make 53 | ``` 54 | 55 | ### logs 56 | ``` 57 | \rm -rf simv* csrc* *.log __pycache__ ucli.key vc_hdrs.h stack.info.* 58 | vcs -full64 -LDFLAGS -Wl,--no-as-needed +incdir+./c -CC -lpython3.6m -CC -lpthread -CC -ldl -CC -lutil -lm -LDFLAGS -lpython3.6m -CC -I/usr/include/python3.6m -CC -I./ -sverilog gen_pkt_tb.sv c_call_py.c -l comp.log 59 | Chronologic VCS (TM) 60 | Version O-2018.09-SP2_Full64 -- Sat Mar 6 23:51:16 2021 61 | Copyright (c) 1991-2018 by Synopsys Inc. 62 | ALL RIGHTS RESERVED 63 | 64 | This program is proprietary and confidential information of Synopsys Inc. 65 | and may be used and disclosed only as authorized in a license agreement 66 | controlling such use and disclosure. 67 | 68 | Parsing design file 'gen_pkt_tb.sv' 69 | Top Level Modules: 70 | hello_world 71 | No TimeScale specified 72 | Starting vcs inline pass... 73 | 74 | 1 module and 0 UDP read. 75 | recompiling module hello_world 76 | make[1]: Entering directory '/home/knat/tmp/c_call_py/0.systemverilog_only/csrc' 77 | rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so 78 | gcc -w -pipe -fPIC -lpython3.6m -lpthread -ldl -lutil -I/usr/include/python3.6m -I./ -O -I/opt/synopsys/O-2018.09-SP2/include -c ../c_call_py.c 79 | if [ -x ../simv ]; then chmod -x ../simv; fi 80 | g++ -o ../simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -Wl,--no-as-needed -lpython3.6m -rdynamic -Wl,-rpath=/opt/synopsys/O-2018.09-SP2/linux64/lib -L/opt/synopsys/O-2018.09-SP2/linux64/lib c_call_py.o objs/amcQw_d.o _4021_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lm -lvcsnew -lsimprofile -luclinative /opt/synopsys/O-2018.09-SP2/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive ./../simv.daidir/vc_hdrs.o /opt/synopsys/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o -ldl -lc -lm -lpthread -ldl 81 | ../simv up to date 82 | make[1]: Leaving directory '/home/knat/tmp/c_call_py/0.systemverilog_only/csrc' 83 | CPU time: .160 seconds to compile + .141 seconds to elab + .251 seconds to link 84 | ./simv -l run.log 85 | Chronologic VCS simulator copyright 1991-2018 86 | Contains Synopsys proprietary information. 87 | Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Mar 6 23:51 2021 88 | initialize Python runtime ! 89 | ###[ Ethernet ]### 90 | dst = 33:32:33:44:55:66 91 | src = 33:22:22:34:56:33 92 | type = IPv4 93 | ###[ IP ]### 94 | version = 4 95 | ihl = 5 96 | tos = 0x0 97 | len = None 98 | id = 1 99 | flags = 100 | frag = 0 101 | ttl = 64 102 | proto = udp 103 | chksum = None 104 | src = 127.0.0.1 105 | dst = 127.0.0.1 106 | \options \ 107 | ###[ UDP ]### 108 | sport = domain 109 | dport = 18944 110 | len = None 111 | chksum = None 112 | ###[ Raw ]### 113 | load = 'This is Python Data !' 114 | 115 | 33 32 33 44 55 66 33 22 22 34 56 33 08 00 45 00 00 31 00 01 00 00 40 11 7C B9 7F 00 00 01 7F 00 00 01 00 35 4A 00 00 1D 2D EE 54 68 69 73 20 69 73 20 50 79 74 68 6F 6E 20 44 61 74 61 20 21 116 | print data in systemverilog ! 117 | get len ='h3f 118 | get data ='h3332334455663322223456330800450000310001000040117cb97f0000017f00000100354a00001d2dee5468697320697320507974686f6e2044617461202100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 119 | get data = 323DUf3""4V E 1 @|� 5J -�This is Python Data ! 120 | finalize Python runtime ! 121 | $finish called from file "gen_pkt_tb.sv", line 22. 122 | $finish at simulation time 0 123 | V C S S i m u l a t i o n R e p o r t 124 | Time: 0 125 | CPU Time: 2.060 seconds; Data structure size: 0.0Mb 126 | Sat Mar 6 23:51:18 2021 127 | 128 | ``` 129 | --------------------------------------------------------------------------------