├── boards ├── enclustra-mercury-aa1-pe1 │ ├── Makefile │ ├── refdes.qpf │ ├── synth_settings.tcl │ ├── peripherals.ipx │ ├── refdes.sdc │ └── enclustra-pe1.dtsi └── intel-a10soc-devkit │ ├── Makefile │ ├── ghrd_10as066n2.qpf │ ├── peripherals.ipx │ ├── ghrd_10as066n2_board_info.xml │ ├── fpga_pcie.sdc │ ├── hps_sgmii.sdc │ ├── ghrd_timing.sdc │ ├── ip │ ├── edge_detect │ │ └── altera_edge_detector.v │ └── debounce │ │ └── debounce.v │ ├── jtag.sdc │ ├── hps_a10_common_board_info.xml │ ├── hps_a10_devkit_board_info.xml │ ├── ghrd_10as066n2_top.v │ └── ghrd_10as066n2.qsf ├── pcie-bsv ├── .gitignore ├── bsv │ ├── PCIePipes │ │ ├── Makefile │ │ ├── AvalonSTTB.bsv │ │ ├── PCIeByteSwap.bsv │ │ ├── MEM.bsv │ │ ├── AvalonSTPCIe.bsv │ │ ├── PCIePacketTransmitter_hw.tcl │ │ ├── PCIePacketReceiver_hw.tcl │ │ ├── PCIePacketReceiver.bsv │ │ ├── AvalonMM.bsv │ │ └── PCIePacketTransmitter.bsv │ └── qsys_ip │ │ └── PCIePipes │ │ ├── PCIePacketTransmitter_hw.tcl │ │ ├── PCIePacketReceiver_hw.tcl │ │ ├── mkPCIePacketReceiver.v │ │ └── mkPCIePacketTransmitter.v └── Makefile ├── Jenkinsfile ├── Makefile ├── makefiles └── intel.mk ├── README.md └── lib ├── FIFOL1.v └── SizedFIFO.v /boards/enclustra-mercury-aa1-pe1/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=refdes 2 | QSYS=system 3 | 4 | include ../../makefiles/intel.mk 5 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=ghrd_10as066n2 2 | QSYS=ghrd_10as066n2 3 | 4 | include ../../makefiles/intel.mk 5 | -------------------------------------------------------------------------------- /boards/enclustra-mercury-aa1-pe1/refdes.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "17.1" 2 | DATE = "09:43:27 January 05, 2018" 3 | PROJECT_REVISION = "refdes" 4 | -------------------------------------------------------------------------------- /pcie-bsv/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.bsp 3 | *.rpt 4 | db/ 5 | incremental_db/ 6 | *.smsg 7 | *.ddb 8 | *.summary 9 | bsv/PCIePipes/*.v 10 | *.bo 11 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/ghrd_10as066n2.qpf: -------------------------------------------------------------------------------- 1 | QUARTUS_VERSION = "15.1" 2 | DATE = "10:23:04 January 13, 2016" 3 | PROJECT_REVISION = "ghrd_10as066n2" 4 | -------------------------------------------------------------------------------- /boards/enclustra-mercury-aa1-pe1/synth_settings.tcl: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QSYS_FILE system.qsys 2 | set_global_assignment -name VERILOG_FILE mercury_aa1_top.v 3 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/peripherals.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 5 | 7 | 8 | -------------------------------------------------------------------------------- /boards/enclustra-mercury-aa1-pe1/peripherals.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 5 | 7 | 8 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/ghrd_10as066n2_board_info.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /boards/enclustra-mercury-aa1-pe1/refdes.sdc: -------------------------------------------------------------------------------- 1 | set_time_format -unit ns -decimal_places 3 2 | create_clock -name EMIF_REF_CLOCK -period 30 [get_ports emif_a10_hps_0_pll_ref_clk_clk] 3 | create_clock -name PCIE_REFCLK -period 10 [get_ports PCIE_REFCLK_p] 4 | -------------------------------------------------------------------------------- /boards/enclustra-mercury-aa1-pe1/enclustra-pe1.dtsi: -------------------------------------------------------------------------------- 1 | &arria10_hps_0_i_sdmmc_sdmmc { 2 | cap-sd-highspeed; 3 | broken-cd; 4 | clock-freq-min-max = <400000 25000000>; 5 | pwr-en = <0>; 6 | }; 7 | 8 | &arria10_hps_0_i_usbotg_0_globgrp { 9 | dr_mode = "host"; 10 | }; 11 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/fpga_pcie.sdc: -------------------------------------------------------------------------------- 1 | # Clock Group 2 | create_clock -name PCIE_REFCLK -period 10 [get_ports pcie_ep_refclk_100] 3 | derive_pll_clocks -create_base_clocks 4 | derive_clock_uncertainty 5 | 6 | set_clock_groups -exclusive -group [get_clocks {MAIN_CLOCK}] -group [get_clocks {PCIE_REFCLK}] 7 | 8 | #set_false_path -from [ get_ports {hps_pcie_a10_hip_avmm_0_npor_pin_perst}] 9 | set_false_path -from [ get_ports {pcie_tlp_buffer_pcie_ep_0_pcie_rstn_pin_perst}] 10 | -------------------------------------------------------------------------------- /Jenkinsfile: -------------------------------------------------------------------------------- 1 | // based on 2 | // https://support.cloudbees.com/hc/en-us/articles/115000088431-Create-a-Matrix-like-flow-with-Pipeline 3 | 4 | def boards = [ "intel-a10soc-devkit", "enclustra-mercury-aa1-pe1" ] 5 | def tasks = [:] 6 | 7 | for(int i=0; i < boards.size(); i++) { 8 | def boardValue = boards[i] 9 | tasks["${boardValue}"] = { 10 | node { 11 | def board = boardValue 12 | println "Building for ${board}" 13 | println "Node=${env.NODE_NAME}" 14 | checkout scm 15 | sh '''#!/bin/bash 16 | source /local/ecad/setup.bash 18.1 17 | ls -l 18 | make ${board} 19 | ''' 20 | archiveArtifacts "boards/${board}/output_files/*.sof,boards/${board}/output_files/*.rbf,boards/${board}/output_files/*.rpt,boards/${board}/*.qsys,boards/${board}/*.sopcinfo,boards/${board}/hps_isw_handoff/*,boards/${board}/*.dts*,boards/${board}/*.xml" 21 | } 22 | } 23 | } 24 | 25 | stage ("Matrix") { 26 | parallel tasks 27 | } 28 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/hps_sgmii.sdc: -------------------------------------------------------------------------------- 1 | # Clock Group 2 | create_clock -name PCS_REFLCLK -period 8.000 [get_ports {pcs_clk_125}] 3 | derive_pll_clocks -create_base_clocks 4 | derive_clock_uncertainty 5 | 6 | set_clock_groups -asynchronous -group [get_clocks {MAIN_CLOCK}] -group [get_clocks {PCS_REFLCLK}] -group [get_clocks {hps_emac2_gtx_clk}] -group [get_clocks {hps_emac1_gtx_clk}] -group [get_clocks {soc_inst|*|gmii_to_sgmii_converter_0|tx_clkout}] 7 | create_clock -name emac1_fpga_mdc -period 400.000 [get_keepers {*~emac1_gmii_mdc_o_1.reg}] 8 | create_clock -name emac2_fpga_mdc -period 400.000 [get_keepers {*~emac2_gmii_mdc_o_1.reg}] 9 | set_output_delay -clock { emac1_fpga_mdc } 30 [get_ports {emac1_fpga_mdio}] 10 | set_input_delay -clock { emac1_fpga_mdc } 30 [get_ports {emac1_fpga_mdio}] 11 | set_output_delay -clock { emac2_fpga_mdc } 30 [get_ports {emac2_fpga_mdio}] 12 | set_input_delay -clock { emac2_fpga_mdc } 30 [get_ports {emac2_fpga_mdio}] 13 | set_false_path -from * -to [ get_ports sgmii1_phy_reset_n ] 14 | set_false_path -from * -to [ get_ports sgmii2_phy_reset_n ] 15 | set_false_path -from * -to [ get_ports emac1_fpga_mdc ] 16 | set_false_path -from * -to [ get_ports emac2_fpga_mdc ] 17 | 18 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/ghrd_timing.sdc: -------------------------------------------------------------------------------- 1 | set_time_format -unit ns -decimal_places 3 2 | 3 | # 100MHz board input clock, 133.3333MHz for EMIF refclk 4 | create_clock -name MAIN_CLOCK -period 10 [get_ports fpga_clk_100] 5 | create_clock -name EMIF_REF_CLOCK -period 7.5 [get_ports emif_ref_clk] 6 | 7 | 8 | set_false_path -from [get_ports {fpga_reset_n}] 9 | set_input_delay -clock MAIN_CLOCK 1 [get_ports {fpga_reset_n}] 10 | set_false_path -from [get_ports altera_reserved_ntrst] -to * 11 | 12 | # sourcing JTAG related SDC 13 | source ./jtag.sdc 14 | 15 | # FPGA IO port constraints 16 | set_false_path -from [get_ports {fpga_button_pio[0]}] -to * 17 | set_false_path -from [get_ports {fpga_button_pio[1]}] -to * 18 | set_false_path -from [get_ports {fpga_button_pio[2]}] -to * 19 | set_false_path -from [get_ports {fpga_button_pio[3]}] -to * 20 | set_false_path -from [get_ports {fpga_dipsw_pio[0]}] -to * 21 | set_false_path -from [get_ports {fpga_dipsw_pio[1]}] -to * 22 | set_false_path -from [get_ports {fpga_dipsw_pio[2]}] -to * 23 | set_false_path -from [get_ports {fpga_dipsw_pio[3]}] -to * 24 | set_false_path -from [get_ports {fpga_led_pio[0]}] -to * 25 | set_false_path -from [get_ports {fpga_led_pio[1]}] -to * 26 | set_false_path -from [get_ports {fpga_led_pio[2]}] -to * 27 | set_false_path -from [get_ports {fpga_led_pio[3]}] -to * 28 | set_false_path -from * -to [get_ports {fpga_led_pio[0]}] 29 | set_false_path -from * -to [get_ports {fpga_led_pio[1]}] 30 | set_false_path -from * -to [get_ports {fpga_led_pio[2]}] 31 | set_false_path -from * -to [get_ports {fpga_led_pio[3]}] 32 | 33 | 34 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | #- 2 | # SPDX-License-Identifier: BSD-2-Clause 3 | # 4 | # Copyright (c) 2019 A. Theodore Markettos 5 | # All rights reserved. 6 | # 7 | # This software was developed by SRI International, the University of 8 | # Cambridge Computer Laboratory (Department of Computer Science and 9 | # Technology), and ARM Research under DARPA contract HR0011-18-C-0016 10 | # ("ECATS"), as part of the DARPA SSITH research programme. 11 | # 12 | # Redistribution and use in source and binary forms, with or without 13 | # modification, are permitted provided that the following conditions 14 | # are met: 15 | # 1. Redistributions of source code must retain the above copyright 16 | # notice, this list of conditions and the following disclaimer. 17 | # 2. Redistributions in binary form must reproduce the above copyright 18 | # notice, this list of conditions and the following disclaimer in the 19 | # documentation and/or other materials provided with the distribution. 20 | # 21 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 | # ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 | # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 | # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 | # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 | # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 | # SUCH DAMAGE. 32 | # 33 | 34 | 35 | TARGETS=enclustra-mercury-aa1-pe1 \ 36 | intel-a10soc-devkit 37 | 38 | .PHONY: ${TARGETS} 39 | 40 | all: ${TARGETS} 41 | 42 | $(TARGETS): % : % 43 | $(MAKE) -C boards/$* 44 | 45 | clean_$(TARGETS): 46 | 47 | %.clean: 48 | echo $* 49 | $(MAKE) -C boards/$* clean 50 | 51 | clean: $(addsuffix .clean, $(TARGETS)) 52 | -------------------------------------------------------------------------------- /makefiles/intel.mk: -------------------------------------------------------------------------------- 1 | #- 2 | # SPDX-License-Identifier: BSD-2-Clause 3 | # 4 | # Copyright (c) 2019 A. Theodore Markettos 5 | # All rights reserved. 6 | # 7 | # This software was developed by SRI International, the University of 8 | # Cambridge Computer Laboratory (Department of Computer Science and 9 | # Technology), and ARM Research under DARPA contract HR0011-18-C-0016 10 | # ("ECATS"), as part of the DARPA SSITH research programme. 11 | # 12 | # Redistribution and use in source and binary forms, with or without 13 | # modification, are permitted provided that the following conditions 14 | # are met: 15 | # 1. Redistributions of source code must retain the above copyright 16 | # notice, this list of conditions and the following disclaimer. 17 | # 2. Redistributions in binary form must reproduce the above copyright 18 | # notice, this list of conditions and the following disclaimer in the 19 | # documentation and/or other materials provided with the distribution. 20 | # 21 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 | # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 | # ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 | # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 | # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 | # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 | # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 | # SUCH DAMAGE. 32 | # 33 | 34 | 35 | # General rules for building Intel/Altera Qsys(Platform Designer)/Quartus 36 | # projects 37 | 38 | all: output_files/${PROJECT}.rbf 39 | 40 | ${QSYS}/${QSYS}.qip: 41 | qsys-generate ${QSYS}.qsys --synthesis=verilog 42 | 43 | output_files/${PROJECT}.sof: ${QSYS}/${QSYS}.qip 44 | quartus_sh --flow compile ${PROJECT} 45 | 46 | output_files/${PROJECT}.rbf: output_files/${PROJECT}.sof 47 | quartus_cpf -c $< $@ 48 | 49 | clean: 50 | -rm -rf ${QSYS}/ ${QSYS}.sopcinfo 51 | -rm -rf output_files db incremental_db 52 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/Makefile: -------------------------------------------------------------------------------- 1 | BSC=bsc 2 | LIBS=../../ 3 | BSCFLAGS=-keep-fires -cross-info -aggressive-conditions -p +:$(LIBS) 4 | VERILOGDEST=../qsys_ip/PCIePipes 5 | 6 | #all: $(VERILOGDEST) $(VERILOGDEST)/mkMMRingBuffer.v $(VERILOGDEST)/mkMMRingBufferSink.v $(VERILOGDEST)/mkMMRingBufferSource.v 7 | all: $(VERILOGDEST) $(VERILOGDEST)/mkPCIePacketReceiver.v $(VERILOGDEST)/mkPCIePacketTransmitter.v 8 | 9 | $(VERILOGDEST): 10 | mkdir -p $(VERILOGDEST) 11 | cp *.tcl $(VERILOGDEST) 12 | 13 | $(VERILOGDEST)/mkMMRingBuffer.v: MMRingBuffer.bsv 14 | $(BSC) $(BSCFLAGS) -vdir $(VERILOGDEST) -u -verilog -g mkMMRingBuffer MMRingBuffer.bsv 15 | 16 | $(VERILOGDEST)/mkMMRingBufferSink.v: MMRingBuffer.bsv 17 | $(BSC) $(BSCFLAGS) -vdir $(VERILOGDEST) -u -verilog -g mkMMRingBufferSink MMRingBuffer.bsv 18 | 19 | $(VERILOGDEST)/mkMMRingBufferSource.v: MMRingBuffer.bsv 20 | $(BSC) $(BSCFLAGS) -vdir $(VERILOGDEST) -u -verilog -g mkMMRingBufferSource MMRingBuffer.bsv 21 | 22 | $(VERILOGDEST)/mkPCIePacketReceiver.v: PCIePacketReceiver.bsv 23 | $(BSC) $(BSCFLAGS) -vdir $(VERILOGDEST) -u -verilog -g mkPCIePacketReceiver PCIePacketReceiver.bsv 24 | 25 | $(VERILOGDEST)/mkPCIePacketTransmitter.v: PCIePacketTransmitter.bsv 26 | $(BSC) $(BSCFLAGS) -vdir $(VERILOGDEST) -u -verilog -g mkPCIePacketTransmitter PCIePacketTransmitter.bsv 27 | 28 | ringtest: 29 | $(BSC) $(BSCFLAGS) -u -sim -g mkMMRingBufferTB MMRingBufferTB.bsv 30 | $(BSC) $(BSCFLAGS) -e mkMMRingBufferTB -sim -o mkMMRingBufferTB -g mkMMRingBufferTB 31 | 32 | sttest: 33 | $(BSC) $(BSCFLAGS) -u -sim -g mkAvalonSinkTB AvalonSTTB.bsv 34 | $(BSC) $(BSCFLAGS) -e mkAvalonSinkTB -sim -o mkAvalonSinkTB -g mkAvalonSinkTB 35 | $(BSC) $(BSCFLAGS) -u -sim -g mkAvalonSourceTB AvalonSTTB.bsv 36 | $(BSC) $(BSCFLAGS) -e mkAvalonSourceTB -sim -o mkAvalonSourceTB -g mkAvalonSourceTB 37 | 38 | pcietest: 39 | $(BSC) $(BSCFLAGS) -u -sim -g mkPCIePacketReceiverTB PCIePacketReceiver.bsv 40 | $(BSC) $(BSCFLAGS) -e mkPCIePacketReceiverTB -sim -o mkPCIePacketReceiverTB -g mkPCIePacketReceiverTB 41 | $(BSC) $(BSCFLAGS) -u -sim -g mkPCIePacketTransmitterTB PCIePacketTransmitter.bsv 42 | $(BSC) $(BSCFLAGS) -e mkPCIePacketTransmitterTB -sim -o mkPCIePacketTransmitterTB -g mkPCIePacketTransmitterTB 43 | # ./sim 44 | 45 | $(VERILOGDEST)/mkAvalonSinkPCIe.v: AvalonST.bsv 46 | $(BSC) $(BSCFLAGS) -vdir $(VERILOGDEST) -u -verilog -g mkAvalonSinkPCIe AvalonST.bsv 47 | 48 | $(VERILOGDEST)/mkAvalonSourcePCIe.v: AvalonST.bsv 49 | $(BSC) $(BSCFLAGS) -vdir $(VERILOGDEST) -u -verilog -g mkAvalonSourcePCIe AvalonST.bsv 50 | 51 | 52 | 53 | .PHONY: clean 54 | clean: 55 | rm -f *.bi *.bo *.ba *.info *.sched *.h *.o *.so $(VERILOGDEST)/mk*.v *~ >/dev/null 56 | rm -rf $(VERILOGDEST) 57 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | module altera_edge_detector #( 2 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 3 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 4 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 5 | ) ( 6 | input clk, 7 | input rst_n, 8 | input signal_in, 9 | output pulse_out 10 | ); 11 | 12 | localparam IDLE = 0, ARM = 1, CAPT = 2; 13 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 14 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 15 | 16 | reg [1:0] state, next_state; 17 | reg pulse_detect; 18 | wire busy_pulsing; 19 | wire reset_qual_n; 20 | 21 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 22 | assign reset_qual_n = rst_n | busy_pulsing; 23 | 24 | generate 25 | if (PULSE_EXT > 1) begin: pulse_extend 26 | integer i; 27 | reg [PULSE_EXT-1:0] extend_pulse; 28 | always @(posedge clk or negedge reset_qual_n) begin 29 | if (!reset_qual_n) 30 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 31 | else begin 32 | for (i = 1; i < PULSE_EXT; i = i+1) begin 33 | extend_pulse[i] <= extend_pulse[i-1]; 34 | end 35 | extend_pulse[0] <= pulse_detect; 36 | end 37 | end 38 | assign pulse_out = |extend_pulse; 39 | end 40 | else begin: single_pulse 41 | reg pulse_reg; 42 | always @(posedge clk or negedge reset_qual_n) begin 43 | if (!reset_qual_n) 44 | pulse_reg <= 1'b0; 45 | else 46 | pulse_reg <= pulse_detect; 47 | end 48 | assign pulse_out = pulse_reg; 49 | end 50 | endgenerate 51 | 52 | always @(posedge clk) begin 53 | if (!rst_n) 54 | state <= IDLE; 55 | else 56 | state <= next_state; 57 | end 58 | 59 | // edge detect 60 | always @(*) begin 61 | next_state = state; 62 | pulse_detect = 1'b0; 63 | case (state) 64 | IDLE : begin 65 | pulse_detect = 1'b0; 66 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 67 | else next_state = IDLE; 68 | end 69 | ARM : begin 70 | pulse_detect = 1'b0; 71 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 72 | else next_state = ARM; 73 | end 74 | CAPT : begin 75 | pulse_detect = 1'b1; 76 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 77 | else next_state = IDLE; 78 | end 79 | default : begin 80 | pulse_detect = 1'b0; 81 | next_state = IDLE; 82 | end 83 | endcase 84 | end 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/AvalonSTTB.bsv: -------------------------------------------------------------------------------- 1 | //import MMRingBuffer::*; 2 | import AvalonSTPCIe::*; 3 | import GetPut::*; 4 | import PCIE::*; 5 | 6 | interface AvalonSTTB; 7 | endinterface 8 | 9 | //typedef Bit#(64) PCIeWord; 10 | 11 | 12 | 13 | module mkAvalonSinkTB(AvalonSTTB); 14 | // MMRingBufferSink tbsink <- mkMMRingBufferSink; 15 | AvalonSinkPCIe sink <- mkAvalonSinkPCIe; 16 | Reg#(Int#(32)) tick <- mkReg(0); 17 | // MMRingBufferSource source <- mkMMRingBufferSource; 18 | 19 | /* rule print; 20 | $display("Hello world\n"); 21 | endrule 22 | */ 23 | rule ticktock; 24 | tick <= tick + 1; 25 | endrule 26 | 27 | rule sink_in; 28 | PCIeWord invalue; 29 | invalue.data = extend(pack(tick)); 30 | invalue.be = 8'hff; 31 | //invalue.parity = 0; 32 | //invalue.bar = 0; 33 | invalue.hit = 0; 34 | invalue.sof = False; 35 | invalue.eof = False; 36 | // sink.asi.asi(data, False, False, False, 8'hff, 8'h00); 37 | sink.asi.asi(invalue.data, True, invalue.sof, invalue.eof, invalue.be, 0, 0); 38 | 39 | $display("%d: Input", tick); 40 | //$display("asi_ready = %d", tbsink.sink.asi_ready()); 41 | endrule 42 | 43 | rule ready; 44 | Bool ready = sink.asi.asi_ready(); 45 | $display("%d: Ready = %d", tick, ready); 46 | endrule 47 | 48 | rule sink_out; 49 | PCIeWord out <- sink.receive.get(); 50 | $display("%d: Output %x", tick, pack(out)); 51 | endrule 52 | 53 | endmodule 54 | 55 | module mkAvalonSourceTB(AvalonSTTB); 56 | // MMRingBufferSink tbsink <- mkMMRingBufferSink; 57 | AvalonSourcePCIe source <- mkAvalonSourcePCIe; 58 | Reg#(Int#(32)) tick <- mkReg(0); 59 | // MMRingBufferSource source <- mkMMRingBufferSource; 60 | 61 | /* rule print; 62 | $display("Hello world\n"); 63 | endrule 64 | */ 65 | rule ticktock; 66 | tick <= tick + 1; 67 | endrule 68 | 69 | rule ready; 70 | source.aso.aso(True); 71 | endrule 72 | 73 | rule source_out; 74 | // sink.asi.asi(data, False, False, False, 8'hff, 8'h00); 75 | Bit#(64) dataout = source.aso.aso_data(); 76 | 77 | $display("%x: Output word %x", tick, pack(dataout)); 78 | //$display("asi_ready = %d", tbsink.sink.asi_ready()); 79 | endrule 80 | 81 | 82 | rule source_in; 83 | PCIeWord invalue; 84 | invalue.data = extend(pack(tick)); 85 | invalue.be = 8'hff; 86 | //invalue.parity = 0; 87 | //invalue.bar = 0; 88 | invalue.hit = 0; 89 | invalue.sof = False; 90 | invalue.eof = False; 91 | 92 | source.send.put(invalue); 93 | $display("%d: put %x", tick, pack(invalue)); 94 | endrule 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/PCIeByteSwap.bsv: -------------------------------------------------------------------------------- 1 | /*- 2 | * SPDX-License-Identifier: BSD-2-Clause 3 | * 4 | * Copyright (c) 2015-2018 A. Theodore Markettos 5 | * All rights reserved. 6 | * 7 | * This software was developed by SRI International and the University of 8 | * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 9 | * ("CTSRD"), as part of the DARPA CRASH research programme. 10 | * 11 | * Redistribution and use in source and binary forms, with or without 12 | * modification, are permitted provided that the following conditions 13 | * are met: 14 | * 1. Redistributions of source code must retain the above copyright 15 | * notice, this list of conditions and the following disclaimer. 16 | * 2. Redistributions in binary form must reproduce the above copyright 17 | * notice, this list of conditions and the following disclaimer in the 18 | * documentation and/or other materials provided with the distribution. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 | * SUCH DAMAGE. 31 | */ 32 | // PCIe-specifc byte swapping functions 33 | // (intended for 64 bit PCIe datapath) 34 | 35 | // note there's an internal byteSwap which only works for Bit(32) 36 | 37 | function Bit#(64) byteSwap64(Bit#(64) in); 38 | Bit#(64) out; 39 | out[7:0] = in[63:56]; 40 | out[15:8] = in[55:48]; 41 | out[23:16] = in[47:40]; 42 | out[31:24] = in[39:32]; 43 | out[39:32] = in[31:24]; 44 | out[47:40] = in[23:16]; 45 | out[55:48] = in[15:8]; 46 | out[63:56] = in[7:0]; 47 | return out; 48 | endfunction 49 | 50 | function Bit#(64) wordSwap(Bit#(64) in); 51 | Bit#(64) out; 52 | out[63:32] = in[31:0]; 53 | out[31:0] = in[63:32]; 54 | return out; 55 | endfunction 56 | 57 | function Bit#(64) byteSwap32in64(Bit#(64) in); 58 | Bit#(64) out; 59 | out[63:32] = {in[39:32], in[47:40], in[55:48], in[63:56]}; 60 | out[31:0] = {in[7:0], in[15:8], in[23:16], in[31:24]}; 61 | return out; 62 | endfunction 63 | 64 | function Bit#(64) byteSwapBottom32(Bit#(64) in); 65 | Bit#(64) out; 66 | out[63:32] = in[63:32]; 67 | out[31:0] = {in[7:0], in[15:8], in[23:16], in[31:24]}; 68 | return out; 69 | endfunction 70 | 71 | function Bit#(64) rxWord1Swap(Bit#(64) in); 72 | Bit#(64) out; 73 | out[63:32] = in[31:0]; 74 | out[31:0] = {in[39:32], in[47:40], in[55:48], in[63:56]}; 75 | return out; 76 | endfunction 77 | 78 | function Bit#(64) txWord1Swap(Bit#(64) in); 79 | Bit#(64) out; 80 | out[31:0] = in[63:32]; 81 | out[63:32] = {in[7:0], in[15:8], in[23:16], in[31:24]}; 82 | return out; 83 | endfunction 84 | 85 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/jtag.sdc: -------------------------------------------------------------------------------- 1 | # For USB BlasterII running at 24MHz or 41.666 ns period 2 | set t_period 41.666 3 | create_clock -name {altera_reserved_tck} -period $t_period [get_ports {altera_reserved_tck}] 4 | set_clock_groups -asynchronous -group {altera_reserved_tck} 5 | 6 | #Datasheet parameters from UBII IP on EPM570F100C5 7 | #TCO/TSU/TH are measured w.r.t usb_clk inside UBII IP which is used to generate TCK signal 8 | set tck_blaster_tco_max 14.603 9 | set tck_blaster_tco_min 14.603 10 | set tdi_blaster_tco_max 8.551 11 | set tdi_blaster_tco_min 8.551 12 | set tms_blaster_tco_max 9.468 13 | set tms_blaster_tco_min 9.468 14 | 15 | #In bitbang mode, TDO is sampled through MAX at FX2 16 | set tdo_blaster_tpd_max 10.718 17 | set tdo_blaster_tpd_min 10.718 18 | set fx2_pb0_trace_max 0.152 19 | set fx2_pb0_trace_min 0.152 20 | 21 | #Cable delays are from USB Blaster II 22 | #TCK 23 | set tck_cable_max 11.627 24 | set tck_cable_min 10.00 25 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 26 | set tck_header_trace_max 0.5 27 | set tck_header_trace_min 0.1 28 | 29 | #TMS 30 | set tms_cable_max 11.627 31 | set tms_cable_min 10.0 32 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 33 | set tms_header_trace_max 0.5 34 | set tms_header_trace_min 0.1 35 | 36 | #TDI 37 | set tdi_cable_max 11.627 38 | set tdi_cable_min 10.0 39 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 40 | set tdi_header_trace_max 0.5 41 | set tdi_header_trace_min 0.1 42 | 43 | #TDO 44 | set tdo_cable_max 11.627 45 | set tdo_cable_min 10.0 46 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 47 | set tdo_header_trace_max 0.5 48 | set tdo_header_trace_min 0.1 49 | 50 | derive_clock_uncertainty 51 | 52 | #TMS 53 | set tms_in_max [expr {$tms_cable_max + $tms_header_trace_max + $tms_blaster_tco_max - $tck_blaster_tco_min - $tck_cable_min - $tck_header_trace_min }] 54 | set tms_in_min [expr {$tms_cable_min + $tms_header_trace_min + $tms_blaster_tco_min - $tck_blaster_tco_max - $tck_cable_max - $tck_header_trace_max }] 55 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tms_in_max [get_ports {altera_reserved_tms}] 56 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tms_in_min [get_ports {altera_reserved_tms}] 57 | 58 | #TDI 59 | set tdi_in_max [expr {$tdi_cable_max + $tdi_header_trace_max + $tdi_blaster_tco_max - $tck_blaster_tco_min - $tck_cable_min - $tck_header_trace_min }] 60 | set tdi_in_min [expr {$tdi_cable_min + $tdi_header_trace_min + $tdi_blaster_tco_min - $tck_blaster_tco_max - $tck_cable_max - $tck_header_trace_max }] 61 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdi_in_max [get_ports {altera_reserved_tdi}] 62 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdi_in_min [get_ports {altera_reserved_tdi}] 63 | 64 | #TDO Timing in Bitbang Mode 65 | #TDO timing delays must take into account the TCK delay from the Blaster to the FPGA TCK input pin 66 | set tdo_out_max [expr {$tdo_cable_max + $tdo_header_trace_max + $tdo_blaster_tpd_max + $fx2_pb0_trace_max + $tck_blaster_tco_max + $tck_cable_max + $tck_header_trace_max }] 67 | set tdo_out_min [expr {$tdo_cable_min + $tdo_header_trace_min + $tdo_blaster_tpd_min + $fx2_pb0_trace_min + $tck_blaster_tco_min + $tck_cable_min + $tck_header_trace_min }] 68 | 69 | #TDO does not latch inside the USB Blaster II at the rising edge of TCK, it actually is passed through to the Cypress FX2 and is latched 3 FX2 cycles later (equivalent to 1.5 JTAG cycles) 70 | set_output_delay -add_delay -clock altera_reserved_tck -max $tdo_out_max [get_ports {altera_reserved_tdo}] 71 | set_output_delay -add_delay -clock altera_reserved_tck -min $tdo_out_min [get_ports {altera_reserved_tdo}] 72 | 73 | set_multicycle_path -setup -end 2 -from * -to [get_ports {altera_reserved_tdo}] 74 | 75 | 76 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Thunderclap FPGA hardware platform 2 | 3 | This repository contains the FPGA design for the [Thunderclap platform](https://thunderclap.io/), as run on two Arria 10 boards: 4 | 5 | * The Intel Arria 10 SoC Development Kit, connected to PCIe via an FMC to PCIe cable in socket FMCB. 6 | (This cable is a Samtec HDR-181157-01-PCIEC, special/made to order for about 7 | $200 in 1 off from Samtec direct) 8 | * The Enclustra Mercury AA1+ board in a PE1 carrier board (probably PE1-200 - still work in progress) 9 | 10 | Architecturally, the system consists of the hard Arm Cortex A9 CPU, with a PCI Express IP core in the FPGA logic. The IP core is connected to the Arm via simple polled pipes that deliver raw PCI Express packets (TLPs). Software reads/writes these pipes and parses the PCIe messages, and is able to generated arbitrary packets on PCIe. All this is software-defined, there is at present no acceleration for PCIe packet generation. 11 | 12 | ## Memory map: 13 | 14 | ``` 15 | HPS2FPGA bridge base: 0xC0000000 16 | 256KB SRAM: 0xC0000000 17 | PCIePacketReceiver: 0xC0040000 18 | PCIePacketTransmitter: 0xC0040400 19 | Transceiver reconfig: 0xC0044000 20 | Reconfig PLL0: 0xC0045000 21 | Reconfig PLL1: 0xC0046000 22 | JTAG UART: 0xC0047000 23 | System ID ('0x4e110') 0xC0047010 24 | 25 | Lightweight HPS2FPGA 26 | bridge base: 0xFF200000 27 | System ID (0xb0071800) 0xFF200000 28 | LED PIO 0xFF200010 29 | Button PIO 0xFF200020 30 | DIP switches 0xFF200030 31 | Reset PIO 0xFF200040 32 | Altera Interrupt 33 | Latency Counter 0xFF200100 34 | ``` 35 | 36 | ## PCIe packet pipes 37 | 38 | Each pipe is 32 bits wide and receives 64 bit data in two pieces: 39 | 40 | ``` 41 | +0x0: bits 0-31 (TX on write/RX dequeue on read) 42 | +0x4: bits 32-63 43 | +0x8: flags: 44 | bits 0-15: reserved 45 | bits 16-23: byte enables for 64 bit word 46 | bit 24: set if start of packet 47 | bit 25: set if end of packet 48 | bits 26-31: reserved 49 | +0xC: read pipe: non-zero if there is data to read 50 | write pipe: bit 0 set will send the packet 51 | ``` 52 | 53 | Offset +0x0 is read/write sensitve, ie the protocol to read a 64 bit word 54 | is to read +0x4 and subsequently +0x0. Reading 0x0 will prepare the next 55 | word for reading. 56 | 57 | Setting bit 0 of the reset PIO will force the PCIe core into reset, clearing 58 | will re-enable the PCIe core. The hard IP is hardwired to the PCIE_PERST 59 | reset line - ie it appears the PIO will only reset PCIe logic but not the 60 | transceivers. 61 | 62 | The pipe logic is written in BSV (Bluespec System Verilog), however generated Verilog sources are also provided. 63 | 64 | # Building the FPGA 65 | 66 | Assuming Intel Quartus is on your PATH (tested with versions 17.1 standard and 18.1 standard), from the top level run: 67 | 68 | ``` 69 | make intel-a10soc-devkit 70 | ``` 71 | 72 | or 73 | ``` 74 | make enclustra-mercury-aa1-pe1 75 | ``` 76 | 77 | (once the first build is run, you can also open the projects in the `boards` directory in the Quartus GUI) 78 | 79 | # Building the SD card image 80 | 81 | (scripted version still work in progress) 82 | 83 | First build your FPGA bitfile with Quartus. Then fetch and build the 84 | necessary components to generate a suitable SD card (requires sudo and 85 | Quartus's embedded tools installed): 86 | 87 | ``` 88 | sudo whoami # prompt early so we aren't interrupted 89 | export SOCEDS_DEST_ROOT=$QUARTUS_ROOTDIR/../embedded 90 | . $SOCEDS_DEST_ROOT/env.sh 91 | git clone https://github.com/thunderclap-io/thunderclap-qemu.git 92 | mkdir sdcard 93 | cd sdcard 94 | ../thunderclap-qemu/scripts/socfpga/build_ubuntu_sdcard.sh ../thunderclap-fpga-arria10 ghrd_10as066n2 95 | ``` 96 | 97 | You may need to install Ubuntu package libssl-dev to build the Linux kernel. 98 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/MEM.bsv: -------------------------------------------------------------------------------- 1 | /*- 2 | * Copyright (c) 2013 Jonathan Woodruff 3 | * Copyright (c) 2013 SRI International 4 | * All rights reserved. 5 | * 6 | * This software was developed by SRI International and the University of 7 | * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 8 | * ("CTSRD"), as part of the DARPA CRASH research programme. 9 | * 10 | * @BERI_LICENSE_HEADER_START@ 11 | * 12 | * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor 13 | * license agreements. See the NOTICE file distributed with this work for 14 | * additional information regarding copyright ownership. BERI licenses this 15 | * file to you under the BERI Hardware-Software License, Version 1.0 (the 16 | * "License"); you may not use this file except in compliance with the 17 | * License. You may obtain a copy of the License at: 18 | * 19 | * http://www.beri-open-systems.org/legal/license-1-0.txt 20 | * 21 | * Unless required by applicable law or agreed to in writing, Work distributed 22 | * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 23 | * CONDITIONS OF ANY KIND, either express or implied. See the License for the 24 | * specific language governing permissions and limitations under the License. 25 | * 26 | * @BERI_LICENSE_HEADER_END@ 27 | */ 28 | 29 | import FIFO :: *; 30 | import Vector :: *; 31 | import RegFile :: *; 32 | 33 | interface ReadIfc#(type addr, type data); 34 | method Action put(addr a); 35 | method ActionValue#(data) get(); 36 | method data peek(); 37 | endinterface 38 | 39 | interface MEM#(type addr, type data); 40 | interface ReadIfc#(addr, data) read; 41 | method Action write(addr a, data x); 42 | endinterface 43 | 44 | module mkMEM(MEM#(addr, data)) 45 | provisos(Bits#(addr, addr_sz), 46 | Bounded#(addr), 47 | Bits#(data, data_sz)); 48 | 49 | RegFile#(addr,data) regFile <- mkRegFileWCF(minBound, maxBound); // BRAM 50 | FIFO#(addr) readReq <- mkSizedFIFO(4); 51 | 52 | interface ReadIfc read; 53 | method Action put(addr a) = readReq.enq(a); 54 | method data peek() = regFile.sub(readReq.first()); 55 | method ActionValue#(data) get(); 56 | readReq.deq(); 57 | return regFile.sub(readReq.first()); 58 | endmethod 59 | endinterface 60 | method Action write(addr a, data x) = regFile.upd(a,x); 61 | endmodule 62 | 63 | 64 | typedef Bit#(8) Byte; 65 | 66 | interface MemBEVerbose#(type addr, type data, numeric type data_bytes); 67 | interface ReadIfc#(addr, data) read; 68 | method Action write(addr a, data x, Vector#(data_bytes,Bool) be); 69 | endinterface 70 | 71 | typedef MemBEVerbose#(addr,data,TDiv#(SizeOf#(data),8)) MemBE#(type addr, type data); 72 | 73 | function data fromChunks(Vector#(n,chunk) vec) 74 | provisos( 75 | Bits#(data,data_sz), 76 | Bits#(chunk,chunk_sz), 77 | Mul#(chunk_sz,n,data_sz) 78 | ); 79 | return unpack(truncate(pack(vec))); 80 | endfunction 81 | 82 | module mkMemBE(MemBE#(addr, data)) 83 | provisos( 84 | Bits#(addr, addr_sz), 85 | Bounded#(addr), 86 | Bits#(data, data_sz), 87 | Mul#(data_bytes, 8, data_sz), 88 | Div#(data_sz, 8, data_bytes) 89 | ); 90 | 91 | Vector#(data_bytes,RegFile#(addr,Byte)) 92 | regFiles <- replicateM(mkRegFileWCF(minBound, maxBound)); 93 | FIFO#(addr) readReq <- mkSizedFIFO(4); 94 | 95 | function readF(rf) = rf.sub(readReq.first); 96 | Vector#(data_bytes,Byte) readBytes = map(readF,regFiles); 97 | data readResult = fromChunks(readBytes); 98 | 99 | 100 | method Action write(addr a, data x, Vector#(data_bytes,Bool) be); 101 | Vector#(data_bytes,Byte) bytes = unpack(pack(x)); 102 | function writeF(rf, b, en) = action 103 | if (en) begin 104 | rf.upd(a,b); 105 | end 106 | endaction; 107 | let _ <- zipWith3M(writeF,regFiles,bytes,be); 108 | endmethod 109 | 110 | interface ReadIfc read; 111 | method Action put(addr a) = readReq.enq(a); 112 | method ActionValue#(data) get(); 113 | readReq.deq(); 114 | return readResult; 115 | endmethod 116 | method data peek = readResult; 117 | endinterface 118 | endmodule 119 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/AvalonSTPCIe.bsv: -------------------------------------------------------------------------------- 1 | /*- 2 | * Copyright (c) 2013 Alex Horsman 3 | * All rights reserved. 4 | * 5 | * This software was developed by SRI International and the University of 6 | * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 | * ("CTSRD"), as part of the DARPA CRASH research programme. 8 | * 9 | * @BERI_LICENSE_HEADER_START@ 10 | * 11 | * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor 12 | * license agreements. See the NOTICE file distributed with this work for 13 | * additional information regarding copyright ownership. BERI licenses this 14 | * file to you under the BERI Hardware-Software License, Version 1.0 (the 15 | * "License"); you may not use this file except in compliance with the 16 | * License. You may obtain a copy of the License at: 17 | * 18 | * http://www.beri-open-systems.org/legal/license-1-0.txt 19 | * 20 | * Unless required by applicable law or agreed to in writing, Work distributed 21 | * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 22 | * CONDITIONS OF ANY KIND, either express or implied. See the License for the 23 | * specific language governing permissions and limitations under the License. 24 | * 25 | * @BERI_LICENSE_HEADER_END@ 26 | */ 27 | 28 | package AvalonSTPCIe; 29 | 30 | import GetPut::*; 31 | import FIFOF::*; 32 | import PCIE::*; 33 | 34 | /* 35 | typedef struct { 36 | Bit#(8) be; 37 | Bit#(8) parity; 38 | Bit#(8) bar; 39 | Bool sop; 40 | Bool eop; 41 | Bit#(64) data; 42 | // Bit#(22) pad; 43 | } PCIeWord deriving (Bits, Eq); 44 | */ 45 | 46 | typedef TLPData#(8) PCIeWord; 47 | 48 | 49 | (* always_ready, always_enabled *) 50 | interface AvalonSourceExtPCIe; 51 | method Action aso(Bool ready); 52 | method Bit#(64) aso_data; 53 | method Bool aso_valid; 54 | method Bool aso_sop; 55 | method Bool aso_eop; 56 | method Bit#(8) aso_be; 57 | method Bit#(8) aso_parity; 58 | method Bit#(8) aso_bar; 59 | method Bool aso_err; 60 | endinterface 61 | 62 | interface AvalonSourcePCIe; 63 | interface AvalonSourceExtPCIe aso; 64 | interface Put#(PCIeWord) send; 65 | endinterface 66 | 67 | 68 | module mkAvalonSourcePCIe(AvalonSourcePCIe); 69 | //provisos(Bits#(PCIeWord,dataWidth)); 70 | 71 | Wire#(Maybe#(PCIeWord)) data <- mkDWire(Invalid); 72 | PulseWire isReady <- mkPulseWire; 73 | 74 | interface AvalonSourceExtPCIe aso; 75 | method Action aso(ready); 76 | if (ready) begin 77 | isReady.send(); 78 | end 79 | endmethod 80 | 81 | method aso_data = fromMaybe(?,data).data; 82 | method aso_valid = isValid(data); 83 | method aso_sop = fromMaybe(?,data).sof; 84 | method aso_eop = fromMaybe(?,data).eof; 85 | method aso_bar = 0; //fromMaybe(?,data).bar; 86 | method aso_be = fromMaybe(?,data).be; 87 | method aso_parity = 0; //fromMaybe(?,data).parity; 88 | method aso_err = False; 89 | endinterface 90 | 91 | interface Put send; 92 | method Action put(x) if (isReady); 93 | data <= Valid(x); 94 | endmethod 95 | endinterface 96 | 97 | endmodule 98 | 99 | 100 | (* always_ready, always_enabled *) 101 | interface AvalonSinkExtPCIe; 102 | method Action asi(Bit#(64) data, Bool valid, Bool sop, Bool eop, Bit#(8) be, Bit#(8) parity, Bit#(8) bar); 103 | method Bool asi_ready; 104 | endinterface 105 | 106 | interface AvalonSinkPCIe; 107 | interface AvalonSinkExtPCIe asi; 108 | interface Get#(PCIeWord) receive; 109 | endinterface 110 | 111 | 112 | module mkAvalonSinkPCIe(AvalonSinkPCIe); 113 | //provisos(Bits#(dataT,dataWidth)); 114 | 115 | FIFOF#(PCIeWord) queue <- mkGLFIFOF(True,False); 116 | 117 | interface AvalonSinkExtPCIe asi; 118 | method Action asi(data,valid,sop,eop,be,parity,bar); 119 | if (valid && queue.notFull) begin 120 | PCIeWord tfr; 121 | tfr.data = data; 122 | tfr.sof = sop; 123 | tfr.eof = eop; 124 | tfr.be = be; 125 | //tfr.parity = parity; 126 | //tfr.bar = bar; 127 | tfr.hit = 0; // unused Xilinx-ism 128 | queue.enq(tfr); 129 | end 130 | endmethod 131 | method asi_ready = queue.notFull; 132 | endinterface 133 | 134 | interface receive = toGet(queue); 135 | 136 | endmodule 137 | 138 | 139 | endpackage 140 | -------------------------------------------------------------------------------- /lib/FIFOL1.v: -------------------------------------------------------------------------------- 1 | 2 | // Copyright (c) 2000-2012 Bluespec, Inc. 3 | 4 | // Permission is hereby granted, free of charge, to any person obtaining a copy 5 | // of this software and associated documentation files (the "Software"), to deal 6 | // in the Software without restriction, including without limitation the rights 7 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | // copies of the Software, and to permit persons to whom the Software is 9 | // furnished to do so, subject to the following conditions: 10 | 11 | // The above copyright notice and this permission notice shall be included in 12 | // all copies or substantial portions of the Software. 13 | 14 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | // THE SOFTWARE. 21 | // 22 | // $Revision$ 23 | // $Date$ 24 | 25 | `ifdef BSV_ASSIGNMENT_DELAY 26 | `else 27 | `define BSV_ASSIGNMENT_DELAY 28 | `endif 29 | 30 | `ifdef BSV_POSITIVE_RESET 31 | `define BSV_RESET_VALUE 1'b1 32 | `define BSV_RESET_EDGE posedge 33 | `else 34 | `define BSV_RESET_VALUE 1'b0 35 | `define BSV_RESET_EDGE negedge 36 | `endif 37 | 38 | `ifdef BSV_ASYNC_RESET 39 | `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST 40 | `else 41 | `define BSV_ARESET_EDGE_META 42 | `endif 43 | 44 | `ifdef BSV_RESET_FIFO_HEAD 45 | `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META 46 | `else 47 | `define BSV_ARESET_EDGE_HEAD 48 | `endif 49 | 50 | // Depth 1 FIFO 51 | // Allows simultaneous ENQ and DEQ (at the expense of potentially 52 | // causing combinational loops). 53 | module FIFOL1(CLK, 54 | RST, 55 | D_IN, 56 | ENQ, 57 | FULL_N, 58 | D_OUT, 59 | DEQ, 60 | EMPTY_N, 61 | CLR); 62 | 63 | parameter width = 1; 64 | 65 | input CLK; 66 | input RST; 67 | 68 | input [width - 1 : 0] D_IN; 69 | input ENQ; 70 | input DEQ; 71 | input CLR ; 72 | 73 | output FULL_N; 74 | output EMPTY_N; 75 | output [width - 1 : 0] D_OUT; 76 | 77 | 78 | 79 | reg empty_reg ; 80 | reg [width - 1 : 0] D_OUT; 81 | 82 | `ifdef BSV_NO_INITIAL_BLOCKS 83 | `else // not BSV_NO_INITIAL_BLOCKS 84 | // synopsys translate_off 85 | initial 86 | begin 87 | D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ; 88 | empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; 89 | end // initial begin 90 | // synopsys translate_on 91 | `endif // BSV_NO_INITIAL_BLOCKS 92 | 93 | 94 | assign FULL_N = !empty_reg || DEQ; 95 | assign EMPTY_N = empty_reg ; 96 | 97 | always@(posedge CLK `BSV_ARESET_EDGE_META) 98 | begin 99 | if (RST == `BSV_RESET_VALUE) 100 | begin 101 | empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; 102 | end 103 | else 104 | begin 105 | if (CLR) 106 | begin 107 | empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; 108 | end 109 | else if (ENQ) 110 | begin 111 | empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; 112 | end 113 | else if (DEQ) 114 | begin 115 | empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; 116 | end // if (DEQ) 117 | end // else: !if(RST == `BSV_RESET_VALUE) 118 | end // always@ (posedge CLK or `BSV_RESET_EDGE RST) 119 | 120 | always@(posedge CLK `BSV_ARESET_EDGE_HEAD) 121 | begin 122 | `ifdef BSV_RESET_FIFO_HEAD 123 | if (RST == `BSV_RESET_VALUE) 124 | begin 125 | D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ; 126 | end 127 | else 128 | `endif 129 | begin 130 | if (ENQ) 131 | D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; 132 | end // else: !if(RST == `BSV_RESET_VALUE) 133 | end // always@ (posedge CLK or `BSV_RESET_EDGE RST) 134 | 135 | // synopsys translate_off 136 | always@(posedge CLK) 137 | begin: error_checks 138 | reg deqerror, enqerror ; 139 | 140 | deqerror = 0; 141 | enqerror = 0; 142 | if ( ! empty_reg && DEQ ) 143 | begin 144 | deqerror = 1 ; 145 | $display( "Warning: FIFOL1: %m -- Dequeuing from empty fifo" ) ; 146 | end 147 | if ( ! FULL_N && ENQ && ! DEQ) 148 | begin 149 | enqerror = 1 ; 150 | $display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ; 151 | end 152 | end 153 | // synopsys translate_on 154 | 155 | endmodule 156 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/hps_a10_common_board_info.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 7 | 8 | altr,socfpga-arria10 9 | altr,socfpga 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 1 18 | 1 19 | 1 20 | 21 | 22 | 2 23 | 1 24 | 1 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 0 34 | 176 35 | 4 36 | 0 37 | 177 38 | 4 39 | 40 | 41 | 42 | 43 | 44 | 45 | 0xff118000 46 | 0x1000 47 | 48 | 49 | 50 | 51 | 52 | 0xff119000 53 | 0x1000 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | arria10_hps_0_i_rst_mgr_rstmgr 66 | 32 67 | 68 | 69 | 70 | 71 | 72 | arria10_hps_0_i_rst_mgr_rstmgr 73 | 33 74 | 75 | 76 | 77 | 78 | 79 | arria10_hps_0_i_rst_mgr_rstmgr 80 | 34 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | arria10_hps_0_i_sys_mgr_core 90 | 0x44 91 | 0 92 | 93 | 94 | 95 | arria10_hps_0_i_sys_mgr_core 96 | 0x48 97 | 0 98 | 99 | 100 | 101 | arria10_hps_0_i_sys_mgr_core 102 | 0x4c 103 | 0 104 | 105 | 106 | 107 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/PCIePacketTransmitter_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 17.1 2 | # Wed Jun 13 16:12:06 BST 2018 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # PCIePacketTransmitter "PCIePacketTransmitter" v1.1 8 | # 2018.06.13.16:12:06 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 16.1 14 | # 15 | package require -exact qsys 16.1 16 | 17 | 18 | # 19 | # module PCIePacketTransmitter 20 | # 21 | set_module_property DESCRIPTION "" 22 | set_module_property NAME PCIePacketTransmitter 23 | set_module_property VERSION 1.1 24 | set_module_property INTERNAL false 25 | set_module_property OPAQUE_ADDRESS_MAP true 26 | set_module_property AUTHOR "" 27 | set_module_property DISPLAY_NAME PCIePacketTransmitter 28 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 29 | set_module_property EDITABLE true 30 | set_module_property REPORT_TO_TALKBACK false 31 | set_module_property ALLOW_GREYBOX_GENERATION false 32 | set_module_property REPORT_HIERARCHY false 33 | 34 | 35 | # 36 | # file sets 37 | # 38 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 39 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mkPCIePacketTransmitter 40 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 41 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 42 | add_fileset_file mkPCIePacketTransmitter.v VERILOG PATH mkPCIePacketTransmitter.v TOP_LEVEL_FILE 43 | 44 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 45 | set_fileset_property SIM_VERILOG TOP_LEVEL mkPCIePacketTransmitter 46 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 47 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 48 | add_fileset_file mkPCIePacketTransmitter.v VERILOG PATH mkPCIePacketTransmitter.v 49 | 50 | 51 | # 52 | # parameters 53 | # 54 | 55 | 56 | # 57 | # display items 58 | # 59 | 60 | 61 | # 62 | # connection point clock 63 | # 64 | add_interface clock clock end 65 | set_interface_property clock clockRate 0 66 | set_interface_property clock ENABLED true 67 | set_interface_property clock EXPORT_OF "" 68 | set_interface_property clock PORT_NAME_MAP "" 69 | set_interface_property clock CMSIS_SVD_VARIABLES "" 70 | set_interface_property clock SVD_ADDRESS_GROUP "" 71 | 72 | add_interface_port clock CLK clk Input 1 73 | 74 | 75 | # 76 | # connection point mmslave_avs 77 | # 78 | add_interface mmslave_avs avalon end 79 | set_interface_property mmslave_avs addressUnits WORDS 80 | set_interface_property mmslave_avs associatedClock clock 81 | set_interface_property mmslave_avs associatedReset reset_sink 82 | set_interface_property mmslave_avs bitsPerSymbol 8 83 | set_interface_property mmslave_avs burstOnBurstBoundariesOnly false 84 | set_interface_property mmslave_avs burstcountUnits WORDS 85 | set_interface_property mmslave_avs explicitAddressSpan 0 86 | set_interface_property mmslave_avs holdTime 0 87 | set_interface_property mmslave_avs linewrapBursts false 88 | set_interface_property mmslave_avs maximumPendingReadTransactions 0 89 | set_interface_property mmslave_avs maximumPendingWriteTransactions 0 90 | set_interface_property mmslave_avs readLatency 0 91 | set_interface_property mmslave_avs readWaitTime 1 92 | set_interface_property mmslave_avs setupTime 0 93 | set_interface_property mmslave_avs timingUnits Cycles 94 | set_interface_property mmslave_avs writeWaitTime 0 95 | set_interface_property mmslave_avs ENABLED true 96 | set_interface_property mmslave_avs EXPORT_OF "" 97 | set_interface_property mmslave_avs PORT_NAME_MAP "" 98 | set_interface_property mmslave_avs CMSIS_SVD_VARIABLES "" 99 | set_interface_property mmslave_avs SVD_ADDRESS_GROUP "" 100 | 101 | add_interface_port mmslave_avs mmSlave_avs_waitrequest waitrequest Output 1 102 | add_interface_port mmslave_avs mmSlave_avs_writedata writedata Input 64 103 | add_interface_port mmslave_avs mmSlave_avs_address address Input 8 104 | add_interface_port mmslave_avs mmSlave_avs_read read Input 1 105 | add_interface_port mmslave_avs mmSlave_avs_write write Input 1 106 | add_interface_port mmslave_avs mmSlave_avs_byteenable byteenable Input 8 107 | add_interface_port mmslave_avs mmSlave_avs_readdata readdata Output 64 108 | set_interface_assignment mmslave_avs embeddedsw.configuration.isFlash 0 109 | set_interface_assignment mmslave_avs embeddedsw.configuration.isMemoryDevice 0 110 | set_interface_assignment mmslave_avs embeddedsw.configuration.isNonVolatileStorage 0 111 | set_interface_assignment mmslave_avs embeddedsw.configuration.isPrintableDevice 0 112 | 113 | 114 | # 115 | # connection point reset_sink 116 | # 117 | add_interface reset_sink reset end 118 | set_interface_property reset_sink associatedClock clock 119 | set_interface_property reset_sink synchronousEdges DEASSERT 120 | set_interface_property reset_sink ENABLED true 121 | set_interface_property reset_sink EXPORT_OF "" 122 | set_interface_property reset_sink PORT_NAME_MAP "" 123 | set_interface_property reset_sink CMSIS_SVD_VARIABLES "" 124 | set_interface_property reset_sink SVD_ADDRESS_GROUP "" 125 | 126 | add_interface_port reset_sink RST_N reset_n Input 1 127 | 128 | 129 | # 130 | # connection point avalon_streaming_source 131 | # 132 | add_interface avalon_streaming_source avalon_streaming start 133 | set_interface_property avalon_streaming_source associatedClock clock 134 | set_interface_property avalon_streaming_source associatedReset reset_sink 135 | set_interface_property avalon_streaming_source dataBitsPerSymbol 64 136 | set_interface_property avalon_streaming_source errorDescriptor "" 137 | set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true 138 | set_interface_property avalon_streaming_source maxChannel 0 139 | set_interface_property avalon_streaming_source readyLatency 0 140 | set_interface_property avalon_streaming_source ENABLED true 141 | set_interface_property avalon_streaming_source EXPORT_OF "" 142 | set_interface_property avalon_streaming_source PORT_NAME_MAP "" 143 | set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES "" 144 | set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP "" 145 | 146 | add_interface_port avalon_streaming_source streamSource_aso_data data Output 64 147 | add_interface_port avalon_streaming_source streamSource_aso_valid valid Output 1 148 | add_interface_port avalon_streaming_source streamSource_aso_sop startofpacket Output 1 149 | add_interface_port avalon_streaming_source streamSource_aso_eop endofpacket Output 1 150 | add_interface_port avalon_streaming_source streamSource_aso_err error Output 1 151 | add_interface_port avalon_streaming_source streamSource_aso_ready ready Input 1 152 | 153 | 154 | # 155 | # connection point conduit_end 156 | # 157 | add_interface conduit_end conduit end 158 | set_interface_property conduit_end associatedClock clock 159 | set_interface_property conduit_end associatedReset "" 160 | set_interface_property conduit_end ENABLED true 161 | set_interface_property conduit_end EXPORT_OF "" 162 | set_interface_property conduit_end PORT_NAME_MAP "" 163 | set_interface_property conduit_end CMSIS_SVD_VARIABLES "" 164 | set_interface_property conduit_end SVD_ADDRESS_GROUP "" 165 | 166 | add_interface_port conduit_end streamSource_aso_be be Output 8 167 | add_interface_port conduit_end streamSource_aso_parity parity Output 8 168 | add_interface_port conduit_end streamSource_aso_bar bar Output 8 169 | 170 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/qsys_ip/PCIePipes/PCIePacketTransmitter_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 17.1 2 | # Wed Jun 13 16:12:06 BST 2018 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # PCIePacketTransmitter "PCIePacketTransmitter" v1.1 8 | # 2018.06.13.16:12:06 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 16.1 14 | # 15 | package require -exact qsys 16.1 16 | 17 | 18 | # 19 | # module PCIePacketTransmitter 20 | # 21 | set_module_property DESCRIPTION "" 22 | set_module_property NAME PCIePacketTransmitter 23 | set_module_property VERSION 1.1 24 | set_module_property INTERNAL false 25 | set_module_property OPAQUE_ADDRESS_MAP true 26 | set_module_property AUTHOR "" 27 | set_module_property DISPLAY_NAME PCIePacketTransmitter 28 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 29 | set_module_property EDITABLE true 30 | set_module_property REPORT_TO_TALKBACK false 31 | set_module_property ALLOW_GREYBOX_GENERATION false 32 | set_module_property REPORT_HIERARCHY false 33 | 34 | 35 | # 36 | # file sets 37 | # 38 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 39 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mkPCIePacketTransmitter 40 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 41 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 42 | add_fileset_file mkPCIePacketTransmitter.v VERILOG PATH mkPCIePacketTransmitter.v TOP_LEVEL_FILE 43 | 44 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 45 | set_fileset_property SIM_VERILOG TOP_LEVEL mkPCIePacketTransmitter 46 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 47 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 48 | add_fileset_file mkPCIePacketTransmitter.v VERILOG PATH mkPCIePacketTransmitter.v 49 | 50 | 51 | # 52 | # parameters 53 | # 54 | 55 | 56 | # 57 | # display items 58 | # 59 | 60 | 61 | # 62 | # connection point clock 63 | # 64 | add_interface clock clock end 65 | set_interface_property clock clockRate 0 66 | set_interface_property clock ENABLED true 67 | set_interface_property clock EXPORT_OF "" 68 | set_interface_property clock PORT_NAME_MAP "" 69 | set_interface_property clock CMSIS_SVD_VARIABLES "" 70 | set_interface_property clock SVD_ADDRESS_GROUP "" 71 | 72 | add_interface_port clock CLK clk Input 1 73 | 74 | 75 | # 76 | # connection point mmslave_avs 77 | # 78 | add_interface mmslave_avs avalon end 79 | set_interface_property mmslave_avs addressUnits WORDS 80 | set_interface_property mmslave_avs associatedClock clock 81 | set_interface_property mmslave_avs associatedReset reset_sink 82 | set_interface_property mmslave_avs bitsPerSymbol 8 83 | set_interface_property mmslave_avs burstOnBurstBoundariesOnly false 84 | set_interface_property mmslave_avs burstcountUnits WORDS 85 | set_interface_property mmslave_avs explicitAddressSpan 0 86 | set_interface_property mmslave_avs holdTime 0 87 | set_interface_property mmslave_avs linewrapBursts false 88 | set_interface_property mmslave_avs maximumPendingReadTransactions 0 89 | set_interface_property mmslave_avs maximumPendingWriteTransactions 0 90 | set_interface_property mmslave_avs readLatency 0 91 | set_interface_property mmslave_avs readWaitTime 1 92 | set_interface_property mmslave_avs setupTime 0 93 | set_interface_property mmslave_avs timingUnits Cycles 94 | set_interface_property mmslave_avs writeWaitTime 0 95 | set_interface_property mmslave_avs ENABLED true 96 | set_interface_property mmslave_avs EXPORT_OF "" 97 | set_interface_property mmslave_avs PORT_NAME_MAP "" 98 | set_interface_property mmslave_avs CMSIS_SVD_VARIABLES "" 99 | set_interface_property mmslave_avs SVD_ADDRESS_GROUP "" 100 | 101 | add_interface_port mmslave_avs mmSlave_avs_waitrequest waitrequest Output 1 102 | add_interface_port mmslave_avs mmSlave_avs_writedata writedata Input 64 103 | add_interface_port mmslave_avs mmSlave_avs_address address Input 8 104 | add_interface_port mmslave_avs mmSlave_avs_read read Input 1 105 | add_interface_port mmslave_avs mmSlave_avs_write write Input 1 106 | add_interface_port mmslave_avs mmSlave_avs_byteenable byteenable Input 8 107 | add_interface_port mmslave_avs mmSlave_avs_readdata readdata Output 64 108 | set_interface_assignment mmslave_avs embeddedsw.configuration.isFlash 0 109 | set_interface_assignment mmslave_avs embeddedsw.configuration.isMemoryDevice 0 110 | set_interface_assignment mmslave_avs embeddedsw.configuration.isNonVolatileStorage 0 111 | set_interface_assignment mmslave_avs embeddedsw.configuration.isPrintableDevice 0 112 | 113 | 114 | # 115 | # connection point reset_sink 116 | # 117 | add_interface reset_sink reset end 118 | set_interface_property reset_sink associatedClock clock 119 | set_interface_property reset_sink synchronousEdges DEASSERT 120 | set_interface_property reset_sink ENABLED true 121 | set_interface_property reset_sink EXPORT_OF "" 122 | set_interface_property reset_sink PORT_NAME_MAP "" 123 | set_interface_property reset_sink CMSIS_SVD_VARIABLES "" 124 | set_interface_property reset_sink SVD_ADDRESS_GROUP "" 125 | 126 | add_interface_port reset_sink RST_N reset_n Input 1 127 | 128 | 129 | # 130 | # connection point avalon_streaming_source 131 | # 132 | add_interface avalon_streaming_source avalon_streaming start 133 | set_interface_property avalon_streaming_source associatedClock clock 134 | set_interface_property avalon_streaming_source associatedReset reset_sink 135 | set_interface_property avalon_streaming_source dataBitsPerSymbol 64 136 | set_interface_property avalon_streaming_source errorDescriptor "" 137 | set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true 138 | set_interface_property avalon_streaming_source maxChannel 0 139 | set_interface_property avalon_streaming_source readyLatency 0 140 | set_interface_property avalon_streaming_source ENABLED true 141 | set_interface_property avalon_streaming_source EXPORT_OF "" 142 | set_interface_property avalon_streaming_source PORT_NAME_MAP "" 143 | set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES "" 144 | set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP "" 145 | 146 | add_interface_port avalon_streaming_source streamSource_aso_data data Output 64 147 | add_interface_port avalon_streaming_source streamSource_aso_valid valid Output 1 148 | add_interface_port avalon_streaming_source streamSource_aso_sop startofpacket Output 1 149 | add_interface_port avalon_streaming_source streamSource_aso_eop endofpacket Output 1 150 | add_interface_port avalon_streaming_source streamSource_aso_err error Output 1 151 | add_interface_port avalon_streaming_source streamSource_aso_ready ready Input 1 152 | 153 | 154 | # 155 | # connection point conduit_end 156 | # 157 | add_interface conduit_end conduit end 158 | set_interface_property conduit_end associatedClock clock 159 | set_interface_property conduit_end associatedReset "" 160 | set_interface_property conduit_end ENABLED true 161 | set_interface_property conduit_end EXPORT_OF "" 162 | set_interface_property conduit_end PORT_NAME_MAP "" 163 | set_interface_property conduit_end CMSIS_SVD_VARIABLES "" 164 | set_interface_property conduit_end SVD_ADDRESS_GROUP "" 165 | 166 | add_interface_port conduit_end streamSource_aso_be be Output 8 167 | add_interface_port conduit_end streamSource_aso_parity parity Output 8 168 | add_interface_port conduit_end streamSource_aso_bar bar Output 8 169 | 170 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/PCIePacketReceiver_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 15.1 2 | # Thu May 05 17:24:02 BST 2016 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # PCIePacketReceiver "PCIePacketReceiver" v1.0 8 | # 2016.05.05.17:24:02 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 15.1 14 | # 15 | package require -exact qsys 15.1 16 | 17 | 18 | # 19 | # module PCIePacketReceiver 20 | # 21 | set_module_property DESCRIPTION "" 22 | set_module_property NAME PCIePacketReceiver 23 | set_module_property VERSION 1.0 24 | set_module_property INTERNAL false 25 | set_module_property OPAQUE_ADDRESS_MAP true 26 | set_module_property AUTHOR "" 27 | set_module_property DISPLAY_NAME PCIePacketReceiver 28 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 29 | set_module_property EDITABLE true 30 | set_module_property REPORT_TO_TALKBACK false 31 | set_module_property ALLOW_GREYBOX_GENERATION false 32 | set_module_property REPORT_HIERARCHY false 33 | 34 | 35 | # 36 | # file sets 37 | # 38 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 39 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mkPCIePacketReceiver 40 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 41 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 42 | add_fileset_file mkPCIePacketReceiver.v VERILOG PATH mkPCIePacketReceiver.v TOP_LEVEL_FILE 43 | 44 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 45 | set_fileset_property SIM_VERILOG TOP_LEVEL mkPCIePacketReceiver 46 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 47 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true 48 | add_fileset_file mkPCIePacketReceiver.v VERILOG PATH mkPCIePacketReceiver.v 49 | 50 | 51 | # 52 | # parameters 53 | # 54 | 55 | 56 | # 57 | # display items 58 | # 59 | 60 | 61 | # 62 | # connection point clock 63 | # 64 | add_interface clock clock end 65 | set_interface_property clock clockRate 0 66 | set_interface_property clock ENABLED true 67 | set_interface_property clock EXPORT_OF "" 68 | set_interface_property clock PORT_NAME_MAP "" 69 | set_interface_property clock CMSIS_SVD_VARIABLES "" 70 | set_interface_property clock SVD_ADDRESS_GROUP "" 71 | 72 | add_interface_port clock CLK clk Input 1 73 | 74 | 75 | # 76 | # connection point mmslave_avs 77 | # 78 | add_interface mmslave_avs avalon end 79 | set_interface_property mmslave_avs addressUnits WORDS 80 | set_interface_property mmslave_avs associatedClock clock 81 | set_interface_property mmslave_avs associatedReset reset_sink 82 | set_interface_property mmslave_avs bitsPerSymbol 8 83 | set_interface_property mmslave_avs burstOnBurstBoundariesOnly false 84 | set_interface_property mmslave_avs burstcountUnits WORDS 85 | set_interface_property mmslave_avs explicitAddressSpan 0 86 | set_interface_property mmslave_avs holdTime 0 87 | set_interface_property mmslave_avs linewrapBursts false 88 | set_interface_property mmslave_avs maximumPendingReadTransactions 1 89 | set_interface_property mmslave_avs maximumPendingWriteTransactions 0 90 | set_interface_property mmslave_avs readLatency 0 91 | set_interface_property mmslave_avs readWaitTime 1 92 | set_interface_property mmslave_avs setupTime 0 93 | set_interface_property mmslave_avs timingUnits Cycles 94 | set_interface_property mmslave_avs writeWaitTime 0 95 | set_interface_property mmslave_avs ENABLED true 96 | set_interface_property mmslave_avs EXPORT_OF "" 97 | set_interface_property mmslave_avs PORT_NAME_MAP "" 98 | set_interface_property mmslave_avs CMSIS_SVD_VARIABLES "" 99 | set_interface_property mmslave_avs SVD_ADDRESS_GROUP "" 100 | 101 | add_interface_port mmslave_avs mmSlave_avs_readdata readdata Output 64 102 | add_interface_port mmslave_avs mmSlave_avs_readdatavalid readdatavalid Output 1 103 | add_interface_port mmslave_avs mmSlave_avs_waitrequest waitrequest Output 1 104 | add_interface_port mmslave_avs mmSlave_avs_writedata writedata Input 64 105 | add_interface_port mmslave_avs mmSlave_avs_address address Input 8 106 | add_interface_port mmslave_avs mmSlave_avs_read read Input 1 107 | add_interface_port mmslave_avs mmSlave_avs_write write Input 1 108 | add_interface_port mmslave_avs mmSlave_avs_byteenable byteenable Input 8 109 | set_interface_assignment mmslave_avs embeddedsw.configuration.isFlash 0 110 | set_interface_assignment mmslave_avs embeddedsw.configuration.isMemoryDevice 0 111 | set_interface_assignment mmslave_avs embeddedsw.configuration.isNonVolatileStorage 0 112 | set_interface_assignment mmslave_avs embeddedsw.configuration.isPrintableDevice 0 113 | 114 | 115 | # 116 | # connection point reset_sink 117 | # 118 | add_interface reset_sink reset end 119 | set_interface_property reset_sink associatedClock clock 120 | set_interface_property reset_sink synchronousEdges DEASSERT 121 | set_interface_property reset_sink ENABLED true 122 | set_interface_property reset_sink EXPORT_OF "" 123 | set_interface_property reset_sink PORT_NAME_MAP "" 124 | set_interface_property reset_sink CMSIS_SVD_VARIABLES "" 125 | set_interface_property reset_sink SVD_ADDRESS_GROUP "" 126 | 127 | add_interface_port reset_sink RST_N reset_n Input 1 128 | 129 | 130 | # 131 | # connection point avalon_streaming_sink 132 | # 133 | add_interface avalon_streaming_sink avalon_streaming end 134 | set_interface_property avalon_streaming_sink associatedClock clock 135 | set_interface_property avalon_streaming_sink associatedReset reset_sink 136 | set_interface_property avalon_streaming_sink dataBitsPerSymbol 64 137 | set_interface_property avalon_streaming_sink errorDescriptor "" 138 | set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true 139 | set_interface_property avalon_streaming_sink maxChannel 0 140 | set_interface_property avalon_streaming_sink readyLatency 0 141 | set_interface_property avalon_streaming_sink ENABLED true 142 | set_interface_property avalon_streaming_sink EXPORT_OF "" 143 | set_interface_property avalon_streaming_sink PORT_NAME_MAP "" 144 | set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES "" 145 | set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP "" 146 | 147 | add_interface_port avalon_streaming_sink streamSink_asi_data data Input 64 148 | add_interface_port avalon_streaming_sink streamSink_asi_valid valid Input 1 149 | add_interface_port avalon_streaming_sink streamSink_asi_eop endofpacket Input 1 150 | add_interface_port avalon_streaming_sink streamSink_asi_sop startofpacket Input 1 151 | add_interface_port avalon_streaming_sink streamSink_asi_ready ready Output 1 152 | 153 | 154 | # 155 | # connection point conduit_bar 156 | # 157 | add_interface conduit_bar conduit end 158 | set_interface_property conduit_bar associatedClock clock 159 | set_interface_property conduit_bar associatedReset reset_sink 160 | set_interface_property conduit_bar ENABLED true 161 | set_interface_property conduit_bar EXPORT_OF "" 162 | set_interface_property conduit_bar PORT_NAME_MAP "" 163 | set_interface_property conduit_bar CMSIS_SVD_VARIABLES "" 164 | set_interface_property conduit_bar SVD_ADDRESS_GROUP "" 165 | 166 | add_interface_port conduit_bar streamSink_asi_bar bar Input 8 167 | 168 | 169 | # 170 | # connection point conduit_be 171 | # 172 | add_interface conduit_be conduit end 173 | set_interface_property conduit_be associatedClock clock 174 | set_interface_property conduit_be associatedReset reset_sink 175 | set_interface_property conduit_be ENABLED true 176 | set_interface_property conduit_be EXPORT_OF "" 177 | set_interface_property conduit_be PORT_NAME_MAP "" 178 | set_interface_property conduit_be CMSIS_SVD_VARIABLES "" 179 | set_interface_property conduit_be SVD_ADDRESS_GROUP "" 180 | 181 | add_interface_port conduit_be streamSink_asi_be be Input 8 182 | 183 | 184 | # 185 | # connection point conduit_parity 186 | # 187 | add_interface conduit_parity conduit end 188 | set_interface_property conduit_parity associatedClock clock 189 | set_interface_property conduit_parity associatedReset reset_sink 190 | set_interface_property conduit_parity ENABLED true 191 | set_interface_property conduit_parity EXPORT_OF "" 192 | set_interface_property conduit_parity PORT_NAME_MAP "" 193 | set_interface_property conduit_parity CMSIS_SVD_VARIABLES "" 194 | set_interface_property conduit_parity SVD_ADDRESS_GROUP "" 195 | 196 | add_interface_port conduit_parity streamSink_asi_parity parity Input 8 197 | 198 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/qsys_ip/PCIePipes/PCIePacketReceiver_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 15.1 2 | # Thu May 05 17:24:02 BST 2016 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # PCIePacketReceiver "PCIePacketReceiver" v1.0 8 | # 2016.05.05.17:24:02 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 15.1 14 | # 15 | package require -exact qsys 15.1 16 | 17 | 18 | # 19 | # module PCIePacketReceiver 20 | # 21 | set_module_property DESCRIPTION "" 22 | set_module_property NAME PCIePacketReceiver 23 | set_module_property VERSION 1.0 24 | set_module_property INTERNAL false 25 | set_module_property OPAQUE_ADDRESS_MAP true 26 | set_module_property AUTHOR "" 27 | set_module_property DISPLAY_NAME PCIePacketReceiver 28 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 29 | set_module_property EDITABLE true 30 | set_module_property REPORT_TO_TALKBACK false 31 | set_module_property ALLOW_GREYBOX_GENERATION false 32 | set_module_property REPORT_HIERARCHY false 33 | 34 | 35 | # 36 | # file sets 37 | # 38 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 39 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mkPCIePacketReceiver 40 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 41 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 42 | add_fileset_file mkPCIePacketReceiver.v VERILOG PATH mkPCIePacketReceiver.v TOP_LEVEL_FILE 43 | 44 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 45 | set_fileset_property SIM_VERILOG TOP_LEVEL mkPCIePacketReceiver 46 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 47 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true 48 | add_fileset_file mkPCIePacketReceiver.v VERILOG PATH mkPCIePacketReceiver.v 49 | 50 | 51 | # 52 | # parameters 53 | # 54 | 55 | 56 | # 57 | # display items 58 | # 59 | 60 | 61 | # 62 | # connection point clock 63 | # 64 | add_interface clock clock end 65 | set_interface_property clock clockRate 0 66 | set_interface_property clock ENABLED true 67 | set_interface_property clock EXPORT_OF "" 68 | set_interface_property clock PORT_NAME_MAP "" 69 | set_interface_property clock CMSIS_SVD_VARIABLES "" 70 | set_interface_property clock SVD_ADDRESS_GROUP "" 71 | 72 | add_interface_port clock CLK clk Input 1 73 | 74 | 75 | # 76 | # connection point mmslave_avs 77 | # 78 | add_interface mmslave_avs avalon end 79 | set_interface_property mmslave_avs addressUnits WORDS 80 | set_interface_property mmslave_avs associatedClock clock 81 | set_interface_property mmslave_avs associatedReset reset_sink 82 | set_interface_property mmslave_avs bitsPerSymbol 8 83 | set_interface_property mmslave_avs burstOnBurstBoundariesOnly false 84 | set_interface_property mmslave_avs burstcountUnits WORDS 85 | set_interface_property mmslave_avs explicitAddressSpan 0 86 | set_interface_property mmslave_avs holdTime 0 87 | set_interface_property mmslave_avs linewrapBursts false 88 | set_interface_property mmslave_avs maximumPendingReadTransactions 1 89 | set_interface_property mmslave_avs maximumPendingWriteTransactions 0 90 | set_interface_property mmslave_avs readLatency 0 91 | set_interface_property mmslave_avs readWaitTime 1 92 | set_interface_property mmslave_avs setupTime 0 93 | set_interface_property mmslave_avs timingUnits Cycles 94 | set_interface_property mmslave_avs writeWaitTime 0 95 | set_interface_property mmslave_avs ENABLED true 96 | set_interface_property mmslave_avs EXPORT_OF "" 97 | set_interface_property mmslave_avs PORT_NAME_MAP "" 98 | set_interface_property mmslave_avs CMSIS_SVD_VARIABLES "" 99 | set_interface_property mmslave_avs SVD_ADDRESS_GROUP "" 100 | 101 | add_interface_port mmslave_avs mmSlave_avs_readdata readdata Output 64 102 | add_interface_port mmslave_avs mmSlave_avs_readdatavalid readdatavalid Output 1 103 | add_interface_port mmslave_avs mmSlave_avs_waitrequest waitrequest Output 1 104 | add_interface_port mmslave_avs mmSlave_avs_writedata writedata Input 64 105 | add_interface_port mmslave_avs mmSlave_avs_address address Input 8 106 | add_interface_port mmslave_avs mmSlave_avs_read read Input 1 107 | add_interface_port mmslave_avs mmSlave_avs_write write Input 1 108 | add_interface_port mmslave_avs mmSlave_avs_byteenable byteenable Input 8 109 | set_interface_assignment mmslave_avs embeddedsw.configuration.isFlash 0 110 | set_interface_assignment mmslave_avs embeddedsw.configuration.isMemoryDevice 0 111 | set_interface_assignment mmslave_avs embeddedsw.configuration.isNonVolatileStorage 0 112 | set_interface_assignment mmslave_avs embeddedsw.configuration.isPrintableDevice 0 113 | 114 | 115 | # 116 | # connection point reset_sink 117 | # 118 | add_interface reset_sink reset end 119 | set_interface_property reset_sink associatedClock clock 120 | set_interface_property reset_sink synchronousEdges DEASSERT 121 | set_interface_property reset_sink ENABLED true 122 | set_interface_property reset_sink EXPORT_OF "" 123 | set_interface_property reset_sink PORT_NAME_MAP "" 124 | set_interface_property reset_sink CMSIS_SVD_VARIABLES "" 125 | set_interface_property reset_sink SVD_ADDRESS_GROUP "" 126 | 127 | add_interface_port reset_sink RST_N reset_n Input 1 128 | 129 | 130 | # 131 | # connection point avalon_streaming_sink 132 | # 133 | add_interface avalon_streaming_sink avalon_streaming end 134 | set_interface_property avalon_streaming_sink associatedClock clock 135 | set_interface_property avalon_streaming_sink associatedReset reset_sink 136 | set_interface_property avalon_streaming_sink dataBitsPerSymbol 64 137 | set_interface_property avalon_streaming_sink errorDescriptor "" 138 | set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true 139 | set_interface_property avalon_streaming_sink maxChannel 0 140 | set_interface_property avalon_streaming_sink readyLatency 0 141 | set_interface_property avalon_streaming_sink ENABLED true 142 | set_interface_property avalon_streaming_sink EXPORT_OF "" 143 | set_interface_property avalon_streaming_sink PORT_NAME_MAP "" 144 | set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES "" 145 | set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP "" 146 | 147 | add_interface_port avalon_streaming_sink streamSink_asi_data data Input 64 148 | add_interface_port avalon_streaming_sink streamSink_asi_valid valid Input 1 149 | add_interface_port avalon_streaming_sink streamSink_asi_eop endofpacket Input 1 150 | add_interface_port avalon_streaming_sink streamSink_asi_sop startofpacket Input 1 151 | add_interface_port avalon_streaming_sink streamSink_asi_ready ready Output 1 152 | 153 | 154 | # 155 | # connection point conduit_bar 156 | # 157 | add_interface conduit_bar conduit end 158 | set_interface_property conduit_bar associatedClock clock 159 | set_interface_property conduit_bar associatedReset reset_sink 160 | set_interface_property conduit_bar ENABLED true 161 | set_interface_property conduit_bar EXPORT_OF "" 162 | set_interface_property conduit_bar PORT_NAME_MAP "" 163 | set_interface_property conduit_bar CMSIS_SVD_VARIABLES "" 164 | set_interface_property conduit_bar SVD_ADDRESS_GROUP "" 165 | 166 | add_interface_port conduit_bar streamSink_asi_bar bar Input 8 167 | 168 | 169 | # 170 | # connection point conduit_be 171 | # 172 | add_interface conduit_be conduit end 173 | set_interface_property conduit_be associatedClock clock 174 | set_interface_property conduit_be associatedReset reset_sink 175 | set_interface_property conduit_be ENABLED true 176 | set_interface_property conduit_be EXPORT_OF "" 177 | set_interface_property conduit_be PORT_NAME_MAP "" 178 | set_interface_property conduit_be CMSIS_SVD_VARIABLES "" 179 | set_interface_property conduit_be SVD_ADDRESS_GROUP "" 180 | 181 | add_interface_port conduit_be streamSink_asi_be be Input 8 182 | 183 | 184 | # 185 | # connection point conduit_parity 186 | # 187 | add_interface conduit_parity conduit end 188 | set_interface_property conduit_parity associatedClock clock 189 | set_interface_property conduit_parity associatedReset reset_sink 190 | set_interface_property conduit_parity ENABLED true 191 | set_interface_property conduit_parity EXPORT_OF "" 192 | set_interface_property conduit_parity PORT_NAME_MAP "" 193 | set_interface_property conduit_parity CMSIS_SVD_VARIABLES "" 194 | set_interface_property conduit_parity SVD_ADDRESS_GROUP "" 195 | 196 | add_interface_port conduit_parity streamSink_asi_parity parity Input 8 197 | 198 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/PCIePacketReceiver.bsv: -------------------------------------------------------------------------------- 1 | /*- 2 | * SPDX-License-Identifier: BSD-2-Clause 3 | * 4 | * Copyright (c) 2015-2018 A. Theodore Markettos 5 | * All rights reserved. 6 | * 7 | * This software was developed by SRI International and the University of 8 | * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 9 | * ("CTSRD"), as part of the DARPA CRASH research programme. 10 | * 11 | * Redistribution and use in source and binary forms, with or without 12 | * modification, are permitted provided that the following conditions 13 | * are met: 14 | * 1. Redistributions of source code must retain the above copyright 15 | * notice, this list of conditions and the following disclaimer. 16 | * 2. Redistributions in binary form must reproduce the above copyright 17 | * notice, this list of conditions and the following disclaimer in the 18 | * documentation and/or other materials provided with the distribution. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 | * SUCH DAMAGE. 31 | */ 32 | // PCIeBuffer.bsv 33 | 34 | import AvalonSTPCIe::*; 35 | import AvalonMM::*; 36 | import GetPut::*; 37 | import ClientServer::*; 38 | import Connectable::*; 39 | import FIFOF::*; 40 | import PCIE::*; 41 | import PCIeByteSwap::*; 42 | 43 | typedef Bit#(64) DataType; 44 | typedef Bit#(8) AddressType; 45 | typedef 0 BurstWidth; 46 | typedef 1 ByteEnable; 47 | 48 | 49 | interface PCIePacketReceiver; 50 | interface AvalonSinkExtPCIe streamSink; 51 | interface AvalonSlaveExt#(DataType, AddressType, BurstWidth, ByteEnable) mmSlave; 52 | endinterface: PCIePacketReceiver 53 | 54 | module mkPCIePacketReceiver(PCIePacketReceiver); 55 | AvalonSinkPCIe streamToFIFO <- mkAvalonSinkPCIe; 56 | AvalonSlave#(DataType, AddressType, BurstWidth, ByteEnable) slave <- mkAvalonSlave; 57 | Reg#(PCIeWord) currentpcieword <- mkReg(unpack(0)); 58 | Reg#(Bool) next <- mkReg(True); 59 | FIFOF#(PCIeWord) rxfifo <- mkUGSizedFIFOF(1024); 60 | Reg#(Bool) fourDWord <- mkReg(True); 61 | Reg#(UInt#(10)) dwordCounter <- mkReg(10'h0); 62 | 63 | 64 | rule serviceMMSlave; 65 | AvalonMMRequest#(DataType, AddressType, BurstWidth, ByteEnable) req <- slave.client.request.get(); 66 | AvalonMMResponse#(DataType) responseWrapped = 64'hfeeb1ec0ffeefeed; 67 | DataType response = 64'hdeadfacebeefcafe; 68 | $display("request"); 69 | if (req matches tagged AvalonRead { address:.address, byteenable:.be, burstcount:.burstcount}) 70 | begin 71 | $display("read %x",address); 72 | case (address) 73 | 0: begin 74 | response = rxfifo.first().data; 75 | $display("trigger pcieword=%x", rxfifo.first()); 76 | if (rxfifo.notEmpty) 77 | rxfifo.deq(); 78 | end 79 | 1: begin 80 | // response = rxfifo.first().data[63:32]; 81 | response = rxfifo.first().data; 82 | end 83 | 2: begin 84 | // response = {38'b0, pack(rxfifo.first().eof), pack(rxfifo.first().sof), rxfifo.first().be, 8'b0, 8'b0}; //rxfifo.first().parity, rxfifo.first().bar}; 85 | response = {rxfifo.first().eof ? 8'hEE:8'h0, rxfifo.first().sof ? 8'h55:8'h0, 22'b0, 86 | pack(rxfifo.first().eof), pack(rxfifo.first().sof), rxfifo.first().be, 8'b0, 8'b0}; //rxfifo.first().parity, rxfifo.first().bar}; 87 | end 88 | 3: begin 89 | response = signExtend(pack(rxfifo.notEmpty)); 90 | end 91 | endcase 92 | responseWrapped = response; // convert from a data word into a response packet 93 | slave.client.response.put(responseWrapped); 94 | end 95 | 96 | else if (req matches tagged AvalonWrite{ writedata:.data, address:.address, byteenable:.be, burstcount:.burstcount}) 97 | begin 98 | $display("write %x",address); 99 | // never block writes 100 | slave.client.response.put(responseWrapped); 101 | end 102 | // $display("address=%x", address); 103 | 104 | endrule 105 | 106 | rule fetchpcieword; 107 | PCIeWord pciedataUnswapped <- streamToFIFO.receive.get(); 108 | PCIeWord pciedataSwapped = pciedataUnswapped; 109 | /* // don't byte-swap data 110 | pciedataSwapped.sof = pciedataUnswapped.sof; 111 | pciedataSwapped.eof = pciedataUnswapped.eof; 112 | pciedataSwapped.hit = pciedataUnswapped.hit; 113 | 114 | // header fields have a different byteswapping from data fields 115 | // the length of the header can be either 3 or 4 dwords, and the start 116 | // of data can change based on whether it is Q-word (16 byte) aligned or not 117 | 118 | // we need to know whether the TLP is a 3 or 4 D-word TLP from 64-bit dword 0 119 | // to decide how to byteswap dword 1 120 | if (pciedataUnswapped.sof) 121 | begin // first word, so make a note of packet format 122 | fourDWord <= unpack(pciedataUnswapped.data[29]); 123 | dwordCounter <= 1; 124 | pciedataSwapped.data = byteSwap32in64(pciedataUnswapped.data); 125 | $display("PCIe packet start, dwordCounter=%d, fourDWord=%d, unswapped word 0 = %x", dwordCounter, fourDWord, pciedataUnswapped.data); 126 | end else begin 127 | dwordCounter <= dwordCounter + 1; 128 | case (dwordCounter) // count words beginning at the second (ie the mixed header/data dword) 129 | 1: begin // if a 3 dword TLP, have to apply data swap and header swap on each half 130 | if (fourDWord) begin // else a straight header swap 131 | pciedataSwapped.data = byteSwap32in64(pciedataUnswapped.data); // header swap 132 | end else begin 133 | pciedataSwapped.data = byteSwapBottom32(pciedataUnswapped.data); // mixed swap 134 | end 135 | end 136 | default: begin 137 | pciedataSwapped.data = pciedataUnswapped.data; 138 | end 139 | endcase 140 | end 141 | 142 | // in all data words the byte enables are reversed, and they are ignore for header words. 143 | // so swap them assuming they're always data 144 | pciedataSwapped.be = pciedataUnswapped.be; 145 | */ 146 | if (rxfifo.notFull) 147 | begin 148 | rxfifo.enq(pciedataSwapped); 149 | $display("PCIe word[%d] arrived as %x, swapped into %x, 4DWordTLP=%x, sof=%d, eof=%d, be.in=%x, be.swapped=%x", 150 | dwordCounter, pciedataUnswapped, pciedataSwapped, fourDWord, 151 | pciedataUnswapped.sof, pciedataUnswapped.eof, pciedataUnswapped.be, pciedataSwapped.be); 152 | end else begin 153 | $display("junked"); 154 | end 155 | next <= False; 156 | endrule 157 | 158 | rule nextprint; 159 | $display("next=%d, rxfifo.empty=%d",next, !rxfifo.notEmpty()); 160 | endrule 161 | 162 | interface streamSink = streamToFIFO.asi; 163 | interface mmSlave = slave.avs; 164 | 165 | 166 | endmodule 167 | 168 | 169 | interface PCIePacketReceiverTB; 170 | endinterface 171 | 172 | //typedef Bit#(64) PCIeWord; 173 | 174 | 175 | module mkPCIePacketReceiverTB(PCIePacketReceiverTB); 176 | // MMRingBufferSink tbsink <- mkMMRingBufferSink; 177 | // AvalonSinkPCIe sink <- mkAvalonSinkPCIe; 178 | PCIePacketReceiver dut <- mkPCIePacketReceiver; 179 | AvalonMaster#(DataType, AddressType, BurstWidth, ByteEnable) master <- mkAvalonMaster; 180 | 181 | //mkConnection(master.avm, dut.mmSlave); 182 | 183 | Reg#(Int#(64)) tick <- mkReg(0); 184 | Reg#(Int#(10)) wordCounter <- mkReg(0); 185 | Reg#(Bool) reading <- mkReg(False); 186 | // MMRingBufferSource source <- mkMMRingBufferSource; 187 | 188 | /* rule print; 189 | $display("Hello world\n"); 190 | endrule 191 | */ 192 | rule ticktock; 193 | tick <= tick + 1; 194 | endrule 195 | 196 | rule sink_in; 197 | PCIeWord invalue; 198 | invalue.data = extend(pack(tick)) ^ 64'h01234567A9ABCDEF; 199 | invalue.be = pack(tick)[12:5]; 200 | invalue.hit = 0; 201 | //invalue.parity = 0; 202 | //invalue.bar = 0; 203 | Int#(10) wordCounterNext = (wordCounter==8) ? 0:wordCounter+1; 204 | wordCounter <= wordCounterNext; 205 | invalue.sof = (wordCounterNext == 0); 206 | invalue.eof = False; 207 | // sink.asi.asi(data, False, False, False, 8'hff, 8'h00); 208 | dut.streamSink.asi(invalue.data, True, invalue.sof, invalue.eof, invalue.be, 0, 0); //invalue.parity, invalue.bar); 209 | 210 | $display("%d: asi_ready = %d", tick, dut.streamSink.asi_ready()); 211 | if (dut.streamSink.asi_ready) 212 | $display("%d: Input word %d", tick, wordCounter); 213 | endrule 214 | 215 | rule ready; 216 | Bool ready = dut.streamSink.asi_ready(); 217 | $display("%d: Ready = %d", tick, ready); 218 | endrule 219 | 220 | rule read; 221 | // AvalonMMRequest#(DataType, AddressType, BurstWidth, ByteEnable) req = 222 | // tagged AvalonRead { address:8'h12, byteenable:1 }; 223 | Bit#(8) address = extend(pack(tick)[5:3]); 224 | dut.mmSlave.avs(64'hfaceb00cdeadbeef, address, reading, False, 1, 0); 225 | reading <= !reading; 226 | if (reading) 227 | $display("%d: read request addr %x", tick,address); 228 | endrule 229 | 230 | rule readdata if (dut.mmSlave.avs_readdatavalid); 231 | $display("%d: read response %x", tick, dut.mmSlave.avs_readdata()); 232 | endrule 233 | 234 | // rule sink_out; 235 | // PCIeWord out <- dut.streamSink.receive.get(); 236 | // $display("%d: Output %x", tick, pack(out)); 237 | // endrule 238 | 239 | endmodule 240 | 241 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/hps_a10_devkit_board_info.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 0x0 37 | 0x1B20000 38 | 39 | 40 | 41 | 42 | 0x1B20000 43 | 0x64E0000 44 | 45 | 46 | 47 | 0 48 | 135 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 0 57 | 3 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | led_pio 99 | 0 100 | 1 101 | 102 | 103 | 104 | 105 | led_pio 106 | 1 107 | 1 108 | 109 | 110 | 111 | 112 | led_pio 113 | 2 114 | 1 115 | 116 | 117 | 118 | 119 | 120 | led_pio 121 | 3 122 | 1 123 | 124 | 125 | 126 | 0x0 127 | 0x66 128 | 0x4 129 | 130 | 131 | 132 | 0x1d 133 | 0x10 134 | 135 | 136 | 137 | 0x1d 138 | 0x11 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 5 147 | 8 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | gpio4 170 | 4 171 | 1 172 | 173 | 174 | 175 | gpio4 176 | 5 177 | 1 178 | 179 | 180 | 181 | gpio4 182 | 6 183 | 1 184 | 185 | 186 | 187 | gpio4 188 | 7 189 | 1 190 | 191 | 192 | 193 | 194 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/AvalonMM.bsv: -------------------------------------------------------------------------------- 1 | /*- 2 | * Copyright (c) 2013 Alex Horsman 3 | * All rights reserved. 4 | * 5 | * This software was developed by SRI International and the University of 6 | * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 | * ("CTSRD"), as part of the DARPA CRASH research programme. 8 | * 9 | * @BERI_LICENSE_HEADER_START@ 10 | * 11 | * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor 12 | * license agreements. See the NOTICE file distributed with this work for 13 | * additional information regarding copyright ownership. BERI licenses this 14 | * file to you under the BERI Hardware-Software License, Version 1.0 (the 15 | * "License"); you may not use this file except in compliance with the 16 | * License. You may obtain a copy of the License at: 17 | * 18 | * http://www.beri-open-systems.org/legal/license-1-0.txt 19 | * 20 | * Unless required by applicable law or agreed to in writing, Work distributed 21 | * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 22 | * CONDITIONS OF ANY KIND, either express or implied. See the License for the 23 | * specific language governing permissions and limitations under the License. 24 | * 25 | * @BERI_LICENSE_HEADER_END@ 26 | */ 27 | 28 | package AvalonMM; 29 | 30 | import GetPut::*; 31 | import ClientServer::*; 32 | import FIFO::*; 33 | import FIFOF::*; 34 | import FIFOLevel::*; 35 | 36 | 37 | typedef union tagged { 38 | struct { 39 | addressT address; 40 | Bit#(TMul#(byteEnable,TDiv#(SizeOf#(dataT),8))) byteenable; 41 | UInt#(burstWidth) burstcount; 42 | } AvalonRead; 43 | struct { 44 | dataT writedata; 45 | addressT address; 46 | Bit#(TMul#(byteEnable,TDiv#(SizeOf#(dataT),8))) byteenable; 47 | UInt#(burstWidth) burstcount; 48 | } AvalonWrite; 49 | } AvalonMMRequest#( 50 | type dataT, 51 | type addressT, 52 | numeric type burstWidth, 53 | numeric type byteEnable 54 | ) deriving(Bits); 55 | 56 | typedef dataT AvalonMMResponse#(type dataT); 57 | 58 | 59 | //External interface for an Avalon Master device. 60 | (* always_ready, always_enabled *) 61 | interface AvalonMasterExtVerbose#( 62 | type dataT, 63 | type addressT, 64 | numeric type burstWidth, 65 | numeric type byteEnableWidth 66 | ); 67 | method Action avm( 68 | dataT readdata, 69 | Bool readdatavalid, 70 | Bool waitrequest 71 | ); 72 | method dataT avm_writedata; 73 | method addressT avm_address; 74 | method Bool avm_read; 75 | method Bool avm_write; 76 | method Bit#(byteEnableWidth) avm_byteenable; 77 | method UInt#(burstWidth) avm_burstcount; 78 | endinterface 79 | 80 | typedef AvalonMasterExtVerbose#(dataT,addressT,burstWidth,TMul#(byteEnable,TDiv#(SizeOf#(dataT),8))) 81 | AvalonMasterExt#(type dataT,type addressT,numeric type burstWidth,numeric type byteEnable); 82 | 83 | 84 | //Internal interface to expose the phases of the 85 | //Avalon Master protocol as Action methods. 86 | interface AvalonMaster#( 87 | type dataT, 88 | type addressT, 89 | numeric type burstWidth, 90 | numeric type byteEnable 91 | ); 92 | interface AvalonMasterExt#(dataT,addressT,burstWidth,byteEnable) avm; 93 | interface Server#( 94 | AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable), 95 | AvalonMMResponse#(dataT) 96 | ) server; 97 | endinterface 98 | 99 | module mkAvalonMaster(AvalonMaster#(dataT,addressT,burstWidth,byteEnable)) 100 | provisos( 101 | Bits#(dataT,dataWidth), 102 | Bits#(addressT,addressWidth), 103 | Mul#(8,dataBytes,dataWidth) 104 | ); 105 | 106 | RWire#(AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable)) 107 | req <- mkRWire; 108 | 109 | Wire#(Bool) reqReady <- mkWire; 110 | 111 | //Should be UGBypassFIFO 112 | FIFOF#(dataT) resp <- mkGLFIFOF(True,False); 113 | 114 | //External interface wiring 115 | interface AvalonMasterExtVerbose avm; 116 | method Action avm(readdata,readdatavalid,waitrequest); 117 | if (readdatavalid) begin 118 | resp.enq(readdata); 119 | end 120 | reqReady <= !waitrequest; 121 | endmethod 122 | method avm_writedata = case (fromMaybe(?,req.wget)) matches 123 | tagged AvalonWrite { writedata: .w } : return w; 124 | endcase; 125 | method avm_address = case (fromMaybe(?,req.wget)) matches 126 | tagged AvalonRead { address: .a } : return a; 127 | tagged AvalonWrite { address: .a } : return a; 128 | endcase; 129 | method avm_read = case (req.wget) matches 130 | tagged Valid (tagged AvalonRead {}) : return True; 131 | default : return False; 132 | endcase; 133 | method avm_write = case (req.wget) matches 134 | tagged Valid (tagged AvalonWrite {}) : return True; 135 | default : return False; 136 | endcase; 137 | method avm_byteenable = case (fromMaybe(?,req.wget)) matches 138 | tagged AvalonRead { byteenable: .be } : return be; 139 | tagged AvalonWrite { byteenable: .be } : return be; 140 | endcase; 141 | method avm_burstcount = case (fromMaybe(?,req.wget)) matches 142 | tagged AvalonRead { burstcount: .c } : return c; 143 | tagged AvalonWrite { burstcount: .c } : return c; 144 | endcase; 145 | endinterface 146 | 147 | interface Server server; 148 | interface Put request; 149 | method Action put(x) if (reqReady); 150 | req.wset(x); 151 | endmethod 152 | endinterface 153 | interface response = toGet(resp); 154 | endinterface 155 | 156 | endmodule 157 | 158 | 159 | //External interface for an Avalon Slave device. 160 | (* always_ready, always_enabled *) 161 | interface AvalonSlaveExtVerbose#( 162 | type dataT, 163 | type addressT, 164 | numeric type burstWidth, 165 | numeric type byteEnableWidth 166 | ); 167 | method dataT avs_readdata; 168 | method Bool avs_readdatavalid; 169 | method Bool avs_waitrequest; 170 | method Action avs( 171 | dataT writedata, 172 | addressT address, 173 | Bool read, 174 | Bool write, 175 | Bit#(byteEnableWidth) byteenable, 176 | UInt#(burstWidth) burstcount 177 | ); 178 | endinterface 179 | 180 | typedef AvalonSlaveExtVerbose#(dataT,addressT,burstWidth,TMul#(byteEnable,TDiv#(SizeOf#(dataT),8))) 181 | AvalonSlaveExt#(type dataT,type addressT,numeric type burstWidth,numeric type byteEnable); 182 | 183 | interface AvalonSlave#( 184 | type dataT, 185 | type addressT, 186 | numeric type burstWidth, 187 | numeric type byteEnable 188 | ); 189 | interface AvalonSlaveExt#(dataT,addressT,burstWidth,byteEnable) avs; 190 | interface Client#( 191 | AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable), 192 | AvalonMMResponse#(dataT) 193 | ) client; 194 | endinterface 195 | 196 | module mkAvalonSlave( 197 | AvalonSlave#(dataT,addressT,burstWidth,byteEnable)) 198 | provisos( 199 | Bits#(dataT,dataWidth), 200 | Bits#(addressT,addressWidth), 201 | Mul#(8,dataBytes,dataWidth) 202 | ); 203 | 204 | //Should be UGBypassFIFO 205 | FIFOF#(AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable)) 206 | req <- mkGLFIFOF(True,False); 207 | 208 | RWire#(dataT) resp <- mkRWire; 209 | 210 | interface AvalonSlaveExtVerbose avs; 211 | method avs_readdata = fromMaybe(?,resp.wget); 212 | method avs_readdatavalid = isValid(resp.wget); 213 | method avs_waitrequest = !req.notFull; 214 | method Action avs(writedata,address,read,write,byteenable,burstcount); 215 | if (read) begin 216 | req.enq(AvalonRead{ 217 | address : address, 218 | byteenable : byteenable, 219 | burstcount : burstcount 220 | }); 221 | end else 222 | if (write) begin 223 | req.enq(AvalonWrite{ 224 | address : address, 225 | writedata : writedata, 226 | byteenable : byteenable, 227 | burstcount : burstcount 228 | }); 229 | end 230 | endmethod 231 | endinterface 232 | 233 | interface Client client; 234 | interface Get request; 235 | method ActionValue#( 236 | AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable) 237 | ) get(); 238 | req.deq(); 239 | return req.first; 240 | endmethod 241 | endinterface 242 | interface response = toPut(resp); 243 | endinterface 244 | 245 | endmodule 246 | 247 | 248 | interface AvalonBuffer#( 249 | numeric type reqDepth, 250 | numeric type respDepth, 251 | type dataT, 252 | type addressT, 253 | numeric type burstWidth, 254 | numeric type byteEnable 255 | ); 256 | interface Server#( 257 | AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable), 258 | AvalonMMResponse#(dataT) 259 | ) server; 260 | interface Client#( 261 | AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable), 262 | AvalonMMResponse#(dataT) 263 | ) client; 264 | endinterface 265 | 266 | typedef UInt#(TLog#(TAdd#(a,1))) Range#(numeric type a); 267 | 268 | module mkAvalonBuffer( 269 | AvalonBuffer#(reqDepth,respDepth,dataT,addressT,burstWidth,byteEnable)) 270 | provisos( 271 | Bits#(dataT,dataWidth), 272 | Bits#(addressT,addressWidth), 273 | Add#(burstWidth, _, TLog#(TAdd#(respDepth, 1))) 274 | ); 275 | 276 | FIFO#(AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable)) 277 | requestBuffer <- mkSizedFIFO(valueof(reqDepth)); 278 | 279 | FIFOCountIfc#(dataT,respDepth) responseBuffer <- mkFIFOCount; 280 | Reg#(Range#(respDepth)) allocated <- mkReg(0); 281 | 282 | Wire#(Range#(respDepth)) allocate <- mkDWire(0); 283 | Wire#(Range#(respDepth)) deallocate <- mkDWire(0); 284 | rule updateAllocated; 285 | allocated <= allocated + allocate - deallocate; 286 | endrule 287 | 288 | Range#(respDepth) nextAllocation = case (requestBuffer.first) matches 289 | tagged AvalonRead { burstcount: .bc } &&& (bc > 1) : return extend(bc); 290 | tagged AvalonRead {} : return 1; 291 | tagged AvalonWrite {} : return 0; 292 | endcase; 293 | 294 | let freeSpace = 295 | fromInteger(valueof(respDepth)) - responseBuffer.count - allocated; 296 | 297 | interface Server server; 298 | interface request = toPut(requestBuffer); 299 | interface response = toGet(responseBuffer); 300 | endinterface 301 | interface Client client; 302 | interface Get request; 303 | method ActionValue#( 304 | AvalonMMRequest#(dataT,addressT,burstWidth,byteEnable) 305 | ) get() if (extend(nextAllocation) < freeSpace); 306 | allocate <= nextAllocation; 307 | requestBuffer.deq(); 308 | return requestBuffer.first; 309 | endmethod 310 | endinterface 311 | interface Put response; 312 | method Action put(x); 313 | responseBuffer.enq(x); 314 | deallocate <= 1; 315 | endmethod 316 | endinterface 317 | endinterface 318 | endmodule 319 | 320 | 321 | endpackage 322 | -------------------------------------------------------------------------------- /lib/SizedFIFO.v: -------------------------------------------------------------------------------- 1 | 2 | // Copyright (c) 2000-2012 Bluespec, Inc. 3 | 4 | // Permission is hereby granted, free of charge, to any person obtaining a copy 5 | // of this software and associated documentation files (the "Software"), to deal 6 | // in the Software without restriction, including without limitation the rights 7 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | // copies of the Software, and to permit persons to whom the Software is 9 | // furnished to do so, subject to the following conditions: 10 | 11 | // The above copyright notice and this permission notice shall be included in 12 | // all copies or substantial portions of the Software. 13 | 14 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | // THE SOFTWARE. 21 | // 22 | // $Revision$ 23 | // $Date$ 24 | 25 | `ifdef BSV_ASSIGNMENT_DELAY 26 | `else 27 | `define BSV_ASSIGNMENT_DELAY 28 | `endif 29 | 30 | `ifdef BSV_POSITIVE_RESET 31 | `define BSV_RESET_VALUE 1'b1 32 | `define BSV_RESET_EDGE posedge 33 | `else 34 | `define BSV_RESET_VALUE 1'b0 35 | `define BSV_RESET_EDGE negedge 36 | `endif 37 | 38 | `ifdef BSV_ASYNC_RESET 39 | `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST 40 | `else 41 | `define BSV_ARESET_EDGE_META 42 | `endif 43 | 44 | `ifdef BSV_RESET_FIFO_HEAD 45 | `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META 46 | `else 47 | `define BSV_ARESET_EDGE_HEAD 48 | `endif 49 | 50 | `ifdef BSV_RESET_FIFO_ARRAY 51 | `define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META 52 | `else 53 | `define BSV_ARESET_EDGE_ARRAY 54 | `endif 55 | 56 | 57 | // Sized fifo. Model has output register which improves timing 58 | module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); 59 | parameter p1width = 1; // data width 60 | parameter p2depth = 3; 61 | parameter p3cntr_width = 1; // log(p2depth-1) 62 | // The -1 is allowed since this model has a fast output register 63 | parameter guarded = 1; 64 | localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ; 65 | 66 | input CLK; 67 | input RST; 68 | input CLR; 69 | input [p1width - 1 : 0] D_IN; 70 | input ENQ; 71 | input DEQ; 72 | 73 | output FULL_N; 74 | output EMPTY_N; 75 | output [p1width - 1 : 0] D_OUT; 76 | 77 | reg not_ring_full; 78 | reg ring_empty; 79 | 80 | reg [p3cntr_width-1 : 0] head; 81 | wire [p3cntr_width-1 : 0] next_head; 82 | 83 | reg [p3cntr_width-1 : 0] tail; 84 | wire [p3cntr_width-1 : 0] next_tail; 85 | 86 | // if the depth is too small, don't create an ill-sized array; 87 | // instead, make a 1-sized array and let the initial block report an error 88 | reg [p1width - 1 : 0] arr[0: p2depth2]; 89 | 90 | reg [p1width - 1 : 0] D_OUT; 91 | reg hasodata; 92 | 93 | wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ; 94 | 95 | wire [p3cntr_width-1 : 0] incr_tail; 96 | wire [p3cntr_width-1 : 0] incr_head; 97 | 98 | assign incr_tail = tail + 1'b1 ; 99 | assign incr_head = head + 1'b1 ; 100 | 101 | assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ; 102 | assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ; 103 | 104 | assign EMPTY_N = hasodata; 105 | assign FULL_N = not_ring_full; 106 | 107 | `ifdef BSV_NO_INITIAL_BLOCKS 108 | `else // not BSV_NO_INITIAL_BLOCKS 109 | // synopsys translate_off 110 | initial 111 | begin : initial_block 112 | integer i; 113 | D_OUT = {((p1width + 1)/2){2'b10}} ; 114 | 115 | ring_empty = 1'b1; 116 | not_ring_full = 1'b1; 117 | hasodata = 1'b0; 118 | head = {p3cntr_width {1'b0}} ; 119 | tail = {p3cntr_width {1'b0}} ; 120 | 121 | for (i = 0; i <= p2depth2; i = i + 1) 122 | begin 123 | arr[i] = D_OUT ; 124 | end 125 | end 126 | // synopsys translate_on 127 | `endif // BSV_NO_INITIAL_BLOCKS 128 | 129 | 130 | always @(posedge CLK `BSV_ARESET_EDGE_META) 131 | begin 132 | if (RST == `BSV_RESET_VALUE) 133 | begin 134 | head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; 135 | tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; 136 | ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1; 137 | not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; 138 | hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; 139 | end // if (RST == `BSV_RESET_VALUE) 140 | else 141 | begin 142 | 143 | casez ({CLR, DEQ, ENQ, hasodata, ring_empty}) 144 | // Clear operation 145 | 5'b1????: begin 146 | head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; 147 | tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; 148 | ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1; 149 | not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; 150 | hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; 151 | end 152 | // ----------------------- 153 | // DEQ && ENQ case -- change head and tail if added to ring 154 | 5'b011?0: begin 155 | tail <= `BSV_ASSIGNMENT_DELAY next_tail; 156 | head <= `BSV_ASSIGNMENT_DELAY next_head; 157 | end 158 | // ----------------------- 159 | // DEQ only and NO data is in ring 160 | 5'b010?1: begin 161 | hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; 162 | end 163 | // DEQ only and data is in ring (move the head pointer) 164 | 5'b010?0: begin 165 | head <= `BSV_ASSIGNMENT_DELAY next_head; 166 | not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; 167 | ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ; 168 | end 169 | // ----------------------- 170 | // ENQ only when empty 171 | 5'b0010?: begin 172 | hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1; 173 | end 174 | // ENQ only when not empty 175 | 5'b0011?: begin 176 | if ( not_ring_full ) // Drop this test to save redundant test 177 | // but be warnned that with test fifo overflow causes loss of new data 178 | // while without test fifo drops all but head entry! (pointer overflow) 179 | begin 180 | tail <= `BSV_ASSIGNMENT_DELAY next_tail; 181 | ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0; 182 | not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ; 183 | end 184 | end 185 | endcase 186 | end // else: !if(RST == `BSV_RESET_VALUE) 187 | end // always @ (posedge CLK) 188 | 189 | // Update the fast data out register 190 | always @(posedge CLK `BSV_ARESET_EDGE_HEAD) 191 | begin 192 | `ifdef BSV_RESET_FIFO_HEAD 193 | if (RST == `BSV_RESET_VALUE) 194 | begin 195 | D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ; 196 | end // if (RST == `BSV_RESET_VALUE) 197 | else 198 | `endif 199 | begin 200 | casez ({CLR, DEQ, ENQ, hasodata, ring_empty}) 201 | // DEQ && ENQ cases 202 | 5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end 203 | 5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end 204 | // DEQ only and data is in ring 205 | 5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end 206 | // ENQ only when empty 207 | 5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end 208 | endcase 209 | end // else: !if(RST == `BSV_RESET_VALUE) 210 | end // always @ (posedge CLK) 211 | 212 | // Update the memory array reset is OFF 213 | always @(posedge CLK `BSV_ARESET_EDGE_ARRAY) 214 | begin: array 215 | `ifdef BSV_RESET_FIFO_ARRAY 216 | if (RST == `BSV_RESET_VALUE) 217 | begin: rst_array 218 | integer i; 219 | for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1) 220 | begin 221 | arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ; 222 | end 223 | end // if (RST == `BSV_RESET_VALUE) 224 | else 225 | `endif 226 | begin 227 | if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full))) 228 | begin 229 | arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN; 230 | end 231 | end // else: !if(RST == `BSV_RESET_VALUE) 232 | end // always @ (posedge CLK) 233 | 234 | // synopsys translate_off 235 | always@(posedge CLK) 236 | begin: error_checks 237 | reg deqerror, enqerror ; 238 | 239 | deqerror = 0; 240 | enqerror = 0; 241 | if (RST == ! `BSV_RESET_VALUE) 242 | begin 243 | if ( ! EMPTY_N && DEQ ) 244 | begin 245 | deqerror = 1 ; 246 | $display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ; 247 | end 248 | if ( ! FULL_N && ENQ && (!DEQ || guarded) ) 249 | begin 250 | enqerror = 1 ; 251 | $display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ; 252 | end 253 | end 254 | end // block: error_checks 255 | // synopsys translate_on 256 | 257 | // synopsys translate_off 258 | // Some assertions about parameter values 259 | initial 260 | begin : parameter_assertions 261 | integer ok ; 262 | ok = 1 ; 263 | 264 | if ( p2depth <= 1) 265 | begin 266 | ok = 0; 267 | $display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth); 268 | end 269 | 270 | if ( p3cntr_width <= 0 ) 271 | begin 272 | ok = 0; 273 | $display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ; 274 | end 275 | 276 | if ( ok == 0 ) $finish ; 277 | 278 | end // initial begin 279 | // synopsys translate_on 280 | 281 | endmodule 282 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/PCIePipes/PCIePacketTransmitter.bsv: -------------------------------------------------------------------------------- 1 | /*- 2 | * SPDX-License-Identifier: BSD-2-Clause 3 | * 4 | * Copyright (c) 2015-2018 A. Theodore Markettos 5 | * All rights reserved. 6 | * 7 | * This software was developed by SRI International and the University of 8 | * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 9 | * ("CTSRD"), as part of the DARPA CRASH research programme. 10 | * 11 | * Redistribution and use in source and binary forms, with or without 12 | * modification, are permitted provided that the following conditions 13 | * are met: 14 | * 1. Redistributions of source code must retain the above copyright 15 | * notice, this list of conditions and the following disclaimer. 16 | * 2. Redistributions in binary form must reproduce the above copyright 17 | * notice, this list of conditions and the following disclaimer in the 18 | * documentation and/or other materials provided with the distribution. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 | * SUCH DAMAGE. 31 | */ 32 | // PCIePacketTx.bsv 33 | 34 | import AvalonSTPCIe::*; 35 | import AvalonMM::*; 36 | import GetPut::*; 37 | import ClientServer::*; 38 | import Connectable::*; 39 | import FIFOF::*; 40 | import PCIE::*; 41 | import PCIeByteSwap::*; 42 | 43 | typedef Bit#(64) DataType; 44 | typedef Bit#(8) AddressType; 45 | typedef 0 BurstWidth; 46 | typedef 1 ByteEnable; 47 | 48 | 49 | interface PCIePacketTransmitter; 50 | interface AvalonSourceExtPCIe streamSource; 51 | interface AvalonSlaveExt#(DataType, AddressType, BurstWidth, ByteEnable) mmSlave; 52 | endinterface: PCIePacketTransmitter 53 | 54 | 55 | interface PCIePacketTransmitterTB; 56 | endinterface 57 | 58 | //typedef Bit#(64) PCIeWord; 59 | 60 | 61 | module mkPCIePacketTransmitter(PCIePacketTransmitter); 62 | AvalonSourcePCIe fifoToStream <- mkAvalonSourcePCIe; 63 | AvalonSlave#(DataType, AddressType, BurstWidth, ByteEnable) slave <- mkAvalonSlave; 64 | Reg#(PCIeWord) currentpcieword <- mkReg(unpack(0)); 65 | // Reg#(Bool) next <- mkReg(True); 66 | Reg#(Bool) go <- mkReg(False); 67 | FIFOF#(PCIeWord) txfifo <- mkUGSizedFIFOF(64); 68 | Reg#(Bool) fourDWord <- mkReg(True); 69 | Reg#(UInt#(10)) dwordCounter <- mkReg(10'h0); 70 | 71 | rule serviceMMSlave; 72 | AvalonMMRequest#(DataType, AddressType, BurstWidth, ByteEnable) req <- slave.client.request.get(); 73 | AvalonMMResponse#(DataType) response = 64'hdeadfacebeefcafe; 74 | PCIeWord amendedWord = currentpcieword; 75 | $display("request"); 76 | if (req matches tagged AvalonWrite { address:.address, byteenable:.be, burstcount:.burstcount}) 77 | begin 78 | // for words which we want to transfer verbatim from BERI, we have to 79 | DataType writedataBERI = req.AvalonWrite.writedata; 80 | $display("write %x",address); 81 | case (address) 82 | 0: begin 83 | amendedWord.data = req.AvalonWrite.writedata; 84 | if (txfifo.notFull) 85 | begin 86 | txfifo.enq(amendedWord); 87 | $display("txfifo enqueued %x", amendedWord); 88 | end 89 | end 90 | 1: begin 91 | amendedWord.data = req.AvalonWrite.writedata; 92 | end 93 | 2: begin 94 | //amendedWord.bar = writedataBERI[7:0]; 95 | //amendedWord.parity = writedataBERI[15:8]; 96 | amendedWord.be = writedataBERI[23:16]; 97 | amendedWord.sof = unpack(writedataBERI[24]); 98 | amendedWord.eof = unpack(writedataBERI[25]); 99 | amendedWord.hit = 0; 100 | $display("Framing bits written: sofreg=%d, eofreg=%d, bereg=%x", amendedWord.sof, amendedWord.eof, amendedWord.be); 101 | end 102 | 3: begin 103 | go <= unpack(writedataBERI[0]); 104 | end 105 | endcase 106 | currentpcieword <= amendedWord; 107 | slave.client.response.put(response); 108 | end 109 | 110 | else if (req matches tagged AvalonRead{ address:.address, byteenable:.be, burstcount:.burstcount}) 111 | begin 112 | $display("read %x",address); 113 | slave.client.response.put(byteSwap64(64'hfaceb00c00c0ffee)); 114 | end 115 | // $display("address=%x", address); 116 | 117 | endrule 118 | 119 | rule sendpcieword; 120 | if (txfifo.notEmpty && go) 121 | begin 122 | PCIeWord pciedataUnswapped = txfifo.first(); 123 | txfifo.deq(); 124 | 125 | PCIeWord pciedataSwapped = pciedataUnswapped; 126 | /* // remove hardware byte swapping 127 | pciedataSwapped.sof = pciedataUnswapped.sof; 128 | pciedataSwapped.eof = pciedataUnswapped.eof; 129 | pciedataSwapped.hit = pciedataUnswapped.hit; 130 | 131 | // header fields have a different byteswapping from data fields 132 | // the length of the header can be either 3 or 4 dwords, and the start 133 | // of data can change based on whether it is Q-word (16 byte) aligned or not 134 | 135 | // we need to know whether the TLP is a 3 or 4 D-word TLP from 64-bit dword 0 136 | // to decide how to byteswap dword 1 137 | if (pciedataUnswapped.sof) 138 | begin // first word, so make a note of packet format 139 | // we think we receive words byte-swapped-within-64 from 140 | // Avalon, so we have to look the 'fmt' bits in the twisted 141 | // position 142 | Bool fourDWordNext = unpack(pciedataUnswapped.data[5]); 143 | fourDWord <= fourDWordNext; 144 | dwordCounter <= 1; 145 | pciedataSwapped.data = pciedataUnswapped.data; //byteSwap32in64(pciedataUnswapped.data); 146 | $display("PCIe packet start, dwordCounter=%d, fourDWord (this packet)=%d, unswapped word 0 = %x", dwordCounter, fourDWordNext, pciedataUnswapped.data); 147 | end else begin 148 | dwordCounter <= dwordCounter + 1; 149 | case (dwordCounter) // count words beginning at the second (ie the mixed header/data dword) 150 | 1: begin // if a 3 dword TLP, have to apply data swap and header swap on each half 151 | if (fourDWord) begin // else a straight header swap 152 | pciedataSwapped.data = pciedataUnswapped.data; //byteSwap32in64(pciedataUnswapped.data); // header swap 153 | $display("Header word 2/3 swap"); 154 | end else begin 155 | pciedataSwapped.data = pciedataUnswapped.data; //byteSwapBottom32(pciedataUnswapped.data); // mixed swap 156 | $display("Header word 2/data word 0 swap"); 157 | end 158 | end 159 | default: begin 160 | // no need to swap as Avalon and PCIe data are little endian 161 | pciedataSwapped.data = pciedataUnswapped.data; 162 | $display("Data swap"); 163 | end 164 | endcase 165 | end 166 | 167 | // in all data words the byte enables are reversed, and they are ignore for header words. 168 | // so swap them assuming they're always data 169 | //pciedataSwapped.be = reverseBits(pciedataUnswapped.be); 170 | pciedataSwapped.be = pciedataUnswapped.be; 171 | */ 172 | 173 | fifoToStream.send.put(pciedataSwapped); 174 | $display("PCIe word[%d] received from MM=%x, sent swapped=%x", dwordCounter, pciedataUnswapped, pciedataSwapped); 175 | end 176 | endrule 177 | 178 | rule nextprint; 179 | $display("go=%d, txfifo.empty=%d, txfifo.full=%d",go, !txfifo.notEmpty(), !txfifo.notFull()); 180 | endrule 181 | 182 | interface streamSource = fifoToStream.aso; 183 | interface mmSlave = slave.avs; 184 | 185 | 186 | endmodule 187 | 188 | 189 | 190 | module mkPCIePacketTransmitterTB(PCIePacketTransmitterTB); 191 | // MMRingBufferSink tbsink <- mkMMRingBufferSink; 192 | // AvalonSinkPCIe sink <- mkAvalonSinkPCIe; 193 | PCIePacketTransmitter dut <- mkPCIePacketTransmitter; 194 | AvalonMaster#(DataType, AddressType, BurstWidth, ByteEnable) master <- mkAvalonMaster; 195 | 196 | //mkConnection(master.avm, dut.mmSlave); 197 | 198 | Reg#(Int#(32)) tick <- mkReg(0); 199 | Reg#(Int#(10)) wordCounter <- mkReg(0); 200 | Reg#(Bool) writing <- mkReg(False); 201 | // MMRingBufferSource source <- mkMMRingBufferSource; 202 | 203 | /* rule print; 204 | $display("Hello world\n"); 205 | endrule 206 | */ 207 | rule ticktock; 208 | tick <= tick + 1; 209 | endrule 210 | 211 | rule source_out if (dut.streamSource.aso_valid); 212 | $display("%d: stream out data=%x, eop=%d, sop=%d, be=%x, parity=%x, bar=%x", tick, 213 | dut.streamSource.aso_data, 214 | dut.streamSource.aso_eop, 215 | dut.streamSource.aso_sop, 216 | dut.streamSource.aso_be, 217 | 0, 0); 218 | // dut.streamSource.aso_parity, 219 | // dut.streamSource.aso_bar); 220 | endrule 221 | 222 | rule source_enable; 223 | // always ready 224 | dut.streamSource.aso(True); 225 | endrule 226 | 227 | rule write; 228 | // AvalonMMRequest#(DataType, AddressType, BurstWidth, ByteEnable) req = 229 | // tagged AvalonRead { address:8'h12, byteenable:1 }; 230 | 231 | Bit#(8) address = extend(pack(tick)[3:1]); 232 | 233 | // count 8 words in a packet, but only count the words we actually wrote data, 234 | // not the ones where our sequential register writes hit something else 235 | Int#(10) wordCounterNext = (wordCounter==8) ? 0:((address==0 && writing) ? wordCounter+1:wordCounter); 236 | wordCounter <= wordCounterNext; 237 | 238 | Bit#(64) data = 64'h0123456789abcdef ^ zeroExtend(pack(tick)); 239 | Bool sof = (wordCounter == 0); 240 | Bool eof = (wordCounter == 3); 241 | Bit#(8) be = 8'h7b; 242 | if (address == 2) begin 243 | data[24] = pack(sof); 244 | data[25] = pack(eof); 245 | data[23:16] = be; 246 | end 247 | if (address == 3) begin 248 | data[0] = 1; 249 | end 250 | dut.mmSlave.avs(data, address, False, writing, 1, 0); 251 | writing <= !writing; 252 | if (writing) 253 | $display("%d: write request addr %x, BERI data=%x, avalon data=%x, sopin=%x, eopin=%x, bein=%x, wordCounter=%d", 254 | tick,address, data, byteSwap64(data), sof, eof, be, wordCounter); 255 | endrule 256 | 257 | rule readdata if (dut.mmSlave.avs_readdatavalid); 258 | $display("%d: read response %x", tick, dut.mmSlave.avs_readdata()); 259 | endrule 260 | 261 | // rule sink_out; 262 | // PCIeWord out <- dut.streamSink.receive.get(); 263 | // $display("%d: Output %x", tick, pack(out)); 264 | // endrule 265 | 266 | endmodule 267 | 268 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/qsys_ip/PCIePipes/mkPCIePacketReceiver.v: -------------------------------------------------------------------------------- 1 | // 2 | // Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21) 3 | // 4 | // On Wed Jan 2 22:34:26 GMT 2019 5 | // 6 | // 7 | // Ports: 8 | // Name I/O size props 9 | // streamSink_asi_ready O 1 10 | // mmSlave_avs_readdata O 64 11 | // mmSlave_avs_readdatavalid O 1 reg 12 | // mmSlave_avs_waitrequest O 1 13 | // CLK I 1 clock 14 | // RST_N I 1 reset 15 | // streamSink_asi_data I 64 reg 16 | // streamSink_asi_valid I 1 17 | // streamSink_asi_sop I 1 reg 18 | // streamSink_asi_eop I 1 reg 19 | // streamSink_asi_be I 8 reg 20 | // streamSink_asi_parity I 8 unused 21 | // streamSink_asi_bar I 8 unused 22 | // mmSlave_avs_writedata I 64 reg 23 | // mmSlave_avs_address I 8 reg 24 | // mmSlave_avs_read I 1 25 | // mmSlave_avs_write I 1 26 | // mmSlave_avs_byteenable I 8 reg 27 | // 28 | // No combinational paths from inputs to outputs 29 | // 30 | // 31 | 32 | `ifdef BSV_ASSIGNMENT_DELAY 33 | `else 34 | `define BSV_ASSIGNMENT_DELAY 35 | `endif 36 | 37 | `ifdef BSV_POSITIVE_RESET 38 | `define BSV_RESET_VALUE 1'b1 39 | `define BSV_RESET_EDGE posedge 40 | `else 41 | `define BSV_RESET_VALUE 1'b0 42 | `define BSV_RESET_EDGE negedge 43 | `endif 44 | 45 | module mkPCIePacketReceiver(CLK, 46 | RST_N, 47 | 48 | streamSink_asi_data, 49 | streamSink_asi_valid, 50 | streamSink_asi_sop, 51 | streamSink_asi_eop, 52 | streamSink_asi_be, 53 | streamSink_asi_parity, 54 | streamSink_asi_bar, 55 | 56 | streamSink_asi_ready, 57 | 58 | mmSlave_avs_readdata, 59 | 60 | mmSlave_avs_readdatavalid, 61 | 62 | mmSlave_avs_waitrequest, 63 | 64 | mmSlave_avs_writedata, 65 | mmSlave_avs_address, 66 | mmSlave_avs_read, 67 | mmSlave_avs_write, 68 | mmSlave_avs_byteenable); 69 | input CLK; 70 | input RST_N; 71 | 72 | // action method streamSink_asi 73 | input [63 : 0] streamSink_asi_data; 74 | input streamSink_asi_valid; 75 | input streamSink_asi_sop; 76 | input streamSink_asi_eop; 77 | input [7 : 0] streamSink_asi_be; 78 | input [7 : 0] streamSink_asi_parity; 79 | input [7 : 0] streamSink_asi_bar; 80 | 81 | // value method streamSink_asi_ready 82 | output streamSink_asi_ready; 83 | 84 | // value method mmSlave_avs_readdata 85 | output [63 : 0] mmSlave_avs_readdata; 86 | 87 | // value method mmSlave_avs_readdatavalid 88 | output mmSlave_avs_readdatavalid; 89 | 90 | // value method mmSlave_avs_waitrequest 91 | output mmSlave_avs_waitrequest; 92 | 93 | // action method mmSlave_avs 94 | input [63 : 0] mmSlave_avs_writedata; 95 | input [7 : 0] mmSlave_avs_address; 96 | input mmSlave_avs_read; 97 | input mmSlave_avs_write; 98 | input [7 : 0] mmSlave_avs_byteenable; 99 | 100 | // signals for module outputs 101 | wire [63 : 0] mmSlave_avs_readdata; 102 | wire mmSlave_avs_readdatavalid, 103 | mmSlave_avs_waitrequest, 104 | streamSink_asi_ready; 105 | 106 | // register currentpcieword 107 | reg [80 : 0] currentpcieword; 108 | wire [80 : 0] currentpcieword$D_IN; 109 | wire currentpcieword$EN; 110 | 111 | // register dwordCounter 112 | reg [9 : 0] dwordCounter; 113 | wire [9 : 0] dwordCounter$D_IN; 114 | wire dwordCounter$EN; 115 | 116 | // register fourDWord 117 | reg fourDWord; 118 | wire fourDWord$D_IN, fourDWord$EN; 119 | 120 | // register next 121 | reg next; 122 | wire next$D_IN, next$EN; 123 | 124 | // ports of submodule rxfifo 125 | wire [80 : 0] rxfifo$D_IN, rxfifo$D_OUT; 126 | wire rxfifo$CLR, rxfifo$DEQ, rxfifo$EMPTY_N, rxfifo$ENQ, rxfifo$FULL_N; 127 | 128 | // ports of submodule slave_req 129 | wire [80 : 0] slave_req$D_IN, slave_req$D_OUT; 130 | wire slave_req$CLR, 131 | slave_req$DEQ, 132 | slave_req$EMPTY_N, 133 | slave_req$ENQ, 134 | slave_req$FULL_N; 135 | 136 | // ports of submodule streamToFIFO_queue 137 | wire [80 : 0] streamToFIFO_queue$D_IN, streamToFIFO_queue$D_OUT; 138 | wire streamToFIFO_queue$CLR, 139 | streamToFIFO_queue$DEQ, 140 | streamToFIFO_queue$EMPTY_N, 141 | streamToFIFO_queue$ENQ, 142 | streamToFIFO_queue$FULL_N; 143 | 144 | // rule scheduling signals 145 | wire CAN_FIRE_RL_fetchpcieword, 146 | CAN_FIRE_RL_nextprint, 147 | CAN_FIRE_RL_serviceMMSlave, 148 | CAN_FIRE_mmSlave_avs, 149 | CAN_FIRE_streamSink_asi, 150 | WILL_FIRE_RL_fetchpcieword, 151 | WILL_FIRE_RL_nextprint, 152 | WILL_FIRE_RL_serviceMMSlave, 153 | WILL_FIRE_mmSlave_avs, 154 | WILL_FIRE_streamSink_asi; 155 | 156 | // remaining internal signals 157 | reg [63 : 0] v__h733; 158 | wire [63 : 0] response__h892, response__h902; 159 | 160 | // action method streamSink_asi 161 | assign CAN_FIRE_streamSink_asi = 1'd1 ; 162 | assign WILL_FIRE_streamSink_asi = 1'd1 ; 163 | 164 | // value method streamSink_asi_ready 165 | assign streamSink_asi_ready = streamToFIFO_queue$FULL_N ; 166 | 167 | // value method mmSlave_avs_readdata 168 | assign mmSlave_avs_readdata = 169 | slave_req$D_OUT[80] ? 64'hFEEB1EC0FFEEFEED : v__h733 ; 170 | 171 | // value method mmSlave_avs_readdatavalid 172 | assign mmSlave_avs_readdatavalid = slave_req$EMPTY_N ; 173 | 174 | // value method mmSlave_avs_waitrequest 175 | assign mmSlave_avs_waitrequest = !slave_req$FULL_N ; 176 | 177 | // action method mmSlave_avs 178 | assign CAN_FIRE_mmSlave_avs = 1'd1 ; 179 | assign WILL_FIRE_mmSlave_avs = 1'd1 ; 180 | 181 | // submodule rxfifo 182 | SizedFIFO #(.p1width(32'd81), 183 | .p2depth(32'd1024), 184 | .p3cntr_width(32'd10), 185 | .guarded(32'd0)) rxfifo(.RST(RST_N), 186 | .CLK(CLK), 187 | .D_IN(rxfifo$D_IN), 188 | .ENQ(rxfifo$ENQ), 189 | .DEQ(rxfifo$DEQ), 190 | .CLR(rxfifo$CLR), 191 | .D_OUT(rxfifo$D_OUT), 192 | .FULL_N(rxfifo$FULL_N), 193 | .EMPTY_N(rxfifo$EMPTY_N)); 194 | 195 | // submodule slave_req 196 | FIFOL1 #(.width(32'd81)) slave_req(.RST(RST_N), 197 | .CLK(CLK), 198 | .D_IN(slave_req$D_IN), 199 | .ENQ(slave_req$ENQ), 200 | .DEQ(slave_req$DEQ), 201 | .CLR(slave_req$CLR), 202 | .D_OUT(slave_req$D_OUT), 203 | .FULL_N(slave_req$FULL_N), 204 | .EMPTY_N(slave_req$EMPTY_N)); 205 | 206 | // submodule streamToFIFO_queue 207 | FIFOL1 #(.width(32'd81)) streamToFIFO_queue(.RST(RST_N), 208 | .CLK(CLK), 209 | .D_IN(streamToFIFO_queue$D_IN), 210 | .ENQ(streamToFIFO_queue$ENQ), 211 | .DEQ(streamToFIFO_queue$DEQ), 212 | .CLR(streamToFIFO_queue$CLR), 213 | .D_OUT(streamToFIFO_queue$D_OUT), 214 | .FULL_N(streamToFIFO_queue$FULL_N), 215 | .EMPTY_N(streamToFIFO_queue$EMPTY_N)); 216 | 217 | // rule RL_serviceMMSlave 218 | assign CAN_FIRE_RL_serviceMMSlave = slave_req$EMPTY_N ; 219 | assign WILL_FIRE_RL_serviceMMSlave = slave_req$EMPTY_N ; 220 | 221 | // rule RL_nextprint 222 | assign CAN_FIRE_RL_nextprint = 1'd1 ; 223 | assign WILL_FIRE_RL_nextprint = 1'd1 ; 224 | 225 | // rule RL_fetchpcieword 226 | assign CAN_FIRE_RL_fetchpcieword = streamToFIFO_queue$EMPTY_N ; 227 | assign WILL_FIRE_RL_fetchpcieword = streamToFIFO_queue$EMPTY_N ; 228 | 229 | // register currentpcieword 230 | assign currentpcieword$D_IN = 81'h0 ; 231 | assign currentpcieword$EN = 1'b0 ; 232 | 233 | // register dwordCounter 234 | assign dwordCounter$D_IN = 10'h0 ; 235 | assign dwordCounter$EN = 1'b0 ; 236 | 237 | // register fourDWord 238 | assign fourDWord$D_IN = 1'b0 ; 239 | assign fourDWord$EN = 1'b0 ; 240 | 241 | // register next 242 | assign next$D_IN = 1'd0 ; 243 | assign next$EN = streamToFIFO_queue$EMPTY_N ; 244 | 245 | // submodule rxfifo 246 | assign rxfifo$D_IN = streamToFIFO_queue$D_OUT ; 247 | assign rxfifo$ENQ = streamToFIFO_queue$EMPTY_N && rxfifo$FULL_N ; 248 | assign rxfifo$DEQ = 249 | slave_req$EMPTY_N && !slave_req$D_OUT[80] && 250 | slave_req$D_OUT[15:8] == 8'd0 && 251 | rxfifo$EMPTY_N ; 252 | assign rxfifo$CLR = 1'b0 ; 253 | 254 | // submodule slave_req 255 | assign slave_req$D_IN = 256 | { !mmSlave_avs_read, 257 | mmSlave_avs_writedata, 258 | mmSlave_avs_address, 259 | mmSlave_avs_byteenable } ; 260 | assign slave_req$ENQ = mmSlave_avs_read || mmSlave_avs_write ; 261 | assign slave_req$DEQ = slave_req$EMPTY_N ; 262 | assign slave_req$CLR = 1'b0 ; 263 | 264 | // submodule streamToFIFO_queue 265 | assign streamToFIFO_queue$D_IN = 266 | { streamSink_asi_sop, 267 | streamSink_asi_eop, 268 | 7'd0, 269 | streamSink_asi_be, 270 | streamSink_asi_data } ; 271 | assign streamToFIFO_queue$ENQ = 272 | streamSink_asi_valid && streamToFIFO_queue$FULL_N ; 273 | assign streamToFIFO_queue$DEQ = streamToFIFO_queue$EMPTY_N ; 274 | assign streamToFIFO_queue$CLR = 1'b0 ; 275 | 276 | // remaining internal signals 277 | assign response__h892 = 278 | { rxfifo$D_OUT[79] ? 8'hEE : 8'h0, 279 | rxfifo$D_OUT[80] ? 8'h55 : 8'h0, 280 | 22'b0, 281 | rxfifo$D_OUT[79], 282 | rxfifo$D_OUT[80], 283 | rxfifo$D_OUT[71:64], 284 | 16'd0 } ; 285 | assign response__h902 = {64{rxfifo$EMPTY_N}} ; 286 | always@(slave_req$D_OUT or rxfifo$D_OUT or response__h892 or response__h902) 287 | begin 288 | case (slave_req$D_OUT[15:8]) 289 | 8'd0, 8'd1: v__h733 = rxfifo$D_OUT[63:0]; 290 | 8'd2: v__h733 = response__h892; 291 | 8'd3: v__h733 = response__h902; 292 | default: v__h733 = 64'hDEADFACEBEEFCAFE; 293 | endcase 294 | end 295 | 296 | // handling of inlined registers 297 | 298 | always@(posedge CLK) 299 | begin 300 | if (RST_N == `BSV_RESET_VALUE) 301 | begin 302 | currentpcieword <= `BSV_ASSIGNMENT_DELAY 81'd0; 303 | dwordCounter <= `BSV_ASSIGNMENT_DELAY 10'h0; 304 | fourDWord <= `BSV_ASSIGNMENT_DELAY 1'd1; 305 | next <= `BSV_ASSIGNMENT_DELAY 1'd1; 306 | end 307 | else 308 | begin 309 | if (currentpcieword$EN) 310 | currentpcieword <= `BSV_ASSIGNMENT_DELAY currentpcieword$D_IN; 311 | if (dwordCounter$EN) 312 | dwordCounter <= `BSV_ASSIGNMENT_DELAY dwordCounter$D_IN; 313 | if (fourDWord$EN) fourDWord <= `BSV_ASSIGNMENT_DELAY fourDWord$D_IN; 314 | if (next$EN) next <= `BSV_ASSIGNMENT_DELAY next$D_IN; 315 | end 316 | end 317 | 318 | // synopsys translate_off 319 | `ifdef BSV_NO_INITIAL_BLOCKS 320 | `else // not BSV_NO_INITIAL_BLOCKS 321 | initial 322 | begin 323 | currentpcieword = 81'h0AAAAAAAAAAAAAAAAAAAA; 324 | dwordCounter = 10'h2AA; 325 | fourDWord = 1'h0; 326 | next = 1'h0; 327 | end 328 | `endif // BSV_NO_INITIAL_BLOCKS 329 | // synopsys translate_on 330 | 331 | // handling of system tasks 332 | 333 | // synopsys translate_off 334 | always@(negedge CLK) 335 | begin 336 | #0; 337 | if (RST_N != `BSV_RESET_VALUE) if (slave_req$EMPTY_N) $display("request"); 338 | if (RST_N != `BSV_RESET_VALUE) 339 | if (slave_req$EMPTY_N && slave_req$D_OUT[80]) 340 | $display("write %x", slave_req$D_OUT[15:8]); 341 | if (RST_N != `BSV_RESET_VALUE) 342 | if (slave_req$EMPTY_N && !slave_req$D_OUT[80]) 343 | $display("read %x", slave_req$D_OUT[15:8]); 344 | if (RST_N != `BSV_RESET_VALUE) 345 | if (slave_req$EMPTY_N && !slave_req$D_OUT[80] && 346 | slave_req$D_OUT[15:8] == 8'd0) 347 | $display("trigger pcieword=%x", rxfifo$D_OUT); 348 | if (RST_N != `BSV_RESET_VALUE) 349 | $display("next=%d, rxfifo.empty=%d", next, !rxfifo$EMPTY_N); 350 | if (RST_N != `BSV_RESET_VALUE) 351 | if (streamToFIFO_queue$EMPTY_N && rxfifo$FULL_N) 352 | $display("PCIe word[%d] arrived as %x, swapped into %x, 4DWordTLP=%x, sof=%d, eof=%d, be.in=%x, be.swapped=%x", 353 | $unsigned(dwordCounter), 354 | streamToFIFO_queue$D_OUT, 355 | streamToFIFO_queue$D_OUT, 356 | fourDWord, 357 | streamToFIFO_queue$D_OUT[80], 358 | streamToFIFO_queue$D_OUT[79], 359 | streamToFIFO_queue$D_OUT[71:64], 360 | streamToFIFO_queue$D_OUT[71:64]); 361 | if (RST_N != `BSV_RESET_VALUE) 362 | if (streamToFIFO_queue$EMPTY_N && !rxfifo$FULL_N) $display("junked"); 363 | end 364 | // synopsys translate_on 365 | endmodule // mkPCIePacketReceiver 366 | 367 | -------------------------------------------------------------------------------- /pcie-bsv/bsv/qsys_ip/PCIePipes/mkPCIePacketTransmitter.v: -------------------------------------------------------------------------------- 1 | // 2 | // Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21) 3 | // 4 | // On Wed Jan 2 22:34:28 GMT 2019 5 | // 6 | // 7 | // Ports: 8 | // Name I/O size props 9 | // streamSource_aso_data O 64 10 | // streamSource_aso_valid O 1 11 | // streamSource_aso_sop O 1 12 | // streamSource_aso_eop O 1 13 | // streamSource_aso_be O 8 14 | // streamSource_aso_parity O 8 const 15 | // streamSource_aso_bar O 8 const 16 | // streamSource_aso_err O 1 const 17 | // mmSlave_avs_readdata O 64 18 | // mmSlave_avs_readdatavalid O 1 reg 19 | // mmSlave_avs_waitrequest O 1 20 | // CLK I 1 clock 21 | // RST_N I 1 reset 22 | // streamSource_aso_ready I 1 23 | // mmSlave_avs_writedata I 64 reg 24 | // mmSlave_avs_address I 8 reg 25 | // mmSlave_avs_read I 1 26 | // mmSlave_avs_write I 1 27 | // mmSlave_avs_byteenable I 8 reg 28 | // 29 | // Combinational paths from inputs to outputs: 30 | // streamSource_aso_ready -> streamSource_aso_data 31 | // streamSource_aso_ready -> streamSource_aso_valid 32 | // streamSource_aso_ready -> streamSource_aso_sop 33 | // streamSource_aso_ready -> streamSource_aso_eop 34 | // streamSource_aso_ready -> streamSource_aso_be 35 | // 36 | // 37 | 38 | `ifdef BSV_ASSIGNMENT_DELAY 39 | `else 40 | `define BSV_ASSIGNMENT_DELAY 41 | `endif 42 | 43 | `ifdef BSV_POSITIVE_RESET 44 | `define BSV_RESET_VALUE 1'b1 45 | `define BSV_RESET_EDGE posedge 46 | `else 47 | `define BSV_RESET_VALUE 1'b0 48 | `define BSV_RESET_EDGE negedge 49 | `endif 50 | 51 | module mkPCIePacketTransmitter(CLK, 52 | RST_N, 53 | 54 | streamSource_aso_ready, 55 | 56 | streamSource_aso_data, 57 | 58 | streamSource_aso_valid, 59 | 60 | streamSource_aso_sop, 61 | 62 | streamSource_aso_eop, 63 | 64 | streamSource_aso_be, 65 | 66 | streamSource_aso_parity, 67 | 68 | streamSource_aso_bar, 69 | 70 | streamSource_aso_err, 71 | 72 | mmSlave_avs_readdata, 73 | 74 | mmSlave_avs_readdatavalid, 75 | 76 | mmSlave_avs_waitrequest, 77 | 78 | mmSlave_avs_writedata, 79 | mmSlave_avs_address, 80 | mmSlave_avs_read, 81 | mmSlave_avs_write, 82 | mmSlave_avs_byteenable); 83 | input CLK; 84 | input RST_N; 85 | 86 | // action method streamSource_aso 87 | input streamSource_aso_ready; 88 | 89 | // value method streamSource_aso_data 90 | output [63 : 0] streamSource_aso_data; 91 | 92 | // value method streamSource_aso_valid 93 | output streamSource_aso_valid; 94 | 95 | // value method streamSource_aso_sop 96 | output streamSource_aso_sop; 97 | 98 | // value method streamSource_aso_eop 99 | output streamSource_aso_eop; 100 | 101 | // value method streamSource_aso_be 102 | output [7 : 0] streamSource_aso_be; 103 | 104 | // value method streamSource_aso_parity 105 | output [7 : 0] streamSource_aso_parity; 106 | 107 | // value method streamSource_aso_bar 108 | output [7 : 0] streamSource_aso_bar; 109 | 110 | // value method streamSource_aso_err 111 | output streamSource_aso_err; 112 | 113 | // value method mmSlave_avs_readdata 114 | output [63 : 0] mmSlave_avs_readdata; 115 | 116 | // value method mmSlave_avs_readdatavalid 117 | output mmSlave_avs_readdatavalid; 118 | 119 | // value method mmSlave_avs_waitrequest 120 | output mmSlave_avs_waitrequest; 121 | 122 | // action method mmSlave_avs 123 | input [63 : 0] mmSlave_avs_writedata; 124 | input [7 : 0] mmSlave_avs_address; 125 | input mmSlave_avs_read; 126 | input mmSlave_avs_write; 127 | input [7 : 0] mmSlave_avs_byteenable; 128 | 129 | // signals for module outputs 130 | wire [63 : 0] mmSlave_avs_readdata, streamSource_aso_data; 131 | wire [7 : 0] streamSource_aso_bar, 132 | streamSource_aso_be, 133 | streamSource_aso_parity; 134 | wire mmSlave_avs_readdatavalid, 135 | mmSlave_avs_waitrequest, 136 | streamSource_aso_eop, 137 | streamSource_aso_err, 138 | streamSource_aso_sop, 139 | streamSource_aso_valid; 140 | 141 | // inlined wires 142 | wire [81 : 0] fifoToStream_data$wget; 143 | wire fifoToStream_data$whas; 144 | 145 | // register currentpcieword 146 | reg [80 : 0] currentpcieword; 147 | reg [80 : 0] currentpcieword$D_IN; 148 | wire currentpcieword$EN; 149 | 150 | // register dwordCounter 151 | reg [9 : 0] dwordCounter; 152 | wire [9 : 0] dwordCounter$D_IN; 153 | wire dwordCounter$EN; 154 | 155 | // register fourDWord 156 | reg fourDWord; 157 | wire fourDWord$D_IN, fourDWord$EN; 158 | 159 | // register go 160 | reg go; 161 | wire go$D_IN, go$EN; 162 | 163 | // ports of submodule slave_req 164 | wire [80 : 0] slave_req$D_IN, slave_req$D_OUT; 165 | wire slave_req$CLR, 166 | slave_req$DEQ, 167 | slave_req$EMPTY_N, 168 | slave_req$ENQ, 169 | slave_req$FULL_N; 170 | 171 | // ports of submodule txfifo 172 | wire [80 : 0] txfifo$D_IN, txfifo$D_OUT; 173 | wire txfifo$CLR, txfifo$DEQ, txfifo$EMPTY_N, txfifo$ENQ, txfifo$FULL_N; 174 | 175 | // rule scheduling signals 176 | wire CAN_FIRE_RL_nextprint, 177 | CAN_FIRE_RL_sendpcieword, 178 | CAN_FIRE_RL_serviceMMSlave, 179 | CAN_FIRE_mmSlave_avs, 180 | CAN_FIRE_streamSource_aso, 181 | WILL_FIRE_RL_nextprint, 182 | WILL_FIRE_RL_sendpcieword, 183 | WILL_FIRE_RL_serviceMMSlave, 184 | WILL_FIRE_mmSlave_avs, 185 | WILL_FIRE_streamSource_aso; 186 | 187 | // action method streamSource_aso 188 | assign CAN_FIRE_streamSource_aso = 1'd1 ; 189 | assign WILL_FIRE_streamSource_aso = 1'd1 ; 190 | 191 | // value method streamSource_aso_data 192 | assign streamSource_aso_data = fifoToStream_data$wget[63:0] ; 193 | 194 | // value method streamSource_aso_valid 195 | assign streamSource_aso_valid = 196 | fifoToStream_data$whas && fifoToStream_data$wget[81] ; 197 | 198 | // value method streamSource_aso_sop 199 | assign streamSource_aso_sop = fifoToStream_data$wget[80] ; 200 | 201 | // value method streamSource_aso_eop 202 | assign streamSource_aso_eop = fifoToStream_data$wget[79] ; 203 | 204 | // value method streamSource_aso_be 205 | assign streamSource_aso_be = fifoToStream_data$wget[71:64] ; 206 | 207 | // value method streamSource_aso_parity 208 | assign streamSource_aso_parity = 8'd0 ; 209 | 210 | // value method streamSource_aso_bar 211 | assign streamSource_aso_bar = 8'd0 ; 212 | 213 | // value method streamSource_aso_err 214 | assign streamSource_aso_err = 1'd0 ; 215 | 216 | // value method mmSlave_avs_readdata 217 | assign mmSlave_avs_readdata = 218 | slave_req$D_OUT[80] ? 219 | 64'hDEADFACEBEEFCAFE : 220 | 64'hEEFFC0000CB0CEFA ; 221 | 222 | // value method mmSlave_avs_readdatavalid 223 | assign mmSlave_avs_readdatavalid = slave_req$EMPTY_N ; 224 | 225 | // value method mmSlave_avs_waitrequest 226 | assign mmSlave_avs_waitrequest = !slave_req$FULL_N ; 227 | 228 | // action method mmSlave_avs 229 | assign CAN_FIRE_mmSlave_avs = 1'd1 ; 230 | assign WILL_FIRE_mmSlave_avs = 1'd1 ; 231 | 232 | // submodule slave_req 233 | FIFOL1 #(.width(32'd81)) slave_req(.RST(RST_N), 234 | .CLK(CLK), 235 | .D_IN(slave_req$D_IN), 236 | .ENQ(slave_req$ENQ), 237 | .DEQ(slave_req$DEQ), 238 | .CLR(slave_req$CLR), 239 | .D_OUT(slave_req$D_OUT), 240 | .FULL_N(slave_req$FULL_N), 241 | .EMPTY_N(slave_req$EMPTY_N)); 242 | 243 | // submodule txfifo 244 | SizedFIFO #(.p1width(32'd81), 245 | .p2depth(32'd64), 246 | .p3cntr_width(32'd6), 247 | .guarded(32'd0)) txfifo(.RST(RST_N), 248 | .CLK(CLK), 249 | .D_IN(txfifo$D_IN), 250 | .ENQ(txfifo$ENQ), 251 | .DEQ(txfifo$DEQ), 252 | .CLR(txfifo$CLR), 253 | .D_OUT(txfifo$D_OUT), 254 | .FULL_N(txfifo$FULL_N), 255 | .EMPTY_N(txfifo$EMPTY_N)); 256 | 257 | // rule RL_sendpcieword 258 | assign CAN_FIRE_RL_sendpcieword = 259 | !txfifo$EMPTY_N || !go || streamSource_aso_ready ; 260 | assign WILL_FIRE_RL_sendpcieword = CAN_FIRE_RL_sendpcieword ; 261 | 262 | // rule RL_nextprint 263 | assign CAN_FIRE_RL_nextprint = 1'd1 ; 264 | assign WILL_FIRE_RL_nextprint = 1'd1 ; 265 | 266 | // rule RL_serviceMMSlave 267 | assign CAN_FIRE_RL_serviceMMSlave = slave_req$EMPTY_N ; 268 | assign WILL_FIRE_RL_serviceMMSlave = slave_req$EMPTY_N ; 269 | 270 | // inlined wires 271 | assign fifoToStream_data$wget = { 1'd1, txfifo$D_OUT } ; 272 | assign fifoToStream_data$whas = 273 | WILL_FIRE_RL_sendpcieword && txfifo$EMPTY_N && go ; 274 | 275 | // register currentpcieword 276 | always@(slave_req$D_OUT or currentpcieword) 277 | begin 278 | case (slave_req$D_OUT[15:8]) 279 | 8'd0, 8'd1: 280 | currentpcieword$D_IN = 281 | { currentpcieword[80:64], slave_req$D_OUT[79:16] }; 282 | default: currentpcieword$D_IN = 283 | { (slave_req$D_OUT[15:8] == 8'd2) ? 284 | slave_req$D_OUT[40] : 285 | currentpcieword[80], 286 | (slave_req$D_OUT[15:8] == 8'd2) ? 287 | slave_req$D_OUT[41] : 288 | currentpcieword[79], 289 | (slave_req$D_OUT[15:8] == 8'd2) ? 290 | 7'd0 : 291 | currentpcieword[78:72], 292 | (slave_req$D_OUT[15:8] == 8'd2) ? 293 | slave_req$D_OUT[39:32] : 294 | currentpcieword[71:64], 295 | currentpcieword[63:0] }; 296 | endcase 297 | end 298 | assign currentpcieword$EN = slave_req$EMPTY_N && slave_req$D_OUT[80] ; 299 | 300 | // register dwordCounter 301 | assign dwordCounter$D_IN = 10'h0 ; 302 | assign dwordCounter$EN = 1'b0 ; 303 | 304 | // register fourDWord 305 | assign fourDWord$D_IN = 1'b0 ; 306 | assign fourDWord$EN = 1'b0 ; 307 | 308 | // register go 309 | assign go$D_IN = slave_req$D_OUT[16] ; 310 | assign go$EN = 311 | slave_req$EMPTY_N && slave_req$D_OUT[80] && 312 | slave_req$D_OUT[15:8] == 8'd3 ; 313 | 314 | // submodule slave_req 315 | assign slave_req$D_IN = 316 | { !mmSlave_avs_read, 317 | mmSlave_avs_writedata, 318 | mmSlave_avs_address, 319 | mmSlave_avs_byteenable } ; 320 | assign slave_req$ENQ = mmSlave_avs_read || mmSlave_avs_write ; 321 | assign slave_req$DEQ = slave_req$EMPTY_N ; 322 | assign slave_req$CLR = 1'b0 ; 323 | 324 | // submodule txfifo 325 | assign txfifo$D_IN = { currentpcieword[80:64], slave_req$D_OUT[79:16] } ; 326 | assign txfifo$ENQ = 327 | slave_req$EMPTY_N && slave_req$D_OUT[80] && 328 | slave_req$D_OUT[15:8] == 8'd0 && 329 | txfifo$FULL_N ; 330 | assign txfifo$DEQ = fifoToStream_data$whas ; 331 | assign txfifo$CLR = 1'b0 ; 332 | 333 | // handling of inlined registers 334 | 335 | always@(posedge CLK) 336 | begin 337 | if (RST_N == `BSV_RESET_VALUE) 338 | begin 339 | currentpcieword <= `BSV_ASSIGNMENT_DELAY 81'd0; 340 | dwordCounter <= `BSV_ASSIGNMENT_DELAY 10'h0; 341 | fourDWord <= `BSV_ASSIGNMENT_DELAY 1'd1; 342 | go <= `BSV_ASSIGNMENT_DELAY 1'd0; 343 | end 344 | else 345 | begin 346 | if (currentpcieword$EN) 347 | currentpcieword <= `BSV_ASSIGNMENT_DELAY currentpcieword$D_IN; 348 | if (dwordCounter$EN) 349 | dwordCounter <= `BSV_ASSIGNMENT_DELAY dwordCounter$D_IN; 350 | if (fourDWord$EN) fourDWord <= `BSV_ASSIGNMENT_DELAY fourDWord$D_IN; 351 | if (go$EN) go <= `BSV_ASSIGNMENT_DELAY go$D_IN; 352 | end 353 | end 354 | 355 | // synopsys translate_off 356 | `ifdef BSV_NO_INITIAL_BLOCKS 357 | `else // not BSV_NO_INITIAL_BLOCKS 358 | initial 359 | begin 360 | currentpcieword = 81'h0AAAAAAAAAAAAAAAAAAAA; 361 | dwordCounter = 10'h2AA; 362 | fourDWord = 1'h0; 363 | go = 1'h0; 364 | end 365 | `endif // BSV_NO_INITIAL_BLOCKS 366 | // synopsys translate_on 367 | 368 | // handling of system tasks 369 | 370 | // synopsys translate_off 371 | always@(negedge CLK) 372 | begin 373 | #0; 374 | if (RST_N != `BSV_RESET_VALUE) 375 | if (WILL_FIRE_RL_sendpcieword && txfifo$EMPTY_N && go) 376 | $display("PCIe word[%d] received from MM=%x, sent swapped=%x", 377 | $unsigned(dwordCounter), 378 | txfifo$D_OUT, 379 | txfifo$D_OUT); 380 | if (RST_N != `BSV_RESET_VALUE) 381 | $display("go=%d, txfifo.empty=%d, txfifo.full=%d", 382 | go, 383 | !txfifo$EMPTY_N, 384 | !txfifo$FULL_N); 385 | if (RST_N != `BSV_RESET_VALUE) if (slave_req$EMPTY_N) $display("request"); 386 | if (RST_N != `BSV_RESET_VALUE) 387 | if (slave_req$EMPTY_N && slave_req$D_OUT[80]) 388 | $display("write %x", slave_req$D_OUT[15:8]); 389 | if (RST_N != `BSV_RESET_VALUE) 390 | if (slave_req$EMPTY_N && slave_req$D_OUT[80] && 391 | slave_req$D_OUT[15:8] == 8'd0 && 392 | txfifo$FULL_N) 393 | $display("txfifo enqueued %x", 394 | { currentpcieword[80:64], slave_req$D_OUT[79:16] }); 395 | if (RST_N != `BSV_RESET_VALUE) 396 | if (slave_req$EMPTY_N && slave_req$D_OUT[80] && 397 | slave_req$D_OUT[15:8] == 8'd2) 398 | $display("Framing bits written: sofreg=%d, eofreg=%d, bereg=%x", 399 | slave_req$D_OUT[40], 400 | slave_req$D_OUT[41], 401 | slave_req$D_OUT[39:32]); 402 | if (RST_N != `BSV_RESET_VALUE) 403 | if (slave_req$EMPTY_N && !slave_req$D_OUT[80]) 404 | $display("read %x", slave_req$D_OUT[15:8]); 405 | end 406 | // synopsys translate_on 407 | endmodule // mkPCIePacketTransmitter 408 | 409 | -------------------------------------------------------------------------------- /pcie-bsv/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # Makefile to build an Altera FPGA system designed in Qsys and Quartus 3 | ############################################################################## 4 | # Updated and tested on Quartus 13.0.1 5 | # 6 | # Notes: 7 | # - Use the IDEs (Quartus and Qsys) to setup the system including 8 | # various parameters. 9 | # - Use Quartus IDE to generate the programming chain file (.cdf) using 10 | # the graphical download tool 11 | # - This makefile is more of a build script, i.e. it does not do incremental 12 | # builds but is useful to build everything 13 | 14 | # The following six envrionment variables are project specific 15 | SHELL=bash 16 | QUARTUS_PROJECT=PCIe_Fundamental 17 | QUARTUS_PROJECT_VERSION=PCIe_Fundamental 18 | QSYS_PROJECT=pcie_de_gen1_x4_ast64 19 | FPGA="Stratix V" 20 | # Version of Quartus this has been tested on: 21 | QUARTUS_VERSION?='15.0' 22 | # User specific temporary area to avoid collisions 23 | TEMP=/tmp/$(USER) 24 | TMP=$(TEMP) 25 | # Bluespec standard Verilog libraries from BLUESPECDIR environment variable 26 | BLUESPEC_VERILOG=$(BLUESPECDIR)/Verilog 27 | # CHERI build specific: 28 | ifdef CHERI2 29 | CHERI_DIR=../../../../cheri2/trunk/ 30 | else 31 | CHERI_DIR=../../ 32 | endif 33 | # project specific peripherals for Qsys 34 | CHERILIBSDIR=../../../../cherilibs/trunk 35 | TOOLS_DIR=$(CHERILIBSDIR)/tools/ 36 | PERIPHERALS_DIR=bsv/MMRingBuffer 37 | # software for boot rom 38 | MINIBOOT_DIR=../../../../cheribsd/trunk/miniboot/ 39 | 40 | # define MICRO to build a TLB-less, L2-less CHERI 41 | # MICRO=Yes 42 | 43 | # define DIMM=4 to build with timing for a Micron/Crucial 4GB DIMM 44 | # note this just affects timing, not memory size 45 | ifndef DIMM 46 | DIMM=1 47 | endif 48 | 49 | # configuration files critical to the design: 50 | QUARTUS_CONFIG=$(QUARTUS_PROJECT).qpf $(wildcard *.sdc) 51 | # Qsys project source 52 | ifdef PCIEXPRESS 53 | QSYS_TEMPLATE=$(QSYS_PROJECT)_pciexpress_template 54 | else 55 | ifeq ($(MULTI),2) 56 | QSYS_TEMPLATE=$(QSYS_PROJECT)_dualcore_template 57 | else 58 | QSYS_TEMPLATE=$(QSYS_PROJECT)_template 59 | endif 60 | endif 61 | QSYS_GENERATED=$(QSYS_PROJECT) 62 | QSYS_PROJECT_SRCS=$(QSYS_PROJECT).qsys 63 | 64 | # derived variables 65 | QSYS_GENERATED_FILES=$(QSYS_PROJECT).sopcinfo PLLJ_PLLSPE_INFO.txt DE4_SOC_ddr2_p0_summary.csv $(QSYS_PROJECT_SRCS) 66 | QSYS_SYNTHESIS_DIR=./$(QSYS_PROJECT)/synthesis/ 67 | MEGAWIZARD_GENERATED_FILES=pll125.v pll125_bb.v pll125.qif display_pll.v display_pll_bb.v display_pll.qip \ 68 | pll_125_bb.v pll_125.bsf pll_125.ppf pll_125.qip pll_125.v display_pll.ppf 69 | 70 | QUARTUS_GENERATED_DIRS=incremental_db db output_files output_files_nodip output_files_default DE4_SOC 71 | 72 | .PHONY : all 73 | all : start_msg check_env temp patch_cheri2 build_cheri build_peripherals build_qsys build_fpga report_critical report_fmax report_error end_msg 74 | 75 | .PHONY : start_msg 76 | start_msg: 77 | @echo "**********************************************************************" 78 | @echo "* Build started at `date`" 79 | @echo "**********************************************************************" 80 | 81 | .PHONY : end_msg 82 | end_msg: 83 | @echo "**********************************************************************" 84 | @echo "* Build ended at `date`" 85 | @echo "**********************************************************************" 86 | 87 | .PHONY : check_env 88 | check_env: 89 | @(/usr/bin/xdpyinfo > /dev/null || (echo "ERROR: X11 display must be active for this build to complete." ; echo "Use VNC or Xvfb if you aren't on an X-enabled machine" && false)) 90 | @((quartus_map --version | grep 'Version '$(QUARTUS_VERSION)) || ((echo "ERROR: this build has been tested against Quartus "$(QUARTUS_VERSION)" but you have version"; quartus_map --version) && false)) 91 | 92 | .PHONY : temp 93 | temp: 94 | mkdir -p $(TEMP) 95 | 96 | CHERI_CONFIG_VARS := 97 | VERILOG_DEFINES := 98 | ifdef CHERI2 99 | # be sure to include a debug unit on cheri2 as it is not on by default 100 | CHERI_CONFIG_VARS += DEBUG=t 101 | endif 102 | ifdef CAP 103 | CHERI_CONFIG_VARS += CAP=t 104 | endif 105 | ifdef MULTI 106 | CHERI_CONFIG_VARS += MULTI=$(MULTI) 107 | endif 108 | ifdef GENERICL1 109 | CHERI_CONFIG_VARS += GENERICL1=1 110 | endif 111 | ifdef WITH_NOCACHE 112 | CHERI_CONFIG_VARS += WITH_NOCACHE=t 113 | endif 114 | ifdef MICRO 115 | CHERI_CONFIG_VARS += MICRO=t 116 | endif 117 | ifdef NOBRANCH 118 | CHERI_CONFIG_VARS += NOBRANCH=t 119 | endif 120 | ifdef HARDCALL 121 | CHERI_CONFIG_VARS += HARDCALL=t 122 | endif 123 | ifdef COP1 124 | CHERI_CONFIG_VARS += COP1=t 125 | endif 126 | ifdef TRACE 127 | CHERI_CONFIG_VARS += TRACE=t 128 | endif 129 | ifdef PCIEXPRESS 130 | CHERI_CONFIG_VARS += PCIEXPRESS=t 131 | VERILOG_DEFINES += --verilog_macro="ENABLE_PCIE=t" 132 | endif 133 | ifdef DMA 134 | CHERI_CONFIG_VARS += DMA=1 135 | endif 136 | 137 | # Patch files for cheri2 build. Note that we set the timestamps on 138 | # patched files so that we can later detect if they are modified and 139 | # refuse to overwrite. 140 | .PHONY : patch_cheri2 141 | patch_cheri2: 142 | ifdef CHERI2 143 | @if [ -z "$$(ls | grep '.*original')" ]; then \ 144 | echo "**********************************************************************"; \ 145 | echo "* Patching files for cheri2 build. "; \ 146 | echo "**********************************************************************"; \ 147 | patch -p5 --backup --suffix .original < cheri2.patch; \ 148 | ls | grep '.*original' | while read orig_file; do \ 149 | touch "$$orig_file" "$${orig_file/.original/}" ; \ 150 | done ; \ 151 | else \ 152 | echo "**********************************************************************"; \ 153 | echo "* Detected cheri2 patches already patched. "; \ 154 | echo "**********************************************************************"; \ 155 | fi 156 | else 157 | @true 158 | endif 159 | 160 | .PHONY : build_cheri build_beri build_processor 161 | 162 | build_processor: build_cheri 163 | 164 | build_beri: build_cheri 165 | 166 | build_cheri: 167 | # @echo "**********************************************************************" 168 | # @echo "* Build Processor Bluespec in " $(CHERI_DIR) 169 | # @echo "**********************************************************************" 170 | # $(MAKE) -C $(CHERI_DIR) verilog $(CHERI_CONFIG_VARS) 171 | 172 | .PHONY : build_peripherals 173 | build_peripherals: 174 | @echo "**********************************************************************" 175 | @echo "* Build Peripherals in " $(PERIPHERALS_DIR) 176 | @echo "**********************************************************************" 177 | $(MAKE) -C $(PERIPHERALS_DIR) 178 | 179 | .PHONY : build_miniboot 180 | build_miniboot: 181 | ifdef MICRO 182 | # Micro CHERI without TLB won't run FreeBSD, so include bare metal code instead 183 | # of miniboot 184 | @echo "**********************************************************************" 185 | @echo "* Build bare metal code ROM (mem64.hex) in " $(CHERI_DIR)/sw 186 | @echo "**********************************************************************" 187 | $(MAKE) -C $(CHERI_DIR)/sw verilog 188 | cp $(CHERI_DIR)/sw/mem64.hex ./ 189 | else 190 | @echo "**********************************************************************" 191 | @echo "* Build miniboot ROM (mem64.hex) in " $(MINIBOOT_DIR) 192 | @echo "**********************************************************************" 193 | $(MAKE) -C $(MINIBOOT_DIR) 194 | cp $(MINIBOOT_DIR)/mem64.hex ./ 195 | $(MAKE) -C $(MINIBOOT_DIR) clean 196 | $(MAKE) -C $(MINIBOOT_DIR) ALWAYS_WAIT=yesplease 197 | cp $(MINIBOOT_DIR)/mem64.hex ./mem64-nodip.hex 198 | endif 199 | 200 | # Force version.hex to be regenerated for every build. 201 | .PHONY: version.hex 202 | version.hex: 203 | @echo "**********************************************************************" 204 | @echo "* Generate version.hex" 205 | @echo "**********************************************************************" 206 | tclsh $(TOOLS_DIR)/versionHexGenerate.tcl 207 | 208 | ifdef MULTI 209 | DTS_CPP_FLAGS+= -DMULTI=$(MULTI) 210 | endif 211 | ifdef THREADSZ 212 | DTS_CPP_FLAGS+= -DTHREADSZ=$(THREADSZ) 213 | endif 214 | 215 | 216 | .PHONY : build_qsys 217 | build_qsys: check_env check_bash 218 | @echo "**********************************************************************" 219 | @echo "* Qsys generation" 220 | @echo "**********************************************************************" 221 | #rm $(QSYS_PROJECT).qsys 222 | # patch the Qsys project with various changes we have to make 223 | qsys-generate -syn $(QSYS_PROJECT).qsys 224 | # perl fixup_qsys.pl $(DIMM) `cat $(CHERI_DIR)/ip_name.txt` $(QSYS_TEMPLATE).qsys $(QSYS_GENERATED).qsys 225 | # ip-generate \ 226 | # --report-file=bsf:./output_files/$(QSYS_PROJECT).bsf \ 227 | # --standard-reports \ 228 | # --system-info=DEVICE_FAMILY=$(FPGA) \ 229 | # --output-directory=$(QSYS_SYNTHESIS_DIR) \ 230 | # --project-directory=./ \ 231 | # --file-set=QUARTUS_SYNTH \ 232 | # --component-file=$(QSYS_GENERATED).qsys 233 | 234 | .PHONY : check_bash 235 | check_bash: 236 | @[ -L /bin/sh ] && [ `/bin/readlink /bin/sh` = bash ] && \ 237 | (echo "Info: /bin/sh -> bash") || \ 238 | (echo "**** WARNING /bin/sh isn't a link to bash which may cause Qsys scripts to fail") 239 | 240 | .PHONY : build_fpga 241 | .DELETE_ON_ERROR: output_files/$(QSYS_PROJECT_VERSION).sof 242 | build_fpga: build_qsys build_peripherals 243 | @echo "**********************************************************************" 244 | @echo "* Synthesis run started to generate" output_files/$(QUARTUS_PROJECT_VERSION).sof 245 | @echo "**********************************************************************" 246 | quartus_map --read_settings_files=on --write_settings_files=off $(QUARTUS_PROJECT) -c $(QUARTUS_PROJECT_VERSION) -l $(BLUESPEC_VERILOG) $(VERILOG_DEFINES) 247 | # REMOVE: -l $(QSYS_PROJECT)/synthesis -l $(QSYS_PROJECT_SUBMODULES) -l $(BLUESPEC_VERILOG) 248 | quartus_cdb --read_settings_files=off --write_settings_files=off $(QUARTUS_PROJECT) -c $(QUARTUS_PROJECT_VERSION) --merge=on 249 | quartus_fit --read_settings_files=off --write_settings_files=off $(QUARTUS_PROJECT) -c $(QUARTUS_PROJECT_VERSION) 250 | quartus_sta $(QUARTUS_PROJECT) -c $(QUARTUS_PROJECT_VERSION) 251 | quartus_asm --read_settings_files=off --write_settings_files=off $(QUARTUS_PROJECT) -c $(QUARTUS_PROJECT_VERSION) 252 | # cp $(QSYS_SYNTHESIS_DIR)/*.sopcinfo . 253 | 254 | # REMOVE: quartus_sh --flow compile $(QUARTUS_PROJECT_VERSION) 255 | 256 | .PHONY : report_fmax 257 | report_fmax: 258 | # @echo "**********************************************************************" 259 | # @echo "* Reporting Fmax summary" 260 | # @echo "**********************************************************************" 261 | # @grep -B3 -A20 "Restricted Fmax" output_files/DE4_BERI.sta.rpt 262 | 263 | .PHONY : report_timing_stats 264 | report_timing_stats: 265 | # @echo "**********************************************************************" 266 | # @echo "* Reporting timing stats" 267 | # @echo "**********************************************************************" 268 | # quartus_sta -t $(TOOLS_DIR)/timequest_csv.tcl \ 269 | # $(QUARTUS_PROJECT) output_files/fmax.csv output_files/slack.csv \ 270 | # output_files/jenkins_fmax.csv output_files/jenkins_slack.csv "DE4_SOC_inst|ddr2|pll0|upll_memphy|auto_generated|pll1|clk[4]" 900 271 | # quartus_sta -t $(TOOLS_DIR)/timequest_csv.tcl \ 272 | # $(QUARTUS_PROJECT) output_files/fmax.csv output_files/slack.csv \ 273 | # output_files/jenkins_mem_fmax.csv output_files/jenkins_mem_slack.csv "DE4_SOC_inst|ddr2|pll0|upll_memphy|auto_generated|pll1|clk[0]" 900 274 | 275 | .PHONY : report_critical 276 | report_critical: 277 | @echo "**********************************************************************" 278 | @echo "* Reporting Critical Warnings During Synthesis" 279 | @echo "**********************************************************************" 280 | @/bin/egrep '^Critical' output_files/*.rpt || echo "No Critical Warnings" 281 | 282 | .PHONY : report_error 283 | report_error: 284 | @echo "**********************************************************************" 285 | @echo "* Reporting Errors During Synthesis" 286 | @echo "**********************************************************************" 287 | @/bin/egrep '^Error' output_files/*.rpt || echo "No Errors" 288 | 289 | .PHONY : update_mif 290 | update_mif: _update_mif report_critical report_error 291 | 292 | .PHONY : _update_mif 293 | _update_mif: build_miniboot 294 | quartus_cdb $(QUARTUS_PROJECT) -c $(QUARTUS_PROJECT_VERSION) --update_mif 295 | quartus_asm --read_settings_files=on --write_settings_files=off $(QUARTUS_PROJECT) -c $(QUARTUS_PROJECT_VERSION) 296 | cp $(QSYS_SYNTHESIS_DIR)/*.sopcinfo . 297 | 298 | .PHONY: megawizard 299 | megawizard: 300 | # @echo "**********************************************************************" 301 | # @echo "* Build local PLLs" 302 | # @echo "**********************************************************************" 303 | # cp pll_125.v.template pll_125.v 304 | # qmegawiz -silent pll_125.v 305 | # cp display_pll.v.template display_pll.v 306 | # qmegawiz -silent display_pll.v 307 | # cp altgx_reconfig.v.template altgx_reconfig.v 308 | # qmegawiz -silent altgx_reconfig.v 309 | 310 | .PHONY : build_nodip_wait 311 | build_nodip_wait: _always_nodip_msg _always_nodip update_mif _always_nodip_restore_dir 312 | 313 | .PHONY : _always_nodip_restore_dir 314 | _always_nodip_restore_dir: 315 | # Make sure the default bitfile stays in the expected output dir. 316 | mv output_files output_files_nodip 317 | mv output_files_default output_files 318 | # Also restore intial.hex. 319 | mv mem64.hex mem64-nodip.hex 320 | mv mem64-default.hex mem64.hex 321 | 322 | .PHONY : _always_nodip_msg 323 | _always_nodip_msg: 324 | @echo "**********************************************************************" 325 | @echo "* Rebuilding bitfile with miniboot ingoring DIP switch for waiting" 326 | @echo "**********************************************************************" 327 | 328 | .PHONY : _always_nodip 329 | _always_nodip: build_fpga 330 | # Swap miniboot ROMs. 331 | mv mem64.hex mem64-default.hex 332 | mv mem64-nodip.hex mem64.hex 333 | # Save previously built files. 334 | cp -pr output_files output_files_default 335 | 336 | .PHONY : download 337 | download : 338 | @echo "**********************************************************************" 339 | @echo "* Downloading the FPGA image to the FPGA " 340 | @echo "**********************************************************************" 341 | @echo "* If this fails you may need to check if the FPGA can be seen using: " 342 | @echo "* jtagconfig " 343 | @echo "* to see what devices are present. If this still doesn't work, " 344 | @echo "* fire up the Quartus IDE and use the graphical programming tool " 345 | @echo "* to diagnose the problem and create a new programming chain " 346 | @echo "* ("$(QUARTUS_PROJECT_VERSION)".cdf) file. " 347 | @echo "**********************************************************************" 348 | quartus_pgm $(QUARTUS_PROJECT_VERSION).cdf 349 | @echo "**********************************************************************" 350 | @echo "* Download of hardware ("$(QUARTUS_PROJECT_VERSION).sof") complete" 351 | @echo "**********************************************************************" 352 | 353 | .PHONY: restore_originals 354 | restore_originals: 355 | @echo "**********************************************************************" 356 | @echo "* Restoring cheri2 patched files to originals." 357 | @echo "**********************************************************************" 358 | @ls *.original 2>/dev/null | while read orig_file; do \ 359 | orig_name="$${orig_file/.original/}" ; \ 360 | if [ "$$orig_name" -nt "$$orig_file" -a -z "${FORCE}" ]; then \ 361 | echo "REFUSING TO OVERWRITE MODIFIED FILE $$orig_name" ; \ 362 | echo "Set FORCE=1 or do this manually using 'mv $$orig_file $$orig_name'." ; \ 363 | exit 1; \ 364 | else \ 365 | echo "Restoring original $$orig_name from $$orig_file" ; \ 366 | mv "$$orig_file" "$$orig_name"; \ 367 | fi; done 368 | 369 | .PHONY : cleanq 370 | cleanq: 371 | # rm -f $(QSYS_GENERATED_FILES) 372 | rm -rf $(QSYS_SYNTHESIS_DIR) 373 | rm -rf $(QUARTUS_GENERATED_DIRS) 374 | rm -f dtb.hex $(QUARTUS_PROJECT).dtb 375 | rm -f $(QUARTUS_PROJECT).dts $(QUARTUS_PROJECT).dts.cpp 376 | rm -f mem64.hex mem64-default.hex mem64-nodip.hex version.hex 377 | rm -rf greybox_tmp 378 | rm -f $(MEGAWIZARD_GENERATED_FILES) 379 | 380 | .PHONY : cleanall 381 | cleanall: cleanq restore_originals 382 | $(MAKE) -C $(CHERI_DIR) clean 383 | $(MAKE) -C $(PERIPHERALS_DIR) clean 384 | $(MAKE) -C $(MINIBOOT_DIR) clean 385 | $(MAKE) -C $(CHERILIBSDIR) clean 386 | 387 | .PHONY : clean 388 | clean: cleanq 389 | @echo "WARNING: this did not clean CHERI, peripherals or miniboot" 390 | @echo " use 'make cleanall' to clean CHERI, peripherals and miniboot" 391 | 392 | .PHONY : help 393 | help : 394 | @echo "Summary of makefile targets" 395 | @echo " all - builds everything using the following steps (except download)" 396 | @echo " build_processor - CHERI/BERI processor" 397 | @echo " build_peripherals - peripherals" 398 | @echo " build_miniboot - build miniboot ROM and copy mem64.hex here" 399 | @echo " build_qsys - build Qsys project containing CHERI, etc." 400 | @echo " build_fpga - synthesis, map, fit, timing analyse and generate FPGA image" 401 | @echo " build_nodip_wait - build_fpga with modified miniboot to ignore wait DIP switch" 402 | @echo " report_fmax - extracts the Fmax summary from build_fpga reports" 403 | @echo "report_timing_stats- output important timing info as CSV files" 404 | @echo " report_critical - scans build_fpga reports for critical warnings" 405 | @echo " report_error - scans build_fpga reports for errors" 406 | @echo " update_mif - Update memory intialization files" 407 | @echo " download - attempts to download the FPGA (.sof) image to the FPGA" 408 | @echo " but the chain file (.cdf) may need to be updated for" 409 | @echo " your configuration (e.g. USB port number)" 410 | @echo " clean - remove Quartus and Qsys build files" 411 | @echo " cleanall - clean + clean peripherals, CHERI and miniboot" 412 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/ghrd_10as066n2_top.v: -------------------------------------------------------------------------------- 1 | module ghrd_10as066n2_top ( 2 | // FPGA peripherals ports 3 | input wire [3:0] fpga_dipsw_pio, 4 | output wire [3:0] fpga_led_pio, 5 | input wire [3:0] fpga_button_pio, 6 | // HPS memory controller ports 7 | // DDR4 single rank -2133 device 8 | output wire hps_memory_mem_act_n, 9 | output wire hps_memory_mem_bg, 10 | output wire hps_memory_mem_par, 11 | input wire hps_memory_mem_alert_n, 12 | inout wire [4-1:0] hps_memory_mem_dbi_n, 13 | output wire [16:0] hps_memory_mem_a, 14 | output wire [1:0] hps_memory_mem_ba, 15 | output wire hps_memory_mem_ck, 16 | output wire hps_memory_mem_ck_n, 17 | output wire hps_memory_mem_cke, 18 | output wire hps_memory_mem_cs_n, 19 | output wire hps_memory_mem_reset_n, 20 | inout wire [32-1:0] hps_memory_mem_dq, 21 | inout wire [4-1:0] hps_memory_mem_dqs, 22 | inout wire [4-1:0] hps_memory_mem_dqs_n, 23 | output wire hps_memory_mem_odt, 24 | input wire hps_memory_oct_rzqin, 25 | input wire emif_ref_clk, 26 | // HPS peripherals 27 | output wire hps_emac0_TX_CLK, 28 | output wire hps_emac0_TXD0, 29 | output wire hps_emac0_TXD1, 30 | output wire hps_emac0_TXD2, 31 | output wire hps_emac0_TXD3, 32 | input wire hps_emac0_RXD0, 33 | inout wire hps_emac0_MDIO, 34 | output wire hps_emac0_MDC, 35 | input wire hps_emac0_RX_CTL, 36 | output wire hps_emac0_TX_CTL, 37 | input wire hps_emac0_RX_CLK, 38 | input wire hps_emac0_RXD1, 39 | input wire hps_emac0_RXD2, 40 | input wire hps_emac0_RXD3, 41 | inout wire hps_usb0_D0, 42 | inout wire hps_usb0_D1, 43 | inout wire hps_usb0_D2, 44 | inout wire hps_usb0_D3, 45 | inout wire hps_usb0_D4, 46 | inout wire hps_usb0_D5, 47 | inout wire hps_usb0_D6, 48 | inout wire hps_usb0_D7, 49 | input wire hps_usb0_CLK, 50 | output wire hps_usb0_STP, 51 | input wire hps_usb0_DIR, 52 | input wire hps_usb0_NXT, 53 | output wire hps_spim1_CLK, 54 | output wire hps_spim1_MOSI, 55 | input wire hps_spim1_MISO, 56 | output wire hps_spim1_SS0_N, 57 | output wire hps_spim1_SS1_N, 58 | input wire hps_uart1_RX, 59 | output wire hps_uart1_TX, 60 | // inout wire hps_i2c1_SDA, 61 | // inout wire hps_i2c1_SCL, 62 | inout wire hps_sdio_CMD, 63 | output wire hps_sdio_CLK, 64 | inout wire hps_sdio_D0, 65 | inout wire hps_sdio_D1, 66 | inout wire hps_sdio_D2, 67 | inout wire hps_sdio_D3, 68 | inout wire hps_sdio_D4, 69 | inout wire hps_sdio_D5, 70 | inout wire hps_sdio_D6, 71 | inout wire hps_sdio_D7, 72 | output wire hps_trace_CLK, 73 | output wire hps_trace_D0, 74 | output wire hps_trace_D1, 75 | output wire hps_trace_D2, 76 | output wire hps_trace_D3, 77 | inout wire hps_gpio_GPIO14, 78 | inout wire hps_gpio_GPIO05, 79 | inout wire hps_gpio_GPIO16, 80 | inout wire hps_gpio_GPIO17, 81 | // Other HPS-FPGA peripherals 82 | input wire pcie_ep_refclk_100, 83 | input wire pcie_ep_rx_in0, 84 | /*input wire pcie_ep_rx_in1, 85 | input wire pcie_ep_rx_in2, 86 | input wire pcie_ep_rx_in3, 87 | */output wire pcie_ep_tx_out0, 88 | /*output wire pcie_ep_tx_out1, 89 | output wire pcie_ep_tx_out2, 90 | output wire pcie_ep_tx_out3, 91 | */input wire pcie_ep_perst, 92 | //output wire pcie_perstn_out, 93 | // FPGA clock and reset 94 | input wire fpga_clk_100, 95 | input wire fpga_reset_n 96 | ); 97 | 98 | // internal wires and registers declaration 99 | wire [3:0] fpga_debounced_buttons; 100 | wire [3:0] fpga_led_internal; 101 | wire [27:0] stm_hw_events; 102 | wire hps_fpga_reset; 103 | wire [2:0] hps_reset_req; 104 | wire hps_cold_reset; 105 | wire hps_warm_reset; 106 | wire hps_debug_reset; 107 | wire [7:0] reset_pio; 108 | wire pcie_npor_pio_h; 109 | 110 | wire pcie_npor_npor; 111 | wire coreclk_fanout_clk; 112 | wire coreclk_fanout_reset_n; 113 | wire [4:0] hps_pcie_a10_hip_avmm_hip_pipe_sim_ltssmstate; 114 | wire [4:0] hps_pcie_a10_hip_avmm_hip_status_ltssmstate; 115 | //wire pcie_ep_perst; 116 | 117 | //assign pcie_ep_perst = 1'b0; 118 | 119 | // connection of internal logics 120 | //assign fpga_led_pio = fpga_led_internal; 121 | // soft reset wire from PIO 122 | assign pcie_npor_pio_h = reset_pio[0]; // active high 123 | assign stm_hw_events = {{16{1'b0}}, fpga_dipsw_pio, fpga_led_internal, fpga_debounced_buttons}; 124 | assign pcie_npor_npor = pcie_ep_perst & fpga_reset_n; // & ~pcie_npor_pio_h; //~hps_fpga_reset & pcie_ep_perst & fpga_reset_n; 125 | 126 | //registers 127 | reg L0_led; // link status ltssm=0xf 128 | reg alive_led; // heart beat 129 | reg [1:0] linkwidth_led; // link width, 1=x1, 2=x4, skipped x2 and ignored x8 130 | reg [39:0] alive_cnt; 131 | reg [39:0] timer; 132 | 133 | 134 | // connection of internal logics 135 | //assign pcie_perstn_out = 1'b1; 136 | //assign fpga_led_pio = {L0_led, alive_led, linkwidth_led[1], ~fpga_led_internal}; 137 | assign fpga_led_pio = timer[39:36]; 138 | //assign sync_pcie_por_n = ~sync_pcie_por; potentailly redundant signal 139 | 140 | // logic for LED display derivation 141 | always @(posedge coreclk_fanout_clk or negedge coreclk_fanout_reset_n) begin // pcie_refclk_clk to be modified with coreclk_out from PCIe IP later 142 | if (!coreclk_fanout_reset_n) begin 143 | L0_led <= 1'b0; 144 | alive_led <= 1'b0; 145 | linkwidth_led <= 2'h0; 146 | alive_cnt <= 40'd0; 147 | end 148 | else begin 149 | L0_led <= ~(hps_pcie_a10_hip_avmm_hip_status_ltssmstate[3:0] == 4'hf); 150 | alive_led <= timer[39]; 151 | linkwidth_led <= {alive_cnt[24],alive_cnt[21]}; // tentatively assign linkwidth_led as flashing display as PCIe HIP has yet exposed the tl_cfg_sts signal 152 | alive_cnt <= alive_cnt + 40'h1; 153 | end 154 | end 155 | 156 | // SoC sub-system module 157 | ghrd_10as066n2 soc_inst ( 158 | .f2h_stm_hw_events_stm_hwevents (stm_hw_events), 159 | .pio_dipsw_external_connection_export (fpga_dipsw_pio), 160 | .pio_led_external_connection_in_port (fpga_led_internal), 161 | .pio_led_external_connection_out_port (fpga_led_internal), 162 | .pio_button_external_connection_export (fpga_debounced_buttons), 163 | .hps_io_hps_io_phery_emac0_TX_CLK (hps_emac0_TX_CLK), 164 | .hps_io_hps_io_phery_emac0_TXD0 (hps_emac0_TXD0), 165 | .hps_io_hps_io_phery_emac0_TXD1 (hps_emac0_TXD1), 166 | .hps_io_hps_io_phery_emac0_TXD2 (hps_emac0_TXD2), 167 | .hps_io_hps_io_phery_emac0_TXD3 (hps_emac0_TXD3), 168 | .hps_io_hps_io_phery_emac0_MDIO (hps_emac0_MDIO), 169 | .hps_io_hps_io_phery_emac0_MDC (hps_emac0_MDC), 170 | .hps_io_hps_io_phery_emac0_RX_CTL (hps_emac0_RX_CTL), 171 | .hps_io_hps_io_phery_emac0_TX_CTL (hps_emac0_TX_CTL), 172 | .hps_io_hps_io_phery_emac0_RX_CLK (hps_emac0_RX_CLK), 173 | .hps_io_hps_io_phery_emac0_RXD0 (hps_emac0_RXD0), 174 | .hps_io_hps_io_phery_emac0_RXD1 (hps_emac0_RXD1), 175 | .hps_io_hps_io_phery_emac0_RXD2 (hps_emac0_RXD2), 176 | .hps_io_hps_io_phery_emac0_RXD3 (hps_emac0_RXD3), 177 | .hps_io_hps_io_phery_usb0_DATA0 (hps_usb0_D0), 178 | .hps_io_hps_io_phery_usb0_DATA1 (hps_usb0_D1), 179 | .hps_io_hps_io_phery_usb0_DATA2 (hps_usb0_D2), 180 | .hps_io_hps_io_phery_usb0_DATA3 (hps_usb0_D3), 181 | .hps_io_hps_io_phery_usb0_DATA4 (hps_usb0_D4), 182 | .hps_io_hps_io_phery_usb0_DATA5 (hps_usb0_D5), 183 | .hps_io_hps_io_phery_usb0_DATA6 (hps_usb0_D6), 184 | .hps_io_hps_io_phery_usb0_DATA7 (hps_usb0_D7), 185 | .hps_io_hps_io_phery_usb0_CLK (hps_usb0_CLK), 186 | .hps_io_hps_io_phery_usb0_STP (hps_usb0_STP), 187 | .hps_io_hps_io_phery_usb0_DIR (hps_usb0_DIR), 188 | .hps_io_hps_io_phery_usb0_NXT (hps_usb0_NXT), 189 | .hps_io_hps_io_phery_spim1_CLK (hps_spim1_CLK), 190 | .hps_io_hps_io_phery_spim1_MOSI (hps_spim1_MOSI), 191 | .hps_io_hps_io_phery_spim1_MISO (hps_spim1_MISO), 192 | .hps_io_hps_io_phery_spim1_SS0_N (hps_spim1_SS0_N), 193 | .hps_io_hps_io_phery_spim1_SS1_N (hps_spim1_SS1_N), 194 | .hps_io_hps_io_phery_uart1_RX (hps_uart1_RX), 195 | .hps_io_hps_io_phery_uart1_TX (hps_uart1_TX), 196 | .hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_CMD), 197 | .hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_D0), 198 | .hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_D1), 199 | .hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_D2), 200 | .hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_D3), 201 | .hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_D4), 202 | .hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_D5), 203 | .hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_D6), 204 | .hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_D7), 205 | .hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_CLK), 206 | .hps_io_hps_io_phery_trace_CLK (hps_trace_CLK), 207 | .hps_io_hps_io_phery_trace_D0 (hps_trace_D0), 208 | .hps_io_hps_io_phery_trace_D1 (hps_trace_D1), 209 | .hps_io_hps_io_phery_trace_D2 (hps_trace_D2), 210 | .hps_io_hps_io_phery_trace_D3 (hps_trace_D3), 211 | .hps_io_hps_io_gpio_gpio1_io5 (hps_gpio_GPIO05), 212 | .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio_GPIO14), 213 | .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio_GPIO16), 214 | .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio_GPIO17), 215 | // .hps_io_hps_io_phery_i2c1_SDA (hps_i2c1_SDA), 216 | // .hps_io_hps_io_phery_i2c1_SCL (hps_i2c1_SCL), 217 | .h2f_gp_gp_in (32'd0), 218 | .h2f_gp_gp_out (), 219 | .emif_a10_hps_0_mem_conduit_end_mem_ck (hps_memory_mem_ck), 220 | .emif_a10_hps_0_mem_conduit_end_mem_ck_n (hps_memory_mem_ck_n), 221 | .emif_a10_hps_0_mem_conduit_end_mem_a (hps_memory_mem_a), 222 | .emif_a10_hps_0_mem_conduit_end_mem_act_n (hps_memory_mem_act_n), 223 | .emif_a10_hps_0_mem_conduit_end_mem_ba (hps_memory_mem_ba), 224 | .emif_a10_hps_0_mem_conduit_end_mem_bg (hps_memory_mem_bg), 225 | .emif_a10_hps_0_mem_conduit_end_mem_cke (hps_memory_mem_cke), 226 | .emif_a10_hps_0_mem_conduit_end_mem_cs_n (hps_memory_mem_cs_n), 227 | .emif_a10_hps_0_mem_conduit_end_mem_odt (hps_memory_mem_odt), 228 | .emif_a10_hps_0_mem_conduit_end_mem_reset_n (hps_memory_mem_reset_n), 229 | .emif_a10_hps_0_mem_conduit_end_mem_par (hps_memory_mem_par), 230 | .emif_a10_hps_0_mem_conduit_end_mem_alert_n (hps_memory_mem_alert_n), 231 | .emif_a10_hps_0_mem_conduit_end_mem_dqs (hps_memory_mem_dqs), 232 | .emif_a10_hps_0_mem_conduit_end_mem_dqs_n (hps_memory_mem_dqs_n), 233 | .emif_a10_hps_0_mem_conduit_end_mem_dq (hps_memory_mem_dq), 234 | .emif_a10_hps_0_mem_conduit_end_mem_dbi_n (hps_memory_mem_dbi_n), 235 | .emif_a10_hps_0_oct_conduit_end_oct_rzqin (hps_memory_oct_rzqin), 236 | .emif_a10_hps_0_pll_ref_clk_clock_sink_clk (emif_ref_clk), 237 | 238 | 239 | .pcie_tlp_buffer_pcie_ep_0_pcie_rstn_npor (pcie_npor_npor), // pcie_tlp_buffer_pcie_rstn.npor 240 | .pcie_tlp_buffer_pcie_ep_0_pcie_rstn_pin_perst (pcie_ep_perst), // .pin_perst 241 | .pcie_tlp_buffer_pcie_ep_0_hip_serial_rx_in0 (pcie_ep_rx_in0), // pcie_tlp_buffer_hip_serial.rx_in0 242 | /* .pcie_tlp_buffer_pcie_ep_0_hip_serial_rx_in1 (pcie_ep_rx_in1), // .rx_in1 243 | .pcie_tlp_buffer_pcie_ep_0_hip_serial_rx_in2 (pcie_ep_rx_in2), // .rx_in2 244 | .pcie_tlp_buffer_pcie_ep_0_hip_serial_rx_in3 (pcie_ep_rx_in3), // .rx_in3 245 | */ .pcie_tlp_buffer_pcie_ep_0_hip_serial_tx_out0 (pcie_ep_tx_out0), // .tx_out0 246 | /* .pcie_tlp_buffer_pcie_ep_0_hip_serial_tx_out1 (pcie_ep_tx_out1), // .tx_out1 247 | .pcie_tlp_buffer_pcie_ep_0_hip_serial_tx_out2 (pcie_ep_tx_out2), // .tx_out2 248 | .pcie_tlp_buffer_pcie_ep_0_hip_serial_tx_out3 (pcie_ep_tx_out3), // .tx_out3 249 | */ .pcie_tlp_buffer_pcie_ep_0_refclk_clk (pcie_ep_refclk_100), // pcie_tlp_buffer_refclk.clk 250 | /* 251 | 252 | //PCIe 253 | .pcie_0_pcie_a10_hip_avmm_refclk_clk (pcie_ep_refclk_100), 254 | .pcie_0_coreclk_fanout_clk_clk (coreclk_fanout_clk), 255 | .pcie_0_coreclk_fanout_clk_reset_reset_n (coreclk_fanout_reset_n), 256 | //.iopll_0_refclk_clk (coreclk_fanout_clk), 257 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_sim_pipe_pclk_in (1'b0), 258 | .pcie_0_pcie_a10_hip_avmm_hip_ctrl_test_in ( 32'h0 ), 259 | .pcie_0_pcie_a10_hip_avmm_hip_ctrl_simu_mode_pipe ( 0 ), 260 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_phystatus0 (1'b0), 261 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_phystatus1 (1'b0), 262 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_phystatus2 (1'b0), 263 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_phystatus3 (1'b0), 264 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdata0 (32'b0), 265 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdata1 (32'b0), 266 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdata2 (32'b0), 267 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdata3 (32'b0), 268 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdatak0 (4'b0), 269 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdatak1 (4'b0), 270 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdatak2 (4'b0), 271 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdatak3 (4'b0), 272 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxelecidle0 (1'b0), 273 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxelecidle1 (1'b0), 274 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxelecidle2 (1'b0), 275 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxelecidle3 (1'b0), 276 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxstatus0 (3'b0), 277 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxstatus1 (3'b0), 278 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxstatus2 (3'b0), 279 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxstatus3 (3'b0), 280 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxvalid0 (1'b0), 281 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxvalid1 (1'b0), 282 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxvalid2 (1'b0), 283 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxvalid3 (1'b0), 284 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdataskip0 (1'b0), 285 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdataskip1 (1'b0), 286 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdataskip2 (1'b0), 287 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxdataskip3 (1'b0), 288 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxblkst0 (1'b0), 289 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxblkst1 (1'b0), 290 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxblkst2 (1'b0), 291 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxblkst3 (1'b0), 292 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxsynchd0 (2'b0), 293 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxsynchd1 (2'b0), 294 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxsynchd2 (2'b0), 295 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_rxsynchd3 (2'b0), 296 | .pcie_0_pcie_a10_hip_avmm_hip_serial_rx_in0 ( pcie_ep_rx_in0 ), 297 | .pcie_0_pcie_a10_hip_avmm_hip_serial_rx_in1 ( pcie_ep_rx_in1 ), 298 | .pcie_0_pcie_a10_hip_avmm_hip_serial_rx_in2 ( pcie_ep_rx_in2 ), 299 | .pcie_0_pcie_a10_hip_avmm_hip_serial_rx_in3 ( pcie_ep_rx_in3 ), 300 | .pcie_0_pcie_a10_hip_avmm_hip_serial_tx_out0 ( pcie_ep_tx_out0 ), 301 | .pcie_0_pcie_a10_hip_avmm_hip_serial_tx_out1 ( pcie_ep_tx_out1 ), 302 | .pcie_0_pcie_a10_hip_avmm_hip_serial_tx_out2 ( pcie_ep_tx_out2 ), 303 | .pcie_0_pcie_a10_hip_avmm_hip_serial_tx_out3 ( pcie_ep_tx_out3 ), 304 | .pcie_0_pcie_a10_hip_avmm_hip_pipe_sim_ltssmstate (hps_pcie_a10_hip_avmm_hip_pipe_sim_ltssmstate), 305 | .pcie_0_pcie_a10_hip_avmm_hip_status_ltssmstate (hps_pcie_a10_hip_avmm_hip_status_ltssmstate), 306 | .pcie_0_pcie_a10_hip_avmm_npor_npor (pcie_npor_npor), 307 | .pcie_0_pcie_a10_hip_avmm_npor_pin_perst (pcie_ep_perst), 308 | */ 309 | 310 | .clk_100_clk (fpga_clk_100), 311 | .reset_reset_n (fpga_reset_n), 312 | .hps_fpga_reset_reset (hps_fpga_reset), 313 | .issp_hps_resets_source (hps_reset_req), 314 | .f2h_cold_reset_req_reset_n (~hps_cold_reset), 315 | .f2h_warm_reset_req_reset_n (~hps_warm_reset), 316 | .f2h_debug_reset_req_reset_n (~hps_debug_reset), 317 | .pio_reset_external_connection_export (reset_pio), // pio_reset_external_connection.export 318 | 319 | ); 320 | 321 | // Debounce logic to clean out glitches within 1ms 322 | debounce debounce_inst ( 323 | .clk (fpga_clk_100), 324 | .reset_n (~hps_fpga_reset), 325 | .data_in (fpga_button_pio), 326 | .data_out (fpga_debounced_buttons) 327 | ); 328 | defparam debounce_inst.WIDTH = 4; 329 | defparam debounce_inst.POLARITY = "LOW"; 330 | defparam debounce_inst.TIMEOUT = 100000; // at 100Mhz this is a debounce time of 1ms 331 | defparam debounce_inst.TIMEOUT_WIDTH = 32; // ceil(log2(TIMEOUT)) 332 | 333 | 334 | altera_edge_detector pulse_cold_reset ( 335 | .clk (fpga_clk_100), 336 | .rst_n (~hps_fpga_reset), 337 | .signal_in (hps_reset_req[0]), 338 | .pulse_out (hps_cold_reset) 339 | ); 340 | defparam pulse_cold_reset.PULSE_EXT = 6; 341 | defparam pulse_cold_reset.EDGE_TYPE = 1; 342 | defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1; 343 | 344 | altera_edge_detector pulse_warm_reset ( 345 | .clk (fpga_clk_100), 346 | .rst_n (~hps_fpga_reset), 347 | .signal_in (hps_reset_req[1]), 348 | .pulse_out (hps_warm_reset) 349 | ); 350 | defparam pulse_warm_reset.PULSE_EXT = 2; 351 | defparam pulse_warm_reset.EDGE_TYPE = 1; 352 | defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1; 353 | 354 | altera_edge_detector pulse_debug_reset ( 355 | .clk (fpga_clk_100), 356 | .rst_n (~hps_fpga_reset), 357 | .signal_in (hps_reset_req[2]), 358 | .pulse_out (hps_debug_reset) 359 | ); 360 | defparam pulse_debug_reset.PULSE_EXT = 32; 361 | defparam pulse_debug_reset.EDGE_TYPE = 1; 362 | defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1; 363 | 364 | 365 | 366 | initial timer=40'h0; 367 | 368 | always @(posedge fpga_clk_100) begin 369 | timer <= timer + 40'h1; 370 | end 371 | 372 | 373 | endmodule 374 | 375 | 376 | -------------------------------------------------------------------------------- /boards/intel-a10soc-devkit/ghrd_10as066n2.qsf: -------------------------------------------------------------------------------- 1 | set_global_assignment -name FAMILY "Arria 10" 2 | set_global_assignment -name DEVICE 10AS066N3F40E2SG 3 | set_global_assignment -name TOP_LEVEL_ENTITY ghrd_10as066n2_top 4 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.1 5 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:23:04 JANUARY 13, 2016" 6 | set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" 7 | set_global_assignment -name QIP_FILE ghrd_10as066n2/ghrd_10as066n2.qip 8 | set_global_assignment -name VERILOG_FILE ghrd_10as066n2_top.v 9 | set_global_assignment -name VERILOG_FILE ip/debounce/debounce.v 10 | set_global_assignment -name VERILOG_FILE ip/edge_detect/altera_edge_detector.v 11 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 12 | set_global_assignment -name SDC_FILE ghrd_timing.sdc 13 | set_global_assignment -name SDC_FILE fpga_pcie.sdc 14 | set_global_assignment -name INI_VARS "ASM_ENABLE_ADVANCED_DEVICES=ON" 15 | set_global_assignment -name ENABLE_SIGNALTAP ON 16 | set_global_assignment -name USE_SIGNALTAP_FILE cti_tapping.stp 17 | set_global_assignment -name SIGNALTAP_FILE cti_tapping.stp 18 | set_location_assignment PIN_AM10 -to fpga_clk_100 19 | set_location_assignment PIN_AV21 -to fpga_reset_n 20 | set_location_assignment PIN_AR23 -to fpga_led_pio[0] 21 | set_location_assignment PIN_AR22 -to fpga_led_pio[1] 22 | set_location_assignment PIN_AM21 -to fpga_led_pio[2] 23 | set_location_assignment PIN_AL20 -to fpga_led_pio[3] 24 | set_location_assignment PIN_P3 -to fpga_dipsw_pio[0] 25 | set_location_assignment PIN_P4 -to fpga_dipsw_pio[1] 26 | set_location_assignment PIN_P1 -to fpga_dipsw_pio[2] 27 | set_location_assignment PIN_R1 -to fpga_dipsw_pio[3] 28 | set_location_assignment PIN_R5 -to fpga_button_pio[0] 29 | set_location_assignment PIN_T5 -to fpga_button_pio[1] 30 | set_location_assignment PIN_P5 -to fpga_button_pio[2] 31 | set_location_assignment PIN_P6 -to fpga_button_pio[3] 32 | set_location_assignment PIN_AE29 -to pcie_refclk_100 33 | set_location_assignment PIN_AE33 -to rx_in0 34 | set_location_assignment PIN_AD31 -to rx_in1 35 | set_location_assignment PIN_AD35 -to rx_in2 36 | set_location_assignment PIN_AC33 -to rx_in3 37 | set_location_assignment PIN_AG37 -to tx_out0 38 | set_location_assignment PIN_AF39 -to tx_out1 39 | set_location_assignment PIN_AE37 -to tx_out2 40 | set_location_assignment PIN_AD39 -to tx_out3 41 | set_location_assignment PIN_F25 -to emif_ref_clk 42 | set_location_assignment PIN_G24 -to "emif_ref_clk(n)" 43 | set_location_assignment PIN_E26 -to hps_memory_oct_rzqin 44 | set_instance_assignment -name IO_STANDARD LVDS -to emif_ref_clk 45 | set_instance_assignment -name IO_STANDARD LVDS -to "emif_ref_clk(n)" 46 | set_location_assignment PIN_AG24 -to hps_memory_mem_alert_n 47 | set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON -to AB31 48 | set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON -to AB35 49 | set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON -to AA33 50 | set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON -to Y35 51 | set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON -to AG33 52 | set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON -to AH35 53 | set_instance_assignment -name IO_STANDARD LVDS -to fpga_clk_100 54 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_reset_n 55 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_dipsw_pio[3] 56 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_dipsw_pio[0] 57 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_dipsw_pio[1] 58 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_dipsw_pio[2] 59 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_led_pio[0] 60 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_led_pio[1] 61 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_led_pio[2] 62 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_led_pio[3] 63 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_button_pio[3] 64 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_button_pio[0] 65 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_button_pio[1] 66 | set_instance_assignment -name IO_STANDARD "1.8 V" -to fpga_button_pio[2] 67 | set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_100 68 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_in0 69 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_in1 70 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_in2 71 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_in3 72 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_out0 73 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_out1 74 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_out2 75 | set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_out3 76 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_in0 77 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_in1 78 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_in2 79 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_in3 80 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_out0 81 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_out1 82 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_out2 83 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_out3 84 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_pcie_a10_hip_avmm_0_npor_pin_perst 85 | set_location_assignment PIN_H18 -to hps_emac0_TX_CLK 86 | set_location_assignment PIN_H19 -to hps_emac0_TX_CTL 87 | set_location_assignment PIN_E20 -to hps_emac0_TXD0 88 | set_location_assignment PIN_F20 -to hps_emac0_TXD1 89 | set_location_assignment PIN_F19 -to hps_emac0_TXD2 90 | set_location_assignment PIN_G19 -to hps_emac0_TXD3 91 | set_location_assignment PIN_F18 -to hps_emac0_RX_CLK 92 | set_location_assignment PIN_G17 -to hps_emac0_RX_CTL 93 | set_location_assignment PIN_G20 -to hps_emac0_RXD0 94 | set_location_assignment PIN_G21 -to hps_emac0_RXD1 95 | set_location_assignment PIN_F22 -to hps_emac0_RXD2 96 | set_location_assignment PIN_G22 -to hps_emac0_RXD3 97 | set_location_assignment PIN_K20 -to hps_emac0_MDC 98 | set_location_assignment PIN_K21 -to hps_emac0_MDIO 99 | set_location_assignment PIN_B21 -to hps_memory_mem_act_n 100 | set_location_assignment PIN_J24 -to hps_memory_mem_bg 101 | set_location_assignment PIN_A18 -to hps_memory_mem_par 102 | set_location_assignment PIN_B26 -to hps_memory_mem_a[0] 103 | set_location_assignment PIN_C26 -to hps_memory_mem_a[1] 104 | set_location_assignment PIN_C22 -to hps_memory_mem_a[2] 105 | set_location_assignment PIN_C21 -to hps_memory_mem_a[3] 106 | set_location_assignment PIN_C25 -to hps_memory_mem_a[4] 107 | set_location_assignment PIN_B24 -to hps_memory_mem_a[5] 108 | set_location_assignment PIN_B22 -to hps_memory_mem_a[6] 109 | set_location_assignment PIN_C23 -to hps_memory_mem_a[7] 110 | set_location_assignment PIN_D23 -to hps_memory_mem_a[8] 111 | set_location_assignment PIN_E23 -to hps_memory_mem_a[9] 112 | set_location_assignment PIN_C24 -to hps_memory_mem_a[10] 113 | set_location_assignment PIN_D24 -to hps_memory_mem_a[11] 114 | set_location_assignment PIN_F26 -to hps_memory_mem_a[12] 115 | set_location_assignment PIN_G26 -to hps_memory_mem_a[13] 116 | set_location_assignment PIN_G25 -to hps_memory_mem_a[14] 117 | set_location_assignment PIN_F24 -to hps_memory_mem_a[15] 118 | set_location_assignment PIN_F23 -to hps_memory_mem_a[16] 119 | set_location_assignment PIN_E25 -to hps_memory_mem_ba[0] 120 | set_location_assignment PIN_H24 -to hps_memory_mem_ba[1] 121 | set_location_assignment PIN_B20 -to hps_memory_mem_ck 122 | set_location_assignment PIN_B19 -to hps_memory_mem_ck_n 123 | set_location_assignment PIN_A24 -to hps_memory_mem_cke 124 | set_location_assignment PIN_A22 -to hps_memory_mem_cs_n 125 | set_location_assignment PIN_A19 -to hps_memory_mem_reset_n 126 | set_location_assignment PIN_A26 -to hps_memory_mem_odt 127 | set_location_assignment PIN_AN26 -to hps_memory_mem_dbi_n[0] 128 | set_location_assignment PIN_AU25 -to hps_memory_mem_dbi_n[1] 129 | set_location_assignment PIN_AV26 -to hps_memory_mem_dbi_n[2] 130 | set_location_assignment PIN_AH25 -to hps_memory_mem_dbi_n[3] 131 | set_location_assignment PIN_AP26 -to hps_memory_mem_dq[0] 132 | set_location_assignment PIN_AN24 -to hps_memory_mem_dq[1] 133 | set_location_assignment PIN_AN23 -to hps_memory_mem_dq[2] 134 | set_location_assignment PIN_AM24 -to hps_memory_mem_dq[3] 135 | set_location_assignment PIN_AK26 -to hps_memory_mem_dq[4] 136 | set_location_assignment PIN_AL23 -to hps_memory_mem_dq[5] 137 | set_location_assignment PIN_AL26 -to hps_memory_mem_dq[6] 138 | set_location_assignment PIN_AK23 -to hps_memory_mem_dq[7] 139 | set_location_assignment PIN_AP23 -to hps_memory_mem_dq[8] 140 | set_location_assignment PIN_AT26 -to hps_memory_mem_dq[9] 141 | set_location_assignment PIN_AR26 -to hps_memory_mem_dq[10] 142 | set_location_assignment PIN_AR25 -to hps_memory_mem_dq[11] 143 | set_location_assignment PIN_AT23 -to hps_memory_mem_dq[12] 144 | set_location_assignment PIN_AP25 -to hps_memory_mem_dq[13] 145 | set_location_assignment PIN_AU24 -to hps_memory_mem_dq[14] 146 | set_location_assignment PIN_AU26 -to hps_memory_mem_dq[15] 147 | set_location_assignment PIN_AU28 -to hps_memory_mem_dq[16] 148 | set_location_assignment PIN_AU27 -to hps_memory_mem_dq[17] 149 | set_location_assignment PIN_AV23 -to hps_memory_mem_dq[18] 150 | set_location_assignment PIN_AW28 -to hps_memory_mem_dq[19] 151 | set_location_assignment PIN_AV24 -to hps_memory_mem_dq[20] 152 | set_location_assignment PIN_AW24 -to hps_memory_mem_dq[21] 153 | set_location_assignment PIN_AV28 -to hps_memory_mem_dq[22] 154 | set_location_assignment PIN_AV27 -to hps_memory_mem_dq[23] 155 | set_location_assignment PIN_AH24 -to hps_memory_mem_dq[24] 156 | set_location_assignment PIN_AH23 -to hps_memory_mem_dq[25] 157 | set_location_assignment PIN_AG25 -to hps_memory_mem_dq[26] 158 | set_location_assignment PIN_AF24 -to hps_memory_mem_dq[27] 159 | set_location_assignment PIN_AF25 -to hps_memory_mem_dq[28] 160 | set_location_assignment PIN_AJ24 -to hps_memory_mem_dq[29] 161 | set_location_assignment PIN_AJ23 -to hps_memory_mem_dq[30] 162 | set_location_assignment PIN_AJ26 -to hps_memory_mem_dq[31] 163 | set_location_assignment PIN_AM25 -to hps_memory_mem_dqs[0] 164 | set_location_assignment PIN_AT25 -to hps_memory_mem_dqs[1] 165 | set_location_assignment PIN_AW26 -to hps_memory_mem_dqs[2] 166 | set_location_assignment PIN_AK25 -to hps_memory_mem_dqs[3] 167 | set_location_assignment PIN_AL25 -to hps_memory_mem_dqs_n[0] 168 | set_location_assignment PIN_AT24 -to hps_memory_mem_dqs_n[1] 169 | set_location_assignment PIN_AW25 -to hps_memory_mem_dqs_n[2] 170 | set_location_assignment PIN_AJ25 -to hps_memory_mem_dqs_n[3] 171 | set_location_assignment PIN_K16 -to hps_sdio_CLK 172 | set_location_assignment PIN_H16 -to hps_sdio_CMD 173 | set_location_assignment PIN_E16 -to hps_sdio_D0 174 | set_location_assignment PIN_G16 -to hps_sdio_D1 175 | set_location_assignment PIN_H17 -to hps_sdio_D2 176 | set_location_assignment PIN_F15 -to hps_sdio_D3 177 | set_location_assignment PIN_M19 -to hps_sdio_D4 178 | set_location_assignment PIN_E15 -to hps_sdio_D5 179 | set_location_assignment PIN_J16 -to hps_sdio_D6 180 | set_location_assignment PIN_L18 -to hps_sdio_D7 181 | set_location_assignment PIN_D18 -to hps_usb0_CLK 182 | set_location_assignment PIN_C19 -to hps_usb0_DIR 183 | set_location_assignment PIN_F17 -to hps_usb0_NXT 184 | set_location_assignment PIN_E18 -to hps_usb0_STP 185 | set_location_assignment PIN_D19 -to hps_usb0_D0 186 | set_location_assignment PIN_E17 -to hps_usb0_D1 187 | set_location_assignment PIN_C17 -to hps_usb0_D2 188 | set_location_assignment PIN_C18 -to hps_usb0_D3 189 | set_location_assignment PIN_D21 -to hps_usb0_D4 190 | set_location_assignment PIN_D20 -to hps_usb0_D5 191 | set_location_assignment PIN_E21 -to hps_usb0_D6 192 | set_location_assignment PIN_E22 -to hps_usb0_D7 193 | set_location_assignment PIN_K18 -to hps_spim1_CLK 194 | set_location_assignment PIN_L19 -to hps_spim1_MOSI 195 | set_location_assignment PIN_H22 -to hps_spim1_MISO 196 | set_location_assignment PIN_H21 -to hps_spim1_SS0_N 197 | set_location_assignment PIN_J21 -to hps_spim1_SS1_N 198 | set_location_assignment PIN_M17 -to hps_uart1_TX 199 | set_location_assignment PIN_K17 -to hps_uart1_RX 200 | set_location_assignment PIN_L20 -to hps_i2c1_SDA 201 | set_location_assignment PIN_M20 -to hps_i2c1_SCL 202 | set_location_assignment PIN_J20 -to hps_gpio_GPIO05 203 | set_location_assignment PIN_N20 -to hps_gpio_GPIO14 204 | set_location_assignment PIN_K23 -to hps_gpio_GPIO16 205 | set_location_assignment PIN_L23 -to hps_gpio_GPIO17 206 | set_location_assignment PIN_P20 -to hps_trace_CLK 207 | set_location_assignment PIN_K22 -to hps_trace_D0 208 | set_location_assignment PIN_L22 -to hps_trace_D1 209 | set_location_assignment PIN_M22 -to hps_trace_D2 210 | set_location_assignment PIN_M21 -to hps_trace_D3 211 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_CLK 212 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_CMD 213 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D0 214 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D1 215 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D2 216 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D3 217 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D4 218 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D5 219 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D6 220 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_D7 221 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_TX_CLK 222 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_TX_CTL 223 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_TXD0 224 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_TXD1 225 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_TXD2 226 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_TXD3 227 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_RX_CLK 228 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_RX_CTL 229 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_RXD0 230 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_RXD1 231 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_RXD2 232 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_RXD3 233 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_MDC 234 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_emac0_MDIO 235 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spim1_CLK 236 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spim1_MOSI 237 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spim1_MISO 238 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spim1_SS0_N 239 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_spim1_SS1_N 240 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart1_TX 241 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart1_RX 242 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_CLK 243 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_DIR 244 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_NXT 245 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_STP 246 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D0 247 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D1 248 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D2 249 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D3 250 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D4 251 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D5 252 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D6 253 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb0_D7 254 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c1_SDA 255 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c1_SCL 256 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio_GPIO05 257 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio_GPIO14 258 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio_GPIO16 259 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio_GPIO17 260 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_CLK 261 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_D0 262 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_D1 263 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_D2 264 | set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_trace_D3 265 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_CLK 266 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_CMD 267 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_D0 268 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_D1 269 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_D2 270 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_D3 271 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_D4 272 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_D5 273 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_D6 274 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_D7 275 | set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_CLK 276 | set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_CMD 277 | set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_D0 278 | set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_D1 279 | set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_D2 280 | set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_D3 281 | set_instance_assignment -name OUTPUT_DELAY_CHAIN 8 -to hps_emac0_TX_CLK 282 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 283 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top 284 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 285 | set_location_assignment PIN_AN29 -to pcie_ep_refclk_100 286 | set_location_assignment PIN_AU37 -to pcie_ep_tx_out0 287 | set_location_assignment PIN_AN33 -to pcie_ep_rx_in0 288 | set_location_assignment PIN_AT35 -to pcie_ep_tx_out1 289 | set_location_assignment PIN_AM35 -to pcie_ep_rx_in2 290 | set_location_assignment PIN_AT39 -to pcie_ep_tx_out2 291 | set_location_assignment PIN_AR37 -to pcie_ep_tx_out3 292 | set_location_assignment PIN_AL33 -to pcie_ep_rx_in3 293 | set_location_assignment PIN_AM31 -to pcie_ep_rx_in1 294 | set_instance_assignment -name IO_STANDARD HCSL -to pcie_ep_refclk_100 295 | set_location_assignment PIN_AN28 -to "pcie_ep_refclk_100(n)" 296 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_rx_in0 297 | set_location_assignment PIN_AN32 -to "pcie_ep_rx_in0(n)" 298 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_rx_in1 299 | set_location_assignment PIN_AM30 -to "pcie_ep_rx_in1(n)" 300 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_rx_in2 301 | set_location_assignment PIN_AM34 -to "pcie_ep_rx_in2(n)" 302 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_rx_in3 303 | set_location_assignment PIN_AL32 -to "pcie_ep_rx_in3(n)" 304 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_tx_out0 305 | set_location_assignment PIN_AU36 -to "pcie_ep_tx_out0(n)" 306 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_tx_out3 307 | set_location_assignment PIN_AR36 -to "pcie_ep_tx_out3(n)" 308 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_tx_out2 309 | set_location_assignment PIN_AT38 -to "pcie_ep_tx_out2(n)" 310 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie_ep_tx_out1 311 | set_location_assignment PIN_AT34 -to "pcie_ep_tx_out1(n)" 312 | set_global_assignment -name SEARCH_PATH ../../lib 313 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 314 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 315 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 316 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 317 | set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_ep_perst 318 | set_location_assignment PIN_AW16 -to hps_pcie_a10_hip_avmm_0_npor_pin_perst 319 | set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION" 320 | set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED" 321 | set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" 322 | set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED 323 | set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON 324 | set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to fpga_clk_100 325 | 326 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 327 | --------------------------------------------------------------------------------