├── demo.gif ├── Files ├── logo.png └── 8080asm.pdf ├── Tests ├── LinuxMain.swift └── Emul8080rTests │ ├── Fakes │ └── FakeClock.swift │ ├── XCTestManifests.swift │ └── Emul8080rTests.swift ├── Sources └── Emul8080r │ ├── Utils │ └── UInt8+Extensions.swift │ ├── Bitmap.swift │ ├── Disassembler.swift │ ├── State.swift │ ├── CPU+InstructionHelpers.swift │ ├── OpCode.swift │ └── CPU.swift ├── Package.swift ├── .gitignore ├── README.md └── LICENSE /demo.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/timsearle/emul8080r/HEAD/demo.gif -------------------------------------------------------------------------------- /Files/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/timsearle/emul8080r/HEAD/Files/logo.png -------------------------------------------------------------------------------- /Files/8080asm.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/timsearle/emul8080r/HEAD/Files/8080asm.pdf -------------------------------------------------------------------------------- /Tests/LinuxMain.swift: -------------------------------------------------------------------------------- 1 | import XCTest 2 | 3 | import Emul8080rTests 4 | 5 | var tests = [XCTestCaseEntry]() 6 | tests += Emul8080rTests.allTests() 7 | XCTMain(tests) 8 | -------------------------------------------------------------------------------- /Tests/Emul8080rTests/Fakes/FakeClock.swift: -------------------------------------------------------------------------------- 1 | import Foundation 2 | @testable import Emul8080r 3 | 4 | struct FakeClock: SystemClock { 5 | func currentMicroseconds() -> Double { 6 | 0 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /Tests/Emul8080rTests/XCTestManifests.swift: -------------------------------------------------------------------------------- 1 | import XCTest 2 | 3 | #if !canImport(ObjectiveC) 4 | public func allTests() -> [XCTestCaseEntry] { 5 | return [ 6 | testCase(Emul8080rTests.allTests), 7 | ] 8 | } 9 | #endif 10 | -------------------------------------------------------------------------------- /Sources/Emul8080r/Utils/UInt8+Extensions.swift: -------------------------------------------------------------------------------- 1 | public extension FixedWidthInteger { 2 | var hex: String { 3 | String(self, radix: 16) 4 | } 5 | 6 | var bits: [UInt8] { 7 | var byte = self 8 | var bits = [UInt8](repeating: 0x00, count: 8) 9 | for i in 0..<8 { 10 | let currentBit = byte & 0x01 11 | if currentBit != 0 { 12 | bits[i] = 0xff 13 | } 14 | 15 | byte >>= 1 16 | } 17 | 18 | return bits 19 | } 20 | 21 | init(_ value: Bool) { 22 | self = value ? 1 : 0 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /Sources/Emul8080r/Bitmap.swift: -------------------------------------------------------------------------------- 1 | public struct Bitmap { 2 | public private(set) var pixels: [UInt8] 3 | public let width: Int 4 | 5 | public init(width: Int, pixels: [UInt8]) { 6 | self.width = width 7 | self.pixels = pixels 8 | } 9 | } 10 | 11 | public extension Bitmap { 12 | var height: Int { 13 | return pixels.count / width 14 | } 15 | 16 | subscript(x: Int, y: Int) -> UInt8 { 17 | get { return pixels[y * width + x] } 18 | set { 19 | guard x >= 0, y >= 0, x < width, y < height else { return } 20 | pixels[y * width + x] = newValue 21 | } 22 | } 23 | 24 | init(width: Int, height: Int, color: UInt8) { 25 | self.pixels = Array(repeating: color, count: width * height) 26 | self.width = width 27 | } 28 | } 29 | -------------------------------------------------------------------------------- /Package.swift: -------------------------------------------------------------------------------- 1 | // swift-tools-version:5.3 2 | // The swift-tools-version declares the minimum version of Swift required to build this package. 3 | 4 | import PackageDescription 5 | 6 | let package = Package( 7 | name: "Emul8080r", 8 | products: [ 9 | // Products define the executables and libraries a package produces, and make them visible to other packages. 10 | .library( 11 | name: "Emul8080r", 12 | targets: ["Emul8080r"]), 13 | ], 14 | dependencies: [ 15 | // Dependencies declare other packages that this package depends on. 16 | // .package(url: /* package url */, from: "1.0.0"), 17 | ], 18 | targets: [ 19 | // Targets are the basic building blocks of a package. A target can define a module or a test suite. 20 | // Targets can depend on other targets in this package, and on products in packages this package depends on. 21 | .target( 22 | name: "Emul8080r", 23 | dependencies: []), 24 | .testTarget( 25 | name: "Emul8080rTests", 26 | dependencies: ["Emul8080r"]), 27 | ] 28 | ) 29 | -------------------------------------------------------------------------------- /Sources/Emul8080r/Disassembler.swift: -------------------------------------------------------------------------------- 1 | struct Disassembler { 2 | enum Error: Swift.Error { 3 | case unknownCode(String) 4 | } 5 | 6 | let data: [UInt8] 7 | 8 | func run() throws { 9 | var offset = 0 10 | 11 | while offset < data.count { 12 | do { 13 | offset += try disassembleOpCode(offset: offset) 14 | } catch { 15 | throw error 16 | } 17 | } 18 | } 19 | 20 | func disassembleOpCode(offset: Int) throws -> Int { 21 | guard let code = OpCode(rawValue: data[offset]) else { 22 | throw Error.unknownCode("PC: \(String(offset, radix: 16)): \(String(data[offset], radix: 16))") 23 | } 24 | 25 | var value = 1 26 | 27 | print("0x\(String(offset, radix: 16)) \(code)", terminator: " ") 28 | 29 | var hex = "" 30 | 31 | while value < code.size { 32 | hex.insert(contentsOf: String(data[offset + value], radix: 16), at: hex.startIndex) 33 | value += 1 34 | } 35 | 36 | if !hex.isEmpty { 37 | hex.insert(contentsOf: "0x", at: hex.startIndex) 38 | } 39 | 40 | print(hex) 41 | 42 | return code.size 43 | } 44 | } 45 | -------------------------------------------------------------------------------- /Sources/Emul8080r/State.swift: -------------------------------------------------------------------------------- 1 | public struct ConditionBits: Codable, Equatable { 2 | var zero: UInt8 = 0 3 | var sign: UInt8 = 0 4 | var parity: UInt8 = 0 5 | var carry: UInt8 = 0 6 | var aux_carry: UInt8 = 0 7 | 8 | var byte: UInt8 { 9 | UInt8("\(sign)\(zero)0\(aux_carry)0\(parity)1\(carry)", radix: 2)! 10 | } 11 | } 12 | 13 | public struct Registers: CustomStringConvertible, Codable, Equatable { 14 | var a: UInt8 = 0 15 | var b: UInt8 = 0 16 | var c: UInt8 = 0 17 | var d: UInt8 = 0 18 | var e: UInt8 = 0 19 | var h: UInt8 = 0 20 | var l: UInt8 = 0 21 | 22 | public var description: String { 23 | """ 24 | a: \(a.hex) 25 | b: \(b.hex) 26 | c: \(c.hex) 27 | d: \(d.hex) 28 | e: \(e.hex) 29 | h: \(h.hex) 30 | l: \(l.hex) 31 | """ 32 | } 33 | } 34 | 35 | public struct State8080: CustomStringConvertible, Codable, Equatable { 36 | var registers = Registers() 37 | 38 | var sp: Int = 0 39 | var pc: Int = 0 40 | var condition_bits = ConditionBits() 41 | 42 | var inte = UInt8(0) // Interrupts Enabled 43 | 44 | var memory: [UInt8] 45 | 46 | public init(memory: [UInt8]) { 47 | self.memory = memory 48 | } 49 | 50 | mutating func updateConditionBits(_ byte: UInt8) { 51 | var bits = String(byte, radix: 2).map { UInt8("\($0)")! } 52 | 53 | while bits.count < 8 { 54 | bits.insert(0, at: 0) 55 | } 56 | 57 | condition_bits.sign = bits[0] 58 | condition_bits.zero = bits[1] 59 | condition_bits.aux_carry = bits[3] 60 | condition_bits.parity = bits[5] 61 | condition_bits.carry = bits[7] 62 | } 63 | 64 | public var description: String { 65 | """ 66 | \n 67 | -= 8080 Internal State =- 68 | Program Counter: \(pc) 69 | Stack Pointer: \(sp) 70 | \(condition_bits) 71 | \(registers) 72 | """ 73 | } 74 | } 75 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | # Xcode 3 | # 4 | # gitignore contributors: remember to update Global/Xcode.gitignore, Objective-C.gitignore & Swift.gitignore 5 | 6 | ## User settings 7 | xcuserdata/ 8 | 9 | ## compatibility with Xcode 8 and earlier (ignoring not required starting Xcode 9) 10 | *.xcscmblueprint 11 | *.xccheckout 12 | 13 | ## compatibility with Xcode 3 and earlier (ignoring not required starting Xcode 4) 14 | build/ 15 | DerivedData/ 16 | *.moved-aside 17 | *.pbxuser 18 | !default.pbxuser 19 | *.mode1v3 20 | !default.mode1v3 21 | *.mode2v3 22 | !default.mode2v3 23 | *.perspectivev3 24 | !default.perspectivev3 25 | 26 | ## Obj-C/Swift specific 27 | *.hmap 28 | 29 | ## App packaging 30 | *.ipa 31 | *.dSYM.zip 32 | *.dSYM 33 | 34 | ## Playgrounds 35 | timeline.xctimeline 36 | playground.xcworkspace 37 | 38 | # Swift Package Manager 39 | # 40 | # Add this line if you want to avoid checking in source code from Swift Package Manager dependencies. 41 | # Packages/ 42 | # Package.pins 43 | # Package.resolved 44 | # *.xcodeproj 45 | # 46 | # Xcode automatically generates this directory with a .xcworkspacedata file and xcuserdata 47 | # hence it is not needed unless you have added a package configuration file to your project 48 | .swiftpm 49 | 50 | .build/ 51 | 52 | # CocoaPods 53 | # 54 | # We recommend against adding the Pods directory to your .gitignore. However 55 | # you should judge for yourself, the pros and cons are mentioned at: 56 | # https://guides.cocoapods.org/using/using-cocoapods.html#should-i-check-the-pods-directory-into-source-control 57 | # 58 | # Pods/ 59 | # 60 | # Add this line if you want to avoid checking in source code from the Xcode workspace 61 | # *.xcworkspace 62 | 63 | # Carthage 64 | # 65 | # Add this line if you want to avoid checking in source code from Carthage dependencies. 66 | # Carthage/Checkouts 67 | 68 | Carthage/Build/ 69 | 70 | # Accio dependency management 71 | Dependencies/ 72 | .accio/ 73 | 74 | # fastlane 75 | # 76 | # It is recommended to not store the screenshots in the git repo. 77 | # Instead, use fastlane to re-generate the screenshots whenever they are needed. 78 | # For more information about the recommended setup visit: 79 | # https://docs.fastlane.tools/best-practices/source-control/#source-control 80 | 81 | fastlane/report.xml 82 | fastlane/Preview.html 83 | fastlane/screenshots/**/*.png 84 | fastlane/test_output 85 | 86 | # Code Injection 87 | # 88 | # After new code Injection tools there's a generated folder /iOSInjectionProject 89 | # https://github.com/johnno1962/injectionforxcode 90 | 91 | iOSInjectionProject/ 92 | -------------------------------------------------------------------------------- /Tests/Emul8080rTests/Emul8080rTests.swift: -------------------------------------------------------------------------------- 1 | import XCTest 2 | @testable import Emul8080r 3 | 4 | final class Emul8080rTests: XCTestCase { 5 | func testBasicInstructionSequence() throws { 6 | // Increment BC, Increment BC, Add immediate value 0x01 to accumulator, Add C to accumulator 7 | let program: [UInt8] = [OpCode.inx_b_c.rawValue, 8 | OpCode.inx_b_c.rawValue, 9 | OpCode.adi.rawValue, 0x01, 10 | OpCode.add_c.rawValue] 11 | 12 | let cpu = CPU(memory: program, systemClock: FakeClock()) 13 | 14 | for _ in 0..<4 { 15 | _ = try cpu.execute() 16 | } 17 | 18 | XCTAssertEqual(cpu.state.registers.a, 3) 19 | XCTAssertEqual(cpu.state.registers.b, 0) 20 | XCTAssertEqual(cpu.state.registers.c, 2) 21 | } 22 | 23 | func test_STAX_bc() throws { 24 | let program: [UInt8] = [OpCode.adi.rawValue, 0x01, 25 | OpCode.mvi_c.rawValue, 0x05, 26 | OpCode.stax_b_c.rawValue, 0x00] 27 | 28 | let cpu = CPU(memory: program, systemClock: FakeClock()) 29 | 30 | var one = State8080(memory: program) 31 | one.registers.a = 0x01 32 | one.pc = 2 33 | 34 | var two = one 35 | two.pc = 4 36 | two.registers.c = 0x05 37 | 38 | var three = two 39 | three.pc = 5 40 | three.memory[0x05] = 1 41 | 42 | let expected = [one, two, three] 43 | 44 | for i in 0..<3 { 45 | _ = try cpu.execute() 46 | XCTAssertEqual(cpu.state, expected[i]) 47 | } 48 | } 49 | 50 | func test_DCX_bc() throws { 51 | let program: [UInt8] = populateRegisters(b: 0x05, c: 0x05) + [OpCode.dcx_b_c.rawValue] 52 | 53 | let cpu = CPU(memory: program, systemClock: FakeClock()) 54 | 55 | var expected = State8080(memory: program) 56 | expected.pc = 5 57 | expected.registers.b = 0x05 58 | expected.registers.c = 0x04 59 | 60 | while true { 61 | do { 62 | _ = try cpu.execute() 63 | } catch CPU.Error.programTerminated { 64 | break 65 | } catch { 66 | throw error 67 | } 68 | } 69 | 70 | XCTAssertEqual(cpu.state, expected) 71 | } 72 | 73 | func test_XRA_a() throws { 74 | let program: [UInt8] = populateRegisters(a: 0x01) + [OpCode.xra_a.rawValue] 75 | 76 | let cpu = CPU(memory: program, systemClock: FakeClock()) 77 | 78 | var expected = State8080(memory: program) 79 | expected.registers.a = 0x00 80 | expected.pc = 3 81 | expected.condition_bits.parity = 1 82 | expected.condition_bits.zero = 1 83 | 84 | while true { 85 | do { 86 | _ = try cpu.execute() 87 | } catch CPU.Error.programTerminated { 88 | break 89 | } catch { 90 | throw error 91 | } 92 | } 93 | 94 | XCTAssertEqual(cpu.state, expected) 95 | } 96 | 97 | func test_XRA_b() throws { 98 | let program: [UInt8] = populateRegisters(a: 0x01, b: 0x0a) + [OpCode.xra_b.rawValue] 99 | 100 | let cpu = CPU(memory: program, systemClock: FakeClock()) 101 | 102 | var expected = State8080(memory: program) 103 | expected.registers.a = 0x0b 104 | expected.registers.b = 0x0a 105 | expected.pc = 5 106 | expected.condition_bits.parity = 0 107 | expected.condition_bits.zero = 0 108 | 109 | while true { 110 | do { 111 | _ = try cpu.execute() 112 | } catch CPU.Error.programTerminated { 113 | break 114 | } catch { 115 | throw error 116 | } 117 | } 118 | 119 | XCTAssertEqual(cpu.state, expected) 120 | } 121 | 122 | private func populateRegisters(a: UInt8? = nil, b: UInt8? = nil, c: UInt8? = nil, d: UInt8? = nil, e: UInt8? = nil, h: UInt8? = nil, l: UInt8? = nil) -> [UInt8] { 123 | [ 124 | a.map { [OpCode.mvi_a.rawValue, $0] }, 125 | b.map { [OpCode.mvi_b.rawValue, $0] }, 126 | c.map { [OpCode.mvi_c.rawValue, $0] }, 127 | d.map { [OpCode.mvi_d.rawValue, $0] }, 128 | e.map { [OpCode.mvi_e.rawValue, $0] }, 129 | h.map { [OpCode.mvi_h.rawValue, $0] }, 130 | l.map { [OpCode.mvi_l.rawValue, $0] } 131 | ] 132 | .compactMap { $0 } 133 | .flatMap { $0 } 134 | } 135 | 136 | static var allTests = [ 137 | ("testBasicInstructionSequence", testBasicInstructionSequence), 138 | ] 139 | } 140 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 |

2 | Emul8080r 3 |

4 | 5 |

6 | 7 | 8 | Swift Package Manager 9 | 10 | iOS + Mac + Linux 11 |

12 | 13 | **Emul8080r** is an Intel 8080 emulator written in Swift! Created initially to support a full emulation of the classic Space Invaders 👾 game on Apple platforms, found [here](https://github.com/timsearle/SpaceInvaders). 14 | 15 | ### Getting started 16 | 17 | The core type to get started with is `CPU`, this is where the all the instruction handling is interpreted, with all the helper functions for each instruction found in `CPU+InstructionHelpers`. Get started by initialising an instance of `CPU` with the available RAM and an implementation of a `SystemClock` to allow the emulate to approximate the speed at which it should be operating on the native system. 18 | 19 | The Intel 8080 supported 256 instructions and emul8080r handles this via a switch from `0x00` through to `0xff`. 20 | 21 | ### In action 22 | 23 | 24 | 25 | ### Work in progress 26 | 27 | There are still many unimplemented instructions as the initial goal was to get Space Invaders running, over time will finalise populating these missing instructions and contributions are of course welcome! 28 | 29 | There is a chance there are currently issues with certain instructions that yet to be discovered - I did not prioritise unit tests during the initial implementation but this is something planned to be improved over time! If you spot an issue, feel free to raise a PR. 30 | 31 | **Outstanding Instructions** 32 | 33 | | Instruction Value | Instruction Name | 34 | | ------------------- | ------------------- | 35 | | 0x08 | ? | 36 | | 0x10 | ? | 37 | | 0x17 | RAL | 38 | | 0x18 | ? | 39 | | 0x1c | INR E | 40 | | 0x1d | DCR E | 41 | | 0x20 | ? | 42 | | 0x25 | DCR H | 43 | | 0x28 | ? | 44 | | 0x2d | DCR L | 45 | | 0x30 | ? | 46 | | 0x33 | INX SP | 47 | | 0x38 | ? | 48 | | 0x39 | DAD SP | 49 | | 0x3b | DCX SP | 50 | | 0x3f | CMC | 51 | | 0x76 | HLT | 52 | | 0x98 | SBB B | 53 | | 0x99 | SBB C | 54 | | 0x9a | SBB D | 55 | | 0x9b | SBB E | 56 | | 0x9c | SBB H | 57 | | 0x9d | SBB L | 58 | | 0x9e | SBB M | 59 | | 0x9f | SBB A | 60 | | 0xc7 | RST 0 | 61 | | 0xcb | ? | 62 | | 0xce | ACI D8 | 63 | | 0xcf | RST 1 | 64 | | 0xd7 | RST 2 | 65 | | 0xd9 | ? | 66 | | 0xdc | CC adr | 67 | | 0xdd | ? | 68 | | 0xdf | RST 3 | 69 | | 0xe2 | JPO adr | 70 | | 0xe4 | CPO adr | 71 | | 0xe7 | RST 4 | 72 | | 0xea | JPE adr | 73 | | 0xec | CPE adr | 74 | | 0xed | ? | 75 | | 0xee | XRI D8 | 76 | | 0xef | RST 5 | 77 | | 0xf2 | JP adr | 78 | | 0xf4 | CP adr | 79 | | 0xf7 | RST 6 | 80 | | 0xf9 | SPHL | 81 | | 0xfc | CM adr | 82 | | 0xfd | ? | 83 | | 0xff | RST 7 | 84 | 85 | ### Thanks 86 | 87 | * [emulator101.com](https://www.emulator101.com) - if it wasn't for this site, this almost certainly would've taken me far longer to produce. 88 | * [classiccmp.org](http://www.classiccmp.org/dunfield/r/8080.txt) - a brilliant, high-level mapping of instruction values to descriptions 89 | * [computerarcheology.com](http://computerarcheology.com/Arcade/SpaceInvaders/) - this site proved invaluable for debugging my implementation, understanding ROM and RAM ranges and just how Space Invaders originally operated on the 8080 and its associated hardware, helping me to build my own version [here](https://github.com/timsearle/SpaceInvaders). 90 | * Official Intel 8080 Assembly manual 91 | 92 | ### Contributing 93 | 94 | Happy to receive any and all contributions relating directly to making this package a more accurate reflection of an Intel 8080 processor! Please do raise PRs including instruction implementations/bug fixes/enhancements alongside a unit test. 95 | -------------------------------------------------------------------------------- /Sources/Emul8080r/CPU+InstructionHelpers.swift: -------------------------------------------------------------------------------- 1 | extension CPU { 2 | // MARK: Control Flow 3 | func jump() { 4 | state.pc = Int(addressRegisterPair(state.memory[state.pc + 2], state.memory[state.pc + 1])) 5 | } 6 | 7 | func ret() throws { 8 | let (high, low) = try pop() 9 | state.pc = Int(addressRegisterPair(high, low)) 10 | } 11 | 12 | func call() throws { 13 | let returnAddress = state.pc + 3 14 | try push(high: UInt8((returnAddress >> 8) & 0xff), low: UInt8(returnAddress & 0xff)) 15 | jump() 16 | } 17 | 18 | // MARK: Arithmetic 19 | func increment(_ register: Register) throws { 20 | let result: UInt8 21 | 22 | switch register { 23 | case .b: 24 | (result, _) = state.registers.b.addingReportingOverflow(1) 25 | state.registers.b = result 26 | case .c: 27 | (result, _) = state.registers.c.addingReportingOverflow(1) 28 | state.registers.c = result 29 | case .d: 30 | (result, _) = state.registers.d.addingReportingOverflow(1) 31 | state.registers.d = result 32 | case .e: 33 | (result, _) = state.registers.e.addingReportingOverflow(1) 34 | state.registers.e = result 35 | case .h: 36 | (result, _) = state.registers.h.addingReportingOverflow(1) 37 | state.registers.h = result 38 | case .l: 39 | (result, _) = state.registers.l.addingReportingOverflow(1) 40 | state.registers.l = result 41 | case .m: 42 | let address = m_address() 43 | let value = state.memory[address] 44 | (result, _) = value.addingReportingOverflow(1) 45 | try write(result, at: address) 46 | case .a: 47 | (result, _) = state.registers.a.addingReportingOverflow(1) 48 | state.registers.a = result 49 | } 50 | 51 | updateZSP(Int(result)) 52 | } 53 | 54 | func decrement(_ register: Register) throws { 55 | let result: UInt8 56 | 57 | switch register { 58 | case .b: 59 | (result, _) = state.registers.b.subtractingReportingOverflow(1) 60 | state.registers.b = result 61 | case .c: 62 | (result, _) = state.registers.c.subtractingReportingOverflow(1) 63 | state.registers.c = result 64 | case .d: 65 | (result, _) = state.registers.d.subtractingReportingOverflow(1) 66 | state.registers.d = result 67 | case .e: 68 | (result, _) = state.registers.e.subtractingReportingOverflow(1) 69 | state.registers.e = result 70 | case .h: 71 | (result, _) = state.registers.h.subtractingReportingOverflow(1) 72 | state.registers.h = result 73 | case .l: 74 | (result, _) = state.registers.l.subtractingReportingOverflow(1) 75 | state.registers.l = result 76 | case .m: 77 | let address = m_address() 78 | let value = state.memory[address] 79 | (result, _) = value.subtractingReportingOverflow(1) 80 | try write(result, at: address) 81 | case .a: 82 | (result, _) = state.registers.a.subtractingReportingOverflow(1) 83 | state.registers.a = result 84 | } 85 | 86 | updateZSP(Int(result)) 87 | } 88 | 89 | func compare(_ value: Int) { 90 | let accumulator = Int(state.registers.a) 91 | state.condition_bits.carry = UInt8(value > accumulator) 92 | updateZSP(accumulator - value) 93 | } 94 | 95 | // MARK: Stack 96 | func push(high: UInt8, low: UInt8) throws { 97 | try write(high, at: state.sp - 1) 98 | try write(low, at: state.sp - 2) 99 | state.sp -= 2 100 | } 101 | 102 | func pop() throws -> (UInt8, UInt8) { 103 | let high = state.memory[state.sp + 1] 104 | let low = state.memory[state.sp] 105 | state.sp += 2 106 | 107 | return (high, low) 108 | } 109 | 110 | // MARK: Mutating Memory 111 | func write(_ value: UInt16, pair: RegisterPair) { 112 | let highValue = UInt8(value >> 8) 113 | let lowValue = UInt8(value & 0xff) 114 | 115 | switch pair { 116 | case .bc: 117 | state.registers.b = highValue 118 | state.registers.c = lowValue 119 | case .de: 120 | state.registers.d = highValue 121 | state.registers.e = lowValue 122 | case .hl: 123 | state.registers.h = highValue 124 | state.registers.l = lowValue 125 | } 126 | } 127 | 128 | func writeImmediate(to pair: RegisterPair) { 129 | write(addressRegisterPair(state.memory[state.pc + 2], state.memory[state.pc + 1]), pair: pair) 130 | } 131 | 132 | func write(_ value: UInt8, at address: Int) throws { 133 | if let bounds = safeMemoryBounds { 134 | guard address >= bounds.lowerBound && address <= bounds.upperBound else { 135 | throw Error.cannotWriteToROM(address) 136 | } 137 | } 138 | state.memory[address] = value 139 | } 140 | 141 | // MARK: Addressing 142 | func addressRegisterPair(_ high: UInt8, _ low: UInt8) -> UInt16 { 143 | return UInt16(high) << 8 | UInt16(low) 144 | } 145 | 146 | func m_address() -> Int { 147 | return Int(addressRegisterPair(state.registers.h, state.registers.l)) 148 | } 149 | 150 | // MARK: Condition Bits 151 | func updateZSP(_ value: Int) { 152 | state.condition_bits.zero = UInt8((value & 0xff) == 0) 153 | state.condition_bits.sign = UInt8(0x80 == (value & 0x80)) 154 | state.condition_bits.parity = parity(value & 0xff) 155 | } 156 | 157 | func updateArithmeticZSPC(_ value: Int, overflow: Bool) { 158 | state.condition_bits.zero = UInt8((value & 0xff) == 0) 159 | state.condition_bits.sign = UInt8(0x80 == (value & 0x80)) 160 | state.condition_bits.parity = parity(value & 0xff) 161 | state.condition_bits.carry = UInt8(overflow) 162 | } 163 | 164 | func updateLogicZSPC(_ value: Int) { 165 | state.condition_bits.zero = UInt8((value & 0xff) == 0) 166 | state.condition_bits.sign = UInt8(0x80 == (value & 0x80)) 167 | state.condition_bits.parity = parity(value & 0xff) 168 | state.condition_bits.carry = 0 169 | } 170 | 171 | func parity(_ value: Int) -> UInt8 { 172 | let binary = String(value, radix: 2) 173 | return UInt8(binary.filter { $0 == "1" }.count % 2 == 0) 174 | } 175 | } 176 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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-------------------------------------------------------------------------------- 1 | public enum OpCode: UInt8, CustomStringConvertible { 2 | case nop = 0x00 3 | case lxi_b_c = 0x01 4 | case stax_b_c = 0x02 5 | case inx_b_c = 0x03 6 | case inr_b = 0x04 7 | case dcr_b = 0x05 8 | case mvi_b = 0x06 9 | case rlc = 0x07 10 | case dad_b_c = 0x09 11 | case ldax_b_c = 0x0a 12 | case dcx_b_c = 0x0b 13 | case inr_c = 0x0c 14 | case dcr_c = 0x0d 15 | case mvi_c = 0x0e 16 | case rrc = 0x0f 17 | case lxi_d_e = 0x11 18 | case stax_d_e = 0x12 19 | case inx_d_e = 0x13 20 | case inr_d = 0x14 21 | case dcr_d = 0x15 22 | case mvi_d = 0x16 23 | case dad_d_e = 0x19 24 | case inr_h = 0x24 25 | case ldax_d_e = 0x1a 26 | case dcx_d_e = 0x1b 27 | case mvi_e = 0x1e 28 | case rar = 0x1f 29 | case lxi_h_l = 0x21 30 | case shld = 0x22 31 | case inx_h_l = 0x23 32 | case mvi_h = 0x26 33 | case daa = 0x27 34 | case dad_h_l = 0x29 35 | case lhld = 0x2a 36 | case dcx_h_l = 0x2b 37 | case inr_l = 0x2c 38 | case mvi_l = 0x2e 39 | case cma = 0x2f 40 | case lxi_sp = 0x31 41 | case sta = 0x32 42 | case inr_m = 0x34 43 | case dcr_m = 0x35 44 | case mvi_m = 0x36 45 | case stc = 0x37 46 | case lda = 0x3a 47 | case inr_a = 0x3c 48 | case dcr_a = 0x3d 49 | case mvi_a = 0x3e 50 | case mov_b_b = 0x40 51 | case mov_b_c = 0x41 52 | case mov_b_d = 0x42 53 | case mov_b_e = 0x43 54 | case mov_b_h = 0x44 55 | case mov_b_l = 0x45 56 | case mov_b_m = 0x46 57 | case mov_b_a = 0x47 58 | case mov_c_b = 0x48 59 | case mov_c_c = 0x49 60 | case mov_c_d = 0x4a 61 | case mov_c_e = 0x4b 62 | case mov_c_h = 0x4c 63 | case mov_c_l = 0x4d 64 | case mov_c_m = 0x4e 65 | case mov_c_a = 0x4f 66 | case mov_d_b = 0x50 67 | case mov_d_c = 0x51 68 | case mov_d_d = 0x52 69 | case mov_d_e = 0x53 70 | case mov_d_h = 0x54 71 | case mov_d_l = 0x55 72 | case mov_d_m = 0x56 73 | case mov_d_a = 0x57 74 | case mov_e_b = 0x58 75 | case mov_e_c = 0x59 76 | case mov_e_d = 0x5a 77 | case mov_e_e = 0x5b 78 | case mov_e_h = 0x5c 79 | case mov_e_l = 0x5d 80 | case mov_e_m = 0x5e 81 | case mov_e_a = 0x5f 82 | case mov_h_b = 0x60 83 | case mov_h_c = 0x61 84 | case mov_h_d = 0x62 85 | case mov_h_e = 0x63 86 | case mov_h_h = 0x64 87 | case mov_h_l = 0x65 88 | case mov_h_m = 0x66 89 | case mov_h_a = 0x67 90 | case mov_l_b = 0x68 91 | case mov_l_c = 0x69 92 | case mov_l_d = 0x6a 93 | case mov_l_e = 0x6b 94 | case mov_l_h = 0x6c 95 | case mov_l_l = 0x6d 96 | case mov_l_m = 0x6e 97 | case mov_l_a = 0x6f 98 | case mov_m_b = 0x70 99 | case mov_m_c = 0x71 100 | case mov_m_d = 0x72 101 | case mov_m_e = 0x73 102 | case mov_m_h = 0x74 103 | case mov_m_l = 0x75 104 | case mov_m_a = 0x77 105 | case mov_a_b = 0x78 106 | case mov_a_c = 0x79 107 | case mov_a_d = 0x7a 108 | case mov_a_e = 0x7b 109 | case mov_a_h = 0x7c 110 | case mov_a_l = 0x7d 111 | case mov_a_m = 0x7e 112 | case mov_a_a = 0x7f 113 | case add_b = 0x80 114 | case add_c = 0x81 115 | case add_d = 0x82 116 | case add_e = 0x83 117 | case add_h = 0x84 118 | case add_l = 0x85 119 | case add_m = 0x86 120 | case add_a = 0x87 121 | case adc_b = 0x88 122 | case adc_c = 0x89 123 | case adc_d = 0x8a 124 | case adc_e = 0x8b 125 | case adc_h = 0x8c 126 | case adc_l = 0x8d 127 | case adc_m = 0x8e 128 | case adc_a = 0x8f 129 | case sub_b = 0x90 130 | case sub_c = 0x91 131 | case sub_d = 0x92 132 | case sub_e = 0x93 133 | case sub_h = 0x94 134 | case sub_l = 0x95 135 | case sub_m = 0x96 136 | case sub_a = 0x97 137 | case ana_b = 0xa0 138 | case ana_c = 0xa1 139 | case ana_d = 0xa2 140 | case ana_e = 0xa3 141 | case ana_h = 0xa4 142 | case ana_l = 0xa5 143 | case ana_m = 0xa6 144 | case ana_a = 0xa7 145 | case xra_b = 0xa8 146 | case xra_c = 0xa9 147 | case xra_d = 0xaa 148 | case xra_e = 0xab 149 | case xra_h = 0xac 150 | case xra_l = 0xad 151 | case xra_m = 0xae 152 | case xra_a = 0xaf 153 | case ora_b = 0xb0 154 | case ora_c = 0xb1 155 | case ora_d = 0xb2 156 | case ora_e = 0xb3 157 | case ora_h = 0xb4 158 | case ora_l = 0xb5 159 | case ora_m = 0xb6 160 | case ora_a = 0xb7 161 | case cmp_b = 0xb8 162 | case cmp_c = 0xb9 163 | case cmp_d = 0xba 164 | case cmp_e = 0xbb 165 | case cmp_h = 0xbc 166 | case cmp_l = 0xbd 167 | case cmp_m = 0xbe 168 | case cmp_a = 0xbf 169 | case rnz = 0xc0 170 | case pop_b = 0xc1 171 | case jnz = 0xc2 172 | case jmp = 0xc3 173 | case cnz = 0xc4 174 | case push_b = 0xc5 175 | case adi = 0xc6 176 | case rz = 0xc8 177 | case ret = 0xc9 178 | case jz = 0xca 179 | case cz = 0xcc 180 | case call = 0xcd 181 | case rnc = 0xd0 182 | case pop_d = 0xd1 183 | case jnc = 0xd2 184 | case out = 0xd3 185 | case cnc = 0xd4 186 | case push_d = 0xd5 187 | case sui = 0xd6 188 | case rc = 0xd8 189 | case jc = 0xda 190 | case `in` = 0xdb 191 | case sbi = 0xde 192 | case rpo = 0xe0 193 | case pop_h = 0xe1 194 | case xthl = 0xe3 195 | case push_h = 0xe5 196 | case ani = 0xe6 197 | case rpe = 0xe8 198 | case pchl = 0xe9 199 | case xchg = 0xeb 200 | case rp = 0xf0 201 | case pop_psw = 0xf1 202 | case di = 0xf3 203 | case push_psw = 0xf5 204 | case ori = 0xf6 205 | case rm = 0xf8 206 | case jm = 0xfa 207 | case ei = 0xfb 208 | case cpi = 0xfe 209 | 210 | public var cycleCount: Int { 211 | [ 212 | 4, 10, 7, 5, 5, 5, 7, 4, 4, 10, 7, 5, 5, 5, 7, 4, 213 | 4, 10, 7, 5, 5, 5, 7, 4, 4, 10, 7, 5, 5, 5, 7, 4, 214 | 4, 10, 16, 5, 5, 5, 7, 4, 4, 10, 16, 5, 5, 5, 7, 4, 215 | 4, 10, 13, 5, 10, 10, 10, 4, 4, 10, 13, 5, 5, 5, 7, 4, 216 | 217 | 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5, 218 | 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5, 219 | 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5, 220 | 7, 7, 7, 7, 7, 7, 7, 7, 5, 5, 5, 5, 5, 5, 7, 5, 221 | 222 | 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 223 | 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 224 | 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 225 | 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 226 | 227 | 11, 10, 10, 10, 17, 11, 7, 11, 11, 10, 10, 10, 10, 17, 7, 11, 228 | 11, 10, 10, 10, 17, 11, 7, 11, 11, 10, 10, 10, 10, 17, 7, 11, 229 | 11, 10, 10, 18, 17, 11, 7, 11, 11, 5, 10, 5, 17, 17, 7, 11, 230 | 11, 10, 10, 4, 17, 11, 7, 11, 11, 5, 10, 4, 17, 17, 7, 11 231 | ][Int(rawValue)] 232 | } 233 | 234 | public var size: Int { 235 | switch self { 236 | case .nop, .stax_b_c, .inx_b_c, .inr_b, .dcr_b, .rlc, .dad_b_c, .ldax_b_c, .dcx_b_c, .inr_c, .rar, .dcr_c, .rrc, .stax_d_e, .inx_d_e, .dad_d_e, .inr_h, .ldax_d_e, .dcx_d_e, .inr_d, .dcr_d, .inx_h_l, .inr_m, .daa, .dcr_a, .dad_h_l, .dcx_h_l, .inr_l, .cma, .dcr_m, .inr_a, .stc, .mov_b_b, .mov_b_c, .mov_b_d, .mov_b_e, .mov_b_h, .mov_b_l, .mov_b_m, .mov_b_a, .mov_c_b, .mov_c_c, .mov_c_d, .mov_c_e, .mov_c_h, .mov_c_l, .mov_c_m, .mov_c_a, .mov_d_b, .mov_d_c, .mov_d_d, .mov_d_e, .mov_d_h, .mov_d_l, .mov_d_m, .mov_d_a, .mov_e_b, .mov_e_c, .mov_e_d, .mov_e_e, .mov_e_h, .mov_e_l, .mov_e_m, .mov_e_a, .mov_h_b, .mov_h_c, .mov_h_d, .mov_h_e, .mov_h_h, .mov_h_l, .mov_h_m, .mov_h_a, .mov_l_b, .mov_l_c, .mov_l_d, .mov_l_e, .mov_l_h, .mov_l_l, .mov_l_m, .mov_l_a, .mov_m_b, .mov_m_c, .mov_m_d, .mov_m_e, .mov_m_h, .mov_m_l, .mov_m_a, .mov_a_b, .mov_a_c, .mov_a_d, .mov_a_e, .mov_a_h, .mov_a_l, .mov_a_m, .mov_a_a, .add_b, .add_c, .add_d, .add_e, .add_h, .add_l, .add_m, .add_a, .adc_b, .adc_c, .adc_d, .adc_e, .adc_h, .adc_l, .adc_m, .adc_a, .sub_b, .sub_c, .sub_d, .sub_e, .sub_h, .sub_l, .sub_m, .sub_a, .ana_b, .ana_c, .ana_d, .ana_e, .ana_h, .ana_l, .ana_m, .ana_a, .xra_b, .xra_c, .xra_d, .xra_e, .xra_h, .xra_l, .xra_m, .xra_a, .ora_b, .ora_c, .ora_d, .ora_e, .ora_h, .ora_l, .ora_m, .ora_a, .cmp_b, .cmp_c, .cmp_d, .cmp_e, .cmp_h, .cmp_l, .cmp_m, .cmp_a, .rnz, .pop_b, .push_b, .rz, .ret, .pop_d, .push_d, .rc, .rp, .rpo, .rpe, .rm, .rnc, .pop_h, .xthl, .push_h, .pchl, .xchg, .pop_psw, .di, .push_psw, .ei: 237 | return 1 238 | case .mvi_b, .mvi_c, .mvi_d, .mvi_e, .mvi_h, .mvi_l, .mvi_m, .mvi_a, .sui, .adi, .out, .in, .sbi, .ani, .ori, .cpi: 239 | return 2 240 | case .lhld, .lxi_b_c, .lxi_d_e, .lxi_h_l, .lxi_sp, .shld, .lda, .sta, .jmp, .cnz, .jnz, .jz, .cz, .call, .jnc, .cnc, .jc, .jm: 241 | return 3 242 | } 243 | } 244 | 245 | public var description: String { 246 | switch self { 247 | case .nop: 248 | return "NOP" 249 | case .stax_b_c: 250 | return "STAX B C" 251 | case .lxi_b_c: 252 | return "LXI B C,#" 253 | case .inx_b_c: 254 | return "INX B C" 255 | case .inr_b: 256 | return "INR B" 257 | case .rlc: 258 | return "RLC" 259 | case .dcr_b: 260 | return "DCR B" 261 | case .mvi_b: 262 | return "MVI B,#" 263 | case .dcr_c: 264 | return "DCR C" 265 | case .mvi_c: 266 | return "MVI C,#" 267 | case .dad_b_c: 268 | return "DAD B C" 269 | case .ldax_b_c: 270 | return "LDAX B C" 271 | case .dcx_b_c: 272 | return "DCX B C" 273 | case .inr_c: 274 | return "INR C" 275 | case .rrc: 276 | return "RRC" 277 | case .lxi_d_e: 278 | return "LXI D E,#" 279 | case .stax_d_e: 280 | return "STAX D E" 281 | case .inx_d_e: 282 | return "INX D E" 283 | case .inr_d: 284 | return "INR D" 285 | case .dcr_d: 286 | return "DCR D" 287 | case .mvi_d: 288 | return "MVI D,#" 289 | case .dad_d_e: 290 | return "DAD D E" 291 | case .inr_h: 292 | return "INR H" 293 | case .ldax_d_e: 294 | return "LDAX D E" 295 | case .dcx_d_e: 296 | return "DCX D E" 297 | case .mvi_e: 298 | return "MVI E,#" 299 | case .rar: 300 | return "RAR" 301 | case .lxi_h_l: 302 | return "LXI H L,#" 303 | case .lxi_sp: 304 | return "LXI SP,#" 305 | case .shld: 306 | return "SHLD" 307 | case .inx_h_l: 308 | return "INX H L" 309 | case .mvi_h: 310 | return "MVI H,#" 311 | case .daa: 312 | return "DAA" 313 | case .dad_h_l: 314 | return "DAD H L" 315 | case .lhld: 316 | return "LHLD" 317 | case .dcx_h_l: 318 | return "DCX H L" 319 | case .inr_l: 320 | return "INR L" 321 | case .mvi_l: 322 | return "MVI L,#" 323 | case .cma: 324 | return "CMA" 325 | case .sta: 326 | return "STA" 327 | case .inr_m: 328 | return "INR M" 329 | case .dcr_m: 330 | return "DCR M" 331 | case .mvi_m: 332 | return "MVI M" 333 | case .stc: 334 | return "STC" 335 | case .lda: 336 | return "LDA" 337 | case .inr_a: 338 | return "INR A" 339 | case .dcr_a: 340 | return "DCR A" 341 | case .mvi_a: 342 | return "MVI A,#" 343 | case .mov_b_b: 344 | return "MOV B, B" 345 | case .mov_b_c: 346 | return "MOV B, C" 347 | case .mov_b_d: 348 | return "MOV B, D" 349 | case .mov_b_e: 350 | return "MOV B, E" 351 | case .mov_b_h: 352 | return "MOV B, H" 353 | case .mov_b_l: 354 | return "MOV B, L" 355 | case .mov_b_m: 356 | return "MOV B, M" 357 | case .mov_b_a: 358 | return "MOV B, A" 359 | case .mov_c_b: 360 | return "MOV C, B" 361 | case .mov_c_c: 362 | return "MOV C, C" 363 | case .mov_c_d: 364 | return "MOV C, D" 365 | case .mov_c_e: 366 | return "MOV C, E" 367 | case .mov_c_h: 368 | return "MOV C, H" 369 | case .mov_c_l: 370 | return "MOV C, L" 371 | case .mov_c_m: 372 | return "MOV C, M" 373 | case .mov_c_a: 374 | return "MOV C, A" 375 | case .mov_d_b: 376 | return "MOV D, B" 377 | case .mov_d_c: 378 | return "MOV D, C" 379 | case .mov_d_d: 380 | return "MOV D, D" 381 | case .mov_d_e: 382 | return "MOV D, E" 383 | case .mov_d_h: 384 | return "MOV D, H" 385 | case .mov_d_l: 386 | return "MOV D, L" 387 | case .mov_d_m: 388 | return "MOV D, M" 389 | case .mov_d_a: 390 | return "MOV D, A" 391 | case .mov_e_b: 392 | return "MOV E, B" 393 | case .mov_e_c: 394 | return "MOV E, C" 395 | case .mov_e_d: 396 | return "MOV E, D" 397 | case .mov_e_e: 398 | return "MOV E, E" 399 | case .mov_e_h: 400 | return "MOV E, H" 401 | case .mov_e_l: 402 | return "MOV E, L" 403 | case .mov_e_m: 404 | return "MOV E, M" 405 | case .mov_e_a: 406 | return "MOV E, A" 407 | case .mov_h_b: 408 | return "MOV H, B" 409 | case .mov_h_c: 410 | return "MOV H, C" 411 | case .mov_h_d: 412 | return "MOV H, D" 413 | case .mov_h_e: 414 | return "MOV H, E" 415 | case .mov_h_h: 416 | return "MOV H, H" 417 | case .mov_h_l: 418 | return "MOV H, L" 419 | case .mov_h_m: 420 | return "MOV H, M" 421 | case .mov_h_a: 422 | return "MOV H, A" 423 | case .mov_l_b: 424 | return "MOV L, B" 425 | case .mov_l_c: 426 | return "MOV L, C" 427 | case .mov_l_d: 428 | return "MOV L, D" 429 | case .mov_l_e: 430 | return "MOV L, E" 431 | case .mov_l_h: 432 | return "MOV L, H" 433 | case .mov_l_l: 434 | return "MOV L, L" 435 | case .mov_l_m: 436 | return "MOV L, M" 437 | case .mov_l_a: 438 | return "MOV L, A" 439 | case .mov_m_b: 440 | return "MOV M, B" 441 | case .mov_m_c: 442 | return "MOV M, C" 443 | case .mov_m_d: 444 | return "MOV M, D" 445 | case .mov_m_e: 446 | return "MOV M, E" 447 | case .mov_m_h: 448 | return "MOV M, H" 449 | case .mov_m_l: 450 | return "MOV M, L" 451 | case .mov_m_a: 452 | return "MOV M, A" 453 | case .mov_a_b: 454 | return "MOV A, B" 455 | case .mov_a_c: 456 | return "MOV A, C" 457 | case .mov_a_d: 458 | return "MOV A, D" 459 | case .mov_a_e: 460 | return "MOV A, E" 461 | case .mov_a_h: 462 | return "MOV A, H" 463 | case .mov_a_l: 464 | return "MOV A, L" 465 | case .mov_a_m: 466 | return "MOV A, M" 467 | case .mov_a_a: 468 | return "MOV A, A" 469 | case .add_b: 470 | return "ADD B" 471 | case .add_c: 472 | return "ADD C" 473 | case .add_d: 474 | return "ADD D" 475 | case .add_e: 476 | return "ADD E" 477 | case .add_h: 478 | return "ADD H" 479 | case .add_l: 480 | return "ADD L" 481 | case .add_m: 482 | return "ADD M" 483 | case .add_a: 484 | return "ADD A" 485 | case .adc_b: 486 | return "ADC B" 487 | case .adc_c: 488 | return "ADC C" 489 | case .adc_d: 490 | return "ADC D" 491 | case .adc_e: 492 | return "ADC E" 493 | case .adc_h: 494 | return "ADC H" 495 | case .adc_l: 496 | return "ADC L" 497 | case .adc_m: 498 | return "ADC M" 499 | case .adc_a: 500 | return "ADC A" 501 | case .sub_b: 502 | return "SUB B" 503 | case .sub_c: 504 | return "SUB C" 505 | case .sub_d: 506 | return "SUB D" 507 | case .sub_e: 508 | return "SUB E" 509 | case .sub_h: 510 | return "SUB H" 511 | case .sub_l: 512 | return "SUB L" 513 | case .sub_m: 514 | return "SUB M" 515 | case .sub_a: 516 | return "SUB A" 517 | case .ana_b: 518 | return "ANA B" 519 | case .ana_c: 520 | return "ANA C" 521 | case .ana_d: 522 | return "ANA D" 523 | case .ana_e: 524 | return "ANA E" 525 | case .ana_h: 526 | return "ANA H" 527 | case .ana_l: 528 | return "ANA L" 529 | case .ana_m: 530 | return "ANA M" 531 | case .ana_a: 532 | return "ANA A" 533 | case .xra_b: 534 | return "XRA B" 535 | case .xra_c: 536 | return "XRA C" 537 | case .xra_d: 538 | return "XRA D" 539 | case .xra_e: 540 | return "XRA E" 541 | case .xra_h: 542 | return "XRA H" 543 | case .xra_l: 544 | return "XRA L" 545 | case .xra_m: 546 | return "XRA M" 547 | case .xra_a: 548 | return "XRA A" 549 | case .ora_b: 550 | return "ORA B" 551 | case .ora_c: 552 | return "ORA C" 553 | case .ora_d: 554 | return "ORA D" 555 | case .ora_e: 556 | return "ORA E" 557 | case .ora_h: 558 | return "ORA H" 559 | case .ora_l: 560 | return "ORA L" 561 | case .ora_m: 562 | return "ORA M" 563 | case .ora_a: 564 | return "ORA A" 565 | case .cmp_b: 566 | return "CMP B" 567 | case .cmp_c: 568 | return "CMP C" 569 | case .cmp_d: 570 | return "CMP D" 571 | case .cmp_e: 572 | return "CMP E" 573 | case .cmp_h: 574 | return "CMP H" 575 | case .cmp_l: 576 | return "CMP L" 577 | case .cmp_m: 578 | return "CMP M" 579 | case .cmp_a: 580 | return "CMP A" 581 | case .rnz: 582 | return "RNZ" 583 | case .pop_b: 584 | return "POP B" 585 | case .jnz: 586 | return "JNZ" 587 | case .jmp: 588 | return "JMP" 589 | case .cnz: 590 | return "CNZ" 591 | case .adi: 592 | return "ADI #" 593 | case .rz: 594 | return "RET Z" 595 | case .ret: 596 | return "RET" 597 | case .jz: 598 | return "JZ" 599 | case .cz: 600 | return "CZ" 601 | case .call: 602 | return "CALL" 603 | case .push_b: 604 | return "PUSH B" 605 | case .pop_d: 606 | return "POP D" 607 | case .jnc: 608 | return "JNC" 609 | case .out: 610 | return "OUT" 611 | case .cnc: 612 | return "CNC" 613 | case .push_d: 614 | return "PUSH D" 615 | case .sui: 616 | return "SUB #" 617 | case .rc: 618 | return "RET C" 619 | case .jc: 620 | return "JC" 621 | case .in: 622 | return "IN #" 623 | case .sbi: 624 | return "SUB #" 625 | case .pop_h: 626 | return "POP H" 627 | case .xthl: 628 | return "XTHL" 629 | case .push_h: 630 | return "PUSH H" 631 | case .ani: 632 | return "ANI" 633 | case .xchg: 634 | return "XCHG" 635 | case .pop_psw: 636 | return "POP PSW" 637 | case .di: 638 | return "DI" 639 | case .push_psw: 640 | return "PUSH PSW" 641 | case .ori: 642 | return "ORI #" 643 | case .rnc: 644 | return "RET NC" 645 | case .rpo: 646 | return "RET PO" 647 | case .rpe: 648 | return "RET PE" 649 | case .pchl: 650 | return "PCHL" 651 | case .rp: 652 | return "RET P" 653 | case .rm: 654 | return "RET M" 655 | case .jm: 656 | return "JMP M" 657 | case .ei: 658 | return "EI" 659 | case .cpi: 660 | return "CPI #" 661 | } 662 | } 663 | } 664 | -------------------------------------------------------------------------------- /Sources/Emul8080r/CPU.swift: -------------------------------------------------------------------------------- 1 | public protocol IOBus: AnyObject { 2 | func machineIN(port: UInt8) -> UInt8 3 | func machineOUT(port: UInt8, accumulator: UInt8) 4 | } 5 | 6 | public protocol SystemClock { 7 | func currentMicroseconds() -> Double 8 | } 9 | 10 | public final class CPU { 11 | public enum Error: Swift.Error { 12 | case missingIOHandler 13 | case unhandledOperation(OpCode) 14 | case cannotWriteToROM(Int) 15 | case unknownCode(String) 16 | case programTerminated 17 | } 18 | 19 | enum RegisterPair { 20 | case bc, de, hl 21 | } 22 | 23 | enum Register { 24 | case b, c, d, e, h, l, m, a 25 | } 26 | 27 | private let systemClock: SystemClock 28 | 29 | private var lastExecutionTime: Double = 0 30 | private var disassembler: Disassembler! 31 | 32 | public weak var bus: IOBus? 33 | 34 | public internal(set) var state: State8080 35 | 36 | let safeMemoryBounds: Range? 37 | 38 | public init(memory: [UInt8], systemClock: SystemClock, safeMemoryBounds: Range? = nil) { 39 | self.state = State8080(memory: memory) 40 | self.systemClock = systemClock 41 | self.safeMemoryBounds = safeMemoryBounds 42 | } 43 | 44 | public func load(_ data: [UInt8]) { 45 | for (offset, byte) in data.enumerated() { 46 | state.memory[offset] = byte 47 | } 48 | 49 | disassembler = Disassembler(data: data) 50 | } 51 | 52 | public func interrupt(_ value: UInt8) throws { 53 | guard state.inte == 0x01 else { 54 | return 55 | } 56 | 57 | state.inte = 0x00 // Reset the interrupt to disabled 58 | try push(high: UInt8((state.pc >> 8) & 0xff), low: UInt8(state.pc & 0xff)) 59 | state.pc = Int(8 * value) 60 | } 61 | 62 | public func start(interrupter: () -> UInt8) throws { 63 | let now = systemClock.currentMicroseconds() 64 | 65 | if lastExecutionTime == 0.0 { 66 | lastExecutionTime = now 67 | } 68 | 69 | let sinceLast = (now - lastExecutionTime) 70 | let cycles_to_catch_up = min(Int(sinceLast),10000) 71 | var cycles = 0 72 | 73 | let code = interrupter() 74 | 75 | if code != 0 { 76 | try interrupt(code) 77 | } else { 78 | while cycles_to_catch_up > cycles { 79 | cycles += try execute() 80 | } 81 | } 82 | lastExecutionTime = now 83 | } 84 | 85 | func execute() throws -> Int { 86 | guard state.pc < state.memory.count else { 87 | // End of program 88 | throw Error.programTerminated 89 | } 90 | 91 | guard let code = OpCode(rawValue: state.memory[Int(state.pc)]) else { 92 | throw Error.unknownCode(String(state.memory[Int(state.pc)], radix: 16)) 93 | } 94 | 95 | switch code { 96 | case .nop: 97 | break 98 | case .stax_b_c: 99 | let address = addressRegisterPair(state.registers.b, state.registers.c) 100 | try write(state.registers.a, at: Int(address)) 101 | case .lxi_b_c: 102 | writeImmediate(to: .bc) 103 | case .inx_b_c: 104 | let value = addressRegisterPair(state.registers.b, state.registers.c) 105 | let (result, _) = value.addingReportingOverflow(1) 106 | write(result, pair: .bc) 107 | case .inr_b: 108 | try increment(.b) 109 | case .dcr_b: 110 | try decrement(.b) 111 | case .mvi_b: 112 | state.registers.b = state.memory[state.pc + 1] 113 | case .rlc: 114 | let value = state.registers.a 115 | state.registers.a = ((value & 0x80) >> 7) | value << 1 116 | state.condition_bits.carry = UInt8((value & 0x80) == 0x80) 117 | case .dad_b_c: 118 | let bc = addressRegisterPair(state.registers.b, state.registers.c) 119 | let hl = addressRegisterPair(state.registers.h, state.registers.l) 120 | 121 | let (result, overflow) = bc.addingReportingOverflow(hl) 122 | 123 | write(result, pair: .hl) 124 | state.condition_bits.carry = UInt8(overflow) 125 | case .ldax_b_c: 126 | let address = Int(addressRegisterPair(state.registers.b, state.registers.c)) 127 | state.registers.a = state.memory[address] 128 | case .dcx_b_c: 129 | let value = addressRegisterPair(state.registers.b, state.registers.c) 130 | let (result, _) = value.subtractingReportingOverflow(1) 131 | write(result, pair: .bc) 132 | case .inr_c: 133 | try increment(.c) 134 | case .dcr_c: 135 | try decrement(.c) 136 | case .mvi_c: 137 | state.registers.c = state.memory[state.pc + 1] 138 | case .rrc: 139 | let accumulator = state.registers.a 140 | state.registers.a = ((accumulator & 1) << 7) | accumulator >> 1 141 | state.condition_bits.carry = UInt8((accumulator & 0x01) == 0x01) 142 | case .lxi_d_e: 143 | writeImmediate(to: .de) 144 | case .stax_d_e: 145 | let address = addressRegisterPair(state.registers.d, state.registers.e) 146 | try write(state.registers.a, at: Int(address)) 147 | case .inx_d_e: 148 | let value = addressRegisterPair(state.registers.d, state.registers.e) 149 | let (result, _) = value.addingReportingOverflow(1) 150 | write(result, pair: .de) 151 | case .inr_d: 152 | try increment(.d) 153 | case .dcr_d: 154 | try decrement(.d) 155 | case .mvi_d: 156 | state.registers.d = state.memory[state.pc + 1] 157 | case .dad_d_e: 158 | let de = addressRegisterPair(state.registers.d, state.registers.e) 159 | let hl = addressRegisterPair(state.registers.h, state.registers.l) 160 | 161 | let (result, overflow) = de.addingReportingOverflow(hl) 162 | 163 | write(result, pair: .hl) 164 | state.condition_bits.carry = UInt8(overflow) 165 | case .inr_h: 166 | try increment(.h) 167 | case .ldax_d_e: 168 | let address = Int(addressRegisterPair(state.registers.d, state.registers.e)) 169 | state.registers.a = state.memory[address] 170 | case .dcx_d_e: 171 | let value = addressRegisterPair(state.registers.d, state.registers.e) 172 | let (result, _) = value.subtractingReportingOverflow(1) 173 | write(result, pair: .de) 174 | case .mvi_e: 175 | state.registers.e = state.memory[state.pc + 1] 176 | case .cma: 177 | state.registers.a = ~state.registers.a 178 | case .rar: 179 | let accumulator = state.registers.a >> 1 180 | let value = accumulator | (state.condition_bits.carry << 7) 181 | state.condition_bits.carry = UInt8((state.registers.a & 0x01) == 0x01) 182 | state.registers.a = value 183 | case .lxi_h_l: 184 | writeImmediate(to: .hl) 185 | case .shld: 186 | let address = Int(addressRegisterPair(state.memory[state.pc + 2], state.memory[state.pc + 1])) 187 | try write(state.registers.l, at: address) 188 | try write(state.registers.h, at: address + 1) 189 | case .inx_h_l: 190 | let value = addressRegisterPair(state.registers.h, state.registers.l) 191 | let (result, _) = value.addingReportingOverflow(1) 192 | write(result, pair: .hl) 193 | case .daa: 194 | let lsb4 = state.registers.a & 0xf 195 | 196 | if lsb4 > 9 || state.condition_bits.aux_carry == 0x01 { 197 | let (result, overflow) = state.registers.a.addingReportingOverflow(6) 198 | state.registers.a = result 199 | updateArithmeticZSPC(Int(result), overflow: overflow) 200 | if overflow { 201 | state.condition_bits.aux_carry = 0x01 202 | } else { 203 | state.condition_bits.aux_carry = 0x00 204 | } 205 | } 206 | 207 | let msb4 = state.registers.a & 0xf0 208 | 209 | if msb4 > 0x90 || state.condition_bits.carry == 0x01 { 210 | let (result, overflow) = state.registers.a.addingReportingOverflow(0x60) 211 | state.registers.a = result 212 | updateArithmeticZSPC(Int(result), overflow: overflow) 213 | } 214 | case .mvi_h: 215 | state.registers.h = state.memory[state.pc + 1] 216 | case .dad_h_l: 217 | let hl = addressRegisterPair(state.registers.h, state.registers.l) 218 | let (result, overflow) = hl.addingReportingOverflow(hl) 219 | 220 | write(result, pair: .hl) 221 | state.condition_bits.carry = UInt8(overflow) 222 | case .lhld: 223 | let address = Int(addressRegisterPair(state.memory[state.pc + 2], state.memory[state.pc + 1])) 224 | state.registers.l = state.memory[address] 225 | state.registers.h = state.memory[address + 1] 226 | case .dcx_h_l: 227 | let value = addressRegisterPair(state.registers.h, state.registers.l) 228 | let (result, _) = value.subtractingReportingOverflow(1) 229 | write(result, pair: .hl) 230 | case .inr_l: 231 | try increment(.l) 232 | case .mvi_l: 233 | state.registers.l = state.memory[state.pc + 1] 234 | case .lxi_sp: 235 | state.sp = Int(addressRegisterPair(state.memory[state.pc + 2], state.memory[state.pc + 1])) 236 | case .sta: 237 | let address = Int(addressRegisterPair(state.memory[state.pc + 2], state.memory[state.pc + 1])) 238 | try write(state.registers.a, at: address) 239 | case .inr_m: 240 | try increment(.m) 241 | case .dcr_m: 242 | try decrement(.m) 243 | case .mvi_m: 244 | try write(state.memory[state.pc + 1], at: m_address()) 245 | case .stc: 246 | state.condition_bits.carry = 1 247 | case .lda: 248 | let address = Int(addressRegisterPair(state.memory[state.pc + 2], state.memory[state.pc + 1])) 249 | state.registers.a = state.memory[address] 250 | case .inr_a: 251 | try increment(.a) 252 | case .dcr_a: 253 | try decrement(.a) 254 | case .mvi_a: 255 | state.registers.a = state.memory[state.pc + 1] 256 | case .mov_b_b: 257 | break 258 | case .mov_b_c: 259 | state.registers.b = state.registers.c 260 | case .mov_b_d: 261 | state.registers.b = state.registers.d 262 | case .mov_b_e: 263 | state.registers.b = state.registers.e 264 | case .mov_b_h: 265 | state.registers.b = state.registers.h 266 | case .mov_b_l: 267 | state.registers.b = state.registers.l 268 | case .mov_b_m: 269 | state.registers.b = state.memory[m_address()] 270 | case .mov_b_a: 271 | state.registers.b = state.registers.a 272 | case .mov_c_b: 273 | state.registers.c = state.registers.b 274 | case .mov_c_c: 275 | break 276 | case .mov_c_d: 277 | state.registers.c = state.registers.d 278 | case .mov_c_e: 279 | state.registers.c = state.registers.e 280 | case .mov_c_h: 281 | state.registers.c = state.registers.h 282 | case .mov_c_l: 283 | state.registers.c = state.registers.l 284 | case .mov_c_m: 285 | state.registers.c = state.memory[m_address()] 286 | case .mov_c_a: 287 | state.registers.c = state.registers.a 288 | case .mov_d_b: 289 | state.registers.d = state.registers.b 290 | case .mov_d_c: 291 | state.registers.d = state.registers.c 292 | case .mov_d_d: 293 | break 294 | case .mov_d_e: 295 | state.registers.d = state.registers.e 296 | case .mov_d_h: 297 | state.registers.d = state.registers.h 298 | case .mov_d_l: 299 | state.registers.d = state.registers.l 300 | case .mov_d_m: 301 | state.registers.d = state.memory[m_address()] 302 | case .mov_d_a: 303 | state.registers.d = state.registers.a 304 | case .mov_e_b: 305 | state.registers.e = state.registers.b 306 | case .mov_e_c: 307 | state.registers.e = state.registers.c 308 | case .mov_e_d: 309 | state.registers.e = state.registers.d 310 | case .mov_e_e: 311 | break 312 | case .mov_e_h: 313 | state.registers.e = state.registers.h 314 | case .mov_e_l: 315 | state.registers.e = state.registers.l 316 | case .mov_e_m: 317 | state.registers.e = state.memory[m_address()] 318 | case .mov_e_a: 319 | state.registers.e = state.registers.a 320 | case .mov_h_b: 321 | state.registers.h = state.registers.b 322 | case .mov_h_c: 323 | state.registers.h = state.registers.c 324 | case .mov_h_d: 325 | state.registers.h = state.registers.d 326 | case .mov_h_e: 327 | state.registers.h = state.registers.e 328 | case .mov_h_h: 329 | break 330 | case .mov_h_l: 331 | state.registers.h = state.registers.l 332 | case .mov_h_m: 333 | state.registers.h = state.memory[m_address()] 334 | case .mov_h_a: 335 | state.registers.h = state.registers.a 336 | case .mov_l_b: 337 | state.registers.l = state.registers.b 338 | case .mov_l_c: 339 | state.registers.l = state.registers.c 340 | case .mov_l_d: 341 | state.registers.l = state.registers.d 342 | case .mov_l_e: 343 | state.registers.l = state.registers.e 344 | case .mov_l_h: 345 | state.registers.l = state.registers.h 346 | case .mov_l_l: 347 | break 348 | case .mov_l_m: 349 | state.registers.l = state.memory[m_address()] 350 | case .mov_l_a: 351 | state.registers.l = state.registers.a 352 | case .mov_m_b: 353 | try write(state.registers.b, at: m_address()) 354 | case .mov_m_c: 355 | try write(state.registers.c, at: m_address()) 356 | case .mov_m_d: 357 | try write(state.registers.d, at: m_address()) 358 | case .mov_m_e: 359 | try write(state.registers.e, at: m_address()) 360 | case .mov_m_h: 361 | try write(state.registers.h, at: m_address()) 362 | case .mov_m_l: 363 | try write(state.registers.l, at: m_address()) 364 | case .mov_m_a: 365 | try write(state.registers.a, at: m_address()) 366 | case .mov_a_b: 367 | state.registers.a = state.registers.b 368 | case .mov_a_c: 369 | state.registers.a = state.registers.c 370 | case .mov_a_d: 371 | state.registers.a = state.registers.d 372 | case .mov_a_e: 373 | state.registers.a = state.registers.e 374 | case .mov_a_h: 375 | state.registers.a = state.registers.h 376 | case .mov_a_l: 377 | state.registers.a = state.registers.l 378 | case .mov_a_m: 379 | state.registers.a = state.memory[m_address()] 380 | case .mov_a_a: 381 | break 382 | case .add_b: 383 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.b) 384 | state.registers.a = result 385 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 386 | case .add_c: 387 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.c) 388 | state.registers.a = result 389 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 390 | case .add_d: 391 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.d) 392 | state.registers.a = result 393 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 394 | case .add_e: 395 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.e) 396 | state.registers.a = result 397 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 398 | case .add_h: 399 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.h) 400 | state.registers.a = result 401 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 402 | case .add_l: 403 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.l) 404 | state.registers.a = result 405 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 406 | case .add_m: 407 | let value = state.memory[m_address()] 408 | let (result, overflow) = state.registers.a.addingReportingOverflow(value) 409 | state.registers.a = result 410 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 411 | case .add_a: 412 | throw Error.unhandledOperation(code) 413 | case .adc_b: 414 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.b + state.condition_bits.carry) 415 | state.registers.a = result 416 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 417 | case .adc_c: 418 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.c + state.condition_bits.carry) 419 | state.registers.a = result 420 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 421 | case .adc_d: 422 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.d + state.condition_bits.carry) 423 | state.registers.a = result 424 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 425 | case .adc_e: 426 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.e + state.condition_bits.carry) 427 | state.registers.a = result 428 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 429 | case .adc_h: 430 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.h + state.condition_bits.carry) 431 | state.registers.a = result 432 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 433 | case .adc_l: 434 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.l + state.condition_bits.carry) 435 | state.registers.a = result 436 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 437 | case .adc_m: 438 | throw Error.unhandledOperation(code) 439 | case .adc_a: 440 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.registers.a + state.condition_bits.carry) 441 | state.registers.a = result 442 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 443 | case .sub_b: 444 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.registers.b) 445 | state.registers.a = result 446 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 447 | case .sub_c: 448 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.registers.c) 449 | state.registers.a = result 450 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 451 | case .sub_d: 452 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.registers.d) 453 | state.registers.a = result 454 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 455 | case .sub_e: 456 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.registers.e) 457 | state.registers.a = result 458 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 459 | case .sub_h: 460 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.registers.h) 461 | state.registers.a = result 462 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 463 | case .sub_l: 464 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.registers.l) 465 | state.registers.a = result 466 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 467 | case .sub_m: 468 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.memory[m_address()]) 469 | state.registers.a = result 470 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 471 | case .sub_a: 472 | state.registers.a = 0 473 | updateArithmeticZSPC(0, overflow: false) 474 | case .ana_b: 475 | state.registers.a &= state.registers.b 476 | updateLogicZSPC(Int(state.registers.a)) 477 | case .ana_c: 478 | state.registers.a &= state.registers.c 479 | updateLogicZSPC(Int(state.registers.a)) 480 | case .ana_d: 481 | state.registers.a &= state.registers.d 482 | updateLogicZSPC(Int(state.registers.a)) 483 | case .ana_e: 484 | state.registers.a &= state.registers.e 485 | updateLogicZSPC(Int(state.registers.a)) 486 | case .ana_h: 487 | state.registers.a &= state.registers.h 488 | updateLogicZSPC(Int(state.registers.a)) 489 | case .ana_l: 490 | state.registers.a &= state.registers.l 491 | updateLogicZSPC(Int(state.registers.a)) 492 | case .ana_m: 493 | state.registers.a &= state.memory[m_address()] 494 | updateLogicZSPC(Int(state.registers.a)) 495 | case .ana_a: 496 | state.registers.a &= state.registers.a 497 | updateLogicZSPC(Int(state.registers.a)) 498 | case .xra_b: 499 | state.registers.a ^= state.registers.b 500 | updateLogicZSPC(Int(state.registers.a)) 501 | case .xra_c: 502 | state.registers.c &= state.registers.c 503 | updateLogicZSPC(Int(state.registers.c)) 504 | case .xra_d: 505 | state.registers.d &= state.registers.d 506 | updateLogicZSPC(Int(state.registers.d)) 507 | case .xra_e: 508 | state.registers.e &= state.registers.e 509 | updateLogicZSPC(Int(state.registers.e)) 510 | case .xra_h: 511 | state.registers.h &= state.registers.h 512 | updateLogicZSPC(Int(state.registers.h)) 513 | case .xra_l: 514 | state.registers.l &= state.registers.l 515 | updateLogicZSPC(Int(state.registers.l)) 516 | case .xra_m: 517 | state.registers.a &= state.memory[m_address()] 518 | updateLogicZSPC(Int(state.registers.a)) 519 | case .xra_a: 520 | state.registers.a ^= state.registers.a 521 | updateLogicZSPC(Int(state.registers.a)) 522 | case .ora_b: 523 | state.registers.a |= state.registers.b 524 | updateLogicZSPC(Int(state.registers.a)) 525 | case .ora_c: 526 | state.registers.a |= state.registers.c 527 | updateLogicZSPC(Int(state.registers.a)) 528 | case .ora_d: 529 | state.registers.a |= state.registers.d 530 | updateLogicZSPC(Int(state.registers.a)) 531 | case .ora_e: 532 | state.registers.a |= state.registers.e 533 | updateLogicZSPC(Int(state.registers.a)) 534 | case .ora_h: 535 | state.registers.a |= state.registers.h 536 | updateLogicZSPC(Int(state.registers.a)) 537 | case .ora_l: 538 | state.registers.a |= state.registers.l 539 | updateLogicZSPC(Int(state.registers.a)) 540 | case .ora_m: 541 | state.registers.a |= state.memory[m_address()] 542 | updateLogicZSPC(Int(state.registers.a)) 543 | case .ora_a: 544 | state.registers.a |= state.registers.a 545 | updateLogicZSPC(Int(state.registers.a)) 546 | case .cmp_b: 547 | compare(Int(state.registers.b)) 548 | case .cmp_c: 549 | compare(Int(state.registers.c)) 550 | case .cmp_d: 551 | compare(Int(state.registers.d)) 552 | case .cmp_e: 553 | compare(Int(state.registers.e)) 554 | case .cmp_h: 555 | compare(Int(state.registers.h)) 556 | case .cmp_l: 557 | compare(Int(state.registers.l)) 558 | case .cmp_m: 559 | compare(Int(state.memory[m_address()])) 560 | case .cmp_a: 561 | compare(Int(state.registers.a)) 562 | case .rnz: 563 | if state.condition_bits.zero == 0 { 564 | try ret() 565 | return code.cycleCount 566 | } 567 | case .pop_b: 568 | let (high, low) = try pop() 569 | state.registers.b = high 570 | state.registers.c = low 571 | case .jnz: 572 | if state.condition_bits.zero == 0 { 573 | jump() 574 | return code.cycleCount 575 | } 576 | case .jmp: 577 | jump() 578 | return code.cycleCount 579 | case .cnz: 580 | if state.condition_bits.zero == 0 { 581 | try call() 582 | return code.cycleCount 583 | } 584 | case .push_b: 585 | try push(high: state.registers.b, low: state.registers.c) 586 | case .adi: 587 | let (result, overflow) = state.registers.a.addingReportingOverflow(state.memory[state.pc + 1]) 588 | state.registers.a = result 589 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 590 | case .rz: 591 | if state.condition_bits.zero == 1 { 592 | try ret() 593 | return code.cycleCount 594 | } 595 | case .ret: 596 | try ret() 597 | return code.cycleCount 598 | case .jz: 599 | if state.condition_bits.zero == 1 { 600 | jump() 601 | return code.cycleCount 602 | } 603 | case .cz: 604 | if state.condition_bits.zero == 1 { 605 | try call() 606 | return code.cycleCount 607 | } 608 | case .call: 609 | try call() 610 | return code.cycleCount 611 | case .pop_d: 612 | let (high, low) = try pop() 613 | state.registers.d = high 614 | state.registers.e = low 615 | case .jnc: 616 | if state.condition_bits.carry == 0 { 617 | jump() 618 | return code.cycleCount 619 | } 620 | case .out: 621 | guard let bus = bus else { 622 | throw Error.missingIOHandler 623 | } 624 | 625 | let port = state.memory[state.pc + 1] 626 | bus.machineOUT(port: port, accumulator: state.registers.a) 627 | case .cnc: 628 | if state.condition_bits.carry == 0 { 629 | try call() 630 | return code.cycleCount 631 | } 632 | case .push_d: 633 | try push(high: state.registers.d, low: state.registers.e) 634 | case .sui: 635 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(state.memory[state.pc + 1]) 636 | state.registers.a = result 637 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 638 | case .rc: 639 | if state.condition_bits.carry == 1 { 640 | try ret() 641 | return code.cycleCount 642 | } 643 | case .rp: 644 | throw Error.unhandledOperation(code) 645 | case .rpe: 646 | throw Error.unhandledOperation(code) 647 | case .pchl: 648 | state.pc = m_address() 649 | return code.cycleCount 650 | case .rnc: 651 | if state.condition_bits.carry == 0 { 652 | try ret() 653 | return code.cycleCount 654 | } 655 | case .rpo: 656 | throw Error.unhandledOperation(code) 657 | case .jc: 658 | if state.condition_bits.carry == 1 { 659 | jump() 660 | return code.cycleCount 661 | } 662 | case .in: 663 | guard let bus = bus else { 664 | throw Error.missingIOHandler 665 | } 666 | 667 | let device = state.memory[state.pc + 1] 668 | state.registers.a = bus.machineIN(port: device) 669 | case .sbi: 670 | let data = state.memory[state.pc + 1] + state.condition_bits.carry 671 | let (result, overflow) = state.registers.a.subtractingReportingOverflow(data) 672 | state.registers.a = result 673 | updateArithmeticZSPC(Int(state.registers.a), overflow: overflow) 674 | case .pop_h: 675 | let (high, low) = try pop() 676 | state.registers.h = high 677 | state.registers.l = low 678 | case .xthl: 679 | let l = state.registers.l 680 | let h = state.registers.h 681 | let sp_0 = state.memory[state.sp] 682 | let sp_1 = state.memory[state.sp + 1] 683 | 684 | state.registers.l = sp_0 685 | state.registers.h = sp_1 686 | 687 | try write(l, at: state.sp) 688 | try write(h, at: state.sp + 1) 689 | case .push_h: 690 | try push(high: state.registers.h, low: state.registers.l) 691 | case .ani: 692 | state.registers.a &= state.memory[state.pc + 1] 693 | updateLogicZSPC(Int(state.registers.a)) 694 | case .xchg: 695 | let h = state.registers.h 696 | let l = state.registers.l 697 | let d = state.registers.d 698 | let e = state.registers.e 699 | 700 | state.registers.h = d 701 | state.registers.l = e 702 | state.registers.d = h 703 | state.registers.e = l 704 | case .pop_psw: 705 | let (high, low) = try pop() 706 | state.registers.a = high 707 | state.updateConditionBits(low) 708 | case .di: 709 | state.inte = 0x00 710 | case .push_psw: 711 | try push(high: state.registers.a, low: state.condition_bits.byte) 712 | case .ori: 713 | state.registers.a |= state.memory[state.pc + 1] 714 | case .rm: 715 | if state.condition_bits.sign == 1 { 716 | try ret() 717 | return code.cycleCount 718 | } 719 | case .jm: 720 | if state.condition_bits.sign == 1 { 721 | jump() 722 | return code.cycleCount 723 | } 724 | case .ei: 725 | state.inte = 0x01 726 | case .cpi: 727 | let value = Int(state.memory[state.pc + 1]) 728 | compare(value) 729 | } 730 | 731 | state.pc += code.size 732 | 733 | return code.cycleCount 734 | } 735 | } 736 | --------------------------------------------------------------------------------