├── .gitignore ├── JLCPCB Rules Test.kicad_prl ├── README.md ├── JLCPCB Rules Test.kicad_sch ├── JLCPCB Rules Test.kicad_dru ├── JLCPCB Rules Test.kicad_pro └── JLCPCB Rules Test.kicad_pcb /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | # General 3 | *.bck 4 | *.bak 5 | .~* 6 | _autosave-* 7 | */#auto_saved_files# 8 | */*-backups/* 9 | *-backups/* 10 | 11 | # KiCad 12 | fp-info-cache 13 | replicate_layout.log 14 | *.kicad_pro 15 | !main.kicad_pro 16 | *.kicad_sch-bak 17 | *.kicad_pcb-bak 18 | -------------------------------------------------------------------------------- /JLCPCB Rules Test.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 40, 4 | "active_layer_preset": "", 5 | "auto_track_width": true, 6 | "hidden_netclasses": [], 7 | "hidden_nets": [], 8 | "high_contrast_mode": 0, 9 | "net_color_mode": 1, 10 | "opacity": { 11 | "images": 0.6, 12 | "pads": 1.0, 13 | "tracks": 1.0, 14 | "vias": 1.0, 15 | "zones": 0.6 16 | }, 17 | "selection_filter": { 18 | "dimensions": true, 19 | "footprints": true, 20 | "graphics": true, 21 | "keepouts": true, 22 | "lockedItems": false, 23 | "otherItems": true, 24 | "pads": true, 25 | "text": true, 26 | "tracks": true, 27 | "vias": true, 28 | "zones": true 29 | }, 30 | "visible_items": [ 31 | 0, 32 | 1, 33 | 2, 34 | 3, 35 | 4, 36 | 5, 37 | 8, 38 | 9, 39 | 10, 40 | 11, 41 | 12, 42 | 13, 43 | 15, 44 | 16, 45 | 17, 46 | 18, 47 | 19, 48 | 20, 49 | 21, 50 | 22, 51 | 23, 52 | 24, 53 | 25, 54 | 26, 55 | 27, 56 | 28, 57 | 29, 58 | 30, 59 | 32, 60 | 33, 61 | 34, 62 | 35, 63 | 36, 64 | 39, 65 | 40 66 | ], 67 | "visible_layers": "ffdffff_fffffff9", 68 | "zone_display_mode": 0 69 | }, 70 | "meta": { 71 | "filename": "JLCPCB Rules Test.kicad_prl", 72 | "version": 3 73 | }, 74 | "project": { 75 | "files": [] 76 | } 77 | } 78 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # KiCAD Custom DRC Rules for JLCPCB with Unit Tests 2 | 3 | - Supported only in KiCad 7 4 | - Has to make some assumptions since not all JLCPCB rules make sense or they contradict each other 5 | - "PTH hole Size" has a minimum of 0.2mm. Makes no sense since min via size is clearly 0.15mm, and "Pad Size" indicates min PTH hole size is 0.5mm. Ignoring this rule. 6 | - "Miniumum annular ring" of 0.13mm makes no sense. A standard 2-layer via of 0.3/0.5mm has an annular ring of 0.1mm which would be a violation if this was real. PTH have annular ring of 0.25mm specified in "Pad Size" section 7 | - 2oz copper "minimum annular ring" of 0.2mm is confusing because it isn't clear which other rules they are overriding with this. 8 | - In "Miniumum annular ring" section, PTH = 0.3mm makes no sense. Assuming they mean an actual hole size not total diameter including annular ring (unclear), vias can definitely go smaller than that. Again, "Pad Size" indicates min PTH hole size is 0.5mm. 9 | - Vias and PTH are the same thing with the same manufacturing process so having different rules for them is very confusing. 10 | 11 | 12 | To use the rules in your project: 13 | - Copy the contents of the "JLCPCB Rules Test.kicad_dru" file in to your Board Setup > Design Rules > Custom Rules section. 14 | - Select your desired option from the "Minimum trace width and spacing" by uncommenting it. Confirm all others are commented. Options: 2-oz copper, 2-layer, or 4-layer 15 | - Select your desired option from the "Via hole/diameter size" by uncommenting it. Confirm all others are commented. Options: 2-layer standard (0.3/0.5mm), 4-layer standard (0.3/0.45mm), 4-layer special (0.25/0.4mm), 4-layer special (0.2/0.35mm), or 4-layer special (0.15/0.3mm) 16 | - Select your desired option from the "Board Outlines" by uncommenting it. Confirm all others are commented. Option: Default Edge Routing, or Special V-Score Clearance 17 | 18 | !!Note: In KiCad you may still need to use Board Setup > Constraints > Minimum clearance to set your desired min. clearance, and then comment out all those rules in the custom rules section. KiCad will forcibly apply the custom rules min. clearance value even to netclasses with higher clearance values set. Thus making net class clearance rules useless especially for zones. 19 | See here for more info: https://gitlab.com/kicad/code/kicad/-/issues/14490 20 | 21 | To test/demo rules in included "JLCPCB Rule Test" PCB: 22 | 1) Open project in KiCad 23 | 2) Open Design Rules Checker 24 | 3) Make sure "Refill all zones before performing DRC" and "Report all errors for each track" are checked. Make sure "Test for parity between PCB and schematic" is unchecked. 25 | 4) Click "Run DRC" 26 | 27 | Credit for the original rules that I debugged, tested, and added to: 28 | - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e 29 | - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 30 | 31 | Misc notes: 32 | - From "Drill Hole Size" in the JLCPCB rules, the minimum size of 0.15mm isn't tested because it is covered by the min via size, min PTH size, and min NPTH size rules. 33 | - JLC specifies their via minimum size option with a preferred minimum and an actual minimum. Ex. 0.3mm/(0.4/0.45mm) means 0.3mm min hole in via, they'd prefer you use a min. via diameter 0.45mm but could go down to 0.4mm if really necessary. All of these rules use the "preferred" values. 34 | - It isn't possible to have 0.127mm pad to pad (without hole) clearance to only apply to to pads without holes in Kicad, I think -------------------------------------------------------------------------------- /JLCPCB Rules Test.kicad_sch: -------------------------------------------------------------------------------- 1 | (kicad_sch (version 20230121) (generator eeschema) 2 | 3 | (uuid 389be96e-94c7-4350-a942-aea90ba18481) 4 | 5 | (paper "A4") 6 | 7 | (lib_symbols 8 | (symbol "Connector_Generic:Conn_01x04" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) 9 | (property "Reference" "J" (at 0 5.08 0) 10 | (effects (font (size 1.27 1.27))) 11 | ) 12 | (property "Value" "Conn_01x04" (at 0 -7.62 0) 13 | (effects (font (size 1.27 1.27))) 14 | ) 15 | (property "Footprint" "" (at 0 0 0) 16 | (effects (font (size 1.27 1.27)) hide) 17 | ) 18 | (property "Datasheet" "~" (at 0 0 0) 19 | (effects (font (size 1.27 1.27)) hide) 20 | ) 21 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(property "Datasheet" "~" (at 69.85 88.9 0) 130 | (effects (font (size 1.27 1.27)) hide) 131 | ) 132 | (pin "1" (uuid fabfa977-373e-4f68-8ecf-9ef6458d6a2c)) 133 | (pin "2" (uuid ea03e54f-2397-4657-9668-93e26d22d0ec)) 134 | (pin "3" (uuid bf803875-7859-4252-98b8-8117150a9525)) 135 | (pin "4" (uuid 3430f804-64c5-4dc7-95f8-80ada4bd172b)) 136 | (instances 137 | (project "JLCPCB Rules Test" 138 | (path "/389be96e-94c7-4350-a942-aea90ba18481" 139 | (reference "J101") (unit 1) 140 | ) 141 | ) 142 | ) 143 | ) 144 | 145 | (sheet_instances 146 | (path "/" (page "1")) 147 | ) 148 | ) 149 | -------------------------------------------------------------------------------- /JLCPCB Rules Test.kicad_dru: -------------------------------------------------------------------------------- 1 | (version 1) 2 | #Kicad 7 3 | 4 | # ----------------------------------- Minimum trace width and spacing (PICK ONE) -------------------- 5 | 6 | # 2oz copper 7 | #(rule "Minimum Trace Width and Spacing" 8 | # (constraint track_width (min 0.2mm)) 9 | # (constraint clearance (min 0.2mm)) 10 | # (condition "A.Type == 'track'")) 11 | 12 | # 2-layer, 1oz copper 13 | #(rule "Minimum Trace Width and Spacing (outer layer)" 14 | # (constraint track_width (min 0.127mm)) 15 | # (constraint clearance (min 0.127mm)) 16 | # (condition "A.Type == 'track'")) 17 | 18 | # 4-layer , 1oz and 0.5oz copper 19 | (rule "Minimum Trace Width and Spacing" 20 | (constraint track_width (min 0.09mm)) 21 | (constraint clearance (min 0.09mm)) 22 | (condition "A.Type == 'track'")) 23 | 24 | # ------------------------------------------------------------------------------------------------------ 25 | 26 | # Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below. 27 | (rule "drill hole size (mechanical)" 28 | (constraint hole_size (min 0.15mm) (max 6.3mm))) 29 | 30 | # ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------ 31 | 32 | # 2-layer standard 33 | #(rule "Minimum Via Diameter and Hole Size" 34 | # (constraint hole_size (min 0.3mm)) 35 | # (constraint via_diameter (min 0.5mm)) 36 | # (constraint disallow buried_via) 37 | # (condition "A.Type == 'via'")) 38 | 39 | # 4-layer standard 40 | (rule "Minimum Via Diameter and Hole Size" 41 | (constraint hole_size (min 0.3mm)) 42 | (constraint via_diameter (min 0.45mm)) 43 | (constraint disallow buried_via) 44 | (condition "A.Type == 'via'")) 45 | 46 | # 4-layer special 47 | #(rule "Minimum Via Diameter and Hole Size" 48 | # (constraint hole_size (min 0.25mm)) 49 | # (constraint via_diameter (min 0.4mm)) 50 | # (constraint disallow buried_via) 51 | # (condition "A.Type == 'via'")) 52 | 53 | # 4-layer special 54 | #(rule "Minimum Via Diameter and Hole Size" 55 | # (constraint hole_size (min 0.2mm)) 56 | # (constraint via_diameter (min 0.35mm)) 57 | # (constraint disallow buried_via) 58 | # (condition "A.Type == 'via'")) 59 | 60 | # 4-layer special 61 | #(rule "Minimum Via Diameter and Hole Size" 62 | # (constraint hole_size (min 0.15mm)) 63 | # (constraint via_diameter (min 0.3mm)) 64 | # (constraint disallow buried_via) 65 | # (condition "A.Type == 'via'")) 66 | 67 | # ----------------------------------- Drill/hole size ------------------------------------ 68 | 69 | (rule "PTH Hole Size" 70 | (constraint hole_size (min 0.2mm) (max 6.35mm)) 71 | (condition "A.Type != 'Via' && A.isPlated()")) 72 | 73 | (rule "Minimum Non-plated Hole Size" 74 | (constraint hole_size (min 0.5mm)) 75 | (condition "A.Type == 'pad' && !A.isPlated()")) 76 | 77 | (rule "Pad Size" 78 | (constraint hole_size (min 0.5mm)) 79 | (constraint annular_width (min 0.25mm)) 80 | (condition "A.Type == 'Pad' && A.isPlated()")) 81 | 82 | (rule "Minimum Castellated Hole Size" 83 | (constraint hole_size (min 0.6mm)) 84 | (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) 85 | 86 | (rule "Min. Plated Slot Width" 87 | (constraint hole_size (min 0.5mm)) 88 | (condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()")) 89 | 90 | (rule "Min. Non-Plated Slot Width" 91 | (constraint hole_size (min 1.0mm)) 92 | (condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()")) 93 | 94 | # ----------------------------------- Minimum clearance ---------------------------------- 95 | (rule "hole to hole clearance (different nets)" 96 | (constraint hole_to_hole (min 0.5mm)) 97 | (condition "A.Net != B.Net")) 98 | 99 | (rule "via to track clearance" 100 | (constraint hole_clearance (min 0.254mm)) 101 | (condition "A.Type == 'via' && B.Type == 'track'")) 102 | 103 | (rule "via to via clearance (same nets)" 104 | (constraint hole_to_hole (min 0.254mm)) 105 | (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) 106 | 107 | (rule "pad to pad clearance (with hole, different nets)" 108 | (constraint hole_to_hole (min 0.5mm)) 109 | (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) 110 | 111 | (rule "pad to pad clearance (without hole, different nets)" 112 | (constraint clearance (min 0.127mm)) 113 | (condition "A.Type == 'Pad' && B.Type == 'Pad'")) 114 | 115 | (rule "NPTH to Track clearance" 116 | (constraint hole_clearance (min 0.254mm)) 117 | (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) 118 | 119 | (rule "NPTH with copper around" 120 | (constraint hole_clearance (min 0.20mm)) 121 | (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'")) 122 | 123 | (rule "PTH to Track clearance" 124 | (constraint hole_clearance (min 0.33mm)) 125 | (condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) 126 | 127 | (rule "Pad to Track clearance" 128 | (constraint clearance (min 0.2mm)) 129 | (condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) 130 | 131 | # ----------------------------------- Board Outlines (PICK ONE) ------------------------------------- 132 | #Default Routed Edge Clearance 133 | (rule "Trace to Outline" 134 | (constraint edge_clearance (min 0.3mm)) 135 | (condition "A.Type == 'track'")) 136 | 137 | #Special Clearance for V-Score Edges 138 | #(rule "Trace to V-Cut" 139 | # (constraint edge_clearance (min 0.4mm)) 140 | # (condition "A.Type == 'track'")) 141 | 142 | # ----------------------------------- silkscreen (Kicad 7 only) -------------------------- 143 | (rule "Minimum Text" 144 | (constraint text_thickness (min 0.15mm)) 145 | (constraint text_height (min 1mm)) 146 | (layer "?.Silkscreen")) 147 | 148 | #JLCPCB pad to silkscreen clearance rule is actually 0.15mm, but KiCad libraries violate that slightly, so JLC will have to deal with it. 149 | (rule "Pad to Silkscreen" 150 | (constraint silk_clearance (min 0.14mm)) 151 | (layer outer) 152 | (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) 153 | -------------------------------------------------------------------------------- /JLCPCB Rules Test.kicad_pro: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "3dviewports": [], 4 | "design_settings": { 5 | "defaults": { 6 | "board_outline_line_width": 0.09999999999999999, 7 | "copper_line_width": 0.19999999999999998, 8 | "copper_text_italic": false, 9 | "copper_text_size_h": 1.5, 10 | "copper_text_size_v": 1.5, 11 | "copper_text_thickness": 0.3, 12 | "copper_text_upright": false, 13 | "courtyard_line_width": 0.049999999999999996, 14 | "dimension_precision": 4, 15 | "dimension_units": 3, 16 | "dimensions": { 17 | "arrow_length": 1270000, 18 | "extension_offset": 500000, 19 | "keep_text_aligned": true, 20 | "suppress_zeroes": false, 21 | "text_position": 0, 22 | "units_format": 1 23 | }, 24 | "fab_line_width": 0.09999999999999999, 25 | "fab_text_italic": false, 26 | "fab_text_size_h": 1.0, 27 | "fab_text_size_v": 1.0, 28 | "fab_text_thickness": 0.15, 29 | "fab_text_upright": false, 30 | "other_line_width": 0.15, 31 | "other_text_italic": false, 32 | "other_text_size_h": 1.0, 33 | "other_text_size_v": 1.0, 34 | "other_text_thickness": 0.15, 35 | "other_text_upright": false, 36 | "pads": { 37 | "drill": 0.5, 38 | "height": 1.0, 39 | "width": 1.0 40 | }, 41 | "silk_line_width": 0.15, 42 | "silk_text_italic": false, 43 | "silk_text_size_h": 1.0, 44 | "silk_text_size_v": 1.0, 45 | "silk_text_thickness": 0.15, 46 | "silk_text_upright": false, 47 | "zones": { 48 | "min_clearance": 0.5 49 | } 50 | }, 51 | "diff_pair_dimensions": [ 52 | { 53 | "gap": 0.0, 54 | "via_gap": 0.0, 55 | "width": 0.0 56 | } 57 | ], 58 | "drc_exclusions": [], 59 | "meta": { 60 | "version": 2 61 | }, 62 | "rule_severities": { 63 | "annular_width": "error", 64 | "clearance": "error", 65 | "connection_width": "warning", 66 | "copper_edge_clearance": "error", 67 | "copper_sliver": "warning", 68 | "courtyards_overlap": "error", 69 | "diff_pair_gap_out_of_range": "error", 70 | "diff_pair_uncoupled_length_too_long": "error", 71 | "drill_out_of_range": "error", 72 | "duplicate_footprints": "warning", 73 | "extra_footprint": "warning", 74 | "footprint": "error", 75 | "footprint_type_mismatch": "ignore", 76 | "hole_clearance": "error", 77 | "hole_near_hole": "error", 78 | "invalid_outline": "error", 79 | "isolated_copper": "warning", 80 | "item_on_disabled_layer": "error", 81 | "items_not_allowed": "error", 82 | "length_out_of_range": "error", 83 | "lib_footprint_issues": "warning", 84 | "lib_footprint_mismatch": "ignore", 85 | "malformed_courtyard": "error", 86 | "microvia_drill_out_of_range": "error", 87 | "missing_courtyard": "ignore", 88 | "missing_footprint": "warning", 89 | "net_conflict": "warning", 90 | "npth_inside_courtyard": "ignore", 91 | "padstack": "warning", 92 | "pth_inside_courtyard": "ignore", 93 | "shorting_items": "error", 94 | "silk_edge_clearance": "warning", 95 | "silk_over_copper": "warning", 96 | "silk_overlap": "warning", 97 | "skew_out_of_range": "error", 98 | "solder_mask_bridge": "error", 99 | "starved_thermal": "error", 100 | "text_height": "warning", 101 | "text_thickness": "warning", 102 | "through_hole_pad_without_hole": "error", 103 | "too_many_vias": "error", 104 | "track_dangling": "warning", 105 | "track_width": "error", 106 | "tracks_crossing": "error", 107 | "unconnected_items": "error", 108 | "unresolved_variable": "error", 109 | "via_dangling": "ignore", 110 | "zones_intersect": "error" 111 | }, 112 | "rules": { 113 | "max_error": 0.005, 114 | "min_clearance": 0.0, 115 | "min_connection": 0.0, 116 | "min_copper_edge_clearance": 0.0, 117 | "min_hole_clearance": 0.0, 118 | "min_hole_to_hole": 0.0, 119 | "min_microvia_diameter": 0.01, 120 | "min_microvia_drill": 0.01, 121 | "min_resolved_spokes": 2, 122 | "min_silk_clearance": 0.0, 123 | "min_text_height": 0.0, 124 | "min_text_thickness": 0.0, 125 | "min_through_hole_diameter": 0.06, 126 | "min_track_width": 0.0, 127 | "min_via_annular_width": 0.01, 128 | "min_via_diameter": 0.01, 129 | "solder_mask_clearance": 0.0, 130 | "solder_mask_min_width": 0.0, 131 | "solder_mask_to_copper_clearance": 0.0, 132 | "use_height_for_length_calcs": true 133 | }, 134 | "teardrop_options": [ 135 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"page_layout_descr_file": "", 474 | "plot_directory": "", 475 | "spice_current_sheet_as_root": false, 476 | "spice_external_command": "spice \"%I\"", 477 | "spice_model_current_sheet_as_root": true, 478 | "spice_save_all_currents": false, 479 | "spice_save_all_voltages": false, 480 | "subpart_first_id": 65, 481 | "subpart_id_separator": 0 482 | }, 483 | "sheets": [ 484 | [ 485 | "389be96e-94c7-4350-a942-aea90ba18481", 486 | "" 487 | ] 488 | ], 489 | "text_variables": {} 490 | } 491 | -------------------------------------------------------------------------------- /JLCPCB Rules Test.kicad_pcb: -------------------------------------------------------------------------------- 1 | (kicad_pcb (version 20221018) (generator pcbnew) 2 | 3 | (general 4 | (thickness 1.6) 5 | ) 6 | 7 | (paper "A4") 8 | (layers 9 | (0 "F.Cu" signal) 10 | (1 "In1.Cu" signal) 11 | (2 "In2.Cu" signal) 12 | (31 "B.Cu" signal) 13 | (32 "B.Adhes" user "B.Adhesive") 14 | (33 "F.Adhes" user "F.Adhesive") 15 | (34 "B.Paste" user) 16 | (35 "F.Paste" user) 17 | (36 "B.SilkS" user "B.Silkscreen") 18 | (37 "F.SilkS" user "F.Silkscreen") 19 | (38 "B.Mask" user) 20 | (39 "F.Mask" user) 21 | (40 "Dwgs.User" user "User.Drawings") 22 | (41 "Cmts.User" user "User.Comments") 23 | (42 "Eco1.User" user "User.Eco1") 24 | (43 "Eco2.User" user "User.Eco2") 25 | (44 "Edge.Cuts" user) 26 | (45 "Margin" user) 27 | (46 "B.CrtYd" user "B.Courtyard") 28 | (47 "F.CrtYd" user "F.Courtyard") 29 | (48 "B.Fab" user) 30 | (49 "F.Fab" user) 31 | (50 "User.1" user) 32 | (51 "User.2" user) 33 | (52 "User.3" user) 34 | (53 "User.4" user) 35 | (54 "User.5" user) 36 | (55 "User.6" user) 37 | (56 "User.7" user) 38 | (57 "User.8" user) 39 | (58 "User.9" user) 40 | ) 41 | 42 | (setup 43 | (stackup 44 | (layer "F.SilkS" (type "Top Silk Screen")) 45 | (layer "F.Paste" (type "Top Solder Paste")) 46 | (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) 47 | (layer "F.Cu" (type "copper") (thickness 0.035)) 48 | (layer "dielectric 1" (type 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33.78) (layer "F.SilkS") (tstamp 22dfaced-11c9-4349-8070-ee102d85c91a) 1125 | (effects (font (size 1 1) (thickness 0.127)) (justify left bottom)) 1126 | ) 1127 | (gr_text "X" (at 166.46 54.37) (layer "F.SilkS") (tstamp 2df6728e-f7cd-42d0-b29e-24fddc1880e1) 1128 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1129 | ) 1130 | (gr_text "X" (at 152.85 33.83) (layer "F.SilkS") (tstamp 3e20dab4-b1ea-4f40-97f3-3c22168d08ef) 1131 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1132 | ) 1133 | (gr_text "X" (at 155.32 40.69) (layer "F.SilkS") (tstamp 7a62bbef-d0ad-46e8-8736-df7ac3b0d48f) 1134 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1135 | ) 1136 | (gr_text "X" (at 155.31 42.32) (layer "F.SilkS") (tstamp a930e047-3a33-49f1-a1e2-adbd287fbaed) 1137 | (effects (font (size 0.9 1) (thickness 0.15)) (justify left bottom)) 1138 | ) 1139 | (gr_text "Y" (at 166.49 52.12) (layer "F.SilkS") (tstamp d5b0b5d8-00a9-4ae4-afb0-345687ee659b) 1140 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1141 | ) 1142 | (gr_text "0.31mm FAIL\n0.36mm PASS\n(ignore annular error)" (at 132.08529 124) (layer "Dwgs.User") (tstamp 018515c1-6212-4940-ba5b-7260e6f51009) 1143 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1144 | ) 1145 | (gr_text "Pad Size" (at 42.015 111.02) (layer "Dwgs.User" knockout) (tstamp 040d5cf6-255c-4d7a-a766-e7def7e713a2) 1146 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1147 | ) 1148 | (gr_text "0.50/0.99mm PTH\nFAIL" (at 59.75 117.55) (layer "Dwgs.User") (tstamp 05c2b4e5-a793-4675-93bf-070f18c275e0) 1149 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1150 | ) 1151 | (gr_text "Minimum text height" (at 153.4 38.25) (layer "Dwgs.User" knockout) (tstamp 07ce9da1-2bd5-46e6-a148-ade92ae0ea2d) 1152 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1153 | ) 1154 | (gr_text "0.153mm PASS\n0.136mm FAIL" (at 153.49 53.83) (layer "Dwgs.User") (tstamp 0b82a8c9-4c4c-44d5-910e-baff5a31bf9b) 1155 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1156 | ) 1157 | (gr_text "0.50/1.0mm PTH\nPASS" (at 31.24 117.55) (layer "Dwgs.User") (tstamp 0ffdb2c9-1107-4d09-8da1-be53c8c73b85) 1158 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1159 | ) 1160 | (gr_text "0.49/1.0mm PTH\nFAIL" (at 45.24 117.55) (layer "Dwgs.User") (tstamp 16a32986-bf0e-46a2-9635-302262d95b72) 1161 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1162 | ) 1163 | (gr_text "0.5x1.0mm Plated Slot\nPASS + PASS" (at 74.75 45) (layer "Dwgs.User") (tstamp 1bd1329a-2767-4dc3-bfba-5bb890333a37) 1164 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1165 | ) 1166 | (gr_text "1.0x2.0mm Non-plated Slot\nPASS + PASS" (at 72.75 58.5) (layer "Dwgs.User") (tstamp 2a1094a0-8455-4d55-bd8b-f51b4cf00843) 1167 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1168 | ) 1169 | (gr_text "0.3mm/0.45mm Via\nPASS (4-layer standard)" (at 29.48 71.42) (layer "Dwgs.User") (tstamp 2fdd94aa-7ec8-4901-a949-95cc88eaf561) 1170 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1171 | ) 1172 | (gr_text "6.36mm PTH\nFAIL" (at 48.89 94.77) (layer "Dwgs.User") (tstamp 3113ae94-b88a-4ad1-925f-22b48b0edfa4) 1173 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1174 | ) 1175 | (gr_text "2-layer" (at 137.49 109.065) (layer "Dwgs.User") (tstamp 33dc0902-7f82-4b40-b908-36d64fb552e7) 1176 | (effects (font (size 0.8 0.8) (thickness 0.1)) (justify left bottom)) 1177 | ) 1178 | (gr_text "NPTH with copper around\n0.1mm clearance\nFAIL" (at 94.5 29) (layer "Dwgs.User") (tstamp 35c05c99-e3b0-41fc-8854-1e0cacd3f3a3) 1179 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1180 | ) 1181 | (gr_text "0.99x2.0mm Non-plated Slot\nFAIL + FAIL" (at 96.25 58.5) (layer "Dwgs.User") (tstamp 368d3f00-0dc1-4021-ba18-e93fab2a8cbb) 1182 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1183 | ) 1184 | (gr_text "0.49x1.0mm Plated Slot\nFAIL + FAIL" (at 94 45) (layer "Dwgs.User") (tstamp 4264126c-7b8f-434b-b935-6497e8a0cdb3) 1185 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1186 | ) 1187 | (gr_text "0.245mm FAIL\n0.27mm PASS" (at 124.79529 130.74471) (layer "Dwgs.User") (tstamp 446c603a-9592-4571-9194-d399075de8be) 1188 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1189 | ) 1190 | (gr_text "1.0mm PASS\n0.9mm FAIL" (at 158.61 42.23) (layer "Dwgs.User") (tstamp 486f865a-dcec-40ac-b721-386b050ba610) 1191 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1192 | ) 1193 | (gr_text "Via to Track" (at 125 127) (layer "Dwgs.User" knockout) (tstamp 48da104a-211a-434a-b10e-7804cf955ea1) 1194 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1195 | ) 1196 | (gr_text "0.08mm\nFAIL" (at 150.3 107.495) (layer "Dwgs.User") (tstamp 49765299-1db5-4c7d-9a7e-a7bd2db63a7d) 1197 | (effects (font (size 0.5 0.5) (thickness 0.05)) (justify left bottom)) 1198 | ) 1199 | (gr_text "Drill Hole Size (max)" (at 38.875 22.5) (layer "Dwgs.User" knockout) (tstamp 4e13c059-d025-42c2-b3d6-784748ba8008) 1200 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1201 | ) 1202 | (gr_text "Blind/Buried Vias" (at 40.625 49) (layer "Dwgs.User" knockout) (tstamp 52f00202-9bad-4222-aaef-d2b5634c31f1) 1203 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1204 | ) 1205 | (gr_text "Trace to Outline\n(Milled Slot Example)\n0.29mm FAIL\n0.3mm PASS" (at 145.38 131.17) (layer "Dwgs.User") (tstamp 592dc5ca-4359-45dc-856e-f83e3e243428) 1206 | (effects (font (size 0.7 0.7) (thickness 0.1)) (justify left bottom)) 1207 | ) 1208 | (gr_text "0.25mm FAIL\n0.27mm PASS" (at 133.26529 100.39471) (layer "Dwgs.User") (tstamp 595f61f4-71c0-4a53-abb4-a6eadd8a62eb) 1209 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1210 | ) 1211 | (gr_text "(Min clearance from NPTH to copper ring surrounding)" (at 85.75 23.75) (layer "Dwgs.User") (tstamp 5cdca4df-7957-4711-95bf-db0f0fbe6607) 1212 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1213 | ) 1214 | (gr_text "Add test for min. annular ring around plated slot" (at 190.5 71) (layer "Dwgs.User") (tstamp 61f87fc7-6871-4955-9fc6-d843faaea8dc) 1215 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1216 | ) 1217 | (gr_text "0.12mm\nFAIL" (at 140.29 107.53) (layer "Dwgs.User") (tstamp 67faf9a4-ee04-494d-93d9-c6559617057b) 1218 | (effects (font (size 0.5 0.5) (thickness 0.05)) (justify left bottom)) 1219 | ) 1220 | (gr_text "0.25mm/0.4mm Via\nPASS (4-layer special)" (at 50.8 71.515) (layer "Dwgs.User") (tstamp 6fe761f8-f6f6-45c3-9d07-9cb876063ba0) 1221 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1222 | ) 1223 | (gr_text "Pad To Silkscreen" (at 153.82 47.28) (layer "Dwgs.User" knockout) (tstamp 71a45c38-10eb-4d30-bd95-1d9e43ff9955) 1224 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1225 | ) 1226 | (gr_text "(PTH, not vias)" (at 40.015 113.27) (layer "Dwgs.User") (tstamp 77f0a574-34b2-4c3d-a606-954e7216fa3d) 1227 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1228 | ) 1229 | (gr_text "0.50mm\nNPTH\nPASS" (at 33.64 133.02) (layer "Dwgs.User") (tstamp 7cdc8495-1192-4809-a222-3401c376afd7) 1230 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1231 | ) 1232 | (gr_text "0.09mm\nPASS" (at 146.22 107.52) (layer "Dwgs.User") (tstamp 80391235-159e-4a8d-8ae0-9ff8309f6205) 1233 | (effects (font (size 0.5 0.5) (thickness 0.05)) (justify left bottom)) 1234 | ) 1235 | (gr_text "PTH to Track" (at 132.25 118.5) (layer "Dwgs.User" knockout) (tstamp 804d87c4-9b71-4aa5-8f3b-ea97fb33deb1) 1236 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1237 | ) 1238 | (gr_text "0.2mm\nPASS" (at 125.17 107.53) (layer "Dwgs.User") (tstamp 8436bc0e-6b69-4df3-9eaf-594f98238fb6) 1239 | (effects (font (size 0.5 0.5) (thickness 0.05)) (justify left bottom)) 1240 | ) 1241 | (gr_text "0.15mm/0.3mm Via\nPASS (4-layer special)" (at 50.8 78.5) (layer "Dwgs.User") (tstamp 8abafa28-cefb-4c63-9226-ee370ea584a3) 1242 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1243 | ) 1244 | (gr_text "0.19mm\nFAIL" (at 129 107.53) (layer "Dwgs.User") (tstamp 8c925f1e-8e65-4def-bd2c-fbbcf2e0fbe1) 1245 | (effects (font (size 0.5 0.5) (thickness 0.05)) (justify left bottom)) 1246 | ) 1247 | (gr_text "Trace to Outline" (at 152.94 134.955) (layer "Dwgs.User" knockout) (tstamp 8eba0f58-bf43-4b25-a024-f5210fcd9bb1) 1248 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1249 | ) 1250 | (gr_text "0.15mm PASS\n0.127mm FAIL" (at 155.7 30.94) (layer "Dwgs.User") (tstamp 934c08b6-14dc-4521-b032-13bc1091b929) 1251 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1252 | ) 1253 | (gr_text "0.3mm/0.5mm Via\nPASS (2-layer)" (at 29.5 64.64) (layer "Dwgs.User") (tstamp 96c87e01-d5f2-4fde-8754-cfd1b86c9797) 1254 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1255 | ) 1256 | (gr_text "Not tested:\nAny tolerances\nMin. Castellated Holes\nDrill Hole Size Min 0.2mm\n (Redundant. NPTH min is 0.5mm. Via min is 0.2mm already)\nRectangle Hole/Slot" (at 190.5 67.75) (layer "Dwgs.User") (tstamp 9a174604-dce8-4727-9de1-1e6b6cf3d848) 1257 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1258 | ) 1259 | (gr_text "Minimum trace spacing" (at 154.14 107.21) (layer "Dwgs.User" knockout) (tstamp 9a97b545-cd92-43bf-a889-001c69c4d304) 1260 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1261 | ) 1262 | (gr_text "Normal Via\nPASS" (at 29.625 53) (layer "Dwgs.User") (tstamp 9ea10fdc-d175-44e6-b564-faed3dcf1c4e) 1263 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1264 | ) 1265 | (gr_text "NPTH with copper around\n0.1mm clearance\nFAIL + Zone auto clearance carveout" (at 115.9 29.2) (layer "Dwgs.User") (tstamp 9faaeb10-e036-4fe7-8f25-2d7ab12419d8) 1266 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1267 | ) 1268 | (gr_text "Min. Plated Slots" (at 86.5 40.75) (layer "Dwgs.User" knockout) (tstamp a4edb985-9a0f-41b3-b6f3-f4d7ab2de92b) 1269 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1270 | ) 1271 | (gr_text "0.2mm PASS (2 oz copper)\n0.19mm FAIL\n\n0.127mm PASS (2-layer)\n0.12mm FAIL\n\n0.09mm PASS (4-layer)\n0.089mm FAIL" (at 164.5 127.5) (layer "Dwgs.User") (tstamp a6df6e7a-12ba-42a0-a6b6-7400b48374be) 1272 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1273 | ) 1274 | (gr_text "Minimum Line Width" (at 153.36 27.16) (layer "Dwgs.User" knockout) (tstamp a8396002-abe8-4088-9561-1806b0e9033c) 1275 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1276 | ) 1277 | (gr_text "(rule is set to 0.14mm min. for KiCad library compatiblity)" (at 138.17 49.32) (layer "Dwgs.User") (tstamp a9250393-e4d6-4eca-b375-04cbc9c9f98c) 1278 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1279 | ) 1280 | (gr_text "Buried Via\nFAIL" (at 57.625 53) (layer "Dwgs.User") (tstamp ab52b93e-e342-4fe8-9c58-24682efbf77f) 1281 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1282 | ) 1283 | (gr_text "Blind Via\nFAIL" (at 45.625 53) (layer "Dwgs.User") (tstamp ae261e6f-fd5d-4321-8154-e085c4e3b804) 1284 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1285 | ) 1286 | (gr_text "0.25mm FAIL\n0.26mm PASS" (at 100.75 119.5) (layer "Dwgs.User") (tstamp b058e2ee-b330-46ab-ab98-366cce6514fb) 1287 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1288 | ) 1289 | (gr_text "0.15mm/0.29mm Via\nFAIL" (at 50.8 85.485) (layer "Dwgs.User") (tstamp b2144dad-e5c9-4bd2-9b7f-9f8796e4730a) 1290 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1291 | ) 1292 | (gr_text "0.15mm" (at 105.8 125.32) (layer "Dwgs.User") (tstamp b41cd282-4b1c-43d4-908e-03cd0bcd1166) 1293 | (effects (font (size 0.3 0.3) (thickness 0.05) bold) (justify left bottom)) 1294 | ) 1295 | (gr_text "0.16mm FAIL\n0.21mm PASS" (at 147.38529 98.14471) (layer "Dwgs.User") (tstamp b9898c9e-eb1c-482a-83b0-100ca9864a04) 1296 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1297 | ) 1298 | (gr_text "Pad to Pad clearance(Pad without hole, Different nets)" (at 76.75 122.5) (layer "Dwgs.User" knockout) (tstamp ba331df9-a881-486c-b996-7441bdd7e4b2) 1299 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1300 | ) 1301 | (gr_text "6.31mm\nFAIL" (at 50.625 26.75) (layer "Dwgs.User") (tstamp be22a6d5-b98b-4061-bc53-0c84a349c622) 1302 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1303 | ) 1304 | (gr_text "0.49mm FAIL\n0.53mm PASS" (at 105.45 101.62) (layer "Dwgs.User") (tstamp bf794086-1b09-40b0-bad0-68dfd7133755) 1305 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1306 | ) 1307 | (gr_text "Pad to Pad clearance(Pad with hole, Different nets)" (at 76.91 131.29) (layer "Dwgs.User" knockout) (tstamp c0aa9027-fc6a-4c98-b7ec-036cf901b6fb) 1308 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1309 | ) 1310 | (gr_text "0.10mm FAIL\n0.15mm PASS\n" (at 92.85 126.33) (layer "Dwgs.User") (tstamp c106c4b0-41df-422f-b79a-152fa1e50803) 1311 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1312 | ) 1313 | (gr_text "Hole to hole clearance(Different nets)" (at 95.5 98) (layer "Dwgs.User" knockout) (tstamp c31c7ba8-4d2d-4856-8231-52eb1ddd2ecb) 1314 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1315 | ) 1316 | (gr_text "0.14mm/0.3mm Via\nFAIL" (at 29.845 85.485) (layer "Dwgs.User") (tstamp c4a3370b-880f-425c-ab25-d7b46a09fdcd) 1317 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1318 | ) 1319 | (gr_text "Min. Via hole size AND Min. Via diameter" (at 34.29 57.25) (layer "Dwgs.User" knockout) (tstamp c5c90ad2-45f1-46c7-bff7-97340b0fb91b) 1320 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1321 | ) 1322 | (gr_text "6.30mm\nPASS" (at 35.625 26.75) (layer "Dwgs.User") (tstamp c8008ad7-6d80-4cc8-9d3f-866bbc554188) 1323 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1324 | ) 1325 | (gr_text "{dblquote}NPTH{dblquote}" (at 103.75 21.25) (layer "Dwgs.User" knockout) (tstamp c896a149-c81b-4b55-a4a5-0712557caa54) 1326 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1327 | ) 1328 | (gr_text "0.10mm" (at 105.77 124.4) (layer "Dwgs.User") (tstamp d68b3e7a-e27b-4c24-9579-5cc29c1f9c24) 1329 | (effects (font (size 0.3 0.3) (thickness 0.05) bold) (justify left bottom)) 1330 | ) 1331 | (gr_text "NPTH to Track" (at 133.25 96.75) (layer "Dwgs.User" knockout) (tstamp d700e5ef-79d8-4379-adf9-bf4b8b91f013) 1332 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1333 | ) 1334 | (gr_text "Min. Non-plated holes" (at 32.89 126.02) (layer "Dwgs.User" knockout) (tstamp d8074e05-364d-493a-a26f-17dd01b97042) 1335 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1336 | ) 1337 | (gr_text "0.49mm\nNPTH\nFAIL" (at 41.64 133.02) (layer "Dwgs.User") (tstamp da5fb30c-186f-468e-bf48-3e7b1ae40d15) 1338 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1339 | ) 1340 | (gr_text "(Assuming by {dblquote}Pad{dblquote} they mean PTH hole)\n< 0.5mm FAIL\n(Actually impossible with 0.25mm annular ring requirement for PTH\n+ 0.127mm pad to pad clearance)\n(Ignore annular width violation)" (at 76.76 139.9) (layer "Dwgs.User") (tstamp dd7cc4f9-41f4-42e2-bccb-40343b849b73) 1341 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1342 | ) 1343 | (gr_text "2-oz Copper" (at 124.52 109.27) (layer "Dwgs.User") (tstamp e359ddaa-008d-4766-9fb7-a234e8cf1404) 1344 | (effects (font (size 0.8 0.8) (thickness 0.1)) (justify left bottom)) 1345 | ) 1346 | (gr_text "0.13mm\nPASS" (at 136.21 107.52) (layer "Dwgs.User") (tstamp e4fa12e8-ae15-4bd4-8c61-af978f3bdc75) 1347 | (effects (font (size 0.5 0.5) (thickness 0.05)) (justify left bottom)) 1348 | ) 1349 | (gr_text "Min. Non-Plated Slots" (at 83.25 54) (layer "Dwgs.User" knockout) (tstamp e7e24ef7-0f6f-4cc3-a14d-ca2833e4f788) 1350 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1351 | ) 1352 | (gr_text "0.2mm/0.35mm Via\nPASS (4-layer special)" (at 29.48 78.405) (layer "Dwgs.User") (tstamp eb0d9d3e-d7c3-4c76-b404-83ac3b5ec299) 1353 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1354 | ) 1355 | (gr_text "NPTH with copper around\n0.21mm clearance\nPASS" (at 73.95 28.75) (layer "Dwgs.User") (tstamp efa22f6a-cb63-4f90-8c08-d353092a90b0) 1356 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1357 | ) 1358 | (gr_text "PTH hole Size" (at 39.29 90.24) (layer "Dwgs.User" knockout) (tstamp f03433cb-fe3a-40a7-8ebf-2803ba0df3cc) 1359 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1360 | ) 1361 | (gr_text "Pad to Track" (at 147.5 94.5) (layer "Dwgs.User" knockout) (tstamp f12bdc91-e430-4a18-86c4-d71e9f96bd58) 1362 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1363 | ) 1364 | (gr_text "0.20mm FAIL\n0.30mm PASS (Routed)\n0.40mm PASS (V-score)" (at 153.17 140.335) (layer "Dwgs.User") (tstamp f3a59cea-f6d8-4173-a343-fdd2decaee97) 1365 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1366 | ) 1367 | (gr_text "Minimum trace width" (at 164.5 114.25) (layer "Dwgs.User" knockout) (tstamp f462bf60-45dd-4ce6-ac45-ed525a3b8fcb) 1368 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1369 | ) 1370 | (gr_text "4-layer" (at 147.5 109.12) (layer "Dwgs.User") (tstamp f48718cd-8c0e-4ce6-a7d4-513e1d7021c0) 1371 | (effects (font (size 0.8 0.8) (thickness 0.1)) (justify left bottom)) 1372 | ) 1373 | (gr_text "6.35mm PTH\nPASS" (at 31.89 94.77) (layer "Dwgs.User") (tstamp fe57a93e-cd54-4e50-bd11-bea985a9b443) 1374 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1375 | ) 1376 | (gr_text "Via to Via clearance(Same nets)" (at 95.5 115.75) (layer "Dwgs.User" knockout) (tstamp fed357ef-cf46-4e39-bfc8-9effa45c7418) 1377 | (effects (font (size 1 1) (thickness 0.15)) (justify left bottom)) 1378 | ) 1379 | (gr_text_box "Special = extra cost\nAny via further down the list than your selected rule size should fail" 1380 | (start 33.5 57.5) (end 66.75 69.5) (layer "Dwgs.User") (tstamp 97fb053a-08d5-48c5-8e4b-75d4ad09c7fa) 1381 | (effects (font (size 0.6 0.6) (thickness 0.09)) (justify left top)) 1382 | ) 1383 | 1384 | (segment (start 111.10529 103.321367) (end 111.107549 103.323626) (width 0.25) (layer "F.Cu") (net 1) (tstamp 10f17c74-439d-41c9-8586-9dc5820cdb3c)) 1385 | (segment (start 111.10529 102.89471) (end 111.10529 103.321367) (width 0.25) (layer "F.Cu") (net 1) (tstamp 41239bf8-5ec4-4f88-b83f-317904e0dcc2)) 1386 | (segment (start 111.25 102.75) (end 182.5 102.75) (width 0.25) (layer "F.Cu") (net 1) (tstamp b087f728-8c4b-423b-92bb-878ba2f236aa)) 1387 | (segment (start 111.25 102.75) (end 100 102.75) (width 0.25) (layer "F.Cu") (net 1) (tstamp d43bda29-035d-4b79-902d-c64dcefcff9f)) 1388 | (segment (start 112.10529 102.89471) (end 112.10529 103.49) (width 0.25) (layer "F.Cu") (net 1) (tstamp ec5a069a-d2c8-45e0-b669-199a826432cb)) 1389 | (segment (start 111.25 102.75) (end 111.10529 102.89471) (width 0.25) (layer "F.Cu") (net 1) (tstamp f3e3bd71-b77c-415f-9dd6-8c8912adadda)) 1390 | (via (at 111.10529 103.5) (size 0.5) (drill 0.3) (layers "F.Cu" "B.Cu") (net 1) (tstamp 58efbc3a-ffdb-4d82-95ce-54ce5ec787e4)) 1391 | (via (at 112.10529 103.49) (size 0.5) (drill 0.3) (layers "F.Cu" "B.Cu") (net 1) (tstamp 9b18e824-d822-4133-8186-a026b7af1574)) 1392 | (segment (start 100 105.29) (end 111 105.29) (width 0.25) (layer "F.Cu") (net 2) (tstamp 60ddf80a-e5c3-4b30-af58-5dcf514544e0)) 1393 | (segment (start 112 105.29) (end 112 104.31) (width 0.25) (layer "F.Cu") (net 2) (tstamp 6d8f635e-06ec-4c62-98e1-8e43b83847a1)) 1394 | (segment (start 166 105.29) (end 182.5 105.29) (width 0.25) (layer "F.Cu") (net 2) (tstamp 71356042-d96f-4fb7-b90a-e572183c8b60)) 1395 | (segment (start 111 105.29) (end 166 105.29) (width 0.25) (layer "F.Cu") (net 2) (tstamp e1995ab7-e88c-4e7c-a239-ab8a81965437)) 1396 | (segment (start 111 105.29) (end 111 104.17) (width 0.25) (layer "F.Cu") (net 2) (tstamp f3a10696-1eda-4133-928b-dcbb2c9a1049)) 1397 | (via (at 112 104.31) (size 0.5) (drill 0.3) (layers "F.Cu" "B.Cu") (net 2) (tstamp 973db75f-3e97-4696-a1d4-6d4cb02465ef)) 1398 | (via (at 111 104.28) (size 0.5) (drill 0.3) (layers "F.Cu" "B.Cu") (net 2) (tstamp d58f0b14-f11d-46fc-bd38-53f8577ec90e)) 1399 | (segment (start 153.4 107.8) (end 153.43 107.83) (width 0.25) (layer "F.Cu") (net 3) (tstamp 10b025bc-92b1-466e-ac6a-5739380e94cb)) 1400 | (segment (start 128 105.8) (end 128 107.83) (width 0.25) (layer "F.Cu") (net 3) (tstamp 12981c65-524b-4367-91dd-5900dd171a22)) 1401 | (segment (start 139.31 107.81) (end 139.29 107.83) (width 0.25) (layer "F.Cu") (net 3) (tstamp 408f2656-a06a-4b72-a391-d5ecaa0557b0)) 1402 | (segment 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