├── .gitignore ├── .gitmodules ├── README.md ├── Slides ├── Hands on with FPGA's Module 1.pdf ├── Hands_on_with_FPGA's_Module_2.pdf ├── Hands_on_with_FPGA's_Module_2.pptx ├── Hands_on_with_FPGA's_Module_3.pdf ├── Hands_on_with_FPGA's_Module_3.pptx ├── Hands_on_with_FPGA's_Module_4.pdf ├── Hands_on_with_FPGA's_Module_4.pptx ├── Hands_on_with_FPGA's_Module_5.pdf ├── Hands_on_with_FPGA's_Module_5.pptx ├── Hands_on_with_FPGA's_Module_6.pdf ├── Hands_on_with_FPGA's_Module_6.pptx ├── Hands_on_with_FPGA's_Module_7.pdf ├── Hands_on_with_FPGA's_Module_7.pptx ├── Hands_on_with_FPGA's_Module_8.pdf ├── Hands_on_with_FPGA's_Module_8.pptx └── drawio_drawings.drawio ├── Week1.md ├── Week2.md ├── Week3.md ├── Week4.md ├── Week5.md ├── Week6.md ├── Week7.md ├── Week8.md ├── fusesoc └── fusesoc.conf ├── resource_list.md ├── verilog-mode ├── my_adder.sv └── my_block.sv └── wb_config ├── Makefile └── wb_config.cfg /.gitignore: -------------------------------------------------------------------------------- 1 | */__pycache__/* 2 | *build/* 3 | *~ 4 | fusesoc_libraries/* -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "wb_intercon"] 2 | path = wb_intercon 3 | url = https://github.com/olofk/wb_intercon.git 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Hands on FPGA Class 2 | 3 | Hardware design and more narrowly, digital electronics forms the basis for almost all devices that modern society takes for granted. We believe in learning by doing and have put together a progression of topics as well as a curated list of resources to help students to get a quick introduction to the field. This is not a substitute for a more formal and deeper course that may be found at a University. Focus is on learning by doing and getting an intuitive understanding of how things work. 4 | 5 | This course augments the excellent series on an [Introduction to FPGA's by Shawn Hymel](https://github.com/ShawnHymel/introduction-to-fpga) as well as many other introductory FPGA courses. As such, it is not really a course in itself according to the traditional definition, but rather a collection of pointers to relevant material so students can choose to learn from a variety of resources in whatever way works best for them. 6 | 7 | This course is a self-paced, hands-on class and we hope that by the time you complete all the modules, you will have gained an understanding of how digital electronics works at a level sufficient to put together simple projects on your own. The course has a broad audience of learners from a typical high school level upwards. 8 | 9 | ## Hardware 10 | 11 | Access to an FPGA board is not essential and we have identified a few online simulators that can provide as close an experience as possible to a real world FPGA. However, there is no substitute for playing with real hardware and experiencing the non-idealities of the real world where real learning happens. 12 | 13 | We will use the open-source [UPDuino](https://github.com/tinyvision-ai-inc/UPduino-v3.0) as the FPGA platform which you can purchase directly from [www.tinyVision.ai](https://tinyvision.ai/products/upduino-v3-1), [Lectronz](https://lectronz.com/products/upduino-v3-1-low-cost-lattice-ice40-fpga-board) (for EU orders) or [Tindie](https://www.tindie.com/products/tinyvision_ai/upduino-v31-low-cost-lattice-ice40-fpga-board/). 14 | 15 | If the UPDuino is out of stock or otherwise unavailable, there are alternative FPGA boards that will allow you to follow along with most of the material. 16 | The UPDuino has a lattice iCE40-UP5K FPGA, purchasing a board that does as well is the best way to ensure a similar experience. Other boards/FPGAs are supported by the open source toolchains to varying degrees. 17 | A good resource for selecting one of the more affordable options as well as a guide on what the differences are, is detailed in this [fantastic blog post by Joel Williams](https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards). That being said, due to the unique quirks of every board, unforseen problems/difficulties may occur. We are not able to offer support for 3rd party boards, in other words **Your mileage may vary**. 18 | 19 | ## Course Methodology 20 | The pace of this course can be varied significantly depending on your time availability and committment. Each module is intended to take a few hours overall to go through the reading material and also perform the experiments on hardware. Initial modules focus on providing the student with resources to get up and running on the hardware as well as environment setup which can be challenging. We will rely as much as possible on open-source tools to enable the audience to be as wide as possible. 21 | 22 | The material should ideally be augmented by weekly interactions with a teacher/expert in the field. We plan to use weekly online AMA (Ask-Me-Anything) sessions following the format below: 23 | 1. Introduction to the upcoming topic 24 | 2. Real world examples of what the topic would be useful for to help students understand why they wouild want to learn the topic 25 | 3. Intuitive understanding of the topic where applicable 26 | 4. Open floor to questions/feedback from the previous week. 27 | 28 | ## Weekly Modules 29 | 30 | ### [Week 1: What is an FPGA and Toolchain setup](Week1.md) 31 | 32 | ### [Week 2: Getting started with Verilog, logic design](Week2.md) 33 | 34 | ### [Week 3: Clocks, verilog experimentation](Week3.md) 35 | 36 | ### [Week 4: State machines](Week4.md) 37 | 38 | ### [Week 5: Memories: RAM, ROM](Week5.md) 39 | 40 | ### [Week 6: Interfacing with the real world: Digital systems architecture](Week6.md) 41 | 42 | ### [Week 7: Interfacing with the real world: Clock domain crossings, reusing code/IP](Week7.md) 43 | 44 | ### [Week 8: Interfacing with the real world: HDL Alternatives, and useful projects](Week8.md) 45 | 46 | ## [Resource list](/resource_list.md) 47 | A curated collection of various sites/books/videos/tutorials and more to help guide those wanting to learn about FPGAs but not quite sure where to begin. 48 | The list is an abbreviated subset of [the more detailed google sheet](https://bit.ly/Learn_FPGA). 49 | 50 | Anything not already listed that is relevant to FPGAs? [Please let us know](https://forms.gle/zcpHWAm1DT5WMZzA8) so it can be shared with fellow learners 51 | 52 | # License 53 | All code in this repository, unless otherwise noted, is licensed under the Zero-Clause BSD / Free Public License 1.0.0 (0BSD). 54 | 55 | Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted. 56 | 57 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 58 | -------------------------------------------------------------------------------- /Slides/Hands on with FPGA's Module 1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tinyvision-ai-inc/Hands-on-FPGA-class/ff8174d7e727eff25c214fee212a00a97c66ea77/Slides/Hands on with FPGA's Module 1.pdf -------------------------------------------------------------------------------- /Slides/Hands_on_with_FPGA's_Module_2.pdf: -------------------------------------------------------------------------------- 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7V1bc5s4FP41eVwPuiDEY5sm253Zne1MHtruS4bYsk1LjAeTxu6vX2EkG5Axsg1IxMlDBo4FhnO+c9WRfINun9d/JsFy/k88YdENdCbrG/TpBkLqIv4/I2xyAqaCMEvCSU5y9oSH8DfLiUBSX8IJWwlaTkrjOErDZZk4jhcLNk5LtCBJ4tfysGkcTUqEZTBjCuFhHEQq9Ws4SefytZw9/TMLZ3P5zcARnzwHcrAgrObBJH4tkNDdDbpN4jjNj57XtyzKeFfmy33Np7sHS9gi1bng69PH/+h9Ei1fH3783iwfk9/f4R9CGKt0I1+YTfj7i9M4SefxLF4E0d2e+jGJXxYTlt3V4Wf7MX/H8ZITASf+YGm6EcIMXtKYk+bpcyQ+Zesw/VY4/p7dagRdcfppLW69PdnIk0WabL4VT4qXZef767Zn+wsnHzIg8NNFvGA55T6MIvF5zoHstWsZK0ir+CUZsyPcJFQgNEhmLD0y0AM7AHDFYfEz40/ML0xYFKThr/KTBALCs9243aVf4pA/I3SEtmGpbULZAHFGxCvfJX8JcWERLtV70eZ75e+p3IsfFN5qT9oC8gRwYnvAqYlNUMbmpdCc8sPbOIqT7dujKR2z8ZjTV2kS/2SFT56oi922wezrghl2Ambk0RIAoQPOQ7LrNNyoBsZcNMGmMGyZDVgdeWC3+j346HMp4zE6rpH+hePLz8MP8jdsVWddkzrrnOZQjitfnVI3OhwTDoWgTnQQ+lUnoKc6jcqs3KhGmduCpfj2X0H0IniRrB/H0U8FrSlbp2VwlY2tgErRMgtSEIWzBT8dcykzTv/4iyVpyCPJD+KD53Ay2eL9dR6m7GEZbEX/ysNmRQem8SItmPd74N/6/g5a2Y3Z+ji4VChISQBSlgQVKvu6D2+xCFnnhchWhrGHwFOS1qmi8RXRBKvNYvw4CdLAUvF0IQYMzIoBAEUOtouhQy1xKaiIBxsWD1LEkw7Ignl3H8hdS6oDKLbLggF8SDbDUZx2hVNx9MYVh5iMSK0ucTSGn1g3BXShNk4uLXFUAkkX+FqBZGNWqNyo4+IG8Izg0vZKRTPUUF9QQ7jsZ1wCW4Kaqwe1SwsQ8oF1CxBEFEZ0CwqnjnfJ8YKIwifSQ8ECUJP+weqKRXv+QWpS90pbrVjomvXGioWuo2kLl8gfXtxyKu7qEjir6+Iy1mkEPXI7QThpClw6BiZUM9GrraUhpywK08kOVDPRayymYd83LAdXkcNODI+cyC+2UxgdKguRdsoWIWFoj4c9rzDQk3+dBIxOD/pXMqbsadquf8Wurn+FbfjXU5Ms4Ltlm9+QZCnjxXndeOiDi8ZjETh2mjRBT7FvV1uNxpVwzHgMoM51imr0kDxPqyKqtEUZ9zxIVR9FKjPOnuUFtvgAx0SPZPAkv8M5lZMQlI0Noo7CSXKAk7QzTqqzlgonyzg7hMQC9Otc5gH0ayHziPxVLhvjImzmYpqEwWJWq8znsXASJhyQYZzZile2Sjvh6q66WLHTCnLBAZ6Dzniumulh2ADklMvi5m2AmmwNwQZQy2wAeRM2oIardtoAGXQMYu6h5xrvTXsZJdLOKC+dk7gMDWAwaBhkYeFi6dYk+J4zIo7jAAI94mBAKsmGU7EeXS+a0LDjVsYVEFRm7hxoNq7AajF9AHFFLn974gqsEZ31FVdMo3D5WdypfQ7vujsMBxVmGouuxo3kZqF9N0LQyEcIQR8SjLhCVsqKUm36ciPa6WmHmWa1BcO4R1DXKgzBI1iWacok7A15hBoOW+IRXI0iaU1IqN1a04kBUBoCTRsA2fszLAPg1nDZGBfVDqKBG4A6DttiACxaSd9PSGiiJbD9Tj/ojQAPCWm2XBa7lQ0Z+o4IXYsW0rxFDDmdYAhhPAI+/wOUAN/zYXnyRlnT0DWIDjaObJsTgvF798jBybReWxOI0SmJ96a4i5viaopTV94UJ6optYs9KkuKTx7fR9Od3DLDftUcsIp1UNfjMW82PcRttucgAA9rSl8OWH7d8KaHUGXV/4E+y16zWKKRxdpXCyA1qYoxLmpMsg2rFlDHYUtqAcToDl19eJEWfQLpZq4HOmRECSEudSEl2PXKy5fkRm29+QSjmX0vM4ZtYqKjrdY4JoptJF7F3ZGeMXFCi3qHXl/ZN86419eYF7XQ61vWcC73Fn1DXr+Gw5Z4fU9jztXSKcDyqlHjBsAb5IoTr6a6bIyLGmnosAxAHYdtMQAW7fSuW9flMfKumJtf6XsNxd3t2ReWhJxrWdl/uPNB2ttv1/Se9NOz7r3PLHeKgo5+KMD1/RHmyQbEGGCHVGqSfecantoi/CHbLmOexIv4ZXUDSZTZ6aeEH82yo/u/7v+90Ome6VwbapSV2VUPIdXqwwNmX26U1r5+WrSq62Q/exqzKTjA7F5drEbK3DmvWdAFrxGyjdcaaXjBsI+jYLUKx3ocPnsbVn273/ybGjWTUQV+uwf4LWmXzllRr2zH3Ip90t35ElW62D3Z+teTZ6Eaaa+1MLFG+hSOZIRwKgAUj0jByHP7xYBGwv6OgQYMUEBbwwAFXu8Y0Cg3vGNA2QG1KrdzvQA2DwCNyfpzAWC9HHHVBsORc64oPeVe/cpRo13gauTokpHj+fu/lkQqG737Eqma/V/tXnJyckGKQtYFTHUDU7V8cLV7/brEMtn0v89fkr+WrdpT2Y3ZI+qciwR0PxJSZ7m7+10gy2XjlRcveciw9vhqZSDpWHsiNm1XQK2aN9kYvFMeoAhIWrx+BKSm7UlnyjMs0SDVrrUkGn66/0HyPMDb/6o7uvsf -------------------------------------------------------------------------------- /Week1.md: -------------------------------------------------------------------------------- 1 | # Week 1: Introduction to digital electronics, FPGA's and environment setup 2 | 3 | ## Material 4 | - [Shawn Hymel FPGA Part 1: Introduction](https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-1-what-is-an-fpga/3ee5f6c8fa594161a655a9f960060893) 5 | - [Shawn Hymel FPGA Part 2: environment setup](https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-2-toolchain-setup/563a9518cd11466fb6a75cf3cb684d6d) 6 | - Complete the following portions of [ES4 course](http://www.ece.tufts.edu/es/4/) 7 | - [Week 1 September 8](http://www.ece.tufts.edu/es/4/#:~:text=Week%201%20(September%208)) (that is the section name not to be confused with our schedule) 8 | - Lecture 1 slides 9 | - All Videos (6 in total) 10 | - decimal/binary conversion site (counting in binary is very useful in many related fields) 11 | 12 | - [Week 2 September 13](http://www.ece.tufts.edu/es/4/#:~:text=Week%202%20(September%2013)) 13 | - All Videos except the first titled "How to submit your first reading check with provide" (7 in total) 14 | - Lecture 2 slides/handout (logic gates) 15 | - Lecture 3 slides 16 | - Attempt reading check 1 and reading check 2 (research any parts you don't understand/are unfamiliar with) 17 | - Lab 1: Blinky lights 18 | - Breadboard circuit tutorial (Starting Electronics) 19 | - Attempt Homework 1 (completing this successfully is a good indicator that you are ready to continue to next module) 20 | 21 | ## Tasks 22 | - Review the website for open source toolchains etc.: [FPGA Wars](http://fpgawars.github.io/) 23 | - Setup your simulation and synthesis environment 24 | 25 | ## Suggested setup: 26 | 27 | - Online Verilog Simulators: 28 | - [EDA Playground](https://www.edaplayground.com/) 29 | - [8 Bit Workshop](https://8bitworkshop.com/) 30 | 31 | - Graphical FPGA Building Tool: [ICE Studio](https://github.com/fpgawars/icestudio) 32 | 33 | - IDE's: You can use plain old Notepad but I prefer to use an IDE meant for Verilog. Some IDE's I've used for Verilog, in alphabetical order: 34 | - [emacs](https://www.gnu.org/software/emacs/): has a wonderful autocompletion mode that automates various tedious error prone tasks. 35 | - [SublimeText](https://www.sublimetext.com/) with [System Verilog Plugin](https://sv-doc.readthedocs.io/en/latest/) 36 | - [VSCode](https://code.visualstudio.com/) with [TerosHDL plugin](https://terostechnology.github.io/terosHDLdoc/) 37 | 38 | ## Challenge 39 | 1. Complete setting up your coding environment. By the end of this, you should be able to compile verilog code on your computer. You can use APIO or Makefiles (see Advanced challenge below). 40 | - Try using [iverilog](http://iverilog.icarus.com/) to compile some simple verilog code snippets from the web (available in browser via EDA Playground under "tools and simulators" dropdown menu). 41 | - Extra points for running through a full design simulation and being able to explain what it does. 42 | 2. If you have an UPduino or other FPGA board, write code to get various colors on the 3 color LED and program the board with it. Try out the [UPduino FPGA](https://blog.idorobots.org/entries/upduino-fpga-tutorial.html) tutorial to get your hands wet. 43 | 3. Advanced challenge: Setup a command line compile using a [Simple Makefile](https://github.com/tinyvision-ai-inc/UPduino-v3.0/blob/master/RTL/blink_led/Makefile) or a more [Complex Makefile](https://github.com/XarkLabs/upduino-video/blob/master/Makefile) as an example. Go through the makefile and understand what it does. 44 | 45 | Keep in mind this is a complex field notorious for it's steep learning curve, and you are encouraged to discuss any difficulties with your fellow learners. If you get stuck and can't get past a portion of the material by researching it yourself or by discussing it with other learners, ask for help on [the discord](https://discord.gg/dEueU6WP3r) 46 | -------------------------------------------------------------------------------- /Week2.md: -------------------------------------------------------------------------------- 1 | # Week 2: Getting started with logic design, Verilog simulations 2 | 3 | ## Material 4 | - [Module 2 Slide Deck](Slides/Hands_on_with_FPGA's_Module_2.pptx) 5 | - [Prof Chuck Pateros](https://www.sandiego.edu/engineering/undergraduate/computer-science/biography.php?profile_id=6276#:~:text=(Chuck)%20Pateros%20is%20Professor%20of,overseeing%20laboratories%20and%20network%20facilities.) 6 | - [Slide deck](https://docs.google.com/presentation/d/1oOwXZfakxP4jgxQA-depaYAc3wtBubVJPcbfLCDveWg/edit?usp=sharing) 7 | 8 | - Further Reading: [ZipCPU Wires and Combinatorial logic](http://zipcpu.com/tutorial/lsn-01-wires.pdf) 9 | 10 | ## Tasks 11 | - Complete the following Chapters from [Circuitverse Digital Logic Course](https://learn.circuitverse.org/): 12 | - Binary Representation 13 | - Binary Algebra 14 | - Combinational SSI 15 | - Logic Design 16 | 17 | ## Suggested tools: 18 | - [Graphical Circuit Simulator](https://circuitverse.org/) 19 | - Online Verilog Simulators: 20 | - [EDA Playground](https://www.edaplayground.com/) 21 | - [8 Bit Workshop](https://8bitworkshop.com/) 22 | - Graphical FPGA Building Tool: [ICE Studio](https://github.com/fpgawars/icestudio) 23 | - Get comfortable with the command line & Makefiles to run tools: GUI's are low productivity for coding. 24 | 25 | ## Challenge 26 | - Create a System Verilog design that combines what you learnt today. You can use the [EDA Playground Example](https://www.edaplayground.com/x/9) as a starting point and modify it: 27 | - An `adder` module 28 | - Inputs: Two 8 bit unsigned numbers to be added 29 | - Output: The sum of the 2 numbers. 30 | - Testbench to exercise the block and print the output to the console 31 | - Bitwidth analysis is an important part of designing a hardware system as well as algorithms, especially for digital processing. We will do some bitwidth analysis as part of this question. Note that these dont require simulations to be done and can be solved by analysis): 32 | - What is the range of unsigned numbers that can be represented by a variable with 2 bits? 3 bits? 8 bits? 16 bits? 33 | - What pattern do you see here? 34 | - What is the minimum number of bits it takes to represent the sum of the 2 numbers? eg. if two numbers are repesented by 2 bits each, how many bits does it take to represent their sum? What if the inputs are now 3 bits instead of 2 bits? What pattern do you see? 35 | - What if one of the above numbers is represented by 2 bits and the other by 3 bits? 36 | - What if the operation were the difference of the two numbers? 37 | - What if the operation were a multiplication of the 2 numbers? 38 | 39 | ### Advanced Challenges/Thought experiments: 40 | - What happens if there are too few bits to represent the result of the operation? eg. if you have the sum of 2 numbers, each represented by 2 bits and the output is represented by a 2 bit number. This is known as an overflow and is a common bug/feature. 41 | - Can you try simulating this with your Verilog design? 42 | - As mentioned in Prof Pateros's slides, signed and floating point numbers can also be represented in binary. 43 | - Look up how to represent signed numbers in Verilog (Two's complement). 44 | - Change your adder to use signed arithmetic. 45 | - What is the minimum number of bits needed for the above operations if the numbers are signed instead of unsigned or a combination. What happens if a signed number overflows? 46 | - How to implement more complex arithmetic functions like: divide, square root, sine, cosine etc. 47 | 48 | -------------------------------------------------------------------------------- /Week3.md: -------------------------------------------------------------------------------- 1 | # Week 3: Getting started with logic design, Verilog simulations 2 | 3 | ## Material 4 | - [Module 3 Slide Deck](Slides/Hands_on_with_FPGA's_Module_3.pptx) 5 | - Hands-on: [Shawn Hymel Video Part 4](https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-4-clocks-and-procedural-assignments/356e12284daf48b5bd9b80af8a6ac5b8) 6 | 7 | - Further Reading: 8 | - [ZipCPU Registers](http://zipcpu.com/tutorial/lsn-02-regs.pdf) 9 | - Advanced reading: [Asynchronous design using Micropipelines](http://web.cse.msu.edu/~cse820/readings/sutherlandMicropipelinesTuring.pdf) 10 | 11 | ## Tasks 12 | - Complete the following Chapters from [Circuitverse Digital Logic Course](https://learn.circuitverse.org/): 13 | - [Sequential SSI Components](https://learn.circuitverse.org/docs/seq-ssi/) 14 | 15 | ## Suggested tools: 16 | - [Graphical Circuit Simulator](https://circuitverse.org/) 17 | - Online Verilog Simulators: 18 | - [EDA Playground](https://www.edaplayground.com/) 19 | - [8 Bit Workshop](https://8bitworkshop.com/) 20 | - Graphical FPGA Building Tool: [ICE Studio](https://github.com/fpgawars/icestudio) 21 | - Get comfortable with the command line & Makefiles to run tools: GUI's are low productivity for coding. 22 | 23 | ## Challenge 24 | Challenge: Use Circuitverse or preferably SystemVerilog to create a 4-bit binary counter. This should count the following sequence: 0000, 0001, 0010 …, 1110, 1111, 0000 25 | 1. Make the counter count up or down 26 | 2. Can you make it so the counter will stop at a particular count? 27 | 3. Try to make it count on negative edges 28 | 4. What if you didn’t have a reset condition? Can you see what happens? 29 | 30 | [Solution in EDA playground](https://www.edaplayground.com/x/9PwL) 31 | 32 | ### Advanced Challenges/Thought experiments: 33 | 1. Can you create a clock signal from plain logic gates? What is the minimum number of gates you need to create a clock? What determines the frequency of the clock? 34 | 2. How can you create a clock circuit from a NAND gate, resistor and a capacitor? 35 | 3. Analyze some verilog code found in the examples of the [8 Bit Workshop](https://8bitworkshop.com/) 36 | -------------------------------------------------------------------------------- /Week4.md: -------------------------------------------------------------------------------- 1 | # Week 4: State Machines 2 | 3 | ## Material 4 | - [Module 4 Slide Deck](Slides/Hands_on_with_FPGA's_Module_4.pdf) 5 | - [Sunburst paper on State Machines](http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf) 6 | 7 | - Further Reading: 8 | - [Wavedrom paper](https://wavedrom.com/images/SNUG2016_WaveDrom.pdf) 9 | - [GTKWave](http://gtkwave.sourceforge.net/) 10 | - [Sunburst Design papers](http://www.sunburst-design.com/papers/) 11 | - [ASIC World FSM's](http://www.asic-world.com/verilog/memory_fsm2.html#Introduction_to_FSM) 12 | - [ZipCPU Finite State Machines](http://zipcpu.com/tutorial/lsn-03-fsm.pdf) 13 | 14 | ## Tasks 15 | - Read the [Sunburst paper on State Machines](http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf) 16 | - Understand the various coding styles for a state machine 17 | - Try it out! Go through the process of typing it out, compiling it and then if possible, push it into an FPGA. 18 | 19 | ## Suggested tools: 20 | - [Graphical Circuit Simulator](https://circuitverse.org/) 21 | - Online Verilog Simulators: 22 | - [EDA Playground](https://www.edaplayground.com/) 23 | - [8 Bit Workshop](https://8bitworkshop.com/) 24 | - Graphical FPGA Building Tool: [ICE Studio](https://github.com/fpgawars/icestudio) 25 | - Get comfortable with the command line & Makefiles to run tools: GUI's are low productivity for coding. 26 | 27 | ## Challenge 28 | Code up a state machine for a traffic light. Here are the specifications: 29 | - Shall have 3 states: Red, Yellow and Green. 30 | - Start in the Red state on reset 31 | - When the Red timer expires, go to the Green state. 32 | - When the Green timer expires, go to the Yellow state. 33 | - When the Yellow timer expires, go to this Red state. 34 | - In case of roadwork, blink the Red light. 35 | 36 | - Identify the various inputs to the state machine 37 | - Identify the various outputs from the state machine 38 | - Identify what causes the system to change state. 39 | - Draw up the state transition diagram using [diagrams.net](https://www.diagrams.net/) or [Graphviz](https://edotor.net/) 40 | - Pick a specific way to implement the state machine and code it up on [EDA Playground](https://www.edaplayground.com/) or other tool. 41 | - Simulate the state machine and check whether this works. 42 | 43 | ### Advanced Challenges/Thought experiments: 44 | - Practical systems often consist of nested simple state machines rather than a single large one. Larger state machines get harder to verify and corner cases can be tough to test. Extend your state machine so you have lights at all 4 roads at an intersection. 45 | - What does a single state machine for a 4 road intersection look like? How does this extend to cases where you may have intersections with 2, 3 or 5 roads as well as road crossing signals? 46 | - What if you used the same state machine at each intersection instead of a single large one? What information does one state machine need to communicate wiht the others so that the intersection is safe for traffic? 47 | -------------------------------------------------------------------------------- /Week5.md: -------------------------------------------------------------------------------- 1 | # Week 5: Memories: RAM, ROM 2 | 3 | Play with verilog to generate memories and use them in a design. eg. generate some pattern of outputs in the simulator 4 | 5 | 6 | 7 | ## Material 8 | - [Module 5 Slide Deck](Slides/Hands_on_with_FPGA's_Module_5.pdf) 9 | 10 | - Further Reading: 11 | - [ZipCPU Using Block RAM](http://zipcpu.com/tutorial/lsn-08-memory.pdf) 12 | 13 | ## Suggested tools: 14 | - [Graphical Circuit Simulator](https://circuitverse.org/) 15 | - Online Verilog Simulators: 16 | - [EDA Playground](https://www.edaplayground.com/) 17 | - [8 Bit Workshop](https://8bitworkshop.com/) 18 | - Graphical FPGA Building Tool: [ICE Studio](https://github.com/fpgawars/icestudio) 19 | - Get comfortable with the command line & Makefiles to run tools: GUI's are low productivity for coding. 20 | 21 | ## Challenge: Digital Clock 22 | - Create a ROM module that maps hex digits to a 7 segment LED display. The module should take as input a 4 bit input and output a 7 bit vector. 23 | - Create a counter module with a programmable value at which it rolls over and also generates a carry output. Cascade multiple of these to create a seconds, minutes and hours counter. 24 | - Connect each of these modules to the ROM. 25 | - Add an oscillator and clock divider that generates a pulse every second as the input to the clock. 26 | - Add an alarm output that goes active when the clock reaches a particular time. 27 | Hint: See [here](https://www.fpga4fun.com/Opto.html) for a nice introduction to how 7 segment displays work as well as how to drive a few of these critters. 28 | 29 | ### Advanced Challenges/Thought experiments: 30 | - How can you use a small memory to build a bigger one? eg. if you want to build an 8kB memory from two 4kB memories. 31 | - What if you wanted double the bitwidth? How would you restructure the smaller memories? 32 | -------------------------------------------------------------------------------- /Week6.md: -------------------------------------------------------------------------------- 1 | # Week 6: Getting into the real world 2 | - Digital Architecture: How to put a system together? 3 | - Concept of a digital bus 4 | - Why busses? 5 | - Wishbone 6 | - AMBA 7 | - Control path & Data path: 8 | - Common data bus 9 | - Dedicated point-point links 10 | 11 | - FPGA specifics: Beyond the basics 12 | - Pin Constraints 13 | - Timing constraints 14 | - Place and Route 15 | 16 | ## Material 17 | - [Module 6 Slide Deck](Slides/Hands_on_with_FPGA's_Module_6.pdf) 18 | 19 | - Further Reading: 20 | - [NoC](https://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html) 21 | - [Wishbone Specification](https://cdn.opencores.org/downloads/wbspec_b4.pdf) 22 | - [Valid-Ready Protocol](https://inst.eecs.berkeley.edu/~cs150/Documents/Interfaces.pdf) 23 | - Matt Venn's videos on [yosys](https://www.youtube.com/watch?v=A5AHglpfdtQ), [nextpnr](https://www.youtube.com/watch?v=V6B3vT3jMlM), [icepack/iceprog](https://www.youtube.com/watch?v=h4bArgeqcLQ) 24 | - [Lattice iCE40 Ultra Plus FPGA Datasheet](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) 25 | 26 | 27 | ## Challenge: 28 | Go through a non-trivial FPGA design backend 29 | - Download the [upduino-video project](https://github.com/XarkLabs/upduino-video) 30 | - Install the related toolchains 31 | - Run the simulation 32 | - Generate the bitfile 33 | - Identify the following parts of the design process we learned about: 34 | - Simulations 35 | - Pin constraints 36 | - Clock constraints 37 | - Placement related steps 38 | - Routing related steps 39 | - Bitgen 40 | - Are you able to identify how large the design is from the logs? 41 | - What clock frquency was the design able to meet? Rerun the tools and see if this changes. Can you explain why this is different? 42 | - Make changes to the code and play with it to see if you can get any changes in the output of the simulations. 43 | 44 | ### Advanced Challenges/Thought experiments: 45 | - Download the [picosoc](https://github.com/YosysHQ/picorv32) project and play with it. 46 | - Do you see any difference in how long the FPGA backend process takes? 47 | - Are you able to identify how large the design is from the logs? 48 | - What clock frquency was the design able to meet? Rerun the tools and see if this changes. Can you explain why this is different? -------------------------------------------------------------------------------- /Week7.md: -------------------------------------------------------------------------------- 1 | # Week 7: Getting into the real world 2 | - Clock domain crossing 3 | - Common digital design patterns 4 | - 5 | - Running through a complete design flow 6 | - Directory Structure 7 | - Simulation 8 | - Synthesis 9 | - Place and Route/Bitgen 10 | - Testing 11 | 12 | - IDE's 13 | - [Emacs: verilog mode](https://www.veripool.org/verilog-mode/) 14 | - Sublime 15 | - Visual Studio 16 | 17 | - Using IP blocks in your design 18 | - Introduction to FuseSOC 19 | - Initialize with `fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores` 20 | - Add a processor, SPI and I2C core to a design 21 | - Simulations 22 | - Implementation 23 | - [LiteX](https://github.com/enjoy-digital/litex) 24 | - Example of LiteX with the UPduino 25 | 26 | ## Material 27 | - [Module 7 Slide Deck](Slides/Hands_on_with_FPGA's_Module_7.pdf) 28 | - [Shawn Hymel Video](https://www.youtube.com/watch?v=dXU1py-Od1g) 29 | - [EE Times article on Clock Domain Crossing](https://www.eetimes.com/understanding-clock-domain-crossing-issues/) 30 | - [FuseSoC]() 31 | 32 | - Further Reading: 33 | 34 | 35 | ## Challenge: 36 | 37 | ### Advanced Challenges/Thought experiments: 38 | -------------------------------------------------------------------------------- /Week8.md: -------------------------------------------------------------------------------- 1 | # Week 8: Getting into the real world 2 | Other ways to code for Hardware: 3 | CHISEL, High level synthesis, Amaranth, LiteX, CFU Playground 4 | 5 | ## Material 6 | - [Module 8 Slide Deck](Slides/Hands_on_with_FPGA's_Module_8.pdf) 7 | 8 | - Further Reading: 9 | - [CHISEL](https://www.chisel-lang.org/) 10 | - [Chipyard](https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/index.html) 11 | - [Hardware-as-code](https://www.hackster.io/sthibault/hardware-as-code-part-i-an-introduction-48bacb) 12 | 13 | ## Challenge: 14 | - Install Chisel and the Chipyard on your computer (Beware, chipyard can take a loong time!!!) and play with it. 15 | - Install Amaranth and apply some of the concepts you learnt in the class. You may want to try something simple like a counter at first and then start to stitch up more complex things like a CPU. 16 | - Get [CFU-Playground](https://github.com/google/CFU-Playground) installed on your machine and go through the accelerator design. You should now have enough background to start working with this complex project and create your own accelerator flavors. 17 | 18 | ### Advanced Challenges/Thought experiments: 19 | -------------------------------------------------------------------------------- /fusesoc/fusesoc.conf: -------------------------------------------------------------------------------- 1 | [library.fusesoc_cores] 2 | location = fusesoc_libraries\fusesoc_cores 3 | sync-uri = https://github.com/fusesoc/fusesoc-cores 4 | sync-type = git 5 | auto-sync = true 6 | 7 | -------------------------------------------------------------------------------- /resource_list.md: -------------------------------------------------------------------------------- 1 | | **Beginner** | 2 | | --- | 3 | |[ Digi-Key Intro to FPGA](https://www.youtube.com/watch?v=lLg1AgA2Xoo) | 4 | |[ PLD World E-books ](http://ebook.pldworld.com/_eBook/FPGA%EF%BC%8FHDL/-Eng-/)| 5 | |[ Intel FPGA Academy](https://fpgacademy.org/courses.html) | 6 | | [fpga4fun FPGAs 1 - What are they?](https://www.fpga4fun.com/FPGAinfo1.htm) | 7 | | [Micro Enthusiast’s 1st look at Prog. Logic](https://www.allaboutcircuits.com/technical-articles/a-microcontroller-enthusiast-first-look-at-programmable-logic/) | 8 | | [eda playground](https://www.edaplayground.com/home) | 9 | | [Sparkfun So you want to learn FPGAs](https://www.sparkfun.com/news/1203) | 10 | | [Alchitry ](https://alchitry.com/)| 11 | | [Hobbyist's guide to FPGAs](https://hackaday.io/project/27550-the-hobbyists-guide-to-fpgas ) | 12 | | [VHDL Wiz](https://vhdlwhiz.com/ ) | 13 | | [VHDL Wiz Terminology](https://vhdlwhiz.com/terminology/) | 14 | | [Cheap FPGA Development boards](https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards ) | 15 | | [F4PGA Link list](https://f4pga.org/) | 16 | | [fpga 101 fpgas for beginners](https://www.nandland.com/articles/fpga-101-fpgas-for-beginners.html) | 17 | | [Fomu Workshop](https://workshop.fomu.im/en/latest/) | 18 | | [FPGA key](https://www.fpgakey.com/) | 19 | | [GHDL](https://ghdl.github.io/ghdl/) | 20 | | [Verilator](https://www.veripool.org/verilator/) | 21 | | [Icarus Verilog](http://iverilog.icarus.com/) | 22 | | [Digital]( https://github.com/hneemann/Digital/releases) | 23 | | [Verilog Tutorial](http://www.asic-world.com/verilog/veritut.html) | 24 | | [FPGA Design Elements](http://fpgacpu.ca/fpga/index.html) | 25 | -------------------------------------------------------------------------------------------------------- 26 | | **Intermediate** | 27 | | --- | 28 | | [HDL Bits](https://hdlbits.01xz.net/wiki/Main_Page ) | 29 | | [NandGame](https://nandgame.com/) | 30 | | [Upduino Verilog Examples](https://github.com/akaFunk/UpduinoVerilogExamples) | 31 | | [Digital systems design using VHDL](https://www.pdfdrive.com/digital-systems-design-using-vhdl-d166870425.html) | 32 | | [FPGAs now what?](https://xess.com/static/media/appnotes/FpgasNowWhatBook.pdf) | 33 | | [Librecores](https://www.librecores.org/) | 34 | | [MixedSim](https://www.isotel.eu/mixedsim/) | 35 | | [verilog to routing](https://verilogtorouting.org/) | 36 | | [Digital System Design (DSD) Spring 2009](http://www.ee.ic.ac.uk/pcheung/teaching/ee3_DSD/) | 37 | | [HDL Simulators](https://en.wikipedia.org/wiki/List_of_HDL_simulators) | 38 | | [Build an FPGA from 7400 series ICs](http://blog.notdot.net/2012/10/Build-your-own-FPGA) | 39 | | [Digital Logic Pocket Data Book](https://www.ti.com/lit/ug/scyd013b/scyd013b.pdf) | 40 | | [Chipress](https://chipress.online/) | 41 | -------------------------------------------------------------------------------------------------------- 42 | | **Advanced** | 43 | | --- | 44 | | [ZIPCPU](http://zipcpu.com/) | 45 | | [Libre-SOC](https://libre-soc.org/) | 46 | | [open FPGA](https://github.com/azonenberg/openfpga) | 47 | | [FASM](https://fasm.readthedocs.io/en/latest/) | 48 | | [Digital to FPGA 101](https://youtu.be/FcFbFTbngrw) | 49 | | [clock domain crossing](http://fpgacpu.ca/fpga/handshake.html ) | 50 | | [RISCV on an ICE40 FPGA](https://pingu98.wordpress.com/2019/04/08/) | 51 | 52 | -------------------------------------------------------------------------------- /verilog-mode/my_adder.sv: -------------------------------------------------------------------------------- 1 | module my_adder 2 | ( 3 | logic input clk, 4 | logic input rst, 5 | 6 | logic input unsigned [7:0] a_data, 7 | logic input a_valid, 8 | logic output a_ready, 9 | 10 | logic input unsigned [7:0] b_data, 11 | logic input b_valid, 12 | logic output b_ready, 13 | 14 | logic output unsigned [8:0] o_data, 15 | logic output o_valid, 16 | logic input o_ready 17 | ); 18 | 19 | logic do_work; 20 | assign do_work = (a_valid & a_ready) & (b_valid & b_ready); 21 | 22 | always_ff @(posedge clk, rst) 23 | if (rst) o_data <= '0; 24 | else begin 25 | if (do_work) o_data <= a_data + b_data; 26 | end 27 | 28 | // Generate the output valid signal 29 | always_ff @(posedge clk, rst) 30 | if (rst) o_valid <= '0; 31 | else begin 32 | o_valid <= do_work; 33 | end 34 | 35 | // Take inputs only when the output is ready to go and the other output is valid 36 | assign a_ready = o_ready & b_valid; 37 | assign b_ready = o_ready & a_valid; 38 | 39 | endmodule // my_adder 40 | -------------------------------------------------------------------------------- /verilog-mode/my_block.sv: -------------------------------------------------------------------------------- 1 | module my_block 2 | ( 3 | logic input clk, 4 | logic input rst, 5 | 6 | logic input unsigned [7:0] a_data, 7 | logic input a_valid, 8 | logic output a_ready, 9 | 10 | logic input unsigned [7:0] b_data, 11 | logic input b_valid, 12 | logic output b_ready, 13 | 14 | logic output unsigned [8:0] o_data, 15 | logic output o_valid, 16 | logic input o_ready 17 | ); 18 | 19 | my_adder first_adder (/*AUTOINST*/); 20 | my_adder second_adder (/*AUTOINST*/); 21 | 22 | endmodule // my_block 23 | -------------------------------------------------------------------------------- /wb_config/Makefile: -------------------------------------------------------------------------------- 1 | 2 | wb_intercon: wb_config.cfg 3 | ../wb_intercon/sw/wb_intercon_gen wb_config.cfg my_wishbone.v 4 | 5 | clean: 6 | rm -rf my_wishbone.* -------------------------------------------------------------------------------- /wb_config/wb_config.cfg: -------------------------------------------------------------------------------- 1 | [master camera] 2 | slaves = 3 | ram 4 | 5 | [master processor] 6 | slaves = 7 | ram 8 | csr 9 | 10 | [master encoder] 11 | slaves = 12 | ram 13 | 14 | [slave ram] 15 | offset: 0x00000000 16 | size : 0x00100000 17 | 18 | [slave csr] 19 | offset: 0x006000000 20 | size : 0x001000000 21 | --------------------------------------------------------------------------------