├── bitstream_ddr_quartus └── src │ ├── 1.ses │ ├── altera │ ├── cmd_fifo.v │ ├── ddr │ │ ├── alt_ddrx_addr_cmd.v │ │ ├── alt_ddrx_afi_block.v │ │ ├── alt_ddrx_avalon_if.v │ │ ├── alt_ddrx_bank_timer.v │ │ ├── alt_ddrx_bank_timer_info.v │ │ ├── alt_ddrx_bank_timer_wrapper.v │ │ ├── alt_ddrx_bypass.v │ │ ├── alt_ddrx_cache.v │ │ ├── alt_ddrx_clock_and_reset.v │ │ ├── alt_ddrx_cmd_gen.v │ │ ├── alt_ddrx_cmd_queue.v │ │ ├── alt_ddrx_controller.v │ │ ├── alt_ddrx_csr.v │ │ ├── alt_ddrx_ddr2_odt_gen.v │ │ ├── alt_ddrx_ddr3_odt_gen.v │ │ ├── alt_ddrx_decoder.v │ │ ├── alt_ddrx_decoder_40.v │ │ ├── alt_ddrx_decoder_72.v │ │ ├── alt_ddrx_ecc.v │ │ ├── alt_ddrx_encoder.v │ │ ├── alt_ddrx_encoder_40.v │ │ ├── alt_ddrx_encoder_72.v │ │ ├── alt_ddrx_input_if.v │ │ ├── alt_ddrx_odt_gen.v │ │ ├── alt_ddrx_rank_monitor.v │ │ ├── alt_ddrx_state_machine.v │ │ ├── alt_ddrx_timing_param.v │ │ ├── alt_ddrx_wdata_fifo.v │ │ ├── alt_mem_phy_defines.v │ │ ├── altera_avalon_half_rate_bridge.v │ │ ├── altera_avalon_half_rate_bridge_constraints.sdc │ │ ├── altera_primitives.v │ │ ├── altmemphy-library │ │ │ └── auk_ddr_hp_controller.ocp │ │ ├── ddr.bsf │ │ ├── ddr.cr.mti │ │ ├── ddr.html │ │ ├── ddr.ppf │ │ ├── ddr.qip │ │ ├── ddr.v │ │ ├── ddr_advisor.ipa │ │ ├── ddr_alt_ddrx_controller_wrapper.v │ │ ├── ddr_bb.v │ │ ├── ddr_controller_phy.v │ │ ├── ddr_ex_lfsr8.v │ │ ├── ddr_example_driver.v │ │ ├── ddr_example_top.sdc │ │ ├── ddr_example_top.v │ │ ├── ddr_example_top.v.tmp2 │ │ ├── ddr_example_top_1.v │ │ ├── ddr_example_top_2.v │ │ ├── ddr_example_top_3.v │ │ ├── ddr_example_top_4.v │ │ ├── ddr_high_performance_controller-library │ │ │ └── auk_ddr_hp_controller.ocp │ │ ├── ddr_phy.bsf │ │ ├── ddr_phy.html │ │ ├── ddr_phy.qip │ │ ├── ddr_phy.v │ │ ├── ddr_phy_alt_mem_phy.v │ │ ├── ddr_phy_alt_mem_phy_pll.qip │ │ ├── ddr_phy_alt_mem_phy_pll.v │ │ ├── ddr_phy_alt_mem_phy_pll.v_.bak │ │ ├── ddr_phy_alt_mem_phy_pll_bb.v │ │ ├── ddr_phy_alt_mem_phy_seq.vhd │ │ ├── ddr_phy_alt_mem_phy_seq_wrapper.v │ │ ├── ddr_phy_bb.v │ │ ├── ddr_phy_ddr_pins.tcl │ │ ├── ddr_phy_ddr_timing.sdc │ │ ├── ddr_phy_ddr_timing.tcl │ │ ├── ddr_phy_report_timing.tcl │ │ ├── ddr_phy_report_timing_core.tcl │ │ ├── ddr_pin_assignments.tcl │ │ ├── ddr_pin_assignments.tcl.bak │ │ ├── defines.v │ │ ├── greybox_tmp │ │ │ └── cbx_args.txt │ │ ├── out.mem │ │ ├── testbench │ │ │ ├── ddr_example_top_tb.v │ │ │ ├── ddr_example_top_tb.v.tmp2 │ │ │ ├── ddr_example_top_tb_1.v │ │ │ ├── ddr_example_top_tb_2.v │ │ │ ├── ddr_example_top_tb_3.v │ │ │ ├── ddr_example_top_tb_4.v │ │ │ ├── ddr_full_mem_model.v │ │ │ └── ddr_mem_model.v │ │ ├── wave.do │ │ ├── wave1.do │ │ └── 复件 ddr_pin_assignments.tcl.bak │ ├── fifo_read_info.v │ ├── pixel_fifo.v │ ├── pll.ppf │ ├── pll.qip │ ├── pll.v │ ├── read_fifo.v │ ├── stream_fifo.v │ └── write_fifo.v │ ├── bitstream_controller.v │ ├── bitstream_ena_gen.v │ ├── bitstream_fifo.v │ ├── bitstream_test.v │ ├── cavlc_fsm.v │ ├── cavlc_len_gen.v │ ├── cavlc_read_levels.v │ ├── cavlc_read_run_befores.v │ ├── cavlc_read_total_coeffs.v │ ├── cavlc_read_total_zeros.v │ ├── cavlc_top.v │ ├── dc_fifo.v │ ├── dc_fifo_async_read.v │ ├── decode_stream.v │ ├── defines.v │ ├── ext_mem_hub.v │ ├── ext_mem_writer.v │ ├── get_mvp.v │ ├── inter_pred_calc.v │ ├── inter_pred_fsm.v │ ├── inter_pred_load.v │ ├── inter_pred_top.v │ ├── intra4x4_pred_mode_decoding.v │ ├── intra_pred_PE.v │ ├── intra_pred_fsm.v │ ├── intra_pred_precalc.v │ ├── intra_pred_regs.v │ ├── intra_pred_top.v │ ├── nC_decoding.v │ ├── play_pause.v │ ├── play_pause.v.bak │ ├── pps.v │ ├── ram.v │ ├── rbsp_buffer.v │ ├── read_bits.v │ ├── read_exp_golomb.v │ ├── read_nalu.v │ ├── residual_ctrl.v │ ├── residual_top.v │ ├── sd_read │ ├── ctrlStsRegBI.v │ ├── fat32_read_file.v │ ├── initSD.v │ ├── ram.v │ ├── readWriteSDBlock.v │ ├── readWriteSPIWireData.v │ ├── sd_read_top.v │ ├── sendCmd.v │ ├── sm_RxFifo.v │ ├── sm_RxFifoBI.v │ ├── sm_TxFifo.v │ ├── sm_TxFifoBI.v │ ├── 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