├── Experiment ├── Exp3_ALU │ ├── ALU_M.stx │ ├── ALU_M.lso │ ├── ALU_TOP.lso │ ├── CLED_M.lso │ ├── Choice_M.lso │ ├── isim │ │ ├── pn_info │ │ ├── ALU_TEST_isim_beh.exe.sim │ │ │ ├── isimcrash.log │ │ │ ├── netId.dat │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ ├── libPortability.dll │ │ │ ├── ALU_TEST_isim_beh.exe │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── work │ │ │ │ ├── ALU_TEST_isim_beh.exe_main.nt64.obj │ │ │ │ ├── m_00000000000044912214_0596150753.didat │ │ │ │ ├── m_00000000000054293371_4092549402.didat │ │ │ │ ├── m_00000000000382606285_2631355185.didat │ │ │ │ ├── m_00000000000906111599_0746708786.didat │ │ │ │ ├── m_00000000003345945164_2631355185.didat │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── m_00000000004274923758_1273188681.didat │ │ │ │ ├── m_00000000000044912214_0596150753.nt64.obj │ │ │ │ ├── m_00000000000054293371_4092549402.nt64.obj │ │ │ │ ├── m_00000000000382606285_2631355185.nt64.obj │ │ │ │ ├── m_00000000000906111599_0746708786.nt64.obj │ │ │ │ ├── m_00000000003345945164_2631355185.nt64.obj │ │ │ │ ├── m_00000000004134447467_2073120511.nt64.obj │ │ │ │ └── m_00000000004274923758_1273188681.nt64.obj │ │ │ └── isimkernel.log │ │ ├── temp │ │ │ ├── glbl.sdb │ │ │ ├── @a@l@u_@m.sdb │ │ │ ├── @choice_@m.sdb │ │ │ ├── @c@l@e@d_@m.sdb │ │ │ ├── @a@l@u_@t@e@s@t.sdb │ │ │ └── @a@l@u_@t@o@p.sdb │ │ └── work │ │ │ ├── glbl.sdb │ │ │ ├── @a@l@u_@m.sdb │ │ │ ├── @choice_@m.sdb │ │ │ ├── @c@l@e@d_@m.sdb │ │ │ ├── @a@l@u_@t@e@s@t.sdb │ │ │ └── @a@l@u_@t@o@p.sdb │ ├── xilinxsim.ini │ ├── CLED_M.prj │ ├── ALU_TOP.prj │ ├── Choice_M.prj │ ├── isim.cmd │ ├── ALU_M.prj │ ├── ALU_M_summary.html │ ├── planAhead_run_1 │ │ ├── Exp3.data │ │ │ ├── constrs_1 │ │ │ │ ├── usercols.xml │ │ │ │ ├── designprops.xml │ │ │ │ └── fileset.xml │ │ │ ├── wt │ │ │ │ ├── project.wpc │ │ │ │ └── java_command_handlers.wdf │ │ │ ├── sim_1 │ │ │ │ └── fileset.xml │ │ │ └── sources_1 │ │ │ │ └── ports.xml │ │ └── Exp3.ppr │ ├── xst │ │ └── work │ │ │ ├── work.sdbl │ │ │ └── work.sdbx │ ├── ALU_TEST_isim_beh.exe │ ├── ALU_TEST_isim_beh.wdb │ ├── planAhead_run_2 │ │ ├── Exp3.data │ │ │ ├── wt │ │ │ │ └── project.wpc │ │ │ ├── runs │ │ │ │ ├── runs.xml │ │ │ │ └── impl_1.psg │ │ │ ├── sim_1 │ │ │ │ └── fileset.xml │ │ │ ├── constrs_1 │ │ │ │ └── fileset.xml │ │ │ └── sources_1 │ │ │ │ └── fileset.xml │ │ ├── planAhead.jou │ │ └── Exp3.ppr │ ├── ALU_TEST_beh.prj │ ├── ALU_TEST_stx_beh.prj │ ├── fuseRelaunch.cmd │ ├── isim.log │ ├── ALU_M.ucf │ ├── pa.fromNetlist.tcl │ ├── ALU_M.cmd_log │ ├── planAhead.ngc2edif.log │ ├── ALU_M.v │ ├── ALU.vhd │ ├── pa.fromHdl.tcl │ ├── CLED_M.v │ ├── ALU_M.xst │ ├── ALU_TOP.xst │ ├── CLED_M.xst │ └── Choice_M.xst ├── Exp2_CLAAdderM │ ├── CLLAAdderM.stx │ ├── isim │ │ ├── pn_info │ │ ├── CLLAAdderM_isim_beh.exe.sim │ │ │ ├── isimcrash.log │ │ │ ├── netId.dat │ │ │ ├── libPortability.dll │ │ │ ├── CLLAAdderM_isim_beh.exe │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── work │ │ │ │ ├── CLLAAdderM_isim_beh.exe_main.nt64.obj │ │ │ │ ├── m_00000000001001103730_2177708692.didat │ │ │ │ ├── m_00000000003917437390_4204508085.didat │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── m_00000000001001103730_2177708692.nt64.obj │ │ │ │ ├── m_00000000003917437390_4204508085.nt64.obj │ │ │ │ └── m_00000000004134447467_2073120511.nt64.obj │ │ │ └── isimkernel.log │ │ ├── CLLAAdderM_test_isim_beh.exe.sim │ │ │ ├── isimcrash.log │ │ │ ├── netId.dat │ │ │ ├── libPortability.dll │ │ │ ├── CLLAAdderM_test_isim_beh.exe │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── work │ │ │ │ ├── m_00000000000273066092_3048495714.didat │ │ │ │ ├── m_00000000001001103730_2177708692.didat │ │ │ │ ├── m_00000000003796769026_2177708692.didat │ │ │ │ ├── m_00000000003917437390_4204508085.didat │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── CLLAAdderM_test_isim_beh.exe_main.nt64.obj │ │ │ │ ├── m_00000000000273066092_3048495714.nt64.obj │ │ │ │ ├── m_00000000001001103730_2177708692.nt64.obj │ │ │ │ ├── m_00000000003796769026_2177708692.nt64.obj │ │ │ │ ├── m_00000000003917437390_4204508085.nt64.obj │ │ │ │ └── m_00000000004134447467_2073120511.nt64.obj │ │ │ └── isimkernel.log │ │ ├── temp │ │ │ ├── glbl.sdb │ │ │ ├── fulladder@m.sdb │ │ │ ├── @c@l@l@a@adder@m.sdb │ │ │ └── @c@l@l@a@adder@m_test.sdb │ │ └── work │ │ │ ├── glbl.sdb │ │ │ ├── fulladder@m.sdb │ │ │ ├── @c@l@l@a@adder@m.sdb │ │ │ └── @c@l@l@a@adder@m_test.sdb │ ├── CLLAAdderM.lso │ ├── xilinxsim.ini │ ├── CLLAAdderM.prj │ ├── isim.cmd │ ├── CLLAAdderM.xpi │ ├── _ngo │ │ └── netlist.lst │ ├── CLLAAdderM.v │ ├── cllaadderm.bit │ ├── xst │ │ └── work │ │ │ ├── work.sdbl │ │ │ └── work.sdbx │ ├── CLLAAdderM_isim_beh.exe │ ├── CLLAAdderM_summary.html │ ├── CLLAAdderM_isim_beh1.wdb │ ├── CLLAAdderM_test_beh.prj │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ ├── CLLAAdderM_test_isim_beh.exe │ ├── CLLAAdderM_test_isim_beh.wdb │ ├── CLLAAdderM_test_isim_beh1.wdb │ ├── CLLAAdderM_test_stx_beh.prj │ ├── cllaadderm.drc │ ├── CLLAAdderM_bitgen.xwbt │ ├── fuseRelaunch.cmd │ ├── CLAAAdderM.ucf │ ├── fuse.xmsgs │ ├── _xmsgs │ │ ├── xst.xmsgs │ │ ├── bitgen.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── pn_parser.xmsgs │ │ └── trce.xmsgs │ ├── CLLAAdderM.unroutes │ ├── CLLAAdderM_summary.xml │ ├── isim.log │ ├── CLLAAdderM.ut │ ├── webtalk.log │ ├── CLLAAdderM.pcf │ ├── CLLAAdderM.bld │ ├── CLLAAdderM.xst │ └── fuse.log ├── Exp1_FullAdderM │ ├── isim │ │ ├── pn_info │ │ ├── fulladderM_test_isim_beh.exe.sim │ │ │ ├── isimcrash.log │ │ │ ├── netId.dat │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ ├── libPortability.dll │ │ │ ├── fulladderM_test_isim_beh.exe │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── work │ │ │ │ ├── m_00000000002746943017_3087695799.didat │ │ │ │ ├── m_00000000003917437390_4204508085.didat │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── fulladderM_test_isim_beh.exe_main.nt64.obj │ │ │ │ ├── m_00000000002746943017_3087695799.nt64.obj │ │ │ │ ├── m_00000000003917437390_4204508085.nt64.obj │ │ │ │ └── m_00000000004134447467_2073120511.nt64.obj │ │ │ └── isimkernel.log │ │ └── work │ │ │ ├── glbl.sdb │ │ │ ├── fulladder@m.sdb │ │ │ └── fulladder@m_test.sdb │ ├── fulladderM.lso │ ├── xilinxsim.ini │ ├── fulladderM.prj │ ├── isim.cmd │ ├── fulladderM.xpi │ ├── _ngo │ │ └── netlist.lst │ ├── fulladderM.v │ ├── fulladderm.bit │ ├── xst │ │ └── work │ │ │ ├── work.sdbl │ │ │ └── work.sdbx │ ├── fulladderM_summary.html │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ ├── fulladderM_test_beh.prj │ ├── fulladderM_test_isim_beh.exe │ ├── fulladderM_test_isim_beh.wdb │ ├── FullAdderM_C.ucf │ ├── fulladderM.unroutes │ ├── fulladderm.drc │ ├── fulladderM_bitgen.xwbt │ ├── fuseRelaunch.cmd │ ├── _xmsgs │ │ ├── bitgen.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── xst.xmsgs │ │ ├── pn_parser.xmsgs │ │ ├── par.xmsgs │ │ └── trce.xmsgs │ ├── fulladderM_summary.xml │ ├── isim.log │ ├── fulladderM.pcf │ ├── fuse.xmsgs │ ├── fulladderM.ut │ ├── webtalk.log │ ├── fulladderM.cmd_log │ ├── fulladderM.bld │ └── fulladderM.ngr ├── Exp4_Segment │ ├── Segment_M.lso │ ├── Segment_Top.lso │ ├── isim │ │ ├── pn_info │ │ ├── Segment_M_isim_beh.exe.sim │ │ │ ├── isimcrash.log │ │ │ ├── netId.dat │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ ├── libPortability.dll │ │ │ ├── Segment_M_isim_beh.exe │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── work │ │ │ │ ├── Segment_M_isim_beh.exe_main.nt64.obj │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── m_00000000004244404791_1771163631.didat │ │ │ │ ├── m_00000000004134447467_2073120511.nt64.obj │ │ │ │ └── m_00000000004244404791_1771163631.nt64.obj │ │ │ └── isimkernel.log │ │ ├── Segment_Test_isim_beh.exe.sim │ │ │ ├── isimcrash.log │ │ │ ├── netId.dat │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ ├── libPortability.dll │ │ │ ├── Segment_Test_isim_beh.exe │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── work │ │ │ │ ├── Segment_Test_isim_beh.exe_main.nt64.obj │ │ │ │ ├── m_00000000001414976503_3238004345.didat │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── m_00000000004244404791_1771163631.didat │ │ │ │ ├── m_00000000001414976503_3238004345.nt64.obj │ │ │ │ ├── m_00000000004134447467_2073120511.nt64.obj │ │ │ │ └── m_00000000004244404791_1771163631.nt64.obj │ │ │ └── isimkernel.log │ │ ├── temp │ │ │ ├── glbl.sdb │ │ │ ├── @segment_@m.sdb │ │ │ └── @segment_@test.sdb │ │ └── work │ │ │ ├── glbl.sdb │ │ │ ├── @segment_@m.sdb │ │ │ └── @segment_@test.sdb │ ├── xilinxsim.ini │ ├── Segment_M.prj │ ├── Segment_Top.prj │ ├── isim.cmd │ ├── Segment_M.v │ ├── Segment_M_stx_beh.prj │ ├── Segment_M.txt │ ├── xst │ │ └── work │ │ │ ├── work.sdbl │ │ │ └── work.sdbx │ ├── Segment_M_isim_beh.exe │ ├── Segment_M_summary.html │ ├── planAhead_run_2 │ │ ├── Exp4_Segment.data │ │ │ ├── constrs_1 │ │ │ │ ├── usercols.xml │ │ │ │ ├── designprops.xml │ │ │ │ └── fileset.xml │ │ │ ├── wt │ │ │ │ ├── project.wpc │ │ │ │ └── java_command_handlers.wdf │ │ │ ├── sim_1 │ │ │ │ └── fileset.xml │ │ │ └── sources_1 │ │ │ │ ├── fileset.xml │ │ │ │ └── ports.xml │ │ └── Exp4_Segment.ppr │ ├── Segment_Test_beh.prj │ ├── Segment_Test_isim_beh.exe │ ├── Segment_Test_isim_beh.wdb │ ├── Segment_Top_summary.html │ ├── Segment_Test_isim_beh1.wdb │ ├── Segment_Test_stx_beh.prj │ ├── planAhead_run_1 │ │ ├── Exp4_Segment.data │ │ │ ├── wt │ │ │ │ └── project.wpc │ │ │ ├── sim_1 │ │ │ │ └── fileset.xml │ │ │ ├── constrs_1 │ │ │ │ └── fileset.xml │ │ │ └── sources_1 │ │ │ │ └── fileset.xml │ │ ├── planAhead.jou │ │ └── Exp4_Segment.ppr │ ├── fuseRelaunch.cmd │ ├── fuse.xmsgs │ ├── _xmsgs │ │ ├── xst.xmsgs │ │ └── pn_parser.xmsgs │ ├── isim.log │ ├── Segment_M.ucf │ ├── pa.fromHdl.tcl │ ├── fuse.log │ └── Segment_M.xst └── Exp5_MemoryIP │ ├── isim │ ├── pn_info │ ├── M1_Test_isim_beh.exe.sim │ │ ├── isimcrash.log │ │ ├── netId.dat │ │ ├── tmp_save │ │ │ └── _1 │ │ ├── libPortability.dll │ │ ├── M1_Test_isim_beh.exe │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── work │ │ │ ├── M1_Test_isim_beh.exe_main.nt64.obj │ │ │ ├── m_00000000001790121353_1020318486.didat │ │ │ ├── m_00000000003332246395_3424102411.didat │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ ├── m_00000000001790121353_1020318486.nt64.obj │ │ │ ├── m_00000000003332246395_3424102411.nt64.obj │ │ │ └── m_00000000004134447467_2073120511.nt64.obj │ │ └── isimkernel.log │ └── work │ │ ├── glbl.sdb │ │ ├── @m1_@test.sdb │ │ └── @method_1_@memory_m.sdb │ ├── Method_1_Memory_m.lso │ ├── ipcore_dir │ ├── tmp │ │ ├── RAM_B.lso │ │ └── _xmsgs │ │ │ └── pn_parser.xmsgs │ ├── RAM_B │ │ ├── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ ├── implement.sh │ │ │ └── implement.bat │ │ ├── simulation │ │ │ ├── timing │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_mti.bat │ │ │ │ ├── wave_ncsim.sv │ │ │ │ └── wave_mti.do │ │ │ └── functional │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── simulate_mti.bat │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── wave_ncsim.sv │ │ │ │ └── wave_mti.do │ │ └── doc │ │ │ └── pg058-blk-mem-gen.pdf │ ├── coregen.log │ ├── coregen.cgp │ ├── RAM_B.mif │ ├── _xmsgs │ │ ├── cg.xmsgs │ │ └── pn_parser.xmsgs │ ├── RAM_B.asy │ ├── summary.log │ └── edit_RAM_B.tcl │ ├── xilinxsim.ini │ ├── Method_1_Memory_m.prj │ ├── isim.cmd │ ├── xst │ └── work │ │ ├── work.sdbl │ │ └── work.sdbx │ ├── M1_Test_beh.prj │ ├── M1_Test_isim_beh.exe │ ├── M1_Test_isim_beh.wdb │ ├── Memory.coe │ ├── fuseRelaunch.cmd │ ├── fuse.xmsgs │ ├── _xmsgs │ ├── xst.xmsgs │ └── pn_parser.xmsgs │ ├── isim.log │ ├── RAM_B_Test.v │ ├── Method_1_Memory_m.v │ ├── fuse.log │ └── Method_1_Memory_m.xst ├── .gitignore ├── Slides ├── 校验码.pdf ├── 主存储器.pdf ├── 名词术语.pdf ├── 固态硬盘.pdf ├── 实验绪论.pdf ├── 寻址方式.pdf ├── 总线（1）.pdf ├── 总线（2）.pdf ├── 戈登•摩尔.pdf ├── 指令格式.pdf ├── 指令类型.pdf ├── 指令系统.pdf ├── 数据格式.pdf ├── 概论（1）.pdf ├── 概论（2）.pdf ├── 流水线原理.pdf ├── 高速存储器.pdf ├── 名词术语（概论）.pdf ├── 存储体系概述.pdf ├── 实验报告格式.pdf ├── 数值数据的表示.pdf ├── 时序逻辑电路实例.pdf ├── 浮点运算及运算器.pdf ├── 浮点运算器举例.pdf ├── 移位控制实验讲解.pdf ├── 组合逻辑电路实例.pdf ├── 进位控制实验讲解.pdf ├── 非数值数据的表示.pdf ├── MIPS实验三总结.pdf ├── MIPS的乘除法运算.pdf ├── MIPS的内存映射.pdf ├── MIPS的浮点操作.pdf ├── 半导体器件的开关特性.pdf ├── 外存储器(补充资料）.pdf ├── 存储器读_写实验讲解.pdf ├── 存储器读写实验及总结.pdf ├── 定点数除法运算及实现.pdf ├── 定点机器数表示方法.pdf ├── 实验系统常见问题解答.pdf ├── 微程序控制器（10）.pdf ├── 微程序控制器（1）.pdf ├── 微程序控制器（2）.pdf ├── 微程序控制器（3）.pdf ├── 微程序控制器（4）.pdf ├── 微程序控制器（5）.pdf ├── 微程序控制器（6）.pdf ├── 微程序控制器（7）.pdf ├── 微程序控制器（8）.pdf ├── 微程序控制器（9）.pdf ├── 浮点机器数的表示方法.pdf ├── 硬布线控制器（1）.pdf ├── 硬布线控制器（2）.pdf ├── 移位控制实验及总结.pdf ├── 算术逻辑运算实验讲解.pdf ├── 计算机芯片的制造过程.pdf ├── 输入输出系统（1）.pdf ├── 输入输出系统（2）.pdf ├── 进位控制实验及总结.pdf ├── MIPS系统的数据存储.pdf ├── 《计算机硬件基础》例题.pdf ├── 《计算机硬件基础》名词术语.pdf ├── 动态微程序的设计与实现讲解.pdf ├── 基本逻辑运算和基本门电路.pdf ├── 定点运算器的组成与结构.pdf ├── 总线数据传送控制实验及总结.pdf ├── 总线数据传送控制实验讲解.pdf ├── 现代计算机系统的数据表示.pdf ├── 综合实验设计题目（举例1）.pdf ├── 综合实验设计题目（举例2）.pdf ├── MIPS实验一（全加器设计）.pdf ├── MIPS实验五（存储器设计）.pdf ├── MIPS实验四----六总结.pdf ├── MIPS实验四（寄存器堆设计）.pdf ├── MIPS实验第4章 实验系统.pdf ├── MIPS的数据存储（补充阅读）.pdf ├── 主存储器与CPU的连接（1）.pdf ├── 主存储器与CPU的连接（2）.pdf ├── 定点数的乘法运算及实现（1）.pdf ├── 定点数的乘法运算及实现（2）.pdf ├── 定点数的加减运算及实现（1）.pdf ├── 定点数的加减运算及实现（2）.pdf ├── 控制器的组成及指令的执行（1）.pdf ├── 控制器的组成及指令的执行（2）.pdf ├── 控制器的组成及指令的执行（3）.pdf ├── 控制器的组成及指令的执行（4）.pdf ├── 简单模型机设计与实现（讲解）.pdf ├── 虚拟存储器、外存储器与存储保护.pdf ├── 高速缓冲存储器Cache（1）.pdf ├── 高速缓冲存储器Cache（2）.pdf ├── MIPS实验三（多功能ALU设计）.pdf ├── MIPS实验二（超前进位加法器设计）.pdf ├── MIPS的加减法指令以及溢出判断.pdf ├── 《存储体系》例题--多体交叉存储器.pdf ├── 实验教学软件（上位机软件）使用说明书.pdf ├── 微控器及上位机软件认识性实验及总结.pdf ├── 微控器及上位机软件认识性实验讲解.pdf ├── 游戏版计算机组成原理实验软件说明书.pdf ├── 简单模型机的设计与实现实验及总结.pdf ├── 计算机机器数运算与转换软件使用说明书.pdf ├── 非教学模型机上的动态微程序设计2.pdf ├── MIPS32指令格式、寻址方式和指令分类.pdf ├── MIPS实验七（取指令与指令译码实验）.pdf ├── 《信息编码与数据表示》例题--数制转换.pdf ├── 《流水线相关及处理》例题--流水线原理.pdf ├── 《运算器与运算方法》例题--移码加减运算.pdf ├── 单周期处理器的数据通路和指令的执行过程.pdf ├── MIPS实验九（R-I型指令的CPU设计）.pdf ├── MIPS实验八（实现R型指令的CPU设计实验）.pdf ├── MIPS实验六（MIPS汇编器与模拟器实验）.pdf ├── MIPS实验十（R-I-J型指令的CPU设计）.pdf ├── MIPS实验第2章 MIPS体系结构与指令系统.pdf ├── MIPS实验第3章 Verilog HDL基础.pdf ├── 《信息编码与数据表示》例题--定点机器数的表示.pdf ├── 《信息编码与数据表示》例题--循环冗余校验码.pdf ├── 《信息编码与数据表示》例题--浮点机器数的表示.pdf ├── 《存储体系》例题--主存储器与CPU的连接.pdf ├── 《运算器与运算方法》例题--定点数的乘法运算.pdf ├── 《运算器与运算方法》例题--定点数除法运算.pdf ├── 《运算器与运算方法》例题--定点补码加减法.pdf ├── 《运算器与运算方法》例题--机器数的移位运算.pdf ├── 《运算器与运算方法》例题--浮点运算及运算器.pdf ├── 实验模型机指令系统与微程序设计-学生作品DOC.pdf ├── MIPS控制器的组成及指令的执行(基于实验讲解）.pdf ├── 《运算器与运算方法》例题--定点运算器的组成与结构.pdf ├── 单周期处理器的数据通路和指令的执行过程（理论讲课）.pdf └── MIPS实验第1章 计算机硬件设计、FPGA与HDL.pdf ├── Notes ├── 计算机硬件基础.mmap ├── 运算方法和运算器.mmap ├── 信息编码与数据表示.mmap ├── 计算机组成原理概论.mmap ├── 计算机组成原理与系统结构概览.mmap └── Review.md ├── Resources ├── Tests │ ├── 2014年期末试卷.pdf │ ├── 2014年期末试卷答案.pdf │ ├── MIPS实验考试笔试题-1.pdf │ ├── MIPS实验考试笔试题-2.pdf │ ├── MIPS实验考试笔试题-3.pdf │ ├── 10级计算机-计算机组成原理（甲）试卷-A卷.pdf │ ├── 10级计算机-计算机组成原理（甲）试卷-A卷答案.pdf │ ├── 10级计算机-计算机组成原理（甲）试卷-B卷.pdf │ ├── 10级计算机-计算机组成原理（甲）试卷-B卷答案.pdf │ ├── 12级计算机-计算机组成原理（甲）试卷-A卷.pdf │ ├── 12级计算机-计算机组成原理（甲）试卷-A卷答案.pdf │ ├── 12级计算机-计算机组成原理（甲）试卷-B卷.pdf │ ├── 12级计算机-计算机组成原理（甲）试卷-B卷答案.pdf │ └── 2010级计算机-计算机组成原理课程设计试卷及答案.pdf ├── USTC │ ├── Ch0-课程介绍.pdf │ ├── Ch2.1-指令系统.pdf │ ├── Ch1-计算机系统概论.pdf │ ├── Ch2.2-程序的编译过程.pdf │ └── Ch3-MIPS处理器设计.pdf └── ProblemSol │ ├── MIPS作业-1.pdf │ ├── MIPS作业及答案.pdf │ ├── 《总线》习题及答案.pdf │ ├── 《概论》习题及答案.pdf │ ├── MIPS实验报告格式.pdf │ ├── 《存储体系》习题及答案.pdf │ ├── 《指令系统》习题及答案.pdf │ ├── 《计算机硬件基础》习题及答案.pdf │ ├── 《输入输出系统》习题及答案.pdf │ ├── 《信息编码与数据表示》习题及答案.pdf │ ├── 《运算方法与运算器》习题及答案.pdf │ ├── MIPS作业-2（基于实验的作业）.pdf │ ├── 优秀学生实验报告（MIPS)-实验一.pdf │ ├── 优秀学生实验报告（MIPS)-实验七.pdf │ ├── 优秀学生实验报告（MIPS)-实验九.pdf │ ├── 优秀学生实验报告（MIPS)-实验二.pdf │ ├── 优秀学生实验报告（MIPS)-实验六.pdf │ ├── 优秀学生实验报告（MIPS）-实验八.pdf │ └── MIPS Instruction Reference.html └── README.md /Experiment/Exp3_ALU/ALU_M.stx: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_M.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.stx: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_TOP.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/CLED_M.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/Choice_M.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/Segment_M.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/Segment_Top.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/CLED_M.prj: -------------------------------------------------------------------------------- 1 | verilog work "CLED_M.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/Method_1_Memory_m.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/tmp/RAM_B.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_TOP.prj: -------------------------------------------------------------------------------- 1 | verilog work "ALU_TOP.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/Choice_M.prj: -------------------------------------------------------------------------------- 1 | verilog work "Choice_M.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim/ALU_TEST_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/Segment_M.prj: -------------------------------------------------------------------------------- 1 | verilog work "Segment_M.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/isim/M1_Test_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.prj: -------------------------------------------------------------------------------- 1 | verilog work "fulladderM.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.prj: -------------------------------------------------------------------------------- 1 | verilog work "CLLAAdderM.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim/CLLAAdderM_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/Segment_Top.prj: -------------------------------------------------------------------------------- 1 | verilog work "Segment_Top.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim/Segment_M_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim/Segment_Test_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/isim/fulladderM_test_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim/CLLAAdderM_test_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/Method_1_Memory_m.prj: -------------------------------------------------------------------------------- 1 | verilog work "Method_1_Memory_m.v" 2 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | 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-------------------------------------------------------------------------------- 1 | verilog isim_temp "Segment_M.v" 2 | verilog isim_temp "Segment_Test.v" 3 | verilog isim_temp "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_1/Exp4_Segment.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_2/Exp4_Segment.data/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | 6d6f64655f636f756e7465727c4953454d6f6465:1 4 | eof: 5 | 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#-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/isim/work/@method_1_@memory_m.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tizee/Computer-Organization-and-Architecture/HEAD/Experiment/Exp5_MemoryIP/isim/work/@method_1_@memory_m.sdb -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim/temp/@c@l@l@a@adder@m_test.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tizee/Computer-Organization-and-Architecture/HEAD/Experiment/Exp2_CLAAdderM/isim/temp/@c@l@l@a@adder@m_test.sdb -------------------------------------------------------------------------------- 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vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/simulation/functional/simulate_mti.sh: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/simulation/timing/simulate_mti.bat: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim/ALU_TEST_isim_beh.exe.sim/tmp_save/_1: -------------------------------------------------------------------------------- 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All rights reserved. 3 | 4 | Fri Apr 20 14:40:21 2018 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim/Segment_M_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tizee/Computer-Organization-and-Architecture/HEAD/Experiment/Exp4_Segment/isim/Segment_M_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/coregen.log: -------------------------------------------------------------------------------- 1 | INFO:sim:172 - Generating IP... 2 | Applying current project options... 3 | Finished applying current project options. 4 | Cancelled executing Tcl generator. 5 | Wrote CGP file for project 'RAM_B'. 6 | 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All rights reserved. 3 | 4 | Fri Apr 20 14:40:29 2018 5 | 6 | drc -z fulladderM.ncd fulladderM.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/isim/fulladderM_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tizee/Computer-Organization-and-Architecture/HEAD/Experiment/Exp1_FullAdderM/isim/fulladderM_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/cllaadderm.drc: -------------------------------------------------------------------------------- 1 | Release 14.7 Drc P.20131013 (nt64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Fri Apr 20 15:35:29 2018 5 | 6 | drc -z CLLAAdderM.ncd CLLAAdderM.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim/ALU_TEST_isim_beh.exe.sim/work/m_00000000000044912214_0596150753.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tizee/Computer-Organization-and-Architecture/HEAD/Experiment/Exp3_ALU/isim/ALU_TEST_isim_beh.exe.sim/work/m_00000000000044912214_0596150753.didat -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim/ALU_TEST_isim_beh.exe.sim/work/m_00000000000054293371_4092549402.didat: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/isim/fulladderM_test_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tizee/Computer-Organization-and-Architecture/HEAD/Experiment/Exp1_FullAdderM/isim/fulladderM_test_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_2/Exp4_Segment.data/constrs_1/designprops.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = Verilog 3 | SET device = xc6slx16 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = csg324 7 | SET speedgrade = -3 8 | SET verilogsim = true 9 | SET vhdlsim = false 10 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM_test_isim_beh.exe" -prj "E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM_test_beh.prj" "work.CLLAAdderM_test" "work.glbl" 2 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_2/Exp3.data/runs/runs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent RAM_B_exdes 4 | -p xc6slx16-csg324-3 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn RAM_B_exdes 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "D:/COAexp-master/COAexp-master/Exp1_FullAdderM/fulladderM_test_isim_beh.exe" -prj "D:/COAexp-master/COAexp-master/Exp1_FullAdderM/fulladderM_test_beh.prj" "work.fulladderM_test" "work.glbl" 2 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Computer Organization and Architecture 2 | ## 所用教材 3 | - 计算机组成原理与系统结构(第二版) 包健版 4 | - 计算机组成原理实验 5 | ## Note 6 | 这是我个人的课程归档项目仓库，包含slides，notes，experiments，往年的试题，实验报告 7 | ## Todo List 8 | - ~~整理Problem Set~~ 9 | - ~~整理Resources~~ 10 | - ~~Slides归档~~ 11 | - ~~习题解答~~ 12 | 13 | ## Resources 14 | **UPDATE: 2018-05-07 01:17:29** 15 | USTC的计组相关的PPT 16 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000100000100000 2 | 00000000011000110010000000100000 3 | 00000000000000010000111111111111 4 | 00100000000000000110011110001001 5 | 11111111111111110000000000000000 6 | 00000000000000001111111111111111 7 | 10001000100010001000100010001000 8 | 10011001100110011001100110011001 9 | 10101010101010101010101010101010 10 | 10111011101110111011101110111011 11 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLAAAdderM.ucf: -------------------------------------------------------------------------------- 1 | NET "A[0]" LOC = 'T10' ; 2 | NET "A[1]"LOC ='T9' ; 3 | NET "A[2]"LOC ='V9' ; 4 | NET "A[3]"LOC ='M8' ; 5 | NET "B[0]"LOC ='N8' ; 6 | NET "B[1]"LOC ='U8' ; 7 | NET "B[2]"LOC ='V8' ; 8 | NET "B[3]"LOC = 'T5'; 9 | NET "CIN" LOC = 'C4'; 10 | NET "COUT" LOC = 'U16'; 11 | 12 | NET "F[0]" LOC = 'T11' ; 13 | NET "F[1]" LOC = 'R11' ; 14 | NET "F[2]" LOC = 'N11' ; 15 | NET "F[3]" LOC = 'M11' ; 16 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_2/Exp3.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: E:\Exp_MemoryIP\M1_Test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/Exp_MemoryIP/M1_Test_isim_beh.wdb 3 | ISim P.20131013 (signature 0x7708f090) 4 | This is a Full version of ISim. 5 | Time resolution is 1 ps 6 | # onerror resume 7 | # wave add / 8 | # run 1000 ns 9 | Simulator is doing circuit initialization process. 10 | Finished circuit initialization process. 11 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: E:\Exp4_Segment\Segment_Test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/Exp4_Segment/Segment_Test_isim_beh.wdb 3 | ISim P.20131013 (signature 0x7708f090) 4 | This is a Full version of ISim. 5 | Time resolution is 1 ps 6 | # onerror resume 7 | # wave add / 8 | # run 1000 ns 9 | Simulator is doing circuit initialization process. 10 | Finished circuit initialization process. 11 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.7 - par P.20131013 (nt64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Fri Apr 27 14:58:22 2018 5 | 6 | All signals are completely routed. 7 | 8 | WARNING:ParHelpers:361 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC 9 | warnings. 10 | 11 | A<0>_IBUF 12 | A<1>_IBUF 13 | B<0>_IBUF 14 | B<1>_IBUF 15 | Cin_IBUF 16 | 17 | 18 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: E:\CCOAexp\Experiment\Exp3_ALU\ALU_TEST_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/CCOAexp/Experiment/Exp3_ALU/ALU_TEST_isim_beh.wdb 3 | ISim P.20131013 (signature 0x7708f090) 4 | This is a Full version of ISim. 5 | Time resolution is 1 ps 6 | # onerror resume 7 | # wave add / 8 | # run 1000 ns 9 | Simulator is doing circuit initialization process. 10 | Finished circuit initialization process. 11 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: E:\CCOAexp\Experiment\Exp2_CLAAdderM\CLLAAdderM_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM_test_isim_beh.wdb 3 | ISim P.20131013 (signature 0x7708f090) 4 | This is a Full version of ISim. 5 | Time resolution is 1 ps 6 | # onerror resume 7 | # wave add / 8 | # run 1000 ns 9 | Simulator is doing circuit initialization process. 10 | Finished circuit initialization process. 11 | -------------------------------------------------------------------------------- /Notes/Review.md: -------------------------------------------------------------------------------- 1 | # 计组复习纲要 2 | Written by Tizee 3 | ## 复习目标 4 | - 应试 5 | - 加深计组的理解 6 | ## 复习内容 7 | - 硬件基础 8 | - 组成原理 9 | - 信息编码与数据表示 10 | - 运算方法和运算器 11 | - 存储体系 12 | - 指令系统 13 | - 控制器 14 | - 输入输出系统 15 | 16 | ## 复习方法 17 | ### 回顾习题 18 | - 课后习题 19 | - 往年考试习题 20 | 21 | 利用清单评价习题回顾效果 22 | ### interleave自测 23 | 发现难点及熟悉应试 24 | ## 复习难点 25 | ### 对难点的理解 26 | 所谓难点不过是对于自己个人学习进展而言没有理解透彻的部分，可能是概念上analogy不够恰当，也可能是不能熟练将将概念知识迁移到题目或实际的环境中运用。 27 | ### 难点列举 28 | - 存储体系 29 | - 指令系统 30 | - 控制器 31 | - 输入输出系统 32 | 33 | 34 | 35 | 36 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: D:\COAexp-master\COAexp-master\Exp1_FullAdderM\fulladderM_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb D:/COAexp-master/COAexp-master/Exp1_FullAdderM/fulladderM_test_isim_beh.wdb 3 | ISim P.20131013 (signature 0x7708f090) 4 | This is a Full version of ISim. 5 | Time resolution is 1 ps 6 | # onerror resume 7 | # wave add / 8 | # run 1000 ns 9 | Simulator is doing circuit initialization process. 10 | Finished circuit initialization process. 11 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map P.20131013 on Fri Apr 20 14:40:15 2018 3 | //! ************************************************************************** 4 | 5 | SCHEMATIC START; 6 | COMP "Cout" LOCATE = SITE "T11" LEVEL 1; 7 | COMP "A" LOCATE = SITE "T10" LEVEL 1; 8 | COMP "B" LOCATE = SITE "T9" LEVEL 1; 9 | COMP "F" LOCATE = SITE "R11" LEVEL 1; 10 | COMP "Cin" LOCATE = SITE "V9" LEVEL 1; 11 | SCHEMATIC END; 12 | 13 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Generating IP... 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_2/Exp3.data/runs/impl_1.psg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | ISE Defaults, including packing registers in IOs off 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_2/planAhead.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # PlanAhead v14.7 (64-bit) 3 | # Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013 4 | # Start of session at: Fri May 18 14:11:04 2018 5 | # Process ID: 4608 6 | # Log file: E:/CCOAexp/Experiment/Exp3_ALU/planAhead_run_2/planAhead.log 7 | # Journal file: E:/CCOAexp/Experiment/Exp3_ALU/planAhead_run_2/planAhead.jou 8 | #----------------------------------------------------------- 9 | start_gui 10 | source E:/CCOAexp/Experiment/Exp3_ALU/pa.fromNetlist.tcl 11 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_M.ucf: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Generated physical constraints 3 | 4 | NET "AB_SW[2]" LOC = T10; 5 | NET "AB_SW[1]" LOC = T9; 6 | NET "AB_SW[0]" LOC = V9; 7 | NET "ALU_OP[2]" LOC = M8; 8 | NET "ALU_OP[1]" LOC = N8; 9 | NET "ALU_OP[0]" LOC = U8; 10 | NET "F_LED_SW[2]" LOC = V8; 11 | NET "F_LED_SW[1]" LOC = T5; 12 | NET "F_LED_SW[0]" LOC = B8; 13 | NET "LED[7]" LOC = U16; 14 | NET "LED[6]" LOC = V16; 15 | NET "LED[5]" LOC = U15; 16 | NET "LED[4]" LOC = V15; 17 | NET "LED[3]" LOC = M11; 18 | NET "LED[2]" LOC = N11; 19 | NET "LED[1]" LOC = R11; 20 | NET "LED[0]" LOC = T11; 21 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_1/Exp3.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_1/Exp4_Segment.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_1/planAhead.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # PlanAhead v14.7 (64-bit) 3 | # Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013 4 | # Start of session at: Fri Jun 01 14:54:24 2018 5 | # Process ID: 3460 6 | # Log file: E:/Exp4_Segment/Exp4_Segment/planAhead_run_1/planAhead.log 7 | # Journal file: E:/Exp4_Segment/Exp4_Segment/planAhead_run_1/planAhead.jou 8 | #----------------------------------------------------------- 9 | start_gui 10 | source E:/Exp4_Segment/Exp4_Segment/pa.fromHdl.tcl 11 | update_compile_order -fileset sim_1 12 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_2/Exp4_Segment.data/sim_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_2/Exp3.data/constrs_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | "D:\COAexp-master\COAexp-master\Exp1_FullAdderM\fulladderM.v" Line 28: Redeclaration of ansi port Cin is not allowed 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | "D:/COAexp-master/COAexp-master/Exp1_FullAdderM/fulladderM.v" Line 28: Redeclaration of ansi port Cin is not allowed 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/pa.fromNetlist.tcl: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Launch Script for Post-Synthesis floorplanning, created by Project Navigator 3 | 4 | create_project -name Exp3 -dir "E:/CCOAexp/Experiment/Exp3_ALU/planAhead_run_3" -part xc6slx16csg324-3 5 | set_property design_mode GateLvl [get_property srcset [current_run -impl]] 6 | set_property edif_top_file "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.ngc" [ get_property srcset [ current_run ] ] 7 | add_files -norecurse { {E:/CCOAexp/Experiment/Exp3_ALU} } 8 | set_property target_constrs_file "ALU_M.ucf" [current_fileset -constrset] 9 | add_files [list {ALU_M.ucf}] -fileset [get_property constrset [current_run]] 10 | link_design 11 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_1/Exp4_Segment.data/constrs_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 RAM_B 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[5:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[31:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[31:0] 24 | PINATTR Polarity OUT 25 | 26 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_M.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "E:/CCOAexp/Exp3/ALU_M.xst" -ofn "E:/CCOAexp/Exp3/ALU_M.syr" 2 | xst -intstyle ise -ifn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.xst" -ofn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.syr" 3 | xst -intstyle ise -ifn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.xst" -ofn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.syr" 4 | xst -intstyle ise -ifn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.xst" -ofn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.syr" 5 | xst -intstyle ise -ifn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.xst" -ofn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.syr" 6 | xst -intstyle ise -ifn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.xst" -ofn "E:/CCOAexp/Experiment/Exp3_ALU/ALU_M.syr" 7 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_1/Exp4_Segment.data/sources_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/simulation/timing/wave_ncsim.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | window new WaveWindow -name "Waves for BMG Example Design" 10 | waveform using "Waves for BMG Example Design" 11 | 12 | 13 | waveform add -signals /RAM_B_tb/status 14 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/CLKA 15 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/ADDRA 16 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/DINA 17 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/WEA 18 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/DOUTA 19 | console submit -using simulator -wait no "run" 20 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/Segment_M.ucf: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Generated physical constraints 3 | 4 | NET "LED[7]" LOC = T11; 5 | NET "LED[6]" LOC = R11; 6 | NET "LED[5]" LOC = N11; 7 | NET "LED[4]" LOC = M11; 8 | NET "LED[3]" LOC = V15; 9 | NET "LED[1]" LOC = V16; 10 | NET "LED[0]" LOC = U16; 11 | NET "LED[2]" LOC = U15; 12 | NET "Switch_Address[4]" LOC = T10; 13 | NET "Switch_Address[3]" LOC = T9; 14 | NET "Switch_Address[1]" LOC = M8; 15 | NET "Switch_Address[0]" LOC = N8; 16 | NET "Switch_Address[2]" LOC = V9; 17 | NET "Switch_Select[1]" LOC = U8; 18 | NET "Switch_Select[0]" LOC = V8; 19 | NET "Switch_WriteReg" LOC = T5; 20 | NET "Button_Clk" LOC = C9; 21 | NET "Button_Reset" LOC = D9; 22 | NET "Button_AB" LOC = A9; 23 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/isim/ALU_TEST_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | ALU_TEST_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 1348 6 | 7 | Fri May 18 14:19:20 2018 8 | 9 | 10 | Elaboration Time: 0.0468 sec 11 | 12 | Current Memory Usage: 674.75 Meg 13 | 14 | Total Signals : 31 15 | Total Nets : 128 16 | Total Signal Drivers : 14 17 | Total Blocks : 6 18 | Total Primitive Blocks : 4 19 | Total Processes : 19 20 | Total Traceable Variables : 30 21 | Total Scalar Nets and Variables : 363 22 | 23 | Total Simulation Time: 0.202802 sec 24 | 25 | Current Memory Usage: 674.75 Meg 26 | 27 | Fri May 18 14:22:02 2018 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/simulation/functional/wave_ncsim.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | window new WaveWindow -name "Waves for BMG Example Design" 11 | waveform using "Waves for BMG Example Design" 12 | 13 | waveform add -signals /RAM_B_tb/status 14 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/CLKA 15 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/ADDRA 16 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/DINA 17 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/WEA 18 | waveform add -signals /RAM_B_tb/RAM_B_synth_inst/bmg_port/DOUTA 19 | 20 | console submit -using simulator -wait no "run" 21 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim/Segment_M_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | Segment_M_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 2058 6 | 7 | Fri May 25 15:56:21 2018 8 | 9 | 10 | Elaboration Time: 0.0624 sec 11 | 12 | Current Memory Usage: 674.746 Meg 13 | 14 | Total Signals : 22 15 | Total Nets : 127 16 | Total Signal Drivers : 7 17 | Total Blocks : 2 18 | Total Primitive Blocks : 2 19 | Total Processes : 9 20 | Total Traceable Variables : 20 21 | Total Scalar Nets and Variables : 1263 22 | 23 | Total Simulation Time: 0.156001 sec 24 | 25 | Current Memory Usage: 674.746 Meg 26 | 27 | Fri May 25 15:56:39 2018 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/isim/M1_Test_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | M1_Test_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 3100 6 | 7 | Fri Jun 01 15:41:16 2018 8 | 9 | 10 | Elaboration Time: 0.124801 sec 11 | 12 | Current Memory Usage: 674.746 Meg 13 | 14 | Total Signals : 18 15 | Total Nets : 87 16 | Total Signal Drivers : 10 17 | Total Blocks : 3 18 | Total Primitive Blocks : 2 19 | Total Processes : 13 20 | Total Traceable Variables : 24 21 | Total Scalar Nets and Variables : 2289 22 | 23 | Total Simulation Time: 0.858006 sec 24 | 25 | Current Memory Usage: 674.746 Meg 26 | 27 | Fri Jun 01 15:45:06 2018 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim/CLLAAdderM_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | CLLAAdderM_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 6902 6 | 7 | Fri Apr 27 15:53:14 2018 8 | 9 | 10 | Elaboration Time: 0.0624 sec 11 | 12 | Current Memory Usage: 674.746 Meg 13 | 14 | Total Signals : 54 15 | Total Nets : 49 16 | Total Signal Drivers : 35 17 | Total Blocks : 6 18 | Total Primitive Blocks : 5 19 | Total Processes : 36 20 | Total Traceable Variables : 21 21 | Total Scalar Nets and Variables : 140 22 | 23 | Total Simulation Time: 0.078 sec 24 | 25 | Current Memory Usage: 674.746 Meg 26 | 27 | Fri Apr 27 15:53:20 2018 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/isim/Segment_Test_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | Segment_Test_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 2094 6 | 7 | Fri May 25 16:04:55 2018 8 | 9 | 10 | Elaboration Time: 0.0624 sec 11 | 12 | Current Memory Usage: 674.75 Meg 13 | 14 | Total Signals : 24 15 | Total Nets : 127 16 | Total Signal Drivers : 14 17 | Total Blocks : 3 18 | Total Primitive Blocks : 2 19 | Total Processes : 17 20 | Total Traceable Variables : 27 21 | Total Scalar Nets and Variables : 1313 22 | 23 | Total Simulation Time: 0.0624 sec 24 | 25 | Current Memory Usage: 989.323 Meg 26 | 27 | Fri May 25 16:05:46 2018 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/pa.fromHdl.tcl: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator 3 | 4 | create_project -name Exp4_Segment -dir "E:/Exp4_Segment/Exp4_Segment/planAhead_run_2" -part xc6slx16csg324-3 5 | set_param project.pinAheadLayout yes 6 | set srcset [get_property srcset [current_run -impl]] 7 | set_property target_constrs_file "Segment_M.ucf" [current_fileset -constrset] 8 | set hdlfile [add_files [list {Segment_Top.v}]] 9 | set_property file_type Verilog $hdlfile 10 | set_property library work $hdlfile 11 | set_property top Segment_Top $srcset 12 | add_files [list {Segment_M.ucf}] -fileset [get_property constrset [current_run]] 13 | open_rtl_design -part xc6slx16csg324-3 14 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/isim/fulladderM_test_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | fulladderM_test_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 5309 6 | 7 | Fri Apr 27 14:23:27 2018 8 | 9 | 10 | Elaboration Time: 0.0624 sec 11 | 12 | Current Memory Usage: 674.746 Meg 13 | 14 | Total Signals : 24 15 | Total Nets : 22 16 | Total Signal Drivers : 14 17 | Total Blocks : 3 18 | Total Primitive Blocks : 2 19 | Total Processes : 16 20 | Total Traceable Variables : 21 21 | Total Scalar Nets and Variables : 105 22 | 23 | Total Simulation Time: 0.421202 sec 24 | 25 | Current Memory Usage: 832.033 Meg 26 | 27 | Fri Apr 27 14:25:06 2018 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/isim/CLLAAdderM_test_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | CLLAAdderM_test_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 1186 6 | 7 | Fri May 18 13:59:29 2018 8 | 9 | 10 | Elaboration Time: 0.109201 sec 11 | 12 | Current Memory Usage: 674.746 Meg 13 | 14 | Total Signals : 20 15 | Total Nets : 27 16 | Total Signal Drivers : 10 17 | Total Blocks : 3 18 | Total Primitive Blocks : 2 19 | Total Processes : 11 20 | Total Traceable Variables : 21 21 | Total Scalar Nets and Variables : 116 22 | 23 | Total Simulation Time: 0.514804 sec 24 | 25 | Current Memory Usage: 832.033 Meg 26 | 27 | Fri May 18 14:01:30 2018 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/summary.log: -------------------------------------------------------------------------------- 1 | 2 | User Configuration 3 | ------------------------------------- 4 | Algorithm : Minimum_Area 5 | Memory Type : Single_Port_RAM 6 | Port A Read Width : 32 7 | Port A Write Width : 32 8 | Memory Depth : 64 9 | -------------------------------------------------------------- 10 | 11 | Block RAM resource(s) (9K BRAMs) : 1 12 | Block RAM resource(s) (18K BRAMs) : 0 13 | -------------------------------------------------------------- 14 | Clock A Frequency : 100 15 | Port A Enable Rate : 100 16 | Port A Write Rate : 50 17 | ---------------------------------------------------------- 18 | Estimated Power for IP : 2.878163 mW 19 | ---------------------------------------------------------- 20 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_2/Exp3.data/sources_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead.ngc2edif.log: -------------------------------------------------------------------------------- 1 | Release 14.7 - ngc2edif P.20131013 (nt64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | Reading design ALU_M.ngc ... 4 | WARNING:NetListWriters:298 - No output is written to ALU_M.xncf, ignored. 5 | Processing design ... 6 | Preping design's networks ... 7 | Preping design's macros ... 8 | WARNING:NetListWriters:306 - Signal bus A<31 : 0> on block ALU_M is not 9 | reconstructed, because there are some missing bus signals. 10 | WARNING:NetListWriters:306 - Signal bus 11 | A1/Mcompar_A[31]_B[31]_LessThan_8_o_cy<15 : 0> on block ALU_M is not 12 | reconstructed, because there are some missing bus signals. 13 | finished :Prep 14 | Writing EDIF netlist file ALU_M.edif ... 15 | ngc2edif: Total memory usage is 86168 kilobytes 16 | 17 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 14.7 - WebTalk (P.20131013) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | Project Information 5 | -------------------- 6 | ProjectID=BA88C84FD4624AF89C21090C22C18A2D 7 | ProjectIteration=2 8 | 9 | WebTalk Summary 10 | ---------------- 11 | INFO:WebTalk:1 - WebTalk is enabled because you are using a WebPACK license. 12 | 13 | INFO:WebTalk:8 - WebTalk Install setting is ON. 14 | INFO:WebTalk:6 - WebTalk User setting is ON. 15 | 16 | INFO:WebTalk:5 - E:/CCOAexp/Exp2CLAAdderM/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html 17 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 14.7 - WebTalk (P.20131013) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | Project Information 5 | -------------------- 6 | ProjectID=5B5847E205004FFC8FFB73BAC3E63A47 7 | ProjectIteration=1 8 | 9 | WebTalk Summary 10 | ---------------- 11 | INFO:WebTalk:1 - WebTalk is enabled because you are using a WebPACK license. 12 | 13 | INFO:WebTalk:8 - WebTalk Install setting is ON. 14 | INFO:WebTalk:6 - WebTalk User setting is ON. 15 | 16 | INFO:WebTalk:5 - E:/CCOAexp/Exp1_FullAdderM/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html 17 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_2/Exp4_Segment.data/sources_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file "E:/Exp_MemoryIP/RAM_B_Test.v" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file "E:/Exp_MemoryIP/ipcore_dir/RAM_B.v" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file "E:/Exp_MemoryIP/ipcore_dir/tmp/_cg/RAM_B.v" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file "D:/COAexp-master/COAexp-master/Exp1_FullAdderM/fulladderM.v" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_1/Exp3.data/sources_1/ports.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_1/Exp3.data/constrs_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_2/Exp4_Segment.data/constrs_1/fileset.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map P.20131013 on Fri Apr 27 14:58:14 2018 3 | //! ************************************************************************** 4 | 5 | SCHEMATIC START; 6 | COMP "A<0>" LOCATE = SITE "T10" LEVEL 1; 7 | COMP "A<1>" LOCATE = SITE "T9" LEVEL 1; 8 | COMP "A<2>" LOCATE = SITE "V9" LEVEL 1; 9 | COMP "A<3>" LOCATE = SITE "M8" LEVEL 1; 10 | COMP "B<0>" LOCATE = SITE "N8" LEVEL 1; 11 | COMP "Cout" LOCATE = SITE "U16" LEVEL 1; 12 | COMP "B<1>" LOCATE = SITE "U8" LEVEL 1; 13 | COMP "B<2>" LOCATE = SITE "V8" LEVEL 1; 14 | COMP "B<3>" LOCATE = SITE "T5" LEVEL 1; 15 | COMP "F<0>" LOCATE = SITE "T11" LEVEL 1; 16 | COMP "F<1>" LOCATE = SITE "R11" LEVEL 1; 17 | COMP "F<2>" LOCATE = SITE "N11" LEVEL 1; 18 | COMP "F<3>" LOCATE = SITE "M11" LEVEL 1; 19 | COMP "Cin" LOCATE = SITE "C4" LEVEL 1; 20 | SCHEMATIC END; 21 | 22 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "E:/CCOAexp/Exp1_FullAdderM/fulladderM.xst" -ofn "E:/CCOAexp/Exp1_FullAdderM/fulladderM.syr" 2 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc FullAdderM_C.ucf -p xc6slx16-csg324-3 fulladderM.ngc fulladderM.ngd 3 | map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o fulladderM_map.ncd fulladderM.ngd fulladderM.pcf 4 | par -w -intstyle ise -ol high -mt off fulladderM_map.ncd fulladderM.ncd fulladderM.pcf 5 | trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml fulladderM.twx fulladderM.ncd -o fulladderM.twr fulladderM.pcf -ucf FullAdderM_C.ucf 6 | bitgen -intstyle ise -f fulladderM.ut fulladderM.ncd 7 | xst -intstyle ise -ifn "D:/COAexp-master/COAexp-master/Exp1_FullAdderM/fulladderM.xst" -ofn "D:/COAexp-master/COAexp-master/Exp1_FullAdderM/fulladderM.syr" 8 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_M.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:48:51 05/11/2018 7 | // Design Name: 8 | // Module Name: ALU_M 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ALU_M(ALU_OP,AB_SW,F_LED_SW,LED 22 | ); 23 | input[2:0] ALU_OP,AB_SW,F_LED_SW; 24 | output[7:0] LED; 25 | 26 | wire[2:0] AB_SW,F_LED_SW,ALU_OP; 27 | wire[31:0] A,B,F; 28 | 29 | wire ZF,OF; 30 | wire[7:0] LED; 31 | Choice_M C1(AB_SW,A,B); 32 | ALU_TOP A1(A,B,F,ZF,OF,ALU_OP); 33 | CLED_M C2(F_LED_SW,LED,F,ZF,OF); 34 | 35 | 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_2/Exp4_Segment.data/sources_1/ports.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file "E:/CCOAexp/Experiment/Exp1_FullAdderM/fulladderM.v" into library work 12 | 13 | 14 | Analyzing Verilog file "E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM.v" into library work 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/RAM_B_Test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:03:52 06/01/2018 7 | // Design Name: 8 | // Module Name: RAM_B_Test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module RAM_B_Test(input [7:2]Mem_Addr, 22 | input [1:0]Select, 23 | input Mem_Write, 24 | input Clk, 25 | output [7:0]LED); 26 | 27 | reg[31:0] M_W_Data; 28 | reg[31:0] M_R_Data; 29 | 30 | 31 | 32 | RAM_B Test( 33 | .clka(Clk), // input clka 34 | .wea(Mem_Write), // input [0 : 0] wea 35 | .addra(Mem_Addr[7:2]), // input [5 : 0] addra 36 | .dina(M_W_Data), // input [31 : 0] dina 37 | .douta(M_R_Data) // output [31 : 0] douta 38 | ); 39 | endmodule 40 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 13:48:20 05/11/2018 6 | -- Design Name: 7 | -- Module Name: ALU - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity ALU is 33 | end ALU; 34 | 35 | architecture Behavioral of ALU is 36 | 37 | begin 38 | 39 | 40 | end Behavioral; 41 | 42 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/pa.fromHdl.tcl: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator 3 | 4 | create_project -name Exp3 -dir "E:/CCOAexp/Experiment/Exp3_ALU/planAhead_run_1" -part xc6slx16csg324-3 5 | set_param project.pinAheadLayout yes 6 | set srcset [get_property srcset [current_run -impl]] 7 | set_property target_constrs_file "ALU_M.ucf" [current_fileset -constrset] 8 | set hdlfile [add_files [list {CLED_M.v}]] 9 | set_property file_type Verilog $hdlfile 10 | set_property library work $hdlfile 11 | set hdlfile [add_files [list {Choice_M.v}]] 12 | set_property file_type Verilog $hdlfile 13 | set_property library work $hdlfile 14 | set hdlfile [add_files [list {ALU_TOP.v}]] 15 | set_property file_type Verilog $hdlfile 16 | set_property library work $hdlfile 17 | set hdlfile [add_files [list {ALU_M.v}]] 18 | set_property file_type Verilog $hdlfile 19 | set_property library work $hdlfile 20 | set_property top ALU_M $srcset 21 | add_files [list {ALU_M.ucf}] -fileset [get_property constrset [current_run]] 22 | open_rtl_design -part xc6slx16csg324-3 23 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/Method_1_Memory_m.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:12:28 06/01/2018 7 | // Design Name: 8 | // Module Name: Method_1_Memory_m 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Method_1_Memory_m( 22 | input wire Mem_Read, 23 | input wire Mem_Write, 24 | input wire[7:0]Mem_Addr, 25 | input wire[31:0]M_W_Data, 26 | output reg[31:0]M_R_Data 27 | ); 28 | reg[63:0] Memory[0:31]; 29 | always@(*) 30 | begin 31 | if(Mem_Read==1&&Mem_Write==0) 32 | begin 33 | M_R_Data=Memory[Mem_Addr]; 34 | end; 35 | if(Mem_Read==0&&Mem_Write==1) 36 | begin 37 | Memory[Mem_Addr]=M_W_Data; 38 | end 39 | end 40 | 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/CLED_M.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:47:30 05/11/2018 7 | // Design Name: 8 | // Module Name: CLED_M 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLED_M( 22 | input[2:0] F_LED_SW, 23 | output[7:0] LED, 24 | input[31:0] F, 25 | input ZF, 26 | input OF 27 | ); 28 | reg[7:0] LED; 29 | wire[31:0] F; 30 | wire[2:0] F_LED_SW; 31 | wire ZF,OF; 32 | // assign F = 32'h1234_5678; 33 | always @(*) 34 | begin 35 | case(F_LED_SW) 36 | 3'b000:LED=F[7:0]; 37 | 3'b001:LED=F[15:8]; 38 | 3'b010:LED=F[23:16]; 39 | 3'b011:LED=F[31:24]; 40 | default:begin LED[7]= ZF; LED[0]=OF;LED[6:1]=6'b0;end 41 | endcase 42 | end 43 | 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_1/Exp3.ppr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/fuse.log: -------------------------------------------------------------------------------- 1 | Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o E:/Exp_MemoryIP/M1_Test_isim_beh.exe -prj E:/Exp_MemoryIP/M1_Test_beh.prj work.M1_Test work.glbl 2 | ISim P.20131013 (signature 0x7708f090) 3 | Number of CPUs detected in this system: 8 4 | Turning on mult-threading, number of parallel sub-compilation jobs: 16 5 | Determining compilation order of HDL files 6 | Analyzing Verilog file "E:/Exp_MemoryIP/Method_1_Memory_m.v" into library work 7 | Analyzing Verilog file "E:/Exp_MemoryIP/M1_Test.v" into library work 8 | Analyzing Verilog file "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work 9 | Starting static elaboration 10 | Completed static elaboration 11 | Compiling module Method_1_Memory_m 12 | Compiling module M1_Test 13 | Compiling module glbl 14 | Time Resolution for simulation is 1ps. 15 | Waiting for 1 sub-compilation(s) to finish... 16 | Compiled 3 Verilog Units 17 | Built simulation executable E:/Exp_MemoryIP/M1_Test_isim_beh.exe 18 | Fuse Memory Usage: 29424 KB 19 | Fuse CPU Usage: 452 ms 20 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/fuse.log: -------------------------------------------------------------------------------- 1 | Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o E:/Exp4_Segment/Segment_Test_isim_beh.exe -prj E:/Exp4_Segment/Segment_Test_beh.prj work.Segment_Test work.glbl 2 | ISim P.20131013 (signature 0x7708f090) 3 | Number of CPUs detected in this system: 8 4 | Turning on mult-threading, number of parallel sub-compilation jobs: 16 5 | Determining compilation order of HDL files 6 | Analyzing Verilog file "E:/Exp4_Segment/Segment_M.v" into library work 7 | Analyzing Verilog file "E:/Exp4_Segment/Segment_Test.v" into library work 8 | Analyzing Verilog file "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work 9 | Starting static elaboration 10 | Completed static elaboration 11 | Compiling module Segment_M 12 | Compiling module Segment_Test 13 | Compiling module glbl 14 | Time Resolution for simulation is 1ps. 15 | Waiting for 1 sub-compilation(s) to finish... 16 | Compiled 3 Verilog Units 17 | Built simulation executable E:/Exp4_Segment/Segment_Test_isim_beh.exe 18 | Fuse Memory Usage: 29428 KB 19 | Fuse CPU Usage: 373 ms 20 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_1/Exp4_Segment.ppr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/planAhead_run_2/Exp4_Segment.ppr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/simulation/timing/wave_mti.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | onerror {resume} 10 | quietly WaveActivateNextPane {} 0 11 | 12 | 13 | add wave -noupdate /RAM_B_tb/status 14 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/CLKA 15 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/ADDRA 16 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/DINA 17 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/WEA 18 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/DOUTA 19 | TreeUpdate [SetDefaultTree] 20 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} 21 | configure wave -namecolwidth 150 22 | configure wave -valuecolwidth 100 23 | configure wave -justifyvalue left 24 | configure wave -signalnamewidth 1 25 | configure wave -snapdistance 10 26 | configure wave -datasetprefix 0 27 | configure wave -rowmargin 4 28 | configure wave -childrowmargin 2 29 | configure wave -gridoffset 0 30 | configure wave -gridperiod 1 31 | configure wave -griddelta 40 32 | configure wave -timeline 0 33 | configure wave -timelineunits ps 34 | update 35 | WaveRestoreZoom {0 ps} {9464063 ps} 36 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/simulation/functional/wave_mti.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | onerror {resume} 10 | quietly WaveActivateNextPane {} 0 11 | 12 | add wave -noupdate /RAM_B_tb/status 13 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/CLKA 14 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/ADDRA 15 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/DINA 16 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/WEA 17 | add wave -noupdate /RAM_B_tb/RAM_B_synth_inst/bmg_port/DOUTA 18 | 19 | TreeUpdate [SetDefaultTree] 20 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} 21 | configure wave -namecolwidth 197 22 | configure wave -valuecolwidth 106 23 | configure wave -justifyvalue left 24 | configure wave -signalnamewidth 1 25 | configure wave -snapdistance 10 26 | configure wave -datasetprefix 0 27 | configure wave -rowmargin 4 28 | configure wave -childrowmargin 2 29 | configure wave -gridoffset 0 30 | configure wave -gridperiod 1 31 | configure wave -griddelta 40 32 | configure wave -timeline 0 33 | configure wave -timelineunits ps 34 | update 35 | WaveRestoreZoom {0 ps} {9464063 ps} 36 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/planAhead_run_2/Exp3.ppr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". 9 | 10 | 11 | The Clock Report is not displayed in the non timing-driven mode. 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No timing constraints found, doing default enumeration. 9 | 10 | To improve timing, see the Timing Closure User Guide (UG612). 11 | 12 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 13 | 14 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.bld: -------------------------------------------------------------------------------- 1 | Release 14.7 ngdbuild P.20131013 (nt64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe 5 | -intstyle ise -dd _ngo -nt timestamp -uc FullAdderM_C.ucf -p xc6slx16-csg324-3 6 | fulladderM.ngc fulladderM.ngd 7 | 8 | Reading NGO file "E:/CCOAexp/Exp1_FullAdderM/fulladderM.ngc" ... 9 | Gathering constraint information from source properties... 10 | Done. 11 | 12 | Annotating constraints to design from ucf file "FullAdderM_C.ucf" ... 13 | Resolving constraint associations... 14 | Checking Constraint Associations... 15 | Done... 16 | 17 | Checking expanded design ... 18 | 19 | Partition Implementation Status 20 | ------------------------------- 21 | 22 | No Partitions were found in this design. 23 | 24 | ------------------------------- 25 | 26 | NGDBUILD Design Results Summary: 27 | Number of errors: 0 28 | Number of warnings: 0 29 | 30 | Total memory usage is 165480 kilobytes 31 | 32 | Writing NGD file "fulladderM.ngd" ... 33 | Total REAL time to NGDBUILD completion: 2 sec 34 | Total CPU time to NGDBUILD completion: 2 sec 35 | 36 | Writing NGDBUILD log file "fulladderM.bld"... 37 | -------------------------------------------------------------------------------- /Experiment/Exp1_FullAdderM/fulladderM.ngr: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.6e 3 | $3fx54=52@D[YY4Kauc?5?69m2Bf|h6:6=08;Ecwe97992L<7AAHIBCO3>Kg{UM=55Bxnp\W47d3Y$9<<=>001\H1=WI[^j7]GA_CWPMA^e3YCESO[\N@OF=>VHZ]UOMYOm;QMQPZTB[\F_?6\[L99QPIYSQYO=7_k|umv1?V733ZCQIk5\OTP@AZ@NDLDJAHj4SNWQG@YKAGOEN95[YQG:?SOB_V^R\H;4WHFWL4b~d>zfs=;#<-bqd77243qeyqMN1d9CD}4>2O09644=9:9nhnl5f3c5k41281e>:49;%06>7454>2;307`bdj3l9m;5k2`83>4<6sZ<1>54>2;307`bdj3l9m;5yF0:94?7=93:p_;4=8;31>454mmii6k1>v*>d;;8j4c=9<1v(5;c33>5<4290;wA<;:6y'5<<5k2.::7o4$0595d=i9j097c<>:09'5a<>3g;n6?84}%3e>46!722j1e=94>;:kg>5<#9<0h7c?;:198k4g=831vn1;v*>9;0`?!712h1/=:4>a:l2g?4d;;8j4c=:<1v(5$079g>h6<3;07dj50;&21?e1<65`1`83>>{t?3:1>vP8;<33>g=z{;0;6?uQ2:?25?b54 2 | 7 | 8 | No timing constraints found, doing default enumeration. 9 | 10 | To improve timing, see the Timing Closure User Guide (UG612). 11 | 12 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 13 | 14 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/implement/implement.sh: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | #!/bin/sh 10 | 11 | # Clean up the results directory 12 | rm -rf results 13 | mkdir results 14 | 15 | #Synthesize the Wrapper Files 16 | 17 | echo 'Synthesizing example design with XST'; 18 | xst -ifn xst.scr 19 | cp RAM_B_exdes.ngc ./results/ 20 | 21 | 22 | # Copy the netlist generated by Coregen 23 | echo 'Copying files from the netlist directory to the results directory' 24 | cp ../../RAM_B.ngc results/ 25 | 26 | # Copy the constraints files generated by Coregen 27 | echo 'Copying files from constraints directory to results directory' 28 | cp ../example_design/RAM_B_exdes.ucf results/ 29 | 30 | cd results 31 | 32 | echo 'Running ngdbuild' 33 | ngdbuild -p xc6slx16-csg324-3 RAM_B_exdes 34 | 35 | echo 'Running map' 36 | map RAM_B_exdes -o mapped.ncd -pr i 37 | 38 | echo 'Running par' 39 | par mapped.ncd routed.ncd 40 | 41 | echo 'Running trce' 42 | trce -e 10 routed.ncd mapped.pcf -o routed 43 | 44 | echo 'Running design through bitgen' 45 | bitgen -w routed 46 | 47 | echo 'Running netgen to create gate level Verilog model' 48 | netgen -ofmt verilog -sim -tm RAM_B_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v 49 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.bld: -------------------------------------------------------------------------------- 1 | Release 14.7 ngdbuild P.20131013 (nt64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe 5 | -intstyle ise -dd _ngo -nt timestamp -uc CLAAAdderM.ucf -p xc6slx16-csg324-3 6 | CLLAAdderM.ngc CLLAAdderM.ngd 7 | 8 | Reading NGO file "D:/COAexp-master/COAexp-master/Exp2_CLAAdderM/CLLAAdderM.ngc" 9 | ... 10 | Gathering constraint information from source properties... 11 | Done. 12 | 13 | Annotating constraints to design from ucf file "CLAAAdderM.ucf" ... 14 | Resolving constraint associations... 15 | Checking Constraint Associations... 16 | Done... 17 | 18 | Checking expanded design ... 19 | 20 | Partition Implementation Status 21 | ------------------------------- 22 | 23 | No Partitions were found in this design. 24 | 25 | ------------------------------- 26 | 27 | NGDBUILD Design Results Summary: 28 | Number of errors: 0 29 | Number of warnings: 0 30 | 31 | Total memory usage is 165352 kilobytes 32 | 33 | Writing NGD file "CLLAAdderM.ngd" ... 34 | Total REAL time to NGDBUILD completion: 4 sec 35 | Total CPU time to NGDBUILD completion: 2 sec 36 | 37 | Writing NGDBUILD log file "CLLAAdderM.bld"... 38 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/RAM_B/implement/implement.bat: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | rem Clean up the results directory 10 | rmdir /S /Q results 11 | mkdir results 12 | 13 | rem Synthesize the VHDL Wrapper Files 14 | 15 | 16 | echo 'Synthesizing example design with XST'; 17 | xst -ifn xst.scr 18 | copy RAM_B_exdes.ngc .\results\ 19 | 20 | 21 | rem Copy the netlist generated by Coregen 22 | echo 'Copying files from the netlist directory to the results directory' 23 | copy ..\..\RAM_B.ngc results\ 24 | 25 | 26 | rem Copy the constraints files generated by Coregen 27 | echo 'Copying files from constraints directory to results directory' 28 | copy ..\example_design\RAM_B_exdes.ucf results\ 29 | 30 | cd results 31 | 32 | echo 'Running ngdbuild' 33 | ngdbuild -p xc6slx16-csg324-3 RAM_B_exdes 34 | 35 | echo 'Running map' 36 | map RAM_B_exdes -o mapped.ncd -pr i 37 | 38 | echo 'Running par' 39 | par mapped.ncd routed.ncd 40 | 41 | echo 'Running trce' 42 | trce -e 10 routed.ncd mapped.pcf -o routed 43 | 44 | echo 'Running design through bitgen' 45 | bitgen -w routed 46 | 47 | echo 'Running netgen to create gate level Verilog model' 48 | netgen -ofmt verilog -sim -tm RAM_B_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v 49 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_M.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn ALU_M.prj 5 | -ofn ALU_M 6 | -ofmt NGC 7 | -p xc6slx16-3-csg324 8 | -top ALU_M 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/ipcore_dir/edit_RAM_B.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "RAM_B" xc6slx16-3csg324 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/ALU_TOP.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "E:/CCOAexp/Exp3/xst/projnav.tmp" 2 | set -xsthdpdir "E:/CCOAexp/Exp3/xst" 3 | run -compileonly yes 4 | -p xc6slx16-3-csg324 5 | -top ALU_TOP 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 16 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn ALU_TOP.prj 51 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/CLED_M.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "E:/CCOAexp/Exp3/xst/projnav.tmp" 2 | set -xsthdpdir "E:/CCOAexp/Exp3/xst" 3 | run -compileonly yes 4 | -p xc6slx16-3-csg324 5 | -top CLED_M 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 16 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn CLED_M.prj 51 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/CLLAAdderM.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn CLLAAdderM.prj 5 | -ofn CLLAAdderM 6 | -ofmt NGC 7 | -p xc6slx16-3-csg324 8 | -top CLLAAdderM 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -------------------------------------------------------------------------------- /Experiment/Exp2_CLAAdderM/fuse.log: -------------------------------------------------------------------------------- 1 | Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM_test_isim_beh.exe -prj E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM_test_beh.prj work.CLLAAdderM_test work.glbl 2 | ISim P.20131013 (signature 0x7708f090) 3 | Number of CPUs detected in this system: 8 4 | Turning on mult-threading, number of parallel sub-compilation jobs: 16 5 | Determining compilation order of HDL files 6 | Analyzing Verilog file "E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM.v" into library work 7 | Analyzing Verilog file "E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM_test.v" into library work 8 | Analyzing Verilog file "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work 9 | Starting static elaboration 10 | Completed static elaboration 11 | Compiling module CLLAAdderM 12 | Compiling module CLLAAdderM_test 13 | Compiling module glbl 14 | Time Resolution for simulation is 1ps. 15 | Waiting for 1 sub-compilation(s) to finish... 16 | Compiled 3 Verilog Units 17 | Built simulation executable E:/CCOAexp/Experiment/Exp2_CLAAdderM/CLLAAdderM_test_isim_beh.exe 18 | Fuse Memory Usage: 29260 KB 19 | Fuse CPU Usage: 561 ms 20 | -------------------------------------------------------------------------------- /Experiment/Exp3_ALU/Choice_M.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "E:/CCOAexp/Exp3/xst/projnav.tmp" 2 | set -xsthdpdir "E:/CCOAexp/Exp3/xst" 3 | run -compileonly yes 4 | -p xc6slx16-3-csg324 5 | -top Choice_M 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 16 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn Choice_M.prj 51 | -------------------------------------------------------------------------------- /Experiment/Exp4_Segment/Segment_M.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "E:/Exp4_Segment/Exp4_Segment/xst/projnav.tmp" 2 | set -xsthdpdir "E:/Exp4_Segment/Exp4_Segment/xst" 3 | run -compileonly yes 4 | -p xc6slx16-3-csg324 5 | -top Segment_M 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 16 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn Segment_M.prj 51 | -------------------------------------------------------------------------------- /Experiment/Exp5_MemoryIP/Method_1_Memory_m.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "E:/Exp_MemoryIP/xst/projnav.tmp" 2 | set -xsthdpdir "E:/Exp_MemoryIP/xst" 3 | run -compileonly yes 4 | -p xc6slx16-3-csg324 5 | -top Method_1_Memory_m 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 16 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn Method_1_Memory_m.prj 51 | --------------------------------------------------------------------------------