├── .gitignore ├── .gitmodules ├── Notes.md ├── README.md ├── misc ├── bin2hex.py ├── create_mif.rb └── hex2bin.py ├── movie ├── .gitignore ├── Makefile ├── nibbles_to_bytes.py ├── palette_to_c.py └── rick_orig.gif ├── pcbs ├── frame_corners │ ├── Library │ │ └── Panelization.pretty │ │ │ ├── README.md │ │ │ ├── mouse-bite-1mm-slot.kicad_mod │ │ │ ├── mouse-bite-2.54mm-slot.kicad_mod │ │ │ ├── mouse-bite-2mm-slot.kicad_mod │ │ │ └── push.sh │ ├── fp-info-cache │ ├── frame_corners-cache.lib │ ├── frame_corners.kicad_pcb │ ├── frame_corners.kicad_pcb-bak │ ├── frame_corners.net │ ├── frame_corners.pro │ ├── frame_corners.sch │ ├── frame_corners.sch-bak │ ├── frame_corners_with_dimensions.kicad_pcb │ ├── gerbers │ │ ├── frame_corners-B_Cu.gbr │ │ ├── frame_corners-B_Mask.gbr │ │ ├── frame_corners-B_Paste.gbr │ │ ├── frame_corners-B_SilkS.gbr │ │ ├── frame_corners-Edge_Cuts.gbr │ │ ├── frame_corners-F_Cu.gbr │ │ ├── frame_corners-F_Mask.gbr │ │ ├── frame_corners-F_Paste.gbr │ │ ├── frame_corners-F_SilkS.gbr │ │ ├── frame_corners-NPTH-drl_map.ps │ │ ├── frame_corners-NPTH.drl │ │ ├── frame_corners-PTH-drl_map.ps │ │ └── frame_corners-PTH.drl │ └── panelized │ │ ├── output.panelized.kicad_pcb │ │ ├── panelized.kicad_pcb │ │ ├── run.sh │ │ ├── upload1 │ │ ├── Untitled_Combined_Bottom.png │ │ ├── Untitled_Combined_Top.png │ │ ├── combined.GKO │ │ ├── combined.drl │ │ ├── combined.gbl │ │ ├── combined.gbo │ │ ├── combined.gbp │ │ ├── combined.gbs │ │ ├── combined.gtl │ │ ├── combined.gto │ │ ├── combined.gtp │ │ ├── combined.gts │ │ └── combined.txt │ │ └── upload2 │ │ ├── output.panelized-B_Cu.gbr │ │ ├── output.panelized-B_Mask.gbr │ │ ├── output.panelized-B_Paste.gbr │ │ ├── output.panelized-B_SilkS.gbr │ │ ├── output.panelized-Edge_Cuts.gbr │ │ ├── output.panelized-F_Cu.gbr │ │ ├── output.panelized-F_Mask.gbr │ │ ├── output.panelized-F_Paste.gbr │ │ ├── output.panelized-F_SilkS.gbr │ │ ├── output.panelized-NPTH-drl_map.ps │ │ ├── output.panelized-NPTH.drl │ │ ├── output.panelized-PTH-drl_map.ps │ │ └── output.panelized-PTH.drl └── gpio2hub75 │ ├── fp-info-cache │ ├── frame_corners-cache.lib │ ├── frame_corners.kicad_pcb │ ├── frame_corners.kicad_pcb-bak │ ├── frame_corners.net │ ├── frame_corners.pro │ ├── frame_corners.sch │ ├── frame_corners.sch-bak │ ├── gerbers │ ├── frame_corners-B_Cu.gbr │ ├── frame_corners-B_Mask.gbr │ ├── frame_corners-B_Paste.gbr │ ├── frame_corners-B_SilkS.gbr │ ├── frame_corners-Edge_Cuts.gbr │ ├── frame_corners-F_Cu.gbr │ ├── frame_corners-F_Mask.gbr │ ├── frame_corners-F_Paste.gbr │ ├── frame_corners-F_SilkS.gbr │ ├── frame_corners-NPTH-drl_map.ps │ ├── frame_corners-NPTH.drl │ ├── frame_corners-PTH-drl_map.ps │ └── frame_corners-PTH.drl │ └── gpio2hub75_gerbers.zip ├── quartus ├── .gitignore ├── Makefile ├── altera_models │ ├── led_ram │ │ ├── led_ram.qip │ │ ├── led_ram.v │ │ └── led_ram_bb.v │ └── main_pll │ │ ├── main_pll.ppf │ │ ├── main_pll.qip │ │ ├── main_pll.v │ │ └── main_pll_bb.v ├── cube.sdc ├── hwic-3g-cdma.qpf ├── hwic-3g-cdma.qsf ├── output_files │ └── hwic-3g-cdma.sof └── pinout.tcl ├── spinal ├── .gitignore ├── Makefile ├── build.sbt ├── project │ ├── build.properties │ └── plugins.sbt └── src │ └── main │ └── scala │ ├── cc │ ├── Apb3CC.scala │ ├── ApbBus2PipelinedMemoryBus.scala │ ├── CCBlocks.scala │ ├── CCGpio.scala │ ├── CpuComplex.scala │ └── Sequence.scala │ ├── cube │ ├── CpuTop.scala │ ├── CubeShim.scala │ ├── CubeTop.scala │ ├── Hub75Intfc.scala │ ├── Hub75Phy.scala │ ├── Hub75Streamer.scala │ ├── LedGpu.scala │ ├── LedMem.scala │ ├── LedStreamer.scala │ └── WS2812Drv.scala │ ├── cyclone2 │ ├── led_ram.scala │ └── main_pll.scala │ └── ice40 │ ├── SB_HFOSC.scala │ ├── SB_I2C.scala │ └── SB_RGBA_DRV.scala ├── sw ├── .gitignore ├── Makefile ├── global.h ├── hub75_streamer.c ├── hub75_streamer.h ├── i2c.c ├── i2c.h ├── led_render.c ├── led_render.h ├── main.c ├── reg.h ├── sections.lds ├── start.S ├── test │ ├── .gdbinit │ ├── run.sh │ ├── test │ └── test.c └── top_defines.h └── tb ├── .gitignore ├── Makefile ├── tb.v └── waves.gtkw /.gitignore: -------------------------------------------------------------------------------- 1 | .*.swp 2 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "VexRiscv"] 2 | path = VexRiscv 3 | url = https://github.com/SpinalHDL/VexRiscv.git 4 | -------------------------------------------------------------------------------- /Notes.md: -------------------------------------------------------------------------------- 1 | ## Current Measurements: 2 | 3 | * 3.3V 4 | 5 | 0: 6 | 7 | * All LEDs off: 0.6A 8 | 9 | 255: 10 | 11 | * All LEDs red: 6.6A 12 | * All LEDs green: 3.6A 13 | * All LEDs blue: 2.8A 14 | 15 | * All LEDs red + green: 6.8A 16 | * All LEDs red + blue: 6.5A 17 | * All LEDs green + blue: 4.2A 18 | 19 | * All LEDs green + green + blue: 7.8A 20 | 21 | 128: (with gamma!) 22 | 23 | * All LEDs red: 2.2A 24 | * All LEDs green: 1.3A 25 | * All LEDs blue: 1.2A 26 | 27 | * All LEDs red + green: 2.5A 28 | * All LEDs red + blue: 2.3A 29 | * All LEDs green + blue: 1.6A 30 | 31 | * All LEDs green + green + blue: 2.4A 32 | 33 | 64: (with gamma!) 34 | 35 | * All LEDs red: 1.0A 36 | * All LEDs green: 0.8A 37 | * All LEDs blue: 0.7A 38 | 39 | * All LEDs red + green: 1.1A 40 | * All LEDs red + blue: 41 | * All LEDs green + blue: 42 | 43 | * All LEDs green + green + blue: 1.1A 44 | 45 | 46 | ## LED Addressing 47 | 48 | ### LED Memory Physical Address map 49 | 50 | LED mem has 2 buffers (for double-buffered rendering). 51 | Each buffer has a size of 6 * 32 * 32 = 6144 words, so the total LED memory is 12288 words. 52 | 53 | In LED mem, each side of the cube has a rectangle assigned to them. 54 | 55 | The sides are numbered as follows: 56 | 57 | ``` 58 | +---+ 59 | | 4 | 60 | +---+---+---+---+ 61 | | 0 | 1 | 2 | 3 | 62 | +---+---+---+---+ 63 | | 5 | 64 | +---+ 65 | ``` 66 | 67 | Within a buffer, addressing is as follows: 68 | 69 | * start address of each side is `side_nr * 32 * 32` 70 | * start address corresponds to the top-left of each square above 71 | * the pitch of each side is the same as the number of columns. 72 | 73 | The corresponding naming convention: left, front, right, back, top, bottom. 74 | 75 | ``` 76 | +---+ 77 | | T | 78 | +---+---+---+---+ 79 | | L | F | R | Ba| 80 | +---+---+---+---+ 81 | | Bo| 82 | +---+ 83 | ``` 84 | 85 | The Hub75Streamer block has a `PANEL_INFO` registers that contains all the information to 86 | translate from the LED mem addressing. If panels are rotated, it can compensate for that. 87 | 88 | ### LED Memory Locial Address Maps 89 | 90 | To make life for the CPU easier, there are also logical address maps, which are 91 | designed such that there is an intuitive overflow behavior wrt neighboring tile. 92 | 93 | There is one logical map for each 'infinite ring', where, if you continue in the same 94 | primary direction, you end up in the same place as before in a logical way. 95 | 96 | Here is one such example: 97 | 98 | ``` 99 | +---+---+---+---+---+---+ 100 | | T | T | T | T | T | T | 101 | +---+---+---+---+---+---+ 102 | | L | F | R | Ba| L | F | 103 | +---+---+---+---+---+---+ 104 | | Bo| Bo| Bo| Bo| Bo| Bo| 105 | +---+---+---+---+---+---+ 106 | ``` 107 | 108 | In this case, the ring consists of tile L-F-R-B. T and B are considered non-ring 109 | overflow tiles. 110 | 111 | When you start on the left side and keep in increasing the X coordinate, you'll wrap around 112 | the cube and end up in the same place after 4 side. 113 | 114 | The image above is laid out on a rectangular logical address map, with a pitch that is at least 115 | 6 wide. But it's easier to make it 8 wide, so it will look a bit like this: 116 | 117 | ``` 118 | +---+---+---+---+---+---+---+---+ 119 | | T | T | T | T | T | T | T | T | 120 | +---+---+---+---+---+---+---+---+ 121 | | L | F | R | Ba| L | F | R | Ba| 122 | +---+---+---+---+---+---+---+---+ 123 | | Bo| Bo| Bo| Bo| Bo| Bo| Bo| Bo| 124 | +---+---+---+---+---+---+---+---+ 125 | ``` 126 | 127 | With the arrangement above, you can blit any image that is 32 pixels height and up to 128 | 5 sides wide at any starting point of the ring and have correct roll-over behavior. 129 | Since it makes no sense to have a image that's more than 4 sides wide (because the right 130 | would overwrite the left), that's fine. 131 | 132 | For the case above, the top and the bottom tiles will have different overflow 133 | behavior for each for the 4 members of the ring. For example if you are in L and 134 | you go up until you roll over into tile T, then the L(X,Y) coordinate converts into 135 | T(X, Y). However, if you in F and you do the same thing, then F(X,Y) converts 136 | into T(32-Y,X). 137 | 138 | 139 | Here are different rings: 140 | 141 | F-Bo-Ba-T: 142 | 143 | ``` 144 | +---+---+---+---+---+---+---+---+ 145 | | R | R | R | R | R | R | R | R | 146 | +---+---+---+---+---+---+---+---+ 147 | | F | Bo| Ba| T | F | Bo| Ba| T | 148 | +---+---+---+---+---+---+---+---+ 149 | | L | L | L | L | L | L | L | L | 150 | +---+---+---+---+---+---+---+---+ 151 | ``` 152 | 153 | L-Bo-R-T: 154 | 155 | ``` 156 | +---+---+---+---+---+---+---+---+ 157 | | Ba| Ba| Ba| Ba| Ba| Ba| Ba| Ba| 158 | +---+---+---+---+---+---+---+---+ 159 | | L | Bo| R | T | L | Bo| R | T | 160 | +---+---+---+---+---+---+---+---+ 161 | | F | F | F | F | F | F | F | F | 162 | +---+---+---+---+---+---+---+---+ 163 | ``` 164 | 165 | Calculation for: 166 | 167 | | L | F | R | Ba| L | F | R | Ba| 168 | 169 | Given an address for a particular ring: 170 | 171 | ``` 172 | strip_size = 16 * 32 * 32 173 | side_size = 32 * 32 174 | 175 | strip_y_nr = addr / strip_size 176 | strip_x_nr = (addr % strip_size) / side_size 177 | 178 | strip_class = [ L, F, R, Ba ][strip_x_nr & 3] 179 | if (strip_y_nr == 0) 180 | side_nr = T 181 | orient_class = { 182 | L -> (32-X, Y), 183 | F -> (X, Y), 184 | R -> (32-Y, X), 185 | Ba -> (32-X, Y) 186 | }[strip_class] 187 | 188 | else if (strip_y_nr == 1) 189 | side_nr = strip_class 190 | orient_class = (X,Y) 191 | 192 | else if (strip_y_nr == 2) 193 | side_nr = Bo 194 | orient_class = { 195 | L -> (32-X, Y), 196 | F -> (X, Y), 197 | R -> (32-Y, X), 198 | Ba -> (32-X, Y) 199 | }[strip_class] 200 | 201 | led_mem_addr = (side_nr * 32 * 32) + orient_class[1] * 32 + orient_class[0] 202 | ``` 203 | 204 | Each ring occupies 8 x 3 = 24 sides, but we allocate 32 sides for that. 205 | That gives 32 * 32 * 32 = 32k addresses per ring. 206 | There are 3 rings, so we need 98k local addresses. 207 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | # LED Cube with Cisco Controller and Pixel Purse LED Panels 3 | 4 | This repo needs a bit of cleanup for general public consumption, 5 | but it had all the assets for my LED cube that’s built from 6 | [Project MC2 Pixel Purse LED panels](https://tomverbeure.github.io/2019/10/03/Pixel-Purse.html) 7 | and a [Cisco HWIC-3G-CDMA modem](https://tomverbeure.github.io/2019/11/11/Cisco-HWIC-3G-CDMA.html). 8 | 9 | I gave a talk about this project at BangBangCon West 2020: here are 10 | the [video](https://www.youtube.com/watch?v=0tBU5-lJYmU) and [slides](https://docs.google.com/presentation/d/1FYmVh-brx6SpZoJmzuIXrNegWdtriQ9k38EbrvDupg8) of the talk. 11 | 12 | I also wrote a [blog post](https://tomverbeure.github.io/2021/05/16/Pixel-Purse-LED-Cube.html) 13 | about this project. 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /misc/bin2hex.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import sys 4 | 5 | for line in sys.stdin: 6 | print( "{0:02x}".format(int(line.strip(),2)) ) 7 | -------------------------------------------------------------------------------- /misc/create_mif.rb: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env ruby 2 | 3 | require 'optparse' 4 | require 'pp' 5 | 6 | options = {} 7 | OptionParser.new do |opts| 8 | opts.banner = "Usage: create_mif.rb [options]" 9 | opts.on("-v", "--[no-]verbose", "Run verbosely") do |v| 10 | options[:verbose] = v 11 | end 12 | 13 | opts.on("-fFORMAT", "--format=FORMAT", "Specify output format ('mif', 'hex', 'coe', 'mem')") do |f| 14 | options[:format] = f 15 | end 16 | 17 | opts.on("-dDEPTH", "--depth=DEPTH", Integer, "Memory depth") do |d| 18 | options[:depth] = d 19 | end 20 | 21 | opts.on("-wWIDTH", "--width=WIDTH", Integer, "Memory width (bits)") do |w| 22 | options[:width] = w 23 | end 24 | 25 | opts.on("-oOFFSET", "--offset=OFFSET", Integer, "First byte to use of the binary input file (default = 0)") do |o| 26 | options[:offset] = o 27 | end 28 | 29 | opts.on("-iINCREMENT", "--increment=INCREMENT", Integer, "How many bytes to the next byte (default = 1)") do |i| 30 | options[:increment] = i 31 | end 32 | 33 | end.parse! 34 | 35 | start_offset = options[:offset] || 0 36 | increment = options[:increment] || 1 37 | 38 | bin = File.open(ARGV[0], "rb").read 39 | bytes = bin.unpack("C*")[start_offset..-1].each_slice(increment).collect{ |a| a.first } 40 | 41 | depth = options[:depth] || bytes.size 42 | width = options[:width] || 8 43 | format = options[:format] || "mif" 44 | 45 | bytes_per_word = (width+7)>>3 46 | nr_addr_bits = Math.log2(depth).ceil 47 | 48 | if options[:verbose] 49 | STDERR.puts "output format : #{format}" 50 | STDERR.puts "depth : #{depth}" 51 | STDERR.puts "width : #{width}" 52 | STDERR.puts "bytes per word: #{bytes_per_word}" 53 | STDERR.puts "start offset : #{start_offset}" 54 | STDERR.puts "increment : #{increment}" 55 | end 56 | 57 | if format == "mif" 58 | puts %{-- Created by create_mif.rb 59 | DEPTH = #{depth}; 60 | WIDTH = #{width}; 61 | ADDRESS_RADIX = HEX; 62 | DATA_RADIX = HEX; 63 | CONTENT 64 | BEGIN 65 | } 66 | 67 | addr_fmt_string = "%%0%dx" % ((nr_addr_bits+3)>>2) 68 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 69 | 70 | fmt_string = "#{addr_fmt_string}: #{data_fmt_string};" 71 | 72 | words = bytes.each_slice(bytes_per_word) 73 | words.each_with_index do |w, addr| 74 | value = 0 75 | w.reverse.collect { |b| value = value * 256 + b } 76 | puts fmt_string % [addr, value] 77 | end 78 | 79 | if words.size < depth 80 | puts "[#{addr_fmt_string}..#{addr_fmt_string}]: #{data_fmt_string};" % [ words.size, depth-1, 0 ] 81 | end 82 | 83 | puts "END;" 84 | puts 85 | 86 | elsif format == "coe" 87 | puts %{; Created by create_mif.rb 88 | ; block memory configuration: 89 | ; DEPTH = #{depth}; 90 | ; WIDTH = #{width}; 91 | memory_initialization_radix=16; 92 | memory_initialization_vector=} 93 | 94 | words = bytes.each_slice(bytes_per_word).collect do |w| 95 | value = 0 96 | w.reverse.collect { |b| value = value * 256 + b } 97 | value 98 | end 99 | 100 | (depth - words.size).times { words << 0 } 101 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 102 | str = words.collect{ |w| data_fmt_string % w }.join(",\n") + ";" 103 | 104 | puts str 105 | 106 | elsif format == "hex" 107 | 108 | words = bytes.each_slice(bytes_per_word).collect do |w| 109 | value = 0 110 | w.reverse.collect { |b| value = value * 256 + b } 111 | value 112 | end 113 | 114 | (depth - words.size).times { words << 0 } 115 | 116 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 117 | str = words.collect{ |w| data_fmt_string % w }.join("\n") 118 | 119 | puts str 120 | 121 | elsif format == "mem" 122 | 123 | words = bytes.each_slice(bytes_per_word).collect do |w| 124 | value = 0 125 | w.reverse.collect { |b| value = value * 256 + b } 126 | value 127 | end 128 | 129 | (depth - words.size).times { words << 0 } 130 | 131 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 132 | str = words.collect{ |w| data_fmt_string % w }.join("\n") 133 | 134 | puts "@00000000" 135 | puts str 136 | 137 | else 138 | Kernel.abort("Unknown format '#{format}'! Aborting...") 139 | end 140 | -------------------------------------------------------------------------------- /misc/hex2bin.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import sys 4 | 5 | for line in sys.stdin: 6 | print( "{0:08b}".format(int(line.strip(),16)) ) 7 | -------------------------------------------------------------------------------- /movie/.gitignore: -------------------------------------------------------------------------------- 1 | 24bpp_to_8bpp 2 | *.png 3 | *.rgb 4 | *.bin 5 | *.h 6 | *.idx 7 | *.info 8 | rick_32x23.gif 9 | ricks_joined.gif 10 | -------------------------------------------------------------------------------- /movie/Makefile: -------------------------------------------------------------------------------- 1 | 2 | #RICKS_ORIG = rick_32x23-0.8bpp.rgb \ 3 | # rick_32x23-1.8bpp.rgb \ 4 | # rick_32x23-2.8bpp.rgb \ 5 | # rick_32x23-3.8bpp.rgb \ 6 | # rick_32x23-4.8bpp.rgb \ 7 | # rick_32x23-5.8bpp.rgb \ 8 | # rick_32x23-6.8bpp.rgb \ 9 | # rick_32x23-7.8bpp.rgb \ 10 | # rick_32x23-8.8bpp.rgb \ 11 | # rick_32x23-9.8bpp.rgb \ 12 | # rick_32x23-10.8bpp.rgb \ 13 | # rick_32x23-11.8bpp.rgb \ 14 | # rick_32x23-12.8bpp.rgb \ 15 | # rick_32x23-13.8bpp.rgb \ 16 | # rick_32x23-14.8bpp.rgb \ 17 | # rick_32x23-15.8bpp.rgb \ 18 | # rick_32x23-16.8bpp.rgb \ 19 | # rick_32x23-17.8bpp.rgb \ 20 | # rick_32x23-18.8bpp.rgb \ 21 | # rick_32x23-19.8bpp.rgb \ 22 | # rick_32x23-20.8bpp.rgb \ 23 | # rick_32x23-21.8bpp.rgb \ 24 | # rick_32x23-22.8bpp.rgb \ 25 | # rick_32x23-23.8bpp.rgb \ 26 | # rick_32x23-24.8bpp.rgb \ 27 | # rick_32x23-25.8bpp.rgb \ 28 | # rick_32x23-26.8bpp.rgb \ 29 | # rick_32x23-27.8bpp.rgb \ 30 | # rick_32x23-28.8bpp.rgb \ 31 | # rick_32x23-29.8bpp.rgb \ 32 | # rick_32x23-30.8bpp.rgb \ 33 | # rick_32x23-31.8bpp.rgb 34 | 35 | RICKS_ORIG = rick_32x23-00 \ 36 | rick_32x23-02 \ 37 | rick_32x23-04 \ 38 | rick_32x23-06 \ 39 | rick_32x23-08 \ 40 | rick_32x23-10 \ 41 | rick_32x23-12 \ 42 | rick_32x23-14 \ 43 | rick_32x23-16 \ 44 | rick_32x23-18 \ 45 | rick_32x23-20 \ 46 | rick_32x23-22 \ 47 | rick_32x23-24 \ 48 | rick_32x23-26 \ 49 | rick_32x23-28 \ 50 | rick_32x23-30 51 | 52 | RICKS_ORIG_PNG = $(RICKS_ORIG:=.png) 53 | RICKS_ORIG_RGB = $(RICKS_ORIG:=.rgb) 54 | 55 | RICKS_FINAL = rick_32x23-00 \ 56 | rick_32x23-01 \ 57 | rick_32x23-02 \ 58 | rick_32x23-03 \ 59 | rick_32x23-04 \ 60 | rick_32x23-05 \ 61 | rick_32x23-06 \ 62 | rick_32x23-07 \ 63 | rick_32x23-08 \ 64 | rick_32x23-09 \ 65 | rick_32x23-10 \ 66 | rick_32x23-11 \ 67 | rick_32x23-12 \ 68 | rick_32x23-13 \ 69 | rick_32x23-14 \ 70 | rick_32x23-15 71 | 72 | RICKS_FINAL_IDX = $(RICKS_FINAL:=.idx) 73 | 74 | all: ricks_compr.h palette.h 75 | 76 | # Convert into 1 file to force unique palette 77 | ricks_joined.gif: $(RICKS_ORIG_PNG) 78 | convert $(RICKS_ORIG_PNG) -append -colors 16 $@ 79 | 80 | .PRECIOUS: %.rgb 81 | %.rgb: ricks_joined.gif 82 | convert $< -crop 32x23 rick_32x23-%02d.rgb 83 | 84 | %.idx: %.rgb palette.info 85 | ./palette_to_c.py palette.info $< $@ 86 | 87 | ricks_compr.h: ricks_compr.bin 88 | xxd --include $< > $@ 89 | 90 | ricks.bin: $(RICKS_FINAL_IDX) 91 | cat $^ > $@ 92 | 93 | ricks_compr.bin: ricks.bin 94 | ./nibbles_to_bytes.py $< $@ 95 | 96 | %.rgb: %.png 97 | convert $< $@ 98 | 99 | %.png: rick_32x23.gif 100 | convert -coalesce rick_32x23.gif rick_32x23-%02d.png 101 | 102 | rick_32x23.gif: rick_orig.gif 103 | convert -resize 32x23 rick_orig.gif rick_32x23.gif 104 | 105 | palette.info: ricks_joined.gif 106 | convert ricks_joined.gif -format %c -depth 8 histogram:info:- > $@ 107 | 108 | palette.bin: palette.info 109 | ./palette_to_c.py $< dummy dummy $@ 110 | 111 | palette.h: palette.bin 112 | xxd --include $< > $@ 113 | 114 | clean: 115 | rm -f rick_32x23.gif *.png *.rgb ricks.* *.idx ricks_joined.gif palette.* ricks_compr.* 116 | -------------------------------------------------------------------------------- /movie/nibbles_to_bytes.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import sys 4 | import struct 5 | from array import array 6 | 7 | import pprint 8 | 9 | 10 | pp = pprint.PrettyPrinter(indent=4) 11 | 12 | bytes_out = [] 13 | 14 | with open(sys.argv[1], "rb") as nibble_file: 15 | while True: 16 | bytes_input = nibble_file.read(2) 17 | 18 | if bytes_input: 19 | byte_out = bytes_input[0] + bytes_input[1] * 16 20 | bytes_out.append(byte_out) 21 | else: 22 | break 23 | 24 | with open(sys.argv[2], "wb") as bytes_out_file: 25 | bytes = bytearray(bytes_out) 26 | bytes_out_file.write(bytes) 27 | 28 | -------------------------------------------------------------------------------- /movie/palette_to_c.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import sys 4 | import struct 5 | import re 6 | from array import array 7 | 8 | import pprint 9 | 10 | 11 | pp = pprint.PrettyPrinter(indent=4) 12 | 13 | palette = [] 14 | palette_lookup = {} 15 | 16 | def create_chunks(list_name, n): 17 | for i in range(0, len(list_name), n): 18 | yield list_name[i:i + n] 19 | 20 | 21 | with open(sys.argv[1]) as palette_file: 22 | re_rgb = re.compile(r"\((\d+),(\d+),(\d+)\)") 23 | 24 | for line in palette_file: 25 | s = re_rgb.search(line) 26 | 27 | r = int(s.group(1)) 28 | g = int(s.group(2)) 29 | b = int(s.group(3)) 30 | 31 | palette_lookup[r + g*256 + b * 65536] = len(palette)//3 32 | palette.append(r) 33 | palette.append(g) 34 | palette.append(b) 35 | 36 | if len(sys.argv) > 4: 37 | with open(sys.argv[4], "wb") as palette_output_file: 38 | bytes = bytearray(palette) 39 | palette_output_file.write(bytes) 40 | sys.exit(0) 41 | 42 | with open(sys.argv[2], 'rb') as bitmap_file: 43 | bitmap = bytearray(bitmap_file.read()) 44 | pixels = list(create_chunks(bitmap, 3)) 45 | 46 | output_buf = [] 47 | 48 | for pixel in pixels: 49 | r = pixel[0] 50 | g = pixel[1] 51 | b = pixel[2] 52 | 53 | index = palette_lookup[r + g*256 + b * 65536] 54 | output_buf.append(index) 55 | 56 | with open(sys.argv[3], "wb") as output_file: 57 | 58 | bytes = bytearray(output_buf) 59 | output_file.write(bytes) 60 | 61 | 62 | 63 | 64 | #pp.pprint(palette) 65 | #pp.pprint(palette_lookup) 66 | #pp.pprint(pixels) 67 | #pp.pprint(output_buf) 68 | 69 | 70 | -------------------------------------------------------------------------------- /movie/rick_orig.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/cube/8825de87cb2f6d403bfcbcad1ebeddac23d54e3b/movie/rick_orig.gif -------------------------------------------------------------------------------- /pcbs/frame_corners/Library/Panelization.pretty/README.md: -------------------------------------------------------------------------------- 1 | 2 | Panelization.pretty 3 | =================== 4 | 5 | LAYOUT FILES: KiCad footprints useful for PCB panelization (mouse-bites...). 6 | 7 | -------------------------------------------------------------------------------- /pcbs/frame_corners/Library/Panelization.pretty/mouse-bite-1mm-slot.kicad_mod: -------------------------------------------------------------------------------- 1 | (module mouse-bite-1mm-slot (layer F.Cu) (tedit 551DB9EF) 2 | (fp_text reference mouse-bite-1mm-slot (at 0 -2) (layer F.SilkS) hide 3 | (effects (font (size 1 1) (thickness 0.2))) 4 | ) 5 | (fp_text value VAL** (at 0 2.1) (layer F.SilkS) hide 6 | (effects (font (size 1 1) (thickness 0.2))) 7 | ) 8 | (fp_circle (center 1.5 0) (end 1.56 0) (layer Dwgs.User) (width 0.05)) 9 | (fp_circle (center -1.5 0) (end -1.44 0) (layer Dwgs.User) (width 0.05)) 10 | (fp_arc (start 1.5 0) (end 1.5 0.5) (angle 180) (layer F.SilkS) (width 0.1)) 11 | (fp_arc (start -1.5 0) (end -1.5 -0.5) (angle 180) (layer F.SilkS) (width 0.1)) 12 | (fp_line (start -1.5 0) (end -1.5 0) (layer Eco1.User) (width 1)) 13 | (fp_line (start 1.5 0) (end 1.5 0) (layer Eco1.User) (width 1)) 14 | (pad "" np_thru_hole circle (at 0.35 -1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 15 | (pad "" np_thru_hole circle (at -1.15 0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 16 | (pad "" np_thru_hole circle (at 1.15 0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 17 | (pad "" np_thru_hole circle (at -1.15 -0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 18 | (pad "" np_thru_hole circle (at -0.35 -1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 19 | (pad "" np_thru_hole circle (at 1.15 -0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 20 | (pad "" np_thru_hole circle (at -0.35 1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 21 | (pad "" np_thru_hole circle (at 0.35 1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 22 | ) 23 | -------------------------------------------------------------------------------- /pcbs/frame_corners/Library/Panelization.pretty/mouse-bite-2.54mm-slot.kicad_mod: -------------------------------------------------------------------------------- 1 | (module mouse-bite-2.54mm-slot (layer F.Cu) (tedit 551DB929) 2 | (fp_text reference mouse-bite-2.54mm-slot (at 0 -2) (layer F.SilkS) hide 3 | (effects (font (size 1 1) (thickness 0.2))) 4 | ) 5 | (fp_text value VAL** (at 0 2.1) (layer F.SilkS) hide 6 | (effects (font (size 1 1) (thickness 0.2))) 7 | ) 8 | (fp_line (start -2.33 0) (end -2.33 0) (layer Eco1.User) (width 2.54)) 9 | (fp_line (start 2.33 0) (end 2.33 0) (layer Eco1.User) (width 2.54)) 10 | (fp_arc (start 2.33 0) (end 2.33 1.27) (angle 180) (layer F.SilkS) (width 0.1)) 11 | (fp_circle (center 2.33 0) (end 2.33 -0.06) (layer Dwgs.User) (width 0.05)) 12 | (fp_circle (center -2.33 0) (end -2.27 0) (layer Dwgs.User) (width 0.05)) 13 | (fp_arc (start -2.33 0) (end -2.33 1.27) (angle -180) (layer F.SilkS) (width 0.1)) 14 | (pad "" np_thru_hole circle (at 0 -1.1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 15 | (pad "" np_thru_hole circle (at 0 1.1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 16 | (pad "" np_thru_hole circle (at 0.8 -1.1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 17 | (pad "" np_thru_hole circle (at -0.8 -1.1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 18 | (pad "" np_thru_hole circle (at -0.8 1.1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 19 | (pad "" np_thru_hole circle (at 0.8 1.1) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 20 | ) 21 | -------------------------------------------------------------------------------- /pcbs/frame_corners/Library/Panelization.pretty/mouse-bite-2mm-slot.kicad_mod: -------------------------------------------------------------------------------- 1 | (module mouse-bite-2mm-slot (layer F.Cu) (tedit 551DB891) 2 | (fp_text reference mouse-bite-2mm-slot (at 0 -2) (layer F.SilkS) hide 3 | (effects (font (size 1 1) (thickness 0.2))) 4 | ) 5 | (fp_text value VAL** (at 0 2.1) (layer F.SilkS) hide 6 | (effects (font (size 1 1) (thickness 0.2))) 7 | ) 8 | (fp_arc (start -2 0) (end -2 -1) (angle 180) (layer F.SilkS) (width 0.1)) 9 | (fp_arc (start 2 0) (end 2 1) (angle 180) (layer F.SilkS) (width 0.1)) 10 | (fp_circle (center 2 0) (end 2.06 0) (layer Dwgs.User) (width 0.05)) 11 | (fp_circle (center -2 0) (end -2 -0.06) (layer Dwgs.User) (width 0.05)) 12 | (fp_line (start -2 0) (end -2 0) (layer Eco1.User) (width 2)) 13 | (fp_line (start 2 0) (end 2 0) (layer Eco1.User) (width 2)) 14 | (pad "" np_thru_hole circle (at 0 -0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 15 | (pad "" np_thru_hole circle (at 0 0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 16 | (pad "" np_thru_hole circle (at 0.75 -0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 17 | (pad "" np_thru_hole circle (at -0.75 -0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 18 | (pad "" np_thru_hole circle (at -0.75 0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 19 | (pad "" np_thru_hole circle (at 0.75 0.75) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask)) 20 | ) 21 | -------------------------------------------------------------------------------- /pcbs/frame_corners/Library/Panelization.pretty/push.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | git push --all gso && git push --all github 3 | git push --tags gso && git push --tags github 4 | 5 | -------------------------------------------------------------------------------- /pcbs/frame_corners/frame_corners-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | #End Library 5 | -------------------------------------------------------------------------------- /pcbs/frame_corners/frame_corners.net: -------------------------------------------------------------------------------- 1 | (export (version D) 2 | (design 3 | (source /home/tom/projects/cube/pcbs/frame_corners/frame_corners.sch) 4 | (date "Sat 11 Jan 2020 12:39:14 PM PST") 5 | (tool "Eeschema 5.1.5-52549c5~84~ubuntu16.04.1") 6 | (sheet (number 1) (name /) (tstamps /) 7 | (title_block 8 | (title) 9 | (company) 10 | (rev) 11 | (date) 12 | (source frame_corners.sch) 13 | (comment (number 1) (value "")) 14 | (comment (number 2) (value "")) 15 | (comment (number 3) (value "")) 16 | (comment (number 4) (value ""))))) 17 | (components) 18 | (libparts) 19 | (libraries) 20 | (nets)) -------------------------------------------------------------------------------- /pcbs/frame_corners/frame_corners.pro: -------------------------------------------------------------------------------- 1 | update=Monday, January 06, 2020 at 11:45:33 PM 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [pcbnew] 9 | version=1 10 | LastNetListRead= 11 | UseCmpFile=1 12 | PadDrill=0.600000000000 13 | PadDrillOvalY=0.600000000000 14 | PadSizeH=1.500000000000 15 | PadSizeV=1.500000000000 16 | PcbTextSizeV=1.500000000000 17 | PcbTextSizeH=1.500000000000 18 | PcbTextThickness=0.300000000000 19 | ModuleTextSizeV=1.000000000000 20 | ModuleTextSizeH=1.000000000000 21 | ModuleTextSizeThickness=0.150000000000 22 | SolderMaskClearance=0.000000000000 23 | SolderMaskMinWidth=0.000000000000 24 | DrawSegmentWidth=0.200000000000 25 | BoardOutlineThickness=0.100000000000 26 | ModuleOutlineThickness=0.150000000000 27 | [cvpcb] 28 | version=1 29 | NetIExt=net 30 | [eeschema] 31 | version=1 32 | LibDir= 33 | [eeschema/libraries] 34 | [schematic_editor] 35 | version=1 36 | PageLayoutDescrFile= 37 | PlotDirectoryName= 38 | SubpartIdSeparator=0 39 | SubpartFirstId=65 40 | NetFmtName=Pcbnew 41 | SpiceAjustPassiveValues=0 42 | LabSize=50 43 | ERC_TestSimilarLabels=1 44 | -------------------------------------------------------------------------------- /pcbs/frame_corners/frame_corners.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | EELAYER 30 0 3 | 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TF.GenerationSoftware,KiCad,Pcbnew,5.1.5-52549c5~84~ubuntu16.04.1* 2 | G04 #@! TF.CreationDate,2020-01-11T14:28:59-08:00* 3 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 4 | G04 #@! TF.SameCoordinates,Original* 5 | G04 #@! TF.FileFunction,Paste,Top* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW 5.1.5-52549c5~84~ubuntu16.04.1) date 2020-01-11 14:28:59* 10 | %MOMM*% 11 | %LPD*% 12 | G04 APERTURE LIST* 13 | G04 APERTURE END LIST* 14 | M02* 15 | -------------------------------------------------------------------------------- /pcbs/frame_corners/gerbers/frame_corners-NPTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ; DRILL file {KiCad 5.1.5-52549c5~84~ubuntu16.04.1} date Sat 11 Jan 2020 02:29:04 PM PST 3 | ; FORMAT={-:-/ absolute / inch / decimal} 4 | ; #@! TF.CreationDate,2020-01-11T14:29:04-08:00 5 | ; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.5-52549c5~84~ubuntu16.04.1 6 | ; #@! TF.FileFunction,NonPlated,1,2,NPTH 7 | FMAT,2 8 | INCH 9 | T1C0.0866 10 | % 11 | G90 12 | G05 13 | T1 14 | X-13.8661Y21.4173 15 | X-14.8031Y21.4173 16 | X-15.5118Y21.4173 17 | X-15.5118Y20.7087 18 | T0 19 | M30 20 | -------------------------------------------------------------------------------- /pcbs/frame_corners/gerbers/frame_corners-PTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ; DRILL file {KiCad 5.1.5-52549c5~84~ubuntu16.04.1} date Sat 11 Jan 2020 02:29:04 PM PST 3 | ; FORMAT={-:-/ absolute / inch / decimal} 4 | ; #@! TF.CreationDate,2020-01-11T14:29:04-08:00 5 | ; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.5-52549c5~84~ubuntu16.04.1 6 | ; #@! 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X-15.5929Y20.1984 54 | T0 55 | M30 56 | -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/run.sh: -------------------------------------------------------------------------------- 1 | 2 | java -jar ~/Downloads/kicadutil.jar pcb -f ./panelized.kicad_pcb panel --width=3 3 | 4 | -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/upload1/Untitled_Combined_Bottom.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/cube/8825de87cb2f6d403bfcbcad1ebeddac23d54e3b/pcbs/frame_corners/panelized/upload1/Untitled_Combined_Bottom.png -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/upload1/Untitled_Combined_Top.png: -------------------------------------------------------------------------------- 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TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 8 | G04 #@! TF.CreationDate,2020-01-11T21:56:43-08:00* 9 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 10 | G04 #@! TF.SameCoordinates,PXe8840980PYdf933800* 11 | G04 #@! TF.FileFunction,Paste,Bot* 12 | G04 #@! TF.FilePolarity,Positive* 13 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 14 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 21:56:43* 15 | G04 APERTURE LIST* 16 | G04 APERTURE END LIST* 17 | G04 next file* 18 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 19 | G04 #@! TF.CreationDate,2020-01-11T21:56:43-08:00* 20 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 21 | G04 #@! TF.SameCoordinates,PXe8840980PYdf933800* 22 | G04 #@! TF.FileFunction,Paste,Bot* 23 | G04 #@! TF.FilePolarity,Positive* 24 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 25 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 21:56:43* 26 | G04 APERTURE LIST* 27 | G04 APERTURE END LIST* 28 | M02* -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/upload1/combined.gtl: -------------------------------------------------------------------------------- 1 | %MOIN*% 2 | %OFA0B0*% 3 | %FSLAX46Y46*% 4 | %IPPOS*% 5 | %LPD*% 6 | %ADD10R,0.066929133858267723X0.066929133858267723*% 7 | %ADD11O,0.066929133858267723X0.066929133858267723*% 8 | %ADD22R,0.066929133858267723X0.066929133858267723*% 9 | %ADD23O,0.066929133858267723X0.066929133858267723*% 10 | %ADD24R,0.066929133858267723X0.066929133858267723*% 11 | %ADD25O,0.066929133858267723X0.066929133858267723*% 12 | D10* 13 | X0000236220Y0003700787D02* 14 | X0000055118Y0003543307D03* 15 | D11* 16 | X0000155118Y0003543307D03* 17 | X0000055118Y0003443307D03* 18 | X0000155118Y0003443307D03* 19 | X0000055118Y0003343307D03* 20 | X0000155118Y0003343307D03* 21 | X0000055118Y0003243307D03* 22 | X0000155118Y0003243307D03* 23 | X0000055118Y0003143307D03* 24 | X0000155118Y0003143307D03* 25 | D10* 26 | X0000393700Y0003881889D03* 27 | D11* 28 | X0000393700Y0003781889D03* 29 | X0000493700Y0003881889D03* 30 | X0000493700Y0003781889D03* 31 | X0000593700Y0003881889D03* 32 | X0000593700Y0003781889D03* 33 | X0000693700Y0003881889D03* 34 | X0000693700Y0003781889D03* 35 | X0000793700Y0003881889D03* 36 | X0000793700Y0003781889D03* 37 | X0001455118Y0003781889D03* 38 | X0001455118Y0003881889D03* 39 | X0001355118Y0003781889D03* 40 | X0001355118Y0003881889D03* 41 | X0001255118Y0003781889D03* 42 | X0001255118Y0003881889D03* 43 | X0001155118Y0003781889D03* 44 | X0001155118Y0003881889D03* 45 | X0001055118Y0003781889D03* 46 | D10* 47 | X0001055118Y0003881889D03* 48 | D11* 49 | X0000155118Y0002481889D03* 50 | X0000055118Y0002481889D03* 51 | X0000155118Y0002581889D03* 52 | X0000055118Y0002581889D03* 53 | X0000155118Y0002681889D03* 54 | X0000055118Y0002681889D03* 55 | X0000155118Y0002781889D03* 56 | X0000055118Y0002781889D03* 57 | X0000155118Y0002881889D03* 58 | D10* 59 | X0000055118Y0002881889D03* 60 | G04 next file* 61 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 62 | G04 #@! TF.CreationDate,2020-01-11T21:56:43-08:00* 63 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 64 | G04 #@! TF.SameCoordinates,PXe8840980PYdf933800* 65 | G04 #@! TF.FileFunction,Copper,L1,Top* 66 | G04 #@! TF.FilePolarity,Positive* 67 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 68 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 21:56:43* 69 | G04 APERTURE LIST* 70 | G04 APERTURE END LIST* 71 | D22* 72 | X0000748031Y0003188976D02* 73 | X0000566929Y0003031496D03* 74 | D23* 75 | X0000666929Y0003031496D03* 76 | X0000566929Y0002931496D03* 77 | X0000666929Y0002931496D03* 78 | X0000566929Y0002831496D03* 79 | X0000666929Y0002831496D03* 80 | X0000566929Y0002731496D03* 81 | X0000666929Y0002731496D03* 82 | X0000566929Y0002631496D03* 83 | X0000666929Y0002631496D03* 84 | D22* 85 | X0000905511Y0003370078D03* 86 | D23* 87 | X0000905511Y0003270078D03* 88 | X0001005511Y0003370078D03* 89 | X0001005511Y0003270078D03* 90 | X0001105511Y0003370078D03* 91 | X0001105511Y0003270078D03* 92 | X0001205511Y0003370078D03* 93 | X0001205511Y0003270078D03* 94 | X0001305511Y0003370078D03* 95 | X0001305511Y0003270078D03* 96 | X0001966929Y0003270078D03* 97 | X0001966929Y0003370078D03* 98 | X0001866929Y0003270078D03* 99 | X0001866929Y0003370078D03* 100 | X0001766929Y0003270078D03* 101 | X0001766929Y0003370078D03* 102 | X0001666929Y0003270078D03* 103 | X0001666929Y0003370078D03* 104 | X0001566929Y0003270078D03* 105 | D22* 106 | X0001566929Y0003370078D03* 107 | D23* 108 | X0000666929Y0001970078D03* 109 | X0000566929Y0001970078D03* 110 | X0000666929Y0002070078D03* 111 | X0000566929Y0002070078D03* 112 | X0000666929Y0002170078D03* 113 | X0000566929Y0002170078D03* 114 | X0000666929Y0002270078D03* 115 | X0000566929Y0002270078D03* 116 | X0000666929Y0002370078D03* 117 | D22* 118 | X0000566929Y0002370078D03* 119 | G04 next file* 120 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 121 | G04 #@! TF.CreationDate,2020-01-11T21:56:43-08:00* 122 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 123 | G04 #@! TF.SameCoordinates,PXe8840980PYdf933800* 124 | G04 #@! TF.FileFunction,Copper,L1,Top* 125 | G04 #@! TF.FilePolarity,Positive* 126 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 127 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 21:56:43* 128 | G04 APERTURE LIST* 129 | G04 APERTURE END LIST* 130 | D24* 131 | X0001259842Y0002677165D02* 132 | X0001078740Y0002519685D03* 133 | D25* 134 | X0001178740Y0002519685D03* 135 | X0001078740Y0002419685D03* 136 | X0001178740Y0002419685D03* 137 | X0001078740Y0002319685D03* 138 | X0001178740Y0002319685D03* 139 | X0001078740Y0002219685D03* 140 | X0001178740Y0002219685D03* 141 | X0001078740Y0002119685D03* 142 | X0001178740Y0002119685D03* 143 | D24* 144 | X0001417322Y0002858267D03* 145 | D25* 146 | X0001417322Y0002758267D03* 147 | X0001517322Y0002858267D03* 148 | X0001517322Y0002758267D03* 149 | X0001617322Y0002858267D03* 150 | X0001617322Y0002758267D03* 151 | X0001717322Y0002858267D03* 152 | X0001717322Y0002758267D03* 153 | X0001817322Y0002858267D03* 154 | X0001817322Y0002758267D03* 155 | X0002478740Y0002758267D03* 156 | X0002478740Y0002858267D03* 157 | X0002378740Y0002758267D03* 158 | X0002378740Y0002858267D03* 159 | X0002278740Y0002758267D03* 160 | X0002278740Y0002858267D03* 161 | X0002178740Y0002758267D03* 162 | X0002178740Y0002858267D03* 163 | X0002078740Y0002758267D03* 164 | D24* 165 | X0002078740Y0002858267D03* 166 | D25* 167 | X0001178740Y0001458267D03* 168 | X0001078740Y0001458267D03* 169 | X0001178740Y0001558267D03* 170 | X0001078740Y0001558267D03* 171 | X0001178740Y0001658267D03* 172 | X0001078740Y0001658267D03* 173 | X0001178740Y0001758267D03* 174 | X0001078740Y0001758267D03* 175 | X0001178740Y0001858267D03* 176 | D24* 177 | X0001078740Y0001858267D03* 178 | M02* -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/upload1/combined.gtp: -------------------------------------------------------------------------------- 1 | %MOIN*% 2 | %OFA0B0*% 3 | %FSLAX46Y46*% 4 | %IPPOS*% 5 | %LPD*% 6 | G04 next file* 7 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 8 | G04 #@! TF.CreationDate,2020-01-11T21:56:43-08:00* 9 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 10 | G04 #@! TF.SameCoordinates,PXe8840980PYdf933800* 11 | G04 #@! TF.FileFunction,Paste,Top* 12 | G04 #@! TF.FilePolarity,Positive* 13 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 14 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 21:56:43* 15 | G04 APERTURE LIST* 16 | G04 APERTURE END LIST* 17 | G04 next file* 18 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 19 | G04 #@! TF.CreationDate,2020-01-11T21:56:43-08:00* 20 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 21 | G04 #@! TF.SameCoordinates,PXe8840980PYdf933800* 22 | G04 #@! TF.FileFunction,Paste,Top* 23 | G04 #@! TF.FilePolarity,Positive* 24 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 25 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 21:56:43* 26 | G04 APERTURE LIST* 27 | G04 APERTURE END LIST* 28 | M02* -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/upload1/combined.txt: -------------------------------------------------------------------------------- 1 | % 2 | M48 3 | METRIC,000.000 4 | T01C0.50 5 | % 6 | T01 7 | X023588Y090750 8 | X024588Y090750 9 | X025588Y090750 10 | X026588Y090750 11 | X027334Y087250 12 | X026334Y087250 13 | X025334Y087250 14 | X024334Y087250 15 | X023334Y087250 16 | X049588Y090750 17 | X050588Y090750 18 | X051588Y090750 19 | X052588Y090750 20 | X053588Y090750 21 | X054334Y087250 22 | X053334Y087250 23 | X052334Y087250 24 | X051334Y087250 25 | X050334Y087250 26 | X009250Y061038 27 | X009250Y062038 28 | X009250Y063038 29 | X009250Y064038 30 | X009250Y065038 31 | X012750Y065296 32 | X012750Y064296 33 | X012750Y063296 34 | X012750Y062296 35 | X012750Y061296 36 | X062588Y077750 37 | X063588Y077750 38 | X064588Y077750 39 | X065588Y077750 40 | X066588Y077750 41 | X067334Y074250 42 | X066334Y074250 43 | X065334Y074250 44 | X064334Y074250 45 | X063334Y074250 46 | X022250Y048038 47 | X022250Y049038 48 | X022250Y050038 49 | X022250Y051038 50 | X022250Y052038 51 | X025750Y052296 52 | X025750Y051296 53 | X025750Y050296 54 | X025750Y049296 55 | X025750Y048296 56 | X036588Y077750 57 | X037588Y077750 58 | X038588Y077750 59 | X039588Y077750 60 | X040334Y074250 61 | X039334Y074250 62 | X038334Y074250 63 | X037334Y074250 64 | X036334Y074250 65 | M30 -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/upload2/output.panelized-B_Cu.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.5-52549c5~84~ubuntu16.04.1* 2 | G04 #@! TF.CreationDate,2020-01-12T22:05:50-08:00* 3 | G04 #@! TF.ProjectId,output.panelized,6f757470-7574-42e7-9061-6e656c697a65,rev?* 4 | G04 #@! TF.SameCoordinates,PX8e95450PY5aa2c88* 5 | G04 #@! TF.FileFunction,Copper,L2,Bot* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW 5.1.5-52549c5~84~ubuntu16.04.1) date 2020-01-12 22:05:50* 10 | %MOMM*% 11 | %LPD*% 12 | G04 APERTURE LIST* 13 | %ADD10R,1.700000X1.700000*% 14 | %ADD11O,1.700000X1.700000*% 15 | G04 APERTURE END LIST* 16 | D10* 17 | X-127690800Y69961400D03* 18 | D11* 19 | X-125150800Y69961400D03* 20 | X-127690800Y67421400D03* 21 | X-125150800Y67421400D03* 22 | X-127690800Y64881400D03* 23 | X-125150800Y64881400D03* 24 | X-127690800Y62341400D03* 25 | X-125150800Y62341400D03* 26 | X-127690800Y59801400D03* 27 | X-125150800Y59801400D03* 28 | D10* 29 | X-119490800Y78161400D03* 30 | D11* 31 | X-119490800Y75621400D03* 32 | X-116950800Y78161400D03* 33 | X-116950800Y75621400D03* 34 | X-114410800Y78161400D03* 35 | X-114410800Y75621400D03* 36 | X-111870800Y78161400D03* 37 | X-111870800Y75621400D03* 38 | X-109330800Y78161400D03* 39 | X-109330800Y75621400D03* 40 | X-92530800Y75621400D03* 41 | X-92530800Y78161400D03* 42 | X-95070800Y75621400D03* 43 | X-95070800Y78161400D03* 44 | X-97610800Y75621400D03* 45 | X-97610800Y78161400D03* 46 | X-100150800Y75621400D03* 47 | X-100150800Y78161400D03* 48 | X-102690800Y75621400D03* 49 | D10* 50 | X-102690800Y78161400D03* 51 | D11* 52 | X-125150800Y43001400D03* 53 | X-127690800Y43001400D03* 54 | X-125150800Y45541400D03* 55 | X-127690800Y45541400D03* 56 | X-125150800Y48081400D03* 57 | X-127690800Y48081400D03* 58 | X-125150800Y50621400D03* 59 | X-127690800Y50621400D03* 60 | X-125150800Y53161400D03* 61 | D10* 62 | X-127690800Y53161400D03* 63 | X-115690800Y57961400D03* 64 | D11* 65 | X-113150800Y57961400D03* 66 | X-115690800Y55421400D03* 67 | X-113150800Y55421400D03* 68 | X-115690800Y52881400D03* 69 | X-113150800Y52881400D03* 70 | X-115690800Y50341400D03* 71 | X-113150800Y50341400D03* 72 | X-115690800Y47801400D03* 73 | X-113150800Y47801400D03* 74 | D10* 75 | X-107490800Y66161400D03* 76 | D11* 77 | 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TF.FileFunction,NonPlated,1,2,NPTH 7 | FMAT,2 8 | INCH 9 | T1C0.0315 10 | T2C0.0787 11 | % 12 | G90 13 | G05 14 | T1 15 | X-3.6709Y0.9129 16 | X-3.6709Y0.86 17 | X-3.6709Y0.8071 18 | X-3.6709Y0.7542 19 | X-3.6709Y0.7013 20 | X-4.5742Y2.6656 21 | X-4.5213Y2.6656 22 | X-4.4684Y2.6657 23 | X-4.4156Y2.6657 24 | X-4.3627Y2.6658 25 | X-3.6058Y0.1658 26 | X-3.5529Y0.1658 27 | X-3.5Y0.1658 28 | X-3.4471Y0.1658 29 | X-3.3942Y0.1658 30 | X-4.2811Y1.3853 31 | X-4.2811Y1.3324 32 | X-4.2811Y1.2795 33 | X-4.2811Y1.2266 34 | X-4.2811Y1.1737 35 | X-4.5743Y2.8823 36 | X-4.5214Y2.8823 37 | X-4.4685Y2.8823 38 | X-4.4156Y2.8823 39 | X-4.3627Y2.8823 40 | X-3.1283Y0.531 41 | X-3.1283Y0.4781 42 | X-3.1283Y0.4252 43 | X-3.1283Y0.3723 44 | X-3.1283Y0.3194 45 | X-2.8617Y1.8587 46 | X-2.8088Y1.8587 47 | X-2.7559Y1.8587 48 | X-2.703Y1.8587 49 | X-2.6501Y1.8587 50 | X-4.1433Y1.3853 51 | X-4.1433Y1.3324 52 | X-4.1433Y1.2795 53 | X-4.1433Y1.2266 54 | X-4.1433Y1.1737 55 | X-4.1019Y2.4099 56 | X-4.049Y2.4099 57 | X-3.9961Y2.4099 58 | X-3.9432Y2.4099 59 | X-3.8902Y2.4099 60 | X-2.8617Y1.7209 61 | X-2.8088Y1.7209 62 | X-2.7559Y1.7209 63 | X-2.703Y1.7209 64 | X-2.6501Y1.7209 65 | X-4.7536Y1.8775 66 | X-4.7536Y1.8246 67 | X-4.7536Y1.7717 68 | X-4.7536Y1.7187 69 | X-4.7536Y1.6658 70 | X-3.1373Y1.2988 71 | X-3.0844Y1.2988 72 | X-3.0315Y1.2988 73 | X-2.9786Y1.2988 74 | X-2.9257Y1.2988 75 | X-4.1018Y2.1931 76 | X-4.0489Y2.1932 77 | X-3.996Y2.1932 78 | X-3.9431Y2.1933 79 | X-3.8902Y2.1933 80 | X-3.8066Y2.8036 81 | X-3.7537Y2.8036 82 | X-3.7008Y2.8036 83 | X-3.6479Y2.8036 84 | X-3.595Y2.8036 85 | X-3.3363Y0.531 86 | X-3.3363Y0.4781 87 | X-3.3363Y0.4252 88 | X-3.3363Y0.3723 89 | X-3.3363Y0.3194 90 | X-3.8087Y0.9129 91 | X-3.8087Y0.86 92 | X-3.8087Y0.8071 93 | X-3.8087Y0.7542 94 | X-3.8087Y0.7013 95 | X-3.6294Y1.9375 96 | X-3.5765Y1.9375 97 | X-3.5236Y1.9375 98 | X-3.4707Y1.9375 99 | X-3.4178Y1.9375 100 | X-4.6158Y1.8775 101 | X-4.6158Y1.8246 102 | X-4.6158Y1.7717 103 | X-4.6158Y1.7187 104 | X-4.6158Y1.6658 105 | X-3.1373Y1.465 106 | X-3.0844Y1.465 107 | X-3.0315Y1.465 108 | X-2.9786Y1.465 109 | X-2.9257Y1.465 110 | X-3.3342Y2.3312 111 | X-3.2813Y2.3312 112 | X-3.2283Y2.3312 113 | X-3.1754Y2.3312 114 | X-3.1225Y2.3312 115 | X-3.8066Y2.6658 116 | X-3.7537Y2.6658 117 | X-3.7008Y2.6658 118 | X-3.6479Y2.6658 119 | X-3.595Y2.6658 120 | X-3.6058Y-0.0004 121 | X-3.5529Y-0.0004 122 | X-3.5Y-0.0004 123 | X-3.4471Y-0.0004 124 | X-3.3942Y-0.0004 125 | X-3.6293Y1.7207 126 | X-3.5764Y1.7207 127 | X-3.5236Y1.7208 128 | X-3.4707Y1.7209 129 | X-3.4178Y1.7209 130 | X-3.3342Y2.1934 131 | X-3.2813Y2.1934 132 | X-3.2283Y2.1934 133 | X-3.1754Y2.1934 134 | X-3.1225Y2.1934 135 | T2 136 | X-1.7989Y1.4945 137 | X-4.3894Y2.4394 138 | X-3.917Y1.967 139 | X-2.7359Y1.4945 140 | X-3.0988Y-0.03 141 | X-4.7445Y-0.03 142 | X-4.8618Y2.9119 143 | X-3.0988Y0.6787 144 | X-3.2162Y2.9119 145 | X-2.7437Y2.4394 146 | X-4.3894Y1.7308 147 | X-3.6807Y2.4394 148 | X-3.8074Y-0.03 149 | X-3.4445Y0.7859 150 | X-3.917Y1.2583 151 | X-4.1532Y2.9119 152 | X-2.2713Y1.967 153 | X-3.4445Y1.4945 154 | X-4.8618Y2.2032 155 | X-3.2083Y1.967 156 | T0 157 | M30 158 | -------------------------------------------------------------------------------- /pcbs/frame_corners/panelized/upload2/output.panelized-PTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ; DRILL file {KiCad 5.1.5-52549c5~84~ubuntu16.04.1} date Sun 12 Jan 2020 10:05:56 PM PST 3 | ; FORMAT={-:-/ absolute / inch / decimal} 4 | ; #@! TF.CreationDate,2020-01-12T22:05:56-08:00 5 | ; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.5-52549c5~84~ubuntu16.04.1 6 | ; #@! TF.FileFunction,Plated,1,2,PTH 7 | FMAT,2 8 | INCH 9 | T1C0.0394 10 | % 11 | G90 12 | G05 13 | T1 14 | X-2.6256Y1.6599 15 | X-2.6256Y1.5599 16 | X-2.5256Y1.6599 17 | X-2.5256Y1.5599 18 | X-2.4256Y1.6599 19 | X-2.4256Y1.5599 20 | X-2.3256Y1.6599 21 | X-2.3256Y1.5599 22 | X-2.2256Y1.6599 23 | X-2.2256Y1.5599 24 | X-5.0272Y2.093 25 | X-5.0272Y1.993 26 | X-5.0272Y1.893 27 | X-5.0272Y1.793 28 | X-5.0272Y1.693 29 | X-4.9272Y2.093 30 | X-4.9272Y1.993 31 | X-4.9272Y1.893 32 | X-4.9272Y1.793 33 | X-4.9272Y1.693 34 | X-3.5705Y2.6048 35 | X-3.5705Y2.5048 36 | X-3.4705Y2.6048 37 | X-3.4705Y2.5048 38 | X-3.3705Y2.6048 39 | X-3.3705Y2.5048 40 | X-3.2705Y2.6048 41 | X-3.2705Y2.5048 42 | X-3.1705Y2.6048 43 | X-3.1705Y2.5048 44 | X-4.0823Y1.1481 45 | X-4.0823Y1.0481 46 | X-4.0823Y0.9481 47 | X-4.0823Y0.8481 48 | X-4.0823Y0.7481 49 | X-3.9823Y1.1481 50 | X-3.9823Y1.0481 51 | X-3.9823Y0.9481 52 | X-3.9823Y0.8481 53 | X-3.9823Y0.7481 54 | X-4.5548Y1.6205 55 | X-4.5548Y1.5205 56 | X-4.5548Y1.4205 57 | X-4.5548Y1.3205 58 | X-4.5548Y1.2205 59 | X-4.4548Y1.6205 60 | X-4.4548Y1.5205 61 | X-4.4548Y1.4205 62 | X-4.4548Y1.3205 63 | X-4.4548Y1.2205 64 | X-4.7044Y3.0772 65 | X-4.7044Y2.9772 66 | X-4.6044Y3.0772 67 | X-4.6044Y2.9772 68 | X-4.5044Y3.0772 69 | X-4.5044Y2.9772 70 | X-4.4044Y3.0772 71 | X-4.4044Y2.9772 72 | X-4.3044Y3.0772 73 | X-4.3044Y2.9772 74 | X-4.2319Y2.6048 75 | X-4.2319Y2.5048 76 | X-4.1319Y2.6048 77 | X-4.1319Y2.5048 78 | X-4.0319Y2.6048 79 | X-4.0319Y2.5048 80 | X-3.9319Y2.6048 81 | X-3.9319Y2.5048 82 | X-3.8319Y2.6048 83 | X-3.8319Y2.5048 84 | X-3.6563Y-0.0953 85 | X-3.6563Y-0.1953 86 | X-3.5563Y-0.0953 87 | X-3.5563Y-0.1953 88 | X-3.4563Y-0.0953 89 | X-3.4563Y-0.1953 90 | X-3.3563Y-0.0953 91 | X-3.3563Y-0.1953 92 | X-3.2563Y-0.0953 93 | X-3.2563Y-0.1953 94 | X-4.0429Y3.0772 95 | X-4.0429Y2.9772 96 | X-3.9429Y3.0772 97 | X-3.9429Y2.9772 98 | X-3.8429Y3.0772 99 | X-3.8429Y2.9772 100 | X-3.7429Y3.0772 101 | X-3.7429Y2.9772 102 | X-3.6429Y3.0772 103 | X-3.6429Y2.9772 104 | X-3.6099Y1.3371 105 | X-3.6099Y1.2371 106 | X-3.6099Y1.1371 107 | X-3.6099Y1.0371 108 | X-3.6099Y0.9371 109 | X-3.5099Y1.3371 110 | X-3.5099Y1.2371 111 | X-3.5099Y1.1371 112 | X-3.5099Y1.0371 113 | X-3.5099Y0.9371 114 | X-4.3177Y-0.0953 115 | X-4.3177Y-0.1953 116 | X-4.2177Y-0.0953 117 | X-4.2177Y-0.1953 118 | X-4.1177Y-0.0953 119 | X-4.1177Y-0.1953 120 | X-4.0177Y-0.0953 121 | X-4.0177Y-0.1953 122 | X-3.9177Y-0.0953 123 | X-3.9177Y-0.1953 124 | X-3.0981Y2.1323 125 | X-3.0981Y2.0323 126 | X-2.9981Y2.1323 127 | X-2.9981Y2.0323 128 | X-2.8981Y2.1323 129 | X-2.8981Y2.0323 130 | X-2.7981Y2.1323 131 | X-2.7981Y2.0323 132 | X-2.6981Y2.1323 133 | X-2.6981Y2.0323 134 | X-5.0272Y2.7544 135 | X-5.0272Y2.6544 136 | X-5.0272Y2.5544 137 | X-5.0272Y2.4544 138 | X-5.0272Y2.3544 139 | X-4.9272Y2.7544 140 | X-4.9272Y2.6544 141 | X-4.9272Y2.5544 142 | X-4.9272Y2.4544 143 | X-4.9272Y2.3544 144 | X-4.5548Y2.2819 145 | X-4.5548Y2.1819 146 | X-4.5548Y2.0819 147 | X-4.5548Y1.9819 148 | X-4.5548Y1.8819 149 | X-4.4548Y2.2819 150 | X-4.4548Y2.1819 151 | X-4.4548Y2.0819 152 | X-4.4548Y1.9819 153 | X-4.4548Y1.8819 154 | X-3.0334Y1.1889 155 | X-3.0334Y1.0889 156 | X-3.0334Y0.9889 157 | X-3.0334Y0.8889 158 | X-3.0334Y0.7889 159 | X-2.9334Y1.1889 160 | X-2.9334Y1.0889 161 | X-2.9334Y0.9889 162 | X-2.9334Y0.8889 163 | X-2.9334Y0.7889 164 | X-4.0823Y1.8095 165 | X-4.0823Y1.7095 166 | X-4.0823Y1.6095 167 | X-4.0823Y1.5095 168 | X-4.0823Y1.4095 169 | X-3.9823Y1.8095 170 | X-3.9823Y1.7095 171 | X-3.9823Y1.6095 172 | X-3.9823Y1.5095 173 | X-3.9823Y1.4095 174 | X-3.0334Y0.5275 175 | X-3.0334Y0.4275 176 | X-3.0334Y0.3275 177 | X-3.0334Y0.2275 178 | X-3.0334Y0.1275 179 | X-2.9334Y0.5275 180 | X-2.9334Y0.4275 181 | X-2.9334Y0.3275 182 | X-2.9334Y0.2275 183 | X-2.9334Y0.1275 184 | X-3.7595Y2.1323 185 | X-3.7595Y2.0323 186 | X-3.6595Y2.1323 187 | X-3.6595Y2.0323 188 | X-3.5595Y2.1323 189 | X-3.5595Y2.0323 190 | X-3.4595Y2.1323 191 | X-3.4595Y2.0323 192 | X-3.3595Y2.1323 193 | X-3.3595Y2.0323 194 | X-3.287Y1.6599 195 | X-3.287Y1.5599 196 | X-3.187Y1.6599 197 | X-3.187Y1.5599 198 | X-3.087Y1.6599 199 | X-3.087Y1.5599 200 | X-2.987Y1.6599 201 | X-2.987Y1.5599 202 | X-2.887Y1.6599 203 | X-2.887Y1.5599 204 | X-3.6099Y0.6756 205 | X-3.6099Y0.5756 206 | X-3.6099Y0.4756 207 | X-3.6099Y0.3756 208 | X-3.6099Y0.2756 209 | X-3.5099Y0.6756 210 | X-3.5099Y0.5756 211 | X-3.5099Y0.4756 212 | X-3.5099Y0.3756 213 | X-3.5099Y0.2756 214 | T0 215 | M30 216 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/frame_corners-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # Connector_Generic_Conn_02x08_Odd_Even 5 | # 6 | DEF Connector_Generic_Conn_02x08_Odd_Even J 0 40 Y N 1 F N 7 | F0 "J" 50 400 50 H V C CNN 8 | F1 "Connector_Generic_Conn_02x08_Odd_Even" 50 -500 50 H V C CNN 9 | F2 "" 0 0 50 H I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | $FPLIST 12 | Connector*:*_2x??_* 13 | $ENDFPLIST 14 | DRAW 15 | S -50 -395 0 -405 1 1 6 N 16 | S -50 -295 0 -305 1 1 6 N 17 | S -50 -195 0 -205 1 1 6 N 18 | S -50 -95 0 -105 1 1 6 N 19 | S -50 5 0 -5 1 1 6 N 20 | S -50 105 0 95 1 1 6 N 21 | S -50 205 0 195 1 1 6 N 22 | S -50 305 0 295 1 1 6 N 23 | S -50 350 150 -450 1 1 10 f 24 | S 150 -395 100 -405 1 1 6 N 25 | S 150 -295 100 -305 1 1 6 N 26 | S 150 -195 100 -205 1 1 6 N 27 | S 150 -95 100 -105 1 1 6 N 28 | S 150 5 100 -5 1 1 6 N 29 | S 150 105 100 95 1 1 6 N 30 | S 150 205 100 195 1 1 6 N 31 | S 150 305 100 295 1 1 6 N 32 | X Pin_1 1 -200 300 150 R 50 50 1 1 P 33 | X Pin_10 10 300 -100 150 L 50 50 1 1 P 34 | X Pin_11 11 -200 -200 150 R 50 50 1 1 P 35 | X Pin_12 12 300 -200 150 L 50 50 1 1 P 36 | X Pin_13 13 -200 -300 150 R 50 50 1 1 P 37 | X Pin_14 14 300 -300 150 L 50 50 1 1 P 38 | X Pin_15 15 -200 -400 150 R 50 50 1 1 P 39 | X Pin_16 16 300 -400 150 L 50 50 1 1 P 40 | X Pin_2 2 300 300 150 L 50 50 1 1 P 41 | X Pin_3 3 -200 200 150 R 50 50 1 1 P 42 | X Pin_4 4 300 200 150 L 50 50 1 1 P 43 | X Pin_5 5 -200 100 150 R 50 50 1 1 P 44 | X Pin_6 6 300 100 150 L 50 50 1 1 P 45 | X Pin_7 7 -200 0 150 R 50 50 1 1 P 46 | X Pin_8 8 300 0 150 L 50 50 1 1 P 47 | X Pin_9 9 -200 -100 150 R 50 50 1 1 P 48 | ENDDRAW 49 | ENDDEF 50 | # 51 | # Connector_Generic_Conn_02x20_Odd_Even 52 | # 53 | DEF Connector_Generic_Conn_02x20_Odd_Even J 0 40 Y N 1 F N 54 | F0 "J" 50 1000 50 H V C CNN 55 | F1 "Connector_Generic_Conn_02x20_Odd_Even" 50 -1100 50 H V C CNN 56 | F2 "" 0 0 50 H I C CNN 57 | F3 "" 0 0 50 H I C CNN 58 | $FPLIST 59 | Connector*:*_2x??_* 60 | $ENDFPLIST 61 | DRAW 62 | S -50 -995 0 -1005 1 1 6 N 63 | S -50 -895 0 -905 1 1 6 N 64 | S -50 -795 0 -805 1 1 6 N 65 | S -50 -695 0 -705 1 1 6 N 66 | S -50 -595 0 -605 1 1 6 N 67 | S -50 -495 0 -505 1 1 6 N 68 | S -50 -395 0 -405 1 1 6 N 69 | S -50 -295 0 -305 1 1 6 N 70 | S -50 -195 0 -205 1 1 6 N 71 | S -50 -95 0 -105 1 1 6 N 72 | S -50 5 0 -5 1 1 6 N 73 | S -50 105 0 95 1 1 6 N 74 | S -50 205 0 195 1 1 6 N 75 | S -50 305 0 295 1 1 6 N 76 | S -50 405 0 395 1 1 6 N 77 | S -50 505 0 495 1 1 6 N 78 | S -50 605 0 595 1 1 6 N 79 | S -50 705 0 695 1 1 6 N 80 | S -50 805 0 795 1 1 6 N 81 | S -50 905 0 895 1 1 6 N 82 | S -50 950 150 -1050 1 1 10 f 83 | S 150 -995 100 -1005 1 1 6 N 84 | S 150 -895 100 -905 1 1 6 N 85 | S 150 -795 100 -805 1 1 6 N 86 | S 150 -695 100 -705 1 1 6 N 87 | S 150 -595 100 -605 1 1 6 N 88 | S 150 -495 100 -505 1 1 6 N 89 | S 150 -395 100 -405 1 1 6 N 90 | S 150 -295 100 -305 1 1 6 N 91 | S 150 -195 100 -205 1 1 6 N 92 | S 150 -95 100 -105 1 1 6 N 93 | S 150 5 100 -5 1 1 6 N 94 | S 150 105 100 95 1 1 6 N 95 | S 150 205 100 195 1 1 6 N 96 | S 150 305 100 295 1 1 6 N 97 | S 150 405 100 395 1 1 6 N 98 | S 150 505 100 495 1 1 6 N 99 | S 150 605 100 595 1 1 6 N 100 | S 150 705 100 695 1 1 6 N 101 | S 150 805 100 795 1 1 6 N 102 | S 150 905 100 895 1 1 6 N 103 | X Pin_1 1 -200 900 150 R 50 50 1 1 P 104 | X Pin_10 10 300 500 150 L 50 50 1 1 P 105 | X Pin_11 11 -200 400 150 R 50 50 1 1 P 106 | X Pin_12 12 300 400 150 L 50 50 1 1 P 107 | X Pin_13 13 -200 300 150 R 50 50 1 1 P 108 | X Pin_14 14 300 300 150 L 50 50 1 1 P 109 | X Pin_15 15 -200 200 150 R 50 50 1 1 P 110 | X Pin_16 16 300 200 150 L 50 50 1 1 P 111 | X Pin_17 17 -200 100 150 R 50 50 1 1 P 112 | X Pin_18 18 300 100 150 L 50 50 1 1 P 113 | X Pin_19 19 -200 0 150 R 50 50 1 1 P 114 | X Pin_2 2 300 900 150 L 50 50 1 1 P 115 | X Pin_20 20 300 0 150 L 50 50 1 1 P 116 | X Pin_21 21 -200 -100 150 R 50 50 1 1 P 117 | X Pin_22 22 300 -100 150 L 50 50 1 1 P 118 | X Pin_23 23 -200 -200 150 R 50 50 1 1 P 119 | X Pin_24 24 300 -200 150 L 50 50 1 1 P 120 | X Pin_25 25 -200 -300 150 R 50 50 1 1 P 121 | X Pin_26 26 300 -300 150 L 50 50 1 1 P 122 | X Pin_27 27 -200 -400 150 R 50 50 1 1 P 123 | X Pin_28 28 300 -400 150 L 50 50 1 1 P 124 | X Pin_29 29 -200 -500 150 R 50 50 1 1 P 125 | X Pin_3 3 -200 800 150 R 50 50 1 1 P 126 | X Pin_30 30 300 -500 150 L 50 50 1 1 P 127 | X Pin_31 31 -200 -600 150 R 50 50 1 1 P 128 | X Pin_32 32 300 -600 150 L 50 50 1 1 P 129 | X Pin_33 33 -200 -700 150 R 50 50 1 1 P 130 | X Pin_34 34 300 -700 150 L 50 50 1 1 P 131 | X Pin_35 35 -200 -800 150 R 50 50 1 1 P 132 | X Pin_36 36 300 -800 150 L 50 50 1 1 P 133 | X Pin_37 37 -200 -900 150 R 50 50 1 1 P 134 | X Pin_38 38 300 -900 150 L 50 50 1 1 P 135 | X Pin_39 39 -200 -1000 150 R 50 50 1 1 P 136 | X Pin_4 4 300 800 150 L 50 50 1 1 P 137 | X Pin_40 40 300 -1000 150 L 50 50 1 1 P 138 | X Pin_5 5 -200 700 150 R 50 50 1 1 P 139 | X Pin_6 6 300 700 150 L 50 50 1 1 P 140 | X Pin_7 7 -200 600 150 R 50 50 1 1 P 141 | X Pin_8 8 300 600 150 L 50 50 1 1 P 142 | X Pin_9 9 -200 500 150 R 50 50 1 1 P 143 | ENDDRAW 144 | ENDDEF 145 | # 146 | # power_+3V3 147 | # 148 | DEF power_+3V3 #PWR 0 0 Y Y 1 F P 149 | F0 "#PWR" 0 -150 50 H I C CNN 150 | F1 "power_+3V3" 0 140 50 H V C CNN 151 | F2 "" 0 0 50 H I C CNN 152 | F3 "" 0 0 50 H I C CNN 153 | ALIAS +3.3V 154 | DRAW 155 | P 2 0 1 0 -30 50 0 100 N 156 | P 2 0 1 0 0 0 0 100 N 157 | P 2 0 1 0 0 100 30 50 N 158 | X +3V3 1 0 0 0 U 50 50 1 1 W N 159 | ENDDRAW 160 | ENDDEF 161 | # 162 | # power_+5V 163 | # 164 | DEF power_+5V #PWR 0 0 Y Y 1 F P 165 | F0 "#PWR" 0 -150 50 H I C CNN 166 | F1 "power_+5V" 0 140 50 H V C CNN 167 | F2 "" 0 0 50 H I C CNN 168 | F3 "" 0 0 50 H I C CNN 169 | DRAW 170 | P 2 0 1 0 -30 50 0 100 N 171 | P 2 0 1 0 0 0 0 100 N 172 | P 2 0 1 0 0 100 30 50 N 173 | X +5V 1 0 0 0 U 50 50 1 1 W N 174 | ENDDRAW 175 | ENDDEF 176 | # 177 | # power_GND 178 | # 179 | DEF power_GND #PWR 0 0 Y Y 1 F P 180 | F0 "#PWR" 0 -250 50 H I C CNN 181 | F1 "power_GND" 0 -150 50 H V C CNN 182 | F2 "" 0 0 50 H I C CNN 183 | F3 "" 0 0 50 H I C CNN 184 | DRAW 185 | P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N 186 | X GND 1 0 0 0 D 50 50 1 1 W N 187 | ENDDRAW 188 | ENDDEF 189 | # 190 | #End Library 191 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/frame_corners.pro: -------------------------------------------------------------------------------- 1 | update=Monday, January 06, 2020 at 11:45:33 PM 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [pcbnew] 9 | version=1 10 | LastNetListRead= 11 | UseCmpFile=1 12 | PadDrill=0.600000000000 13 | PadDrillOvalY=0.600000000000 14 | PadSizeH=1.500000000000 15 | PadSizeV=1.500000000000 16 | PcbTextSizeV=1.500000000000 17 | PcbTextSizeH=1.500000000000 18 | PcbTextThickness=0.300000000000 19 | ModuleTextSizeV=1.000000000000 20 | ModuleTextSizeH=1.000000000000 21 | ModuleTextSizeThickness=0.150000000000 22 | SolderMaskClearance=0.000000000000 23 | SolderMaskMinWidth=0.000000000000 24 | DrawSegmentWidth=0.200000000000 25 | BoardOutlineThickness=0.100000000000 26 | ModuleOutlineThickness=0.150000000000 27 | [cvpcb] 28 | version=1 29 | NetIExt=net 30 | [eeschema] 31 | version=1 32 | LibDir= 33 | [eeschema/libraries] 34 | [schematic_editor] 35 | version=1 36 | PageLayoutDescrFile= 37 | PlotDirectoryName= 38 | SubpartIdSeparator=0 39 | SubpartFirstId=65 40 | NetFmtName=Pcbnew 41 | SpiceAjustPassiveValues=0 42 | LabSize=50 43 | ERC_TestSimilarLabels=1 44 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gerbers/frame_corners-B_Paste.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 2 | G04 #@! TF.CreationDate,2020-01-11T16:24:58-08:00* 3 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 4 | G04 #@! TF.SameCoordinates,PXe8fce300PYe19b7798* 5 | G04 #@! TF.FileFunction,Paste,Bot* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 16:24:58* 10 | %MOMM*% 11 | %LPD*% 12 | G04 APERTURE LIST* 13 | G04 APERTURE END LIST* 14 | M02* 15 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gerbers/frame_corners-Edge_Cuts.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 2 | G04 #@! TF.CreationDate,2020-01-11T16:24:58-08:00* 3 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 4 | G04 #@! TF.SameCoordinates,PXe8fce300PYe19b7798* 5 | G04 #@! TF.FileFunction,Profile,NP* 6 | %FSLAX46Y46*% 7 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 8 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 16:24:58* 9 | %MOMM*% 10 | %LPD*% 11 | G04 APERTURE LIST* 12 | %ADD10C,0.050000*% 13 | G04 APERTURE END LIST* 14 | D10* 15 | X0Y0D02* 16 | X0Y19050000D01* 17 | X52070000Y0D02* 18 | X0Y0D01* 19 | X52070000Y19050000D02* 20 | X52070000Y0D01* 21 | X0Y19050000D02* 22 | X52070000Y19050000D01* 23 | M02* 24 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gerbers/frame_corners-F_Paste.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 2 | G04 #@! TF.CreationDate,2020-01-11T16:24:58-08:00* 3 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 4 | G04 #@! TF.SameCoordinates,PXe8fce300PYe19b7798* 5 | G04 #@! TF.FileFunction,Paste,Top* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 16:24:58* 10 | %MOMM*% 11 | %LPD*% 12 | G04 APERTURE LIST* 13 | G04 APERTURE END LIST* 14 | M02* 15 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gerbers/frame_corners-F_SilkS.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5)-3* 2 | G04 #@! TF.CreationDate,2020-01-11T16:24:58-08:00* 3 | G04 #@! TF.ProjectId,frame_corners,6672616d-655f-4636-9f72-6e6572732e6b,rev?* 4 | G04 #@! TF.SameCoordinates,PXe8fce300PYe19b7798* 5 | G04 #@! TF.FileFunction,Legend,Top* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW (5.1.5)-3) date 2020-01-11 16:24:58* 10 | %MOMM*% 11 | %LPD*% 12 | G04 APERTURE LIST* 13 | G04 APERTURE END LIST* 14 | M02* 15 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gerbers/frame_corners-NPTH-drl_map.ps: -------------------------------------------------------------------------------- 1 | %!PS-Adobe-3.0 2 | %%Creator: PCBNEW 3 | %%CreationDate: Sat Jan 11 16:25:09 2020 4 | %%Title: C:\Users\Tom Verbeure\projects\cube2\pcbs\gpio2hub75\gerbers\frame_corners-NPTH-drl_map.ps 5 | %%Pages: 1 6 | %%PageOrder: Ascend 7 | %%BoundingBox: 0 0 596 842 8 | %%DocumentMedia: A4 595 842 0 () () 9 | %%Orientation: Landscape 10 | %%EndComments 11 | %%BeginProlog 12 | /line { newpath moveto lineto stroke } bind def 13 | /cir0 { newpath 0 360 arc stroke } bind def 14 | /cir1 { newpath 0 360 arc gsave fill grestore stroke } bind def 15 | /cir2 { newpath 0 360 arc gsave fill grestore stroke } bind def 16 | /arc0 { newpath arc stroke } bind def 17 | /arc1 { newpath 4 index 4 index moveto arc closepath gsave fill 18 | grestore stroke } bind def 19 | /arc2 { newpath 4 index 4 index moveto arc closepath gsave fill 20 | grestore stroke } bind def 21 | /poly0 { stroke } bind def 22 | /poly1 { closepath gsave fill grestore stroke } bind def 23 | /poly2 { closepath gsave fill grestore stroke } bind def 24 | /rect0 { rectstroke } bind def 25 | /rect1 { rectfill } bind def 26 | /rect2 { rectfill } bind def 27 | /linemode0 { 0 setlinecap 0 setlinejoin 0 setlinewidth } bind def 28 | /linemode1 { 1 setlinecap 1 setlinejoin } bind def 29 | /dashedline { [200] 100 setdash } bind def 30 | /solidline { [] 0 setdash } bind def 31 | /phantomshow { moveto 32 | /KicadFont findfont 0.000001 scalefont setfont 33 | show } bind def 34 | /textshow { gsave 35 | findfont exch scalefont setfont concat 1 scale 0 0 moveto show 36 | } bind def 37 | /reencodefont { 38 | findfont dup length dict begin 39 | { 1 index /FID ne 40 | { def } 41 | { pop pop } ifelse 42 | } forall 43 | /Encoding ISOLatin1Encoding def 44 | currentdict 45 | end } bind def 46 | /KicadFont /Helvetica reencodefont definefont pop 47 | /KicadFont-Bold /Helvetica-Bold reencodefont definefont pop 48 | /KicadFont-Oblique /Helvetica-Oblique reencodefont definefont pop 49 | /KicadFont-BoldOblique /Helvetica-BoldOblique reencodefont definefont pop 50 | %%EndProlog 51 | %%Page: 1 1 52 | %%BeginPageSetup 53 | gsave 54 | 0.0072 0.0072 scale 55 | linemode1 56 | 82680 0 translate 90 rotate 57 | 150 setlinewidth 58 | %%EndPageSetup 59 | 0 0 0 setrgbcolor 60 | 59.0551 setlinewidth 61 | newpath 62 | 27715 46626 moveto 63 | 27715 69126 lineto 64 | stroke 65 | 0 0 0 setrgbcolor 66 | newpath 67 | 89215 46626 moveto 68 | 27715 46626 lineto 69 | stroke 70 | 0 0 0 setrgbcolor 71 | newpath 72 | 89215 69126 moveto 73 | 89215 46626 lineto 74 | stroke 75 | 0 0 0 setrgbcolor 76 | newpath 77 | 27715 69126 moveto 78 | 89215 69126 lineto 79 | stroke 80 | 78.7394 setlinewidth 81 | 118.11 setlinewidth 82 | 0 0 0 setrgbcolor 83 | 0 0 0 setrgbcolor 84 | newpath 85 | 28813.1 44763 moveto 86 | 28813.1 45944.1 lineto 87 | 29094.4 45944.1 lineto 88 | 29263.1 45887.8 lineto 89 | 29375.6 45775.3 lineto 90 | 29431.8 45662.8 lineto 91 | 29488.1 45437.9 lineto 92 | 29488.1 45269.1 lineto 93 | 29431.8 45044.2 lineto 94 | 29375.6 44931.7 lineto 95 | 29263.1 44819.2 lineto 96 | 29094.4 44763 lineto 97 | 28813.1 44763 lineto 98 | stroke 99 | newpath 100 | 29994.2 44763 moveto 101 | 29994.2 45550.4 lineto 102 | stroke 103 | newpath 104 | 29994.2 45325.4 moveto 105 | 30050.5 45437.9 lineto 106 | 30106.7 45494.1 lineto 107 | 30219.2 45550.4 lineto 108 | 30331.7 45550.4 lineto 109 | stroke 110 | newpath 111 | 30725.4 44763 moveto 112 | 30725.4 45550.4 lineto 113 | stroke 114 | newpath 115 | 30725.4 45944.1 moveto 116 | 30669.2 45887.8 lineto 117 | 30725.4 45831.6 lineto 118 | 30781.6 45887.8 lineto 119 | 30725.4 45944.1 lineto 120 | 30725.4 45831.6 lineto 121 | stroke 122 | newpath 123 | 31456.6 44763 moveto 124 | 31344.1 44819.2 lineto 125 | 31287.8 44931.7 lineto 126 | 31287.8 45944.1 lineto 127 | stroke 128 | newpath 129 | 32075.2 44763 moveto 130 | 31962.8 44819.2 lineto 131 | 31906.5 44931.7 lineto 132 | 31906.5 45944.1 lineto 133 | stroke 134 | newpath 135 | 33425.1 44763 moveto 136 | 33425.1 45944.1 lineto 137 | 33818.8 45100.4 lineto 138 | 34212.5 45944.1 lineto 139 | 34212.5 44763 lineto 140 | stroke 141 | newpath 142 | 35281.1 44763 moveto 143 | 35281.1 45381.6 lineto 144 | 35224.8 45494.1 lineto 145 | 35112.4 45550.4 lineto 146 | 34887.4 45550.4 lineto 147 | 34774.9 45494.1 lineto 148 | stroke 149 | newpath 150 | 35281.1 44819.2 moveto 151 | 35168.6 44763 lineto 152 | 34887.4 44763 lineto 153 | 34774.9 44819.2 lineto 154 | 34718.7 44931.7 lineto 155 | 34718.7 45044.2 lineto 156 | 34774.9 45156.7 lineto 157 | 34887.4 45212.9 lineto 158 | 35168.6 45212.9 lineto 159 | 35281.1 45269.1 lineto 160 | stroke 161 | newpath 162 | 35843.5 45550.4 moveto 163 | 35843.5 44369.2 lineto 164 | stroke 165 | newpath 166 | 35843.5 45494.1 moveto 167 | 35956 45550.4 lineto 168 | 36181 45550.4 lineto 169 | 36293.5 45494.1 lineto 170 | 36349.7 45437.9 lineto 171 | 36405.9 45325.4 lineto 172 | 36405.9 44987.9 lineto 173 | 36349.7 44875.4 lineto 174 | 36293.5 44819.2 lineto 175 | 36181 44763 lineto 176 | 35956 44763 lineto 177 | 35843.5 44819.2 lineto 178 | stroke 179 | newpath 180 | 36912.1 44875.4 moveto 181 | 36968.4 44819.2 lineto 182 | 36912.1 44763 lineto 183 | 36855.9 44819.2 lineto 184 | 36912.1 44875.4 lineto 185 | 36912.1 44763 lineto 186 | stroke 187 | newpath 188 | 36912.1 45494.1 moveto 189 | 36968.4 45437.9 lineto 190 | 36912.1 45381.6 lineto 191 | 36855.9 45437.9 lineto 192 | 36912.1 45494.1 lineto 193 | 36912.1 45381.6 lineto 194 | stroke 195 | showpage 196 | grestore 197 | %%EOF 198 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gerbers/frame_corners-NPTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ; DRILL file {KiCad (5.1.5)-3} date 1/11/2020 4:25:07 PM 3 | ; FORMAT={-:-/ absolute / inch / decimal} 4 | ; #@! TF.CreationDate,2020-01-11T16:25:07-08:00 5 | ; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5)-3 6 | ; #@! TF.FileFunction,NonPlated,1,2,NPTH 7 | FMAT,2 8 | INCH 9 | % 10 | G90 11 | G05 12 | T0 13 | M30 14 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gerbers/frame_corners-PTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ; DRILL file {KiCad (5.1.5)-3} date 1/11/2020 4:25:07 PM 3 | ; FORMAT={-:-/ absolute / inch / decimal} 4 | ; #@! TF.CreationDate,2020-01-11T16:25:07-08:00 5 | ; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5)-3 6 | ; #@! TF.FileFunction,Plated,1,2,PTH 7 | FMAT,2 8 | INCH 9 | T1C0.0157 10 | T2C0.0394 11 | % 12 | G90 13 | G05 14 | T1 15 | X0.825Y0.4 16 | X0.95Y0.125 17 | X1.025Y0.125 18 | X1.425Y0.325 19 | T2 20 | X0.075Y0.675 21 | X0.075Y0.575 22 | X0.175Y0.675 23 | X0.175Y0.575 24 | X0.275Y0.675 25 | X0.275Y0.575 26 | X0.375Y0.675 27 | X0.375Y0.575 28 | X0.475Y0.675 29 | X0.475Y0.575 30 | X0.575Y0.675 31 | X0.575Y0.575 32 | X0.675Y0.675 33 | X0.675Y0.575 34 | X0.775Y0.675 35 | X0.775Y0.575 36 | X0.875Y0.675 37 | X0.875Y0.575 38 | X0.975Y0.675 39 | X0.975Y0.575 40 | X1.075Y0.675 41 | X1.075Y0.575 42 | X1.175Y0.675 43 | X1.175Y0.575 44 | X1.275Y0.675 45 | X1.275Y0.575 46 | X1.375Y0.675 47 | X1.375Y0.575 48 | X1.475Y0.675 49 | X1.475Y0.575 50 | X1.575Y0.675 51 | X1.575Y0.575 52 | X1.675Y0.675 53 | X1.675Y0.575 54 | X1.775Y0.675 55 | X1.775Y0.575 56 | X1.875Y0.675 57 | X1.875Y0.575 58 | X1.975Y0.675 59 | X1.975Y0.575 60 | X0.075Y0.25 61 | X0.075Y0.15 62 | X0.175Y0.25 63 | X0.175Y0.15 64 | X0.275Y0.25 65 | X0.275Y0.15 66 | X0.375Y0.25 67 | X0.375Y0.15 68 | X0.475Y0.25 69 | X0.475Y0.15 70 | X0.575Y0.25 71 | X0.575Y0.15 72 | X0.675Y0.25 73 | X0.675Y0.15 74 | X0.775Y0.25 75 | X0.775Y0.15 76 | X1.275Y0.25 77 | X1.275Y0.15 78 | X1.375Y0.25 79 | X1.375Y0.15 80 | X1.475Y0.25 81 | X1.475Y0.15 82 | X1.575Y0.25 83 | X1.575Y0.15 84 | X1.675Y0.25 85 | X1.675Y0.15 86 | X1.775Y0.25 87 | X1.775Y0.15 88 | X1.875Y0.25 89 | X1.875Y0.15 90 | X1.975Y0.25 91 | X1.975Y0.15 92 | T0 93 | M30 94 | -------------------------------------------------------------------------------- /pcbs/gpio2hub75/gpio2hub75_gerbers.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/cube/8825de87cb2f6d403bfcbcad1ebeddac23d54e3b/pcbs/gpio2hub75/gpio2hub75_gerbers.zip -------------------------------------------------------------------------------- /quartus/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | -------------------------------------------------------------------------------- /quartus/Makefile: -------------------------------------------------------------------------------- 1 | 2 | QUARTUS_DIR = /home/tom/altera/13.0sp1/quartus/bin/ 3 | 4 | CPU_RAM0 = $(wildcard ./db/*ram0_CCPipelinedMemory*.mif) 5 | CPU_RAM1 = $(wildcard ./db/*ram1_CCPipelinedMemory*.mif) 6 | CPU_RAM2 = $(wildcard ./db/*ram2_CCPipelinedMemory*.mif) 7 | CPU_RAM3 = $(wildcard ./db/*ram3_CCPipelinedMemory*.mif) 8 | 9 | CPU_RAMS = $(CPU_RAM0) $(CPU_RAM1) $(CPU_RAM2) $(CPU_RAM3) 10 | 11 | all: 12 | $(QUARTUS_DIR)/quartus_map --read_settings_files=on --write_settings_files=off hwic-3g-cdma -c hwic-3g-cdma 13 | $(QUARTUS_DIR)/quartus_fit --read_settings_files=on --write_settings_files=off hwic-3g-cdma -c hwic-3g-cdma 14 | $(QUARTUS_DIR)/quartus_asm --read_settings_files=on --write_settings_files=off hwic-3g-cdma -c hwic-3g-cdma 15 | $(QUARTUS_DIR)/quartus_sta hwic-3g-cdma -c hwic-3g-cdma 16 | 17 | update_ram: sw $(CPU_RAMS) 18 | $(QUARTUS_DIR)/quartus_cdb hwic-3g-cdma -c hwic-3g-cdma --update_mif 19 | $(QUARTUS_DIR)/quartus_asm --read_settings_files=on --write_settings_files=off hwic-3g-cdma -c hwic-3g-cdma 20 | 21 | $(CPU_RAM0): ../sw/progmem0.mif 22 | cp $< $@ 23 | 24 | $(CPU_RAM1): ../sw/progmem1.mif 25 | cp $< $@ 26 | 27 | $(CPU_RAM2): ../sw/progmem2.mif 28 | cp $< $@ 29 | 30 | $(CPU_RAM3): ../sw/progmem3.mif 31 | cp $< $@ 32 | 33 | sw: 34 | cd ../sw && make 35 | -------------------------------------------------------------------------------- /quartus/altera_models/led_ram/led_ram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "led_ram.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "led_ram_bb.v"] 5 | -------------------------------------------------------------------------------- /quartus/altera_models/main_pll/main_pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /quartus/altera_models/main_pll/main_pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "main_pll.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "main_pll_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "main_pll.ppf"] 6 | -------------------------------------------------------------------------------- /quartus/cube.sdc: -------------------------------------------------------------------------------- 1 | ## Generated SDC file "hwic-3g-cdma.sdc" 2 | 3 | ## Copyright (C) 1991-2013 Altera Corporation 4 | ## Your use of Altera Corporation's design tools, logic functions 5 | ## and other software and tools, and its AMPP partner logic 6 | ## functions, and any output files from any of the foregoing 7 | ## (including device programming or simulation files), and any 8 | ## associated documentation or information are expressly subject 9 | ## to the terms and conditions of the Altera Program License 10 | ## Subscription Agreement, Altera MegaCore Function License 11 | ## Agreement, or other applicable license agreement, including, 12 | ## without limitation, that your use is for the sole purpose of 13 | ## programming logic devices manufactured by Altera and sold by 14 | ## Altera or its authorized distributors. Please refer to the 15 | ## applicable agreement for further details. 16 | 17 | 18 | ## VENDOR "Altera" 19 | ## PROGRAM "Quartus II" 20 | ## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" 21 | 22 | ## DATE "Sat Nov 9 21:30:49 2019" 23 | 24 | ## 25 | ## DEVICE "EP2C35F484C8" 26 | ## 27 | 28 | 29 | #************************************************************** 30 | # Time Information 31 | #************************************************************** 32 | 33 | set_time_format -unit ns -decimal_places 3 34 | 35 | 36 | 37 | #************************************************************** 38 | # Create Clock 39 | #************************************************************** 40 | 41 | create_clock -name {clk25} -period 40.000 -waveform { 0.000 20.000 } [get_ports { clk25 }] 42 | 43 | derive_pll_clocks 44 | 45 | 46 | #************************************************************** 47 | # Create Generated Clock 48 | #************************************************************** 49 | 50 | 51 | 52 | #************************************************************** 53 | # Set Clock Latency 54 | #************************************************************** 55 | 56 | 57 | 58 | #************************************************************** 59 | # Set Clock Uncertainty 60 | #************************************************************** 61 | 62 | 63 | 64 | #************************************************************** 65 | # Set Input Delay 66 | #************************************************************** 67 | 68 | 69 | 70 | #************************************************************** 71 | # Set Output Delay 72 | #************************************************************** 73 | 74 | 75 | 76 | #************************************************************** 77 | # Set Clock Groups 78 | #************************************************************** 79 | 80 | 81 | 82 | #************************************************************** 83 | # Set False Path 84 | #************************************************************** 85 | 86 | 87 | 88 | #************************************************************** 89 | # Set Multicycle Path 90 | #************************************************************** 91 | 92 | 93 | 94 | #************************************************************** 95 | # Set Maximum Delay 96 | #************************************************************** 97 | 98 | 99 | 100 | #************************************************************** 101 | # Set Minimum Delay 102 | #************************************************************** 103 | 104 | 105 | 106 | #************************************************************** 107 | # Set Input Transition 108 | #************************************************************** 109 | 110 | -------------------------------------------------------------------------------- /quartus/hwic-3g-cdma.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 22:08:15 October 30, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "22:08:15 October 30, 2019" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "hwic-3g-cdma" 31 | -------------------------------------------------------------------------------- /quartus/hwic-3g-cdma.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 22:08:15 October 30, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # hwic-3g-cdma_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone II" 40 | set_global_assignment -name DEVICE EP2C35F484C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY CubeShim 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:08:15 OCTOBER 30, 2019" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 49 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 50 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 51 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" 52 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation 53 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 54 | 55 | set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "PASSIVE SERIAL" 56 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 57 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" 58 | set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" 59 | 60 | source "pinout.tcl" 61 | 62 | 63 | set_global_assignment -name SDC_FILE cube.sdc 64 | set_global_assignment -name VERILOG_FILE ../spinal/CubeShim.syn.v 65 | 66 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 67 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 68 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 69 | set_global_assignment -name QIP_FILE altera_models/main_pll/main_pll.qip 70 | set_global_assignment -name QIP_FILE altera_models/led_ram/led_ram.qip 71 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /quartus/output_files/hwic-3g-cdma.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/cube/8825de87cb2f6d403bfcbcad1ebeddac23d54e3b/quartus/output_files/hwic-3g-cdma.sof -------------------------------------------------------------------------------- /spinal/.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | *.log 3 | *.bak 4 | *.bin 5 | *.yaml 6 | 7 | # sbt specific 8 | .cache/ 9 | .history/ 10 | .lib/ 11 | dist/* 12 | target 13 | lib_managed/ 14 | src_managed/ 15 | project/boot/ 16 | project/plugins/project/ 17 | 18 | # Scala-IDE specific 19 | .scala_dependencies 20 | .worksheet 21 | 22 | .idea 23 | out 24 | 25 | # Eclipse 26 | bin/ 27 | .classpath 28 | .project 29 | .settings 30 | .cache-main 31 | 32 | #User 33 | /*.vhd 34 | /*.v 35 | *.cf 36 | *.json 37 | *.vcd 38 | !tester/src/test/resources/*.vhd 39 | 40 | 41 | simWorkspace/ 42 | tmp/ 43 | -------------------------------------------------------------------------------- /spinal/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: syn 3 | 4 | #sim: 5 | # sbt "test-only rt.PanoTester" 6 | 7 | .PHONY: submodule 8 | submodule: 9 | cd ../ && git submodule update --init 10 | 11 | sw: 12 | cd ../sw && make 13 | 14 | syn: submodule sw 15 | sbt "runMain cube.CubeShimVerilogSyn" 16 | mv CubeShim.v CubeShim.syn.v 17 | 18 | sim: submodule sw 19 | sbt "runMain cube.CubeTopVerilogSim" 20 | mv CubeTop.v CubeTop.sim.v 21 | 22 | 23 | waves: 24 | gtkwave -o simWorkspace/PanoCoreDut/test.vcd & 25 | 26 | -------------------------------------------------------------------------------- /spinal/build.sbt: -------------------------------------------------------------------------------- 1 | /* 2 | name := "SpinalTemplateSbt" 3 | 4 | version := "1.0" 5 | 6 | scalaVersion := "2.11.12" 7 | 8 | EclipseKeys.withSource := true 9 | 10 | libraryDependencies ++= Seq( 11 | "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.5", 12 | "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.5" 13 | ) 14 | 15 | fork := true 16 | */ 17 | 18 | lazy val root = (project in file(".")). 19 | settings( 20 | inThisBuild(List( 21 | organization := "com.github.spinalhdl", 22 | scalaVersion := "2.11.12", 23 | version := "1.0.0" 24 | )), 25 | libraryDependencies ++= Seq( 26 | "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.5", 27 | "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.5", 28 | "org.scalatest" % "scalatest_2.11" % "2.2.1", 29 | "org.yaml" % "snakeyaml" % "1.8" 30 | ), 31 | name := "cube" 32 | ).dependsOn(vexRiscv) 33 | 34 | lazy val vexRiscv = RootProject(file("../VexRiscv")) 35 | 36 | fork := true 37 | -------------------------------------------------------------------------------- /spinal/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.2.7 2 | -------------------------------------------------------------------------------- /spinal/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | addSbtPlugin("com.typesafe.sbteclipse" % "sbteclipse-plugin" % "5.2.4") 2 | 3 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/Apb3CC.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.amba3.apb._ 7 | 8 | //============================================================ 9 | // 10 | // APB3 Clock Crossing block 11 | // 12 | //============================================================ 13 | 14 | object Apb3CC { 15 | } 16 | 17 | class Apb3CC(apb3Config: Apb3Config, srcDomain: ClockDomain, destDomain: ClockDomain) extends Component { 18 | 19 | val io = new Bundle { 20 | val src = slave(Apb3(apb3Config)) 21 | val dest = master(Apb3(apb3Config)) 22 | } 23 | 24 | val PRDATA_dest = Bits(apb3Config.dataWidth bits) 25 | 26 | val xfer_done_src = Bool 27 | val xfer_done_dest = Bool 28 | 29 | val u_sync_pulse_xfer_done = new PulseCCByToggle(destDomain, srcDomain) 30 | u_sync_pulse_xfer_done.io.pulseIn <> xfer_done_dest 31 | u_sync_pulse_xfer_done.io.pulseOut <> xfer_done_src 32 | 33 | 34 | val src = new ClockingArea(srcDomain) { 35 | 36 | val xfer_start = Reg(Bool) init(False) 37 | val PADDR = Reg(UInt(apb3Config.addressWidth bits)) init(0) 38 | val PSEL = Reg(Bits(apb3Config.selWidth bits)) init(0) 39 | val PWRITE = RegInit(False) 40 | val PWDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 41 | val PRDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 42 | val PREADY = RegInit(False) 43 | val PSLVERROR = if (apb3Config.useSlaveError) Reg(Bool) else null 44 | 45 | xfer_start := False 46 | when((io.src.PENABLE && io.src.PSEL.orR).rise){ 47 | xfer_start := True 48 | PADDR := io.src.PADDR 49 | PSEL := io.src.PSEL 50 | PWRITE := io.src.PWRITE 51 | PWDATA := io.src.PWDATA 52 | } 53 | 54 | PREADY := False 55 | when(xfer_done_src){ 56 | PREADY := True 57 | when (!io.src.PWRITE){ 58 | PRDATA := PRDATA_dest.addTag(crossClockDomain) 59 | } 60 | } 61 | 62 | io.src.PRDATA := PRDATA 63 | io.src.PREADY := PREADY 64 | } 65 | 66 | val xfer_start_dest = Bool 67 | val u_sync_pulse_xfer_start = new PulseCCByToggle(srcDomain, destDomain) 68 | u_sync_pulse_xfer_start.io.pulseIn <> src.xfer_start 69 | u_sync_pulse_xfer_start.io.pulseOut <> xfer_start_dest 70 | 71 | val dest = new ClockingArea(destDomain) { 72 | val xfer_start_dest_d1 = RegNext(xfer_start_dest) init(False) 73 | 74 | val PADDR = Reg(UInt(apb3Config.addressWidth bits)) init(0) 75 | val PSEL = Reg(Bits(apb3Config.selWidth bits)) init(0) 76 | val PWRITE = RegInit(False) 77 | val PWDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 78 | val PRDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 79 | val PSLVERROR = if (apb3Config.useSlaveError) Reg(Bool) else null 80 | 81 | when(xfer_start_dest){ 82 | PADDR := src.PADDR.addTag(crossClockDomain) 83 | PSEL := src.PSEL.addTag(crossClockDomain) 84 | PWRITE := src.PWRITE.addTag(crossClockDomain) 85 | PWDATA := src.PWDATA.addTag(crossClockDomain) 86 | } 87 | 88 | val PENABLE = RegInit(False) setWhen(xfer_start_dest_d1) clearWhen(io.dest.PREADY) 89 | val xfer_done = RegInit(False) 90 | 91 | xfer_done := False 92 | when(PENABLE && io.dest.PREADY){ 93 | PSEL := 0 94 | when(!io.dest.PWRITE){ 95 | PRDATA := io.dest.PRDATA 96 | } 97 | xfer_done := True 98 | } 99 | 100 | 101 | io.dest.PENABLE := PENABLE 102 | io.dest.PADDR := PADDR 103 | io.dest.PSEL := PSEL 104 | io.dest.PWRITE := PWRITE 105 | io.dest.PWDATA := PWDATA 106 | 107 | PRDATA_dest := PRDATA 108 | xfer_done_dest := xfer_done 109 | } 110 | } 111 | 112 | 113 | case class Apb3CCFormalTb() extends Component 114 | { 115 | val io = new Bundle() { 116 | val clk = in(Bool) 117 | val reset_ = in(Bool) 118 | } 119 | 120 | 121 | val domain = new ClockingArea(ClockDomain(io.clk, io.reset_, 122 | config = ClockDomainConfig(resetKind = SYNC, resetActiveLevel = LOW))) 123 | { 124 | val apb3Config = Apb3Config(addressWidth = 6, dataWidth = 32) 125 | 126 | val src = Apb3(apb3Config) 127 | val dest = Apb3(apb3Config) 128 | 129 | val u_apb3cc = new Apb3CC(apb3Config, ClockDomain.current, ClockDomain.current) 130 | u_apb3cc.io.src <> src 131 | u_apb3cc.io.dest <> dest 132 | 133 | val src_xfer_cntr = Reg(UInt(8 bits)) init(0) 134 | val dest_xfer_cntr = Reg(UInt(8 bits)) init(0) 135 | 136 | when(src.PENABLE && src.PREADY){ 137 | src_xfer_cntr := src_xfer_cntr + 1 138 | } 139 | 140 | when(dest.PENABLE && dest.PREADY){ 141 | dest_xfer_cntr := dest_xfer_cntr + 1 142 | } 143 | 144 | 145 | import spinal.core.GenerationFlags._ 146 | import spinal.core.Formal._ 147 | 148 | GenerationFlags.formal{ 149 | import cc.lib._ 150 | 151 | assume(io.reset_ === !initstate()) 152 | 153 | assume(rose(src.PENABLE) |-> stable(src.PSEL)) 154 | assume(rose(src.PENABLE) |-> stable(src.PADDR)) 155 | assume(rose(src.PENABLE) |-> stable(src.PWRITE)) 156 | assume(rose(src.PENABLE) |-> stable(src.PWDATA)) 157 | 158 | assume(src.PREADY |-> stable(src.PENABLE)) 159 | assume(src.PREADY |-> stable(src.PSEL)) 160 | assume(src.PREADY |-> stable(src.PADDR)) 161 | assume(src.PREADY |-> stable(src.PWRITE)) 162 | assume(src.PREADY |-> stable(src.PWDATA)) 163 | 164 | assume(fell(src.PENABLE) |-> src.PREADY) 165 | assume(fell(src.PSEL.orR) |-> src.PREADY) 166 | 167 | assume(!stable(src.PSEL) |=> (fell(src.PENABLE) || !src.PENABLE)) 168 | assume(!stable(src.PADDR) |=> (fell(src.PENABLE) || !src.PENABLE)) 169 | assume(!stable(src.PWRITE) |=> (fell(src.PENABLE) || !src.PENABLE)) 170 | assume(!stable(src.PWDATA) |=> (fell(src.PENABLE) || !src.PENABLE)) 171 | 172 | assume(rose(dest.PREADY) |-> dest.PENABLE) 173 | assume(rose(dest.PREADY) |=> fell(dest.PREADY)) 174 | 175 | when(!initstate()){ 176 | assert(src_xfer_cntr === dest_xfer_cntr || src_xfer_cntr+1 === dest_xfer_cntr) 177 | } 178 | } 179 | }.setName("") 180 | } 181 | 182 | object Apb3CCVerilog{ 183 | def main(args: Array[String]) { 184 | 185 | val config = SpinalConfig(anonymSignalUniqueness = true) 186 | config.includeFormal.generateSystemVerilog({ 187 | val toplevel = new Apb3CCFormalTb() 188 | toplevel 189 | }) 190 | println("DONE") 191 | } 192 | } 193 | 194 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/ApbBus2PipelinedMemoryBus.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.amba3.apb._ 7 | import spinal.lib.bus.misc.SizeMapping 8 | import spinal.lib.bus.simple._ 9 | 10 | object ApbBus2PipelinedMemoryBus { 11 | } 12 | 13 | class ApbBus2PipelinedMemoryBus(baseAddr: Int, apb3Config: Apb3Config, pipelinedMemoryBusConfig: PipelinedMemoryBusConfig) extends Component { 14 | 15 | val io = new Bundle { 16 | val src = slave(Apb3(apb3Config)) 17 | val dest = master(PipelinedMemoryBus(pipelinedMemoryBusConfig)) 18 | } 19 | 20 | val xfer_req_pending = RegInit(False).clearWhen(io.dest.cmd.ready) 21 | val xfer_rsp_pending = RegInit(False).clearWhen(io.dest.rsp.valid && !io.src.PWRITE) 22 | 23 | val update_addr = False 24 | when((io.src.PENABLE && io.src.PSEL.orR).rise){ 25 | xfer_req_pending := True 26 | xfer_rsp_pending := !io.src.PWRITE 27 | update_addr := True 28 | } 29 | 30 | val addr = RegNextWhen(io.src.PADDR.resize(io.dest.cmd.address.getWidth) + baseAddr, update_addr) 31 | 32 | io.dest.cmd.valid := xfer_req_pending 33 | io.dest.cmd.address := addr 34 | io.dest.cmd.write := io.src.PWRITE 35 | io.dest.cmd.mask := (default -> True) 36 | io.dest.cmd.data := io.src.PWDATA 37 | 38 | io.src.PREADY := io.src.PWRITE ? io.dest.cmd.ready | io.dest.rsp.valid 39 | io.src.PRDATA := io.dest.rsp.data 40 | } 41 | 42 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/CCBlocks.scala: -------------------------------------------------------------------------------- 1 | package cc 2 | 3 | // All code copied from vexriscv.demo.Murax 4 | 5 | import java.nio.{ByteBuffer, ByteOrder} 6 | import java.nio.file.{Files, Paths} 7 | 8 | import spinal.core._ 9 | import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory} 10 | import spinal.lib.bus.misc.SizeMapping 11 | import spinal.lib.misc.{ InterruptCtrl, Prescaler, Timer} 12 | import spinal.lib._ 13 | import spinal.lib.bus.simple._ 14 | import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus} 15 | 16 | class CCMasterArbiter(pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{ 17 | val io = new Bundle{ 18 | val iBus = slave(IBusSimpleBus(null)) 19 | val dBus = slave(DBusSimpleBus()) 20 | val masterBus = master(PipelinedMemoryBus(pipelinedMemoryBusConfig)) 21 | } 22 | 23 | io.masterBus.cmd.valid := io.iBus.cmd.valid || io.dBus.cmd.valid 24 | io.masterBus.cmd.write := io.dBus.cmd.valid && io.dBus.cmd.wr 25 | io.masterBus.cmd.address := io.dBus.cmd.valid ? io.dBus.cmd.address | io.iBus.cmd.pc 26 | io.masterBus.cmd.data := io.dBus.cmd.data 27 | io.masterBus.cmd.mask := io.dBus.cmd.size.mux( 28 | 0 -> B"0001", 29 | 1 -> B"0011", 30 | default -> B"1111" 31 | ) |<< io.dBus.cmd.address(1 downto 0) 32 | io.iBus.cmd.ready := io.masterBus.cmd.ready && !io.dBus.cmd.valid 33 | io.dBus.cmd.ready := io.masterBus.cmd.ready 34 | 35 | 36 | val rspPending = RegInit(False) clearWhen(io.masterBus.rsp.valid) 37 | val rspTarget = RegInit(False) 38 | when(io.masterBus.cmd.fire && !io.masterBus.cmd.write){ 39 | rspTarget := io.dBus.cmd.valid 40 | rspPending := True 41 | } 42 | 43 | when(rspPending && !io.masterBus.rsp.valid){ 44 | io.iBus.cmd.ready := False 45 | io.dBus.cmd.ready := False 46 | io.masterBus.cmd.valid := False 47 | } 48 | 49 | io.iBus.rsp.valid := io.masterBus.rsp.valid && !rspTarget 50 | io.iBus.rsp.inst := io.masterBus.rsp.data 51 | io.iBus.rsp.error := False 52 | 53 | io.dBus.rsp.ready := io.masterBus.rsp.valid && rspTarget 54 | io.dBus.rsp.data := io.masterBus.rsp.data 55 | io.dBus.rsp.error := False 56 | } 57 | 58 | 59 | case class CCPipelinedMemoryBusRam(onChipRamSize : BigInt, onChipRamBinFile : String, pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{ 60 | val io = new Bundle{ 61 | val bus = slave(PipelinedMemoryBus(pipelinedMemoryBusConfig)) 62 | } 63 | 64 | val ram = Mem(Bits(32 bits), onChipRamSize / 4) 65 | io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.write) init(False) 66 | io.bus.rsp.data := ram.readWriteSync( 67 | address = (io.bus.cmd.address >> 2).resized, 68 | data = io.bus.cmd.data, 69 | enable = io.bus.cmd.valid, 70 | write = io.bus.cmd.write, 71 | mask = io.bus.cmd.mask 72 | ) 73 | io.bus.cmd.ready := True 74 | 75 | if(onChipRamBinFile != null){ 76 | 77 | val byteArray = Files.readAllBytes(Paths.get(onChipRamBinFile)) 78 | 79 | val initContent = for(i <- 0 until onChipRamSize.toInt/4) yield { 80 | BigInt( (byteArray(4*i).toLong & 0xff) + ((byteArray(4*i+1).toLong & 0xff)<<8) + ((byteArray(4*i+2).toLong & 0xff)<<16) + ((byteArray(4*i+3).toLong & 0xff)<<24) ) 81 | } 82 | ram.initBigInt(initContent) 83 | } 84 | } 85 | 86 | 87 | 88 | case class Apb3Rom(onChipRamBinFile : String) extends Component{ 89 | val byteArray = Files.readAllBytes(Paths.get(onChipRamBinFile)) 90 | val wordCount = (byteArray.length+3)/4 91 | val buffer = ByteBuffer.wrap(Files.readAllBytes(Paths.get(onChipRamBinFile))).order(ByteOrder.LITTLE_ENDIAN); 92 | val wordArray = (0 until wordCount).map(i => { 93 | val v = buffer.getInt 94 | if(v < 0) BigInt(v.toLong & 0xFFFFFFFFl) else BigInt(v) 95 | }) 96 | 97 | val io = new Bundle{ 98 | val apb = slave(Apb3(log2Up(wordCount*4),32)) 99 | } 100 | 101 | val rom = Mem(Bits(32 bits), wordCount) initBigInt(wordArray) 102 | // io.apb.PRDATA := rom.readSync(io.apb.PADDR >> 2) 103 | io.apb.PRDATA := rom.readAsync(RegNext(io.apb.PADDR >> 2)) 104 | io.apb.PREADY := True 105 | } 106 | 107 | 108 | 109 | class CCPipelinedMemoryBusDecoder(master : PipelinedMemoryBus, val specification : Seq[(PipelinedMemoryBus,SizeMapping)], pipelineMaster : Boolean) extends Area{ 110 | val masterPipelined = PipelinedMemoryBus(master.config) 111 | if(!pipelineMaster) { 112 | masterPipelined.cmd << master.cmd 113 | masterPipelined.rsp >> master.rsp 114 | } else { 115 | masterPipelined.cmd <-< master.cmd 116 | masterPipelined.rsp >> master.rsp 117 | } 118 | 119 | val slaveBuses = specification.map(_._1) 120 | val memorySpaces = specification.map(_._2) 121 | 122 | val hits = for((slaveBus, memorySpace) <- specification) yield { 123 | val hit = memorySpace.hit(masterPipelined.cmd.address) 124 | slaveBus.cmd.valid := masterPipelined.cmd.valid && hit 125 | slaveBus.cmd.payload := masterPipelined.cmd.payload.resized 126 | hit 127 | } 128 | val noHit = !hits.orR 129 | masterPipelined.cmd.ready := (hits,slaveBuses).zipped.map(_ && _.cmd.ready).orR || noHit 130 | 131 | val rspPending = RegInit(False) clearWhen(masterPipelined.rsp.valid) setWhen(masterPipelined.cmd.fire && !masterPipelined.cmd.write) 132 | val rspNoHit = RegNext(False) init(False) setWhen(noHit) 133 | val rspSourceId = RegNextWhen(OHToUInt(hits), masterPipelined.cmd.fire) 134 | masterPipelined.rsp.valid := slaveBuses.map(_.rsp.valid).orR || (rspPending && rspNoHit) 135 | masterPipelined.rsp.payload := slaveBuses.map(_.rsp.payload).read(rspSourceId) 136 | 137 | when(rspPending && !masterPipelined.rsp.valid) { //Only one pending read request is allowed 138 | masterPipelined.cmd.ready := False 139 | slaveBuses.foreach(_.cmd.valid := False) 140 | } 141 | } 142 | 143 | class CCApb3Timer extends Component{ 144 | val io = new Bundle { 145 | val apb = slave(Apb3( 146 | addressWidth = 8, 147 | dataWidth = 32 148 | )) 149 | val interrupt = out Bool 150 | } 151 | 152 | val prescaler = Prescaler(16) 153 | val timerA,timerB = Timer(16) 154 | 155 | val busCtrl = Apb3SlaveFactory(io.apb) 156 | val prescalerBridge = prescaler.driveFrom(busCtrl,0x00) 157 | 158 | val timerABridge = timerA.driveFrom(busCtrl,0x40)( 159 | ticks = List(True, prescaler.io.overflow), 160 | clears = List(timerA.io.full) 161 | ) 162 | 163 | val timerBBridge = timerB.driveFrom(busCtrl,0x50)( 164 | ticks = List(True, prescaler.io.overflow), 165 | clears = List(timerB.io.full) 166 | ) 167 | 168 | val interruptCtrl = InterruptCtrl(2) 169 | val interruptCtrlBridge = interruptCtrl.driveFrom(busCtrl,0x10) 170 | interruptCtrl.io.inputs(0) := timerA.io.full 171 | interruptCtrl.io.inputs(1) := timerB.io.full 172 | io.interrupt := interruptCtrl.io.pendings.orR 173 | } 174 | 175 | 176 | object CCApb3TimerGen extends App{ 177 | SpinalVhdl(new CCApb3Timer()) 178 | } 179 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/CCGpio.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.amba3.apb._ 7 | import spinal.lib.io.{TriStateArray, TriState} 8 | 9 | object CCGpio { 10 | def getApb3Config() = Apb3Config(addressWidth = 5,dataWidth = 32) 11 | } 12 | 13 | // 0x0000 : Direction. 0 -> input, 1 -> output 14 | // 0x0004 : Write 15 | // 0x0008 : Set 16 | // 0x000c : Clear 17 | // 0x0010 : Read 18 | 19 | case class CCGpio(gpioWidth: Int) extends Component { 20 | 21 | val io = new Bundle { 22 | val apb = slave(Apb3(CCGpio.getApb3Config())) 23 | val gpio = master(TriStateArray(gpioWidth bits)) 24 | } 25 | 26 | val value = Reg(Bits(gpioWidth bits)) init(0) 27 | val ctrl = Apb3SlaveFactory(io.apb) 28 | 29 | // Direction 30 | io.gpio.writeEnable := ctrl.createReadAndWrite(Bits(gpioWidth bits), 0) init(0) 31 | 32 | // Straight read and write 33 | ctrl.readAndWrite(value, 4) 34 | 35 | // Set bit when corresponding value is set 36 | val wrBits = ctrl.nonStopWrite(Bits(gpioWidth bits), 0) 37 | ctrl.onWrite(8){ 38 | for(i <- 0 until gpioWidth){ 39 | when(wrBits(i)){ 40 | value(i) := True 41 | } 42 | } 43 | } 44 | 45 | // Clear bit when corresponding value is set 46 | ctrl.onWrite(12){ 47 | for(i <- 0 until gpioWidth){ 48 | when(wrBits(i)){ 49 | value(i) := False 50 | } 51 | } 52 | } 53 | 54 | ctrl.read(io.gpio.read, 0x0010) 55 | 56 | io.gpio.write := value 57 | } 58 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/CpuComplex.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.amba3.apb._ 7 | import spinal.lib.bus.misc.SizeMapping 8 | import spinal.lib.bus.simple._ 9 | 10 | import scala.collection.mutable.ArrayBuffer 11 | import vexriscv.plugin.{NONE, _} 12 | import vexriscv.{VexRiscv, VexRiscvConfig, plugin} 13 | import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} 14 | 15 | 16 | case class CpuComplexConfig( 17 | onChipRamSize : BigInt, 18 | onChipRamBinFile : String, 19 | pipelineDBus : Boolean, 20 | pipelineMainBus : Boolean, 21 | pipelineApbBridge : Boolean, 22 | periphApbConfig : Apb3Config, 23 | cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ 24 | 25 | require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") 26 | } 27 | 28 | object CpuComplexConfig{ 29 | 30 | def default = CpuComplexConfig( 31 | onChipRamSize = 16 kB, 32 | onChipRamBinFile = null, 33 | pipelineDBus = true, 34 | pipelineMainBus = false, 35 | pipelineApbBridge = true, 36 | cpuPlugins = ArrayBuffer( 37 | new IBusSimplePlugin( 38 | resetVector = 0x00000000l, 39 | cmdForkOnSecondStage = true, 40 | cmdForkPersistence = false, 41 | prediction = STATIC, 42 | catchAccessFault = false, 43 | compressedGen = true 44 | ), 45 | new DBusSimplePlugin( 46 | catchAddressMisaligned = false, 47 | catchAccessFault = false, 48 | earlyInjection = false 49 | ), 50 | new CsrPlugin( 51 | CsrPluginConfig( 52 | catchIllegalAccess = false, 53 | mvendorid = null, 54 | marchid = null, 55 | mimpid = null, 56 | mhartid = null, 57 | misaExtensionsInit = 0, 58 | misaAccess = CsrAccess.NONE, 59 | mtvecAccess = CsrAccess.NONE, 60 | mtvecInit = 0x00000020l, 61 | mepcAccess = CsrAccess.NONE, 62 | mscratchGen = false, 63 | mcauseAccess = CsrAccess.NONE, 64 | mbadaddrAccess = CsrAccess.NONE, 65 | mcycleAccess = CsrAccess.READ_WRITE, 66 | minstretAccess = CsrAccess.NONE, 67 | ecallGen = false, 68 | wfiGenAsWait = false, 69 | ucycleAccess = CsrAccess.NONE 70 | ) 71 | ), 72 | new DecoderSimplePlugin( 73 | catchIllegalInstruction = false 74 | ), 75 | new RegFilePlugin( 76 | regFileReadyKind = plugin.SYNC, 77 | zeroBoot = false 78 | ), 79 | new IntAluPlugin, 80 | new SrcPlugin( 81 | separatedAddSub = false, 82 | executeInsertion = false 83 | ), 84 | new FullBarrelShifterPlugin(), 85 | new MulSimplePlugin, 86 | new DivPlugin, 87 | new HazardSimplePlugin( 88 | bypassExecute = true, 89 | bypassMemory = true, 90 | bypassWriteBack = true, 91 | bypassWriteBackBuffer = true, 92 | pessimisticUseSrc = false, 93 | pessimisticWriteRegFile = false, 94 | pessimisticAddressMatch = false 95 | ), 96 | new BranchPlugin( 97 | earlyBranch = false, 98 | catchAddressMisaligned = false 99 | ), 100 | new YamlPlugin("cpu0.yaml") 101 | ), 102 | periphApbConfig = Apb3Config( 103 | addressWidth = 20, 104 | dataWidth = 32 105 | ) 106 | ) 107 | 108 | def fast = { 109 | val config = default 110 | 111 | // Replace HazardSimplePlugin to get datapath bypass 112 | config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[HazardSimplePlugin])) = new HazardSimplePlugin( 113 | bypassExecute = true, 114 | bypassMemory = true, 115 | bypassWriteBack = true, 116 | bypassWriteBackBuffer = true 117 | ) 118 | // config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrelShifterPlugin() 119 | 120 | config 121 | } 122 | } 123 | 124 | 125 | case class CpuComplex(config : CpuComplexConfig) extends Component 126 | { 127 | import config._ 128 | 129 | val io = new Bundle { 130 | val periphApb = master(Apb3(config.periphApbConfig)) 131 | val externalInterrupt = in(Bool) 132 | val timerInterrupt = in(Bool) 133 | } 134 | 135 | val pipelinedMemoryBusConfig = PipelinedMemoryBusConfig( 136 | addressWidth = 32, 137 | dataWidth = 32 138 | ) 139 | 140 | // Arbiter of the CPU dBus/iBus and DMA bus to drive the mainBus 141 | val mainBusArbiter = new CCMasterArbiter(pipelinedMemoryBusConfig) 142 | 143 | val cpu = new VexRiscv( 144 | config = VexRiscvConfig( 145 | plugins = cpuPlugins 146 | ) 147 | ) 148 | 149 | // Checkout plugins used to instanciate the CPU to connect them to the SoC 150 | for(plugin <- cpu.plugins) plugin match{ 151 | case plugin : IBusSimplePlugin => mainBusArbiter.io.iBus <> plugin.iBus 152 | case plugin : DBusSimplePlugin => { 153 | if(!pipelineDBus) 154 | mainBusArbiter.io.dBus <> plugin.dBus 155 | else { 156 | mainBusArbiter.io.dBus.cmd << plugin.dBus.cmd.halfPipe() 157 | mainBusArbiter.io.dBus.rsp <> plugin.dBus.rsp 158 | } 159 | } 160 | case plugin : CsrPlugin => { 161 | plugin.externalInterrupt := io.externalInterrupt 162 | plugin.timerInterrupt := io.timerInterrupt 163 | } 164 | case _ => 165 | } 166 | 167 | //****** MainBus slaves ******** 168 | val mainBusMapping = ArrayBuffer[(PipelinedMemoryBus,SizeMapping)]() 169 | val ram = new CCPipelinedMemoryBusRam( 170 | onChipRamSize = onChipRamSize, 171 | onChipRamBinFile = onChipRamBinFile, 172 | pipelinedMemoryBusConfig = pipelinedMemoryBusConfig 173 | ) 174 | 175 | mainBusMapping += ram.io.bus -> (0x00000000l, onChipRamSize) 176 | 177 | val periphApbBridge = new PipelinedMemoryBusToApbBridge( 178 | apb3Config = config.periphApbConfig, 179 | pipelineBridge = pipelineApbBridge, 180 | pipelinedMemoryBusConfig = pipelinedMemoryBusConfig 181 | ) 182 | mainBusMapping += periphApbBridge.io.pipelinedMemoryBus -> (0x80000000l, 1 MB) 183 | 184 | io.periphApb <> periphApbBridge.io.apb 185 | 186 | val mainBusDecoder = new Area { 187 | val logic = new CCPipelinedMemoryBusDecoder( 188 | master = mainBusArbiter.io.masterBus, 189 | specification = mainBusMapping, 190 | pipelineMaster = pipelineMainBus 191 | ) 192 | } 193 | 194 | } 195 | 196 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/Sequence.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | 6 | // Eventually, this needs to become that whole thing with FSMs etc. 7 | 8 | class Sequence(seq: Bool){ 9 | 10 | def |->(that: Bool): Bool = { 11 | val result = Bool 12 | 13 | result := !seq || that 14 | 15 | result 16 | } 17 | 18 | def |=>(that: Bool): Bool = { 19 | val result = Bool 20 | 21 | result := !RegNext(seq) || that 22 | 23 | result 24 | } 25 | 26 | } 27 | 28 | package object lib { 29 | implicit def sequence(that: Bool)= new Sequence(that) 30 | } 31 | 32 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/CpuTop.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.io._ 7 | import spinal.lib.bus.amba3.apb._ 8 | import spinal.lib.bus.misc.SizeMapping 9 | 10 | import scala.collection.mutable.ArrayBuffer 11 | import spinal.lib.com.uart._ 12 | 13 | import cc._ 14 | 15 | case class CpuTop() extends Component { 16 | 17 | val io = new Bundle { 18 | val led_red = out(Bool) 19 | val led_green = out(Bool) 20 | val led_blue = out(Bool) 21 | 22 | val led_mem_apb = master(Apb3(LedMem.getApb3Config())) 23 | val hub75_streamer_apb = master(Apb3(Hub75Streamer.getApb3Config())) 24 | } 25 | 26 | val cpuConfig = CpuComplexConfig.default.copy(onChipRamBinFile = "../sw/progmem4k.bin") 27 | //val cpuConfig = CpuComplexConfig.default 28 | 29 | val u_cpu = CpuComplex(cpuConfig) 30 | u_cpu.io.externalInterrupt <> False 31 | 32 | val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]() 33 | 34 | //============================================================ 35 | // Timer 36 | //============================================================ 37 | 38 | val u_timer = new CCApb3Timer() 39 | u_timer.io.interrupt <> u_cpu.io.timerInterrupt 40 | apbMapping += u_timer.io.apb -> (0x00000, 4 kB) 41 | 42 | //============================================================ 43 | // GPIO control, bits: 44 | // 0 - Green LED 45 | // 1 - Blue LED 46 | // 2 - Red LED (write only: hardware limitation) 47 | // 3 - Pano button 48 | //============================================================ 49 | 50 | val u_led_ctrl = Apb3Gpio(3, withReadSync = true) 51 | u_led_ctrl.io.gpio.write(0) <> io.led_red 52 | u_led_ctrl.io.gpio.write(1) <> io.led_green 53 | u_led_ctrl.io.gpio.write(2) <> io.led_blue 54 | u_led_ctrl.io.gpio.read(0) := io.led_red 55 | u_led_ctrl.io.gpio.read(1) := io.led_green 56 | u_led_ctrl.io.gpio.read(2) := io.led_blue 57 | 58 | apbMapping += u_led_ctrl.io.apb -> (0x10000, 4 kB) 59 | 60 | //============================================================ 61 | // External APBs 62 | //============================================================ 63 | 64 | apbMapping += io.led_mem_apb -> (0x20000, 64 kB) 65 | apbMapping += io.hub75_streamer_apb -> (0x30000, 4 kB) 66 | 67 | //============================================================ 68 | // Local APB decoder 69 | //============================================================ 70 | val apbDecoder = Apb3Decoder( 71 | master = u_cpu.io.periphApb, 72 | slaves = apbMapping 73 | ) 74 | 75 | } 76 | 77 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/CubeShim.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.misc._ 7 | import spinal.lib.bus.amba3.apb._ 8 | 9 | import ice40._ 10 | 11 | class CubeShim(internalOsc : Boolean = true) extends Component { 12 | 13 | val io = new Bundle { 14 | val clk25 = in(Bool) 15 | val hwic_3 = out(Bool) 16 | val hwic_11 = out(Bool) 17 | val hwic_12 = out(Bool) 18 | val hwic_13 = out(Bool) 19 | val hwic_14 = out(Bool) 20 | val hwic_15 = out(Bool) 21 | val hwic_18 = out(Bool) 22 | val hwic_19 = out(Bool) 23 | val hwic_20 = out(Bool) 24 | val hwic_21 = out(Bool) 25 | val hwic_25 = out(Bool) 26 | // val hwic_32 = out(Bool) 27 | val hwic_45 = out(Bool) 28 | val hwic_46 = out(Bool) 29 | val hwic_47 = out(Bool) 30 | val hwic_48 = out(Bool) 31 | val hwic_52 = out(Bool) 32 | val hwic_53 = out(Bool) 33 | val hwic_54 = out(Bool) 34 | val hwic_55 = out(Bool) 35 | val hwic_56 = out(Bool) 36 | 37 | val leds = out(Bits(4 bits)) 38 | } 39 | 40 | noIoPrefix() 41 | 42 | val cubeTop = new CubeTop(false) 43 | cubeTop.io.clk25 <> io.clk25 44 | cubeTop.io.leds <> io.leds 45 | 46 | cubeTop.io.hub75.clk <> io.hwic_45 47 | cubeTop.io.hub75.lat <> io.hwic_11 48 | cubeTop.io.hub75.oe_ <> io.hwic_3 49 | cubeTop.io.hub75.row(0) <> io.hwic_47 50 | cubeTop.io.hub75.row(1) <> io.hwic_13 51 | cubeTop.io.hub75.row(2) <> io.hwic_46 52 | 53 | cubeTop.io.hub75.r0 <> io.hwic_20 54 | cubeTop.io.hub75.g0 <> io.hwic_53 55 | cubeTop.io.hub75.b0 <> io.hwic_19 56 | 57 | cubeTop.io.hub75.r1 <> io.hwic_52 58 | cubeTop.io.hub75.g1 <> io.hwic_18 59 | cubeTop.io.hub75.b1 <> io.hwic_48 60 | 61 | cubeTop.io.hub75.r2 <> io.hwic_25 62 | cubeTop.io.hub75.g2 <> io.hwic_15 63 | cubeTop.io.hub75.b2 <> io.hwic_56 64 | 65 | cubeTop.io.hub75.r3 <> io.hwic_21 66 | cubeTop.io.hub75.g3 <> io.hwic_55 67 | cubeTop.io.hub75.b3 <> io.hwic_54 68 | 69 | // D, E / row(3), row(4) 70 | io.hwic_12 := False // PB2 71 | io.hwic_14 := False // PB6 72 | } 73 | 74 | 75 | //Generate the MyTopLevel's Verilog 76 | object CubeShimVerilogSim { 77 | def main(args: Array[String]) { 78 | 79 | val config = SpinalConfig(anonymSignalUniqueness = true) 80 | config.generateVerilog(new CubeShim(internalOsc = false)) 81 | } 82 | } 83 | 84 | object CubeShimVerilogSyn { 85 | def main(args: Array[String]) { 86 | 87 | val config = SpinalConfig(anonymSignalUniqueness = true) 88 | config.generateVerilog(new CubeShim(internalOsc = true)) 89 | } 90 | } 91 | 92 | 93 | //Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere 94 | object CubeShimSpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC)) 95 | 96 | 97 | //Generate the MyTopLevel's Verilog using the above custom configuration. 98 | object CubeShimVerilogWithCustomConfig { 99 | def main(args: Array[String]) { 100 | CubeShimSpinalConfig.generateVerilog(new CubeShim) 101 | } 102 | } 103 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/CubeTop.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | import scala.collection.mutable.ArrayBuffer 5 | 6 | import spinal.core._ 7 | import spinal.lib._ 8 | import spinal.lib.bus.misc._ 9 | import spinal.lib.bus.amba3.apb._ 10 | 11 | import cyclone2._ 12 | 13 | class CubeTop(isSim : Boolean = true) extends Component { 14 | 15 | val panels = ArrayBuffer[PanelInfo]() 16 | 17 | if (!isSim){ 18 | panels += PanelInfo(-1, 1,-1, 5, true, 0, 0,-1, 1) 19 | panels += PanelInfo(-1, 0,-1, 5, false, 0, 0,-1, 1) 20 | 21 | // top face 22 | panels += PanelInfo(-1, 1,-1, 4, true, 0, 1, 0, 1) 23 | panels += PanelInfo(-1, 1, 0, 4, false, 0, 1, 0, 1) 24 | 25 | // bottom face 26 | panels += PanelInfo(-1,-1, 1, 3, true, 0, 1, 0,-1) 27 | panels += PanelInfo(-1,-1, 0, 3, false, 0, 1, 0,-1) 28 | 29 | panels += PanelInfo( 1, 1,-1, 2, true, 0, -1,-1, 0) 30 | panels += PanelInfo( 1, 0,-1, 2, false, 0, -1,-1, 0) 31 | 32 | panels += PanelInfo( 1, 1, 1, 1, true, 90, 0,-1,-1) 33 | panels += PanelInfo( 1, 0, 1, 1, false, 90, 0,-1,-1) 34 | } 35 | 36 | 37 | // Side Top Rot 38 | panels += PanelInfo(-1, 1, 1, 0, true, 180, 1,-1, 0) 39 | panels += PanelInfo(-1, 0, 1, 0, true, 0, 1,-1, 0) 40 | 41 | val hub75Config = Hub75Config( 42 | panel_rows = 16, 43 | panel_cols = 32, 44 | bpc = if (isSim) 4 else 6, 45 | panels = panels.toArray 46 | ) 47 | 48 | val ledMemConfig = LedMemConfig(memWords = 2 * 6 * 32 * 32, bpc = 6) 49 | 50 | val io = new Bundle { 51 | val clk25 = in(Bool) 52 | 53 | val hub75 = out(Hub75Intfc(hub75Config.nr_row_bits)) 54 | 55 | val leds = out(Bits(4 bits)) 56 | } 57 | 58 | noIoPrefix() 59 | 60 | val main_clk = Bool 61 | val main_clk_speed = if (isSim) 2 MHz else 50 MHz 62 | 63 | val osc_src = if (isSim) new Area { 64 | main_clk := io.clk25 65 | } 66 | else new Area { 67 | val u_main_clk = new main_pll() 68 | u_main_clk.io.inclk0 <> io.clk25 69 | u_main_clk.io.c0 <> main_clk 70 | } 71 | 72 | val mainClkRawDomain = ClockDomain( 73 | clock = main_clk, 74 | frequency = FixedFrequency(main_clk_speed), 75 | config = ClockDomainConfig( 76 | resetKind = BOOT 77 | ) 78 | ) 79 | 80 | //============================================================ 81 | // Create main clock reset 82 | //============================================================ 83 | val main_reset_ = Bool 84 | 85 | val main_reset_gen = new ClockingArea(mainClkRawDomain) { 86 | val reset_unbuffered_ = True 87 | 88 | val reset_cntr = Reg(UInt(5 bits)) init(0) 89 | when(reset_cntr =/= U(reset_cntr.range -> true)){ 90 | reset_cntr := reset_cntr + 1 91 | reset_unbuffered_ := False 92 | } 93 | 94 | main_reset_ := RegNext(reset_unbuffered_) 95 | } 96 | 97 | 98 | val mainClkDomain = ClockDomain( 99 | clock = main_clk, 100 | reset = main_reset_, 101 | config = ClockDomainConfig( 102 | resetKind = SYNC, 103 | resetActiveLevel = LOW 104 | ) 105 | ) 106 | 107 | //============================================================ 108 | // General Logic 109 | //============================================================ 110 | 111 | val debug_leds = new ClockingArea(mainClkDomain) { 112 | 113 | val led_counter = Reg(UInt(24 bits)) 114 | led_counter := led_counter + 1 115 | 116 | io.leds(3) := led_counter.msb 117 | } 118 | 119 | val core = new ClockingArea(mainClkDomain) { 120 | 121 | val u_cpu = new CpuTop() 122 | 123 | //============================================================ 124 | // LED memory 125 | //============================================================ 126 | 127 | val u_led_mem = new LedMem(ledMemConfig, isSim) 128 | u_led_mem.io.led_mem_b_wr := False 129 | u_led_mem.io.led_mem_b_wr_data := 0 130 | 131 | val led_mem_apb_regs = u_led_mem.driveFrom(Apb3SlaveFactory(u_cpu.io.led_mem_apb), 0x0) 132 | 133 | //============================================================ 134 | // HUB75 Streamer 135 | //============================================================ 136 | 137 | val u_hub75_streamer = new Hub75Streamer(hub75Config, ledMemConfig) 138 | u_hub75_streamer.io.led_mem_rd <> u_led_mem.io.led_mem_b_req 139 | u_hub75_streamer.io.led_mem_rd_addr <> u_led_mem.io.led_mem_b_addr 140 | u_hub75_streamer.io.led_mem_rd_data <> u_led_mem.io.led_mem_b_rd_data 141 | 142 | val hub75_streamer_regs = u_hub75_streamer.driveFrom(Apb3SlaveFactory(u_cpu.io.hub75_streamer_apb), 0x0) 143 | 144 | //============================================================ 145 | // HUB75 Phy 146 | //============================================================ 147 | 148 | val u_hub75phy = new Hub75Phy(main_clk_speed, hub75Config) 149 | u_hub75phy.io.rgb <> u_hub75_streamer.io.rgb 150 | u_hub75phy.io.hub75 <> io.hub75 151 | 152 | } 153 | 154 | 155 | val leds = new Area { 156 | io.leds(2) := False 157 | io.leds(1) := core.u_cpu.io.led_green 158 | io.leds(0) := core.u_cpu.io.led_blue 159 | } 160 | 161 | 162 | } 163 | 164 | 165 | //Generate the MyTopLevel's Verilog 166 | object CubeTopVerilogSim { 167 | def main(args: Array[String]) { 168 | 169 | val config = SpinalConfig(anonymSignalUniqueness = true) 170 | config.generateVerilog(new CubeTop(isSim = true)) 171 | } 172 | } 173 | 174 | object CubeTopVerilogSyn { 175 | def main(args: Array[String]) { 176 | 177 | val config = SpinalConfig(anonymSignalUniqueness = true) 178 | config.generateVerilog(new CubeTop(isSim = false)) 179 | } 180 | } 181 | 182 | 183 | //Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere 184 | object MySpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC)) 185 | 186 | 187 | //Generate the MyTopLevel's Verilog using the above custom configuration. 188 | object CubeTopVerilogWithCustomConfig { 189 | def main(args: Array[String]) { 190 | MySpinalConfig.generateVerilog(new CubeTop) 191 | } 192 | } 193 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/Hub75Intfc.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | //import scala.collection.immutable.Array 5 | 6 | import spinal.core._ 7 | import spinal.lib._ 8 | import spinal.lib.io._ 9 | import spinal.lib.bus.misc._ 10 | import spinal.lib.bus.simple._ 11 | 12 | case class PanelInfoHW(conf: Hub75Config) extends Bundle { 13 | val topLeftXCoord = SInt(2 bits) 14 | val topLeftYCoord = SInt(2 bits) 15 | val topLeftZCoord = SInt(2 bits) 16 | 17 | val memAddrStartPh0 = UInt(log2Up(conf.total_nr_pixels+1) bits) 18 | val memAddrStartPh1 = UInt(log2Up(conf.total_nr_pixels+1) bits) 19 | val memAddrColMul = SInt(log2Up(conf.panel_cols)+2 bits) 20 | val memAddrRowMul = SInt(log2Up(conf.panel_cols)+2 bits) 21 | 22 | val xIncr = SInt(2 bits) 23 | val yIncr = SInt(2 bits) 24 | val zIncr = SInt(2 bits) 25 | } 26 | 27 | case class PanelInfo( 28 | topLeftXCoord : Int, 29 | topLeftYCoord : Int, 30 | topLeftZCoord : Int, 31 | 32 | side : Int, 33 | sideTop : Boolean, 34 | sideRotation : Int, 35 | 36 | xIncr : Int, 37 | yIncr : Int, 38 | zIncr : Int 39 | ) 40 | { 41 | 42 | def toPanelInfoHW(conf: Hub75Config) : PanelInfoHW = { 43 | 44 | val piHW = PanelInfoHW(conf) 45 | 46 | piHW.topLeftXCoord := topLeftXCoord 47 | piHW.topLeftYCoord := topLeftYCoord 48 | piHW.topLeftZCoord := topLeftZCoord 49 | 50 | var memAddrStartPh0 = side * 2 * conf.pixels_per_panel 51 | var memAddrStartPh1 = side * 2 * conf.pixels_per_panel 52 | var memAddrColMul = 1 53 | var memAddrRowMul = 1 54 | 55 | if (sideRotation == 0){ 56 | memAddrStartPh1 += conf.panel_rows/2 * conf.panel_cols 57 | 58 | if (!sideTop){ 59 | memAddrStartPh0 += conf.panel_rows * conf.panel_cols 60 | memAddrStartPh1 += conf.panel_rows * conf.panel_cols 61 | } 62 | memAddrColMul = 1 63 | memAddrRowMul = conf.panel_cols 64 | } 65 | else if (sideRotation == 90) { 66 | memAddrStartPh0 += conf.panel_cols -1 67 | memAddrStartPh1 += conf.panel_cols -1 - conf.panel_rows/2 68 | 69 | if (!sideTop){ 70 | memAddrStartPh0 -= conf.panel_cols/2 71 | memAddrStartPh1 -= conf.panel_cols/2 72 | } 73 | memAddrColMul = conf.panel_cols 74 | memAddrRowMul = -1 75 | } 76 | else{ 77 | memAddrStartPh0 += conf.panel_cols -1 + (conf.panel_rows*2 -1) * conf.panel_cols 78 | memAddrStartPh1 += memAddrStartPh0 - (conf.panel_rows/2 * conf.panel_cols) 79 | 80 | if (!sideTop){ 81 | memAddrStartPh0 -= conf.panel_rows * conf.panel_cols 82 | memAddrStartPh1 -= conf.panel_rows * conf.panel_cols 83 | } 84 | memAddrColMul = -1 85 | memAddrRowMul = -conf.panel_cols 86 | } 87 | 88 | println(s"Side: $side") 89 | println(s"Top: $sideTop") 90 | println(s"Rot: $sideRotation") 91 | println(s"Ph0: $memAddrStartPh0") 92 | println(s"Ph1: $memAddrStartPh1") 93 | 94 | piHW.memAddrStartPh0 := memAddrStartPh0 95 | piHW.memAddrStartPh1 := memAddrStartPh1 96 | piHW.memAddrColMul := memAddrColMul 97 | piHW.memAddrRowMul := memAddrRowMul 98 | 99 | piHW.xIncr := xIncr 100 | piHW.yIncr := yIncr 101 | piHW.zIncr := zIncr 102 | 103 | piHW 104 | } 105 | } 106 | 107 | case class Hub75Config( 108 | panel_rows : Int, 109 | panel_cols : Int, 110 | bpc : Int, 111 | panels : Array[PanelInfo] 112 | ) 113 | { 114 | def pixels_per_clk = 2 115 | def nr_row_bits = log2Up(panel_rows / pixels_per_clk) 116 | def total_nr_pixels = panels.size * panel_rows * panel_cols 117 | def pixels_per_panel = panel_rows * panel_cols 118 | } 119 | 120 | case class Hub75Intfc(nr_row_bits : Int) extends Bundle { 121 | val clk = Bool 122 | val lat = Bool 123 | val oe_ = Bool 124 | val row = UInt(nr_row_bits bits) 125 | 126 | val r0 = Bool 127 | val g0 = Bool 128 | val b0 = Bool 129 | 130 | val r1 = Bool 131 | val g1 = Bool 132 | val b1 = Bool 133 | 134 | val r2 = Bool 135 | val g2 = Bool 136 | val b2 = Bool 137 | 138 | val r3 = Bool 139 | val g3 = Bool 140 | val b3 = Bool 141 | } 142 | 143 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/Hub75Phy.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.io._ 7 | import spinal.lib.bus.misc._ 8 | import spinal.lib.bus.simple._ 9 | 10 | 11 | class Hub75Phy(oscSpeed: HertzNumber, conf: Hub75Config) extends Component { 12 | 13 | def osc_clk_speed = oscSpeed 14 | def refresh_rate = 120 // frame per second 15 | 16 | val sclk_desired = (conf.panels.size/2 * conf.panel_rows * conf.panel_cols / conf.pixels_per_clk) * (1 << conf.bpc) * refresh_rate 17 | val sclk_ratio = (osc_clk_speed.toLong / sclk_desired).toInt 18 | val sclk_actual = (osc_clk_speed / sclk_ratio).toLong 19 | 20 | println(s"Desired sclk: $sclk_desired") 21 | println(s"Clock ratio: $sclk_ratio") 22 | println(s"Actual sclk: $sclk_actual") 23 | 24 | val io = new Bundle { 25 | val rgb = slave(Stream(Bits(13 bits))) 26 | val hub75 = out(Hub75Intfc(nr_row_bits = 3)) 27 | } 28 | 29 | val clk_div_cntr = Counter(sclk_ratio, True) 30 | val col_cntr = Counter((conf.panels.size/2 * conf.panel_cols)+3, clk_div_cntr.willOverflow) 31 | val bin_dec_phase = Counter(1 << conf.bpc) 32 | val bit_cntr = Counter(conf.bpc) 33 | val row_cntr = Counter(conf.panel_rows/2, bit_cntr.willOverflow) 34 | 35 | val bin_dec_phase_max = UInt(conf.bpc bits) 36 | 37 | bin_dec_phase_max := ((U(1, 1 bits) << bit_cntr)-1).resize(conf.bpc) 38 | 39 | when(col_cntr.willOverflow){ 40 | when(bin_dec_phase === bin_dec_phase_max){ 41 | bit_cntr.increment() 42 | bin_dec_phase.clear() 43 | } 44 | .otherwise{ 45 | bin_dec_phase.increment() 46 | } 47 | } 48 | 49 | val col_active_phase = col_cntr.value < (conf.panels.size/2 * conf.panel_cols) 50 | 51 | val need_data = bin_dec_phase === 0 && col_active_phase && clk_div_cntr === 0 52 | val need_sof = (col_cntr === 0 && row_cntr === 0 && bit_cntr === 0 && bin_dec_phase === 0) 53 | 54 | val force_clear_no_data = False 55 | val force_clear_desync = False 56 | 57 | io.rgb.ready := False 58 | when(need_data){ 59 | when(!io.rgb.valid){ 60 | force_clear_no_data := True 61 | } 62 | .elsewhen(io.rgb.valid && ((io.rgb.payload(12) && !need_sof) || (!io.rgb.payload(12) && need_sof) )){ 63 | force_clear_desync := True 64 | } 65 | .otherwise{ 66 | io.rgb.ready := True 67 | } 68 | } 69 | 70 | when(force_clear_no_data || force_clear_desync){ 71 | clk_div_cntr.clear() 72 | col_cntr.clear() 73 | bin_dec_phase.clear() 74 | bit_cntr.clear() 75 | row_cntr.clear() 76 | } 77 | 78 | io.hub75.clk := RegNext(bin_dec_phase === 0 && col_active_phase && (clk_div_cntr >= sclk_ratio/2)) init(False) 79 | io.hub75.oe_ := RegNext(bin_dec_phase === 0 && !col_active_phase) init(True) 80 | io.hub75.lat := RegNext(bin_dec_phase === 0 && col_cntr === (conf.panels.size/2 * conf.panel_cols)+1) init(False) 81 | 82 | io.hub75.r0 := RegNextWhen(io.rgb.payload( 0), io.rgb.valid && io.rgb.ready) 83 | io.hub75.g0 := RegNextWhen(io.rgb.payload( 1), io.rgb.valid && io.rgb.ready) 84 | io.hub75.b0 := RegNextWhen(io.rgb.payload( 2), io.rgb.valid && io.rgb.ready) 85 | io.hub75.r1 := RegNextWhen(io.rgb.payload( 3), io.rgb.valid && io.rgb.ready) 86 | io.hub75.g1 := RegNextWhen(io.rgb.payload( 4), io.rgb.valid && io.rgb.ready) 87 | io.hub75.b1 := RegNextWhen(io.rgb.payload( 5), io.rgb.valid && io.rgb.ready) 88 | io.hub75.r2 := RegNextWhen(io.rgb.payload( 6), io.rgb.valid && io.rgb.ready) 89 | io.hub75.g2 := RegNextWhen(io.rgb.payload( 7), io.rgb.valid && io.rgb.ready) 90 | io.hub75.b2 := RegNextWhen(io.rgb.payload( 8), io.rgb.valid && io.rgb.ready) 91 | io.hub75.r3 := RegNextWhen(io.rgb.payload( 9), io.rgb.valid && io.rgb.ready) 92 | io.hub75.g3 := RegNextWhen(io.rgb.payload(10), io.rgb.valid && io.rgb.ready) 93 | io.hub75.b3 := RegNextWhen(io.rgb.payload(11), io.rgb.valid && io.rgb.ready) 94 | 95 | io.hub75.row := RegNextWhen(row_cntr.value, col_cntr.willOverflow) init(0) 96 | 97 | } 98 | 99 | 100 | 101 | 102 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/LedGpu.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | import scala.collection.mutable.ArrayBuffer 5 | 6 | import spinal.core._ 7 | import spinal.lib._ 8 | import spinal.lib.bus.misc._ 9 | import spinal.lib.bus.amba3.apb._ 10 | 11 | object LedGpu { 12 | def getApb3Config() = Apb3Config(addressWidth = 8, dataWidth = 32) 13 | } 14 | 15 | class LedGpu(conf: Hub75Config, ledMemConf: LedMemConfig) extends Component { 16 | 17 | val io = new Bundle { 18 | 19 | } 20 | 21 | // val panel_info_vec = Vec(conf.panels.map(_.toPanelInfoHW(conf))) 22 | // val cur_panel_info = panel_info_vec(panel_cntr.value) 23 | 24 | /* 25 | // Loop through all pixels of the cube 26 | // 27 | // Plan: 28 | // A launch FIFO with: current value of pixel, coordinates, other attributes. 29 | // Filling up this FIFO is lowest priority. 30 | // 31 | // Instructions to load data from surrounding pixels on the same surface? 32 | // - load from FROM buffer to TO buffer 33 | // - 8 surrounding locations 34 | // - overflow behavior: use pixel on other face or clamp? 35 | 36 | // - F.rgb : FROM color of current pixel 37 | // - P.xyz : position of current pixel (x,y,z) 38 | // - C0.xyz : Constant attribute 39 | // - C1.xyz : Constant attribute 40 | // - C2.xyz : Constant attribute 41 | // - T0.xyz : temporary stronage 42 | // - T1.xyz : temporary stronage 43 | // 44 | // Instructions: 45 | // MUL.xyz : DEST.x = SRC0.x * SRC1.x, ... 46 | // ADD.xyz : DEST.x = SRC0.x + SRC1.x, ... 47 | // SUB.xyz : DEST.x = SRC0.x + SRC1.x, ... 48 | // DOT.xyz : DEST.x = SRC0.x + SRC1.y, ... 49 | 50 | // Function: (x-cx)^2 * (1/rx*rx) + (y-cy)^2 * (1/ry*ry) + (z-cz)^2 * (1/rz*rz) - 1 > 0 or < 0 51 | // C0: center of sphere 52 | // C1: 1/radius of sphere (different x,y,z sizes) 53 | // C2: 1/(radius+1) of sphere (different x,y,z sizes) 54 | SUB.xyz T0.xyz, P.xyz, C0.xyz 55 | MUL.xyz T0.xyz, T0.xyz, T0.xyz 56 | MUL.xyz T1.xyz, T0.xyz, C2.xyz 57 | MUL.xyz T0.xyz, T0.xyz, C1.xyz 58 | RADD T0.x, T0.xyz 59 | RADD T0.y, T1.xyz 60 | LD T1.xy, #1.0 61 | SUB T0.xy, T1.xy 62 | 63 | */ 64 | 65 | } 66 | 67 | 68 | 69 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/LedMem.scala: -------------------------------------------------------------------------------- 1 | package cube 2 | 3 | import spinal.core._ 4 | import spinal.lib._ 5 | import spinal.lib.bus.misc._ 6 | import spinal.lib.bus.amba3.apb._ 7 | 8 | import cyclone2._ 9 | 10 | object LedMem { 11 | def getApb3Config() = Apb3Config(addressWidth = 16, dataWidth = 32) 12 | } 13 | 14 | case class LedMemConfig( 15 | memWords : Int, 16 | bpc : Int 17 | ) 18 | { 19 | def addrBits = log2Up(memWords) 20 | def dataBits = 3 * bpc 21 | } 22 | 23 | class LedMem(conf: LedMemConfig, isSim: Boolean = true) extends Component { 24 | 25 | import conf._ 26 | 27 | val io = new Bundle { 28 | val led_mem_a_req = in(Bool) 29 | val led_mem_a_addr = in(UInt(conf.addrBits bits)) 30 | val led_mem_a_wr = in(Bool) 31 | val led_mem_a_wr_data = in(Bits(conf.dataBits bits)) 32 | val led_mem_a_rd_data = out(Bits(conf.dataBits bits)) 33 | 34 | val led_mem_b_req = in(Bool) 35 | val led_mem_b_addr = in(UInt(conf.addrBits bits)) 36 | val led_mem_b_wr = in(Bool) 37 | val led_mem_b_wr_data = in(Bits(conf.dataBits bits)) 38 | val led_mem_b_rd_data = out(Bits(conf.dataBits bits)) 39 | } 40 | 41 | println(s"LedMem: memWords: ${conf.memWords}") 42 | 43 | if (isSim){ 44 | val u_led_ram = Mem(UInt(conf.dataBits bits), conf.memWords).addAttribute("ramstyle", "no_rw_check") 45 | 46 | io.led_mem_a_rd_data := u_led_ram.readWriteSync( 47 | enable = io.led_mem_a_req, 48 | address = io.led_mem_a_addr, 49 | write = io.led_mem_a_wr, 50 | data = io.led_mem_a_wr_data.asUInt 51 | ).asBits 52 | 53 | io.led_mem_b_rd_data := u_led_ram.readWriteSync( 54 | enable = io.led_mem_b_req, 55 | address = io.led_mem_b_addr, 56 | write = io.led_mem_b_wr, 57 | data = io.led_mem_b_wr_data.asUInt 58 | ).asBits 59 | } 60 | else { 61 | val u_led_ram = new led_ram() 62 | 63 | u_led_ram.io.clock_a := ClockDomain.current.readClockWire 64 | u_led_ram.io.address_a := io.led_mem_a_addr 65 | u_led_ram.io.wren_a := io.led_mem_a_req && io.led_mem_a_wr 66 | u_led_ram.io.data_a := io.led_mem_a_wr_data 67 | io.led_mem_a_rd_data := u_led_ram.io.q_a 68 | 69 | u_led_ram.io.clock_b := ClockDomain.current.readClockWire 70 | u_led_ram.io.address_b := io.led_mem_b_addr 71 | u_led_ram.io.wren_b := io.led_mem_b_req && io.led_mem_b_wr 72 | u_led_ram.io.data_b := io.led_mem_b_wr_data 73 | io.led_mem_b_rd_data := u_led_ram.io.q_b 74 | } 75 | 76 | 77 | def driveFrom(busCtrl: BusSlaveFactory, baseAddress: BigInt) = new Area { 78 | val mapping = SizeMapping(0x0, conf.memWords * 4) 79 | 80 | val led_mem_a_wr_addr = busCtrl.writeAddress(mapping) >> 2 81 | val led_mem_a_rd_addr = busCtrl.readAddress(mapping) >> 2 82 | 83 | val bus_a_wr_data = Bits(24 bits) 84 | busCtrl.nonStopWrite(bus_a_wr_data, 0) 85 | 86 | val mem_a_wr_data = bus_a_wr_data(23 downto 24-conf.bpc) ## 87 | bus_a_wr_data(15 downto 16-conf.bpc) ## 88 | bus_a_wr_data( 7 downto 8-conf.bpc) 89 | 90 | io.led_mem_a_req := False 91 | io.led_mem_a_wr := False 92 | io.led_mem_a_addr := led_mem_a_wr_addr 93 | 94 | busCtrl.onWritePrimitive(mapping, true, null){ 95 | io.led_mem_a_req := True 96 | io.led_mem_a_wr := True 97 | io.led_mem_a_addr := led_mem_a_wr_addr 98 | } 99 | io.led_mem_a_wr_data := mem_a_wr_data 100 | 101 | busCtrl.multiCycleRead(mapping, 2) 102 | busCtrl.onReadPrimitive(mapping, false, null){ 103 | io.led_mem_a_req := True 104 | io.led_mem_a_wr := False 105 | io.led_mem_a_addr := led_mem_a_rd_addr 106 | } 107 | busCtrl.readPrimitive(io.led_mem_a_rd_data, mapping, 0, null) 108 | } 109 | 110 | } 111 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/LedStreamer.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.misc._ 7 | import spinal.lib.bus.amba3.apb._ 8 | 9 | object LedStreamer { 10 | def getApb3Config() = Apb3Config(addressWidth = 4, dataWidth = 32) 11 | } 12 | 13 | class LedStreamer extends Component { 14 | 15 | val io = new Bundle { 16 | val start = in(Bool) 17 | val active = out(Bool) 18 | 19 | val led_stream = master(Stream(Bits(24 bits))) 20 | 21 | val led_mem_rd = out(Bool) 22 | val led_mem_rd_addr = out(UInt(9 bits)) 23 | val led_mem_rd_data = in(Bits(24 bits)) 24 | } 25 | 26 | object FsmState extends SpinalEnum { 27 | val Idle = newElement() 28 | val FetchLedVal = newElement() 29 | val ReadyLedVal = newElement() 30 | val SendLedVal = newElement() 31 | val ShiftLedTh = newElement() 32 | val ShiftLedTl = newElement() 33 | val LedReset = newElement() 34 | } 35 | 36 | val cur_state = Reg(FsmState()) init(FsmState.Idle) 37 | 38 | val led_cntr = Reg(UInt(9 bits)) 39 | 40 | val led_mem_addr = Reg(UInt(9 bits)) 41 | val led_val = Reg(Bits(24 bits)) 42 | 43 | io.led_stream.valid := False 44 | io.led_stream.payload := led_val 45 | 46 | io.led_mem_rd := False 47 | io.led_mem_rd_addr := led_mem_addr.resize(io.led_mem_rd_addr.getWidth) 48 | 49 | io.active := True 50 | 51 | switch(cur_state){ 52 | is(FsmState.Idle){ 53 | io.led_stream.valid := False 54 | io.active := False 55 | 56 | led_cntr := 383 57 | led_mem_addr := 0 58 | 59 | when(io.start && !RegNext(io.start)){ 60 | cur_state := FsmState.FetchLedVal 61 | } 62 | } 63 | 64 | is(FsmState.FetchLedVal){ 65 | io.led_mem_rd := True 66 | led_mem_addr := led_mem_addr + 1 67 | cur_state := FsmState.ReadyLedVal 68 | } 69 | 70 | is(FsmState.ReadyLedVal){ 71 | led_val := io.led_mem_rd_data 72 | 73 | cur_state := FsmState.SendLedVal 74 | } 75 | 76 | is(FsmState.SendLedVal){ 77 | 78 | io.led_stream.valid := True 79 | io.led_stream.payload := led_val 80 | 81 | io.led_mem_rd := True 82 | 83 | when(io.led_stream.ready){ 84 | when(led_cntr === 0){ 85 | cur_state := FsmState.Idle 86 | } 87 | .otherwise{ 88 | led_cntr := led_cntr - 1 89 | led_mem_addr := led_mem_addr + 1 90 | led_val := io.led_mem_rd_data 91 | cur_state := FsmState.SendLedVal 92 | } 93 | } 94 | } 95 | } 96 | 97 | def driveFrom(busCtrl: BusSlaveFactory, baseAddress: BigInt) = new Area { 98 | val start = busCtrl.createReadAndWrite(io.start, 0x0) init(False) 99 | val active = busCtrl.createReadOnly(io.active, 0x4) 100 | 101 | io.start := start 102 | active := io.active 103 | } 104 | 105 | } 106 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cube/WS2812Drv.scala: -------------------------------------------------------------------------------- 1 | 2 | package cube 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.io._ 7 | import spinal.lib.bus.misc._ 8 | 9 | class WS2812Drv extends Component { 10 | 11 | def osc_clk_mhz = 12 12 | 13 | def led_t0l_ns = 850 14 | def led_t0h_ns = 400 15 | 16 | def led_t1l_ns = 450 17 | def led_t1h_ns = 800 18 | 19 | def reset_ns = 280000 20 | 21 | def led_t0l_cyc = led_t0l_ns * osc_clk_mhz / 1000 22 | def led_t0h_cyc = led_t0h_ns * osc_clk_mhz / 1000 23 | 24 | def led_t1l_cyc = led_t1l_ns * osc_clk_mhz / 1000 25 | def led_t1h_cyc = led_t1h_ns * osc_clk_mhz / 1000 26 | 27 | def reset_cyc = reset_ns * osc_clk_mhz / 1000 28 | 29 | 30 | val io = new Bundle { 31 | val led_stream = slave(Stream(Bits(24 bits))) 32 | val led_din = out(Bool) 33 | } 34 | 35 | object FsmState extends SpinalEnum { 36 | val Idle = newElement() 37 | val LoadLedVal = newElement() 38 | val ShiftLedTh = newElement() 39 | val ShiftLedTl = newElement() 40 | val LedReset = newElement() 41 | } 42 | 43 | 44 | val cur_state = Reg(FsmState()) init(FsmState.Idle) 45 | 46 | val bit_cntr = Reg(UInt(5 bits)) 47 | val t_cntr = Reg(UInt(13 bits)) 48 | val led_shift = Reg(Bits(24 bits)) 49 | 50 | io.led_stream.ready := False 51 | io.led_din := False 52 | 53 | switch(cur_state){ 54 | is(FsmState.Idle){ 55 | when(io.led_stream.valid){ 56 | cur_state := FsmState.LoadLedVal 57 | } 58 | } 59 | 60 | is(FsmState.LoadLedVal){ 61 | 62 | when(io.led_stream.valid){ 63 | led_shift := io.led_stream.payload 64 | bit_cntr := 23 65 | t_cntr := 0 66 | cur_state := FsmState.ShiftLedTh 67 | } 68 | .otherwise{ 69 | cur_state := FsmState.LedReset 70 | } 71 | } 72 | 73 | is(FsmState.ShiftLedTh){ 74 | io.led_din := True 75 | t_cntr := t_cntr + 1 76 | 77 | when ((led_shift(23) && t_cntr === led_t1h_cyc) || (!led_shift(23) && t_cntr === led_t0h_cyc)) { 78 | t_cntr := 0 79 | cur_state := FsmState.ShiftLedTl 80 | } 81 | } 82 | 83 | is(FsmState.ShiftLedTl){ 84 | io.led_din := False 85 | t_cntr := t_cntr + 1 86 | 87 | when ((led_shift(23) && t_cntr === led_t1l_cyc) || (!led_shift(23) && t_cntr === led_t0l_cyc)) { 88 | t_cntr := 0 89 | 90 | when(bit_cntr =/= 0) { 91 | bit_cntr := bit_cntr -1 92 | led_shift := led_shift(22 downto 0) ## False 93 | cur_state := FsmState.ShiftLedTh 94 | } 95 | .otherwise{ 96 | io.led_stream.ready := True 97 | cur_state := FsmState.LoadLedVal 98 | } 99 | } 100 | } 101 | 102 | is(FsmState.LedReset){ 103 | t_cntr := t_cntr + 1 104 | 105 | when (t_cntr === reset_cyc){ 106 | cur_state := FsmState.Idle 107 | } 108 | } 109 | 110 | } 111 | 112 | } 113 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cyclone2/led_ram.scala: -------------------------------------------------------------------------------- 1 | 2 | package cyclone2 3 | 4 | import spinal.core._ 5 | 6 | class led_ram extends BlackBox { 7 | 8 | val io = new Bundle { 9 | val clock_a = in(Bool) 10 | val address_a = in(UInt(14 bits)) 11 | val wren_a = in(Bool) 12 | val data_a = in(Bits(18 bits)) 13 | val q_a = out(Bits(18 bits)) 14 | 15 | val clock_b = in(Bool) 16 | val address_b = in(UInt(14 bits)) 17 | val wren_b = in(Bool) 18 | val data_b = in(Bits(18 bits)) 19 | val q_b = out(Bits(18 bits)) 20 | } 21 | 22 | noIoPrefix() 23 | 24 | //addRTLPath("./quartus/altera_models/cpu_ram/cpu_ram_bb.v") 25 | } 26 | 27 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cyclone2/main_pll.scala: -------------------------------------------------------------------------------- 1 | 2 | package cyclone2 3 | 4 | import spinal.core._ 5 | 6 | class main_pll() extends BlackBox { 7 | 8 | val io = new Bundle { 9 | val inclk0 = in(Bool) 10 | val c0 = out(Bool) 11 | val locked = out(Bool) 12 | } 13 | 14 | noIoPrefix() 15 | } 16 | 17 | 18 | -------------------------------------------------------------------------------- /spinal/src/main/scala/ice40/SB_HFOSC.scala: -------------------------------------------------------------------------------- 1 | 2 | package ice40 3 | 4 | import spinal.core._ 5 | 6 | class SB_HFOSC( 7 | clkhf_div : String = "0b00" 8 | ) extends BlackBox { 9 | 10 | val generic = new Generic { 11 | val CLKHF_DIV = clkhf_div 12 | } 13 | 14 | val io = new Bundle { 15 | val CLKHFPU = in(Bool) 16 | val CLKHFEN = in(Bool) 17 | val CLKHF = out(Bool) 18 | } 19 | 20 | noIoPrefix() 21 | } 22 | 23 | 24 | -------------------------------------------------------------------------------- /spinal/src/main/scala/ice40/SB_I2C.scala: -------------------------------------------------------------------------------- 1 | 2 | 3 | package ice40 4 | 5 | import spinal.core._ 6 | 7 | class SB_I2C( 8 | i2c_slave_init_addr : String = "0b1111100001", 9 | bus_addr74 : String = "0b0001" 10 | ) extends BlackBox { 11 | 12 | val generic = new Generic { 13 | val I2C_SLAVE_INIT_ADDR = i2c_slave_init_addr 14 | val BUS_ADDR74 = bus_addr74 15 | } 16 | 17 | val io = new Bundle { 18 | val SBCLKI = in(Bool) 19 | val SBRWI = in(Bool) 20 | val SBSTBI = in(Bool) 21 | val SBADRI7 = in(Bool) 22 | val SBADRI6 = in(Bool) 23 | val SBADRI5 = in(Bool) 24 | val SBADRI4 = in(Bool) 25 | val SBADRI3 = in(Bool) 26 | val SBADRI2 = in(Bool) 27 | val SBADRI1 = in(Bool) 28 | val SBADRI0 = in(Bool) 29 | val SBDATI7 = in(Bool) 30 | val SBDATI6 = in(Bool) 31 | val SBDATI5 = in(Bool) 32 | val SBDATI4 = in(Bool) 33 | val SBDATI3 = in(Bool) 34 | val SBDATI2 = in(Bool) 35 | val SBDATI1 = in(Bool) 36 | val SBDATI0 = in(Bool) 37 | val SCLI = in(Bool) 38 | val SDAI = in(Bool) 39 | 40 | val SBDATO7 = out(Bool) 41 | val SBDATO6 = out(Bool) 42 | val SBDATO5 = out(Bool) 43 | val SBDATO4 = out(Bool) 44 | val SBDATO3 = out(Bool) 45 | val SBDATO2 = out(Bool) 46 | val SBDATO1 = out(Bool) 47 | val SBDATO0 = out(Bool) 48 | val SBACKO = out(Bool) 49 | val I2CIRQ = out(Bool) 50 | val I2CWKUP = out(Bool) 51 | val SCLO = out(Bool) 52 | val SCLOE = out(Bool) 53 | val SDAO = out(Bool) 54 | val SDAOE = out(Bool) 55 | } 56 | 57 | noIoPrefix() 58 | } 59 | 60 | 61 | -------------------------------------------------------------------------------- /spinal/src/main/scala/ice40/SB_RGBA_DRV.scala: -------------------------------------------------------------------------------- 1 | 2 | 3 | package ice40 4 | 5 | import spinal.core._ 6 | 7 | class SB_RGBA_DRV( 8 | current_mode : String = "0b0", 9 | rgb0_current : String = "0b000000", 10 | rgb1_current : String = "0b000000", 11 | rgb2_current : String = "0b000000" 12 | ) extends BlackBox { 13 | 14 | val generic = new Generic { 15 | val CURRENT_MODE = current_mode 16 | val RGB0_CURRENT = rgb0_current 17 | val RGB1_CURRENT = rgb1_current 18 | val RGB2_CURRENT = rgb2_current 19 | } 20 | 21 | val io = new Bundle { 22 | val CURREN = in(Bool) 23 | val RGBLEDEN = in(Bool) 24 | val RGB0PWM = in(Bool) 25 | val RGB1PWM = in(Bool) 26 | val RGB2PWM = in(Bool) 27 | 28 | val RGB0 = out(Bool) 29 | val RGB1 = out(Bool) 30 | val RGB2 = out(Bool) 31 | } 32 | 33 | noIoPrefix() 34 | } 35 | 36 | 37 | -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.dis 3 | *.elf 4 | *.hex 5 | *.map 6 | *.mem 7 | *.o 8 | *.mif 9 | -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- 1 | 2 | MEM_BYTES = 16384 3 | MEM_WORDS = 4096 4 | 5 | OBJ_FILES = start.o main.o led_render.o hub75_streamer.o 6 | 7 | TOOLS_PREFIX = /opt/riscv32i/bin 8 | TARGET = $(TOOLS_PREFIX)/riscv32-unknown-elf 9 | AS = $(TARGET)-as 10 | ASFLAGS = -march=rv32imc -mabi=ilp32 11 | LD = $(TARGET)-gcc 12 | LDFLAGS = -march=rv32imc -mabi=ilp32 -Wl,-Tsections.lds,-Map,progmem.map -ffreestanding -nostartfiles 13 | CC = $(TARGET)-gcc 14 | #CFLAGS = -march=rv32imc -mabi=ilp32 -Wall -Wextra -pedantic -DFREQ=$(FREQ_PLL)000000 -O2 15 | CFLAGS = -march=rv32imc -mabi=ilp32 -Wall -Wextra -Wpedantic -DFREQ=$(FREQ_PLL)000000 -O2 16 | OBJCOPY = $(TARGET)-objcopy 17 | OBJDUMP = $(TARGET)-objdump 18 | 19 | .PHONY: all clean syntax time stat flash 20 | 21 | #all: progmem.dis progmem.bin progmem0.coe progmem0.mif progmem0.hex progmem.mem 22 | all: progmem.dis progmem.bin progmem4k.bin progmem.mem progmem.hex progmem0.mif 23 | 24 | progmem.dis: progmem_dis.elf 25 | $(OBJDUMP) -s -D $< > $@ 26 | 27 | progmem.hex: progmem4k.bin 28 | $(OBJCOPY) --change-addresses 0x80000000 -O ihex -I binary $< $@ 29 | 30 | progmem0.hex: progmem.bin 31 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 0 -i 4 $< > progmem0.hex 32 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 1 -i 4 $< > progmem1.hex 33 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 2 -i 4 $< > progmem2.hex 34 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 3 -i 4 $< > progmem3.hex 35 | 36 | progmem0.coe: progmem.bin 37 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 0 -i 4 $< > progmem0.coe 38 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 1 -i 4 $< > progmem1.coe 39 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 2 -i 4 $< > progmem2.coe 40 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 3 -i 4 $< > progmem3.coe 41 | 42 | progmem0.mif: progmem.bin 43 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 0 -i 4 $< > progmem0.mif 44 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 1 -i 4 $< > progmem1.mif 45 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 2 -i 4 $< > progmem2.mif 46 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 3 -i 4 $< > progmem3.mif 47 | 48 | progmem.mif: progmem.bin 49 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 32 $< > progmem.mif 50 | 51 | progmem.mem: progmem.bin 52 | ../misc/create_mif.rb -f mem -d $(MEM_WORDS) -w 32 $< > progmem.mem 53 | 54 | progmem.bin: progmem.elf 55 | $(OBJCOPY) -O binary $< $@ 56 | 57 | progmem4k.bin: progmem.elf 58 | $(OBJCOPY) --pad-to=$(MEM_BYTES) -O binary $< $@ 59 | 60 | progmem.elf: $(OBJ_FILES) global.h hub75_streamer.h reg.h top_defines.h sections.lds Makefile ../movie/ricks_compr.h ../movie/palette.h 61 | $(LD) $(LDFLAGS) -s -o $@ $(OBJ_FILES) > progmem.map 62 | 63 | progmem_dis.elf: $(OBJ_FILES) top_defines.h sections.lds Makefile 64 | $(LD) $(LDFLAGS) -o $@ $(OBJ_FILES) > progmem.map 65 | 66 | clean: 67 | \rm -fr *.o *.hex *.elf *.dis *.bin *.coe *.map *.mif *.mem 68 | -------------------------------------------------------------------------------- /sw/global.h: -------------------------------------------------------------------------------- 1 | #ifndef GLOBAL_H 2 | #define GLOBAL_H 3 | 4 | #include 5 | #include "top_defines.h" 6 | 7 | typedef unsigned char byte; 8 | typedef int bool; 9 | 10 | #endif 11 | -------------------------------------------------------------------------------- /sw/hub75_streamer.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | 5 | #include "top_defines.h" 6 | #include "reg.h" 7 | #include "hub75_streamer.h" 8 | 9 | typedef struct { 10 | int topLeftCoordX; 11 | int topLeftCoordY; 12 | int topLeftCoordZ; 13 | 14 | int side; 15 | int sideTop; 16 | int sideRotation; 17 | 18 | int xIncr; 19 | int yIncr; 20 | int zIncr; 21 | 22 | } t_panel_info; 23 | 24 | const int panel_rows = 16; 25 | const int panel_cols = 32; 26 | int pixels_per_panel; 27 | 28 | typedef enum { 29 | SIDE_LEFT = 0, 30 | SIDE_FRONT = 1, 31 | SIDE_RIGHT = 2, 32 | SIDE_BACK = 3, 33 | SIDE_TOP = 4, 34 | SIDE_BOTTOM = 5 35 | } e_side_nr; 36 | 37 | typedef enum { 38 | ORIENT_X_Y = 0, 39 | ORIENT_X_INV_Y = 1, 40 | ORIENT_INV_X_Y = 2, 41 | ORIENT_INV_X_INV_Y = 3, 42 | 43 | ORIENT_Y_X = 4, 44 | ORIENT_Y_INV_X = 5, 45 | ORIENT_INV_Y_X = 6, 46 | ORIENT_INV_Y_INV_X = 7 47 | } e_orient; 48 | 49 | 50 | t_panel_info panels[] = { 51 | // L2 - Left 52 | { 1, 1,-1, 0, 1, 270, -1,-1, 0 }, 53 | { 1, 0,-1, 0, 1, 90, -1,-1, 0 }, 54 | 55 | // L1 - Back 56 | { 1, 1, 1, 3, 1, 180, 0,-1,-1 }, 57 | { 1, 0, 1, 3, 1, 0, 0,-1,-1 }, 58 | 59 | // L0 - Bottom 60 | {-1, 1, 1, 5, 1, 270, 1,-1, 0 }, 61 | { 1, 0, 1, 5, 1, 90, 1,-1, 0 }, 62 | 63 | // R2 - Top 64 | { 1, 1,-1, 4, 1, 270, -1,-1, 0 }, 65 | { 1, 0,-1, 4, 1, 90, -1,-1, 0 }, 66 | 67 | // R1 - Front 68 | { 1, 1, 1, 1, 1, 0, 0,-1,-1 }, 69 | { 1, 0, 1, 1, 1, 180, 0,-1,-1 }, 70 | 71 | // R0 - Right 72 | {-1, 1, 1, 2, 1, 270, 1,-1, 0 }, 73 | { 1, 0, 1, 2, 1, 90, 1,-1, 0 } 74 | 75 | }; 76 | 77 | void hub75s_config(void) 78 | { 79 | pixels_per_panel = panel_rows * panel_cols; 80 | 81 | for(int i=0; i<12;++i){ 82 | t_panel_info *pi = &panels[i]; 83 | 84 | int memAddrStartPh0 = pi->side * 2 * pixels_per_panel; 85 | int memAddrStartPh1 = pi->side * 2 * pixels_per_panel; 86 | int memAddrColMul = 1; 87 | int memAddrRowMul = 1; 88 | 89 | if (pi->sideRotation == 0){ 90 | memAddrStartPh1 += panel_rows/2 * panel_cols; 91 | 92 | if (!pi->sideTop){ 93 | memAddrStartPh0 += panel_rows * panel_cols; 94 | memAddrStartPh1 += panel_rows * panel_cols; 95 | } 96 | memAddrColMul = 1; 97 | memAddrRowMul = panel_cols; 98 | } 99 | else if (pi->sideRotation == 90) { 100 | memAddrStartPh0 += panel_cols -1; 101 | memAddrStartPh1 += panel_cols -1 - panel_rows/2; 102 | 103 | if (!pi->sideTop){ 104 | memAddrStartPh0 -= panel_cols/2; 105 | memAddrStartPh1 -= panel_cols/2; 106 | } 107 | memAddrColMul = panel_cols; 108 | memAddrRowMul = -1; 109 | } 110 | else if (pi->sideRotation == 180){ 111 | memAddrStartPh0 += panel_cols -1 + (panel_rows*2 -1) * panel_cols; 112 | memAddrStartPh1 += panel_cols -1 + (panel_rows*3/2 -1) * panel_cols; 113 | 114 | if (!pi->sideTop){ 115 | memAddrStartPh0 -= panel_rows * panel_cols; 116 | memAddrStartPh1 -= panel_rows * panel_cols; 117 | } 118 | memAddrColMul = -1; 119 | memAddrRowMul = -panel_cols; 120 | } 121 | else{ 122 | memAddrStartPh0 += (panel_rows*2 -1) * panel_cols; 123 | memAddrStartPh1 += (panel_rows*2 -1) * panel_cols + (panel_rows/2); 124 | 125 | if (!pi->sideTop){ 126 | memAddrStartPh0 += panel_cols/2; 127 | memAddrStartPh1 += panel_cols/2; 128 | } 129 | memAddrColMul = -panel_cols; 130 | memAddrRowMul = 1; 131 | } 132 | 133 | HUB75S_PI_REG_WR(i, MEM_ADDR_START_PH0, memAddrStartPh0); 134 | HUB75S_PI_REG_WR(i, MEM_ADDR_START_PH1, memAddrStartPh1); 135 | HUB75S_PI_REG_WR(i, MEM_ADDR_COL_MUL, memAddrColMul); 136 | HUB75S_PI_REG_WR(i, MEM_ADDR_ROW_MUL, memAddrRowMul); 137 | 138 | } 139 | } 140 | 141 | 142 | void hub75s_start(void) 143 | { 144 | REG_WR_FIELD(HUB75S_CONFIG, ENABLE, 1); 145 | REG_WR_FIELD(HUB75S_CONFIG, START, 1); 146 | REG_WR_FIELD(HUB75S_CONFIG, AUTO_RESTART, 1); 147 | REG_WR_FIELD(HUB75S_CONFIG, BUFFER_NR, 0); 148 | } 149 | 150 | void hub75s_dim(unsigned char r_dim, unsigned char g_dim, unsigned char b_dim) 151 | { 152 | REG_WR(HUB75S_RGB_DIM, (b_dim << 16) | (g_dim << 8) | r_dim); 153 | } 154 | 155 | int hub75s_get_scratch_buffer(void) 156 | { 157 | int row; 158 | do{ 159 | row = REG_RD_FIELD(HUB75S_STATUS, CUR_ROW_NR); 160 | } 161 | while(row != 1); 162 | 163 | return !REG_RD_FIELD(HUB75S_STATUS, CUR_BUFFER_NR); 164 | } 165 | 166 | uint32_t hub75s_calc_phys_addr(int buffer, int log_addr) 167 | { 168 | const uint32_t side_width = HUB75S_SIDE_WIDTH; 169 | const uint32_t side_height = HUB75S_SIDE_HEIGHT; 170 | const uint32_t side_size = HUB75S_SIDE_SIZE; 171 | const uint32_t strip_width = HUB75S_STRIP_WIDTH; 172 | const uint32_t strip_size = HUB75S_STRIP_SIZE; 173 | const uint32_t ring_size = HUB75S_RING_SIZE; 174 | 175 | uint32_t cur_ring_nr = log_addr / ring_size; 176 | log_addr = log_addr % ring_size; 177 | 178 | uint32_t cur_strip_y_nr = log_addr / strip_size; 179 | uint32_t cur_strip_x_nr = (log_addr / side_width) & 3; 180 | 181 | uint32_t y = (log_addr / strip_width) % side_height; 182 | uint32_t x = log_addr % side_width; 183 | 184 | const uint8_t side_nr_lut[3][3][4] = { 185 | // Ring 0: | L | F | R | Ba 186 | { 187 | { SIDE_TOP, SIDE_TOP, SIDE_TOP, SIDE_TOP }, 188 | { SIDE_LEFT, SIDE_FRONT, SIDE_RIGHT, SIDE_BACK }, 189 | { SIDE_BOTTOM, SIDE_BOTTOM, SIDE_BOTTOM, SIDE_BOTTOM } 190 | } 191 | }; 192 | 193 | const uint8_t orient_class_lut[3][3][4] = { 194 | // Ring 0: | L | F | R | Ba| 195 | { 196 | // 197 | { ORIENT_INV_Y_X, ORIENT_X_Y, ORIENT_Y_INV_X, ORIENT_INV_X_INV_Y }, 198 | { ORIENT_X_Y, ORIENT_X_Y, ORIENT_X_Y, ORIENT_X_Y }, 199 | { ORIENT_Y_INV_X, ORIENT_X_Y, ORIENT_INV_Y_X, ORIENT_INV_X_INV_Y } 200 | } 201 | }; 202 | 203 | uint32_t cur_side_nr = side_nr_lut [cur_ring_nr][cur_strip_y_nr][cur_strip_x_nr]; 204 | uint32_t cur_orient_class = orient_class_lut[cur_ring_nr][cur_strip_y_nr][cur_strip_x_nr]; 205 | 206 | uint32_t cur_x = (cur_orient_class == ORIENT_X_Y || cur_orient_class == ORIENT_X_INV_Y) ? x : 207 | (cur_orient_class == ORIENT_INV_X_Y || cur_orient_class == ORIENT_INV_X_INV_Y) ? 31-x : 208 | (cur_orient_class == ORIENT_Y_X || cur_orient_class == ORIENT_Y_INV_X) ? y : 209 | 31-y ; 210 | 211 | uint32_t cur_y = (cur_orient_class == ORIENT_X_Y || cur_orient_class == ORIENT_INV_X_Y) ? y : 212 | (cur_orient_class == ORIENT_X_INV_Y || cur_orient_class == ORIENT_INV_X_INV_Y) ? 31-y : 213 | (cur_orient_class == ORIENT_Y_X || cur_orient_class == ORIENT_INV_Y_X) ? x : 214 | 31-x ; 215 | 216 | uint32_t phys_addr = cur_side_nr * side_size + (cur_y * 32) + cur_x; 217 | phys_addr += buffer * 6 * side_size; 218 | 219 | return phys_addr; 220 | } 221 | 222 | 223 | 224 | -------------------------------------------------------------------------------- /sw/hub75_streamer.h: -------------------------------------------------------------------------------- 1 | #ifndef HUB75_STREAMER_H 2 | #define HUB75_STREAMER_H 3 | 4 | typedef enum { 5 | RING_LFRBa = 0, 6 | RING_FBoBaT = 1, 7 | RING_LBoRT = 2, 8 | } e_hub75_ring; 9 | 10 | #define HUB75S_SIDE_HEIGHT 32 11 | #define HUB75S_SIDE_WIDTH 32 12 | #define HUB75S_SIDE_SIZE (HUB75S_SIDE_HEIGHT * HUB75S_SIDE_WIDTH) 13 | 14 | #define HUB75S_STRIP_HEIGHT HUB75S_SIDE_HEIGHT 15 | #define HUB75S_STRIP_WIDTH (HUB75S_SIDE_WIDTH * 8) 16 | #define HUB75S_STRIP_SIZE (HUB75S_STRIP_WIDTH * HUB75S_STRIP_HEIGHT) 17 | 18 | #define HUB75S_RING_WIDTH (HUB75S_STRIP_WIDTH) 19 | #define HUB75S_RING_HEIGHT (HUB75S_STRIP_HEIGHT * 4) 20 | #define HUB75S_RING_SIZE (HUB75S_RING_WIDTH * HUB75S_RING_HEIGHT) 21 | 22 | void hub75s_config(void); 23 | void hub75s_start(void); 24 | int hub75s_get_scratch_buffer(void); 25 | void hub75s_dim(unsigned char r_dim, unsigned char g_dim, unsigned char b_dim); 26 | uint32_t hub75s_calc_phys_addr(int buffer, int log_addr); 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /sw/i2c.c: -------------------------------------------------------------------------------- 1 | 2 | #include "global.h" 3 | #include "top_defines.h" 4 | #include "i2c.h" 5 | #include "reg.h" 6 | 7 | #define IOWR_ALTERA_AVALON_PIO_SET_BITS(addr, bits) (REG_WR(DVI_CTRL_SET, (bits))) 8 | #define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(addr, bits) (REG_WR(DVI_CTRL_CLR, (bits))) 9 | #define IORD_ALTERA_AVALON_PIO_DATA(addr) (REG_RD(DVI_CTRL_RD)) 10 | 11 | void i2c_set_scl(i2c_ctx_t *ctx, int bit) 12 | { 13 | if (bit) 14 | IOWR_ALTERA_AVALON_PIO_SET_BITS(ctx->base_addr, 1 << ctx->scl_pin_nr); 15 | else 16 | IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(ctx->base_addr, 1 << ctx->scl_pin_nr); 17 | } 18 | 19 | void i2c_set_sda(i2c_ctx_t *ctx, int bit) 20 | { 21 | if (bit) 22 | IOWR_ALTERA_AVALON_PIO_SET_BITS(ctx->base_addr, 1 << ctx->sda_pin_nr); 23 | else 24 | IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(ctx->base_addr, 1 << ctx->sda_pin_nr); 25 | } 26 | 27 | 28 | static int i2c_get_scl(i2c_ctx_t *ctx) 29 | { 30 | return (IORD_ALTERA_AVALON_PIO_DATA(ctx->base_addr) >> ctx->scl_pin_nr) & 1; 31 | } 32 | 33 | static int i2c_get_sda(i2c_ctx_t *ctx) 34 | { 35 | return (IORD_ALTERA_AVALON_PIO_DATA(ctx->base_addr) >> ctx->sda_pin_nr) & 1; 36 | } 37 | 38 | void i2c_init(i2c_ctx_t *ctx) 39 | { 40 | i2c_set_sda(ctx, 1); 41 | i2c_set_scl(ctx, 1); 42 | } 43 | 44 | 45 | void i2c_dly() 46 | { 47 | int i; 48 | for(i=0;i<15;++i){ 49 | IOWR_ALTERA_AVALON_PIO_SET_BITS(PIO_0_BASE, 0x80); 50 | } 51 | } 52 | 53 | void i2c_start(i2c_ctx_t *ctx) 54 | { 55 | i2c_set_sda(ctx, 1); // i2c start bit sequence 56 | i2c_dly(); 57 | i2c_set_scl(ctx, 1); 58 | i2c_dly(); 59 | i2c_set_sda(ctx, 0); 60 | i2c_dly(); 61 | i2c_set_scl(ctx, 0); 62 | i2c_dly(); 63 | i2c_dly(); 64 | } 65 | 66 | void i2c_stop(i2c_ctx_t *ctx) 67 | { 68 | i2c_dly(); 69 | i2c_set_sda(ctx, 0); // i2c stop bit sequence 70 | i2c_dly(); 71 | i2c_set_scl(ctx, 1); 72 | i2c_dly(); 73 | i2c_set_sda(ctx, 1); 74 | i2c_dly(); 75 | } 76 | 77 | unsigned char i2c_rx(i2c_ctx_t *ctx, char ack) 78 | { 79 | char x, d=0; 80 | i2c_set_sda(ctx, 1); 81 | 82 | for(x=0; x<8; x++) { 83 | d <<= 1; 84 | 85 | i2c_set_scl(ctx, 1); 86 | i2c_dly(); 87 | // wait for any i2c_set_scl clock stretching 88 | while(i2c_get_scl(ctx)==0); 89 | 90 | d |= i2c_get_sda(ctx); 91 | i2c_set_scl(ctx, 0); 92 | i2c_dly(); 93 | } 94 | i2c_dly(); 95 | 96 | if(ack) 97 | i2c_set_sda(ctx, 0); 98 | else 99 | i2c_set_sda(ctx, 1); 100 | 101 | i2c_set_scl(ctx, 1); 102 | i2c_dly(); // send (N)ACK bit 103 | 104 | i2c_set_scl(ctx, 0); 105 | i2c_dly(); // send (N)ACK bit 106 | 107 | i2c_set_sda(ctx, 1); 108 | return d; 109 | } 110 | 111 | // return 1: ACK, 0: NACK 112 | int i2c_tx(i2c_ctx_t *ctx, unsigned char d) 113 | { 114 | char x; 115 | for(x=8; x; x--) { 116 | i2c_set_sda(ctx, (d & 0x80)>>7); 117 | d <<= 1; 118 | i2c_dly(); 119 | i2c_set_scl(ctx, 1); 120 | i2c_dly(); 121 | i2c_set_scl(ctx, 0); 122 | } 123 | i2c_dly(); 124 | i2c_dly(); 125 | i2c_set_sda(ctx, 1); 126 | i2c_dly(); 127 | i2c_set_scl(ctx, 1); 128 | i2c_dly(); 129 | 130 | int bit = i2c_get_sda(ctx); // possible ACK bit 131 | #if 0 132 | if (bit){ 133 | GPIO_DOUT_SET = 1; 134 | } 135 | else { 136 | GPIO_DOUT_CLR = 1; 137 | } 138 | #endif 139 | 140 | i2c_set_scl(ctx, 0); 141 | i2c_dly(); 142 | 143 | return !bit; 144 | } 145 | 146 | int i2c_write_buf(i2c_ctx_t *ctx, byte addr, byte* data, int len) 147 | { 148 | int ack; 149 | 150 | i2c_start(ctx); 151 | ack = i2c_tx(ctx, addr); 152 | if (!ack){ 153 | i2c_stop(ctx); 154 | return 0; 155 | } 156 | 157 | 158 | int i; 159 | for(i=0;i 3 | #include 4 | 5 | #include "led_render.h" 6 | #include "top_defines.h" 7 | #include "reg.h" 8 | 9 | /* 10 | void led_render_clear_leds(void) 11 | { 12 | t_panel_info *pi = panels; 13 | volatile uint32_t *led_mem = (volatile uint32_t *)(0x80000000 | LED_MEM_ADDR); 14 | 15 | while(pi->topLeftMemAddr >= 0){ 16 | volatile uint32_t *l = &led_mem[pi->topLeftMemAddr * panel_rows * panel_cols]; 17 | for(int i=0;i> (reg_name##_##field_name##_FIELD_START)) 15 | 16 | #define MEM_WR(mem_name, wr_addr, wr_data) (*( (volatile uint32_t *)(0x80000000 | mem_name##_ADDR) + (wr_addr)) = (wr_data)) 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /sw/sections.lds: -------------------------------------------------------------------------------- 1 | /* 2 | This is free and unencumbered software released into the public domain. 3 | 4 | Anyone is free to copy, modify, publish, use, compile, sell, or 5 | distribute this software, either in source code form or as a compiled 6 | binary, for any purpose, commercial or non-commercial, and by any 7 | means. 8 | */ 9 | 10 | SECTIONS { 11 | .memory : { 12 | . = 0x00000; 13 | start*(.text); 14 | *(.text); 15 | *(*); 16 | end = .; 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /sw/start.S: -------------------------------------------------------------------------------- 1 | .section .text 2 | .global start 3 | .global main 4 | 5 | .org 0x00000000 6 | start: 7 | /* set stack pointer */ 8 | lui sp,(16*1024)>>12 9 | 10 | /* jump to main C code */ 11 | jal ra,main 12 | 13 | /* trap */ 14 | ebreak 15 | 16 | .org 0x00000020 17 | irq: 18 | j irq 19 | 20 | -------------------------------------------------------------------------------- /sw/test/.gdbinit: -------------------------------------------------------------------------------- 1 | tui ena 2 | br main 3 | r 4 | -------------------------------------------------------------------------------- /sw/test/run.sh: -------------------------------------------------------------------------------- 1 | 2 | gcc -O0 -g -o test test.c ../hub75_streamer.c ../reg.h ../top_defines.h -I.. 3 | 4 | -------------------------------------------------------------------------------- /sw/test/test: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/cube/8825de87cb2f6d403bfcbcad1ebeddac23d54e3b/sw/test/test -------------------------------------------------------------------------------- /sw/test/test.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | 5 | #include "hub75_streamer.h" 6 | 7 | void main() 8 | { 9 | int pos_x = 0; 10 | int pos_y = -5; 11 | 12 | uint32_t log_addr = (pos_y + HUB75S_SIDE_HEIGHT) * HUB75S_STRIP_WIDTH + pos_x; 13 | uint32_t phys_addr = hub75s_calc_phys_addr(0, log_addr); 14 | 15 | printf("log_addr: %d -> phy_addr: %d\n", log_addr, phys_addr); 16 | 17 | } 18 | -------------------------------------------------------------------------------- /sw/top_defines.h: -------------------------------------------------------------------------------- 1 | 2 | #define TIMER_ADDR 0x00000000 3 | 4 | #define LED_READ_ADDR 0x00010000 5 | #define LED_WRITE_ADDR 0x00010004 6 | #define LED_DIR_ADDR 0x00010008 7 | 8 | #define LED_MEM_ADDR 0x00020000 9 | 10 | #define HUB75S_CONFIG_ADDR 0x00030000 11 | 12 | #define HUB75S_CONFIG_ENABLE_FIELD_START 0 13 | #define HUB75S_CONFIG_ENABLE_FIELD_LENGTH 1 14 | 15 | #define HUB75S_CONFIG_START_FIELD_START 1 16 | #define HUB75S_CONFIG_START_FIELD_LENGTH 1 17 | 18 | #define HUB75S_CONFIG_AUTO_RESTART_FIELD_START 2 19 | #define HUB75S_CONFIG_AUTO_RESTART_FIELD_LENGTH 1 20 | 21 | #define HUB75S_CONFIG_BUFFER_NR_FIELD_START 4 22 | #define HUB75S_CONFIG_BUFFER_NR_FIELD_LENGTH 1 23 | 24 | 25 | #define HUB75S_STATUS_ADDR 0x00030004 26 | 27 | #define HUB75S_STATUS_CUR_PANEL_NR_FIELD_START 0 28 | #define HUB75S_STATUS_CUR_PANEL_NR_FIELD_LENGTH 4 29 | 30 | #define HUB75S_STATUS_CUR_ROW_NR_FIELD_START 8 31 | #define HUB75S_STATUS_CUR_ROW_NR_FIELD_LENGTH 5 32 | 33 | #define HUB75S_STATUS_CUR_BIT_NR_FIELD_START 16 34 | #define HUB75S_STATUS_CUR_BIT_NR_FIELD_LENGTH 3 35 | 36 | #define HUB75S_STATUS_CUR_BUFFER_NR_FIELD_START 31 37 | #define HUB75S_STATUS_CUR_BUFFER_NR_FIELD_LENGTH 1 38 | 39 | #define HUB75S_FRAME_CNTR_ADDR 0x00030008 40 | 41 | #define HUB75S_RGB_DIM_ADDR 0x0003000c 42 | 43 | #define HUB75S_PANEL_INFOS_ADDR 0x0030100 44 | 45 | #define HUB75S_PANEL_INFO_X_SIZE 0x40 46 | 47 | #define HUB75S_PANEL_INFO_X_MISC_ADDR 0x00 48 | #define HUB75S_PANEL_INFO_X_MEM_ADDR_START_PH0_ADDR 0x04 49 | #define HUB75S_PANEL_INFO_X_MEM_ADDR_START_PH1_ADDR 0x08 50 | #define HUB75S_PANEL_INFO_X_MEM_ADDR_COL_MUL_ADDR 0x0c 51 | #define HUB75S_PANEL_INFO_X_MEM_ADDR_ROW_MUL_ADDR 0x10 52 | 53 | #define HUB75S_PI_REG_WR(idx, reg_name, wr_data) (*( (volatile uint32_t *)(0x80000000 | (HUB75S_PANEL_INFOS_ADDR + (HUB75S_PANEL_INFO_X_SIZE * idx) + HUB75S_PANEL_INFO_X_##reg_name##_ADDR) )) = (wr_data)) 54 | 55 | 56 | -------------------------------------------------------------------------------- /tb/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.hex 3 | *.vcd 4 | tb 5 | -------------------------------------------------------------------------------- /tb/Makefile: -------------------------------------------------------------------------------- 1 | 2 | MEM_WORDS = 6144 3 | 4 | CREATE_MIF = ../misc/create_mif.rb 5 | HEX2BIN = ../misc/hex2bin.py 6 | 7 | ROM_FILES = CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol0.bin \ 8 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol1.bin \ 9 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol2.bin \ 10 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol3.bin \ 11 | CubeTop.v_toplevel_core_u_hub75_streamer_gamma_rom_r.bin \ 12 | CubeTop.v_toplevel_core_u_hub75_streamer_gamma_rom_g.bin \ 13 | CubeTop.v_toplevel_core_u_hub75_streamer_gamma_rom_b.bin 14 | 15 | all: tb $(ROM_FILES) 16 | ./tb 17 | 18 | tb: tb.v ../spinal/CubeTop.sim.v 19 | iverilog $^ -o $@ 20 | 21 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol0.bin: CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol0.hex 22 | $(HEX2BIN) < $< > $@ 23 | 24 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol1.bin: CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol1.hex 25 | $(HEX2BIN) < $< > $@ 26 | 27 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol2.bin: CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol2.hex 28 | $(HEX2BIN) < $< > $@ 29 | 30 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol3.bin: CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol3.hex 31 | $(HEX2BIN) < $< > $@ 32 | 33 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol0.hex: ../sw/progmem.bin 34 | $(CREATE_MIF) -f hex -d $(MEM_WORDS) -w 8 -o 0 -i 4 $< > $@ 35 | 36 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol1.hex: ../sw/progmem.bin 37 | $(CREATE_MIF) -f hex -d $(MEM_WORDS) -w 8 -o 1 -i 4 $< > $@ 38 | 39 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol2.hex: ../sw/progmem.bin 40 | $(CREATE_MIF) -f hex -d $(MEM_WORDS) -w 8 -o 2 -i 4 $< > $@ 41 | 42 | CubeTop.v_toplevel_core_u_cpu_u_cpu_ram_ram_symbol3.hex: ../sw/progmem.bin 43 | $(CREATE_MIF) -f hex -d $(MEM_WORDS) -w 8 -o 3 -i 4 $< > $@ 44 | 45 | waves: 46 | gtkwave waves.vcd waves.gtkw & 47 | 48 | CubeTop.v_toplevel_core_u_hub75_streamer_gamma_rom_r.bin \ 49 | CubeTop.v_toplevel_core_u_hub75_streamer_gamma_rom_g.bin \ 50 | CubeTop.v_toplevel_core_u_hub75_streamer_gamma_rom_b.bin : 51 | cp ../spinal/*gamma_rom*.bin . 52 | 53 | clean: 54 | \rm -f *.bin *.hex tb *.vcd 55 | 56 | -------------------------------------------------------------------------------- /tb/tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/1ns 3 | 4 | module tb; 5 | 6 | reg clk; 7 | 8 | initial begin 9 | $dumpfile("waves.vcd"); 10 | $dumpvars; 11 | 12 | clk = 0; 13 | 14 | repeat(80000) 15 | @(posedge clk); 16 | 17 | $finish; 18 | end 19 | 20 | always 21 | #40 clk = !clk; 22 | 23 | wire [3:0] leds; 24 | wire [2:0] hub75_row; 25 | 26 | CubeTop u_dut( 27 | .clk25(clk), 28 | .hub75_clk(hub75_clk), 29 | .hub75_lat(hub75_lat), 30 | .hub75_oe_(hub75_oe_), 31 | .hub75_row(hub75_row), 32 | .hub75_r0(hub75_r0), 33 | .hub75_g0(hub75_g0), 34 | .hub75_b0(hub75_b0), 35 | .hub75_r1(hub75_r1), 36 | .hub75_g1(hub75_g1), 37 | .hub75_b1(hub75_b1), 38 | .leds(leds) 39 | ); 40 | 41 | localparam cols = 64; 42 | 43 | reg [23:0] led_values [0:cols*16-1]; 44 | 45 | reg sclk_d; 46 | reg [2:0] row_d; 47 | 48 | reg [cols-1:0] r0_shift; 49 | reg [cols-1:0] g0_shift; 50 | reg [cols-1:0] b0_shift; 51 | 52 | reg [cols-1:0] r1_shift; 53 | reg [cols-1:0] g1_shift; 54 | reg [cols-1:0] b1_shift; 55 | 56 | reg [cols-1:0] r0_lat; 57 | reg [cols-1:0] g0_lat; 58 | reg [cols-1:0] b0_lat; 59 | 60 | reg [cols-1:0] r1_lat; 61 | reg [cols-1:0] g1_lat; 62 | reg [cols-1:0] b1_lat; 63 | 64 | reg [2:0] bit_nr; 65 | 66 | 67 | integer i; 68 | 69 | initial begin 70 | bit_nr = 0; 71 | end 72 | 73 | always @(posedge clk) begin 74 | if (hub75_clk && !sclk_d) begin 75 | r0_shift <= { r0_shift[cols-2:0], hub75_r0 }; 76 | g0_shift <= { g0_shift[cols-2:0], hub75_g0 }; 77 | b0_shift <= { b0_shift[cols-2:0], hub75_b0 }; 78 | 79 | r1_shift <= { r1_shift[cols-2:0], hub75_r1 }; 80 | g1_shift <= { g1_shift[cols-2:0], hub75_g1 }; 81 | b1_shift <= { b1_shift[cols-2:0], hub75_b1 }; 82 | end 83 | 84 | if (hub75_row < row_d) begin 85 | bit_nr <= 0; 86 | 87 | $writememh("ledvalues.hex", led_values, 0, cols*16-1); 88 | end 89 | 90 | sclk_d <= hub75_clk; 91 | row_d <= hub75_row; 92 | 93 | end 94 | 95 | always @(posedge hub75_lat) begin 96 | r0_lat <= r0_shift; 97 | g0_lat <= g0_shift; 98 | b0_lat <= b0_shift; 99 | 100 | r1_lat <= r1_shift; 101 | g1_lat <= g1_shift; 102 | b1_lat <= b1_shift; 103 | 104 | bit_nr <= bit_nr + 1; 105 | end 106 | 107 | reg [15:0] led_addr; 108 | 109 | always @(negedge hub75_oe_) begin 110 | for(i = 0; i