├── .gitignore ├── .gitmodules ├── README.md ├── blink_basic ├── .gitignore ├── Makefile ├── blink.v └── main.cpp ├── blink_basic_vhdl ├── .gitignore ├── Makefile ├── blink.vhdl └── main.cpp ├── blink_introspect ├── .gitignore ├── Makefile ├── blink.v └── main.cpp ├── blink_vcd ├── .gitignore ├── Makefile ├── blink.v ├── main.cpp └── waves.gtkw ├── compile_yosys.sh ├── cxxrtl ├── .gitignore ├── Makefile ├── build.sh ├── compile_time.txt ├── main.cpp └── proc.ys ├── lib ├── cxxrtl_lib.cpp └── cxxrtl_lib.h ├── misc ├── bin2hex.py ├── create_mif.rb └── hex2bin.py ├── results.txt ├── rpu_vhdl ├── .gitignore ├── VexRiscv_wrapper.v ├── main.cpp └── run.sh ├── run.sh ├── save_restore ├── .gitignore ├── Makefile ├── blink.v ├── restore.cpp └── save.cpp ├── spinal ├── .gitignore ├── ExampleTop.sim.v ├── ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol0.bin ├── ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol1.bin ├── ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol2.bin ├── ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol3.bin ├── Makefile ├── build.sbt ├── project │ └── build.properties └── src │ └── main │ └── scala │ ├── cc │ ├── Apb3CC.scala │ ├── CCApb3Timer.scala │ ├── CCBlocks.scala │ ├── CCGpio.scala │ ├── CpuComplex.scala │ └── Sequence.scala │ └── example │ ├── CpuTop.scala │ └── ExampleTop.scala ├── sw ├── .gitignore ├── Makefile ├── lib.c ├── lib.h ├── main.c ├── progmem.bin ├── reg.h ├── riscv.h ├── sections.lds ├── start.S ├── timer.c ├── timer.h ├── top_defines.h ├── type.h ├── uart.c └── uart.h ├── tb ├── .gitignore ├── Makefile ├── tb.v └── waves.gtkw └── verilator ├── .gitignore ├── Makefile ├── main.cpp └── tb.v /.gitignore: -------------------------------------------------------------------------------- 1 | .*.swp 2 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "spinal/VexRiscv"] 2 | path = spinal/VexRiscv 3 | url = https://github.com/SpinalHDL/VexRiscv.git 4 | [submodule "rpu_vhdl/RPU"] 5 | path = rpu_vhdl/RPU 6 | url = https://github.com/tomverbeure/RPU.git 7 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | **NOTE: These results are still very much in flux as CXXRTL is under heavy development!** 3 | 4 | **Check out the ["CXXRTL, A Yosys Simulation Backend"](https://tomverbeure.github.io/2020/08/08/CXXRTL-the-New-Yosys-Simulation-Backend.html) article on my blog!** 5 | 6 | # Yosys CXXRTL simulation backend (Yosim?) Benchmark 7 | 8 | This project compares the simulation speed of the following open source simulators: 9 | 10 | * Icarus Verilog (11.0) 11 | * Verilator (rev 4.033) 12 | * Yosys CXXRTL (version listed with results.) 13 | 14 | The test design is a VexRiscv CPU with some RAM and some LEDs that are toggling. 15 | 16 | I run the simulation for 1M clock cycles, except on Icarus Verilog where I only do 100K. It's just too slow... 17 | 18 | ## Prepare Verilog 19 | 20 | (This is optional: the generated Verilog and .bin files are part of the repo.) 21 | 22 | ``` 23 | cd sw 24 | make 25 | cd ../spinal 26 | make sim 27 | ``` 28 | 29 | 30 | ## Icarus Verilog 31 | 32 | ``` 33 | cd tb 34 | make tb 35 | time ./tb 36 | ``` 37 | 38 | Result (for 100K clock cycles): 39 | ``` 40 | ... 41 | real 0m26.389s 42 | user 0m26.313s 43 | sys 0m0.061s 44 | ``` 45 | 46 | ## Verilator 47 | 48 | ``` 49 | Verilator - No Waves 50 | Verilator 4.033 devel rev v4.032-73-gdef40fa 51 | 52 | 53 | real 0m0.456s 54 | user 0m0.452s 55 | sys 0m0.004s 56 | 57 | real 0m0.456s 58 | user 0m0.456s 59 | sys 0m0.000s 60 | 61 | real 0m0.456s 62 | user 0m0.456s 63 | sys 0m0.000s 64 | 65 | Verilator - VCD 66 | Verilator 4.033 devel rev v4.032-73-gdef40fa 67 | 68 | 69 | real 0m9.381s 70 | user 0m3.371s 71 | sys 0m2.406s 72 | 73 | real 0m7.503s 74 | user 0m3.484s 75 | sys 0m2.447s 76 | 77 | real 0m7.078s 78 | user 0m3.421s 79 | sys 0m2.521s 80 | ``` 81 | 82 | ## CXXRTL - Max Opt 83 | 84 | ``` 85 | CXXRTL - Max Opt - No Waves 86 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 87 | 88 | 89 | real 0m1.473s 90 | user 0m1.472s 91 | sys 0m0.000s 92 | 93 | real 0m1.470s 94 | user 0m1.469s 95 | sys 0m0.000s 96 | 97 | real 0m1.472s 98 | user 0m1.467s 99 | sys 0m0.004s 100 | 101 | CXXRTL - Max Opt - VCD full (incl Mem) 102 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 103 | 104 | 105 | real 1m34.634s 106 | user 1m32.743s 107 | sys 0m1.759s 108 | 109 | CXXRTL - Max Opt - VCD full (no Mem) 110 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 111 | 112 | 113 | real 0m9.158s 114 | user 0m7.337s 115 | sys 0m1.170s 116 | 117 | CXXRTL - Max Opt - VCD regs only 118 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 119 | 120 | 121 | real 0m8.517s 122 | user 0m6.740s 123 | sys 0m1.146s 124 | ``` 125 | 126 | ## CXXRTL - Max Debug 127 | 128 | ``` 129 | CXXRTL - Max Debug - No Waves 130 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 131 | 132 | 133 | real 0m2.474s 134 | user 0m2.384s 135 | sys 0m0.008s 136 | 137 | real 0m2.382s 138 | user 0m2.381s 139 | sys 0m0.000s 140 | 141 | real 0m2.373s 142 | user 0m2.371s 143 | sys 0m0.000s 144 | 145 | CXXRTL - Max Debug - VCD full (incl Mem) 146 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 147 | 148 | 149 | real 2m3.533s 150 | user 1m58.238s 151 | sys 0m4.685s 152 | 153 | CXXRTL - Max Debug - VCD full (no Mem) 154 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 155 | 156 | 157 | real 0m39.661s 158 | user 0m33.152s 159 | sys 0m5.129s 160 | 161 | CXXRTL - Max Debug - VCD regs only 162 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 163 | 164 | 165 | real 0m10.470s 166 | user 0m7.970s 167 | sys 0m1.659s 168 | ``` 169 | 170 | ## CXXRTL - Compiler Versions 171 | 172 | ``` 173 | CXXRTL - Max Opt - clang9 174 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 175 | 176 | 177 | real 0m1.488s 178 | user 0m1.474s 179 | sys 0m0.012s 180 | 181 | real 0m1.473s 182 | user 0m1.472s 183 | sys 0m0.000s 184 | 185 | real 0m1.461s 186 | user 0m1.457s 187 | sys 0m0.004s 188 | 189 | CXXRTL - Max Opt - clang6 190 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 191 | 192 | 193 | real 0m1.455s 194 | user 0m1.444s 195 | sys 0m0.004s 196 | 197 | real 0m1.450s 198 | user 0m1.445s 199 | sys 0m0.004s 200 | 201 | real 0m1.447s 202 | user 0m1.446s 203 | sys 0m0.000s 204 | 205 | CXXRTL - Max Opt - gcc10.1 206 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 207 | 208 | 209 | real 0m1.736s 210 | user 0m1.729s 211 | sys 0m0.000s 212 | 213 | real 0m1.726s 214 | user 0m1.717s 215 | sys 0m0.008s 216 | 217 | real 0m1.727s 218 | user 0m1.726s 219 | sys 0m0.000s 220 | 221 | CXXRTL - Max Opt - gcc7.5 222 | Yosys 0.9+2406 (git sha1 334ec5fa, clang 6.0.0-1ubuntu2 -fPIC -Os) 223 | 224 | 225 | real 0m1.688s 226 | user 0m1.678s 227 | sys 0m0.004s 228 | 229 | real 0m1.678s 230 | user 0m1.677s 231 | sys 0m0.000s 232 | 233 | real 0m1.674s 234 | user 0m1.673s 235 | sys 0m0.000s 236 | ``` 237 | 238 | ## CXXRTL Recipe 239 | 240 | At the time of writing this, the cxxrtl optimization recipe was as follows: 241 | ``` 242 | read_verilog ../spinal/ExampleTop.sim.v 243 | hierarchy -check -top ExampleTop 244 | write_ilang ExampleTop.sim.ilang 245 | write_cxxrtl ExampleTop.sim.cpp 246 | ``` 247 | 248 | # Verilator Compile Time 249 | 250 | ``` 251 | real 0m3.671s 252 | user 0m3.221s 253 | sys 0m0.138s 254 | ``` 255 | 256 | ## CXXRTL Compile Time 257 | 258 | clang9 not only gives the best simulation results, but it also compiles 259 | must faster than anything else. 260 | 261 | ``` 262 | Compile time example_default_clang9 263 | 264 | real 0m7.321s 265 | user 0m6.976s 266 | sys 0m0.183s 267 | 268 | 269 | Compile time example_Og_clang9 270 | 271 | real 0m9.195s 272 | user 0m9.020s 273 | sys 0m0.142s 274 | 275 | 276 | Compile time example_default_clang6 277 | 278 | real 0m17.038s 279 | user 0m16.562s 280 | sys 0m0.181s 281 | 282 | 283 | Compile time example_default_gcc10 284 | 285 | real 0m32.420s 286 | user 0m31.701s 287 | sys 0m0.497s 288 | 289 | 290 | Compile time example_default_gcc7 291 | 292 | real 0m19.918s 293 | user 0m19.277s 294 | sys 0m0.425s 295 | 296 | ``` 297 | 298 | 299 | 300 | -------------------------------------------------------------------------------- /blink_basic/.gitignore: -------------------------------------------------------------------------------- 1 | blink.cpp 2 | tb 3 | -------------------------------------------------------------------------------- /blink_basic/Makefile: -------------------------------------------------------------------------------- 1 | 2 | YOSYS = yosys 3 | YOSYS_INCLUDE = $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime 4 | 5 | all: tb 6 | ./tb 7 | 8 | tb: main.cpp blink.cpp 9 | clang++ -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@ 10 | 11 | blink.cpp: blink.v 12 | $(YOSYS) -p "read_verilog $<; write_cxxrtl $@" 13 | 14 | 15 | clean: 16 | \rm -f blink.cpp tb 17 | -------------------------------------------------------------------------------- /blink_basic/blink.v: -------------------------------------------------------------------------------- 1 | 2 | module blink(input clk, output led); 3 | 4 | reg [11:0] counter = 16'h0; 5 | 6 | always @(posedge clk) 7 | counter <= counter + 1'b1; 8 | 9 | assign led = counter[7]; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /blink_basic/main.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include "blink.cpp" 4 | 5 | using namespace std; 6 | 7 | int main() 8 | { 9 | cxxrtl_design::p_blink top; 10 | 11 | bool prev_led = 0; 12 | 13 | top.step(); 14 | for(int cycle=0;cycle<1000;++cycle){ 15 | 16 | top.p_clk.set(false); 17 | top.step(); 18 | top.p_clk.set(true); 19 | top.step(); 20 | 21 | bool cur_led = top.p_led.get(); 22 | uint32_t counter = top.p_counter.get(); 23 | 24 | if (cur_led != prev_led){ 25 | cout << "cycle " << cycle << " - led: " << cur_led << ", counter: " << counter << endl; 26 | } 27 | prev_led = cur_led; 28 | } 29 | } 30 | 31 | -------------------------------------------------------------------------------- /blink_basic_vhdl/.gitignore: -------------------------------------------------------------------------------- 1 | blink.cpp 2 | tb 3 | *.cf 4 | -------------------------------------------------------------------------------- /blink_basic_vhdl/Makefile: -------------------------------------------------------------------------------- 1 | 2 | YOSYS = yosys 3 | YOSYS_INCLUDE = $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime 4 | GHDL = /opt/ghdl/bin/ghdl 5 | 6 | all: tb 7 | ./tb 8 | 9 | tb: main.cpp blink.cpp 10 | clang++ -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@ 11 | 12 | blink.cpp: blink.vhdl 13 | $(GHDL) analyse $< 14 | $(YOSYS) -m ghdl -p "ghdl blink; write_cxxrtl $@" 15 | 16 | clean: 17 | \rm -f blink.cpp tb *.cf 18 | -------------------------------------------------------------------------------- /blink_basic_vhdl/blink.vhdl: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity blink is 6 | port ( 7 | clk : in std_logic; 8 | led : out std_logic 9 | ); 10 | end blink; 11 | 12 | architecture RTL of blink is 13 | signal counter : unsigned(11 downto 0) := "000000000000"; 14 | begin 15 | 16 | process(clk) begin 17 | if rising_edge(clk) then 18 | counter <= counter + 1; 19 | end if; 20 | end process; 21 | 22 | led <= counter(7); 23 | 24 | end RTL; 25 | -------------------------------------------------------------------------------- /blink_basic_vhdl/main.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include "blink.cpp" 4 | 5 | using namespace std; 6 | 7 | int main() 8 | { 9 | cxxrtl_design::p_blink top; 10 | 11 | bool prev_led = 0; 12 | 13 | top.step(); 14 | for(int cycle=0;cycle<1000;++cycle){ 15 | 16 | top.p_clk.set(false); 17 | top.step(); 18 | top.p_clk.set(true); 19 | top.step(); 20 | 21 | bool cur_led = top.p_led.get(); 22 | uint32_t counter = top.p_counter.get(); 23 | 24 | if (cur_led != prev_led){ 25 | cout << "cycle " << cycle << " - led: " << cur_led << ", counter: " << counter << endl; 26 | } 27 | prev_led = cur_led; 28 | } 29 | } 30 | 31 | -------------------------------------------------------------------------------- /blink_introspect/.gitignore: -------------------------------------------------------------------------------- 1 | blink.cpp 2 | tb 3 | *.vcd 4 | -------------------------------------------------------------------------------- /blink_introspect/Makefile: -------------------------------------------------------------------------------- 1 | 2 | YOSYS = yosys 3 | YOSYS_INCLUDE = $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime 4 | 5 | all: tb 6 | ./tb 7 | 8 | tb: main.cpp blink.cpp 9 | clang++ -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@ 10 | 11 | blink.cpp: blink.v 12 | $(YOSYS) -p "read_verilog $<; hierarchy -top top; write_cxxrtl -Og $@" 13 | 14 | 15 | clean: 16 | \rm -f blink.cpp tb *.vcd 17 | -------------------------------------------------------------------------------- /blink_introspect/blink.v: -------------------------------------------------------------------------------- 1 | 2 | module blink(input clk, output led); 3 | 4 | reg [63:0] counter = 0; 5 | reg [43:11] non_zero_lsb = 1; 6 | 7 | always @(posedge clk) 8 | counter <= counter + 1'b1; 9 | 10 | assign led = counter[7]; 11 | 12 | 13 | endmodule 14 | 15 | module top(input clk, output led); 16 | 17 | reg [39:0] mem[10:0]; 18 | 19 | initial begin 20 | mem[0] = 0; 21 | mem[4] = 3; 22 | mem[7] = (1<<33); 23 | end 24 | 25 | blink u_blink( 26 | .clk(clk), 27 | .led(led) 28 | ); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /blink_introspect/main.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | 6 | #include "blink.cpp" 7 | 8 | using namespace std; 9 | using std::setw; 10 | 11 | 12 | void dump_all_items(cxxrtl::debug_items &items) 13 | { 14 | cout << "All items:" << endl; 15 | for(auto &it : items.table) 16 | for(auto &part: it.second) 17 | cout << setw(24) << it.first 18 | << " : type = " << part.type 19 | << " ; width = " << setw(4) << part.width 20 | << " ; depth = " << setw(6) << part.depth 21 | << " ; lsb_at = " << setw(3) << part.lsb_at 22 | << " ; zero_at = " << setw(3) << part.zero_at << endl; 23 | cout << endl; 24 | } 25 | 26 | void dump_item_value(cxxrtl::debug_items &items, std::string path) 27 | { 28 | cxxrtl::debug_item item = items.at(path)[0]; 29 | 30 | // Number of chunks per value 31 | const size_t nr_chunks = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8); 32 | 33 | cout << "\"" << path << "\":" << endl; 34 | 35 | for (size_t index = 0; index < item.depth; index++) { 36 | if (item.depth > 1) 37 | cout << "location[" << index << "] : "; 38 | 39 | for(size_t chunk_nr = 0; chunk_nr < nr_chunks; ++chunk_nr){ 40 | cout << item.curr[nr_chunks * index + chunk_nr]; 41 | cout << (chunk_nr == nr_chunks-1 ? "\n" : ", "); 42 | } 43 | } 44 | } 45 | 46 | int main() 47 | { 48 | cxxrtl_design::p_top top; 49 | 50 | cxxrtl::debug_items all_debug_items; 51 | 52 | top.debug_info(&all_debug_items, nullptr, ""); 53 | 54 | dump_all_items(all_debug_items); 55 | 56 | bool prev_led = false; 57 | 58 | top.step(); 59 | 60 | for(int steps=0;steps<1000;++steps){ 61 | 62 | top.p_clk.set(false); 63 | top.step(); 64 | 65 | top.p_clk.set(true); 66 | top.step(); 67 | 68 | bool cur_led = top.p_led.get(); 69 | 70 | if (cur_led != prev_led) 71 | cout << "cycle " << steps << " - led: " << cur_led << endl; 72 | 73 | if (steps == 200){ 74 | dump_item_value(all_debug_items, "u_blink counter"); 75 | dump_item_value(all_debug_items, "mem"); 76 | } 77 | 78 | 79 | prev_led = cur_led; 80 | } 81 | } 82 | 83 | -------------------------------------------------------------------------------- /blink_vcd/.gitignore: -------------------------------------------------------------------------------- 1 | blink.cpp 2 | tb 3 | *.vcd 4 | tb.dSYM/* 5 | -------------------------------------------------------------------------------- /blink_vcd/Makefile: -------------------------------------------------------------------------------- 1 | 2 | YOSYS = yosys 3 | YOSYS_INCLUDE = $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime 4 | 5 | all: waves 6 | ./tb 7 | 8 | waves: sim 9 | gtkwave waves.vcd waves.gtkw 10 | 11 | sim: tb 12 | ./tb 13 | 14 | tb: main.cpp blink.cpp 15 | clang++ -g -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@ 16 | 17 | blink.cpp: blink.v 18 | $(YOSYS) -p "read_verilog $<; write_cxxrtl $@" 19 | 20 | 21 | clean: 22 | \rm -f blink.cpp tb *.vcd 23 | -------------------------------------------------------------------------------- /blink_vcd/blink.v: -------------------------------------------------------------------------------- 1 | 2 | module blink(input clk, output led); 3 | 4 | reg [7:0] counter = 0; 5 | 6 | always @(posedge clk) 7 | counter <= counter + 1'b1; 8 | 9 | assign led = counter[7]; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /blink_vcd/main.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | 5 | #include 6 | 7 | #include "blink.cpp" 8 | 9 | using namespace std; 10 | 11 | int main() 12 | { 13 | cxxrtl_design::p_blink top; 14 | 15 | // debug_items maps the hierarchical names of signals and memories in the design 16 | // to a cxxrtl_object (a value, a wire, or a memory) 17 | cxxrtl::debug_items all_debug_items; 18 | 19 | // Load the debug items of the top down the whole design hierarchy 20 | top.debug_info(&all_debug_items, nullptr, ""); 21 | 22 | // vcd_writer is the CXXRTL object that's responsible of creating a string with 23 | // the VCD file contents. 24 | cxxrtl::vcd_writer vcd; 25 | vcd.timescale(1, "us"); 26 | 27 | // Here we tell the vcd writer to dump all the signals of the design, except for the 28 | // memories, to the VCD file. 29 | // 30 | // It's not necessary to load all debug objects to the VCD. There is, for example, 31 | // a vcd.add(, )) method which allows creating your custom filter to decide 32 | // what to add and what not. 33 | vcd.add_without_memories(all_debug_items); 34 | 35 | std::ofstream waves("waves.vcd"); 36 | 37 | bool prev_led = 0; 38 | 39 | top.step(); 40 | 41 | // We need to manually tell the VCD writer when sample and write out the traced items. 42 | // This is only a slight inconvenience and allows for complete flexibilty. 43 | // E.g. you could only start waveform tracing when an internal signal has reached some specific 44 | // value etc. 45 | vcd.sample(0); 46 | 47 | for(int steps=0;steps<1000;++steps){ 48 | 49 | top.p_clk.set(false); 50 | top.step(); 51 | vcd.sample(steps*2 + 0); 52 | 53 | top.p_clk.set(true); 54 | top.step(); 55 | vcd.sample(steps*2 + 1); 56 | 57 | bool cur_led = top.p_led.get(); 58 | 59 | if (cur_led != prev_led) 60 | cout << "cycle " << steps << " - led: " << cur_led << endl; 61 | 62 | prev_led = cur_led; 63 | 64 | waves << vcd.buffer; 65 | vcd.buffer.clear(); 66 | } 67 | } 68 | 69 | -------------------------------------------------------------------------------- /blink_vcd/waves.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI 3 | [*] Sun Aug 9 21:01:28 2020 4 | [*] 5 | [dumpfile] "/Users/tom/projects/cxxrtl_eval/blink_vcd/waves.vcd" 6 | [dumpfile_mtime] "Sun Aug 9 21:00:40 2020" 7 | [dumpfile_size] 29042 8 | [savefile] "/Users/tom/projects/cxxrtl_eval/blink_vcd/waves.gtkw" 9 | [timestart] 249 10 | [size] 1000 350 11 | [pos] 212 20 12 | *-2.000000 255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [sst_width] 193 14 | [signals_width] 133 15 | [sst_expanded] 1 16 | [sst_vpaned_height] 80 17 | @28 18 | clk 19 | @22 20 | counter[7:0] 21 | @28 22 | led 23 | [pattern_trace] 1 24 | [pattern_trace] 0 25 | -------------------------------------------------------------------------------- /compile_yosys.sh: -------------------------------------------------------------------------------- 1 | 2 | # Compile different Yosys versions for different versions of CXXRTL 3 | 4 | cd ~/tools/yosys 5 | 6 | #git checkout bf0f96b847a9738df10e2a549a53bddfa0d1346a 7 | #make clean 8 | #make config-clang 9 | #echo "ENABLE_DEBUG := 1" >> Makefile.conf 10 | #make -j $(nproc) 11 | #cp yosys yosys-20200419 12 | # 13 | #git checkout 95c74b319b36f8cb950196c3e1d10c945629c1f5 14 | #make clean 15 | #make config-clang 16 | #echo "ENABLE_DEBUG := 1" >> Makefile.conf 17 | #make -j $(nproc) 18 | #cp yosys yosys-20200422a 19 | # 20 | #git checkout cf14e186eb6c89696cd1db4b36697a4e80b6884a 21 | #make clean 22 | #make config-clang 23 | #echo "ENABLE_DEBUG := 1" >> Makefile.conf 24 | #make -j $(nproc) 25 | #cp yosys yosys-20200422b 26 | # 27 | #git checkout a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4 28 | #make clean 29 | #make config-clang 30 | #echo "ENABLE_DEBUG := 1" >> Makefile.conf 31 | #make -j $(nproc) 32 | #cp yosys yosys-20200526 33 | # 34 | #git checkout 83f84afc0b617fe78fb7cfa31fb9d1cd202e22f2 35 | #make clean 36 | #make config-clang 37 | #echo "ENABLE_DEBUG := 1" >> Makefile.conf 38 | #make -j $(nproc) 39 | #cp yosys yosys-20200608 40 | 41 | git checkout 971a7651555651e569311c6cbe039f0eee8cde93 42 | make clean 43 | make config-clang 44 | echo "ENABLE_DEBUG := 1" >> Makefile.conf 45 | make -j $(nproc) 46 | cp yosys yosys-20200613 47 | -------------------------------------------------------------------------------- /cxxrtl/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | ExampleTop.*.cpp 3 | *.txt 4 | example 5 | example*clang* 6 | example*gcc* 7 | *.ilang 8 | yosys 9 | t 10 | *.vcd 11 | *.o 12 | *.log 13 | checkpoint.val 14 | -------------------------------------------------------------------------------- /cxxrtl/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | YOSYS = yosys 4 | YOSYS_INCLUDE = $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime 5 | 6 | SRC = main.cpp 7 | OBJ = cxxrtl_lib.o 8 | VERILOG = ../spinal/ExampleTop.sim.v 9 | MEM_FILES = ../spinal/ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol0.bin \ 10 | ../spinal/ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol1.bin \ 11 | ../spinal/ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol2.bin \ 12 | ../spinal/ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol3.bin 13 | 14 | CLANG6 = clang++-6.0 15 | #CLANG9 = clang++-9 16 | CLANG9 = clang++ 17 | GCC7 = g++ 18 | GCC10 = g++-10 19 | 20 | CLANG_INLINE = -mllvm -inline-threshold=10000 21 | 22 | YOSYS_PREPROC = "read_verilog $(VERILOG); hierarchy -check -top ExampleTop" 23 | YOSYS_RECIPE = "" 24 | 25 | all: compile 26 | 27 | .PHONY: compile 28 | compile: \ 29 | compile_time.txt \ 30 | example_default_clang9 \ 31 | example_Og_clang9 \ 32 | example_default_clang6 \ 33 | example_default_gcc10 \ 34 | example_default_gcc7 35 | # example_default_clang6_inline \ 36 | # example_default_clang9_inline \ 37 | # example_Og_clang9_inline 38 | 39 | .PHONY: compile_time.txt 40 | compile_time.txt: 41 | rm -f $@ 42 | touch $@ 43 | 44 | example_default_clang9: ExampleTop.sim.default.cpp $(SRC) $(OBJ) 45 | echo >> compile_time.txt 46 | echo "Compile time $@" >> compile_time.txt 47 | (time $(CLANG9) -g -O3 -std=c++14 -DEXAMPLE_TOP=\"$<\" -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 48 | echo >> compile_time.txt 49 | 50 | example_default_clang6: ExampleTop.sim.default.cpp $(SRC) $(OBJ) 51 | echo >> compile_time.txt 52 | echo "Compile time $@" >> compile_time.txt 53 | (time $(CLANG6) -g -O3 -std=c++14 -DEXAMPLE_TOP=\"$<\" -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 54 | echo >> compile_time.txt 55 | 56 | example_default_clang9_inline: ExampleTop.sim.default.cpp $(SRC) $(OBJ) 57 | echo >> compile_time.txt 58 | echo "Compile time $@" >> compile_time.txt 59 | (time $(CLANG9) -g -O3 $(CLANG_INLINE) -std=c++14 -DEXAMPLE_TOP=\"$<\" -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 60 | echo >> compile_time.txt 61 | 62 | example_default_clang6_inline: ExampleTop.sim.default.cpp $(SRC) $(OBJ) 63 | echo >> compile_time.txt 64 | echo "Compile time $@" >> compile_time.txt 65 | (time $(CLANG6) -g -O3 $(CLANG_INLINE) -std=c++14 -DEXAMPLE_TOP=\"$<\" -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 66 | echo >> compile_time.txt 67 | 68 | example_Og_clang9: ExampleTop.sim.Og.cpp $(SRC) $(OBJ) 69 | echo >> compile_time.txt 70 | echo "Compile time $@" >> compile_time.txt 71 | (time $(CLANG9) -g -O3 -std=c++14 -DEXAMPLE_TOP=\"$<\" -DSPY_UART_TX -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 72 | echo >> compile_time.txt 73 | 74 | example_Og_clang9_inline: ExampleTop.sim.Og.cpp $(SRC) $(OBJ) 75 | echo >> compile_time.txt 76 | echo "Compile time $@" >> compile_time.txt 77 | (time $(CLANG9) -g -O3 $(CLANG_INLINE) -std=c++14 -DEXAMPLE_TOP=\"$<\" -DSPY_UART_TX -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 78 | echo >> compile_time.txt 79 | 80 | example_default_gcc10: ExampleTop.sim.default.cpp $(SRC) $(OBJ) 81 | echo >> compile_time.txt 82 | echo "Compile time $@" >> compile_time.txt 83 | (time $(GCC10) -g -O3 -std=c++14 -DEXAMPLE_TOP=\"$<\" -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 84 | echo >> compile_time.txt 85 | 86 | example_default_gcc7: ExampleTop.sim.Og.cpp $(SRC) $(OBJ) 87 | echo >> compile_time.txt 88 | echo "Compile time $@" >> compile_time.txt 89 | (time $(GCC7) -g -O3 -std=c++14 -DEXAMPLE_TOP=\"$<\" -DSPY_UART_TX -I $(YOSYS_INCLUDE) $(SRC) -I../lib $(OBJ) -o $@) 2>> compile_time.txt 90 | echo >> compile_time.txt 91 | 92 | 93 | .PHONY: ExampleTop.sim.default.cpp 94 | ExampleTop.sim.default.cpp: 95 | cp $(MEM_FILES) . 96 | $(YOSYS) -l yosys.log -p $(YOSYS_PREPROC) -p $(YOSYS_RECIPE) -p "write_cxxrtl $@" 97 | 98 | .PHONY: ExampleTop.sim.Og.cpp 99 | ExampleTop.sim.Og.cpp: 100 | cp $(MEM_FILES) . 101 | $(YOSYS) -l yosys.log -p $(YOSYS_PREPROC) -p "write_cxxrtl -Og $@" 102 | 103 | cxxrtl_lib.o: ../lib/cxxrtl_lib.cpp 104 | g++ -c --std=c++14 -I $(YOSYS_INCLUDE) $< 105 | 106 | clean: 107 | \rm -fr *.bin *.txt *.sim.* example_*_clang* example_*_gcc* example *.vcd 108 | -------------------------------------------------------------------------------- /cxxrtl/build.sh: -------------------------------------------------------------------------------- 1 | yosys proc.ys 2 | clang++ -g -O3 -std=c++14 -DEXAMPLE_TOP=\"ExampleTop.sim.cpp\" -I `yosys-config --datdir`/include/backends/cxxrtl/runtime/ main.cpp -o example 3 | 4 | -------------------------------------------------------------------------------- /cxxrtl/compile_time.txt: -------------------------------------------------------------------------------- 1 | 2 | Compile time example_default_clang9 3 | /bin/sh: 1: time: not found 4 | 5 | Compile time example_default_clang9 6 | /bin/sh: 1: time: not found 7 | -------------------------------------------------------------------------------- /cxxrtl/main.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | 6 | #include 7 | 8 | #include 9 | 10 | #include EXAMPLE_TOP 11 | 12 | using namespace std; 13 | 14 | int main(int argc, char **argv) 15 | { 16 | char *filename; 17 | int dump_level = 0; 18 | 19 | // 20 | // debug level: 21 | // 0 -> No dumping, no save/restore 22 | // 1 -> dump everything 23 | // 2 -> dump everything except memories 24 | // 3 -> dump custom (only wires) 25 | // 4 -> save to checkpoint 26 | // 5 -> restore from checkpoint 27 | 28 | if (argc >= 2){ 29 | dump_level = atoi(argv[1]); 30 | } 31 | 32 | if (argc >= 3){ 33 | filename = argv[2]; 34 | } 35 | 36 | cxxrtl_design::p_ExampleTop top; 37 | cxxrtl::debug_items all_debug_items; 38 | top.debug_info(&all_debug_items, nullptr, ""); 39 | cxxrtl::vcd_writer vcd; 40 | std::ofstream waves; 41 | 42 | if (dump_level >=1 && dump_level <= 3){ 43 | vcd.timescale(1, "us"); 44 | if (dump_level == 1) 45 | vcd.add(all_debug_items); 46 | else if (dump_level == 2) 47 | vcd.add_without_memories(all_debug_items); 48 | else if (dump_level == 3) 49 | vcd.add(all_debug_items, [](const std::string &, const debug_item &item) { 50 | return item.type == debug_item::WIRE; 51 | }); 52 | waves.open(filename); 53 | } 54 | 55 | bool prev_led_red, prev_led_green, prev_led_blue; 56 | 57 | if (dump_level == 5){ 58 | cout << "Restoring from checkpoint..." << endl; 59 | std::ifstream checkpoint("checkpoint.val"); 60 | restore_state(all_debug_items, checkpoint); 61 | cout << "Restore done..." << endl; 62 | dump_all_items(all_debug_items); 63 | } 64 | 65 | top.p_osc__clk__in.set(true); 66 | top.step(); 67 | 68 | if (dump_level >=1 && dump_level <= 3) 69 | vcd.sample(0); 70 | 71 | cxxrtl::debug_item psel = all_debug_items.at("cpu_u_cpu u_uart io_apb_PSEL")[0]; 72 | cxxrtl::debug_item penable = all_debug_items.at("cpu_u_cpu u_uart io_apb_PENABLE")[0]; 73 | cxxrtl::debug_item pwrite = all_debug_items.at("cpu_u_cpu u_uart io_apb_PWRITE")[0]; 74 | cxxrtl::debug_item pwdata = all_debug_items.at("cpu_u_cpu u_uart io_apb_PWDATA")[0]; 75 | cxxrtl::debug_item paddr = all_debug_items.at("cpu_u_cpu u_uart io_apb_PADDR")[0]; 76 | 77 | int led_red_cntr = 0; 78 | 79 | for(int i=0;i<1000000;++i){ 80 | top.p_osc__clk__in.set(false); 81 | top.step(); 82 | 83 | if (dump_level >=1 && dump_level <= 3) 84 | vcd.sample(i*2 + 0); 85 | 86 | top.p_osc__clk__in.set(true); 87 | top.step(); 88 | 89 | if (debug_item_get_value32(psel) && 90 | debug_item_get_value32(penable) && 91 | debug_item_get_value32(pwrite) && 92 | debug_item_get_value32(paddr) == 0 93 | ){ 94 | // APB write to UART RXTX register 95 | cout << "UART TX: " << (char)debug_item_get_value32(pwdata) << endl; 96 | } 97 | 98 | if (dump_level == 4 && i==10000){ 99 | cout << "Saving checkpoint..." << endl; 100 | std::ofstream checkpoint("checkpoint.val"); 101 | save_state(all_debug_items, checkpoint); 102 | exit(0); 103 | } 104 | 105 | if (dump_level >= 1 && dump_level <= 3) 106 | vcd.sample(i*2 + 1); 107 | 108 | bool cur_led_red = top.p_led__red.get(); 109 | bool cur_led_green = top.p_led__green.get(); 110 | bool cur_led_blue = top.p_led__blue.get(); 111 | 112 | if (cur_led_red != prev_led_red){ 113 | cout << "led_red: " << cur_led_red << " " << led_red_cntr << endl; 114 | if (cur_led_red) 115 | ++led_red_cntr; 116 | } 117 | 118 | if (cur_led_green != prev_led_green){ 119 | cout << "led_green: " << cur_led_green << endl; 120 | } 121 | 122 | if (cur_led_blue != prev_led_blue){ 123 | cout << "led_blue: " << cur_led_blue << endl; 124 | } 125 | 126 | prev_led_red = cur_led_red; 127 | prev_led_green = cur_led_green; 128 | prev_led_blue = cur_led_blue; 129 | 130 | if (dump_level >= 1 && dump_level <= 3){ 131 | waves << vcd.buffer; 132 | vcd.buffer.clear(); 133 | } 134 | } 135 | } 136 | 137 | -------------------------------------------------------------------------------- /cxxrtl/proc.ys: -------------------------------------------------------------------------------- 1 | read_verilog ../spinal/ExampleTop.sim.v 2 | hierarchy -check -top ExampleTop 3 | write_ilang ExampleTop.sim.ilang 4 | write_cxxrtl ExampleTop.sim.cpp 5 | 6 | -------------------------------------------------------------------------------- /lib/cxxrtl_lib.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | using namespace std; 8 | using std::setw; 9 | 10 | void save_state(cxxrtl::debug_items &items, std::ofstream &save_file, uint32_t types) 11 | { 12 | save_file << items.table.size() << endl; 13 | for(auto &it : items.table){ 14 | save_file << it.first << endl; 15 | for(auto &part: it.second){ 16 | if (part.type & types){ 17 | uint32_t *mem_data = part.curr; 18 | for(int a=0;a> size; 33 | 34 | for(int i=0;i &item_parts = items.table[name]; 42 | for(auto &part: item_parts){ 43 | if (part.type & types){ 44 | uint32_t *mem_data = part.curr; 45 | for(int a=0;a> value; 48 | *mem_data = value; 49 | ++mem_data; 50 | 51 | //cout << value << endl; 52 | } 53 | } 54 | } 55 | } 56 | } 57 | } 58 | 59 | void dump_all_items(cxxrtl::debug_items &items) 60 | { 61 | cout << "All items:" << endl; 62 | for(auto &it : items.table) 63 | for(auto &part: it.second) 64 | cout << setw(24) << it.first 65 | << " : type = " << part.type 66 | << " ; width = " << setw(4) << part.width 67 | << " ; depth = " << setw(6) << part.depth 68 | << " ; lsb_at = " << setw(3) << part.lsb_at 69 | << " ; zero_at = " << setw(3) << part.zero_at 70 | << " ; value = " << *it.second.begin()->curr 71 | << endl; 72 | cout << endl; 73 | } 74 | 75 | uint32_t debug_item_get_value32(cxxrtl::debug_item &item) 76 | { 77 | //return *item.begin()->curr; 78 | return *item.curr; 79 | } 80 | 81 | 82 | -------------------------------------------------------------------------------- /lib/cxxrtl_lib.h: -------------------------------------------------------------------------------- 1 | #ifndef CXXRTL_LIB_H 2 | #define CXXRTL_LIB_H 3 | 4 | #include 5 | 6 | void save_state(cxxrtl::debug_items &items, std::ofstream &save_file, uint32_t types = (CXXRTL_WIRE | CXXRTL_MEMORY)); 7 | void restore_state(cxxrtl::debug_items &items, std::ifstream &restore_file, uint32_t types = (CXXRTL_WIRE | CXXRTL_MEMORY)); 8 | void dump_all_items(cxxrtl::debug_items &items); 9 | uint32_t debug_item_get_value32(cxxrtl::debug_item &item); 10 | 11 | #endif 12 | -------------------------------------------------------------------------------- /misc/bin2hex.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import sys 4 | 5 | for line in sys.stdin: 6 | print( "{0:02x}".format(int(line.strip(),2)) ) 7 | -------------------------------------------------------------------------------- /misc/create_mif.rb: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env ruby 2 | 3 | require 'optparse' 4 | require 'pp' 5 | 6 | options = {} 7 | OptionParser.new do |opts| 8 | opts.banner = "Usage: create_mif.rb [options]" 9 | opts.on("-v", "--[no-]verbose", "Run verbosely") do |v| 10 | options[:verbose] = v 11 | end 12 | 13 | opts.on("-fFORMAT", "--format=FORMAT", "Specify output format ('mif', 'hex', 'coe', 'mem')") do |f| 14 | options[:format] = f 15 | end 16 | 17 | opts.on("-dDEPTH", "--depth=DEPTH", Integer, "Memory depth") do |d| 18 | options[:depth] = d 19 | end 20 | 21 | opts.on("-wWIDTH", "--width=WIDTH", Integer, "Memory width (bits)") do |w| 22 | options[:width] = w 23 | end 24 | 25 | opts.on("-oOFFSET", "--offset=OFFSET", Integer, "First byte to use of the binary input file (default = 0)") do |o| 26 | options[:offset] = o 27 | end 28 | 29 | opts.on("-iINCREMENT", "--increment=INCREMENT", Integer, "How many bytes to the next byte (default = 1)") do |i| 30 | options[:increment] = i 31 | end 32 | 33 | end.parse! 34 | 35 | start_offset = options[:offset] || 0 36 | increment = options[:increment] || 1 37 | 38 | bin = File.open(ARGV[0], "rb").read 39 | bytes = bin.unpack("C*")[start_offset..-1].each_slice(increment).collect{ |a| a.first } 40 | 41 | depth = options[:depth] || bytes.size 42 | width = options[:width] || 8 43 | format = options[:format] || "mif" 44 | 45 | bytes_per_word = (width+7)>>3 46 | nr_addr_bits = Math.log2(depth).ceil 47 | 48 | if options[:verbose] 49 | STDERR.puts "output format : #{format}" 50 | STDERR.puts "depth : #{depth}" 51 | STDERR.puts "width : #{width}" 52 | STDERR.puts "bytes per word: #{bytes_per_word}" 53 | STDERR.puts "start offset : #{start_offset}" 54 | STDERR.puts "increment : #{increment}" 55 | end 56 | 57 | if format == "mif" 58 | puts %{-- Created by create_mif.rb 59 | DEPTH = #{depth}; 60 | WIDTH = #{width}; 61 | ADDRESS_RADIX = HEX; 62 | DATA_RADIX = HEX; 63 | CONTENT 64 | BEGIN 65 | } 66 | 67 | addr_fmt_string = "%%0%dx" % ((nr_addr_bits+3)>>2) 68 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 69 | 70 | fmt_string = "#{addr_fmt_string}: #{data_fmt_string};" 71 | 72 | words = bytes.each_slice(bytes_per_word) 73 | words.each_with_index do |w, addr| 74 | value = 0 75 | w.reverse.collect { |b| value = value * 256 + b } 76 | puts fmt_string % [addr, value] 77 | end 78 | 79 | if words.size < depth 80 | puts "[#{addr_fmt_string}..#{addr_fmt_string}]: #{data_fmt_string};" % [ words.size, depth-1, 0 ] 81 | end 82 | 83 | puts "END;" 84 | puts 85 | 86 | elsif format == "coe" 87 | puts %{; Created by create_mif.rb 88 | ; block memory configuration: 89 | ; DEPTH = #{depth}; 90 | ; WIDTH = #{width}; 91 | memory_initialization_radix=16; 92 | memory_initialization_vector=} 93 | 94 | words = bytes.each_slice(bytes_per_word).collect do |w| 95 | value = 0 96 | w.reverse.collect { |b| value = value * 256 + b } 97 | value 98 | end 99 | 100 | (depth - words.size).times { words << 0 } 101 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 102 | str = words.collect{ |w| data_fmt_string % w }.join(",\n") + ";" 103 | 104 | puts str 105 | 106 | elsif format == "hex" 107 | 108 | words = bytes.each_slice(bytes_per_word).collect do |w| 109 | value = 0 110 | w.reverse.collect { |b| value = value * 256 + b } 111 | value 112 | end 113 | 114 | (depth - words.size).times { words << 0 } 115 | 116 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 117 | str = words.collect{ |w| data_fmt_string % w }.join("\n") 118 | 119 | puts str 120 | 121 | elsif format == "mem" 122 | 123 | words = bytes.each_slice(bytes_per_word).collect do |w| 124 | value = 0 125 | w.reverse.collect { |b| value = value * 256 + b } 126 | value 127 | end 128 | 129 | (depth - words.size).times { words << 0 } 130 | 131 | data_fmt_string = "%%0%dx" % (bytes_per_word * 2) 132 | str = words.collect{ |w| data_fmt_string % w }.join("\n") 133 | 134 | puts "@00000000" 135 | puts str 136 | 137 | else 138 | Kernel.abort("Unknown format '#{format}'! Aborting...") 139 | end 140 | -------------------------------------------------------------------------------- /misc/hex2bin.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import sys 4 | 5 | for line in sys.stdin: 6 | print( "{0:08b}".format(int(line.strip(),16)) ) 7 | -------------------------------------------------------------------------------- /results.txt: -------------------------------------------------------------------------------- 1 | ## Verilator 2 | 3 | ``` 4 | Verilator - No Waves 5 | Verilator 4.033 devel rev v4.032-73-gdef40fa 6 | 7 | 8 | real 0m0.450s 9 | user 0m0.450s 10 | sys 0m0.000s 11 | 12 | real 0m0.449s 13 | user 0m0.449s 14 | sys 0m0.000s 15 | 16 | real 0m0.449s 17 | user 0m0.450s 18 | sys 0m0.000s 19 | 20 | Verilator - VCD 21 | Verilator 4.033 devel rev v4.032-73-gdef40fa 22 | 23 | 24 | real 0m6.807s 25 | user 0m3.093s 26 | sys 0m2.040s 27 | 28 | real 0m6.761s 29 | user 0m3.038s 30 | sys 0m2.229s 31 | 32 | real 0m7.105s 33 | user 0m3.082s 34 | sys 0m2.224s 35 | ``` 36 | 37 | ## CXXRTL - Max Opt 38 | 39 | ``` 40 | CXXRTL - Max Opt - No Waves 41 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 42 | 43 | 44 | real 0m1.465s 45 | user 0m1.452s 46 | sys 0m0.004s 47 | 48 | real 0m1.451s 49 | user 0m1.443s 50 | sys 0m0.008s 51 | 52 | real 0m1.448s 53 | user 0m1.448s 54 | sys 0m0.000s 55 | 56 | CXXRTL - Max Opt - VCD full (incl Mem) 57 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 58 | 59 | 60 | real 1m33.319s 61 | user 1m31.562s 62 | sys 0m1.152s 63 | 64 | CXXRTL - Max Opt - VCD full (no Mem) 65 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 66 | 67 | 68 | real 0m7.965s 69 | user 0m6.714s 70 | sys 0m0.973s 71 | 72 | CXXRTL - Max Opt - VCD regs only 73 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 74 | 75 | 76 | real 0m8.222s 77 | user 0m6.291s 78 | sys 0m0.940s 79 | ``` 80 | 81 | ## CXXRTL - Max Debug 82 | 83 | ``` 84 | CXXRTL - Max Debug - No Waves 85 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 86 | 87 | 88 | real 0m2.465s 89 | user 0m2.423s 90 | sys 0m0.008s 91 | 92 | real 0m2.407s 93 | user 0m2.403s 94 | sys 0m0.004s 95 | 96 | real 0m2.406s 97 | user 0m2.406s 98 | sys 0m0.000s 99 | 100 | CXXRTL - Max Debug - VCD full (incl Mem) 101 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 102 | 103 | 104 | real 2m1.431s 105 | user 1m56.116s 106 | sys 0m4.931s 107 | 108 | CXXRTL - Max Debug - VCD full (no Mem) 109 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 110 | 111 | 112 | real 0m36.630s 113 | user 0m31.641s 114 | sys 0m3.925s 115 | 116 | CXXRTL - Max Debug - VCD regs only 117 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 118 | 119 | 120 | real 0m8.580s 121 | user 0m7.327s 122 | sys 0m0.908s 123 | ``` 124 | 125 | ## CXXRTL - Compiler Versions 126 | 127 | ``` 128 | 129 | CXXRTL - Max Opt - clang9 130 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 131 | 132 | 133 | real 0m1.454s 134 | user 0m1.449s 135 | sys 0m0.004s 136 | 137 | real 0m1.451s 138 | user 0m1.451s 139 | sys 0m0.000s 140 | 141 | real 0m1.448s 142 | user 0m1.444s 143 | sys 0m0.004s 144 | 145 | CXXRTL - Max Opt - clang6 146 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 147 | 148 | 149 | real 0m1.398s 150 | user 0m1.388s 151 | sys 0m0.008s 152 | 153 | real 0m1.390s 154 | user 0m1.390s 155 | sys 0m0.000s 156 | 157 | real 0m1.388s 158 | user 0m1.388s 159 | sys 0m0.000s 160 | 161 | CXXRTL - Max Opt - gcc10.1 162 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 163 | 164 | 165 | real 0m1.594s 166 | user 0m1.583s 167 | sys 0m0.004s 168 | 169 | real 0m1.582s 170 | user 0m1.583s 171 | sys 0m0.000s 172 | 173 | real 0m1.579s 174 | user 0m1.575s 175 | sys 0m0.004s 176 | 177 | CXXRTL - Max Opt - gcc7.5 178 | Yosys 0.9+3667 (git sha1 e7f36d01e, clang 6.0.0-1ubuntu2 -fPIC -Os) 179 | 180 | 181 | real 0m2.409s 182 | user 0m2.399s 183 | sys 0m0.004s 184 | 185 | real 0m2.390s 186 | user 0m2.390s 187 | sys 0m0.000s 188 | 189 | real 0m2.388s 190 | user 0m2.388s 191 | sys 0m0.000s 192 | ``` 193 | -------------------------------------------------------------------------------- /rpu_vhdl/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.cf 3 | tb 4 | ExampleTop.sim.cpp 5 | waves.vcd 6 | 7 | -------------------------------------------------------------------------------- /rpu_vhdl/VexRiscv_wrapper.v: -------------------------------------------------------------------------------- 1 | 2 | module VexRiscv( 3 | input clk_cpu, 4 | input clk_cpu_reset_, 5 | 6 | output iBus_cmd_valid, 7 | input iBus_cmd_ready, 8 | output [31:0] iBus_cmd_payload_pc, 9 | 10 | input iBus_rsp_valid, 11 | input iBus_rsp_payload_error, 12 | input [31:0] iBus_rsp_payload_inst, 13 | 14 | output dBus_cmd_valid, 15 | input dBus_cmd_ready, 16 | output dBus_cmd_payload_wr, 17 | output [31:0] dBus_cmd_payload_address, 18 | output [31:0] dBus_cmd_payload_data, 19 | output [1:0] dBus_cmd_payload_size, 20 | 21 | input dBus_rsp_ready, 22 | input dBus_rsp_error, 23 | input [31:0] dBus_rsp_data, 24 | 25 | input timerInterrupt, 26 | input externalInterrupt, 27 | input softwareInterrupt 28 | ); 29 | 30 | // RPU only has 1 memory interface. Use dBus for that and strap iBus to 31 | // always idle. 32 | assign iBus_cmd_valid = 1'b0; 33 | assign iBus_cmd_payload_pc = 32'd0; 34 | 35 | wire MEM_O_cmd; 36 | wire MEM_I_ready; 37 | wire MEM_O_we; 38 | wire [1:0] MEM_O_byteEnable; 39 | wire [31:0] MEM_O_addr; 40 | wire [31:0] MEM_O_data; 41 | 42 | wire MEM_I_dataReady; 43 | reg [31:0] MEM_I_data; 44 | 45 | core u_rpu( 46 | .I_clk(clk_cpu), 47 | .I_reset(!clk_cpu_reset_), 48 | .I_halt(1'b0), 49 | 50 | .I_int_data(32'd0), 51 | .I_int(1'b0), 52 | .O_int_ack(), 53 | 54 | .MEM_O_cmd(MEM_O_cmd), 55 | .MEM_I_ready(MEM_I_ready), 56 | .MEM_O_addr(MEM_O_addr), 57 | 58 | .MEM_O_we(MEM_O_we), 59 | .MEM_O_byteEnable(MEM_O_byteEnable), 60 | .MEM_O_data(MEM_O_data), 61 | 62 | .MEM_I_dataReady(MEM_I_dataReady), 63 | .MEM_I_data(MEM_I_data), 64 | 65 | .O_halted(), 66 | .O_DBG() 67 | ); 68 | 69 | assign dBus_cmd_valid = MEM_O_cmd; 70 | assign MEM_I_ready = 1'b1; 71 | assign dBus_cmd_payload_address = MEM_O_addr; 72 | assign dBus_cmd_payload_wr = MEM_O_we; 73 | 74 | assign dBus_cmd_payload_size = MEM_O_byteEnable; 75 | assign dBus_cmd_payload_data = MEM_O_data; 76 | 77 | assign MEM_I_dataReady = dBus_rsp_ready; 78 | 79 | always @(*) begin 80 | MEM_I_data = dBus_rsp_data; // Default to avoid a latch 81 | case(MEM_O_byteEnable) 82 | 2'b00: begin 83 | // Byte access 84 | MEM_I_data = (dBus_rsp_data >> (MEM_O_addr[1:0] * 8)) & 32'hff; 85 | end 86 | 2'b01: begin 87 | // HalfWord access 88 | MEM_I_data = (dBus_rsp_data >> (MEM_O_addr[1] * 16)) & 32'hffff; 89 | end 90 | 2'b10: begin 91 | MEM_I_data = dBus_rsp_data; 92 | end 93 | endcase 94 | end 95 | 96 | endmodule 97 | 98 | // 800-746-6216 99 | // 100 | -------------------------------------------------------------------------------- /rpu_vhdl/main.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | 6 | #include 7 | 8 | #include 9 | 10 | #include EXAMPLE_TOP 11 | 12 | using namespace std; 13 | 14 | int main(int argc, char **argv) 15 | { 16 | char *filename; 17 | int dump_level = 0; 18 | 19 | // 20 | // debug level: 21 | // 0 -> No dumping, no save/restore 22 | // 1 -> dump everything 23 | // 2 -> dump everything except memories 24 | // 3 -> dump custom (only wires) 25 | // 4 -> save to checkpoint 26 | // 5 -> restore from checkpoint 27 | 28 | if (argc >= 2){ 29 | dump_level = atoi(argv[1]); 30 | } 31 | 32 | if (argc >= 3){ 33 | filename = argv[2]; 34 | } 35 | 36 | cxxrtl_design::p_ExampleTop top; 37 | cxxrtl::debug_items all_debug_items; 38 | top.debug_info(&all_debug_items, nullptr, ""); 39 | cxxrtl::vcd_writer vcd; 40 | std::ofstream waves; 41 | 42 | if (dump_level >=1 && dump_level <= 3){ 43 | vcd.timescale(1, "us"); 44 | if (dump_level == 1) 45 | vcd.add(all_debug_items); 46 | else if (dump_level == 2) 47 | vcd.add_without_memories(all_debug_items); 48 | else if (dump_level == 3) 49 | vcd.add(all_debug_items, [](const std::string &, const debug_item &item) { 50 | return item.type == debug_item::WIRE; 51 | }); 52 | waves.open(filename); 53 | } 54 | 55 | bool prev_led_red, prev_led_green, prev_led_blue; 56 | 57 | if (dump_level == 5){ 58 | cout << "Restoring from checkpoint..." << endl; 59 | std::ifstream checkpoint("checkpoint.val"); 60 | restore_state(all_debug_items, checkpoint); 61 | cout << "Restore done..." << endl; 62 | dump_all_items(all_debug_items); 63 | } 64 | 65 | top.p_osc__clk__in.set(true); 66 | top.step(); 67 | 68 | if (dump_level >=1 && dump_level <= 3) 69 | vcd.sample(0); 70 | 71 | cxxrtl::debug_item psel = all_debug_items.at("cpu_u_cpu u_uart io_apb_PSEL")[0]; 72 | cxxrtl::debug_item penable = all_debug_items.at("cpu_u_cpu u_uart io_apb_PENABLE")[0]; 73 | cxxrtl::debug_item pwrite = all_debug_items.at("cpu_u_cpu u_uart io_apb_PWRITE")[0]; 74 | cxxrtl::debug_item pwdata = all_debug_items.at("cpu_u_cpu u_uart io_apb_PWDATA")[0]; 75 | cxxrtl::debug_item paddr = all_debug_items.at("cpu_u_cpu u_uart io_apb_PADDR")[0]; 76 | 77 | int led_red_cntr = 0; 78 | 79 | for(int i=0;i<1000000;++i){ 80 | top.p_osc__clk__in.set(false); 81 | top.step(); 82 | 83 | if (dump_level >=1 && dump_level <= 3) 84 | vcd.sample(i*2 + 0); 85 | 86 | top.p_osc__clk__in.set(true); 87 | top.step(); 88 | 89 | if (debug_item_get_value32(psel) && 90 | debug_item_get_value32(penable) && 91 | debug_item_get_value32(pwrite) && 92 | debug_item_get_value32(paddr) == 0 93 | ){ 94 | // APB write to UART RXTX register 95 | cout << "UART TX: " << (char)debug_item_get_value32(pwdata) << endl; 96 | } 97 | 98 | 99 | if (dump_level == 4 && i==10000){ 100 | cout << "Saving checkpoint..." << endl; 101 | std::ofstream checkpoint("checkpoint.val"); 102 | save_state(all_debug_items, checkpoint); 103 | exit(0); 104 | } 105 | 106 | if (dump_level >= 1 && dump_level <= 3) 107 | vcd.sample(i*2 + 1); 108 | 109 | bool cur_led_red = top.p_led__red.get(); 110 | bool cur_led_green = top.p_led__green.get(); 111 | bool cur_led_blue = top.p_led__blue.get(); 112 | 113 | if (cur_led_red != prev_led_red){ 114 | cout << "led_red: " << cur_led_red << " " << led_red_cntr << endl; 115 | if (cur_led_red) 116 | ++led_red_cntr; 117 | } 118 | 119 | if (cur_led_green != prev_led_green){ 120 | cout << "led_green: " << cur_led_green << endl; 121 | } 122 | 123 | if (cur_led_blue != prev_led_blue){ 124 | cout << "led_blue: " << cur_led_blue << endl; 125 | } 126 | 127 | prev_led_red = cur_led_red; 128 | prev_led_green = cur_led_green; 129 | prev_led_blue = cur_led_blue; 130 | 131 | if (dump_level >= 1 && dump_level <= 3){ 132 | waves << vcd.buffer; 133 | vcd.buffer.clear(); 134 | } 135 | } 136 | } 137 | 138 | -------------------------------------------------------------------------------- /rpu_vhdl/run.sh: -------------------------------------------------------------------------------- 1 | 2 | # Fetch RPU 3 | git submodule update --init 4 | 5 | rm -f *.cf 6 | rm -f *.bin 7 | 8 | RPU=./RPU/vhdl/ 9 | 10 | OPTIONS="--std=08" 11 | 12 | ghdl -a $OPTIONS $RPU/constants.vhd $RPU/alu_int32_div.vhd $RPU/control_unit.vhd $RPU/csr_unit.vhd \ 13 | $RPU/lint_unit.vhd $RPU/mem_controller.vhd $RPU/pc_unit.vhd $RPU/register_set.vhd \ 14 | $RPU/unit_alu_RV32_I.vhd $RPU/unit_decoder_RV32I.vhd $RPU/core.vhd 15 | 16 | cp ../spinal/*symbol*.bin . 17 | 18 | yosys -m ghdl -p "read_verilog ../spinal/ExampleTop.sim.v; delete VexRiscv; read_verilog VexRiscv_wrapper.v; ghdl --std=08 core; hierarchy -check -top ExampleTop; write_cxxrtl -Og ExampleTop.sim.cpp" 19 | 20 | clang++-9 -g -O3 -I`yosys-config --datdir`/include/backends/cxxrtl/runtime -DEXAMPLE_TOP=\"ExampleTop.sim.cpp\" -std=c++14 -I../lib main.cpp ../lib/cxxrtl_lib.cpp -o tb 21 | ./tb 2 waves.vcd 22 | -------------------------------------------------------------------------------- /run.sh: -------------------------------------------------------------------------------- 1 | export TOP=`pwd` 2 | 3 | rm $TOP/results.txt 4 | touch $TOP/results.txt 5 | 6 | #cd $TOP/sw 7 | #make clean 8 | #make 9 | #cd $TOP/spinal 10 | #make sim 11 | 12 | ############################################################ 13 | # Icarus Verilog 14 | ############################################################ 15 | 16 | #cd $TOP/tb 17 | #make clean 18 | #make tb 19 | #echo >> $TOP/results.txt 20 | #echo "Icarus Verilog" >> $TOP/results.txt 21 | #echo >> $TOP/results.txt 22 | #(time ./tb) &>> $TOP/results.txt 23 | 24 | 25 | ############################################################ 26 | # Verilator 27 | ############################################################ 28 | 29 | echo "Verilator..." 30 | echo "## Verilator" >> $TOP/results.txt 31 | echo >> $TOP/results.txt 32 | echo "\`\`\`" >> $TOP/results.txt 33 | 34 | cd $TOP/verilator 35 | make tb 36 | 37 | echo "Verilator - No Waves" 38 | echo "Verilator - No Waves" >> $TOP/results.txt 39 | verilator --version >> $TOP/results.txt 40 | echo >> $TOP/results.txt 41 | 42 | (time ./tb) 2>> $TOP/results.txt > /dev/null 43 | (time ./tb) 2>> $TOP/results.txt > /dev/null 44 | (time ./tb) 2>> $TOP/results.txt > /dev/null 45 | 46 | 47 | cd $TOP/verilator 48 | make tb_vcd 49 | 50 | echo >> $TOP/results.txt 51 | echo "Verilator - VCD" 52 | echo "Verilator - VCD" >> $TOP/results.txt 53 | verilator --version >> $TOP/results.txt 54 | echo >> $TOP/results.txt 55 | 56 | (time ./tb_vcd) 2>> $TOP/results.txt > /dev/null 57 | (time ./tb_vcd) 2>> $TOP/results.txt > /dev/null 58 | (time ./tb_vcd) 2>> $TOP/results.txt > /dev/null 59 | 60 | echo "\`\`\`" >> $TOP/results.txt 61 | echo >> $TOP/results.txt 62 | ############################################################ 63 | # CXXRTL - Build simulators 64 | ############################################################ 65 | 66 | #cd $TOP/cxxrtl 67 | #ln -s ~/tools/yosys/yosys-20200612 ./yosys 68 | #make compile 69 | 70 | ############################################################ 71 | # CXXRTL - Max Opt 72 | ############################################################ 73 | 74 | echo "CXXRTL - Max Opt..." 75 | echo "## CXXRTL - Max Opt" >> $TOP/results.txt 76 | 77 | echo >> $TOP/results.txt 78 | echo "\`\`\`" >> $TOP/results.txt 79 | 80 | cd $TOP/cxxrtl 81 | 82 | echo "CXXRTL - Max Opt - No Waves" 83 | echo "CXXRTL - Max Opt - No Waves" >> $TOP/results.txt 84 | ./yosys --version >> $TOP/results.txt 85 | echo >> $TOP/results.txt 86 | 87 | (time ./example_default_clang9) 2>> $TOP/results.txt > /dev/null 88 | (time ./example_default_clang9) 2>> $TOP/results.txt > /dev/null 89 | (time ./example_default_clang9) 2>> $TOP/results.txt > /dev/null 90 | 91 | echo >> $TOP/results.txt 92 | echo "CXXRTL - Max Opt - VCD full (incl Mem)" 93 | echo "CXXRTL - Max Opt - VCD full (incl Mem)" >> $TOP/results.txt 94 | ./yosys --version >> $TOP/results.txt 95 | echo >> $TOP/results.txt 96 | 97 | (time ./example_default_clang9 1 waves_full_incl_mem.vcd) 2>> $TOP/results.txt > /dev/null 98 | 99 | echo >> $TOP/results.txt 100 | echo "CXXRTL - Max Opt - VCD full (no Mem)" 101 | echo "CXXRTL - Max Opt - VCD full (no Mem)" >> $TOP/results.txt 102 | ./yosys --version >> $TOP/results.txt 103 | echo >> $TOP/results.txt 104 | 105 | (time ./example_default_clang9 2 waves_full_no_mem.vcd) 2>> $TOP/results.txt > /dev/null 106 | 107 | echo >> $TOP/results.txt 108 | echo "CXXRTL - Max Opt - VCD regs only" 109 | echo "CXXRTL - Max Opt - VCD regs only" >> $TOP/results.txt 110 | ./yosys --version >> $TOP/results.txt 111 | echo >> $TOP/results.txt 112 | 113 | (time ./example_default_clang9 3 waves_regs_only.vcd) 2>> $TOP/results.txt > /dev/null 114 | 115 | echo "\`\`\`" >> $TOP/results.txt 116 | echo >> $TOP/results.txt 117 | 118 | ############################################################ 119 | # CXXRTL - Max Debug 120 | ############################################################ 121 | 122 | echo "CXXRTL - Max Debug" 123 | echo "## CXXRTL - Max Debug" >> $TOP/results.txt 124 | 125 | echo >> $TOP/results.txt 126 | echo "\`\`\`" >> $TOP/results.txt 127 | 128 | cd $TOP/cxxrtl 129 | 130 | echo "CXXRTL - Max Debug - No Waves" 131 | echo "CXXRTL - Max Debug - No Waves" >> $TOP/results.txt 132 | ./yosys --version >> $TOP/results.txt 133 | echo >> $TOP/results.txt 134 | 135 | (time ./example_Og_clang9) 2>> $TOP/results.txt > /dev/null 136 | (time ./example_Og_clang9) 2>> $TOP/results.txt > /dev/null 137 | (time ./example_Og_clang9) 2>> $TOP/results.txt > /dev/null 138 | 139 | echo >> $TOP/results.txt 140 | echo "CXXRTL - Max Debug - VCD full (incl Mem)" 141 | echo "CXXRTL - Max Debug - VCD full (incl Mem)" >> $TOP/results.txt 142 | ./yosys --version >> $TOP/results.txt 143 | echo >> $TOP/results.txt 144 | 145 | (time ./example_Og_clang9 1 waves_full_incl_mem.vcd) 2>> $TOP/results.txt > /dev/null 146 | 147 | echo >> $TOP/results.txt 148 | echo "CXXRTL - Max Debug - VCD full (no Mem)" 149 | echo "CXXRTL - Max Debug - VCD full (no Mem)" >> $TOP/results.txt 150 | ./yosys --version >> $TOP/results.txt 151 | echo >> $TOP/results.txt 152 | 153 | (time ./example_Og_clang9 2 waves_full_no_mem.vcd) 2>> $TOP/results.txt > /dev/null 154 | 155 | echo >> $TOP/results.txt 156 | echo "CXXRTL - Max Debug - VCD regs only" 157 | echo "CXXRTL - Max Debug - VCD regs only" >> $TOP/results.txt 158 | ./yosys --version >> $TOP/results.txt 159 | echo >> $TOP/results.txt 160 | 161 | (time ./example_Og_clang9 3 waves_regs_only.vcd) 2>> $TOP/results.txt > /dev/null 162 | 163 | echo "\`\`\`" >> $TOP/results.txt 164 | echo >> $TOP/results.txt 165 | 166 | ############################################################ 167 | # CXXRTL - Compiler Versions 168 | ############################################################ 169 | 170 | echo "CXXRTL - Compiler Versions" 171 | echo "## CXXRTL - Compiler Versions" >> $TOP/results.txt 172 | 173 | echo >> $TOP/results.txt 174 | echo "\`\`\`" >> $TOP/results.txt 175 | 176 | cd $TOP/cxxrtl 177 | 178 | echo >> $TOP/results.txt 179 | echo "CXXRTL - Max Opt - clang9" 180 | echo "CXXRTL - Max Opt - clang9" >> $TOP/results.txt 181 | ./yosys --version >> $TOP/results.txt 182 | echo >> $TOP/results.txt 183 | 184 | (time ./example_default_clang9) 2>> $TOP/results.txt > /dev/null 185 | (time ./example_default_clang9) 2>> $TOP/results.txt > /dev/null 186 | (time ./example_default_clang9) 2>> $TOP/results.txt > /dev/null 187 | 188 | echo >> $TOP/results.txt 189 | echo "CXXRTL - Max Opt - clang6" 190 | echo "CXXRTL - Max Opt - clang6" >> $TOP/results.txt 191 | ./yosys --version >> $TOP/results.txt 192 | echo >> $TOP/results.txt 193 | 194 | (time ./example_default_clang6) 2>> $TOP/results.txt > /dev/null 195 | (time ./example_default_clang6) 2>> $TOP/results.txt > /dev/null 196 | (time ./example_default_clang6) 2>> $TOP/results.txt > /dev/null 197 | 198 | echo >> $TOP/results.txt 199 | echo "CXXRTL - Max Opt - gcc10.1" 200 | echo "CXXRTL - Max Opt - gcc10.1" >> $TOP/results.txt 201 | ./yosys --version >> $TOP/results.txt 202 | echo >> $TOP/results.txt 203 | 204 | (time ./example_default_gcc10) 2>> $TOP/results.txt > /dev/null 205 | (time ./example_default_gcc10) 2>> $TOP/results.txt > /dev/null 206 | (time ./example_default_gcc10) 2>> $TOP/results.txt > /dev/null 207 | 208 | echo >> $TOP/results.txt 209 | echo "CXXRTL - Max Opt - gcc7.5" 210 | echo "CXXRTL - Max Opt - gcc7.5" >> $TOP/results.txt 211 | ./yosys --version >> $TOP/results.txt 212 | echo >> $TOP/results.txt 213 | 214 | (time ./example_default_gcc7) 2>> $TOP/results.txt > /dev/null 215 | (time ./example_default_gcc7) 2>> $TOP/results.txt > /dev/null 216 | (time ./example_default_gcc7) 2>> $TOP/results.txt > /dev/null 217 | 218 | echo "\`\`\`" >> $TOP/results.txt 219 | 220 | -------------------------------------------------------------------------------- /save_restore/.gitignore: -------------------------------------------------------------------------------- 1 | blink.cpp 2 | checkpoint.val 3 | tb_save 4 | tb_restore 5 | *.o 6 | -------------------------------------------------------------------------------- /save_restore/Makefile: -------------------------------------------------------------------------------- 1 | 2 | YOSYS = yosys 3 | YOSYS_INCLUDE = $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime 4 | 5 | all: tb_save tb_restore 6 | ./tb_save 7 | ./tb_restore 8 | 9 | tb_save: save.cpp blink.cpp cxxrtl_lib.o 10 | clang++ -g -O0 -std=c++14 -I $(YOSYS_INCLUDE) -I../lib cxxrtl_lib.o $< -o $@ 11 | 12 | tb_restore: restore.cpp blink.cpp cxxrtl_lib.o 13 | clang++ -g -O0 -std=c++14 -I $(YOSYS_INCLUDE) -I../lib cxxrtl_lib.o $< -o $@ 14 | 15 | blink.cpp: blink.v 16 | $(YOSYS) -p "read_verilog blink.v; hierarchy -top blink; write_cxxrtl -Og blink.cpp" 17 | 18 | 19 | cxxrtl_lib.o: ../lib/cxxrtl_lib.cpp 20 | clang++ -c -g -std=c++14 -I $(YOSYS_INCLUDE) -I../lib $< 21 | 22 | clean: 23 | \rm -f blink.cpp tb *.vcd 24 | -------------------------------------------------------------------------------- /save_restore/blink.v: -------------------------------------------------------------------------------- 1 | 2 | module blink(input clk, output led); 3 | 4 | reg [12:0] counter = 0; 5 | 6 | always @(posedge clk) 7 | counter <= counter + 1'b1; 8 | 9 | assign led = counter[7]; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /save_restore/restore.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | 6 | #include 7 | 8 | #include "blink.cpp" 9 | 10 | using namespace std; 11 | using std::setw; 12 | 13 | int main() 14 | { 15 | cxxrtl_design::p_blink top; 16 | 17 | cxxrtl::debug_items all_debug_items; 18 | 19 | top.debug_info(&all_debug_items, nullptr, ""); 20 | 21 | cout << "Restoring from checkpoint..." << endl; 22 | std::ifstream checkpoint("checkpoint.val"); 23 | restore_state(all_debug_items, checkpoint); 24 | 25 | int prev_led = 1; 26 | 27 | top.p_clk = value<1>{1u}; 28 | top.step(); 29 | 30 | dump_all_items(all_debug_items); 31 | 32 | for(int steps=200;steps<1000;++steps){ 33 | 34 | top.p_clk = value<1>{0u}; 35 | top.step(); 36 | 37 | top.p_clk = value<1>{1u}; 38 | top.step(); 39 | 40 | int cur_led = top.p_led.data[0]; 41 | int counter = top.p_counter.curr.data[0]; 42 | 43 | if (cur_led != prev_led) 44 | cout << "cycle " << steps << " - led: " << cur_led << " - counter: " << counter << endl; 45 | 46 | prev_led = cur_led; 47 | } 48 | } 49 | 50 | -------------------------------------------------------------------------------- /save_restore/save.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | 6 | #include 7 | 8 | #include "blink.cpp" 9 | 10 | using namespace std; 11 | 12 | int main() 13 | { 14 | cxxrtl_design::p_blink top; 15 | 16 | cxxrtl::debug_items all_debug_items; 17 | 18 | top.debug_info(&all_debug_items, nullptr, ""); 19 | 20 | // Print all the introspectable information of all debug items 21 | for(auto &it : all_debug_items.table) 22 | for(auto &part: it.second) 23 | cout << setw(20) << it.first << " : type = " << part.type << " : width = " << setw(4) << part.width << " : depth = " << setw(6) << part.depth 24 | << setw(4) << " : lsb_at = " << part.lsb_at << " : zero_at = " << part.zero_at << endl; 25 | 26 | int prev_led = 0; 27 | 28 | top.step(); 29 | 30 | for(int steps=0;steps<1000;++steps){ 31 | 32 | top.p_clk = value<1>{0u}; 33 | top.step(); 34 | 35 | top.p_clk = value<1>{1u}; 36 | top.step(); 37 | 38 | int cur_led = top.p_led.data[0]; 39 | int counter = top.p_counter.curr.data[0]; 40 | 41 | if (cur_led != prev_led) 42 | cout << "cycle " << steps << " - led: " << cur_led << " - counter: " << counter << endl; 43 | 44 | if (counter == 200){ 45 | dump_all_items(all_debug_items); 46 | 47 | std::ofstream checkpoint("checkpoint.val"); 48 | save_state(all_debug_items, checkpoint); 49 | 50 | exit(0); 51 | } 52 | 53 | prev_led = cur_led; 54 | } 55 | } 56 | 57 | -------------------------------------------------------------------------------- /spinal/.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | *.log 3 | *.bak 4 | *.bin 5 | *.yaml 6 | 7 | # sbt specific 8 | .cache/ 9 | .history/ 10 | .lib/ 11 | dist/* 12 | target 13 | lib_managed/ 14 | src_managed/ 15 | project/boot/ 16 | project/plugins/project/ 17 | 18 | # Scala-IDE specific 19 | .scala_dependencies 20 | .worksheet 21 | 22 | .idea 23 | out 24 | 25 | # Eclipse 26 | bin/ 27 | .classpath 28 | .project 29 | .settings 30 | .cache-main 31 | 32 | #User 33 | /*.vhd 34 | /*.v 35 | *.cf 36 | *.json 37 | *.vcd 38 | !tester/src/test/resources/*.vhd 39 | 40 | 41 | simWorkspace/ 42 | tmp/ 43 | -------------------------------------------------------------------------------- /spinal/ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol0.bin: -------------------------------------------------------------------------------- 1 | 00110111 2 | 00010011 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1827 | 00000000 1828 | 00000000 1829 | 00000000 1830 | 00000000 1831 | 00000000 1832 | 00000000 1833 | 00000000 1834 | 00000000 1835 | 00000000 1836 | 00000000 1837 | 00000000 1838 | 00000000 1839 | 00000000 1840 | 00000000 1841 | 00000000 1842 | 00000000 1843 | 00000000 1844 | 00000000 1845 | 00000000 1846 | 00000000 1847 | 00000000 1848 | 00000000 1849 | 00000000 1850 | 00000000 1851 | 00000000 1852 | 00000000 1853 | 00000000 1854 | 00000000 1855 | 00000000 1856 | 00000000 1857 | 00000000 1858 | 00000000 1859 | 00000000 1860 | 00000000 1861 | 00000000 1862 | 00000000 1863 | 00000000 1864 | 00000000 1865 | 00000000 1866 | 00000000 1867 | 00000000 1868 | 00000000 1869 | 00000000 1870 | 00000000 1871 | 00000000 1872 | 00000000 1873 | 00000000 1874 | 00000000 1875 | 00000000 1876 | 00000000 1877 | 00000000 1878 | 00000000 1879 | 00000000 1880 | 00000000 1881 | 00000000 1882 | 00000000 1883 | 00000000 1884 | 00000000 1885 | 00000000 1886 | 00000000 1887 | 00000000 1888 | 00000000 1889 | 00000000 1890 | 00000000 1891 | 00000000 1892 | 00000000 1893 | 00000000 1894 | 00000000 1895 | 00000000 1896 | 00000000 1897 | 00000000 1898 | 00000000 1899 | 00000000 1900 | 00000000 1901 | 00000000 1902 | 00000000 1903 | 00000000 1904 | 00000000 1905 | 00000000 1906 | 00000000 1907 | 00000000 1908 | 00000000 1909 | 00000000 1910 | 00000000 1911 | 00000000 1912 | 00000000 1913 | 00000000 1914 | 00000000 1915 | 00000000 1916 | 00000000 1917 | 00000000 1918 | 00000000 1919 | 00000000 1920 | 00000000 1921 | 00000000 1922 | 00000000 1923 | 00000000 1924 | 00000000 1925 | 00000000 1926 | 00000000 1927 | 00000000 1928 | 00000000 1929 | 00000000 1930 | 00000000 1931 | 00000000 1932 | 00000000 1933 | 00000000 1934 | 00000000 1935 | 00000000 1936 | 00000000 1937 | 00000000 1938 | 00000000 1939 | 00000000 1940 | 00000000 1941 | 00000000 1942 | 00000000 1943 | 00000000 1944 | 00000000 1945 | 00000000 1946 | 00000000 1947 | 00000000 1948 | 00000000 1949 | 00000000 1950 | 00000000 1951 | 00000000 1952 | 00000000 1953 | 00000000 1954 | 00000000 1955 | 00000000 1956 | 00000000 1957 | 00000000 1958 | 00000000 1959 | 00000000 1960 | 00000000 1961 | 00000000 1962 | 00000000 1963 | 00000000 1964 | 00000000 1965 | 00000000 1966 | 00000000 1967 | 00000000 1968 | 00000000 1969 | 00000000 1970 | 00000000 1971 | 00000000 1972 | 00000000 1973 | 00000000 1974 | 00000000 1975 | 00000000 1976 | 00000000 1977 | 00000000 1978 | 00000000 1979 | 00000000 1980 | 00000000 1981 | 00000000 1982 | 00000000 1983 | 00000000 1984 | 00000000 1985 | 00000000 1986 | 00000000 1987 | 00000000 1988 | 00000000 1989 | 00000000 1990 | 00000000 1991 | 00000000 1992 | 00000000 1993 | 00000000 1994 | 00000000 1995 | 00000000 1996 | 00000000 1997 | 00000000 1998 | 00000000 1999 | 00000000 2000 | 00000000 2001 | 00000000 2002 | 00000000 2003 | 00000000 2004 | 00000000 2005 | 00000000 2006 | 00000000 2007 | 00000000 2008 | 00000000 2009 | 00000000 2010 | 00000000 2011 | 00000000 2012 | 00000000 2013 | 00000000 2014 | 00000000 2015 | 00000000 2016 | 00000000 2017 | 00000000 2018 | 00000000 2019 | 00000000 2020 | 00000000 2021 | 00000000 2022 | 00000000 2023 | 00000000 2024 | 00000000 2025 | 00000000 2026 | 00000000 2027 | 00000000 2028 | 00000000 2029 | 00000000 2030 | 00000000 2031 | 00000000 2032 | 00000000 2033 | 00000000 2034 | 00000000 2035 | 00000000 2036 | 00000000 2037 | 00000000 2038 | 00000000 2039 | 00000000 2040 | 00000000 2041 | 00000000 2042 | 00000000 2043 | 00000000 2044 | 00000000 2045 | 00000000 2046 | 00000000 2047 | 00000000 2048 | 00000000 2049 | -------------------------------------------------------------------------------- /spinal/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: syn 3 | 4 | .PHONY: submodule 5 | submodule: 6 | cd ../ && git submodule update --init 7 | 8 | .PHONY: sw 9 | sw: 10 | cd ../sw && make 11 | 12 | 13 | syn: submodule sw 14 | sbt "runMain example.ExampleTopVerilogSyn" 15 | mv ExampleTop.v ExampleTop.syn.v 16 | 17 | sim: submodule sw 18 | sbt "runMain example.ExampleTopVerilogSim" 19 | mv ExampleTop.v ExampleTop.sim.v 20 | 21 | 22 | #waves: 23 | # gtkwave -o simWorkspace/PanoCoreDut/test.vcd & 24 | 25 | -------------------------------------------------------------------------------- /spinal/build.sbt: -------------------------------------------------------------------------------- 1 | 2 | val spinalVersion = "1.4.0" 3 | 4 | lazy val root = (project in file(".")). 5 | settings( 6 | inThisBuild(List( 7 | organization := "com.github.spinalhdl", 8 | scalaVersion := "2.11.12", 9 | version := "1.0.0" 10 | )), 11 | name := "example", 12 | libraryDependencies ++= Seq( 13 | "com.github.spinalhdl" % "spinalhdl-core_2.11" % spinalVersion, 14 | "com.github.spinalhdl" % "spinalhdl-lib_2.11" % spinalVersion, 15 | compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion) 16 | ), 17 | ).dependsOn(vexRiscv) 18 | 19 | lazy val vexRiscv = RootProject(file("./VexRiscv")) 20 | 21 | fork := true 22 | -------------------------------------------------------------------------------- /spinal/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.3.6 2 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/Apb3CC.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.amba3.apb._ 7 | 8 | //============================================================ 9 | // 10 | // APB3 Clock Crossing block 11 | // 12 | //============================================================ 13 | 14 | object Apb3CC { 15 | } 16 | 17 | class Apb3CC(apb3Config: Apb3Config, srcDomain: ClockDomain, destDomain: ClockDomain) extends Component { 18 | 19 | val io = new Bundle { 20 | val src = slave(Apb3(apb3Config)) 21 | val dest = master(Apb3(apb3Config)) 22 | } 23 | 24 | val PRDATA_dest = Bits(apb3Config.dataWidth bits) 25 | 26 | val xfer_done_src = Bool 27 | val xfer_done_dest = Bool 28 | 29 | val u_sync_pulse_xfer_done = new PulseCCByToggle(destDomain, srcDomain) 30 | u_sync_pulse_xfer_done.io.pulseIn <> xfer_done_dest 31 | u_sync_pulse_xfer_done.io.pulseOut <> xfer_done_src 32 | 33 | 34 | val src = new ClockingArea(srcDomain) { 35 | 36 | val xfer_start = Reg(Bool) init(False) 37 | val PADDR = Reg(UInt(apb3Config.addressWidth bits)) init(0) 38 | val PSEL = Reg(Bits(apb3Config.selWidth bits)) init(0) 39 | val PWRITE = RegInit(False) 40 | val PWDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 41 | val PRDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 42 | val PREADY = RegInit(False) 43 | val PSLVERROR = if (apb3Config.useSlaveError) Reg(Bool) else null 44 | 45 | xfer_start := False 46 | when((io.src.PENABLE && io.src.PSEL.orR).rise){ 47 | xfer_start := True 48 | PADDR := io.src.PADDR 49 | PSEL := io.src.PSEL 50 | PWRITE := io.src.PWRITE 51 | PWDATA := io.src.PWDATA 52 | } 53 | 54 | PREADY := False 55 | when(xfer_done_src){ 56 | PREADY := True 57 | when (!io.src.PWRITE){ 58 | PRDATA := PRDATA_dest.addTag(crossClockDomain) 59 | } 60 | } 61 | 62 | io.src.PRDATA := PRDATA 63 | io.src.PREADY := PREADY 64 | } 65 | 66 | val xfer_start_dest = Bool 67 | val u_sync_pulse_xfer_start = new PulseCCByToggle(srcDomain, destDomain) 68 | u_sync_pulse_xfer_start.io.pulseIn <> src.xfer_start 69 | u_sync_pulse_xfer_start.io.pulseOut <> xfer_start_dest 70 | 71 | val dest = new ClockingArea(destDomain) { 72 | val xfer_start_dest_d1 = RegNext(xfer_start_dest) init(False) 73 | 74 | val PADDR = Reg(UInt(apb3Config.addressWidth bits)) init(0) 75 | val PSEL = Reg(Bits(apb3Config.selWidth bits)) init(0) 76 | val PWRITE = RegInit(False) 77 | val PWDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 78 | val PRDATA = Reg(Bits(apb3Config.dataWidth bits)) init(0) 79 | val PSLVERROR = if (apb3Config.useSlaveError) Reg(Bool) else null 80 | 81 | when(xfer_start_dest){ 82 | PADDR := src.PADDR.addTag(crossClockDomain) 83 | PSEL := src.PSEL.addTag(crossClockDomain) 84 | PWRITE := src.PWRITE.addTag(crossClockDomain) 85 | PWDATA := src.PWDATA.addTag(crossClockDomain) 86 | } 87 | 88 | val PENABLE = RegInit(False) setWhen(xfer_start_dest_d1) clearWhen(io.dest.PREADY) 89 | val xfer_done = RegInit(False) 90 | 91 | xfer_done := False 92 | when(PENABLE && io.dest.PREADY){ 93 | PSEL := 0 94 | when(!io.dest.PWRITE){ 95 | PRDATA := io.dest.PRDATA 96 | } 97 | xfer_done := True 98 | } 99 | 100 | 101 | io.dest.PENABLE := PENABLE 102 | io.dest.PADDR := PADDR 103 | io.dest.PSEL := PSEL 104 | io.dest.PWRITE := PWRITE 105 | io.dest.PWDATA := PWDATA 106 | 107 | PRDATA_dest := PRDATA 108 | xfer_done_dest := xfer_done 109 | } 110 | } 111 | 112 | 113 | case class Apb3CCFormalTb() extends Component 114 | { 115 | val io = new Bundle() { 116 | val clk = in(Bool) 117 | val reset_ = in(Bool) 118 | } 119 | 120 | 121 | val domain = new ClockingArea(ClockDomain(io.clk, io.reset_, 122 | config = ClockDomainConfig(resetKind = SYNC, resetActiveLevel = LOW))) 123 | { 124 | val apb3Config = Apb3Config(addressWidth = 6, dataWidth = 32) 125 | 126 | val src = Apb3(apb3Config) 127 | val dest = Apb3(apb3Config) 128 | 129 | val u_apb3cc = new Apb3CC(apb3Config, ClockDomain.current, ClockDomain.current) 130 | u_apb3cc.io.src <> src 131 | u_apb3cc.io.dest <> dest 132 | 133 | val src_xfer_cntr = Reg(UInt(8 bits)) init(0) 134 | val dest_xfer_cntr = Reg(UInt(8 bits)) init(0) 135 | 136 | when(src.PENABLE && src.PREADY){ 137 | src_xfer_cntr := src_xfer_cntr + 1 138 | } 139 | 140 | when(dest.PENABLE && dest.PREADY){ 141 | dest_xfer_cntr := dest_xfer_cntr + 1 142 | } 143 | 144 | 145 | import spinal.core.GenerationFlags._ 146 | import spinal.core.Formal._ 147 | 148 | GenerationFlags.formal{ 149 | import cc.lib._ 150 | 151 | assume(io.reset_ === !initstate()) 152 | 153 | assume(rose(src.PENABLE) |-> stable(src.PSEL)) 154 | assume(rose(src.PENABLE) |-> stable(src.PADDR)) 155 | assume(rose(src.PENABLE) |-> stable(src.PWRITE)) 156 | assume(rose(src.PENABLE) |-> stable(src.PWDATA)) 157 | 158 | assume(src.PREADY |-> stable(src.PENABLE)) 159 | assume(src.PREADY |-> stable(src.PSEL)) 160 | assume(src.PREADY |-> stable(src.PADDR)) 161 | assume(src.PREADY |-> stable(src.PWRITE)) 162 | assume(src.PREADY |-> stable(src.PWDATA)) 163 | 164 | assume(fell(src.PENABLE) |-> src.PREADY) 165 | assume(fell(src.PSEL.orR) |-> src.PREADY) 166 | 167 | assume(!stable(src.PSEL) |=> (fell(src.PENABLE) || !src.PENABLE)) 168 | assume(!stable(src.PADDR) |=> (fell(src.PENABLE) || !src.PENABLE)) 169 | assume(!stable(src.PWRITE) |=> (fell(src.PENABLE) || !src.PENABLE)) 170 | assume(!stable(src.PWDATA) |=> (fell(src.PENABLE) || !src.PENABLE)) 171 | 172 | assume(rose(dest.PREADY) |-> dest.PENABLE) 173 | assume(rose(dest.PREADY) |=> fell(dest.PREADY)) 174 | 175 | when(!initstate()){ 176 | assert(src_xfer_cntr === dest_xfer_cntr || src_xfer_cntr+1 === dest_xfer_cntr) 177 | } 178 | } 179 | }.setName("") 180 | } 181 | 182 | object Apb3CCVerilog{ 183 | def main(args: Array[String]) { 184 | 185 | val config = SpinalConfig(anonymSignalUniqueness = true) 186 | config.includeFormal.generateSystemVerilog({ 187 | val toplevel = new Apb3CCFormalTb() 188 | toplevel 189 | }) 190 | println("DONE") 191 | } 192 | } 193 | 194 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/CCApb3Timer.scala: -------------------------------------------------------------------------------- 1 | package cc 2 | 3 | // All code copied from vexriscv.demo.Murax 4 | 5 | import spinal.core._ 6 | import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory} 7 | import spinal.lib.bus.misc.SizeMapping 8 | import spinal.lib.misc.{ InterruptCtrl, Prescaler, Timer} 9 | import spinal.lib._ 10 | import spinal.lib.bus.simple._ 11 | 12 | class CCApb3Timer extends Component{ 13 | val io = new Bundle { 14 | val apb = slave(Apb3( 15 | addressWidth = 8, 16 | dataWidth = 32 17 | )) 18 | val interrupt = out Bool 19 | } 20 | 21 | val prescaler = Prescaler(8) 22 | val timerA,timerB = Timer(16) 23 | 24 | val busCtrl = Apb3SlaveFactory(io.apb) 25 | val prescalerBridge = prescaler.driveFrom(busCtrl,0x00) 26 | 27 | val timerABridge = timerA.driveFrom(busCtrl,0x40)( 28 | ticks = List(True, prescaler.io.overflow), 29 | clears = List(timerA.io.full) 30 | ) 31 | 32 | val timerBBridge = timerB.driveFrom(busCtrl,0x50)( 33 | ticks = List(True, prescaler.io.overflow), 34 | clears = List(timerB.io.full) 35 | ) 36 | 37 | val interruptCtrl = InterruptCtrl(2) 38 | val interruptCtrlBridge = interruptCtrl.driveFrom(busCtrl,0x10) 39 | interruptCtrl.io.inputs(0) := timerA.io.full 40 | interruptCtrl.io.inputs(1) := timerB.io.full 41 | io.interrupt := interruptCtrl.io.pendings.orR 42 | } 43 | 44 | 45 | object CCApb3TimerGen extends App{ 46 | SpinalVhdl(new CCApb3Timer()) 47 | } 48 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/CCBlocks.scala: -------------------------------------------------------------------------------- 1 | package cc 2 | 3 | // All code copied from vexriscv.demo.Murax 4 | 5 | import java.nio.{ByteBuffer, ByteOrder} 6 | import java.nio.file.{Files, Paths} 7 | 8 | import spinal.core._ 9 | import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory} 10 | import spinal.lib.bus.misc.SizeMapping 11 | import spinal.lib._ 12 | import spinal.lib.bus.simple._ 13 | import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus} 14 | 15 | class CCMasterArbiter(pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{ 16 | val io = new Bundle{ 17 | val iBus = slave(IBusSimpleBus(null)) 18 | val dBus = slave(DBusSimpleBus()) 19 | val masterBus = master(PipelinedMemoryBus(pipelinedMemoryBusConfig)) 20 | } 21 | 22 | io.masterBus.cmd.valid := io.iBus.cmd.valid || io.dBus.cmd.valid 23 | io.masterBus.cmd.write := io.dBus.cmd.valid && io.dBus.cmd.wr 24 | io.masterBus.cmd.address := io.dBus.cmd.valid ? io.dBus.cmd.address | io.iBus.cmd.pc 25 | io.masterBus.cmd.data := io.dBus.cmd.data 26 | io.masterBus.cmd.mask := io.dBus.cmd.size.mux( 27 | 0 -> B"0001", 28 | 1 -> B"0011", 29 | default -> B"1111" 30 | ) |<< io.dBus.cmd.address(1 downto 0) 31 | io.iBus.cmd.ready := io.masterBus.cmd.ready && !io.dBus.cmd.valid 32 | io.dBus.cmd.ready := io.masterBus.cmd.ready 33 | 34 | 35 | val rspPending = RegInit(False) clearWhen(io.masterBus.rsp.valid) 36 | val rspTarget = RegInit(False) 37 | when(io.masterBus.cmd.fire && !io.masterBus.cmd.write){ 38 | rspTarget := io.dBus.cmd.valid 39 | rspPending := True 40 | } 41 | 42 | when(rspPending && !io.masterBus.rsp.valid){ 43 | io.iBus.cmd.ready := False 44 | io.dBus.cmd.ready := False 45 | io.masterBus.cmd.valid := False 46 | } 47 | 48 | io.iBus.rsp.valid := io.masterBus.rsp.valid && !rspTarget 49 | io.iBus.rsp.inst := io.masterBus.rsp.data 50 | io.iBus.rsp.error := False 51 | 52 | io.dBus.rsp.ready := io.masterBus.rsp.valid && rspTarget 53 | io.dBus.rsp.data := io.masterBus.rsp.data 54 | io.dBus.rsp.error := False 55 | } 56 | 57 | 58 | case class CCPipelinedMemoryBusRam(onChipRamSize : BigInt, onChipRamBinFile : String, pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{ 59 | val io = new Bundle{ 60 | val bus = slave(PipelinedMemoryBus(pipelinedMemoryBusConfig)) 61 | } 62 | 63 | val ram = Mem(Bits(32 bits), onChipRamSize / 4) 64 | io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.write) init(False) 65 | io.bus.rsp.data := ram.readWriteSync( 66 | address = (io.bus.cmd.address >> 2).resized, 67 | data = io.bus.cmd.data, 68 | enable = io.bus.cmd.valid, 69 | write = io.bus.cmd.write, 70 | mask = io.bus.cmd.mask 71 | ) 72 | io.bus.cmd.ready := True 73 | 74 | if(onChipRamBinFile != null){ 75 | 76 | val byteArray = Files.readAllBytes(Paths.get(onChipRamBinFile)) 77 | 78 | val initContent = for(i <- 0 until onChipRamSize.toInt/4) yield { 79 | BigInt( (byteArray(4*i).toLong & 0xff) + ((byteArray(4*i+1).toLong & 0xff)<<8) + ((byteArray(4*i+2).toLong & 0xff)<<16) + ((byteArray(4*i+3).toLong & 0xff)<<24) ) 80 | } 81 | ram.initBigInt(initContent) 82 | } 83 | } 84 | 85 | 86 | 87 | case class Apb3Rom(onChipRamBinFile : String) extends Component{ 88 | val byteArray = Files.readAllBytes(Paths.get(onChipRamBinFile)) 89 | val wordCount = (byteArray.length+3)/4 90 | val buffer = ByteBuffer.wrap(Files.readAllBytes(Paths.get(onChipRamBinFile))).order(ByteOrder.LITTLE_ENDIAN); 91 | val wordArray = (0 until wordCount).map(i => { 92 | val v = buffer.getInt 93 | if(v < 0) BigInt(v.toLong & 0xFFFFFFFFl) else BigInt(v) 94 | }) 95 | 96 | val io = new Bundle{ 97 | val apb = slave(Apb3(log2Up(wordCount*4),32)) 98 | } 99 | 100 | val rom = Mem(Bits(32 bits), wordCount) initBigInt(wordArray) 101 | // io.apb.PRDATA := rom.readSync(io.apb.PADDR >> 2) 102 | io.apb.PRDATA := rom.readAsync(RegNext(io.apb.PADDR >> 2)) 103 | io.apb.PREADY := True 104 | } 105 | 106 | 107 | 108 | class CCPipelinedMemoryBusDecoder(master : PipelinedMemoryBus, val specification : Seq[(PipelinedMemoryBus,SizeMapping)], pipelineMaster : Boolean) extends Area{ 109 | val masterPipelined = PipelinedMemoryBus(master.config) 110 | if(!pipelineMaster) { 111 | masterPipelined.cmd << master.cmd 112 | masterPipelined.rsp >> master.rsp 113 | } else { 114 | masterPipelined.cmd <-< master.cmd 115 | masterPipelined.rsp >> master.rsp 116 | } 117 | 118 | val slaveBuses = specification.map(_._1) 119 | val memorySpaces = specification.map(_._2) 120 | 121 | val hits = for((slaveBus, memorySpace) <- specification) yield { 122 | val hit = memorySpace.hit(masterPipelined.cmd.address) 123 | slaveBus.cmd.valid := masterPipelined.cmd.valid && hit 124 | slaveBus.cmd.payload := masterPipelined.cmd.payload.resized 125 | hit 126 | } 127 | val noHit = !hits.orR 128 | masterPipelined.cmd.ready := (hits,slaveBuses).zipped.map(_ && _.cmd.ready).orR || noHit 129 | 130 | val rspPending = RegInit(False) clearWhen(masterPipelined.rsp.valid) setWhen(masterPipelined.cmd.fire && !masterPipelined.cmd.write) 131 | val rspNoHit = RegNext(False) init(False) setWhen(noHit) 132 | val rspSourceId = RegNextWhen(OHToUInt(hits), masterPipelined.cmd.fire) 133 | masterPipelined.rsp.valid := slaveBuses.map(_.rsp.valid).orR || (rspPending && rspNoHit) 134 | masterPipelined.rsp.payload := slaveBuses.map(_.rsp.payload).read(rspSourceId) 135 | 136 | when(rspPending && !masterPipelined.rsp.valid) { //Only one pending read request is allowed 137 | masterPipelined.cmd.ready := False 138 | slaveBuses.foreach(_.cmd.valid := False) 139 | } 140 | } 141 | 142 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/CCGpio.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.amba3.apb._ 7 | import spinal.lib.io.{TriStateArray, TriState} 8 | 9 | object CCGpio { 10 | def getApb3Config() = Apb3Config(addressWidth = 5,dataWidth = 32) 11 | } 12 | 13 | // 0x0000 : Direction. 0 -> input, 1 -> output 14 | // 0x0004 : Write 15 | // 0x0008 : Set 16 | // 0x000c : Clear 17 | // 0x0010 : Read 18 | 19 | case class CCGpio(gpioWidth: Int) extends Component { 20 | 21 | val io = new Bundle { 22 | val apb = slave(Apb3(CCGpio.getApb3Config())) 23 | val gpio = master(TriStateArray(gpioWidth bits)) 24 | } 25 | 26 | val value = Reg(Bits(gpioWidth bits)) init(0) 27 | val ctrl = Apb3SlaveFactory(io.apb) 28 | 29 | // Direction 30 | io.gpio.writeEnable := ctrl.createReadAndWrite(Bits(gpioWidth bits), 0) init(0) 31 | 32 | // Straight read and write 33 | ctrl.readAndWrite(value, 4) 34 | 35 | // Set bit when corresponding value is set 36 | val wrBits = ctrl.nonStopWrite(Bits(gpioWidth bits), 0) 37 | ctrl.onWrite(8){ 38 | for(i <- 0 until gpioWidth){ 39 | when(wrBits(i)){ 40 | value(i) := True 41 | } 42 | } 43 | } 44 | 45 | // Clear bit when corresponding value is set 46 | ctrl.onWrite(12){ 47 | for(i <- 0 until gpioWidth){ 48 | when(wrBits(i)){ 49 | value(i) := False 50 | } 51 | } 52 | } 53 | 54 | ctrl.read(io.gpio.read, 0x0010) 55 | 56 | io.gpio.write := value 57 | } 58 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/CpuComplex.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.bus.amba3.apb._ 7 | import spinal.lib.bus.misc.SizeMapping 8 | import spinal.lib.bus.simple._ 9 | 10 | import scala.collection.mutable.ArrayBuffer 11 | import vexriscv.plugin.{NONE, _} 12 | import vexriscv.{VexRiscv, VexRiscvConfig, plugin} 13 | 14 | case class CpuComplexConfig( 15 | onChipRamSize : BigInt, 16 | onChipRamBinFile : String, 17 | pipelineDBus : Boolean, 18 | pipelineMainBus : Boolean, 19 | pipelineApbBridge : Boolean, 20 | apb3Config : Apb3Config, 21 | cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ 22 | 23 | require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") 24 | } 25 | 26 | object CpuComplexConfig{ 27 | 28 | def default = CpuComplexConfig( 29 | onChipRamSize = 8 kB, 30 | onChipRamBinFile = null, 31 | pipelineDBus = true, 32 | pipelineMainBus = false, 33 | pipelineApbBridge = true, 34 | cpuPlugins = ArrayBuffer( 35 | new IBusSimplePlugin( 36 | resetVector = 0x00000000l, 37 | cmdForkOnSecondStage = true, 38 | cmdForkPersistence = false, 39 | prediction = STATIC, 40 | catchAccessFault = false, 41 | compressedGen = true 42 | ), 43 | new DBusSimplePlugin( 44 | catchAddressMisaligned = false, 45 | catchAccessFault = false, 46 | earlyInjection = false 47 | ), 48 | new CsrPlugin( 49 | CsrPluginConfig( 50 | catchIllegalAccess = false, 51 | mvendorid = null, 52 | marchid = null, 53 | mimpid = null, 54 | mhartid = null, 55 | misaExtensionsInit = 0, 56 | misaAccess = CsrAccess.NONE, 57 | mtvecAccess = CsrAccess.NONE, 58 | mtvecInit = 0x00000020l, 59 | mepcAccess = CsrAccess.NONE, 60 | mscratchGen = true, 61 | mcauseAccess = CsrAccess.READ_ONLY, 62 | mbadaddrAccess = CsrAccess.NONE, 63 | mcycleAccess = CsrAccess.NONE, 64 | minstretAccess = CsrAccess.NONE, 65 | ecallGen = false, 66 | wfiGenAsWait = false, 67 | ucycleAccess = CsrAccess.READ_ONLY 68 | ) 69 | ), 70 | new DecoderSimplePlugin( 71 | catchIllegalInstruction = false 72 | ), 73 | new RegFilePlugin( 74 | regFileReadyKind = plugin.SYNC, 75 | zeroBoot = false 76 | ), 77 | new IntAluPlugin, 78 | new MulPlugin, 79 | new SrcPlugin( 80 | separatedAddSub = false, 81 | executeInsertion = false 82 | ), 83 | new FullBarrelShifterPlugin, 84 | new HazardSimplePlugin( 85 | bypassExecute = true, 86 | bypassMemory = true, 87 | bypassWriteBack = true, 88 | bypassWriteBackBuffer = true, 89 | pessimisticUseSrc = false, 90 | pessimisticWriteRegFile = false, 91 | pessimisticAddressMatch = false 92 | ), 93 | new BranchPlugin( 94 | earlyBranch = false, 95 | catchAddressMisaligned = false 96 | ), 97 | new YamlPlugin("cpu0.yaml") 98 | ), 99 | apb3Config = Apb3Config( 100 | addressWidth = 20, 101 | dataWidth = 32 102 | ) 103 | ) 104 | 105 | def fast = { 106 | val config = default 107 | 108 | // Replace HazardSimplePlugin to get datapath bypass 109 | config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[HazardSimplePlugin])) = new HazardSimplePlugin( 110 | bypassExecute = true, 111 | bypassMemory = true, 112 | bypassWriteBack = true, 113 | bypassWriteBackBuffer = true 114 | ) 115 | // config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrelShifterPlugin() 116 | 117 | config 118 | } 119 | } 120 | 121 | 122 | case class CpuComplex(config : CpuComplexConfig) extends Component 123 | { 124 | import config._ 125 | 126 | val io = new Bundle { 127 | val apb = master(Apb3(config.apb3Config)) 128 | val externalInterrupt = in(Bool) 129 | val timerInterrupt = in(Bool) 130 | } 131 | 132 | val pipelinedMemoryBusConfig = PipelinedMemoryBusConfig( 133 | addressWidth = 32, 134 | dataWidth = 32 135 | ) 136 | 137 | // Arbiter of the cpu dBus/iBus to drive the mainBus 138 | // Priority to dBus, !! cmd transactions can change on the fly !! 139 | val mainBusArbiter = new CCMasterArbiter(pipelinedMemoryBusConfig) 140 | 141 | //Instanciate the CPU 142 | val cpu = new VexRiscv( 143 | config = VexRiscvConfig( 144 | plugins = cpuPlugins 145 | ) 146 | ) 147 | 148 | // Checkout plugins used to instanciate the CPU to connect them to the SoC 149 | for(plugin <- cpu.plugins) plugin match{ 150 | case plugin : IBusSimplePlugin => mainBusArbiter.io.iBus <> plugin.iBus 151 | case plugin : DBusSimplePlugin => { 152 | if(!pipelineDBus) 153 | mainBusArbiter.io.dBus <> plugin.dBus 154 | else { 155 | mainBusArbiter.io.dBus.cmd << plugin.dBus.cmd.halfPipe() 156 | mainBusArbiter.io.dBus.rsp <> plugin.dBus.rsp 157 | } 158 | } 159 | case plugin : CsrPlugin => { 160 | plugin.externalInterrupt := io.externalInterrupt 161 | plugin.timerInterrupt := io.timerInterrupt 162 | } 163 | case _ => 164 | } 165 | 166 | //****** MainBus slaves ******** 167 | val mainBusMapping = ArrayBuffer[(PipelinedMemoryBus,SizeMapping)]() 168 | val ram = new CCPipelinedMemoryBusRam( 169 | onChipRamSize = onChipRamSize, 170 | onChipRamBinFile = onChipRamBinFile, 171 | pipelinedMemoryBusConfig = pipelinedMemoryBusConfig 172 | ) 173 | 174 | mainBusMapping += ram.io.bus -> (0x00000000l, onChipRamSize) 175 | 176 | val apbBridge = new PipelinedMemoryBusToApbBridge( 177 | apb3Config = Apb3Config( 178 | addressWidth = 20, 179 | dataWidth = 32 180 | ), 181 | pipelineBridge = pipelineApbBridge, 182 | pipelinedMemoryBusConfig = pipelinedMemoryBusConfig 183 | ) 184 | mainBusMapping += apbBridge.io.pipelinedMemoryBus -> (0x80000000l, 1 MB) 185 | 186 | io.apb <> apbBridge.io.apb 187 | 188 | val mainBusDecoder = new Area { 189 | val logic = new CCPipelinedMemoryBusDecoder( 190 | master = mainBusArbiter.io.masterBus, 191 | specification = mainBusMapping, 192 | pipelineMaster = pipelineMainBus 193 | ) 194 | } 195 | 196 | } 197 | 198 | -------------------------------------------------------------------------------- /spinal/src/main/scala/cc/Sequence.scala: -------------------------------------------------------------------------------- 1 | 2 | package cc 3 | 4 | import spinal.core._ 5 | 6 | // Eventually, this needs to become that whole thing with FSMs etc. 7 | 8 | class Sequence(seq: Bool){ 9 | 10 | def |->(that: Bool): Bool = { 11 | val result = Bool 12 | 13 | result := !seq || that 14 | 15 | result 16 | } 17 | 18 | def |=>(that: Bool): Bool = { 19 | val result = Bool 20 | 21 | result := !RegNext(seq) || that 22 | 23 | result 24 | } 25 | 26 | } 27 | 28 | package object lib { 29 | implicit def sequence(that: Bool)= new Sequence(that) 30 | } 31 | 32 | -------------------------------------------------------------------------------- /spinal/src/main/scala/example/CpuTop.scala: -------------------------------------------------------------------------------- 1 | 2 | package example 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.io._ 7 | import spinal.lib.bus.amba3.apb._ 8 | import spinal.lib.bus.misc.SizeMapping 9 | import spinal.lib.com.uart._ 10 | import spinal.lib.com.i2c._ 11 | 12 | import scala.collection.mutable.ArrayBuffer 13 | import cc._ 14 | 15 | case class CpuTop() extends Component { 16 | 17 | val io = new Bundle { 18 | val led_red = out(Bool) 19 | val led_green = out(Bool) 20 | val led_blue = out(Bool) 21 | 22 | val uart = master(Uart()) 23 | } 24 | 25 | val cpuConfig = CpuComplexConfig.default.copy(onChipRamBinFile = "../sw/progmem_full.bin") 26 | //val cpuConfig = CpuComplexConfig.default 27 | 28 | val u_cpu = CpuComplex(cpuConfig) 29 | u_cpu.io.externalInterrupt := False 30 | 31 | val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]() 32 | 33 | //============================================================ 34 | // Timer 35 | //============================================================ 36 | 37 | val u_timer = new CCApb3Timer() 38 | u_timer.io.interrupt <> u_cpu.io.timerInterrupt 39 | apbMapping += u_timer.io.apb -> (0x00000, 4 kB) 40 | 41 | //============================================================ 42 | // GPIO control, bits: 43 | // 0 - Green LED 44 | // 1 - Blue LED 45 | // 2 - Red LED (write only: hardware limitation) 46 | // 3 - Pano button 47 | //============================================================ 48 | 49 | val u_led_ctrl = Apb3Gpio(3, withReadSync = true) 50 | u_led_ctrl.io.gpio.write(0) <> io.led_red 51 | u_led_ctrl.io.gpio.write(1) <> io.led_green 52 | u_led_ctrl.io.gpio.write(2) <> io.led_blue 53 | u_led_ctrl.io.gpio.read(0) := io.led_red 54 | u_led_ctrl.io.gpio.read(1) := io.led_green 55 | u_led_ctrl.io.gpio.read(2) := io.led_blue 56 | 57 | apbMapping += u_led_ctrl.io.apb -> (0x10000, 4 kB) 58 | 59 | //============================================================ 60 | // Uart 61 | //============================================================ 62 | 63 | val uartConfig = UartCtrlMemoryMappedConfig( 64 | uartCtrlConfig = UartCtrlGenerics(), 65 | initConfig = UartCtrlInitConfig( 66 | baudrate = 115200 67 | ), 68 | txFifoDepth = 255 69 | ) 70 | 71 | val u_uart = Apb3UartCtrl(config = uartConfig) 72 | u_uart.io.uart <> io.uart 73 | 74 | apbMapping += u_uart.io.apb -> (0x20000, 4 kB) 75 | 76 | //============================================================ 77 | // External APBs 78 | //============================================================ 79 | 80 | //============================================================ 81 | // Local APB decoder 82 | //============================================================ 83 | val apbDecoder = Apb3Decoder( 84 | master = u_cpu.io.apb, 85 | slaves = apbMapping 86 | ) 87 | 88 | } 89 | 90 | -------------------------------------------------------------------------------- /spinal/src/main/scala/example/ExampleTop.scala: -------------------------------------------------------------------------------- 1 | 2 | package example 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import spinal.lib.io._ 7 | import spinal.lib.bus.misc._ 8 | import spinal.lib.bus.amba3.apb._ 9 | import spinal.lib.com.uart._ 10 | 11 | class ExampleTop() extends Component 12 | { 13 | val io = new Bundle { 14 | 15 | val osc_clk_in = in(Bool) 16 | 17 | val button = in(Bool) 18 | 19 | val led_red = out(Bool) 20 | val led_green = out(Bool) 21 | val led_blue = out(Bool) 22 | 23 | val uart = master(Uart()) 24 | } 25 | 26 | noIoPrefix() 27 | 28 | val clk_cpu = Bool 29 | 30 | clk_cpu := io.osc_clk_in 31 | 32 | val clkCpuRawDomain = ClockDomain( 33 | clock = clk_cpu, 34 | frequency = FixedFrequency(50 MHz), 35 | config = ClockDomainConfig( 36 | resetKind = BOOT 37 | ) 38 | ) 39 | 40 | //============================================================ 41 | // Create clk_cpu reset 42 | //============================================================ 43 | val clk_cpu_reset_ = Bool 44 | 45 | val clk_cpu_reset_gen = new ClockingArea(clkCpuRawDomain) { 46 | val reset_unbuffered_ = True 47 | 48 | val reset_cntr = Reg(UInt(5 bits)) init(0) 49 | when(reset_cntr =/= U(reset_cntr.range -> true)){ 50 | reset_cntr := reset_cntr + 1 51 | reset_unbuffered_ := False 52 | } 53 | 54 | clk_cpu_reset_ := RegNext(reset_unbuffered_) 55 | } 56 | 57 | 58 | val clkCpuDomain = ClockDomain( 59 | clock = clk_cpu, 60 | reset = clk_cpu_reset_, 61 | frequency = FixedFrequency(50 MHz), 62 | config = ClockDomainConfig( 63 | resetKind = SYNC, 64 | resetActiveLevel = LOW 65 | ) 66 | ) 67 | 68 | val cpu = new ClockingArea(clkCpuDomain) { 69 | val u_cpu = new CpuTop() 70 | u_cpu.io.uart <> io.uart 71 | u_cpu.io.led_red <> io.led_red 72 | u_cpu.io.led_green <> io.led_green 73 | u_cpu.io.led_blue <> io.led_blue 74 | } 75 | 76 | } 77 | 78 | 79 | object ExampleTopVerilogSim { 80 | def main(args: Array[String]) { 81 | 82 | val config = SpinalConfig(anonymSignalUniqueness = true) 83 | 84 | config.generateVerilog({ 85 | val toplevel = new ExampleTop() 86 | InOutWrapper(toplevel) 87 | }) 88 | 89 | } 90 | } 91 | 92 | object ExampleTopVerilogSyn { 93 | def main(args: Array[String]) { 94 | 95 | val config = SpinalConfig(anonymSignalUniqueness = true) 96 | config.generateVerilog({ 97 | val toplevel = new ExampleTop() 98 | InOutWrapper(toplevel) 99 | toplevel 100 | }) 101 | } 102 | } 103 | 104 | 105 | -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- 1 | progmem*.* 2 | *.o 3 | -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- 1 | 2 | MEM_WORDS = 2048 3 | MEM_BYTES = 8192 4 | 5 | MARCH = rv32im_zicsr 6 | CPU_FREQ_MHZ = 50 7 | CC_OPT = -Os 8 | 9 | OBJ_FILES = start.o main.o uart.o lib.o timer.o 10 | 11 | TOOLS_PREFIX = /opt/riscv32i/bin 12 | ##TOOLS_PREFIX = /opt/riscv32im/bin 13 | TARGET = $(TOOLS_PREFIX)/riscv32-unknown-elf 14 | AS = $(TARGET)-as 15 | ASFLAGS = -march=$(MARCH) -mabi=ilp32 16 | LD = $(TARGET)-gcc 17 | LDFLAGS = -march=$(MARCH) -mabi=ilp32 -Wl,-Tsections.lds,-Map,progmem.map -ffreestanding -nostartfiles 18 | CC = $(TARGET)-gcc 19 | CFLAGS = -march=$(MARCH) -mno-div -mabi=ilp32 -Wall -Wextra -pedantic -DCPU_FREQ=$(CPU_FREQ_MHZ)000000 $(CC_OPT) 20 | OBJCOPY = $(TARGET)-objcopy 21 | OBJDUMP = $(TARGET)-objdump 22 | 23 | .PHONY: all clean syntax time stat flash 24 | 25 | #all: progmem.dis progmem.bin progmem0.coe progmem0.mif progmem0.hex progmem.mem 26 | all: progmem.dis progmem.bin progmem_full.bin progmem.mem progmem.hex progmem0.mif 27 | 28 | progmem.dis: progmem_dis.elf 29 | $(OBJDUMP) -s -D $< > $@ 30 | 31 | progmem.hex: progmem_full.bin 32 | $(OBJCOPY) --change-addresses 0x80000000 -O ihex -I binary $< $@ 33 | 34 | progmem0.hex: progmem.bin 35 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 0 -i 4 $< > progmem0.hex 36 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 1 -i 4 $< > progmem1.hex 37 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 2 -i 4 $< > progmem2.hex 38 | ../misc/create_mif.rb -f hex -d $(MEM_WORDS) -w 8 -o 3 -i 4 $< > progmem3.hex 39 | 40 | progmem0.coe: progmem.bin 41 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 0 -i 4 $< > progmem0.coe 42 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 1 -i 4 $< > progmem1.coe 43 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 2 -i 4 $< > progmem2.coe 44 | ../misc/create_mif.rb -f coe -d $(MEM_WORDS) -w 8 -o 3 -i 4 $< > progmem3.coe 45 | 46 | progmem0.mif: progmem.bin 47 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 0 -i 4 $< > progmem0.mif 48 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 1 -i 4 $< > progmem1.mif 49 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 2 -i 4 $< > progmem2.mif 50 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 8 -o 3 -i 4 $< > progmem3.mif 51 | 52 | progmem.mif: progmem.bin 53 | ../misc/create_mif.rb -f mif -d $(MEM_WORDS) -w 32 $< > progmem.mif 54 | 55 | progmem.mem: progmem.bin 56 | ../misc/create_mif.rb -f mem -d $(MEM_WORDS) -w 32 $< > progmem.mem 57 | 58 | progmem.bin: progmem.elf 59 | $(OBJCOPY) -O binary $< $@ 60 | 61 | progmem_full.bin: progmem.elf 62 | $(OBJCOPY) --pad-to=$(MEM_BYTES) -O binary $< $@ 63 | 64 | progmem.elf: $(OBJ_FILES) top_defines.h sections.lds Makefile 65 | $(LD) $(LDFLAGS) -s -o $@ $(OBJ_FILES) > progmem.map 66 | 67 | progmem_dis.elf: $(OBJ_FILES) top_defines.h sections.lds Makefile 68 | $(LD) $(LDFLAGS) -o $@ $(OBJ_FILES) > progmem.map 69 | 70 | clean: 71 | \rm -fr *.o *.hex *.elf *.dis *.bin *.coe *.map *.mif *.mem 72 | -------------------------------------------------------------------------------- /sw/lib.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "reg.h" 4 | #include "top_defines.h" 5 | 6 | static inline uint32_t _rdcycle(void) { 7 | uint32_t cycle; 8 | asm volatile ("rdcycle %0" : "=r"(cycle)); 9 | return cycle; 10 | } 11 | 12 | static inline uint32_t _rdcycleh(void) { 13 | uint32_t cycle; 14 | asm volatile ("rdcycleh %0" : "=r"(cycle)); 15 | return cycle; 16 | } 17 | 18 | static inline int nop(void) { 19 | asm volatile ("addi x0, x0, 0"); 20 | return 0; 21 | } 22 | 23 | uint64_t rdcycle(void) { 24 | 25 | uint32_t msw; 26 | uint32_t lsw; 27 | 28 | do{ 29 | msw = _rdcycleh(); 30 | lsw = _rdcycle(); 31 | } while(msw != _rdcycleh()); 32 | 33 | return ((uint64_t)msw << 32) | lsw; 34 | } 35 | 36 | void wait_cycles(unsigned int cycles) 37 | { 38 | uint64_t start; 39 | 40 | start = rdcycle(); 41 | while ((rdcycle() - start) <= (uint64_t)cycles); 42 | } 43 | 44 | 45 | void wait_ms(unsigned int ms) 46 | { 47 | wait_cycles(CPU_FREQ * (uint64_t)ms / 1000); 48 | } 49 | 50 | void wait_us(unsigned int us) 51 | { 52 | wait_cycles(CPU_FREQ * (uint64_t)us / 1000000); 53 | } 54 | -------------------------------------------------------------------------------- /sw/lib.h: -------------------------------------------------------------------------------- 1 | #ifndef LIB_H 2 | #define LIB_H 3 | 4 | uint64_t rdcycle(void); 5 | void wait_cycles(unsigned int cycles); 6 | void wait_ms(unsigned int ms); 7 | void wait_us(unsigned int us); 8 | 9 | #endif 10 | -------------------------------------------------------------------------------- /sw/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "lib.h" 5 | #include "reg.h" 6 | #include "top_defines.h" 7 | #include "uart.h" 8 | #include "timer.h" 9 | #include "riscv.h" 10 | 11 | void externalInterrupt() 12 | { 13 | /* 14 | uint32_t claim; 15 | //While there is pending interrupts 16 | while(claim = plic_claim(PLIC, PLIC_CPU_0)){ 17 | switch(claim){ 18 | case PLIC_I2C_INTERRUPT: externalInterrupt_i2c(); break; 19 | default: crash(); break; 20 | } 21 | plic_release(PLIC, PLIC_CPU_0, claim); //unmask the claimed interrupt 22 | } 23 | */ 24 | 25 | } 26 | 27 | void crash(){ 28 | while(1); 29 | } 30 | 31 | void trap() 32 | { 33 | //timer_irq_clr(0xff); 34 | 35 | int32_t mcause = csr_read(mcause); 36 | int32_t interrupt = mcause < 0; //Interrupt if set, exception if cleared 37 | int32_t cause = mcause & 0xF; 38 | if(interrupt){ 39 | 40 | switch(cause){ 41 | case CAUSE_MACHINE_EXTERNAL: externalInterrupt(); break; 42 | default: crash(); break; 43 | } 44 | } 45 | else { 46 | crash(); 47 | } 48 | } 49 | 50 | 51 | 52 | int main() 53 | { 54 | // Enable global interrupt: set MIE bit in MSTATUS 55 | csr_set(mstatus, MSTATUS_MPP | MSTATUS_MIE); // FIXME: what is MPP? 56 | 57 | // Enable timer interrupt 58 | //csr_set(mie, MIE_MTIE); 59 | 60 | // Enable external interrupt 61 | csr_set(mie, MIE_MEIE); 62 | 63 | uart_init(); 64 | uart_tx_str("\nHello World!\n"); 65 | 66 | REG_WR(LED_DIR, 0xff); 67 | for(int i=0;i<1500;++i){ 68 | REG_WR(LED_WRITE, 0x01); 69 | wait_cycles(100); 70 | REG_WR(LED_WRITE, 0x02); 71 | wait_cycles(100); 72 | REG_WR(LED_WRITE, 0x04); 73 | wait_cycles(100); 74 | } 75 | 76 | uart_tx_str("\nLEDs done!\n"); 77 | 78 | while(1); 79 | } 80 | -------------------------------------------------------------------------------- /sw/progmem.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/cxxrtl_eval/a8fbed97f8f55e5b89960eccac01cbf463a6d4b3/sw/progmem.bin -------------------------------------------------------------------------------- /sw/reg.h: -------------------------------------------------------------------------------- 1 | #ifndef REG_H 2 | #define REG_H 3 | 4 | #define REG_WR(reg_name, wr_data) (*((volatile uint32_t *)(0x80000000 | reg_name##_ADDR)) = (wr_data)) 5 | #define REG_RD(reg_name) (*((volatile uint32_t *)(0x80000000 | reg_name##_ADDR))) 6 | 7 | #define FIELD_MASK(reg_name, field_name) ( ((1<<(reg_name##_##field_name##_FIELD_LENGTH))-1) << (reg_name##_##field_name##_FIELD_START)) 8 | 9 | #define REG_WR_FIELD(reg_name, field_name, wr_data) (*((volatile uint32_t *)(0x80000000 | reg_name##_ADDR)) = \ 10 | ((REG_RD(reg_name) \ 11 | & ~FIELD_MASK(reg_name, field_name)) \ 12 | | (((wr_data)<<(reg_name##_##field_name##_FIELD_START)) & FIELD_MASK(reg_name, field_name)))) 13 | 14 | #define REG_RD_FIELD(reg_name, field_name) ((REG_RD(reg_name) & FIELD_MASK(reg_name, field_name)) >> (reg_name##_##field_name##_FIELD_START)) 15 | 16 | 17 | #define MEM_WR(mem_name, wr_addr, wr_data) (*( (volatile uint32_t *)(0x80000000 | mem_name##_ADDR) + (wr_addr)) = (wr_data)) 18 | #define MEM_RD(mem_name, rd_addr) (*( (volatile uint32_t *)(0x80000000 | mem_name##_ADDR) + (rd_addr))) 19 | 20 | #define GET_FIELD(var, reg_name, field_name) (((var) >> (reg_name##_##field_name##_##FIELD_START)) & ((1<<(reg_name##_##field_name##_##FIELD_LENGTH))-1)) 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /sw/riscv.h: -------------------------------------------------------------------------------- 1 | #ifndef RISCV_H 2 | #define RISCV_H 3 | 4 | //exceptions 5 | #define CAUSE_ILLEGAL_INSTRUCTION 2 6 | #define CAUSE_MACHINE_TIMER 7 7 | #define CAUSE_SCALL 9 8 | 9 | //interrupts 10 | #define CAUSE_MACHINE_EXTERNAL 11 11 | 12 | 13 | #define MEDELEG_INSTRUCTION_PAGE_FAULT (1 << 12) 14 | #define MEDELEG_LOAD_PAGE_FAULT (1 << 13) 15 | #define MEDELEG_STORE_PAGE_FAULT (1 << 15) 16 | #define MEDELEG_USER_ENVIRONNEMENT_CALL (1 << 8) 17 | #define MIDELEG_SUPERVISOR_SOFTWARE (1 << 1) 18 | #define MIDELEG_SUPERVISOR_TIMER (1 << 5) 19 | #define MIDELEG_SUPERVISOR_EXTERNAL (1 << 9) 20 | 21 | #define MIP_STIP (1 << 5) 22 | #define MIE_MTIE (1 << CAUSE_MACHINE_TIMER) 23 | #define MIE_MEIE (1 << CAUSE_MACHINE_EXTERNAL) 24 | 25 | #define MSTATUS_UIE 0x00000001 26 | #define MSTATUS_SIE 0x00000002 27 | #define MSTATUS_HIE 0x00000004 28 | #define MSTATUS_MIE 0x00000008 29 | #define MSTATUS_UPIE 0x00000010 30 | #define MSTATUS_SPIE 0x00000020 31 | #define MSTATUS_HPIE 0x00000040 32 | #define MSTATUS_MPIE 0x00000080 33 | #define MSTATUS_SPP 0x00000100 34 | #define MSTATUS_HPP 0x00000600 35 | #define MSTATUS_MPP 0x00001800 36 | #define MSTATUS_FS 0x00006000 37 | #define MSTATUS_XS 0x00018000 38 | #define MSTATUS_MPRV 0x00020000 39 | #define MSTATUS_SUM 0x00040000 40 | #define MSTATUS_MXR 0x00080000 41 | #define MSTATUS_TVM 0x00100000 42 | #define MSTATUS_TW 0x00200000 43 | #define MSTATUS_TSR 0x00400000 44 | #define MSTATUS32_SD 0x80000000 45 | #define MSTATUS_UXL 0x0000000300000000 46 | #define MSTATUS_SXL 0x0000000C00000000 47 | #define MSTATUS64_SD 0x8000000000000000 48 | 49 | #define SSTATUS_UIE 0x00000001 50 | #define SSTATUS_SIE 0x00000002 51 | #define SSTATUS_UPIE 0x00000010 52 | #define SSTATUS_SPIE 0x00000020 53 | #define SSTATUS_SPP 0x00000100 54 | #define SSTATUS_FS 0x00006000 55 | #define SSTATUS_XS 0x00018000 56 | #define SSTATUS_SUM 0x00040000 57 | #define SSTATUS_MXR 0x00080000 58 | #define SSTATUS32_SD 0x80000000 59 | #define SSTATUS_UXL 0x0000000300000000 60 | #define SSTATUS64_SD 0x8000000000000000 61 | 62 | 63 | #define PMP_R 0x01 64 | #define PMP_W 0x02 65 | #define PMP_X 0x04 66 | #define PMP_A 0x18 67 | #define PMP_L 0x80 68 | #define PMP_SHIFT 2 69 | 70 | #define PMP_TOR 0x08 71 | #define PMP_NA4 0x10 72 | #define PMP_NAPOT 0x18 73 | 74 | #define RDCYCLE 0xC00 //Read-only cycle Cycle counter for RDCYCLE instruction. 75 | #define RDTIME 0xC01 //Read-only time Timer for RDTIME instruction. 76 | #define RDINSTRET 0xC02 //Read-only instret Instructions-retired counter for RDINSTRET instruction. 77 | #define RDCYCLEH 0xC80 //Read-only cycleh Upper 32 bits of cycle, RV32I only. 78 | #define RDTIMEH 0xC81 //Read-only timeh Upper 32 bits of time, RV32I only. 79 | #define RDINSTRETH 0xC82 //Read-only instreth Upper 32 bits of instret, RV32I only. 80 | 81 | 82 | #define csr_swap(csr, val) \ 83 | ({ \ 84 | unsigned long __v = (unsigned long)(val); \ 85 | __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ 86 | : "=r" (__v) : "rK" (__v)); \ 87 | __v; \ 88 | }) 89 | 90 | #define csr_read(csr) \ 91 | ({ \ 92 | register unsigned long __v; \ 93 | __asm__ __volatile__ ("csrr %0, " #csr \ 94 | : "=r" (__v)); \ 95 | __v; \ 96 | }) 97 | 98 | #define csr_write(csr, val) \ 99 | { \ 100 | unsigned long __v = (unsigned long)(val); \ 101 | __asm__ __volatile__ ("csrw " #csr ", %0" \ 102 | : : "rK" (__v)); \ 103 | } 104 | 105 | #define csr_read_set(csr, val) \ 106 | ({ \ 107 | unsigned long __v = (unsigned long)(val); \ 108 | __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ 109 | : "=r" (__v) : "rK" (__v)); \ 110 | __v; \ 111 | }) 112 | 113 | #define csr_set(csr, val) \ 114 | { \ 115 | unsigned long __v = (unsigned long)(val); \ 116 | __asm__ __volatile__ ("csrs " #csr ", %0" \ 117 | : : "rK" (__v)); \ 118 | } 119 | 120 | #define csr_read_clear(csr, val) \ 121 | ({ \ 122 | unsigned long __v = (unsigned long)(val); \ 123 | __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ 124 | : "=r" (__v) : "rK" (__v)); \ 125 | __v; \ 126 | }) 127 | 128 | #define csr_clear(csr, val) \ 129 | { \ 130 | unsigned long __v = (unsigned long)(val); \ 131 | __asm__ __volatile__ ("csrc " #csr ", %0" \ 132 | : : "rK" (__v)); \ 133 | } 134 | 135 | 136 | 137 | #endif 138 | 139 | 140 | -------------------------------------------------------------------------------- /sw/sections.lds: -------------------------------------------------------------------------------- 1 | /* 2 | This is free and unencumbered software released into the public domain. 3 | 4 | Anyone is free to copy, modify, publish, use, compile, sell, or 5 | distribute this software, either in source code form or as a compiled 6 | binary, for any purpose, commercial or non-commercial, and by any 7 | means. 8 | */ 9 | 10 | SECTIONS { 11 | .memory : { 12 | . = 0x00000; 13 | start*(.text); 14 | *(.text); 15 | *(*); 16 | end = .; 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /sw/start.S: -------------------------------------------------------------------------------- 1 | .section .text 2 | .global start 3 | .global main 4 | 5 | .org 0x00000000 6 | start: 7 | /* set IRQ stack pointer */ 8 | /* Top 128 bytes are used to save all registers. */ 9 | li sp,(8*1024) - 128 10 | 11 | /* Save IRQ stack pointer in mscratch */ 12 | csrrw sp, mscratch, sp 13 | 14 | li sp,((8*1024) - 512) 15 | 16 | /* jump to main C code */ 17 | jal ra,main 18 | 19 | /* trap */ 20 | ebreak 21 | 22 | .org 0x00000020 23 | trapEntry: 24 | /* Set IRQ stack pointer */ 25 | csrrw sp, mscratch, sp 26 | 27 | /* Save full register state */ 28 | sw x1, 1*4(sp) 29 | /* Don't save SP: that's already stored in mscratch */ 30 | sw x3, 3*4(sp) 31 | sw x4, 4*4(sp) 32 | sw x5, 5*4(sp) 33 | sw x6, 6*4(sp) 34 | sw x7, 7*4(sp) 35 | sw x8, 8*4(sp) 36 | sw x9, 9*4(sp) 37 | sw x10, 10*4(sp) 38 | sw x11, 11*4(sp) 39 | sw x12, 12*4(sp) 40 | sw x13, 13*4(sp) 41 | sw x14, 14*4(sp) 42 | sw x15, 15*4(sp) 43 | sw x16, 16*4(sp) 44 | sw x17, 17*4(sp) 45 | sw x18, 18*4(sp) 46 | sw x19, 19*4(sp) 47 | sw x20, 20*4(sp) 48 | sw x21, 21*4(sp) 49 | sw x22, 22*4(sp) 50 | sw x23, 23*4(sp) 51 | sw x24, 24*4(sp) 52 | sw x25, 25*4(sp) 53 | sw x26, 26*4(sp) 54 | sw x27, 27*4(sp) 55 | sw x28, 28*4(sp) 56 | sw x29, 29*4(sp) 57 | sw x30, 30*4(sp) 58 | sw x31, 31*4(sp) 59 | 60 | /* Call C trap function */ 61 | call trap 62 | 63 | /* Restore full register state */ 64 | lw x1, 1*4(sp) 65 | lw x3, 3*4(sp) 66 | lw x4, 4*4(sp) 67 | lw x5, 5*4(sp) 68 | lw x6, 6*4(sp) 69 | lw x7, 7*4(sp) 70 | lw x8, 8*4(sp) 71 | lw x9, 9*4(sp) 72 | lw x10, 10*4(sp) 73 | lw x11, 11*4(sp) 74 | lw x12, 12*4(sp) 75 | lw x13, 13*4(sp) 76 | lw x14, 14*4(sp) 77 | lw x15, 15*4(sp) 78 | lw x16, 16*4(sp) 79 | lw x17, 17*4(sp) 80 | lw x18, 18*4(sp) 81 | lw x19, 19*4(sp) 82 | lw x20, 20*4(sp) 83 | lw x21, 21*4(sp) 84 | lw x22, 22*4(sp) 85 | lw x23, 23*4(sp) 86 | lw x24, 24*4(sp) 87 | lw x25, 25*4(sp) 88 | lw x26, 26*4(sp) 89 | lw x27, 27*4(sp) 90 | lw x28, 28*4(sp) 91 | lw x29, 29*4(sp) 92 | lw x30, 30*4(sp) 93 | lw x31, 31*4(sp) 94 | 95 | /* Restore stack pointer */ 96 | csrrw sp, mscratch, sp 97 | 98 | mret 99 | 100 | -------------------------------------------------------------------------------- /sw/timer.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "reg.h" 4 | #include "top_defines.h" 5 | #include "timer.h" 6 | 7 | void timer_prescaler_config(int prescaler_div) 8 | { 9 | REG_WR(TIMER_PRESCALER_LIMIT, prescaler_div); 10 | } 11 | 12 | void timer_a_config(int limit, int ticks_ena) 13 | { 14 | REG_WR(TIMER_A_LIMIT, limit); 15 | REG_WR_FIELD(TIMER_A_CONFIG, TICKS_ENABLE, ticks_ena); 16 | } 17 | 18 | void timer_b_config(int limit, int ticks_ena) 19 | { 20 | REG_WR(TIMER_B_LIMIT, limit); 21 | REG_WR_FIELD(TIMER_B_CONFIG, TICKS_ENABLE, ticks_ena); 22 | } 23 | 24 | uint32_t timer_irq_pending() 25 | { 26 | return REG_RD(TIMER_IRQ_STATUS); 27 | } 28 | 29 | 30 | void timer_irq_clr(int bits) 31 | { 32 | REG_WR(TIMER_IRQ_STATUS, bits); 33 | } 34 | 35 | 36 | void timer_irq_config(int mask) 37 | { 38 | REG_WR(TIMER_IRQ_MASK, mask); 39 | } 40 | 41 | -------------------------------------------------------------------------------- /sw/timer.h: -------------------------------------------------------------------------------- 1 | #ifndef TIMER_H 2 | #define TIMER_H 3 | 4 | #include 5 | 6 | void timer_prescaler_config(int prescaler_div); 7 | void timer_a_config(int limit, int ticks_ena); 8 | void timer_b_config(int limit, int ticks_ena); 9 | uint32_t timer_irq_pending(); 10 | void timer_irq_clr(int bits); 11 | void timer_irq_config(int mask); 12 | 13 | 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /sw/top_defines.h: -------------------------------------------------------------------------------- 1 | 2 | //============================================================ 3 | // Timer 4 | //============================================================ 5 | 6 | //== TIMER PRESCALER 7 | 8 | #define TIMER_PRESCALER_LIMIT_ADDR 0x00000000 9 | 10 | #define TIMER_PRESCALER_LIMIT_VALUE_FIELD_START 0 11 | #define TIMER_PRESCALER_LIMIT_VALUE_FIELD_LENGTH 16 12 | 13 | //== TIMER IRQ 14 | 15 | #define TIMER_IRQ_STATUS_ADDR 0x00000010 16 | 17 | #define TIMER_IRQ_STATUS_PENDING_FIELD_START 0 18 | #define TIMER_IRQ_STATUS_PENDING_FIELD_LENGTH 2 19 | 20 | #define TIMER_IRQ_MASK_ADDR 0x00000014 21 | 22 | #define TIMER_IRQ_MASK_VALUE_FIELD_START 0 23 | #define TIMER_IRQ_MASK_VALUE_FIELD_LENGTH 2 24 | 25 | //== TIMERS 26 | 27 | #define TIMER_A_CONFIG_ADDR 0x00000040 28 | 29 | #define TIMER_A_CONFIG_TICKS_ENABLE_FIELD_START 0 30 | #define TIMER_A_CONFIG_TICKS_ENABLE_FIELD_LENGTH 16 31 | 32 | #define TIMER_A_CONFIG_CLEARS_ENABLE_FIELD_START 16 33 | #define TIMER_A_CONFIG_CLEARS_ENABLE_FIELD_LENGTH 16 34 | 35 | #define TIMER_A_LIMIT_ADDR 0x00000044 36 | 37 | #define TIMER_A_LIMIT_VALUE_FIELD_START 0 38 | #define TIMER_A_LIMIT_VALUE_FIELD_LENGTH 32 39 | 40 | #define TIMER_A_VALUE_ADDR 0x00000048 41 | 42 | #define TIMER_A_VALUE_VALUE_FIELD_START 0 43 | #define TIMER_A_VALUE_VALUE_FIELD_LENGTH 32 44 | 45 | #define TIMER_B_CONFIG_ADDR 0x00000050 46 | 47 | #define TIMER_B_CONFIG_TICKS_ENABLE_FIELD_START 0 48 | #define TIMER_B_CONFIG_TICKS_ENABLE_FIELD_LENGTH 16 49 | 50 | #define TIMER_B_CONFIG_CLEARS_ENABLE_FIELD_START 16 51 | #define TIMER_B_CONFIG_CLEARS_ENABLE_FIELD_LENGTH 16 52 | 53 | #define TIMER_B_LIMIT_ADDR 0x00000054 54 | 55 | #define TIMER_B_LIMIT_VALUE_FIELD_START 0 56 | #define TIMER_B_LIMIT_VALUE_FIELD_LENGTH 32 57 | 58 | #define TIMER_B_VALUE_ADDR 0x00000058 59 | 60 | #define TIMER_B_VALUE_VALUE_FIELD_START 0 61 | #define TIMER_B_VALUE_VALUE_FIELD_LENGTH 32 62 | 63 | //============================================================ 64 | // LEDs 65 | //============================================================ 66 | 67 | #define LED_READ_ADDR 0x00010000 68 | #define LED_WRITE_ADDR 0x00010004 69 | #define LED_DIR_ADDR 0x00010008 70 | 71 | //============================================================ 72 | // UART 73 | //============================================================ 74 | // 75 | #define UART_RXTX_ADDR 0x00020000 76 | 77 | #define UART_RXTX_DATA_FIELD_START 0 78 | #define UART_RXTX_DATA_FIELD_LENGTH 8 79 | 80 | #define UART_RXTX_RX_HAS_DATA_FIELD_START 16 81 | #define UART_RXTX_RX_HAS_DATA_FIELD_LENGTH 0 82 | 83 | #define UART_STATUS_ADDR 0x00020004 84 | 85 | #define UART_STATUS_TX_AVAIL_FIELD_START 16 86 | #define UART_STATUS_TX_AVAIL_FIELD_LENGTH 8 87 | 88 | #define UART_CLK_DIV_ADDR 0x00020008 89 | 90 | #define UART_CLK_DIV_DIVIDER_FIELD_START 0 91 | #define UART_CLK_DIV_DIVIDER_FIELD_LENGTH 16 92 | 93 | #define UART_FRAME_ADDR 0x0002000c 94 | 95 | #define UART_FRAME_DATA_LENGTH_FIELD_START 0 96 | #define UART_FRAME_DATA_LENGTH_FIELD_LENGTH 3 97 | 98 | #define UART_FRAME_PARITY_FIELD_START 8 99 | #define UART_FRAME_PARITY_FIELD_LENGTH 2 100 | 101 | #define UART_FRAME_STOP_FIELD_START 16 102 | #define UART_FRAME_STOP_FIELD_LENGTH 1 103 | 104 | 105 | -------------------------------------------------------------------------------- /sw/type.h: -------------------------------------------------------------------------------- 1 | #ifndef TYPE_H 2 | #define TYPE_H 3 | 4 | #include 5 | 6 | typedef uint64_t u64; 7 | typedef int64_t s64; 8 | 9 | typedef uint32_t u32; 10 | typedef int32_t s32; 11 | 12 | typedef uint16_t u16; 13 | typedef int16_t s16; 14 | 15 | typedef uint8_t u8; 16 | typedef int8_t s8; 17 | 18 | 19 | #endif 20 | 21 | 22 | -------------------------------------------------------------------------------- /sw/uart.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "uart.h" 5 | 6 | #include "top_defines.h" 7 | #include "reg.h" 8 | 9 | void uart_init() 10 | { 11 | REG_WR(UART_FRAME, (7 << UART_FRAME_DATA_LENGTH_FIELD_START) 12 | | (0 << UART_FRAME_PARITY_FIELD_START) 13 | | (0 << UART_FRAME_STOP_FIELD_START)); 14 | 15 | } 16 | 17 | void uart_tx_char(char c) 18 | { 19 | if (c == '\n'){ 20 | REG_WR(UART_RXTX, '\r'); 21 | } 22 | REG_WR(UART_RXTX, c); 23 | } 24 | 25 | void uart_tx_str(char *str) 26 | { 27 | while(*str != 0){ 28 | uart_tx_char(*str); 29 | ++str; 30 | } 31 | } 32 | 33 | void uart_tx_byte(uint8_t b) 34 | { 35 | unsigned char hex[16] = "0123456789abcdef"; 36 | 37 | uart_tx_char(hex[b>>4]); 38 | uart_tx_char(hex[b&0xf]); 39 | } 40 | 41 | void uart_tx_short(uint16_t c) 42 | { 43 | unsigned char hex[16] = "0123456789abcdef"; 44 | 45 | uint8_t b; 46 | 47 | b = (uint8_t)((c>> 8) & 0xff); 48 | uart_tx_char(hex[b>>4]); 49 | uart_tx_char(hex[b&0xf]); 50 | 51 | b = (uint8_t)(c & 0xff); 52 | uart_tx_char(hex[b>>4]); 53 | uart_tx_char(hex[b&0xf]); 54 | 55 | } 56 | 57 | void uart_tx_wait_avail(int nr_chars) 58 | { 59 | while(REG_RD_FIELD(UART_STATUS, TX_AVAIL) < nr_chars); 60 | } 61 | 62 | int uart_rx_get_char() 63 | { 64 | uint32_t rxtx_data = REG_RD(UART_RXTX); 65 | 66 | int has_data = (rxtx_data >> UART_RXTX_RX_HAS_DATA_FIELD_START) & ((1<<(UART_RXTX_RX_HAS_DATA_FIELD_START))-1); 67 | 68 | if (has_data){ 69 | return (rxtx_data >> UART_RXTX_DATA_FIELD_START) & ((1<<(UART_RXTX_DATA_FIELD_LENGTH))-1); 70 | } 71 | else{ 72 | return -1; 73 | } 74 | } 75 | 76 | 77 | -------------------------------------------------------------------------------- /sw/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef UART_H 2 | #define UART_H 3 | 4 | 5 | void uart_init(); 6 | 7 | void uart_tx_char(char c); 8 | void uart_tx_str(char *str); 9 | void uart_tx_byte(uint8_t b); 10 | void uart_tx_short(uint16_t b); 11 | void uart_tx_wait_avail(int nr_chars); 12 | 13 | int uart_rx_get_char(); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /tb/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.hex 3 | tb 4 | *.vcd 5 | -------------------------------------------------------------------------------- /tb/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CREATE_MIF = ../misc/create_mif.rb 3 | HEX2BIN = ../misc/hex2bin.py 4 | SW_DIR = ../sw 5 | VERILOG_FILES = tb.v ../spinal/ExampleTop.sim.v 6 | 7 | ROM_FILES = ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol0.bin \ 8 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol1.bin \ 9 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol2.bin \ 10 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol3.bin 11 | 12 | all: tb $(ROM_FILES) 13 | ./tb 14 | 15 | tb: $(VERILOG_FILES) $(ROM_FILES) 16 | iverilog -o $@ $(VERILOG_FILES) 17 | 18 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol0.bin: ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol0.hex 19 | $(HEX2BIN) < $< > $@ 20 | 21 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol1.bin: ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol1.hex 22 | $(HEX2BIN) < $< > $@ 23 | 24 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol2.bin: ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol2.hex 25 | $(HEX2BIN) < $< > $@ 26 | 27 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol3.bin: ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol3.hex 28 | $(HEX2BIN) < $< > $@ 29 | 30 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol0.hex: $(SW_DIR)/progmem.bin 31 | $(CREATE_MIF) -f hex -d 1024 -w 8 -o 0 -i 4 $< > $@ 32 | 33 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol1.hex: $(SW_DIR)/progmem.bin 34 | $(CREATE_MIF) -f hex -d 1024 -w 8 -o 1 -i 4 $< > $@ 35 | 36 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol2.hex: $(SW_DIR)/progmem.bin 37 | $(CREATE_MIF) -f hex -d 1024 -w 8 -o 2 -i 4 $< > $@ 38 | 39 | ExampleTop.v_toplevel_cpu_u_cpu_u_cpu_ram_ram_symbol3.hex: $(SW_DIR)/progmem.bin 40 | $(CREATE_MIF) -f hex -d 1024 -w 8 -o 3 -i 4 $< > $@ 41 | 42 | waves: 43 | gtkwave waves.vcd waves.gtkw & 44 | 45 | lint: 46 | verilator --lint-only ../spinal/ExampleTop.sim.v 47 | 48 | clean: 49 | \rm -f *.bin *.hex tb *.vcd 50 | 51 | -------------------------------------------------------------------------------- /tb/tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/100ps 3 | 4 | `default_nettype none 5 | 6 | module tb; 7 | 8 | reg osc_clk; 9 | reg osc_reset_; 10 | 11 | initial begin 12 | // $dumpfile("waves.vcd"); 13 | // $dumpvars; 14 | 15 | osc_clk = 0; 16 | osc_reset_ = 1; 17 | 18 | repeat(20) 19 | @(posedge osc_clk); 20 | 21 | osc_reset_ = 0; 22 | 23 | repeat(100000) 24 | @(posedge osc_clk); 25 | 26 | $finish; 27 | end 28 | 29 | always 30 | #20 osc_clk = !osc_clk; 31 | 32 | wire led_red, led_green, led_blue; 33 | wire uart_txd, uart_rxd; 34 | 35 | ExampleTop u_dut( 36 | .osc_clk_in(osc_clk), 37 | 38 | .led_red(led_red), 39 | .led_green(led_green), 40 | .led_blue(led_blue), 41 | 42 | .button(1'b1), 43 | 44 | .uart_txd(uart_txd), 45 | .uart_rxd(uart_rxd) 46 | ); 47 | 48 | reg prev_led_red, prev_led_green, prev_led_blue; 49 | 50 | always @(posedge osc_clk) begin 51 | 52 | if (led_red != prev_led_red) begin 53 | $display("led_red: %d\n", led_red); 54 | end 55 | if (led_green != prev_led_green) begin 56 | $display("led_green: %d\n", led_green); 57 | end 58 | if (led_blue != prev_led_blue) begin 59 | $display("led_blue: %d\n", led_blue); 60 | end 61 | 62 | prev_led_red <= led_red; 63 | prev_led_green <= led_green; 64 | prev_led_blue <= led_blue; 65 | end 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /tb/waves.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.90 (w)1999-2018 BSI 3 | [*] Sat Apr 18 22:40:31 2020 4 | [*] 5 | [dumpfile] "/home/tom/projects/cpu_skeleton/tb/waves.vcd" 6 | [dumpfile_mtime] "Sat Apr 18 22:38:13 2020" 7 | [dumpfile_size] 200237530 8 | [savefile] "/home/tom/projects/cpu_skeleton/tb/waves.gtkw" 9 | [timestart] 0 10 | [size] 2973 1602 11 | [pos] -1 -1 12 | *-28.000000 15740000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb. 14 | [treeopen] tb.u_dut. 15 | [treeopen] tb.u_dut.cpu_u_cpu. 16 | [treeopen] tb.u_dut.cpu_u_cpu.u_cpu. 17 | [treeopen] tb.u_dut.cpu_u_cpu.u_cpu.cpu. 18 | [treeopen] tb.u_dut.cpu_u_cpu.u_uart. 19 | [treeopen] tb.u_dut.cpu_u_cpu.u_uart.uartCtrl_1_. 20 | [sst_width] 509 21 | [signals_width] 630 22 | [sst_expanded] 1 23 | [sst_vpaned_height] 931 24 | @200 25 | - 26 | @28 27 | tb.u_dut.led_red 28 | tb.u_dut.led_green 29 | tb.u_dut.led_blue 30 | @201 31 | - 32 | @28 33 | tb.u_dut.uart_rxd 34 | tb.u_dut.uart_txd 35 | [pattern_trace] 1 36 | [pattern_trace] 0 37 | -------------------------------------------------------------------------------- /verilator/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | obj_dir* 3 | tb 4 | tb_vcd 5 | tb_fst 6 | waves.vcd* 7 | waves.fst 8 | -------------------------------------------------------------------------------- /verilator/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | SRC_FILES = tb.v ../spinal/ExampleTop.sim.v main.cpp 4 | 5 | #VERILATOR_PREFIX = /opt/verilator/ 6 | VERILATOR_PREFIX = /usr/ 7 | 8 | # output directory 9 | VERILATOR_OPTIONS += --Mdir obj_dir 10 | # generate c++ code 11 | VERILATOR_OPTIONS += --cc 12 | # Don't bail on some Verilog warnings 13 | VERILATOR_OPTIONS += -Wno-fatal 14 | # Create Makefile to generate executable (instead of an archive) 15 | VERILATOR_OPTIONS += --exe 16 | # Kick off build automatically after Verilog code has been converted 17 | VERILATOR_OPTIONS += --build 18 | 19 | #CFLAGS = -CFLAGS "-g -O3" 20 | 21 | 22 | CXX = clang++ 23 | 24 | all: tb_vcd tb_fst 25 | 26 | #============================================================ 27 | # No tracing 28 | #============================================================ 29 | 30 | tb: verilator 31 | 32 | .PHONY: verilator 33 | verilator: 34 | rm -fr obj_dir 35 | verilator $(CFLAGS) $(VERILATOR_OPTIONS) --Mdir obj_dir $(SRC_FILES) 36 | cp ../spinal/*.bin . 37 | 38 | #============================================================ 39 | # VCD 40 | #============================================================ 41 | 42 | tb_vcd: verilator_vcd 43 | 44 | .PHONY: verilator_vcd 45 | verilator_vcd: 46 | rm -fr obj_dir_vcd 47 | verilator $(CFLAGS) $(VERILATOR_OPTIONS) --trace --Mdir obj_dir_vcd $(SRC_FILES) 48 | cp ../spinal/*.bin . 49 | 50 | #============================================================ 51 | # FST 52 | #============================================================ 53 | 54 | tb_fst: verilator_fst 55 | 56 | .PHONY: verilator_fst 57 | verilator_fst: 58 | rm -fr obj_dir_fst 59 | verilator $(CFLAGS) $(VERILATOR_OPTIONS) --trace-fst --Mdir obj_dir_fst $(SRC_FILES) 60 | cp ../spinal/*.bin . 61 | 62 | clean: 63 | \rm -fr *.bin obj_dir obj_dir_vcd obj_dir_fst tb 64 | -------------------------------------------------------------------------------- /verilator/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include "Vtb.h" 3 | 4 | #if VM_TRACE_VCD==1 5 | #include "verilated_vcd_c.h" 6 | #endif 7 | 8 | #if VM_TRACE_FST==1 9 | #include "verilated_fst_c.h" 10 | #endif 11 | 12 | #include "verilated.h" 13 | 14 | int main(int argc, char **argv) 15 | { 16 | Verilated::commandArgs(argc, argv); 17 | 18 | int nr_cycles = 1000000; 19 | if (argc ==2) 20 | nr_cycles = atoi(argv[1]); 21 | 22 | Vtb *tb = new Vtb; 23 | #if VM_TRACE_VCD==1 24 | VerilatedVcdC *trace; 25 | #endif 26 | #if VM_TRACE_FST==1 27 | VerilatedFstC *trace; 28 | #endif 29 | 30 | #if VM_TRACE_VCD==1 || VM_TRACE_FST==1 31 | Verilated::traceEverOn(true); 32 | #endif 33 | 34 | #if VM_TRACE_VCD==1 35 | trace = new VerilatedVcdC; 36 | tb->trace(trace, 99); 37 | trace->open("waves.vcd"); 38 | #endif 39 | 40 | #if VM_TRACE_FST==1 41 | trace = new VerilatedFstC; 42 | tb->trace(trace, 99); 43 | trace->open("waves.fst"); 44 | #endif 45 | 46 | for(int i=0;iosc_clk = 1; 48 | tb->eval(); 49 | #if VM_TRACE_VCD==1 || VM_TRACE_FST==1 50 | trace->dump(i*2); 51 | #endif 52 | 53 | tb->osc_clk = 0; 54 | tb->eval(); 55 | 56 | #if VM_TRACE_VCD==1 || VM_TRACE_FST==1 57 | trace->dump(i*2+1); 58 | #endif 59 | 60 | } 61 | 62 | #if defined(VM_TRACE_VCD) || defined(VM_TRACE_FST) 63 | trace->flush(); 64 | trace->close(); 65 | #endif 66 | 67 | exit(EXIT_SUCCESS); 68 | } 69 | 70 | -------------------------------------------------------------------------------- /verilator/tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/100ps 3 | 4 | `default_nettype none 5 | 6 | module tb(input osc_clk); 7 | 8 | reg osc_reset_ = 1'b0; 9 | 10 | always @(posedge osc_clk) begin 11 | osc_reset_ <= 1'b1; 12 | end 13 | 14 | wire led_red, led_green, led_blue; 15 | wire uart_txd, uart_rxd; 16 | 17 | ExampleTop u_dut( 18 | .osc_clk_in(osc_clk), 19 | 20 | .led_red(led_red), 21 | .led_green(led_green), 22 | .led_blue(led_blue), 23 | 24 | .button(1'b1), 25 | 26 | .uart_txd(uart_txd), 27 | .uart_rxd(uart_rxd) 28 | ); 29 | 30 | reg prev_led_red, prev_led_green, prev_led_blue; 31 | 32 | always @(posedge osc_clk) begin 33 | 34 | if (led_red != prev_led_red) begin 35 | $display("led_red: %d\n", led_red); 36 | end 37 | if (led_green != prev_led_green) begin 38 | $display("led_green: %d\n", led_green); 39 | end 40 | if (led_blue != prev_led_blue) begin 41 | $display("led_blue: %d\n", led_blue); 42 | end 43 | 44 | prev_led_red <= led_red; 45 | prev_led_green <= led_green; 46 | prev_led_blue <= led_blue; 47 | end 48 | 49 | 50 | endmodule 51 | --------------------------------------------------------------------------------