├── README.md ├── altera_models ├── pll.ppf ├── pll.qip ├── pll.v ├── pll_bb.v └── pll_inst.v ├── pics ├── FPGA_VDD_CORE_change.png ├── shift_reg_toggle_off.png └── shift_reg_toggle_on.png ├── quartus ├── sidechan.qpf └── sidechan.qsf └── src └── top.v /README.md: -------------------------------------------------------------------------------- 1 | 2 | # Side Channel Communication Test 3 | 4 | Checks the impact of FPGA toggle activity on the speed of a free-running ring oscillator 5 | in that same FPGA. 6 | 7 | I'm using an Intel Cyclone II EP2C5T144 development board for this. 8 | 9 | The case here is extreme in that 3000 FFs of a shift register of the FPGA or continuously 10 | toggling... or not. 11 | 12 | That said: since 50% of the FFs of the shift register are going 0 to 1 and the other 50% are 13 | going 1 to 0, the load on the power supply is the same for each clock cycle. 14 | 15 | A more extreme case would be *all* 3000 FFs toggling 0 or 1 in the same clock cycle. 16 | 17 | Pressing the button on the dev board will stop the toggling. 18 | 19 | The output of the ring oscillator is divided by 32, sent to a GPIO and recorded with a Saleae Logic 16. 20 | 21 | Results: 22 | 23 | When the shift register is toggling, the ring oscillator divided by 32 runs at 5.3MHz. 24 | 25 | ![Shift Register Toggling](./pics/shift_reg_toggle_on.png) 26 | 27 | When the shift register is idle, the clock raises to 5.8MHz. 28 | 29 | ![Shift Register Idle](./pics/shift_reg_toggle_off.png) 30 | 31 | The change in clock frequency happens in less than 6us, so it's almost certainly related to 32 | a changing in VDD Core. When the shift register is toggling, VDD core is 1.15V. It's 1.16V when idle. 33 | 34 | ![VDD Core change](./pics/FPGA_VDD_CORE_change.png) 35 | 36 | The EP2C5 FPGA has room for 4608 FFs, but when I increase the shift register from 3000 to 4000 FFs, 37 | my dev board resets after a few seconds. The power regulator on the board is burning hot. 38 | 39 | Meanwhile, the FPGA itself goes to ~53C when it stays toggling. 40 | 41 | 42 | -------------------------------------------------------------------------------- /altera_models/pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altera_models/pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] 7 | -------------------------------------------------------------------------------- /altera_models/pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module pll ( 40 | areset, 41 | inclk0, 42 | c0, 43 | locked); 44 | 45 | input areset; 46 | input inclk0; 47 | output c0; 48 | output locked; 49 | `ifndef ALTERA_RESERVED_QIS 50 | // synopsys translate_off 51 | `endif 52 | tri0 areset; 53 | `ifndef ALTERA_RESERVED_QIS 54 | // synopsys translate_on 55 | `endif 56 | 57 | wire sub_wire0; 58 | wire [5:0] sub_wire1; 59 | wire [0:0] sub_wire5 = 1'h0; 60 | wire locked = sub_wire0; 61 | wire [0:0] sub_wire2 = sub_wire1[0:0]; 62 | wire c0 = sub_wire2; 63 | wire sub_wire3 = inclk0; 64 | wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; 65 | 66 | altpll altpll_component ( 67 | .areset (areset), 68 | .inclk (sub_wire4), 69 | .locked (sub_wire0), 70 | .clk (sub_wire1), 71 | .activeclock (), 72 | .clkbad (), 73 | .clkena ({6{1'b1}}), 74 | .clkloss (), 75 | .clkswitch (1'b0), 76 | .configupdate (1'b0), 77 | .enable0 (), 78 | .enable1 (), 79 | .extclk (), 80 | .extclkena ({4{1'b1}}), 81 | .fbin (1'b1), 82 | .fbmimicbidir (), 83 | .fbout (), 84 | .fref (), 85 | .icdrclk (), 86 | .pfdena (1'b1), 87 | .phasecounterselect ({4{1'b1}}), 88 | .phasedone (), 89 | .phasestep (1'b1), 90 | .phaseupdown (1'b1), 91 | .pllena (1'b1), 92 | .scanaclr (1'b0), 93 | .scanclk (1'b0), 94 | .scanclkena (1'b1), 95 | .scandata (1'b0), 96 | .scandataout (), 97 | .scandone (), 98 | .scanread (1'b0), 99 | .scanwrite (1'b0), 100 | .sclkout0 (), 101 | .sclkout1 (), 102 | .vcooverrange (), 103 | .vcounderrange ()); 104 | defparam 105 | altpll_component.clk0_divide_by = 1, 106 | altpll_component.clk0_duty_cycle = 50, 107 | altpll_component.clk0_multiply_by = 8, 108 | altpll_component.clk0_phase_shift = "0", 109 | altpll_component.compensate_clock = "CLK0", 110 | altpll_component.gate_lock_signal = "NO", 111 | altpll_component.inclk0_input_frequency = 20000, 112 | altpll_component.intended_device_family = "Cyclone II", 113 | altpll_component.invalid_lock_multiplier = 5, 114 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 115 | altpll_component.lpm_type = "altpll", 116 | altpll_component.operation_mode = "NORMAL", 117 | altpll_component.port_activeclock = "PORT_UNUSED", 118 | altpll_component.port_areset = "PORT_USED", 119 | altpll_component.port_clkbad0 = "PORT_UNUSED", 120 | altpll_component.port_clkbad1 = "PORT_UNUSED", 121 | altpll_component.port_clkloss = "PORT_UNUSED", 122 | altpll_component.port_clkswitch = "PORT_UNUSED", 123 | altpll_component.port_configupdate = "PORT_UNUSED", 124 | altpll_component.port_fbin = "PORT_UNUSED", 125 | altpll_component.port_inclk0 = "PORT_USED", 126 | altpll_component.port_inclk1 = "PORT_UNUSED", 127 | altpll_component.port_locked = "PORT_USED", 128 | altpll_component.port_pfdena = "PORT_UNUSED", 129 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 130 | altpll_component.port_phasedone = "PORT_UNUSED", 131 | altpll_component.port_phasestep = "PORT_UNUSED", 132 | altpll_component.port_phaseupdown = "PORT_UNUSED", 133 | altpll_component.port_pllena = "PORT_UNUSED", 134 | altpll_component.port_scanaclr = "PORT_UNUSED", 135 | altpll_component.port_scanclk = "PORT_UNUSED", 136 | altpll_component.port_scanclkena = "PORT_UNUSED", 137 | altpll_component.port_scandata = "PORT_UNUSED", 138 | altpll_component.port_scandataout = "PORT_UNUSED", 139 | altpll_component.port_scandone = "PORT_UNUSED", 140 | altpll_component.port_scanread = "PORT_UNUSED", 141 | altpll_component.port_scanwrite = "PORT_UNUSED", 142 | altpll_component.port_clk0 = "PORT_USED", 143 | altpll_component.port_clk1 = "PORT_UNUSED", 144 | altpll_component.port_clk2 = "PORT_UNUSED", 145 | altpll_component.port_clk3 = "PORT_UNUSED", 146 | altpll_component.port_clk4 = "PORT_UNUSED", 147 | altpll_component.port_clk5 = "PORT_UNUSED", 148 | altpll_component.port_clkena0 = "PORT_UNUSED", 149 | altpll_component.port_clkena1 = "PORT_UNUSED", 150 | altpll_component.port_clkena2 = "PORT_UNUSED", 151 | altpll_component.port_clkena3 = "PORT_UNUSED", 152 | altpll_component.port_clkena4 = "PORT_UNUSED", 153 | altpll_component.port_clkena5 = "PORT_UNUSED", 154 | altpll_component.port_extclk0 = "PORT_UNUSED", 155 | altpll_component.port_extclk1 = "PORT_UNUSED", 156 | altpll_component.port_extclk2 = "PORT_UNUSED", 157 | altpll_component.port_extclk3 = "PORT_UNUSED", 158 | altpll_component.valid_lock_multiplier = 1; 159 | 160 | 161 | endmodule 162 | 163 | // ============================================================ 164 | // CNX file retrieval info 165 | // ============================================================ 166 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 168 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" 169 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 170 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 171 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 172 | // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" 173 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 174 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 175 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 176 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" 177 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 178 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 179 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 180 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 181 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 182 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" 183 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 184 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 185 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "400.000000" 186 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 187 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 188 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 189 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" 190 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 191 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 192 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 193 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 194 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 195 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 196 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 197 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 198 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 199 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 200 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 201 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" 202 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 203 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 204 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 205 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 206 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 207 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 208 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 209 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 210 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "400.00000000" 211 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 212 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 213 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" 214 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 215 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 216 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 217 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 218 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 219 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" 220 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 221 | // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" 222 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 223 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 224 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 225 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 226 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 227 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 228 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 229 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 230 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 231 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" 232 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 233 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 234 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 235 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 236 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 237 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 238 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 239 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 240 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 241 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 242 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 243 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 244 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 245 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 246 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 247 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 248 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 249 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 250 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 251 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" 252 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 253 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 254 | // Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" 255 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 256 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 257 | // Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" 258 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 259 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 260 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 261 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" 262 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 263 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 264 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 265 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 266 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 267 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 268 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 269 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 270 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" 271 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 272 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 273 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 274 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 275 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 276 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 277 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 278 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 279 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 280 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 281 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 282 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 283 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 284 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 285 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 286 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 287 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 288 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 289 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 290 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 291 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 292 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 293 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 294 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 295 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 296 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 297 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 298 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 299 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 300 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 301 | // Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" 302 | // Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" 303 | // Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" 304 | // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" 305 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 306 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 307 | // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" 308 | // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 309 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 310 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 311 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 312 | // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 313 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 314 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 315 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 316 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 317 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 318 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE 319 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE 320 | // Retrieval info: LIB_FILE: altera_mf 321 | // Retrieval info: CBX_MODULE_PREFIX: ON 322 | -------------------------------------------------------------------------------- /altera_models/pll_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module pll ( 35 | areset, 36 | inclk0, 37 | c0, 38 | locked); 39 | 40 | input areset; 41 | input inclk0; 42 | output c0; 43 | output locked; 44 | `ifndef ALTERA_RESERVED_QIS 45 | // synopsys translate_off 46 | `endif 47 | tri0 areset; 48 | `ifndef ALTERA_RESERVED_QIS 49 | // synopsys translate_on 50 | `endif 51 | 52 | endmodule 53 | 54 | // ============================================================ 55 | // CNX file retrieval info 56 | // ============================================================ 57 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 58 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 59 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" 60 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 61 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 62 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 63 | // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" 64 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 65 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 66 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 67 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" 68 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 69 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 70 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 71 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 72 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 73 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" 74 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 75 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 76 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "400.000000" 77 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 78 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 79 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 80 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" 81 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 82 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 83 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 84 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 85 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 86 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 87 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 88 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 89 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 90 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 91 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 92 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" 93 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 94 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 95 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 96 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 97 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 98 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 99 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 100 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 101 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "400.00000000" 102 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 103 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 104 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" 105 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 106 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 107 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 108 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 109 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 110 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" 111 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 112 | // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" 113 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 114 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 115 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 116 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 117 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 118 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 119 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 120 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 121 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 122 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" 123 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 124 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 125 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 126 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 127 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 128 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 129 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 130 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 131 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 132 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 133 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 134 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 135 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 136 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 137 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 138 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 139 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 140 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 141 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 142 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" 143 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 144 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 145 | // Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" 146 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 147 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" 148 | // Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" 149 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 150 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 151 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 152 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" 153 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 154 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 155 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 156 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 157 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 158 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 159 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 160 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 161 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" 162 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 163 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 164 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 165 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 166 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 167 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 168 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 169 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 170 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 171 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 172 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 173 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 174 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 175 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 176 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 177 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 178 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 179 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 180 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 181 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 182 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 183 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 184 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 185 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 186 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 187 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 188 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 189 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 190 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 191 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 192 | // Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" 193 | // Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" 194 | // Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" 195 | // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" 196 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 197 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 198 | // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" 199 | // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 200 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 201 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 202 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 203 | // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 204 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 205 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 206 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 207 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 208 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 209 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE 210 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE 211 | // Retrieval info: LIB_FILE: altera_mf 212 | // Retrieval info: CBX_MODULE_PREFIX: ON 213 | -------------------------------------------------------------------------------- /altera_models/pll_inst.v: -------------------------------------------------------------------------------- 1 | pll pll_inst ( 2 | .areset ( areset_sig ), 3 | .inclk0 ( inclk0_sig ), 4 | .c0 ( c0_sig ), 5 | .locked ( locked_sig ) 6 | ); 7 | -------------------------------------------------------------------------------- /pics/FPGA_VDD_CORE_change.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/sidechan/3e70ffd34a6699546cf5877621207f6c94903d1f/pics/FPGA_VDD_CORE_change.png -------------------------------------------------------------------------------- /pics/shift_reg_toggle_off.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/sidechan/3e70ffd34a6699546cf5877621207f6c94903d1f/pics/shift_reg_toggle_off.png -------------------------------------------------------------------------------- /pics/shift_reg_toggle_on.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tomverbeure/sidechan/3e70ffd34a6699546cf5877621207f6c94903d1f/pics/shift_reg_toggle_on.png -------------------------------------------------------------------------------- /quartus/sidechan.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 22:49:00 August 08, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "22:49:00 August 08, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "sidechan" 31 | -------------------------------------------------------------------------------- /quartus/sidechan.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 22:49:00 August 08, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # sidechan_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone II" 40 | set_global_assignment -name DEVICE EP2C5T144C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY top 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:49:00 AUGUST 08, 2020" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" 51 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation 52 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 53 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 54 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 55 | set_global_assignment -name VERILOG_FILE ../src/top.v 56 | set_global_assignment -name QIP_FILE ../altera_models/pll.qip 57 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF 58 | set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF 59 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 60 | set_location_assignment PIN_17 -to clk50 61 | set_location_assignment PIN_144 -to button 62 | set_location_assignment PIN_104 -to primary_out 63 | set_location_assignment PIN_101 -to ring_osc_out 64 | set_global_assignment -name CDF_FILE output_files/Chain2.cdf 65 | set_location_assignment PIN_3 -to led0 66 | set_location_assignment PIN_7 -to led1 67 | set_location_assignment PIN_9 -to led2 68 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /src/top.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // Divide input clock by 32 with cascaded FFs 4 | module clk_div32(input clk_in, output clk_out); 5 | 6 | reg [4:0] cntr; 7 | 8 | always @(posedge clk_in) 9 | cntr[0] <= !cntr[0]; 10 | 11 | always @(posedge cntr[0]) 12 | cntr[1] <= !cntr[1]; 13 | 14 | always @(posedge cntr[1]) 15 | cntr[2] <= !cntr[2]; 16 | 17 | always @(posedge cntr[2]) 18 | cntr[3] <= !cntr[3]; 19 | 20 | always @(posedge cntr[3]) 21 | cntr[4] <= !cntr[4]; 22 | 23 | assign clk_out = cntr[4]; 24 | 25 | endmodule 26 | 27 | module top( 28 | input clk50, 29 | input button, 30 | output primary_out, 31 | output ring_osc_out, 32 | output led0, 33 | output led1, 34 | output led2 35 | ); 36 | 37 | // ============================================================ 38 | // Design one: shift register that toggles all the time (or not) 39 | // ============================================================ 40 | 41 | localparam nr_ffs = 3000; 42 | 43 | reg [nr_ffs-1:0] shift_reg; 44 | 45 | wire main_clk; 46 | 47 | pll pll_inst ( 48 | .areset (1'b0), 49 | .inclk0 (clk50), 50 | .c0 (main_clk), 51 | .locked () 52 | ); 53 | 54 | // Shift toggle pattern when button = 1, otherwise shift static value. 55 | always @(posedge main_clk) begin 56 | shift_reg[nr_ffs-1:1] <= shift_reg[nr_ffs-2:0]; 57 | shift_reg[0] <= shift_reg[0] ^ button; 58 | end 59 | 60 | wire primary_clk; 61 | clk_div32 primary_div(.clk_in(shift_reg[nr_ffs-1]), .clk_out(primary_clk)); 62 | 63 | reg [21:0] cntr; 64 | 65 | always @(posedge primary_clk) 66 | cntr <= cntr + 1'b1; 67 | 68 | assign led0 = cntr[21]; 69 | assign primary_out = primary_clk; 70 | 71 | // ============================================================ 72 | // Design two: free-running ring oscillator 73 | // ============================================================ 74 | 75 | wire [6:0] ring; 76 | 77 | lcell cell0 (.in(!ring[6]), .out(ring[0])); 78 | lcell cell1 (.in(!ring[0]), .out(ring[1])); 79 | lcell cell2 (.in(!ring[1]), .out(ring[2])); 80 | lcell cell3 (.in(!ring[2]), .out(ring[3])); 81 | lcell cell4 (.in(!ring[3]), .out(ring[4])); 82 | lcell cell5 (.in(!ring[4]), .out(ring[5])); 83 | lcell cell6 (.in(!ring[5]), .out(ring[6])); 84 | 85 | wire secondary_clk; 86 | clk_div32 secondary_div(.clk_in(ring[6]), .clk_out(secondary_clk)); 87 | 88 | reg [21:0] ring_cntr; 89 | 90 | always @(posedge secondary_clk) begin 91 | ring_cntr <= ring_cntr + 1'b1; 92 | end 93 | 94 | assign ring_osc_out = secondary_clk; 95 | 96 | assign led1 = ring_cntr[21]; 97 | assign led2 = 1'b1; 98 | 99 | endmodule 100 | --------------------------------------------------------------------------------