├── .coveragerc ├── .flake8 ├── .github └── workflows │ └── pythonpackage.yml ├── .gitignore ├── .gitlab-ci.yml ├── .readthedocs.yml ├── .travis.yml ├── CHANGELOG ├── CONTRIBUTING.md ├── LICENSE ├── Makefile ├── PortingSV2Python.md ├── README.md ├── __init__.py ├── bin ├── fixer.py ├── fixes │ └── fix_func_comments.py ├── function_signatures.py ├── status.pl ├── sv2py.pl └── test_file.py ├── ci ├── check_errors.sh ├── install_ghdl.sh ├── install_iverilog.sh ├── install_verilator.sh └── requirements.txt ├── devscripts ├── create_release.pl ├── create_release.py └── dev_requirements.txt ├── docs ├── Makefile ├── requirements.txt └── source │ ├── _static │ └── overflow_fix.css │ ├── base │ ├── uvm_barrier.rst │ ├── uvm_bottomup_phase.rst │ ├── uvm_callback.rst │ ├── uvm_cmdline_processor.rst │ ├── uvm_common_phases.rst │ ├── uvm_comparer.rst │ ├── uvm_component.rst │ ├── uvm_config_db.rst │ ├── uvm_coreservice.rst │ ├── uvm_domain.rst │ ├── uvm_event.rst │ ├── uvm_event_callback.rst │ ├── uvm_factory.rst │ ├── uvm_globals.rst │ ├── uvm_heartbeat.rst │ ├── uvm_links.rst │ ├── uvm_misc.rst │ ├── uvm_object.rst │ ├── uvm_object_globals.rst │ ├── uvm_objection.rst │ ├── uvm_packer.rst │ ├── uvm_phase.rst │ ├── uvm_pool.rst │ ├── uvm_port_base.rst │ ├── uvm_printer.rst │ ├── uvm_queue.rst │ ├── uvm_recorder.rst │ ├── uvm_registry.rst │ ├── uvm_report_catcher.rst │ ├── uvm_report_handler.rst │ ├── uvm_report_message.rst │ ├── uvm_report_object.rst │ ├── uvm_report_server.rst │ ├── uvm_resource.rst │ ├── uvm_resource_db.rst │ ├── uvm_root.rst │ ├── uvm_runtime_phases.rst │ ├── uvm_task_phase.rst │ ├── uvm_topdown_phase.rst │ ├── uvm_tr_database.rst │ ├── uvm_tr_stream.rst │ ├── uvm_transaction.rst │ └── uvm_traversal.rst │ ├── comps │ ├── uvm_agent.rst │ ├── uvm_algorithmic_comparator.rst │ ├── uvm_driver.rst │ ├── uvm_env.rst │ ├── uvm_in_order_comparator.rst │ ├── uvm_monitor.rst │ ├── uvm_pair.rst │ ├── uvm_policies.rst │ ├── uvm_push_driver.rst │ ├── uvm_random_stimulus.rst │ ├── uvm_scoreboard.rst │ ├── uvm_subscriber.rst │ └── uvm_test.rst │ ├── conf.py │ ├── dap │ ├── uvm_get_to_lock_dap.rst │ ├── uvm_set_before_get_dap.rst │ ├── uvm_set_get_dap_base.rst │ └── uvm_simple_lock_dap.rst │ ├── dpi │ └── uvm_hdl.rst │ ├── fig │ ├── 01_typical_uvm_tb_architecture.png │ ├── 02_uvm_agent.png │ ├── 03_uvm_class_diagram.png │ ├── 04_single_producer_consumer.png │ ├── 05_consumer_gets_from_producer.png │ ├── 06_using_uvm_tlm_fifo.png │ ├── 07_hierarchy_in_tlm.png │ ├── 08_analysis_communication.png │ ├── 09_socket_connections.png │ ├── 10_simplified_transaction_level_testbench.png │ ├── 11_highly_reusable_verification_component_agent.png │ ├── 12_sequencer_driver_interaction.png │ ├── 13_agent.png │ ├── 14_typical_uvm_environment_architecture.png │ ├── 15_sequence_item_flow_in_pull_mode.png │ ├── 16_subsequence_flow.png │ ├── 17_verification_environment_class_diagram.png │ ├── 18_standard_configuration_fields_and_locations.png │ ├── 19_virtual_sequence.png │ ├── 20_ubus_demo_environment.png │ ├── 21_register_model_in_uvm_environment.png │ ├── 22_register_model_class_collaboration.png │ ├── 23_design_structure_of_registers_fields_and_memories.png │ ├── 24_register_model_structure.png │ ├── 25_128_bit_register.png │ ├── 26_composite_register_structure.png │ ├── 27_register_sequence_running_directly_on_a_bus_sequencer.png │ ├── 28_register_sequence_running_as_a_virtual_sequence.png │ ├── 29_register_sequence_running_on_a_layered_sequencer.png │ ├── 30_integration_with_a_bus_monitor.png │ ├── 31_hierarchy_created_with_set_type_override_applied.png │ ├── 32_hierarchy_created_with_both_overrides_applied.png │ ├── 38_layering_drivers.png │ ├── 39_complex_arbitrary_protocol_stack.png │ ├── 40_ubus_example_architecture.png │ ├── 41_testbench_derived_from_uvm_env.png │ ├── 42_instance_of_ubus_env.png │ ├── 43_instance_of_ubus_master_agent.png │ ├── 44_instance_of_ubus_master_sequencer.png │ ├── 45_instance_of_ubus_master_driver.png │ ├── 46_instance_of_ubus_master_monitor.png │ ├── 47_example_write_waveform.png │ └── 48_example_read_waveform.png │ ├── index.rst │ ├── macros │ ├── uvm_callback_defines.rst │ ├── uvm_global_defines.rst │ ├── uvm_message_defines.rst │ ├── uvm_object_defines.rst │ ├── uvm_reg_defines.rst │ ├── uvm_sequence_defines.rst │ ├── uvm_tlm_defines.rst │ └── uvm_version_defines.rst │ ├── overviews │ ├── base.rst │ ├── cmdlineproc.rst │ ├── comparators.rst │ ├── components.rst │ ├── config_and_res.rst │ ├── containers.rst │ ├── dap.rst │ ├── factory.rst │ ├── globals.rst │ ├── intro.rst │ ├── macros.rst │ ├── phasing.rst │ ├── policies.rst │ ├── recording.rst │ ├── registers.rst │ ├── relnotes.rst │ ├── reporting.rst │ ├── sequencers.rst │ ├── sequences.rst │ ├── synchro.rst │ ├── test_phasing.rst │ ├── tlm1.rst │ ├── tlm2.rst │ └── tlm_ifs_and_ports.rst │ ├── reg │ ├── sequences │ │ ├── uvm_mem_access_seq.rst │ │ ├── uvm_mem_walk_seq.rst │ │ ├── uvm_reg_access_seq.rst │ │ ├── uvm_reg_bit_bash_seq.rst │ │ ├── uvm_reg_hw_reset_seq.rst │ │ ├── uvm_reg_mem_built_in_seq.rst │ │ ├── uvm_reg_mem_hdl_paths_seq.rst │ │ └── uvm_reg_mem_shared_access_seq.rst │ ├── uvm_mem.rst │ ├── uvm_mem_mam.rst │ ├── uvm_reg.rst │ ├── uvm_reg_adapter.rst │ ├── uvm_reg_backdoor.rst │ ├── uvm_reg_block.rst │ ├── uvm_reg_cbs.rst │ ├── uvm_reg_field.rst │ ├── uvm_reg_fifo.rst │ ├── uvm_reg_file.rst │ ├── uvm_reg_indirect.rst │ ├── uvm_reg_item.rst │ ├── uvm_reg_map.rst │ ├── uvm_reg_model.rst │ ├── uvm_reg_predictor.rst │ ├── uvm_reg_sequence.rst │ ├── uvm_vreg.rst │ └── uvm_vreg_field.rst │ ├── seq │ ├── uvm_push_sequencer.rst │ ├── uvm_sequence.rst │ ├── uvm_sequence_base.rst │ ├── uvm_sequence_item.rst │ ├── uvm_sequence_library.rst │ ├── uvm_sequencer.rst │ ├── uvm_sequencer_base.rst │ └── uvm_sequencer_param_base.rst │ ├── tlm1 │ ├── uvm_analysis_port.rst │ ├── uvm_exports.rst │ ├── uvm_imps.rst │ ├── uvm_ports.rst │ ├── uvm_sqr_connections.rst │ ├── uvm_sqr_ifs.rst │ ├── uvm_tlm_fifo_base.rst │ ├── uvm_tlm_fifos.rst │ ├── uvm_tlm_ifs.rst │ └── uvm_tlm_req_rsp.rst │ ├── tlm2 │ ├── uvm_tlm2_defines.rst │ ├── uvm_tlm2_exports.rst │ ├── uvm_tlm2_generic_payload.rst │ ├── uvm_tlm2_ifs.rst │ ├── uvm_tlm2_imps.rst │ ├── uvm_tlm2_ports.rst │ ├── uvm_tlm2_sockets.rst │ ├── uvm_tlm2_sockets_base.rst │ └── uvm_tlm2_time.rst │ ├── uvm_1.2_class_reference.rst │ └── uvm_users_guide_1.2.rst ├── gen_ctags.sh ├── pyproject.toml ├── pyrightconfig.json ├── pytype.cfg ├── setup.cfg ├── setup.py ├── src └── uvm │ ├── __init__.py │ ├── base │ ├── __init__.py │ ├── sv.py │ ├── uvm_barrier.py │ ├── uvm_bottomup_phase.py │ ├── uvm_callback.py │ ├── uvm_cmdline_processor.py │ ├── uvm_common_phases.py │ ├── uvm_comparer.py │ ├── uvm_component.py │ ├── uvm_config_db.py │ ├── uvm_coreservice.py │ ├── uvm_debug.py │ ├── uvm_domain.py │ ├── uvm_event.py │ ├── uvm_exceptions.py │ ├── uvm_factory.py │ ├── uvm_global_vars.py │ ├── uvm_globals.py │ ├── uvm_links.py │ ├── uvm_mailbox.py │ ├── uvm_misc.py │ ├── uvm_object.py │ ├── uvm_object_globals.py │ ├── uvm_objection.py │ ├── uvm_packer.py │ ├── uvm_phase.py │ ├── uvm_pool.py │ ├── uvm_port_base.py │ ├── uvm_printer.py │ ├── uvm_queue.py │ ├── uvm_recorder.py │ ├── uvm_registry.py │ ├── uvm_report_catcher.py │ ├── uvm_report_handler.py │ ├── uvm_report_message.py │ ├── uvm_report_object.py │ ├── uvm_report_server.py │ ├── uvm_resource.py │ ├── uvm_resource_db.py │ ├── uvm_root.py │ ├── uvm_runtime_phases.py │ ├── uvm_scheduler.py │ ├── uvm_scope_stack.py │ ├── uvm_server.py │ ├── uvm_spell_chkr.py │ ├── uvm_task_phase.py │ ├── uvm_topdown_phase.py │ ├── uvm_tr_database.py │ ├── uvm_tr_stream.py │ ├── uvm_transaction.py │ └── uvm_version.py │ ├── comps │ ├── __init__.py │ ├── uvm_agent.py │ ├── uvm_algorithmic_comparator.py │ ├── uvm_comps.py │ ├── uvm_driver.py │ ├── uvm_env.py │ ├── uvm_in_order_comparator.py │ ├── uvm_monitor.py │ ├── uvm_pair.py │ ├── uvm_policies.py │ ├── uvm_push_driver.py │ ├── uvm_random_stimulus.py │ ├── uvm_scoreboard.py │ ├── uvm_subscriber.py │ └── uvm_test.py │ ├── dap │ ├── __init__.py │ ├── uvm_dap.py │ ├── uvm_get_to_lock_dap.py │ ├── uvm_set_before_get_dap.py │ ├── uvm_set_get_dap_base.py │ └── uvm_simple_lock_dap.py │ ├── dpi │ ├── __init__.py │ └── uvm_hdl.py │ ├── macros │ ├── __init__.py │ ├── uvm_callback_defines.py │ ├── uvm_deprecated_defines.py │ ├── uvm_global_defines.py │ ├── uvm_message_defines.py │ ├── uvm_object_defines.py │ ├── uvm_phase_defines.py │ ├── uvm_printer_defines.py │ ├── uvm_reg_defines.py │ ├── uvm_sequence_defines.py │ ├── uvm_tlm_defines.py │ ├── uvm_undefineall.py │ └── uvm_version_defines.py │ ├── reg │ ├── __init__.py │ ├── sequences │ │ ├── __init__.py │ │ ├── uvm_mem_access_seq.py │ │ ├── uvm_mem_walk_seq.py │ │ ├── uvm_reg_access_seq.py │ │ ├── uvm_reg_bit_bash_seq.py │ │ ├── uvm_reg_hw_reset_seq.py │ │ ├── uvm_reg_mem_built_in_seq.py │ │ ├── uvm_reg_mem_hdl_paths_seq.py │ │ └── uvm_reg_mem_shared_access_seq.py │ ├── uvm_mem.py │ ├── uvm_mem_mam.py │ ├── uvm_reg.py │ ├── uvm_reg_adapter.py │ ├── uvm_reg_backdoor.py │ ├── uvm_reg_block.py │ ├── uvm_reg_cbs.py │ ├── uvm_reg_field.py │ ├── uvm_reg_fifo.py │ ├── uvm_reg_file.py │ ├── uvm_reg_indirect.py │ ├── uvm_reg_item.py │ ├── uvm_reg_map.py │ ├── uvm_reg_model.py │ ├── uvm_reg_predictor.py │ ├── uvm_reg_sequence.py │ ├── uvm_vreg.py │ └── uvm_vreg_field.py │ ├── seq │ ├── __init__.py │ ├── uvm_push_sequencer.py │ ├── uvm_seq.py │ ├── uvm_sequence.py │ ├── uvm_sequence_base.py │ ├── uvm_sequence_builtin.py │ ├── uvm_sequence_item.py │ ├── uvm_sequence_library.py │ ├── uvm_sequencer.py │ ├── uvm_sequencer_analysis_fifo.py │ ├── uvm_sequencer_base.py │ └── uvm_sequencer_param_base.py │ ├── tlm1 │ ├── __init__.py │ ├── uvm_analysis_port.py │ ├── uvm_exports.py │ ├── uvm_imps.py │ ├── uvm_ports.py │ ├── uvm_sqr_connections.py │ ├── uvm_sqr_ifs.py │ ├── uvm_tlm.py │ ├── uvm_tlm_fifo_base.py │ ├── uvm_tlm_fifos.py │ ├── uvm_tlm_ifs.py │ ├── uvm_tlm_imps.py │ └── uvm_tlm_req_rsp.py │ ├── tlm2 │ ├── __init__.py │ ├── uvm_tlm2.py │ ├── uvm_tlm2_defines.py │ ├── uvm_tlm2_exports.py │ ├── uvm_tlm2_generic_payload.py │ ├── uvm_tlm2_ifs.py │ ├── uvm_tlm2_imps.py │ ├── uvm_tlm2_ports.py │ ├── uvm_tlm2_sockets.py │ ├── uvm_tlm2_sockets_base.py │ ├── uvm_tlm2_time.py │ └── uvm_tlm_time.py │ ├── uvm_macros.py │ ├── uvm_pkg.py │ ├── uvm_unit.py │ └── version.py ├── test ├── .gitignore ├── Makefile ├── examples │ ├── integrated │ │ ├── Makefile │ │ ├── README.txt │ │ ├── apb │ │ │ ├── __init__.py │ │ │ ├── apb.sv │ │ │ ├── apb_agent.py │ │ │ ├── apb_agent.sv │ │ │ ├── apb_config.py │ │ │ ├── apb_config.sv │ │ │ ├── apb_if.py │ │ │ ├── apb_if.sv │ │ │ ├── apb_master.py │ │ │ ├── apb_master.sv │ │ │ ├── apb_monitor.py │ │ │ ├── apb_monitor.sv │ │ │ ├── apb_rw.py │ │ │ ├── apb_rw.sv │ │ │ ├── apb_sequencer.py │ │ │ └── apb_sequencer.sv │ │ ├── codec │ │ │ ├── Makefile │ │ │ ├── README.txt │ │ │ ├── __init__.py │ │ │ ├── apb2txrx.py │ │ │ ├── apb2txrx.svh │ │ │ ├── block_diagram.pdf │ │ │ ├── dut.sv │ │ │ ├── reg_model.py │ │ │ ├── reg_model.svh │ │ │ ├── sym_sb.py │ │ │ ├── sym_sb.svh │ │ │ ├── tb_env.py │ │ │ ├── tb_env.svh │ │ │ ├── tb_top.sv │ │ │ ├── test.sv │ │ │ ├── test_codec.py │ │ │ ├── testlib.py │ │ │ ├── testlib.svh │ │ │ └── vip │ │ │ │ ├── __init__.py │ │ │ │ ├── vip_agent.py │ │ │ │ ├── vip_agent.svh │ │ │ │ ├── vip_driver.py │ │ │ │ ├── vip_driver.svh │ │ │ │ ├── vip_if.py │ │ │ │ ├── vip_if.sv │ │ │ │ ├── vip_monitor.py │ │ │ │ ├── vip_monitor.svh │ │ │ │ ├── vip_seqlib.py │ │ │ │ ├── vip_seqlib.svh │ │ │ │ ├── vip_sequencer.py │ │ │ │ ├── vip_tr.py │ │ │ │ └── vip_tr.svh │ │ └── ubus │ │ │ ├── examples │ │ │ ├── Makefile │ │ │ ├── dut_dummy.v │ │ │ ├── test_lib.py │ │ │ ├── test_lib.sv │ │ │ ├── ubus_example_master_seq_lib.py │ │ │ ├── ubus_example_master_seq_lib.sv │ │ │ ├── ubus_example_scoreboard.py │ │ │ ├── ubus_example_scoreboard.sv │ │ │ ├── ubus_example_tb.py │ │ │ ├── ubus_example_tb.sv │ │ │ ├── ubus_tb_top.py │ │ │ ├── ubus_tb_top.sv │ │ │ └── vsim.do │ │ │ ├── py │ │ │ ├── ubus_bus_monitor.py │ │ │ ├── ubus_env.py │ │ │ ├── ubus_if.py │ │ │ ├── ubus_master_agent.py │ │ │ ├── ubus_master_driver.py │ │ │ ├── ubus_master_monitor.py │ │ │ ├── ubus_master_seq_lib.py │ │ │ ├── ubus_master_sequencer.py │ │ │ ├── ubus_pkg.py │ │ │ ├── ubus_slave_agent.py │ │ │ ├── ubus_slave_driver.py │ │ │ ├── ubus_slave_monitor.py │ │ │ ├── ubus_slave_seq_lib.py │ │ │ ├── ubus_slave_sequencer.py │ │ │ ├── ubus_transfer.py │ │ │ └── ubus_version.svh │ │ │ └── sv │ │ │ ├── ubus_bus_monitor.sv │ │ │ ├── ubus_env.sv │ │ │ ├── ubus_if.sv │ │ │ ├── ubus_master_agent.sv │ │ │ ├── ubus_master_driver.sv │ │ │ ├── ubus_master_monitor.sv │ │ │ ├── ubus_master_seq_lib.sv │ │ │ ├── ubus_master_sequencer.sv │ │ │ ├── ubus_pkg.sv │ │ │ ├── ubus_slave_agent.sv │ │ │ ├── ubus_slave_driver.sv │ │ │ ├── ubus_slave_monitor.sv │ │ │ ├── ubus_slave_seq_lib.sv │ │ │ ├── ubus_slave_sequencer.sv │ │ │ ├── ubus_transfer.sv │ │ │ └── ubus_version.svh │ ├── minimal │ │ ├── Makefile │ │ ├── new_dut.sv │ │ └── new_test.py │ ├── simple │ │ ├── Makefile │ │ ├── MakefileCommon.mk │ │ ├── README.txt │ │ ├── TODO.md │ │ ├── basic_examples │ │ │ ├── event_pool │ │ │ │ ├── Makefile │ │ │ │ └── test.py │ │ │ ├── module │ │ │ │ ├── Makefile │ │ │ │ ├── test.py │ │ │ │ └── test.sv │ │ │ └── pkg │ │ │ │ ├── Makefile │ │ │ │ ├── test.py │ │ │ │ └── test.sv │ │ ├── callbacks │ │ │ ├── Makefile │ │ │ ├── top.py │ │ │ └── top.sv │ │ ├── cmdline │ │ │ ├── Makefile │ │ │ └── test_cmdline_args.py │ │ ├── common_stub.sv │ │ ├── common_stub.vhd │ │ ├── comps │ │ │ └── comparator │ │ │ │ ├── Makefile │ │ │ │ └── test_comparators.py │ │ ├── configuration │ │ │ ├── automated │ │ │ │ ├── Makefile │ │ │ │ ├── classA.py │ │ │ │ ├── classA.svh │ │ │ │ ├── classB.py │ │ │ │ ├── classB.svh │ │ │ │ ├── classC.py │ │ │ │ ├── classC.svh │ │ │ │ ├── module_top.sv │ │ │ │ ├── my_env_pkg.py │ │ │ │ ├── my_env_pkg.sv │ │ │ │ ├── top.py │ │ │ │ └── top.sv │ │ │ └── manual │ │ │ │ ├── Makefile │ │ │ │ ├── classA.py │ │ │ │ ├── classA.svh │ │ │ │ ├── classB.py │ │ │ │ ├── classB.svh │ │ │ │ ├── classC.py │ │ │ │ ├── classC.svh │ │ │ │ ├── module_top.sv │ │ │ │ ├── my_env_pkg.py │ │ │ │ ├── my_env_pkg.sv │ │ │ │ ├── top.py │ │ │ │ └── top.sv │ │ ├── factory │ │ │ ├── Makefile │ │ │ ├── env_pkg.py │ │ │ ├── env_pkg.sv │ │ │ ├── gen_pkg.py │ │ │ ├── gen_pkg.sv │ │ │ ├── packet_pkg.py │ │ │ ├── packet_pkg.sv │ │ │ ├── test.py │ │ │ └── test.sv │ │ ├── hello_world │ │ │ ├── Makefile │ │ │ ├── __init__.py │ │ │ ├── consumer.py │ │ │ ├── consumer.sv │ │ │ ├── hello_world.py │ │ │ ├── hello_world.sv │ │ │ ├── packet.py │ │ │ ├── packet.sv │ │ │ ├── producer.py │ │ │ ├── producer.sv │ │ │ ├── top.py │ │ │ └── top.sv │ │ ├── interfaces │ │ │ ├── Makefile │ │ │ ├── dut.sv │ │ │ ├── interface.py │ │ │ └── interface.sv │ │ ├── objections │ │ │ ├── Makefile │ │ │ ├── simple.py │ │ │ └── simple.sv │ │ ├── phases │ │ │ ├── basic │ │ │ │ ├── Makefile │ │ │ │ ├── test.py │ │ │ │ └── test.sv │ │ │ ├── run_test │ │ │ │ └── test.sv │ │ │ └── timeout │ │ │ │ ├── Makefile │ │ │ │ ├── tb_env.py │ │ │ │ ├── tb_env.svh │ │ │ │ ├── tb_timer.py │ │ │ │ ├── tb_timer.svh │ │ │ │ ├── test.py │ │ │ │ └── test.sv │ │ ├── registers │ │ │ ├── common │ │ │ │ ├── Makefile │ │ │ │ ├── __init__.py │ │ │ │ ├── any_agent.sv │ │ │ │ ├── any_config.sv │ │ │ │ ├── apb │ │ │ │ │ ├── apb_agent.py │ │ │ │ │ ├── apb_agent.sv │ │ │ │ │ ├── apb_master.py │ │ │ │ │ ├── apb_master.sv │ │ │ │ │ ├── apb_monitor.py │ │ │ │ │ └── apb_monitor.sv │ │ │ │ ├── reg_agent.py │ │ │ │ ├── reg_agent.sv │ │ │ │ └── wishbone │ │ │ │ │ ├── agent.sv │ │ │ │ │ ├── config.sv │ │ │ │ │ ├── cycle.sv │ │ │ │ │ ├── driver.sv │ │ │ │ │ ├── wb_if.sv │ │ │ │ │ └── wishbone.sv │ │ │ ├── integration │ │ │ │ ├── 10direct │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── tb_env.py │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ └── test_top.py │ │ │ │ ├── 20layered │ │ │ │ │ └── tb_env.sv │ │ │ │ └── common │ │ │ │ │ ├── dut.sv │ │ │ │ │ ├── dut_with_clkgen.sv │ │ │ │ │ ├── regmodel.py │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_top.sv │ │ │ │ │ ├── test.py │ │ │ │ │ └── test.sv │ │ │ ├── models │ │ │ │ ├── aliasing │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ └── tb_run.sv │ │ │ │ ├── broadcast │ │ │ │ │ ├── dut.sv │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ ├── tb_run.sv │ │ │ │ │ └── tb_top.sv │ │ │ │ ├── coverage │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── reg_mem_dut.sv │ │ │ │ │ ├── regmodel.py │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_env.py │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ ├── tb_run.py │ │ │ │ │ └── tb_run.sv │ │ │ │ ├── fifo_reg │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── dut.sv │ │ │ │ │ ├── dut.vhd │ │ │ │ │ ├── reg_model.py │ │ │ │ │ ├── reg_model.sv │ │ │ │ │ ├── tb_env.py │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ ├── tb_run.py │ │ │ │ │ └── tb_run.sv │ │ │ │ ├── not_yet_implemented │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ └── tb_run.sv │ │ │ │ ├── reg_without_field │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ └── tb_run.sv │ │ │ │ ├── ro_wo_same_addr │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ └── tb_run.sv │ │ │ │ ├── shared_reg │ │ │ │ │ ├── blk_env.sv │ │ │ │ │ ├── blk_pkg.sv │ │ │ │ │ ├── blk_run.sv │ │ │ │ │ ├── blk_seqlib.sv │ │ │ │ │ ├── blk_testlib.sv │ │ │ │ │ ├── reg_B.sv │ │ │ │ │ └── reg_pkg.sv │ │ │ │ ├── user-defined │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── dut.sv │ │ │ │ │ ├── regmodel.py │ │ │ │ │ ├── regmodel.sv │ │ │ │ │ ├── tb_env.py │ │ │ │ │ ├── tb_env.sv │ │ │ │ │ ├── tb_run.py │ │ │ │ │ └── tb_run.sv │ │ │ │ └── virtual_regs │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── dut.sv │ │ │ │ │ ├── regmodel.py │ │ │ │ │ ├── tb_env.py │ │ │ │ │ ├── tb_run.py │ │ │ │ │ └── virtual_regs.rdl │ │ │ ├── primer │ │ │ │ ├── Makefile │ │ │ │ ├── cmdline_test.py │ │ │ │ ├── cmdline_test.sv │ │ │ │ ├── dut.sv │ │ │ │ ├── mem_test.py │ │ │ │ ├── primer.pdf │ │ │ │ ├── reg_model.py │ │ │ │ ├── reg_model.sv │ │ │ │ ├── tb_env.py │ │ │ │ ├── tb_env.sv │ │ │ │ ├── tb_top.sv │ │ │ │ ├── test.py │ │ │ │ ├── test.sv │ │ │ │ ├── testlib.py │ │ │ │ ├── testlib.sv │ │ │ │ ├── user_test.py │ │ │ │ └── user_test.sv │ │ │ ├── sequence_api │ │ │ │ ├── README.txt │ │ │ │ ├── blk_dut.sv │ │ │ │ ├── blk_env.sv │ │ │ │ ├── blk_pkg.sv │ │ │ │ ├── blk_reg_pkg.sv │ │ │ │ ├── blk_run.sv │ │ │ │ ├── blk_seqlib.sv │ │ │ │ ├── blk_testlib.sv │ │ │ │ ├── blk_top.sv │ │ │ │ └── reg_B.sv │ │ │ └── vertical_reuse │ │ │ │ ├── Makefile │ │ │ │ ├── blk_dut.sv │ │ │ │ ├── blk_dut.vhd │ │ │ │ ├── blk_env.py │ │ │ │ ├── blk_env.sv │ │ │ │ ├── blk_pkg.sv │ │ │ │ ├── blk_reg_pkg.sv │ │ │ │ ├── blk_run.py │ │ │ │ ├── blk_run.sv │ │ │ │ ├── blk_seqlib.py │ │ │ │ ├── blk_seqlib.sv │ │ │ │ ├── blk_testlib.py │ │ │ │ ├── blk_testlib.sv │ │ │ │ ├── blk_top.sv │ │ │ │ ├── reg_B.py │ │ │ │ ├── reg_B.sv │ │ │ │ ├── reg_S.py │ │ │ │ ├── reg_S.sv │ │ │ │ ├── sys_dut.sv │ │ │ │ ├── sys_dut.vhd │ │ │ │ ├── sys_env.py │ │ │ │ ├── sys_env.sv │ │ │ │ ├── sys_pkg.sv │ │ │ │ ├── sys_reg_pkg.sv │ │ │ │ ├── sys_run.py │ │ │ │ ├── sys_run.sv │ │ │ │ ├── sys_seqlib.py │ │ │ │ ├── sys_seqlib.sv │ │ │ │ ├── sys_testlib.py │ │ │ │ ├── sys_testlib.sv │ │ │ │ └── sys_top.sv │ │ ├── reporting │ │ │ ├── Makefile │ │ │ └── test_reporting.py │ │ ├── sequence │ │ │ ├── basic_read_write_sequence │ │ │ │ ├── Makefile │ │ │ │ ├── top.py │ │ │ │ └── top.sv │ │ │ ├── forking │ │ │ │ ├── Makefile │ │ │ │ └── seq_fork_test_top.py │ │ │ └── uvm_dos │ │ │ │ ├── Makefile │ │ │ │ └── top_uvm_dos.py │ │ ├── tlm1 │ │ │ ├── bidir │ │ │ │ ├── Makefile │ │ │ │ ├── bidir.py │ │ │ │ └── bidir.sv │ │ │ ├── fifo │ │ │ │ ├── Makefile │ │ │ │ ├── test.py │ │ │ │ └── test.sv │ │ │ ├── hierarchy │ │ │ │ ├── Makefile │ │ │ │ ├── hierarchy.py │ │ │ │ ├── hierarchy.sv │ │ │ │ └── module_top.sv │ │ │ ├── master_slave │ │ │ │ ├── Makefile │ │ │ │ ├── master_slave_pkg.py │ │ │ │ └── test_master_slave.py │ │ │ └── producer_consumer │ │ │ │ ├── Makefile │ │ │ │ ├── fifo.py │ │ │ │ ├── fifo.sv │ │ │ │ ├── module_top.sv │ │ │ │ └── module_top.vhd │ │ ├── tlm2 │ │ │ ├── blocking_simple │ │ │ │ ├── Makefile │ │ │ │ ├── apb_rw.py │ │ │ │ ├── initiator.py │ │ │ │ ├── target.py │ │ │ │ ├── tb_env.py │ │ │ │ └── tb_run.py │ │ │ ├── nonblocking_simple │ │ │ │ ├── Makefile │ │ │ │ ├── README.txt │ │ │ │ ├── device.py │ │ │ │ ├── device.sv │ │ │ │ ├── host.py │ │ │ │ ├── host.sv │ │ │ │ ├── tb_env.py │ │ │ │ ├── tb_env.sv │ │ │ │ ├── tb_run.py │ │ │ │ ├── tb_run.sv │ │ │ │ ├── usb_xfer.py │ │ │ │ └── usb_xfer.sv │ │ │ └── temporal_decoupling │ │ │ │ ├── apb_rw.sv │ │ │ │ ├── initiator.sv │ │ │ │ ├── target.sv │ │ │ │ ├── tb_env.sv │ │ │ │ └── tb_run.sv │ │ └── trivial │ │ │ ├── Makefile │ │ │ └── component.py │ └── sv │ │ ├── Makefile │ │ └── test_forks.py ├── hdl │ └── uvm_test.v ├── sim_integration │ ├── Makefile │ ├── module_top.sv │ ├── test_uvm_events.py │ └── uvm_testlib.py ├── test_uvm.py └── test_uvm_tlm.py └── unit ├── test_sv.py ├── test_uvm_analysis_port.py ├── test_uvm_callback.py ├── test_uvm_cmdline_processor.py ├── test_uvm_component.py ├── test_uvm_config_db.py ├── test_uvm_coreservice.py ├── test_uvm_domain.py ├── test_uvm_factory.py ├── test_uvm_globals.py ├── test_uvm_hdl.py ├── test_uvm_mailbox.py ├── test_uvm_misc.py ├── test_uvm_object.py ├── test_uvm_object_defines.py ├── test_uvm_objection.py ├── test_uvm_packer.py ├── test_uvm_phase.py ├── test_uvm_pool.py ├── test_uvm_port_base.py ├── test_uvm_ports.py ├── test_uvm_printer.py ├── test_uvm_queue.py ├── test_uvm_reg.py ├── test_uvm_reg_block.py ├── test_uvm_reg_field.py ├── test_uvm_reg_map.py ├── test_uvm_reg_model.py ├── test_uvm_reg_predictor.py ├── test_uvm_registry.py ├── test_uvm_report_catcher.py ├── test_uvm_report_handler.py ├── test_uvm_report_message.py ├── test_uvm_report_object.py ├── test_uvm_report_server.py ├── test_uvm_resource.py ├── test_uvm_resource_db.py ├── test_uvm_root.py ├── test_uvm_scope_stack.py ├── test_uvm_sequencer_base.py ├── test_uvm_spell_chkr.py ├── test_uvm_sqr_connections.py ├── test_uvm_tlm_fifos.py ├── test_uvm_tlm_imps.py └── test_uvm_topdown_phase.py /.coveragerc: -------------------------------------------------------------------------------- 1 | # .coveragerc to control coverage.py 2 | # Coverages settings for uvm-python 3 | 4 | [run] 5 | include = 6 | *src/uvm* 7 | parallel = True 8 | branch = True 9 | 10 | [report] 11 | include = 12 | *src/uvm* 13 | 14 | skip_covered = True 15 | #skip_empty = True 16 | 17 | [html] 18 | directory = htmlcov 19 | -------------------------------------------------------------------------------- /.flake8: -------------------------------------------------------------------------------- 1 | [flake8] 2 | max-line-length = 100 3 | max-complexity = 10 4 | ignore = E226,E265,E231,E266,E221,E128,W504,E303,W503,F405 5 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | uvm-1.2 2 | uvm_ref/ 3 | uvm_logfile.txt 4 | 5 | tags 6 | vimproject 7 | 8 | __pycache__ 9 | *.log 10 | *.pyc 11 | build 12 | dist 13 | out 14 | sim_build* 15 | .mypy_cache 16 | .pytype 17 | 18 | obj_dir 19 | .venv 20 | 21 | # Code coverage 22 | .coverage 23 | .coverage.* 24 | htmlcov/ 25 | .coveralls.yml 26 | test-cocotb.xml 27 | test-results.xml 28 | .cocotb-results 29 | 30 | # ghdl files 31 | e~*.o 32 | 33 | common_stub 34 | 35 | .eggs 36 | *egg-info* 37 | *.bak 38 | 39 | # Vim tmp files 40 | *.swp 41 | *~ 42 | 43 | # Emacs tmp files 44 | \#*\# 45 | \.\#* 46 | 47 | # Mergetool tmp files 48 | *.orig 49 | *.bak 50 | 51 | # Waveforms 52 | *.vcd 53 | *.fst 54 | *.fst.hier 55 | 56 | # Results 57 | results*.xml 58 | results_coverage.xml 59 | combined_results.xml 60 | 61 | # Debuggers 62 | .gdb_history 63 | 64 | # Pytest 65 | .pytest_cache 66 | 67 | # Synopsys VCS 68 | *.tab 69 | sim_build 70 | ucli.key 71 | 72 | # Cadence Incisive/Xcelium 73 | *.elog 74 | irun.log 75 | xrun.log 76 | irun.key 77 | xrun.key 78 | irun.history 79 | xrun.history 80 | INCA_libs 81 | xcelium.d 82 | ncelab_*.err 83 | xmelab_*.err 84 | ncsim_*.err 85 | xmsim_*.err 86 | bpad_*.err 87 | .bpad/ 88 | .simvision/ 89 | waves.shm/ 90 | 91 | # Mentor Modelsim/Questa 92 | test/examples/**/modelsim.ini 93 | test/examples/**/transcript 94 | *.wlf 95 | vish_stacktrace.vstf 96 | 97 | # Aldec Riviera 98 | test/examples/**/library.cfg 99 | test/examples/**/dataset.asdb 100 | test/examples/**/compile 101 | 102 | # Tachyon DA CVC 103 | test/examples/**/verilog.log 104 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | # .readthedocs.yml 2 | # Read the Docs configuration file 3 | # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details 4 | 5 | # Required 6 | version: 2 7 | 8 | # Build documentation in the docs/ directory with Sphinx 9 | sphinx: 10 | configuration: docs/source/conf.py 11 | 12 | # Build documentation with MkDocs 13 | #mkdocs: 14 | # configuration: mkdocs.yml 15 | 16 | # Optionally build your docs in additional formats such as PDF and ePub 17 | #formats: html 18 | 19 | # Optionally set the version of Python and requirements required to build your docs 20 | python: 21 | version: 3.7 22 | install: 23 | - requirements: docs/requirements.txt 24 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | language: python 2 | python: 3 | - "3.7" 4 | # command to install dependencies 5 | install: 6 | - pip install -r ci/requirements.txt 7 | #- bash ci/install_iverilog.sh 8 | - apt-get update -qq 9 | - apt-get install -y -qq flex bison gperf 10 | - apt-get install iverilog 11 | # command to run tests 12 | script: 13 | - make test || exit 1 14 | - find -name results.xml -exec cat {} \; > results.log 15 | - bash ci/check_errors.sh 16 | -------------------------------------------------------------------------------- /CHANGELOG: -------------------------------------------------------------------------------- 1 | 2 | # Changelog 3 | All notable changes to uvm-python will be documented in this file. 4 | 5 | The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), 6 | and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). 7 | 8 | ## [Unreleased] 9 | 10 | ## [0.4.0] - 2025-02-09 11 | - Bug fixes in uvm_objection (missing casts) 12 | - Tested on verilator 5.032, iverilog version 13.0 (devel) (s20221226-498-g52d049b51) 13 | - Tested on cocotb 1.9.2 14 | 15 | ## [0.3.0] 16 | - updated to support verilator 5.006+ (required by cocotb) 17 | - old verilator v4.016 no longer works 18 | - UVMVoid class removed 19 | 20 | ## [0.2.0] 21 | - verilator stability improved by using NullTrigger 22 | - uvm_do_* API expanded, support for sequence randomisation 23 | - 2 functions added to uvm_globals.py 24 | 25 | ## [0.1.1] - 2021-03-17 26 | ### Fixed 27 | - pytype errors in uvm_sequencer 28 | - Added missing dep for cocotb-bus for document generation 29 | 30 | ## [0.1.0] - 2021-03-15 31 | ### Added 32 | - First release 33 | - Objection code improved, unnecessary zero delays removed 34 | - 3 find-methods for UVMPhase added 35 | - try_next_item() for sequencer added 36 | - codec example further expanded, still some issues with test termination 37 | - cocotb bumped to version v1.5.0 38 | 39 | [Unreleased]: https://github.com/tpoikela/uvm-python/compare/v0.3.0...HEAD 40 | [0.3.0]: https://github.com/tpoikela/uvm-python//compare/v0.2.0...v0.3.0 41 | [0.2.0]: https://github.com/tpoikela/uvm-python//compare/v0.1.1...v0.2.0 42 | [0.1.1]: https://github.com/tpoikela/uvm-python//compare/v0.1.0...v0.1.1 43 | [0.1.0]: https://github.com/tpoikela/uvm-python/releases/tag/v0.1.0 44 | -------------------------------------------------------------------------------- /__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tpoikela/uvm-python/2301431a22ddec14abebb8df38f35c6dcdefd241/__init__.py -------------------------------------------------------------------------------- /bin/fixer.py: -------------------------------------------------------------------------------- 1 | """ Wrapper for lib2to3 main to use custom fixes folder """ 2 | 3 | import sys 4 | from lib2to3.main import main 5 | 6 | sys.exit(main('fixes')) 7 | -------------------------------------------------------------------------------- /ci/check_errors.sh: -------------------------------------------------------------------------------- 1 | 2 | # Check that SIM is defined, exit otherwise 3 | if [[ -z $SIM ]] 4 | then 5 | echo "SIM is not defined, exiting" 6 | exit 1 7 | fi 8 | 9 | RET_VAL=`grep -l failure results_${SIM}.log` 10 | echo "RET_VAL is |$RET_VAL|" 11 | if [[ -n $RET_VAL ]] 12 | then 13 | echo "Test failures found for SIM=${SIM}:" 14 | exit 1 15 | fi 16 | 17 | echo "All testcases passed for SIM=${SIM}:" 18 | grep testcase results_${SIM}.log | sort 19 | 20 | exit 0 21 | -------------------------------------------------------------------------------- /ci/install_ghdl.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | apt-get install -y --no-install-recommends ghdl 4 | -------------------------------------------------------------------------------- /ci/install_iverilog.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | git clone https://github.com/steveicarus/iverilog.git 4 | cd iverilog 5 | git pull 6 | git checkout 52d049b5 7 | sh autoconf.sh 8 | ./configure 9 | make -j `nproc` 10 | make install 11 | -------------------------------------------------------------------------------- /ci/install_verilator.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | # VERILATOR_ROOT="$PWD/verilator" 4 | 5 | # Clone repo only if it doesn't exist 6 | if [ ! -d "verilator" ]; then 7 | git clone https://github.com/verilator/verilator.git 8 | fi 9 | 10 | cd verilator 11 | 12 | # Returns non-zero if no .o files exist 13 | find -name '*.o' | grep -q . 14 | 15 | # If .o files don't exist, do autoconf and do make 16 | if [ $? -ne 0 ]; then 17 | git checkout v5.022 18 | echo "autoconf" 19 | autoconf 20 | echo "configure" 21 | ./configure --prefix="$VERILATOR_ROOT" 22 | echo "make" 23 | make -d -j `nproc` 24 | echo "make install" 25 | else 26 | echo "Verilator already built, skipping compile/install steps" 27 | fi 28 | -------------------------------------------------------------------------------- /ci/requirements.txt: -------------------------------------------------------------------------------- 1 | #git+https://github.com/cocotb/cocotb@88bca3c9a9515c9ed399ca6dcf569696fded23f7#egg=cocotb 2 | cocotb>=1.7.2 3 | cocotb-bus>=0.1.1 4 | cocotb-coverage==1.1.0 5 | regex==2019.11.1 6 | -------------------------------------------------------------------------------- /devscripts/create_release.pl: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env perl 2 | 3 | use strict; 4 | 5 | use Getopt::Long; 6 | 7 | my %opt; 8 | GetOptions( 9 | "production" => \$opt{production}, 10 | "clean" => \$opt{clean}, 11 | ); 12 | 13 | if (defined $opt{clean}) { 14 | system("rm dist/*") if -d "./dist"; 15 | } 16 | 17 | my $build_cmd = "python -m build"; 18 | my $twine_cmd = "python -m twine upload --repository testpypi dist/*"; 19 | if ($opt{production}) { 20 | $twine_cmd = "python -m twine upload dist/*"; 21 | } 22 | 23 | my $err = system($build_cmd); 24 | if ($err == 0) { 25 | system($twine_cmd); 26 | } 27 | else { 28 | die("$build_cmd failed. Not uploading to PyPi"); 29 | } 30 | -------------------------------------------------------------------------------- /devscripts/create_release.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import argparse 4 | import os 5 | import subprocess 6 | 7 | parser = argparse.ArgumentParser() 8 | parser.add_argument('--production', action='store_true') 9 | parser.add_argument('--clean', action='store_true') 10 | args = parser.parse_args() 11 | 12 | if args.clean: 13 | if os.path.isdir('./dist'): 14 | subprocess.run(['rm', 'dist/*'], check=True, shell=True) 15 | 16 | build_cmd = 'python -m build' 17 | testpypi_twine_cmd = 'python -m twine upload --repository testpypi dist/*' 18 | production_twine_cmd = 'python -m twine upload dist/*' 19 | twine_cmd = testpypi_twine_cmd if not args.production else production_twine_cmd 20 | 21 | try: 22 | subprocess.run(build_cmd, check=True, shell=True) 23 | subprocess.run(twine_cmd, check=True, shell=True) 24 | except subprocess.CalledProcessError: 25 | raise SystemExit(f'{build_cmd} failed. Not uploading to PyPi') 26 | 27 | -------------------------------------------------------------------------------- /devscripts/dev_requirements.txt: -------------------------------------------------------------------------------- 1 | # Modules needed for PyPI release 2 | build 3 | twine 4 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # Build the documentation 2 | # 3 | # Note: this Makefile is *not* used by Read The Docs, it exec()'s the conf.py 4 | # file directly. Hence, all special build steps here are only relevant for 5 | # local builds, not for RTD builds. Add all build steps which should be executed 6 | # in RTD builds as Python code into the conf.py file. 7 | # 8 | 9 | # You can set these variables from the command line. 10 | SPHINXOPTS = 11 | SPHINXBUILD = .venv/bin/sphinx-build 12 | SOURCEDIR = source 13 | BUILDDIR = build 14 | 15 | # Put it first so that "make" without argument is like "make help". 16 | help: .venv 17 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 18 | 19 | .venv: requirements.txt 20 | @echo Creating Python venv for Sphinx build 21 | python3 -m venv .venv 22 | .venv/bin/pip -q install --upgrade pip 23 | .venv/bin/pip -q install -r requirements.txt 24 | 25 | .PHONY: clean 26 | clean: .venv Makefile 27 | @$(SPHINXBUILD) -M clean "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 28 | 29 | .PHONY: distclean 30 | distclean: 31 | -rm -rf .venv build sphinxext/__pycache__ 32 | 33 | .PHONY: help Makefile 34 | 35 | # Catch-all target: route all unknown targets to Sphinx using the new 36 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 37 | .DEFAULT: 38 | # Dependencies for this special target are ignored by make, as discussed in 39 | # http://stackoverflow.com/questions/26875072/dependencies-for-special-make-target-default-not-firing 40 | # We hack around that by calling the target explicitly. 41 | ifeq ($(DEV), ) 42 | make .venv 43 | endif 44 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 45 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | # Python dependencies to build the documentation 2 | Sphinx>=2.1 3 | sphinx-rtd-theme 4 | # sphinx-automodapi 5 | cocotb 6 | cocotb-bus 7 | #git+git://github.com/cocotb/cocotb@8604628#egg=cocotb 8 | cocotb-coverage 9 | regex 10 | -------------------------------------------------------------------------------- /docs/source/_static/overflow_fix.css: -------------------------------------------------------------------------------- 1 | 2 | div.documentwrapper div.bodywrapper { margin-left: 350px;} 3 | div.document div.sphinxsidebar { width: 350px; } 4 | 5 | div.sphinxsidebarwrapper div { 6 | overflow: auto; 7 | } 8 | -------------------------------------------------------------------------------- /docs/source/base/uvm_barrier.rst: -------------------------------------------------------------------------------- 1 | uvm_barrier 2 | ----------- 3 | 4 | .. automodule:: uvm.base.uvm_barrier 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_bottomup_phase.rst: -------------------------------------------------------------------------------- 1 | uvm_bottomup_phase 2 | ------------------ 3 | 4 | .. automodule:: uvm.base.uvm_bottomup_phase 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_callback.rst: -------------------------------------------------------------------------------- 1 | uvm_callback 2 | ------------ 3 | 4 | .. automodule:: uvm.base.uvm_callback 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_cmdline_processor.rst: -------------------------------------------------------------------------------- 1 | uvm_cmdline_processor 2 | --------------------- 3 | 4 | .. automodule:: uvm.base.uvm_cmdline_processor 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_common_phases.rst: -------------------------------------------------------------------------------- 1 | UVM Common Phases 2 | ----------------- 3 | 4 | .. automodule:: uvm.base.uvm_common_phases 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_comparer.rst: -------------------------------------------------------------------------------- 1 | uvm_comparer 2 | ------------ 3 | 4 | .. automodule:: uvm.base.uvm_comparer 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_component.rst: -------------------------------------------------------------------------------- 1 | uvm_component 2 | ------------- 3 | 4 | .. automodule:: uvm.base.uvm_component 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_config_db.rst: -------------------------------------------------------------------------------- 1 | uvm_config_db 2 | ------------- 3 | 4 | .. automodule:: uvm.base.uvm_config_db 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_coreservice.rst: -------------------------------------------------------------------------------- 1 | UVM Core Service 2 | ---------------- 3 | 4 | .. automodule:: uvm.base.uvm_coreservice 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_domain.rst: -------------------------------------------------------------------------------- 1 | uvm_domain 2 | ---------- 3 | 4 | .. automodule:: uvm.base.uvm_domain 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_event.rst: -------------------------------------------------------------------------------- 1 | uvm_event 2 | --------- 3 | 4 | .. automodule:: uvm.base.uvm_event 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_event_callback.rst: -------------------------------------------------------------------------------- 1 | uvm_event_callback 2 | ------------------ 3 | 4 | .. automodule:: uvm.base.uvm_event_callback 5 | -------------------------------------------------------------------------------- /docs/source/base/uvm_factory.rst: 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(UVM) `_ 6 | version 1.2 to `Python `_ and the 7 | `cocotb Coroutine based Cosimulation Testbench environment `_. 8 | 9 | .. toctree:: 10 | :maxdepth: 2 11 | 12 | uvm_1.2_class_reference 13 | uvm_users_guide_1.2 14 | 15 | 16 | Indices and tables 17 | ------------------ 18 | 19 | * :ref:`genindex` 20 | * :ref:`modindex` 21 | * :ref:`search` 22 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_callback_defines.rst: -------------------------------------------------------------------------------- 1 | Callbacks 2 | --------- 3 | 4 | .. automodule:: uvm.macros.uvm_callback_defines 5 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_global_defines.rst: -------------------------------------------------------------------------------- 1 | Global Macros 2 | ------------- 3 | 4 | .. automodule:: uvm.macros.uvm_global_defines 5 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_message_defines.rst: -------------------------------------------------------------------------------- 1 | Report Macros 2 | ------------- 3 | 4 | .. automodule:: uvm.macros.uvm_message_defines 5 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_object_defines.rst: -------------------------------------------------------------------------------- 1 | Component and Object 2 | -------------------- 3 | 4 | .. automodule:: uvm.macros.uvm_object_defines 5 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_reg_defines.rst: -------------------------------------------------------------------------------- 1 | Registers 2 | --------- 3 | 4 | .. automodule:: uvm.macros.uvm_reg_defines 5 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_sequence_defines.rst: -------------------------------------------------------------------------------- 1 | Sequence and Do Action 2 | ---------------------- 3 | 4 | .. automodule:: uvm.macros.uvm_sequence_defines 5 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_tlm_defines.rst: -------------------------------------------------------------------------------- 1 | TLM 2 | --- 3 | 4 | .. automodule:: uvm.macros.uvm_tlm_defines 5 | -------------------------------------------------------------------------------- /docs/source/macros/uvm_version_defines.rst: -------------------------------------------------------------------------------- 1 | Version Macros 2 | -------------- 3 | 4 | .. automodule:: uvm.macros.uvm_version_defines 5 | -------------------------------------------------------------------------------- /docs/source/overviews/base.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.base 5 | -------------------------------------------------------------------------------- /docs/source/overviews/cmdlineproc.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.cmdlineproc 5 | -------------------------------------------------------------------------------- /docs/source/overviews/comparators.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.comparators 5 | -------------------------------------------------------------------------------- /docs/source/overviews/components.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.components 5 | -------------------------------------------------------------------------------- /docs/source/overviews/config_and_res.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.config_and_res 5 | -------------------------------------------------------------------------------- /docs/source/overviews/containers.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.containers 5 | -------------------------------------------------------------------------------- /docs/source/overviews/dap.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.dap 5 | -------------------------------------------------------------------------------- /docs/source/overviews/factory.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.factory 5 | -------------------------------------------------------------------------------- /docs/source/overviews/globals.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.globals 5 | -------------------------------------------------------------------------------- /docs/source/overviews/intro.rst: -------------------------------------------------------------------------------- 1 | Introduction 2 | --------------------------------------- 3 | FIXME 4 | -------------------------------------------------------------------------------- /docs/source/overviews/macros.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.macros 5 | -------------------------------------------------------------------------------- /docs/source/overviews/phasing.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.phasing 5 | -------------------------------------------------------------------------------- /docs/source/overviews/policies.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.policies 5 | -------------------------------------------------------------------------------- /docs/source/overviews/recording.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.recording 5 | -------------------------------------------------------------------------------- /docs/source/overviews/registers.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.registers 5 | -------------------------------------------------------------------------------- /docs/source/overviews/relnotes.rst: -------------------------------------------------------------------------------- 1 | Release Notes 2 | ------------- 3 | FIXME 4 | -------------------------------------------------------------------------------- /docs/source/overviews/reporting.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.reporting 5 | -------------------------------------------------------------------------------- /docs/source/overviews/sequencers.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.sequencers 5 | -------------------------------------------------------------------------------- /docs/source/overviews/sequences.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.sequences 5 | -------------------------------------------------------------------------------- /docs/source/overviews/synchro.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.synchro 5 | -------------------------------------------------------------------------------- /docs/source/overviews/test_phasing.rst: -------------------------------------------------------------------------------- 1 | User-Defined Phases 2 | ------------------- 3 | 4 | .. automodule:: uvm.test_phasing 5 | -------------------------------------------------------------------------------- /docs/source/overviews/tlm1.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.tlm1 5 | -------------------------------------------------------------------------------- /docs/source/overviews/tlm2.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.tlm2 5 | -------------------------------------------------------------------------------- /docs/source/overviews/tlm_ifs_and_ports.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | .. automodule:: uvm.tlm_ifs_and_ports 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_mem_access_seq.rst: -------------------------------------------------------------------------------- 1 | Memory Access 2 | ------------- 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_mem_access_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_mem_walk_seq.rst: -------------------------------------------------------------------------------- 1 | Memory Walk 2 | ----------- 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_mem_walk_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_reg_access_seq.rst: -------------------------------------------------------------------------------- 1 | Register Access 2 | --------------- 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_reg_access_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_reg_bit_bash_seq.rst: -------------------------------------------------------------------------------- 1 | Register Bit Bash 2 | ----------------- 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_reg_bit_bash_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_reg_hw_reset_seq.rst: -------------------------------------------------------------------------------- 1 | Reset 2 | ----- 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_reg_hw_reset_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_reg_mem_built_in_seq.rst: -------------------------------------------------------------------------------- 1 | Run All Built-In 2 | ---------------- 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_reg_mem_built_in_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_reg_mem_hdl_paths_seq.rst: -------------------------------------------------------------------------------- 1 | HDL Paths Checking 2 | ------------------ 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_reg_mem_hdl_paths_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/sequences/uvm_reg_mem_shared_access_seq.rst: -------------------------------------------------------------------------------- 1 | Shared Access 2 | ------------- 3 | 4 | .. automodule:: uvm.reg.sequences.uvm_reg_mem_shared_access_seq 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_mem.rst: -------------------------------------------------------------------------------- 1 | Memories 2 | -------- 3 | 4 | .. automodule:: uvm.reg.uvm_mem 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_mem_mam.rst: -------------------------------------------------------------------------------- 1 | Memory Allocation Mgr 2 | --------------------- 3 | 4 | .. automodule:: uvm.reg.uvm_mem_mam 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg.rst: -------------------------------------------------------------------------------- 1 | Registers 2 | --------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_adapter.rst: -------------------------------------------------------------------------------- 1 | Register Model Adaptor 2 | ---------------------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_adapter 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_backdoor.rst: -------------------------------------------------------------------------------- 1 | Backdoors 2 | --------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_backdoor 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_block.rst: -------------------------------------------------------------------------------- 1 | Blocks 2 | ------ 3 | 4 | .. automodule:: uvm.reg.uvm_reg_block 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_cbs.rst: -------------------------------------------------------------------------------- 1 | Callbacks 2 | --------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_cbs 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_field.rst: -------------------------------------------------------------------------------- 1 | Fields 2 | ------ 3 | 4 | .. automodule:: uvm.reg.uvm_reg_field 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_fifo.rst: -------------------------------------------------------------------------------- 1 | FIFO Registers 2 | -------------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_fifo 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_file.rst: -------------------------------------------------------------------------------- 1 | Register Files 2 | -------------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_file 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_indirect.rst: -------------------------------------------------------------------------------- 1 | Indirect Registers 2 | ------------------ 3 | 4 | .. automodule:: uvm.reg.uvm_reg_indirect 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_item.rst: -------------------------------------------------------------------------------- 1 | Generic Register Operation Descriptors 2 | -------------------------------------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_item 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_map.rst: -------------------------------------------------------------------------------- 1 | Address Maps 2 | ------------ 3 | 4 | .. automodule:: uvm.reg.uvm_reg_map 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_model.rst: -------------------------------------------------------------------------------- 1 | Globals 2 | ------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_model 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_predictor.rst: -------------------------------------------------------------------------------- 1 | Explicit Register Predictor 2 | --------------------------- 3 | 4 | .. automodule:: uvm.reg.uvm_reg_predictor 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_reg_sequence.rst: -------------------------------------------------------------------------------- 1 | Register Sequences 2 | ------------------ 3 | 4 | .. automodule:: uvm.reg.uvm_reg_sequence 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_vreg.rst: -------------------------------------------------------------------------------- 1 | Virtual Registers 2 | ----------------- 3 | 4 | .. automodule:: uvm.reg.uvm_vreg 5 | -------------------------------------------------------------------------------- /docs/source/reg/uvm_vreg_field.rst: -------------------------------------------------------------------------------- 1 | Virtual Fields 2 | -------------- 3 | 4 | .. automodule:: uvm.reg.uvm_vreg_field 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_push_sequencer.rst: -------------------------------------------------------------------------------- 1 | uvm_push_sequencer 2 | ------------------ 3 | 4 | .. automodule:: uvm.seq.uvm_push_sequencer 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_sequence.rst: -------------------------------------------------------------------------------- 1 | uvm_sequence 2 | ------------ 3 | 4 | .. automodule:: uvm.seq.uvm_sequence 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_sequence_base.rst: -------------------------------------------------------------------------------- 1 | uvm_sequence_base 2 | ----------------- 3 | 4 | .. automodule:: uvm.seq.uvm_sequence_base 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_sequence_item.rst: -------------------------------------------------------------------------------- 1 | uvm_sequence_item 2 | ----------------- 3 | 4 | .. automodule:: uvm.seq.uvm_sequence_item 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_sequence_library.rst: -------------------------------------------------------------------------------- 1 | uvm_sequence_library 2 | -------------------- 3 | 4 | .. automodule:: uvm.seq.uvm_sequence_library 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_sequencer.rst: -------------------------------------------------------------------------------- 1 | uvm_sequencer 2 | ------------- 3 | 4 | .. automodule:: uvm.seq.uvm_sequencer 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_sequencer_base.rst: -------------------------------------------------------------------------------- 1 | uvm_sequencer_base 2 | ------------------ 3 | 4 | .. automodule:: uvm.seq.uvm_sequencer_base 5 | -------------------------------------------------------------------------------- /docs/source/seq/uvm_sequencer_param_base.rst: -------------------------------------------------------------------------------- 1 | uvm_sequencer_param_base 2 | ------------------------ 3 | 4 | .. automodule:: uvm.seq.uvm_sequencer_param_base 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_analysis_port.rst: -------------------------------------------------------------------------------- 1 | Analysis Ports 2 | -------------- 3 | 4 | .. automodule:: uvm.tlm1.uvm_analysis_port 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_exports.rst: -------------------------------------------------------------------------------- 1 | Exports 2 | ------- 3 | 4 | .. automodule:: uvm.tlm1.uvm_exports 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_imps.rst: -------------------------------------------------------------------------------- 1 | Imps 2 | ---- 3 | 4 | .. automodule:: uvm.tlm1.uvm_imps 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_ports.rst: -------------------------------------------------------------------------------- 1 | Ports 2 | ----- 3 | 4 | .. automodule:: uvm.tlm1.uvm_ports 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_sqr_connections.rst: -------------------------------------------------------------------------------- 1 | Sequence Item Pull Ports 2 | ------------------------ 3 | 4 | .. automodule:: uvm.tlm1.uvm_sqr_connections 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_sqr_ifs.rst: -------------------------------------------------------------------------------- 1 | Sequencer Base 2 | -------------- 3 | 4 | .. automodule:: uvm.tlm1.uvm_sqr_ifs 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_tlm_fifo_base.rst: -------------------------------------------------------------------------------- 1 | FIFO Base 2 | --------- 3 | 4 | .. automodule:: uvm.tlm1.uvm_tlm_fifo_base 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_tlm_fifos.rst: -------------------------------------------------------------------------------- 1 | FIFO 2 | ---- 3 | 4 | .. automodule:: uvm.tlm1.uvm_tlm_fifos 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_tlm_ifs.rst: -------------------------------------------------------------------------------- 1 | Interfaces 2 | ---------- 3 | 4 | .. automodule:: uvm.tlm1.uvm_tlm_ifs 5 | -------------------------------------------------------------------------------- /docs/source/tlm1/uvm_tlm_req_rsp.rst: -------------------------------------------------------------------------------- 1 | Request-Response Channel 2 | ------------------------ 3 | 4 | .. automodule:: uvm.tlm1.uvm_tlm_req_rsp 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_defines.rst: -------------------------------------------------------------------------------- 1 | Interface Masks 2 | --------------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_defines 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_exports.rst: -------------------------------------------------------------------------------- 1 | TLM2 Export Classes 2 | ------------------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_exports 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_generic_payload.rst: -------------------------------------------------------------------------------- 1 | TLM Generic Payload & Extensions 2 | -------------------------------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_generic_payload 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_ifs.rst: -------------------------------------------------------------------------------- 1 | TLM2 Types 2 | ---------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_ifs 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_imps.rst: -------------------------------------------------------------------------------- 1 | TLM2 imps (interface implementations) 2 | ------------------------------------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_imps 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_ports.rst: -------------------------------------------------------------------------------- 1 | TLM2 ports 2 | ---------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_ports 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_sockets.rst: -------------------------------------------------------------------------------- 1 | TLM Sockets 2 | ----------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_sockets 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_sockets_base.rst: -------------------------------------------------------------------------------- 1 | TLM Socket Base Classes 2 | ----------------------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_sockets_base 5 | -------------------------------------------------------------------------------- /docs/source/tlm2/uvm_tlm2_time.rst: -------------------------------------------------------------------------------- 1 | uvm_tlm_time 2 | --------------------------------------- 3 | 4 | .. automodule:: uvm.tlm2.uvm_tlm2_time 5 | -------------------------------------------------------------------------------- /gen_ctags.sh: -------------------------------------------------------------------------------- 1 | #! /usr/bin/sh 2 | 3 | ctags --fields=+l --languages=python --python-kinds=-iv -R src/ 4 | -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = [ 3 | "setuptools>=42", 4 | "wheel" 5 | ] 6 | build-backend = "setuptools.build_meta" 7 | -------------------------------------------------------------------------------- /pyrightconfig.json: -------------------------------------------------------------------------------- 1 | { 2 | "include": [ 3 | "src" 4 | ], 5 | 6 | "exclude": [ 7 | ".venv", 8 | "**/__pycache__", 9 | "examples", 10 | "test/", 11 | "bin/", 12 | "devscripts/" 13 | ], 14 | 15 | "reportMissingImports": true, 16 | "reportMissingTypeStubs": false, 17 | 18 | "pythonVersion": "3.11", 19 | "pythonPlatform": "Linux" 20 | } -------------------------------------------------------------------------------- /setup.cfg: -------------------------------------------------------------------------------- 1 | [metadata] 2 | # replace with your username: 3 | name = uvm-python 4 | author = Tuomas Poikela 5 | author_email = tuomas.sakari.poikela@gmail.com 6 | description = UVM for Python 7 | long_description = file: README.md 8 | long_description_content_type = text/markdown 9 | url = https://github.com/tpoikela/uvm-python 10 | project_urls = 11 | Bug Tracker = https://github.com/tpoikela/uvm-python/issues 12 | classifiers = 13 | Programming Language :: Python :: 3 14 | License :: Apache 2.0 15 | Operating System :: OS Independent 16 | Topic :: Scientific/Engineering :: Electronic Design Automation (EDA) 17 | 18 | [options] 19 | packages = find: 20 | python_requires = >=3.6 21 | -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | from os import path 2 | from setuptools import setup, find_packages 3 | 4 | version = {} 5 | with open("src/uvm/version.py") as fp: 6 | exec(fp.read(), version) 7 | 8 | 9 | def read_file(fname): 10 | return open(path.join(path.dirname(__file__), fname)).read() 11 | 12 | 13 | setup( 14 | name="uvm-python", 15 | url="https://github.com/tpoikela/uvm-python", 16 | author="Tuomas Poikela", 17 | author_email="tuomas.sakari.poikela@gmail.com", 18 | description=("uvm-python UVM implementation in Python on top of cocotb"), 19 | long_description=read_file("README.md"), 20 | long_description_content_type="text/markdown", 21 | license="Apache 2.0", 22 | keywords=["UVM", "SystemVerilog", "Verilog", "RTL", "Coverage"], 23 | packages=find_packages(where="src"), 24 | package_dir={"": "src"}, 25 | setup_requires=["setuptools_scm",], 26 | python_requires=">=3.8", 27 | version=version['__version__'], 28 | install_requires=[ 29 | #"cocotb @ git+https://github.com/cocotb/cocotb@88bca3c9a9515c9ed399ca6dcf569696fded23f7#egg=cocotb", 30 | "cocotb>=1.9.2", 31 | "cocotb-bus>=0.1.1", 32 | "cocotb-coverage>=1.1.0", 33 | "regex>=2019.11.1" 34 | ], 35 | platforms="any", 36 | classifiers=[ 37 | "Programming Language :: Python :: 3", 38 | "License :: OSI Approved :: Apache Software License", 39 | "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", 40 | ], 41 | ) 42 | -------------------------------------------------------------------------------- /src/uvm/__init__.py: -------------------------------------------------------------------------------- 1 | # flake8: noqa 2 | from .base import * 3 | from .macros import * 4 | from .comps import * 5 | from .dap import * 6 | from .reg import * 7 | from .seq import * 8 | from .tlm1 import * 9 | from .tlm2 import * 10 | -------------------------------------------------------------------------------- /src/uvm/base/__init__.py: -------------------------------------------------------------------------------- 1 | #from .uvm_barrier import * 2 | from .uvm_bottomup_phase import * 3 | from .uvm_callback import * 4 | from .uvm_cmdline_processor import * 5 | from .uvm_common_phases import * 6 | from .uvm_component import * 7 | from .uvm_config_db import * 8 | from .uvm_coreservice import * 9 | from .uvm_debug import * 10 | from .uvm_domain import * 11 | from .uvm_event import * 12 | from .uvm_factory import * 13 | from .uvm_global_vars import * 14 | from .uvm_globals import * 15 | from .uvm_mailbox import * 16 | from .uvm_misc import * 17 | from .uvm_object import * 18 | from .uvm_object_globals import * 19 | from .uvm_objection import * 20 | from .uvm_phase import * 21 | from .uvm_pool import * 22 | from .uvm_port_base import * 23 | from .uvm_printer import * 24 | from .uvm_queue import * 25 | from .uvm_recorder import * 26 | from .uvm_registry import * 27 | from .uvm_report_catcher import * 28 | from .uvm_report_handler import * 29 | from .uvm_report_message import * 30 | from .uvm_report_object import * 31 | from .uvm_report_server import * 32 | from .uvm_resource import * 33 | from .uvm_resource_db import * 34 | from .uvm_root import * 35 | from .uvm_runtime_phases import * 36 | from .uvm_scope_stack import * 37 | from .uvm_server import * 38 | from .uvm_spell_chkr import * 39 | from .uvm_task_phase import * 40 | from .uvm_topdown_phase import * 41 | from .uvm_transaction import * 42 | from .sv import * 43 | -------------------------------------------------------------------------------- /src/uvm/base/uvm_exceptions.py: -------------------------------------------------------------------------------- 1 | 2 | class RandomizeError(Exception): 3 | """ 4 | Exception which is thrown when constrained randomization 5 | fails 6 | """ 7 | pass 8 | 9 | 10 | class TLMError(Exception): 11 | """ 12 | Exception which is thrown when nonblocking TLM method fails 13 | fails 14 | """ 15 | pass 16 | 17 | class UVMFinishError(Exception): 18 | """ 19 | Exception which is thrown when the test is finished 20 | """ 21 | pass 22 | -------------------------------------------------------------------------------- /src/uvm/base/uvm_global_vars.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_printer import UVMTablePrinter, UVMTreePrinter 3 | from .uvm_comparer import UVMComparer 4 | from .uvm_packer import UVMPacker 5 | 6 | uvm_default_table_printer = UVMTablePrinter() 7 | 8 | uvm_default_tree_printer = UVMTreePrinter() 9 | 10 | uvm_default_printer = uvm_default_table_printer 11 | 12 | uvm_default_comparer = UVMComparer() 13 | 14 | uvm_default_packer = UVMPacker() 15 | -------------------------------------------------------------------------------- /src/uvm/base/uvm_server.py: -------------------------------------------------------------------------------- 1 | 2 | class UVMDefaultServer: 3 | 4 | def __init__(self): 5 | self.m_quit_count = 0 6 | self.m_max_quit_count = 0 7 | self.max_quit_overridable = True 8 | self.m_severity_count = {} 9 | self.m_id_count = {} 10 | ## uvm_tr_database m_message_db; 11 | ## uvm_tr_stream m_streams[string][string]; // ro.name,rh.name 12 | 13 | -------------------------------------------------------------------------------- /src/uvm/base/uvm_version.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2007-2010 Mentor Graphics Corporation 3 | #// Copyright 2007-2011 Cadence Design Systems, Inc. 4 | #// Copyright 2010-2011 Synopsys, Inc. 5 | #// Copyright 2013-2014 NVIDIA Corporation 6 | #// Copyright 2019 Tuomas Poikela 7 | #// All Rights Reserved Worldwide 8 | #// 9 | #// Licensed under the Apache License, Version 2.0 (the 10 | #// "License"); you may not use this file except in 11 | #// compliance with the License. You may obtain a copy of 12 | #// the License at 13 | #// 14 | #// http://www.apache.org/licenses/LICENSE-2.0 15 | #// 16 | #// Unless required by applicable law or agreed to in 17 | #// writing, software distributed under the License is 18 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 19 | #// CONDITIONS OF ANY KIND, either express or implied. See 20 | #// the License for the specific language governing 21 | #// permissions and limitations under the License. 22 | #//---------------------------------------------------------------------- 23 | 24 | from .. import version 25 | 26 | uvm_mgc_copyright = "(C) 2007-2014 Mentor Graphics Corporation" 27 | uvm_cdn_copyright = "(C) 2007-2014 Cadence Design Systems, Inc." 28 | uvm_snps_copyright = "(C) 2006-2014 Synopsys, Inc." 29 | uvm_cy_copyright = "(C) 2011-2013 Cypress Semiconductor Corp." 30 | uvm_nv_copyright = "(C) 2013-2014 NVIDIA Corporation" 31 | uvm_revision = "uvm-python {} (Ported from UVM 1.2)".format(version.__version__) 32 | uvm_tpoikela_copyright = "(C) 2019-2021 Tuomas Poikela (tpoikela)" 33 | 34 | def uvm_revision_string(): 35 | return uvm_revision 36 | -------------------------------------------------------------------------------- /src/uvm/comps/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_agent import * 3 | from .uvm_algorithmic_comparator import * 4 | from .uvm_comps import * 5 | from .uvm_driver import * 6 | from .uvm_env import * 7 | from .uvm_in_order_comparator import * 8 | from .uvm_monitor import * 9 | from .uvm_pair import * 10 | from .uvm_policies import * 11 | from .uvm_push_driver import * 12 | from .uvm_random_stimulus import * 13 | from .uvm_scoreboard import * 14 | from .uvm_subscriber import * 15 | from .uvm_test import * 16 | -------------------------------------------------------------------------------- /src/uvm/comps/uvm_comps.py: -------------------------------------------------------------------------------- 1 | #// 2 | #//------------------------------------------------------------------------------ 3 | #// Copyright 2007-2011 Mentor Graphics Corporation 4 | #// Copyright 2007-2010 Cadence Design Systems, Inc. 5 | #// Copyright 2010 Synopsys, Inc. 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #//------------------------------------------------------------------------------ 22 | # 23 | # `include "comps/uvm_pair.svh" 24 | # `include "comps/uvm_policies.svh" 25 | # `include "comps/uvm_in_order_comparator.svh" 26 | # `include "comps/uvm_algorithmic_comparator.svh" 27 | # `include "comps/uvm_random_stimulus.svh" 28 | # `include "comps/uvm_subscriber.svh" 29 | # 30 | # `include "comps/uvm_monitor.svh" 31 | # `include "comps/uvm_driver.svh" 32 | # `include "comps/uvm_push_driver.svh" 33 | # `include "comps/uvm_scoreboard.svh" 34 | # `include "comps/uvm_agent.svh" 35 | # `include "comps/uvm_env.svh" 36 | # `include "comps/uvm_test.svh" 37 | -------------------------------------------------------------------------------- /src/uvm/dap/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_get_to_lock_dap import * 3 | from .uvm_set_before_get_dap import * 4 | from .uvm_set_get_dap_base import * 5 | from .uvm_simple_lock_dap import * 6 | -------------------------------------------------------------------------------- /src/uvm/dap/uvm_dap.py: -------------------------------------------------------------------------------- 1 | #// 2 | #//------------------------------------------------------------------------------ 3 | #// Copyright 2007-2011 Mentor Graphics Corporation 4 | #// Copyright 2007-2011 Cadence Design Systems, Inc. 5 | #// Copyright 2010-2011 Synopsys, Inc. 6 | #// Copyright 2013 NVIDIA Corporation 7 | #// All Rights Reserved Worldwide 8 | #// 9 | #// Licensed under the Apache License, Version 2.0 (the 10 | #// "License"); you may not use this file except in 11 | #// compliance with the License. You may obtain a copy of 12 | #// the License at 13 | #// 14 | #// http://www.apache.org/licenses/LICENSE-2.0 15 | #// 16 | #// Unless required by applicable law or agreed to in 17 | #// writing, software distributed under the License is 18 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 19 | #// CONDITIONS OF ANY KIND, either express or implied. See 20 | #// the License for the specific language governing 21 | #// permissions and limitations under the License. 22 | #//------------------------------------------------------------------------------ 23 | # 24 | #`ifndef UVM_DAP_SVH 25 | # `define UVM_DAP_SVH 26 | # 27 | #// Set/Get DAPS 28 | # `include "dap/uvm_set_get_dap_base.svh" 29 | # `include "dap/uvm_simple_lock_dap.svh" 30 | # `include "dap/uvm_get_to_lock_dap.svh" 31 | # `include "dap/uvm_set_before_get_dap.svh" 32 | # 33 | #`endif // UVM_DAP_SVH 34 | # 35 | -------------------------------------------------------------------------------- /src/uvm/dpi/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_hdl import * 3 | -------------------------------------------------------------------------------- /src/uvm/macros/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_global_defines import * 3 | from .uvm_message_defines import * 4 | from .uvm_object_defines import * 5 | from .uvm_sequence_defines import * 6 | from .uvm_reg_defines import * 7 | from .uvm_callback_defines import * 8 | -------------------------------------------------------------------------------- /src/uvm/reg/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_mem import * 3 | from .uvm_mem_mam import * 4 | from .uvm_reg import * 5 | from .uvm_reg_adapter import * 6 | from .uvm_reg_backdoor import * 7 | from .uvm_reg_block import * 8 | from .uvm_reg_cbs import * 9 | from .uvm_reg_field import * 10 | from .uvm_reg_fifo import * 11 | from .uvm_reg_file import * 12 | from .uvm_reg_indirect import * 13 | from .uvm_reg_item import * 14 | from .uvm_reg_map import * 15 | from .uvm_reg_model import * 16 | from .uvm_reg_predictor import * 17 | from .uvm_reg_sequence import * 18 | from .uvm_vreg import * 19 | from .uvm_vreg_field import * 20 | from .sequences import * 21 | -------------------------------------------------------------------------------- /src/uvm/reg/sequences/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_mem_access_seq import * 3 | from .uvm_mem_walk_seq import * 4 | from .uvm_reg_access_seq import * 5 | from .uvm_reg_bit_bash_seq import * 6 | from .uvm_reg_hw_reset_seq import * 7 | from .uvm_reg_mem_built_in_seq import * 8 | from .uvm_reg_mem_hdl_paths_seq import * 9 | from .uvm_reg_mem_shared_access_seq import * 10 | -------------------------------------------------------------------------------- /src/uvm/seq/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | 3 | from .uvm_sequence_item import * 4 | from .uvm_sequence import * 5 | from .uvm_sequencer import * 6 | -------------------------------------------------------------------------------- /src/uvm/seq/uvm_sequencer_analysis_fifo.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2007-2011 Mentor Graphics Corporation 3 | #// Copyright 2007-2010 Cadence Design Systems, Inc. 4 | #// Copyright 2010 Synopsys, Inc. 5 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #//---------------------------------------------------------------------- 22 | 23 | from ..tlm1 import (UVMTLMFIFO, UVMAnalysisImp) 24 | from ..macros import (uvm_fatal) 25 | 26 | 27 | class UVMSequencerAnalysisFIFO(UVMTLMFIFO): 28 | 29 | # uvm_analysis_imp #(RSP, UVMSequencerAnalysisFIFO #(RSP)) analysis_export 30 | # uvm_sequencer_base sequencer_ptr 31 | 32 | 33 | def __init__(self, name, parent=None): 34 | super().__init__(name, parent, 0) 35 | self.analysis_export = UVMAnalysisImp("analysis_export", self) 36 | self.sequencer_ptr = None 37 | 38 | 39 | def write(self, t): 40 | if self.sequencer_ptr is None: 41 | uvm_fatal("SEQRNULL", "The sequencer pointer is None when attempting a write") 42 | self.sequencer_ptr.analysis_write(t) 43 | -------------------------------------------------------------------------------- /src/uvm/tlm1/__init__.py: -------------------------------------------------------------------------------- 1 | # flake8: noqa 2 | from .uvm_analysis_port import * 3 | from .uvm_exports import * 4 | from .uvm_imps import * 5 | from .uvm_ports import * 6 | from .uvm_sqr_connections import * 7 | from .uvm_sqr_ifs import * 8 | from .uvm_tlm_fifo_base import * 9 | from .uvm_tlm_fifos import * 10 | from .uvm_tlm_ifs import * 11 | from .uvm_tlm_imps import * 12 | from .uvm_tlm import * 13 | from .uvm_tlm_req_rsp import * 14 | -------------------------------------------------------------------------------- /src/uvm/tlm1/uvm_tlm.py: -------------------------------------------------------------------------------- 1 | # 2 | #---------------------------------------------------------------------- 3 | # Copyright 2007-2011 Mentor Graphics Corporation 4 | # Copyright 2007-2010 Cadence Design Systems, Inc. 5 | # Copyright 2010 Synopsys, Inc. 6 | # All Rights Reserved Worldwide 7 | # 8 | # Licensed under the Apache License, Version 2.0 (the 9 | # "License"); you may not use this file except in 10 | # compliance with the License. You may obtain a copy of 11 | # the License at 12 | # 13 | # http://www.apache.org/licenses/LICENSE-2.0 14 | # 15 | # Unless required by applicable law or agreed to in 16 | # writing, software distributed under the License is 17 | # distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | # CONDITIONS OF ANY KIND, either express or implied. See 19 | # the License for the specific language governing 20 | # permissions and limitations under the License. 21 | #---------------------------------------------------------------------- 22 | 23 | # File list only for reference at the moment: 24 | 25 | #`include "tlm1/uvm_tlm_ifs.svh" 26 | #`include "tlm1/uvm_sqr_ifs.svh" 27 | #`include "base/uvm_port_base.svh" 28 | # 29 | #`include "tlm1/uvm_tlm_imps.svh" 30 | # 31 | #`include "tlm1/uvm_imps.svh" 32 | #`include "tlm1/uvm_ports.svh" 33 | #`include "tlm1/uvm_exports.svh" 34 | #`include "tlm1/uvm_analysis_port.svh" 35 | # 36 | #`include "tlm1/uvm_tlm_fifo_base.svh" 37 | #`include "tlm1/uvm_tlm_fifos.svh" 38 | #`include "tlm1/uvm_tlm_req_rsp.svh" 39 | # 40 | #`include "tlm1/uvm_sqr_connections.svh" 41 | # 42 | -------------------------------------------------------------------------------- /src/uvm/tlm2/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_tlm2_defines import * 3 | from .uvm_tlm2_exports import * 4 | from .uvm_tlm2_generic_payload import * 5 | from .uvm_tlm2_ifs import * 6 | from .uvm_tlm2_imps import * 7 | from .uvm_tlm2_ports import * 8 | from .uvm_tlm2_sockets import * 9 | from .uvm_tlm2_sockets_base import * 10 | from .uvm_tlm_time import * 11 | -------------------------------------------------------------------------------- /src/uvm/tlm2/uvm_tlm2.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2010-2011 Mentor Graphics Corporation 3 | #// Copyright 2010-2017 Synopsys, Inc. 4 | #// Copyright 2010-2018 Cadence Design Systems, Inc. 5 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #//---------------------------------------------------------------------- 22 | # 23 | # `include "tlm2/uvm_tlm2_defines.svh" 24 | # `include "tlm2/uvm_tlm_time.svh" 25 | # `include "tlm2/uvm_tlm2_generic_payload.svh" 26 | # `include "tlm2/uvm_tlm2_ifs.svh" 27 | # `include "tlm2/uvm_tlm2_imps.svh" 28 | # `include "tlm2/uvm_tlm2_ports.svh" 29 | # `include "tlm2/uvm_tlm2_exports.svh" 30 | # `include "tlm2/uvm_tlm2_sockets_base.svh" 31 | # `include "tlm2/uvm_tlm2_sockets.svh" 32 | -------------------------------------------------------------------------------- /src/uvm/uvm_macros.py: -------------------------------------------------------------------------------- 1 | 2 | from .uvm_pkg import m_uvm_string_queue_join 3 | 4 | def uvm_typename(obj): 5 | name = "" 6 | if hasattr(obj, '__class__'): 7 | name = obj.__class__ 8 | else: 9 | name = obj 10 | return name 11 | 12 | def UVM_STRING_QUEUE_STREAMING_PACK(q): 13 | return m_uvm_string_queue_join(q) 14 | -------------------------------------------------------------------------------- /src/uvm/uvm_pkg.py: -------------------------------------------------------------------------------- 1 | # flake8: noqa 2 | from .base.uvm_misc import * 3 | -------------------------------------------------------------------------------- /src/uvm/version.py: -------------------------------------------------------------------------------- 1 | __version__ = "0.4.0" 2 | -------------------------------------------------------------------------------- /test/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | build/ 3 | results.xml 4 | sim_build/ 5 | -------------------------------------------------------------------------------- /test/examples/integrated/Makefile: -------------------------------------------------------------------------------- 1 | 2 | test: test-ubus 3 | 4 | test-ubus: 5 | make -C ubus/examples UVM_TEST=test_read_modify_write COCOTB_RESULTS_FILE=results_ubus.xml RANDOM_SEED=1679306404 6 | make -C ubus/examples UVM_TEST=test_2m_4s COCOTB_RESULTS_FILE=results_ubus_2m_4s.xml RANDOM_SEED=1679306635 7 | 8 | # TODO 9 | test-codec: 10 | make -C codec/ 11 | -------------------------------------------------------------------------------- /test/examples/integrated/README.txt: -------------------------------------------------------------------------------- 1 | This directory contains examples of complete verification components 2 | and verification environments. As such, they should be UVM compliant. 3 | 4 | See the $UVM_HOME/examples/simple directory for simpler examples 5 | focus on illustrating specific features of the UVM library. 6 | 7 | 8 | -------------------------------------------------------------------------------- /test/examples/integrated/apb/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .apb_if import apb_if 3 | -------------------------------------------------------------------------------- /test/examples/integrated/apb/apb.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `ifndef APB__SV 24 | `define APB__SV 25 | 26 | `include "apb_if.sv" 27 | `include "uvm_macros.svh" 28 | 29 | package apb_pkg; 30 | 31 | import uvm_pkg::*; 32 | 33 | typedef virtual apb_if apb_vif; 34 | 35 | typedef class apb_agent; 36 | 37 | `include "apb_rw.sv" 38 | `include "apb_config.sv" 39 | `include "apb_master.sv" 40 | `include "apb_monitor.sv" 41 | `include "apb_sequencer.sv" 42 | `include "apb_agent.sv" 43 | endpackage 44 | 45 | `endif 46 | -------------------------------------------------------------------------------- /test/examples/integrated/apb/apb_config.py: -------------------------------------------------------------------------------- 1 | #// 2 | #// ------------------------------------------------------------- 3 | #// Copyright 2004-2011 Synopsys, Inc. 4 | #// Copyright 2010 Mentor Graphics Corporation 5 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #// ------------------------------------------------------------- 22 | 23 | from uvm.base.uvm_object import * 24 | from uvm.macros import * 25 | 26 | 27 | class apb_config(UVMObject): 28 | 29 | 30 | def __init__(self, name="apb_config"): 31 | super().__init__(name) 32 | self.vif = None # apb_if 33 | 34 | 35 | uvm_object_utils(apb_config) 36 | -------------------------------------------------------------------------------- /test/examples/integrated/apb/apb_config.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | 24 | class apb_config extends uvm_object; 25 | 26 | `uvm_object_utils(apb_config) 27 | virtual apb_if vif; 28 | 29 | 30 | function new(string name="apb_config"); 31 | super.new(name); 32 | endfunction 33 | 34 | endclass 35 | 36 | -------------------------------------------------------------------------------- /test/examples/integrated/apb/apb_sequencer.py: -------------------------------------------------------------------------------- 1 | #// 2 | #// ------------------------------------------------------------- 3 | #// Copyright 2004-2011 Synopsys, Inc. 4 | #// Copyright 2010 Mentor Graphics Corporation 5 | #// Copyright 2010 Cadence Design Systems, Inc. 6 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 7 | #// All Rights Reserved Worldwide 8 | #// 9 | #// Licensed under the Apache License, Version 2.0 (the 10 | #// "License"); you may not use this file except in 11 | #// compliance with the License. You may obtain a copy of 12 | #// the License at 13 | #// 14 | #// http://www.apache.org/licenses/LICENSE-2.0 15 | #// 16 | #// Unless required by applicable law or agreed to in 17 | #// writing, software distributed under the License is 18 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 19 | #// CONDITIONS OF ANY KIND, either express or implied. See 20 | #// the License for the specific language governing 21 | #// permissions and limitations under the License. 22 | #// ------------------------------------------------------------- 23 | #// 24 | 25 | 26 | from uvm.seq.uvm_sequencer import UVMSequencer 27 | from uvm.macros import uvm_component_utils 28 | 29 | 30 | class apb_sequencer(UVMSequencer): # (apb_rw) 31 | 32 | def __init__(self, name, parent=None): 33 | super().__init__(name, parent) 34 | 35 | 36 | uvm_component_utils(apb_sequencer) 37 | -------------------------------------------------------------------------------- /test/examples/integrated/apb/apb_sequencer.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // Copyright 2010 Cadence Design Systems, Inc. 6 | // All Rights Reserved Worldwide 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in 10 | // compliance with the License. You may obtain a copy of 11 | // the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in 16 | // writing, software distributed under the License is 17 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | // CONDITIONS OF ANY KIND, either express or implied. See 19 | // the License for the specific language governing 20 | // permissions and limitations under the License. 21 | // ------------------------------------------------------------- 22 | // 23 | 24 | `ifndef APB_SEQUENCER__SV 25 | `define APB_SEQUENCER__SV 26 | 27 | class apb_sequencer extends uvm_sequencer #(apb_rw); 28 | 29 | `uvm_component_utils(apb_sequencer) 30 | 31 | function new(input string name, uvm_component parent=null); 32 | super.new(name, parent); 33 | endfunction : new 34 | 35 | endclass : apb_sequencer 36 | 37 | `endif 38 | 39 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for testing python-uvm 2 | 3 | # Usage: 4 | # To execute tests in given file using given verilog source, you can do: 5 | # >$ make MODULE=py_mod_name VLOG=hdl/my_vlog.v SIM_ARGS='-aaa +bbb' 6 | 7 | 8 | include ../../simple/MakefileCommon.mk 9 | PYTHONPATH := $(WPWD)/../../integrated:$(PYTHONPATH) 10 | 11 | # SIM_ARGS = "" 12 | TOPLEVEL := dut 13 | MODULE ?= test_codec 14 | 15 | ifeq ($(TOPLEVEL_LANG),verilog) 16 | VERILOG_SOURCES = dut.sv 17 | else 18 | $(error "A valid value (verilog) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)") 19 | endif 20 | 21 | ifneq ($(UVM_TEST),) 22 | PLUSARGS += +UVM_TESTNAME=$(UVM_TEST) 23 | else 24 | PLUSARGS += +UVM_TESTNAME=test 25 | endif 26 | 27 | include $(shell cocotb-config --makefiles)/Makefile.sim 28 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tpoikela/uvm-python/2301431a22ddec14abebb8df38f35c6dcdefd241/test/examples/integrated/codec/__init__.py -------------------------------------------------------------------------------- /test/examples/integrated/codec/block_diagram.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tpoikela/uvm-python/2301431a22ddec14abebb8df38f35c6dcdefd241/test/examples/integrated/codec/block_diagram.pdf -------------------------------------------------------------------------------- /test/examples/integrated/codec/testlib.py: -------------------------------------------------------------------------------- 1 | #// 2 | #// ------------------------------------------------------------- 3 | #// Copyright 2011 Synopsys, Inc. 4 | #// Copyright 2010-2011 Mentor Graphics Corporation 5 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #// ------------------------------------------------------------- 22 | #// 23 | # 24 | #class hw_reset_test(test): 25 | # 26 | # `uvm_component_utils(hw_reset_test) 27 | # 28 | # def __init__(self, name, parent=None) 29 | # super().__init__(name, parent) 30 | # endfunction 31 | # 32 | # local bit once = 1 33 | #async 34 | # def main_phase(self, phase): 35 | # if (once): 36 | # once = 0 37 | # phase.raise_objection(self) 38 | # repeat (100 * 8) @(posedge env.vif.sclk) 39 | # // This will clear the objection 40 | # uvm_info("TEST", "Jumping back to reset phase", UVM_NONE) 41 | # phase.jump(uvm_reset_phase::get()) 42 | # end 43 | # endtask 44 | # 45 | from uvm.macros import * 46 | #endclass 47 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/testlib.svh: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2011 Synopsys, Inc. 4 | // Copyright 2010-2011 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | class hw_reset_test extends test; 24 | 25 | `uvm_component_utils(hw_reset_test) 26 | 27 | function new(string name, uvm_component parent = null); 28 | super.new(name, parent); 29 | endfunction 30 | 31 | local bit once = 1; 32 | task main_phase(uvm_phase phase); 33 | if (once) begin 34 | once = 0; 35 | phase.raise_objection(this); 36 | repeat (100 * 8) @(posedge env.vif.sclk); 37 | // This will clear the objection 38 | `uvm_info("TEST", "Jumping back to reset phase", UVM_NONE); 39 | phase.jump(uvm_reset_phase::get()); 40 | end 41 | endtask 42 | 43 | endclass 44 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/vip/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .vip_if import * 3 | from .vip_sequencer import vip_sequencer 4 | from .vip_agent import vip_agent 5 | from .vip_seqlib import * 6 | from .vip_tr import * 7 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/vip/vip_if.py: -------------------------------------------------------------------------------- 1 | #// 2 | #// ------------------------------------------------------------- 3 | #// Copyright 2011 Synopsys, Inc. 4 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 5 | #// All Rights Reserved Worldwide 6 | #// 7 | #// Licensed under the Apache License, Version 2.0 (the 8 | #// "License"); you may not use this file except in 9 | #// compliance with the License. You may obtain a copy of 10 | #// the License at 11 | #// 12 | #// http://www.apache.org/licenses/LICENSE-2.0 13 | #// 14 | #// Unless required by applicable law or agreed to in 15 | #// writing, software distributed under the License is 16 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | #// CONDITIONS OF ANY KIND, either express or implied. See 18 | #// the License for the specific language governing 19 | #// permissions and limitations under the License. 20 | #// ------------------------------------------------------------- 21 | #// 22 | 23 | 24 | class vip_tx_if(): 25 | 26 | def __init__(self, clk, Tx): 27 | self.clk = clk 28 | self.Tx = Tx 29 | 30 | class vip_rx_if(): 31 | 32 | def __init__(self, clk, Rx): 33 | self.clk = clk 34 | self.Rx = Rx 35 | 36 | class vip_if(): 37 | 38 | def __init__(self, clk, Tx, Rx): 39 | self.clk = clk 40 | self.Tx = Tx 41 | self.Rx = Rx 42 | 43 | self.tx = vip_tx_if(self.clk, self.Tx) 44 | self.rx = vip_rx_if(self.clk, self.Rx) 45 | self.tx_mon = vip_rx_if(self.clk, self.Tx) 46 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/vip/vip_if.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2011 Synopsys, Inc. 4 | // All Rights Reserved Worldwide 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the 7 | // "License"); you may not use this file except in 8 | // compliance with the License. You may obtain a copy of 9 | // the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in 14 | // writing, software distributed under the License is 15 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | // CONDITIONS OF ANY KIND, either express or implied. See 17 | // the License for the specific language governing 18 | // permissions and limitations under the License. 19 | // ------------------------------------------------------------- 20 | // 21 | 22 | 23 | `ifndef VIP_IF__SV 24 | `define VIP_IF__SV 25 | 26 | `timescale 1ns/1ns 27 | 28 | 29 | interface vip_tx_if(input bit clk, 30 | output reg Tx); 31 | endinterface: vip_tx_if 32 | 33 | 34 | interface vip_rx_if(input bit clk, 35 | input reg Rx); 36 | endinterface: vip_rx_if 37 | 38 | 39 | interface vip_if(input bit clk, 40 | output reg Tx, 41 | input wire Rx); 42 | 43 | vip_tx_if tx(clk, Tx); 44 | vip_rx_if rx(clk, Rx); 45 | vip_rx_if tx_mon(clk, Tx); 46 | 47 | endinterface: vip_if 48 | 49 | `endif 50 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/vip/vip_sequencer.py: -------------------------------------------------------------------------------- 1 | 2 | 3 | from uvm import * 4 | 5 | class vip_sequencer(UVMSequencer): 6 | 7 | def __init__(self, name, parent): 8 | super().__init__(name, parent) 9 | 10 | uvm_component_utils(vip_sequencer) 11 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/vip/vip_tr.py: -------------------------------------------------------------------------------- 1 | #// 2 | #// ------------------------------------------------------------- 3 | #// Copyright 2011 Synopsys, Inc. 4 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 5 | #// All Rights Reserved Worldwide 6 | #// 7 | #// Licensed under the Apache License, Version 2.0 (the 8 | #// "License"); you may not use this file except in 9 | #// compliance with the License. You may obtain a copy of 10 | #// the License at 11 | #// 12 | #// http://www.apache.org/licenses/LICENSE-2.0 13 | #// 14 | #// Unless required by applicable law or agreed to in 15 | #// writing, software distributed under the License is 16 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | #// CONDITIONS OF ANY KIND, either express or implied. See 18 | #// the License for the specific language governing 19 | #// permissions and limitations under the License. 20 | #// ------------------------------------------------------------- 21 | #// 22 | 23 | from uvm import * 24 | 25 | 26 | class vip_tr(UVMSequenceItem): 27 | 28 | def __init__(self, name="vip_tr"): 29 | super().__init__(name) 30 | self.chr = 0x0 31 | self.rand('chr', range(0, 256)) 32 | 33 | 34 | def convert2string(self): 35 | return sv.sformatf("0x%0h", self.chr) 36 | 37 | 38 | uvm_object_utils_begin(vip_tr) 39 | uvm_field_int('vip_tr', UVM_ALL_ON) 40 | uvm_object_utils_end(vip_tr) 41 | -------------------------------------------------------------------------------- /test/examples/integrated/codec/vip/vip_tr.svh: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2011 Synopsys, Inc. 4 | // All Rights Reserved Worldwide 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the 7 | // "License"); you may not use this file except in 8 | // compliance with the License. You may obtain a copy of 9 | // the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in 14 | // writing, software distributed under the License is 15 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | // CONDITIONS OF ANY KIND, either express or implied. See 17 | // the License for the specific language governing 18 | // permissions and limitations under the License. 19 | // ------------------------------------------------------------- 20 | // 21 | 22 | 23 | class vip_tr extends uvm_sequence_item; 24 | 25 | rand bit [7:0] chr; 26 | `uvm_object_utils_begin(vip_tr) 27 | `uvm_field_int(chr, UVM_ALL_ON); 28 | `uvm_object_utils_end 29 | 30 | function new (string name = "vip_tr"); 31 | super.new(name); 32 | endfunction 33 | 34 | function string convert2string(); 35 | return $sformatf("0x%0h", chr); 36 | endfunction 37 | 38 | endclass: vip_tr 39 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/examples/vsim.do: -------------------------------------------------------------------------------- 1 | onerror resume 2 | onbreak resume 3 | onElabError resume 4 | run -all 5 | exit 6 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/py/ubus_master_sequencer.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2007-2011 Mentor Graphics Corporation 3 | #// Copyright 2007-2010 Cadence Design Systems, Inc. 4 | #// Copyright 2010 Synopsys, Inc. 5 | #// Copyright 2019 Tuomas Poikela (tpoikela) 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #//---------------------------------------------------------------------- 22 | 23 | from uvm.seq import UVMSequencer 24 | from uvm.tlm1 import UVMBlockingPeekPort 25 | from uvm.macros import uvm_component_utils 26 | 27 | #//------------------------------------------------------------------------------ 28 | #// 29 | #// CLASS: ubus_master_sequencer 30 | #// 31 | #//------------------------------------------------------------------------------ 32 | 33 | class ubus_master_sequencer(UVMSequencer): 34 | 35 | def __init__(self, name, parent): 36 | UVMSequencer.__init__(self, name, parent) 37 | self.addr_ph_port = UVMBlockingPeekPort("addr_ph_port", self) 38 | #endclass : ubus_master_sequencer 39 | uvm_component_utils(ubus_master_sequencer) 40 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/py/ubus_pkg.py: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | 22 | 23 | package ubus_pkg; 24 | 25 | import uvm_pkg::*; 26 | 27 | `include "uvm_macros.svh" 28 | 29 | typedef uvm_config_db#(virtual ubus_if) ubus_vif_config; 30 | typedef virtual ubus_if ubus_vif; 31 | 32 | `include "ubus_transfer.sv" 33 | 34 | `include "ubus_master_monitor.sv" 35 | `include "ubus_master_sequencer.sv" 36 | `include "ubus_master_driver.sv" 37 | `include "ubus_master_agent.sv" 38 | 39 | `include "ubus_slave_monitor.sv" 40 | `include "ubus_slave_sequencer.sv" 41 | `include "ubus_slave_driver.sv" 42 | `include "ubus_slave_agent.sv" 43 | 44 | `include "ubus_bus_monitor.sv" 45 | 46 | `include "ubus_env.sv" 47 | 48 | endpackage: ubus_pkg 49 | 50 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/py/ubus_version.svh: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | `define UBUS_KIT_VERSION "1.0ea" 22 | `define UBUS_KIT_DATE "2010-04-30" 23 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/sv/ubus_master_sequencer.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2011 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | 22 | //------------------------------------------------------------------------------ 23 | // 24 | // CLASS: ubus_master_sequencer 25 | // 26 | //------------------------------------------------------------------------------ 27 | 28 | class ubus_master_sequencer extends uvm_sequencer #(ubus_transfer); 29 | 30 | `uvm_component_utils(ubus_master_sequencer) 31 | 32 | function new (string name, uvm_component parent); 33 | super.new(name, parent); 34 | endfunction : new 35 | 36 | endclass : ubus_master_sequencer 37 | 38 | 39 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/sv/ubus_pkg.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | 22 | 23 | package ubus_pkg; 24 | 25 | import uvm_pkg::*; 26 | 27 | `include "uvm_macros.svh" 28 | 29 | typedef uvm_config_db#(virtual ubus_if) ubus_vif_config; 30 | typedef virtual ubus_if ubus_vif; 31 | 32 | `include "ubus_transfer.sv" 33 | 34 | `include "ubus_master_monitor.sv" 35 | `include "ubus_master_sequencer.sv" 36 | `include "ubus_master_driver.sv" 37 | `include "ubus_master_agent.sv" 38 | 39 | `include "ubus_slave_monitor.sv" 40 | `include "ubus_slave_sequencer.sv" 41 | `include "ubus_slave_driver.sv" 42 | `include "ubus_slave_agent.sv" 43 | 44 | `include "ubus_bus_monitor.sv" 45 | 46 | `include "ubus_env.sv" 47 | 48 | endpackage: ubus_pkg 49 | 50 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/sv/ubus_slave_sequencer.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2011 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | 22 | //------------------------------------------------------------------------------ 23 | // 24 | // CLASS: ubus_slave_sequencer 25 | // 26 | //------------------------------------------------------------------------------ 27 | 28 | class ubus_slave_sequencer extends uvm_sequencer #(ubus_transfer); 29 | 30 | // TLM port to peek the address phase from the slave monitor 31 | uvm_blocking_peek_port#(ubus_transfer) addr_ph_port; 32 | 33 | // Provide implementations of virtual methods such as get_type_name and create 34 | `uvm_component_utils(ubus_slave_sequencer) 35 | 36 | 37 | function new (string name, uvm_component parent); 38 | super.new(name, parent); 39 | addr_ph_port = new("addr_ph_port", this); 40 | endfunction : new 41 | 42 | endclass : ubus_slave_sequencer 43 | 44 | 45 | -------------------------------------------------------------------------------- /test/examples/integrated/ubus/sv/ubus_version.svh: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | `define UBUS_KIT_VERSION "1.0ea" 22 | `define UBUS_KIT_DATE "2010-04-30" 23 | -------------------------------------------------------------------------------- /test/examples/minimal/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal Makefile for uvm-python minimal example 2 | TOPLEVEL_LANG ?= verilog 3 | VERILOG_SOURCES ?= new_dut.sv 4 | TOPLEVEL := new_dut 5 | MODULE ?= new_test 6 | 7 | PYTHONPATH := ../../../src:$(PYTHONPATH) 8 | export PYTHONPATH 9 | 10 | include $(shell cocotb-config --makefiles)/Makefile.sim 11 | -------------------------------------------------------------------------------- /test/examples/minimal/new_dut.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module new_dut(input clk, input rst, output[7:0] byte_out); 3 | assign byte_out = 8'hAB; 4 | endmodule: new_dut 5 | -------------------------------------------------------------------------------- /test/examples/minimal/new_test.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from cocotb.triggers import Timer 3 | from uvm import * 4 | 5 | class NewTest(UVMTest): 6 | 7 | async def run_phase(self, phase): 8 | phase.raise_objection(self) 9 | await Timer(100, "NS") 10 | phase.drop_objection(self) 11 | 12 | uvm_component_utils(NewTest) 13 | 14 | class NewTest2(NewTest): 15 | pass 16 | 17 | @cocotb.test() 18 | async def test_dut(dut): 19 | await run_test('NewTest') 20 | 21 | # Cannot run 2 tests with same run yet 22 | #@cocotb.test() 23 | #async def test_dut2(dut): 24 | # await run_test('NewTest2') 25 | -------------------------------------------------------------------------------- /test/examples/simple/MakefileCommon.mk: -------------------------------------------------------------------------------- 1 | # Common makefile for uvm-python examples 2 | # 3 | 4 | COCOTB_HDL_TIMEUNIT ?= 1ns 5 | COCOTB_HDL_TIMEPRECISION ?= 1ns 6 | 7 | TOPLEVEL_LANG ?= verilog 8 | 9 | MAKEDIR := $(dir $(realpath $(lastword $(MAKEFILE_LIST)))) 10 | UVM_PYTHON ?= $(MAKEDIR)/../../../src 11 | 12 | ifeq ($(OS),Msys) 13 | WPWD=$(shell sh -c 'pwd -W') 14 | PYTHONPATH := $(UVM_PYTHON):$(PYTHONPATH):. 15 | else 16 | WPWD=$(shell pwd) 17 | PYTHONPATH := $(UVM_PYTHON):$(PYTHONPATH):. 18 | endif 19 | 20 | export PYTHONPATH 21 | 22 | ifeq ($(TOPLEVEL_LANG),verilog) 23 | VERILOG_SOURCES ?= $(MAKEDIR)/common_stub.sv 24 | else ifeq ($(TOPLEVEL_LANG),vhdl) 25 | VHDL_SOURCES ?= $(MAKEDIR)/common_stub.vhd 26 | else 27 | $(error "A valid value (verilog) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)") 28 | endif 29 | 30 | ifneq ($(VLOG),) 31 | VERILOG_SOURCES := $(VLOG) 32 | endif 33 | 34 | ifneq ($(UVM_TEST),) 35 | ifeq ($(TOPLEVEL_LANG),vhdl) 36 | SIMARGS += -- +UVM_TESTNAME=$(UVM_TEST) 37 | else 38 | PLUSARGS += +UVM_TESTNAME=$(UVM_TEST) 39 | endif 40 | endif 41 | 42 | -------------------------------------------------------------------------------- /test/examples/simple/README.txt: -------------------------------------------------------------------------------- 1 | This directory contains examples that exercise specific features of 2 | the UVM library. As such, they are neither complete, exhaustive nor 3 | necessarily fully compliant to the UVM methodology. 4 | 5 | See the $UVM_HOME/examples/integrated directory for complete examples. 6 | 7 | -------------------------------------------------------------------------------- /test/examples/simple/common_stub.sv: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/1ps 3 | 4 | module common_stub( 5 | input clk, input rst 6 | ); 7 | 8 | reg[7:0] word; 9 | /* Does nothing */ 10 | 11 | always_ff@(posedge clk or negedge rst) 12 | if (!rst) word <= 8'h00; 13 | else word <= word + 8'h01; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /test/examples/simple/common_stub.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity common_stub is 5 | port ( 6 | signal clk : in std_ulogic; 7 | signal rst : in std_ulogic); 8 | end common_stub; 9 | 10 | architecture bhv of common_stub is 11 | signal word : natural; 12 | begin 13 | 14 | process (clk, rst) begin 15 | if rst = '0' then 16 | word <= 0; 17 | elsif rising_edge(clk) then 18 | word <= word + 1; 19 | end if; 20 | end process; 21 | 22 | end bhv; 23 | -------------------------------------------------------------------------------- /test/examples/simple/configuration/automated/classA.svh: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2011 Cadence Design Systems, Inc. 4 | // Copyright 2010-2011 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | `ifndef CLASSA_SVH 22 | `define CLASSA_SVH 23 | 24 | `include "classC.svh" 25 | 26 | class A extends uvm_component; 27 | bit debug = 0; 28 | C u1; 29 | C u2; 30 | 31 | `uvm_component_utils_begin(A) 32 | `uvm_field_int(debug, UVM_DEFAULT) 33 | `uvm_component_utils_end 34 | 35 | function new(string name, uvm_component parent); 36 | super.new(name, parent); 37 | endfunction 38 | function void build_phase(uvm_phase phase); 39 | super.build_phase(phase); 40 | uvm_config_int::set(this, "*", "v", 0); 41 | 42 | $display("%s: In Build: debug = %0d", get_full_name(), debug); 43 | 44 | u1 = new("u1", this); 45 | u2 = new("u2", this); 46 | endfunction 47 | endclass 48 | 49 | `endif 50 | 51 | -------------------------------------------------------------------------------- /test/examples/simple/configuration/automated/classB.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2007-2010 Mentor Graphics Corporation 3 | #// Copyright 2007-2011 Cadence Design Systems, Inc. 4 | #// Copyright 2010-2011 Synopsys, Inc. 5 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #//---------------------------------------------------------------------- 22 | 23 | from uvm import (UVMComponent, sv, UVMConfigDb, UVM_DEFAULT) 24 | from uvm.macros import * 25 | 26 | from classC import C 27 | 28 | 29 | class B(UVMComponent): 30 | 31 | def __init__(self, name, parent): 32 | super().__init__(name, parent) 33 | self.debug = 0 # type: int 34 | self.u1 = None # type: C 35 | 36 | def build_phase(self, phase): 37 | super().build_phase(phase) 38 | UVMConfigDb.set(self, "u1", "v", 0) 39 | 40 | sv.display("%s: In Build: debug = %0d", self.get_full_name(), self.debug) 41 | self.u1 = C("u1", self) 42 | 43 | uvm_component_utils_begin(B) 44 | uvm_field_int('debug', UVM_DEFAULT) 45 | uvm_component_utils_end(B) 46 | -------------------------------------------------------------------------------- /test/examples/simple/configuration/automated/classB.svh: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2011 Cadence Design Systems, Inc. 4 | // Copyright 2010-2011 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | `ifndef CLASSB_SVH 22 | `define CLASSB_SVH 23 | 24 | `include "classC.svh" 25 | 26 | class B extends uvm_component; 27 | bit debug = 0; 28 | C u1; 29 | 30 | `uvm_component_utils_begin(B) 31 | `uvm_field_int(debug, UVM_DEFAULT) 32 | `uvm_component_utils_end 33 | 34 | function new(string name, uvm_component parent); 35 | super.new(name, parent); 36 | endfunction 37 | function void build_phase(uvm_phase phase); 38 | super.build_phase(phase); 39 | uvm_config_int::set(this, "u1", "v", 0); 40 | 41 | $display("%s: In Build: debug = %0d", get_full_name(), debug); 42 | 43 | u1 = new("u1", this); 44 | endfunction 45 | endclass 46 | 47 | `endif 48 | 49 | -------------------------------------------------------------------------------- /test/examples/simple/configuration/automated/classC.svh: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010-2011 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | `ifndef CLASSC_SVH 22 | `define CLASSC_SVH 23 | 24 | class C extends uvm_component; 25 | int v=0; 26 | int s=0; 27 | string myaa[string]; 28 | 29 | function new(string name, uvm_component parent); 30 | super.new(name, parent); 31 | endfunction 32 | 33 | function void build_phase(uvm_phase phase); 34 | super.build_phase(phase); 35 | $display("%s: In Build: v = %0d s = %0d", get_full_name(), v, s); 36 | endfunction 37 | 38 | `uvm_component_utils_begin(C) 39 | `uvm_field_int(v, UVM_DEFAULT) 40 | `uvm_field_int(s, UVM_DEFAULT) 41 | `uvm_field_aa_string_string(myaa, UVM_DEFAULT) 42 | `uvm_component_utils_end 43 | endclass 44 | 45 | `endif 46 | -------------------------------------------------------------------------------- /test/examples/simple/configuration/automated/module_top.sv: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------------- 2 | // File: module_top.sv 3 | // Created on 2020-01-08 4 | // Tuomas Poikela, tuomas.sakari.poikela@gmail.com 5 | // 6 | // Description: 7 | //--------------------------------------------------------------------------- 8 | 9 | `timescale 1ns/1ps 10 | 11 | module module_top(input clk, input rst); 12 | 13 | endmodule: module_top 14 | 15 | -------------------------------------------------------------------------------- /test/examples/simple/configuration/manual/module_top.sv: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------------- 2 | // File: module_top.sv 3 | // Created on 2020-01-08 4 | // Tuomas Poikela, tuomas.sakari.poikela@gmail.com 5 | // 6 | // Description: 7 | //--------------------------------------------------------------------------- 8 | 9 | `timescale 1ns/1ps 10 | 11 | module module_top(input clk, input rst); 12 | 13 | endmodule: module_top 14 | 15 | -------------------------------------------------------------------------------- /test/examples/simple/hello_world/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for testing python-uvm 2 | 3 | # Usage: 4 | # To execute tests in given file using given verilog source, you can do: 5 | # >$ make MODULE=py_mod_name VLOG=hdl/my_vlog.v SIM_ARGS='-aaa +bbb' 6 | 7 | include ../MakefileCommon.mk 8 | 9 | # SIM_ARGS = "" 10 | TOPLEVEL := common_stub 11 | MODULE ?= hello_world 12 | 13 | include $(shell cocotb-config --makefiles)/Makefile.sim 14 | -------------------------------------------------------------------------------- /test/examples/simple/hello_world/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tpoikela/uvm-python/2301431a22ddec14abebb8df38f35c6dcdefd241/test/examples/simple/hello_world/__init__.py -------------------------------------------------------------------------------- /test/examples/simple/hello_world/packet.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2007-2010 Mentor Graphics Corporation 3 | #// Copyright 2007-2010 Cadence Design Systems, Inc. 4 | #// Copyright 2010-2011 Synopsys, Inc. 5 | #// Copyright 2019 Tuomas Poikela (tpoikela) 6 | #// All Rights Reserved Worldwide 7 | #// 8 | #// Licensed under the Apache License, Version 2.0 (the 9 | #// "License"); you may not use this file except in 10 | #// compliance with the License. You may obtain a copy of 11 | #// the License at 12 | #// 13 | #// http://www.apache.org/licenses/LICENSE-2.0 14 | #// 15 | #// Unless required by applicable law or agreed to in 16 | #// writing, software distributed under the License is 17 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | #// CONDITIONS OF ANY KIND, either express or implied. See 19 | #// the License for the specific language governing 20 | #// permissions and limitations under the License. 21 | #//---------------------------------------------------------------------- 22 | 23 | from uvm.base import UVMTransaction 24 | from uvm.macros import uvm_object_utils 25 | 26 | class packet(UVMTransaction): 27 | 28 | #`ifndef NO_RAND 29 | # rand 30 | #`endif 31 | # int addr; 32 | 33 | # constraint c { addr >= 0 && addr < 'h100; } 34 | 35 | def __init__(self, name): 36 | UVMTransaction.__init__(self, name) 37 | self.addr = 0 38 | 39 | uvm_object_utils(packet) 40 | #uvm_field_int(addr, UVM_ALL_ON) 41 | -------------------------------------------------------------------------------- /test/examples/simple/hello_world/packet.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010-2011 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | 22 | class packet extends uvm_transaction; 23 | 24 | `ifndef NO_RAND 25 | rand 26 | `endif 27 | int addr; 28 | 29 | `uvm_object_utils_begin(packet) 30 | `uvm_field_int(addr, UVM_ALL_ON) 31 | `uvm_object_utils_end 32 | 33 | constraint c { addr >= 0 && addr < 'h100; } 34 | 35 | 36 | function new(string name="packet"); 37 | super.new(name); 38 | endfunction 39 | 40 | endclass 41 | 42 | -------------------------------------------------------------------------------- /test/examples/simple/hello_world/top.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2007-2010 Mentor Graphics Corporation 3 | // Copyright 2007-2010 Cadence Design Systems, Inc. 4 | // Copyright 2010-2011 Synopsys, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | 22 | class top extends uvm_component; 23 | 24 | producer #(packet) p1; 25 | producer #(packet) p2; 26 | uvm_tlm_fifo #(packet) f; 27 | consumer #(packet) c; 28 | 29 | `uvm_component_utils(top) 30 | 31 | function new (string name, uvm_component parent=null); 32 | super.new(name,parent); 33 | 34 | p1 = new("producer1",this); 35 | p2 = new("producer2",this); 36 | f = new("fifo",this); 37 | c = new("consumer",this); 38 | 39 | p1.out.connect( c.in ); 40 | p2.out.connect( f.blocking_put_export ); 41 | c.out.connect( f.get_export ); 42 | endfunction 43 | 44 | task run_phase(uvm_phase phase); 45 | phase.raise_objection(this); 46 | uvm_top.print_topology(); 47 | #1us; 48 | phase.drop_objection(this); 49 | endtask 50 | endclass 51 | 52 | 53 | -------------------------------------------------------------------------------- /test/examples/simple/registers/common/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | from .reg_agent import * 3 | -------------------------------------------------------------------------------- /test/examples/simple/registers/common/wishbone/wishbone.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // All Rights Reserved Worldwide 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the 7 | // "License"); you may not use this file except in 8 | // compliance with the License. You may obtain a copy of 9 | // the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in 14 | // writing, software distributed under the License is 15 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | // CONDITIONS OF ANY KIND, either express or implied. See 17 | // the License for the specific language governing 18 | // permissions and limitations under the License. 19 | // ------------------------------------------------------------- 20 | // 21 | 22 | 23 | `ifndef WISHBONE__SV 24 | `define WISHBONE__SV 25 | 26 | package wb_pkg; 27 | 28 | import uvm_pkg::*; 29 | 30 | `include "config.sv" 31 | `include "cycle.sv" 32 | `include "driver.sv" 33 | `include "agent.sv" 34 | 35 | endpackage 36 | 37 | `endif 38 | -------------------------------------------------------------------------------- /test/examples/simple/registers/integration/10direct/test_top.py: -------------------------------------------------------------------------------- 1 | 2 | 3 | from tb_env import tb_env 4 | from test import initial_begin 5 | -------------------------------------------------------------------------------- /test/examples/simple/registers/integration/common/dut_with_clkgen.sv: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------------- 2 | // File: dut_with_clkgen.sv 3 | // Created on 2024-03-17 4 | // 5 | // Tuomas Poikela, tuomas.sakari.poikela@gmail.com 6 | // 7 | // Description: 8 | //--------------------------------------------------------------------------- 9 | // 10 | module apb_slave_with_clkgen#( 11 | parameter int MEM_SIZE = 128, 12 | parameter int NSOCKETS = 64, 13 | parameter int ID_REGISTER = {2'b00, 4'h0, 10'h176, 8'h5A, 8'h03}, 14 | parameter int ADDR_WIDTH = 16 15 | ) 16 | ( 17 | output logic apb_pclk, 18 | input wire rst, 19 | input wire [31:0] apb_paddr, 20 | input wire apb_psel, 21 | input wire apb_penable, 22 | input wire apb_pwrite, 23 | output wire [31:0] apb_prdata, 24 | input wire [31:0] apb_pwdata 25 | ); 26 | 27 | // Instantiate the apb_slave 28 | apb_slave#( 29 | .MEM_SIZE(MEM_SIZE), 30 | .NSOCKETS(NSOCKETS), 31 | .ID_REGISTER(ID_REGISTER), 32 | .ADDR_WIDTH(ADDR_WIDTH) 33 | ) apb_slave_inst ( 34 | .apb_pclk(apb_pclk), 35 | .rst(rst), 36 | .apb_paddr(apb_paddr), 37 | .apb_psel(apb_psel), 38 | .apb_penable(apb_penable), 39 | .apb_pwrite(apb_pwrite), 40 | .apb_prdata(apb_prdata), 41 | .apb_pwdata(apb_pwdata) 42 | ); 43 | 44 | initial begin 45 | apb_pclk = 1'b0; 46 | forever #5ns apb_pclk = ~apb_pclk; 47 | end 48 | 49 | endmodule: apb_slave_with_clkgen 50 | -------------------------------------------------------------------------------- /test/examples/simple/registers/integration/common/tb_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // Copyright 2010 Cadence Design Systems, Inc. 6 | // All Rights Reserved Worldwide 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in 10 | // compliance with the License. You may obtain a copy of 11 | // the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in 16 | // writing, software distributed under the License is 17 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | // CONDITIONS OF ANY KIND, either express or implied. See 19 | // the License for the specific language governing 20 | // permissions and limitations under the License. 21 | // ------------------------------------------------------------- 22 | // 23 | 24 | `include "apb.sv" 25 | `include "dut.sv" 26 | 27 | module tb_top; 28 | bit clk = 0; 29 | bit rst = 0; 30 | 31 | apb_if apb0(clk); 32 | slave dut(apb0, rst); 33 | 34 | always #10 clk = ~clk; 35 | endmodule: tb_top 36 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/broadcast/tb_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2011 Synopsys, Inc. 4 | // All Rights Reserved Worldwide 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the 7 | // "License"); you may not use this file except in 8 | // compliance with the License. You may obtain a copy of 9 | // the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in 14 | // writing, software distributed under the License is 15 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | // CONDITIONS OF ANY KIND, either express or implied. See 17 | // the License for the specific language governing 18 | // permissions and limitations under the License. 19 | // ------------------------------------------------------------- 20 | // 21 | 22 | `include "apb.sv" 23 | `include "dut.sv" 24 | 25 | module tb_top; 26 | bit clk = 0; 27 | bit rst = 0; 28 | 29 | apb_if apb(clk); 30 | soc dut(apb, rst); 31 | 32 | always #10 clk = ~clk; 33 | endmodule: tb_top 34 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/shared_reg/blk_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package blk_pkg; 24 | 25 | import uvm_pkg::*; 26 | import reg_pkg::*; 27 | 28 | `include "blk_env.sv" 29 | `include "blk_seqlib.sv" 30 | 31 | endpackage 32 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/shared_reg/blk_run.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `include "uvm_pkg.sv" 24 | `include "reg_pkg.sv" 25 | `include "blk_pkg.sv" 26 | 27 | program tb; 28 | 29 | import uvm_pkg::*; 30 | import blk_pkg::*; 31 | import reg_pkg::*; 32 | 33 | `include "blk_testlib.sv" 34 | 35 | initial begin automatic uvm_coreservice_t cs_ = uvm_coreservice_t::get(); 36 | 37 | uvm_report_server svr; 38 | svr = cs_.get_report_server(); 39 | svr.set_max_quit_count(10); 40 | run_test(); 41 | end 42 | 43 | endprogram 44 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/shared_reg/blk_testlib.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2010-2011 Synopsys, Inc. 3 | // Copyright 2010 Mentor Graphics Corporation 4 | // Copyright 2010-2011 Cadence Design Systems, Inc. 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | //---------------------------------------------------------------------- 21 | 22 | 23 | class blk_test extends uvm_test; 24 | 25 | `uvm_component_utils(blk_test) 26 | 27 | blk_env env; 28 | 29 | function new(string name = "blk_test", uvm_component parent = null); 30 | super.new(name, parent); 31 | endfunction 32 | 33 | function void build_phase(uvm_phase phase); 34 | env = blk_env::type_id::create("blk_env",this); 35 | endfunction 36 | 37 | task run_phase(uvm_phase phase); 38 | blk_AXW_test_seq seq = blk_AXW_test_seq::type_id::create("blk_AXW_test_seq",this); 39 | seq.model = env.model; 40 | 41 | phase.raise_objection(this); 42 | 43 | seq.start(null); 44 | seq.wait_for_sequence_state(UVM_FINISHED); 45 | 46 | phase.drop_objection(this); 47 | endtask 48 | 49 | endclass 50 | 51 | 52 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/shared_reg/reg_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package reg_pkg; 24 | 25 | `include "reg_B.sv" 26 | 27 | endpackage 28 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/user-defined/dut.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `timescale 1ns/1ns 24 | 25 | module dut( 26 | input clk, 27 | input reset, 28 | input[15:0] data_in, 29 | input[15:0] addr_in, 30 | input we, 31 | input read, 32 | output[15:0] data_out 33 | ); 34 | 35 | reg [15:0][15:0] acp; 36 | assign data_out = read ? acp[addr_in] : 16'hFFFF; 37 | 38 | always_ff@(posedge clk or negedge reset) 39 | if (!reset) 40 | acp <= 0; 41 | else begin 42 | if (we) acp[addr_in] <= data_in; 43 | end 44 | 45 | `ifndef VERILATOR 46 | `ifdef COCOTB_SIM 47 | initial begin 48 | $dumpfile ("gui.vcd"); 49 | $dumpvars (0, dut); 50 | #1; 51 | end 52 | `endif 53 | `endif 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/virtual_regs/dut.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `timescale 1ns/1ns 24 | 25 | module dut( 26 | input clk, 27 | input reset, 28 | input[15:0] data_in, 29 | input[15:0] addr_in, 30 | input we, 31 | input read, 32 | output[15:0] data_out 33 | ); 34 | 35 | reg [15:0][15:0] acp; 36 | assign data_out = read ? acp[addr_in] : 16'hFFFF; 37 | 38 | always_ff@(posedge clk or negedge reset) 39 | if (!reset) 40 | acp <= 0; 41 | else begin 42 | if (we) acp[addr_in] <= data_in; 43 | end 44 | 45 | `ifndef VERILATOR 46 | `ifdef COCOTB_SIM 47 | initial begin 48 | $dumpfile ("gui.vcd"); 49 | $dumpvars (0, dut); 50 | #1; 51 | end 52 | `endif 53 | `endif 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /test/examples/simple/registers/models/virtual_regs/virtual_regs.rdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tpoikela/uvm-python/2301431a22ddec14abebb8df38f35c6dcdefd241/test/examples/simple/registers/models/virtual_regs/virtual_regs.rdl -------------------------------------------------------------------------------- /test/examples/simple/registers/primer/primer.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tpoikela/uvm-python/2301431a22ddec14abebb8df38f35c6dcdefd241/test/examples/simple/registers/primer/primer.pdf -------------------------------------------------------------------------------- /test/examples/simple/registers/primer/tb_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // Copyright 2010 Cadence Design Systems, Inc. 6 | // All Rights Reserved Worldwide 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in 10 | // compliance with the License. You may obtain a copy of 11 | // the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in 16 | // writing, software distributed under the License is 17 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | // CONDITIONS OF ANY KIND, either express or implied. See 19 | // the License for the specific language governing 20 | // permissions and limitations under the License. 21 | // ------------------------------------------------------------- 22 | // 23 | 24 | `include "uvm_macros.svh" 25 | `include "apb.sv" 26 | `include "dut.sv" 27 | 28 | module tb_top; 29 | bit clk = 0; 30 | bit rst = 0; 31 | 32 | apb_if apb0(clk); 33 | slave dut(apb0, rst); 34 | 35 | always #10 clk = ~clk; 36 | endmodule: tb_top 37 | -------------------------------------------------------------------------------- /test/examples/simple/registers/primer/test.py: -------------------------------------------------------------------------------- 1 | #// 2 | #// ------------------------------------------------------------- 3 | #// Copyright 2004-2011 Synopsys, Inc. 4 | #// Copyright 2010 Mentor Graphics Corporation 5 | #// Copyright 2010 Cadence Design Systems, Inc. 6 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 7 | #// All Rights Reserved Worldwide 8 | #// 9 | #// Licensed under the Apache License, Version 2.0 (the 10 | #// "License"); you may not use this file except in 11 | #// compliance with the License. You may obtain a copy of 12 | #// the License at 13 | #// 14 | #// http://www.apache.org/licenses/LICENSE-2.0 15 | #// 16 | #// Unless required by applicable law or agreed to in 17 | #// writing, software distributed under the License is 18 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 19 | #// CONDITIONS OF ANY KIND, either express or implied. See 20 | #// the License for the specific language governing 21 | #// permissions and limitations under the License. 22 | #// ------------------------------------------------------------- 23 | #// 24 | 25 | import cocotb 26 | from cocotb.clock import Clock 27 | 28 | from uvm.macros import * 29 | from uvm import (UVMConfigDb, run_test) 30 | 31 | from tb_env import tb_env 32 | from apb.apb_if import apb_if 33 | from testlib import * 34 | 35 | 36 | @cocotb.test() 37 | async def initial(dut): 38 | env = tb_env("env", None) 39 | vif = apb_if(dut) 40 | UVMConfigDb.set(env, "apb", "vif", vif) 41 | UVMConfigDb.set(None, "", "dut", dut) 42 | #UVMConfigDb.set(env, "apb", "vif", tb_top.apb0) 43 | cocotb.start_soon(Clock(vif.clk, 10, "NS").start()) 44 | await run_test() 45 | -------------------------------------------------------------------------------- /test/examples/simple/registers/primer/test.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // Copyright 2010 Cadence Design Systems, Inc. 6 | // All Rights Reserved Worldwide 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in 10 | // compliance with the License. You may obtain a copy of 11 | // the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in 16 | // writing, software distributed under the License is 17 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | // CONDITIONS OF ANY KIND, either express or implied. See 19 | // the License for the specific language governing 20 | // permissions and limitations under the License. 21 | // ------------------------------------------------------------- 22 | // 23 | 24 | 25 | program test; 26 | 27 | import uvm_pkg::*; 28 | import apb_pkg::*; 29 | 30 | `include "reg_model.sv" 31 | `include "tb_env.sv" 32 | `include "testlib.sv" 33 | 34 | 35 | class dut_reset_seq extends uvm_sequence; 36 | 37 | function new(string name = "dut_reset_seq"); 38 | super.new(name); 39 | endfunction 40 | 41 | `uvm_object_utils(dut_reset_seq) 42 | 43 | virtual task body(); 44 | tb_top.rst = 1; 45 | repeat (5) @(negedge tb_top.clk); 46 | tb_top.rst = 0; 47 | endtask 48 | endclass 49 | 50 | 51 | initial 52 | begin 53 | static tb_env env = new("env"); 54 | 55 | uvm_config_db#(apb_vif)::set(env, "apb", "vif", $root.tb_top.apb0); 56 | 57 | run_test(); 58 | 59 | end 60 | 61 | endprogram 62 | 63 | -------------------------------------------------------------------------------- /test/examples/simple/registers/primer/testlib.py: -------------------------------------------------------------------------------- 1 | #// 2 | #// ------------------------------------------------------------- 3 | #// Copyright 2004-2011 Synopsys, Inc. 4 | #// Copyright 2010 Mentor Graphics Corporation 5 | #// Copyright 2010 Cadence Design Systems, Inc. 6 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 7 | #// All Rights Reserved Worldwide 8 | #// 9 | #// Licensed under the Apache License, Version 2.0 (the 10 | #// "License"); you may not use this file except in 11 | #// compliance with the License. You may obtain a copy of 12 | #// the License at 13 | #// 14 | #// http://www.apache.org/licenses/LICENSE-2.0 15 | #// 16 | #// Unless required by applicable law or agreed to in 17 | #// writing, software distributed under the License is 18 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 19 | #// CONDITIONS OF ANY KIND, either express or implied. See 20 | #// the License for the specific language governing 21 | #// permissions and limitations under the License. 22 | #// ------------------------------------------------------------- 23 | 24 | 25 | from cmdline_test import * 26 | from user_test import * 27 | from mem_test import * 28 | -------------------------------------------------------------------------------- /test/examples/simple/registers/primer/testlib.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // Copyright 2010 Cadence Design Systems, Inc. 6 | // All Rights Reserved Worldwide 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in 10 | // compliance with the License. You may obtain a copy of 11 | // the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in 16 | // writing, software distributed under the License is 17 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | // CONDITIONS OF ANY KIND, either express or implied. See 19 | // the License for the specific language governing 20 | // permissions and limitations under the License. 21 | // ------------------------------------------------------------- 22 | // 23 | `include "cmdline_test.sv" 24 | `include "user_test.sv" 25 | -------------------------------------------------------------------------------- /test/examples/simple/registers/sequence_api/README.txt: -------------------------------------------------------------------------------- 1 | // This example uses the reg/mem write/read convenience API in the 2 | // user register sequence (blk_seqlib.sv). The convenience methods 3 | // provide the ~parent~ argument for you when calling the corresponding 4 | // method in the register or memory. Compare this example's blk_seqlib.sv 5 | // file with that in the ~vertical_reuse~ example. 6 | 7 | 8 | -------------------------------------------------------------------------------- /test/examples/simple/registers/sequence_api/blk_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package blk_pkg; 24 | 25 | import uvm_pkg::*; 26 | import blk_reg_pkg::*; 27 | 28 | `include "blk_env.sv" 29 | `include "blk_seqlib.sv" 30 | 31 | endpackage 32 | -------------------------------------------------------------------------------- /test/examples/simple/registers/sequence_api/blk_reg_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package blk_reg_pkg; 24 | 25 | `include "reg_B.sv" 26 | 27 | endpackage 28 | -------------------------------------------------------------------------------- /test/examples/simple/registers/sequence_api/blk_run.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `include "uvm_pkg.sv" 24 | `include "apb.sv" 25 | `include "blk_reg_pkg.sv" 26 | `include "blk_pkg.sv" 27 | `include "blk_top.sv" 28 | 29 | program tb; 30 | 31 | import uvm_pkg::*; 32 | import blk_reg_pkg::*; 33 | import blk_pkg::*; 34 | 35 | `include "blk_testlib.sv" 36 | 37 | 38 | class dut_reset_seq extends uvm_sequence; 39 | 40 | function new(string name = "dut_reset_seq"); 41 | super.new(name); 42 | endfunction 43 | 44 | `uvm_object_utils(dut_reset_seq) 45 | 46 | virtual task body(); 47 | blk_top.rst = 1; 48 | repeat (5) @(negedge blk_top.clk); 49 | blk_top.rst = 0; 50 | endtask 51 | endclass 52 | 53 | 54 | initial 55 | begin 56 | static blk_env env = new("env"); 57 | 58 | uvm_config_db#(apb_vif)::set(env, "apb", "vif", $root.blk_top.apb0); 59 | 60 | run_test(); 61 | end 62 | 63 | endprogram 64 | -------------------------------------------------------------------------------- /test/examples/simple/registers/sequence_api/blk_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `include "blk_dut.sv" 24 | 25 | module blk_top; 26 | bit clk = 0; 27 | bit rst = 0; 28 | 29 | apb_if apb0(clk); 30 | blk_dut dut(apb0, rst); 31 | 32 | always #10 clk = ~clk; 33 | endmodule: blk_top 34 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/blk_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package blk_pkg; 24 | 25 | import uvm_pkg::*; 26 | import blk_reg_pkg::*; 27 | 28 | `include "blk_env.sv" 29 | `include "blk_seqlib.sv" 30 | 31 | endpackage 32 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/blk_reg_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package blk_reg_pkg; 24 | 25 | `include "reg_B.sv" 26 | 27 | endpackage 28 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/blk_run.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `include "uvm_pkg.sv" 24 | `include "apb.sv" 25 | `include "blk_reg_pkg.sv" 26 | `include "blk_pkg.sv" 27 | `include "blk_top.sv" 28 | 29 | program tb; 30 | 31 | import uvm_pkg::*; 32 | import blk_reg_pkg::*; 33 | import blk_pkg::*; 34 | 35 | `include "blk_testlib.sv" 36 | 37 | 38 | class dut_reset_seq extends uvm_sequence; 39 | 40 | function new(string name = "dut_reset_seq"); 41 | super.new(name); 42 | endfunction 43 | 44 | `uvm_object_utils(dut_reset_seq) 45 | 46 | virtual task body(); 47 | blk_top.rst = 1; 48 | repeat (5) @(negedge blk_top.clk); 49 | blk_top.rst = 0; 50 | endtask 51 | endclass 52 | 53 | 54 | initial 55 | begin 56 | static blk_env env = new("env"); 57 | 58 | uvm_config_db#(apb_vif)::set(env, "apb", "vif", $root.blk_top.apb0); 59 | 60 | run_test(); 61 | end 62 | 63 | endprogram 64 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/blk_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | `include "blk_dut.sv" 24 | 25 | module blk_top; 26 | bit clk = 0; 27 | bit rst = 0; 28 | 29 | apb_if apb0(clk); 30 | blk_dut dut(apb0, rst); 31 | 32 | always #10 clk = ~clk; 33 | endmodule: blk_top 34 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/reg_S.sv: -------------------------------------------------------------------------------- 1 | // 2 | //------------------------------------------------------------------------------ 3 | // Copyright 2011 Mentor Graphics Corporation 4 | // Copyright 2011 Cadence Design Systems, Inc. 5 | // Copyright 2011 Synopsys, Inc. 6 | // All Rights Reserved Worldwide 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in 10 | // compliance with the License. You may obtain a copy of 11 | // the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in 16 | // writing, software distributed under the License is 17 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | // CONDITIONS OF ANY KIND, either express or implied. See 19 | // the License for the specific language governing 20 | // permissions and limitations under the License. 21 | //------------------------------------------------------------------------------ 22 | 23 | `ifndef REG_S 24 | `define REG_S 25 | 26 | 27 | class reg_sys_S extends uvm_reg_block; 28 | 29 | rand reg_block_B B[2]; 30 | 31 | `uvm_object_utils(reg_sys_S) 32 | 33 | function new(string name = "S"); 34 | super.new(name,UVM_NO_COVERAGE); 35 | endfunction: new 36 | 37 | function void build(); 38 | 39 | default_map = create_map("default_map", 'h0, 1, UVM_LITTLE_ENDIAN); 40 | 41 | foreach (B[i]) begin 42 | B[i] = reg_block_B::type_id::create($sformatf("B[%0d]", i)); 43 | B[i].configure(this); 44 | B[i].build(); 45 | default_map.add_submap(this.B[i].default_map, 'h100 + i*'h100); 46 | end 47 | endfunction : build 48 | 49 | endclass : reg_sys_S 50 | 51 | 52 | `endif 53 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/sys_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package sys_pkg; 24 | 25 | import uvm_pkg::*; 26 | import sys_reg_pkg::*; 27 | import blk_pkg::*; 28 | 29 | `include "sys_env.sv" 30 | `include "sys_seqlib.sv" 31 | 32 | endpackage 33 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/sys_reg_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | package sys_reg_pkg; 24 | 25 | import uvm_pkg::*; 26 | import blk_reg_pkg::*; 27 | 28 | `include "reg_S.sv" 29 | 30 | endpackage 31 | -------------------------------------------------------------------------------- /test/examples/simple/registers/vertical_reuse/sys_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // All Rights Reserved Worldwide 6 | // 7 | // Licensed under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in 9 | // compliance with the License. You may obtain a copy of 10 | // the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in 15 | // writing, software distributed under the License is 16 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | // CONDITIONS OF ANY KIND, either express or implied. See 18 | // the License for the specific language governing 19 | // permissions and limitations under the License. 20 | // ------------------------------------------------------------- 21 | // 22 | 23 | 24 | `include "sys_dut.sv" 25 | 26 | module sys_top; 27 | bit clk = 0; 28 | bit rst = 0; 29 | 30 | apb_if apb0(clk); 31 | sys_dut #('h100) dut(apb0, rst); 32 | 33 | always #10 clk = ~clk; 34 | endmodule: sys_top 35 | -------------------------------------------------------------------------------- /test/examples/simple/tlm1/hierarchy/module_top.sv: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------------- 2 | // File: module_top.sv 3 | // Created on 2020-01-08 4 | // Tuomas Poikela, tuomas.sakari.poikela@gmail.com 5 | // 6 | // Description: 7 | //--------------------------------------------------------------------------- 8 | 9 | `timescale 1ns/1ps 10 | 11 | module module_top(input clk, input rst); 12 | 13 | endmodule: module_top 14 | 15 | -------------------------------------------------------------------------------- /test/examples/simple/tlm1/master_slave/test_master_slave.py: -------------------------------------------------------------------------------- 1 | 2 | import cocotb 3 | from cocotb.triggers import Timer 4 | from uvm import (UVMTest, run_test, UVMDebug) 5 | from uvm.macros import (uvm_component_utils, uvm_fatal) 6 | 7 | from master_slave_pkg import env_top 8 | 9 | test_dur = 1200 # NS 10 | 11 | if False: 12 | UVMDebug.full_debug() 13 | 14 | @uvm_component_utils 15 | class master_slave_test(UVMTest): 16 | 17 | def __init__(self, name, parent): 18 | super().__init__(name, parent) 19 | 20 | def build_phase(self, phase): 21 | self.env = env_top("env_master_slave", self) 22 | 23 | 24 | async def run_phase(self, phase): 25 | phase.raise_objection(self) 26 | await Timer(test_dur, "NS") 27 | phase.drop_objection(self) 28 | 29 | 30 | def check_phase(self, phase): 31 | if not self.env.all_ok(): 32 | uvm_fatal("ENV_NOT_OK", "There were errors in the env") 33 | 34 | 35 | @cocotb.test() 36 | async def master_slave_top(dut): 37 | await run_test() 38 | -------------------------------------------------------------------------------- /test/examples/simple/tlm1/producer_consumer/module_top.sv: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------------- 2 | // File: module_top.sv 3 | // Created on 2020-01-08 4 | // Tuomas Poikela, tuomas.sakari.poikela@gmail.com 5 | // 6 | // Description: 7 | //--------------------------------------------------------------------------- 8 | 9 | `timescale 1ns/1ps 10 | 11 | module module_top(input clk, input rst); 12 | 13 | endmodule: module_top 14 | 15 | -------------------------------------------------------------------------------- /test/examples/simple/tlm1/producer_consumer/module_top.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity module_top is 5 | port ( 6 | signal clk : in std_ulogic; 7 | signal rst : in std_ulogic); 8 | end module_top; 9 | 10 | architecture bhv of module_top is 11 | signal word : natural; 12 | begin 13 | 14 | process (clk, rst) begin 15 | if rst = '0' then 16 | word <= 0; 17 | elsif rising_edge(clk) then 18 | word <= word + 1; 19 | end if; 20 | end process; 21 | 22 | end bhv; 23 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/blocking_simple/tb_run.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2010 Mentor Graphics Corporation 3 | #// Copyright 2010-2011 Synopsys, Inc. 4 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 5 | #// All Rights Reserved Worldwide 6 | #// 7 | #// Licensed under the Apache License, Version 2.0 (the 8 | #// "License"); you may not use this file except in 9 | #// compliance with the License. You may obtain a copy of 10 | #// the License at 11 | #// 12 | #// http://www.apache.org/licenses/LICENSE-2.0 13 | #// 14 | #// Unless required by applicable law or agreed to in 15 | #// writing, software distributed under the License is 16 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 17 | #// CONDITIONS OF ANY KIND, either express or implied. See 18 | #// the License for the specific language governing 19 | #// permissions and limitations under the License. 20 | #//---------------------------------------------------------------------- 21 | 22 | import cocotb 23 | from uvm import run_test 24 | from tb_env import tb_env 25 | 26 | 27 | @cocotb.test() 28 | async def initial_begin(dut): 29 | env = tb_env("env_for_tlm2_test") 30 | await run_test() 31 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/nonblocking_simple/tb_env.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2010-2011 Synopsys, Inc 3 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 4 | #// All Rights Reserved Worldwide 5 | #// 6 | #// Licensed under the Apache License, Version 2.0 (the 7 | #// "License"); you may not use this file except in 8 | #// compliance with the License. You may obtain a copy of 9 | #// the License at 10 | #// 11 | #// http://www.apache.org/licenses/LICENSE-2.0 12 | #// 13 | #// Unless required by applicable law or agreed to in 14 | #// writing, software distributed under the License is 15 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | #// CONDITIONS OF ANY KIND, either express or implied. See 17 | #// the License for the specific language governing 18 | #// permissions and limitations under the License. 19 | #//---------------------------------------------------------------------- 20 | 21 | from uvm.base.uvm_component import UVMComponent 22 | from uvm.macros import * 23 | 24 | from host import host 25 | from device import device 26 | 27 | 28 | class tb_env(UVMComponent): 29 | 30 | 31 | def __init__(self, name="tb_env", parent=None): 32 | super().__init__(name, parent) 33 | self.hst = None 34 | self.dev = None 35 | 36 | 37 | def build_phase(self, phase): 38 | self.hst = host.type_id.create("hst", self) 39 | self.dev = device.type_id.create("dev", self) 40 | 41 | 42 | def connect_phase(self, phase): 43 | self.hst.sock.connect(self.dev.sock) 44 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/nonblocking_simple/tb_env.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2010-2011 Synopsys, Inc 3 | // All Rights Reserved Worldwide 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the 6 | // "License"); you may not use this file except in 7 | // compliance with the License. You may obtain a copy of 8 | // the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in 13 | // writing, software distributed under the License is 14 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 15 | // CONDITIONS OF ANY KIND, either express or implied. See 16 | // the License for the specific language governing 17 | // permissions and limitations under the License. 18 | //---------------------------------------------------------------------- 19 | 20 | class tb_env extends uvm_component; 21 | 22 | `uvm_component_utils(tb_env) 23 | 24 | host hst; 25 | device dev; 26 | 27 | function new(string name = "tb_env", uvm_component parent = null); 28 | super.new(name, parent); 29 | endfunction 30 | 31 | function void build_phase(uvm_phase phase); 32 | hst = host::type_id::create("hst", this); 33 | dev = device::type_id::create("dev", this); 34 | endfunction 35 | 36 | function void connect_phase(uvm_phase phase); 37 | hst.sock.connect(dev.sock); 38 | endfunction 39 | 40 | endclass 41 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/nonblocking_simple/tb_run.py: -------------------------------------------------------------------------------- 1 | #//---------------------------------------------------------------------- 2 | #// Copyright 2010-2011 Synopsys, Inc. 3 | #// Copyright 2019-2020 Tuomas Poikela (tpoikela) 4 | #// All Rights Reserved Worldwide 5 | #// 6 | #// Licensed under the Apache License, Version 2.0 (the 7 | #// "License"); you may not use this file except in 8 | #// compliance with the License. You may obtain a copy of 9 | #// the License at 10 | #// 11 | #// http://www.apache.org/licenses/LICENSE-2.0 12 | #// 13 | #// Unless required by applicable law or agreed to in 14 | #// writing, software distributed under the License is 15 | #// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | #// CONDITIONS OF ANY KIND, either express or implied. See 17 | #// the License for the specific language governing 18 | #// permissions and limitations under the License. 19 | #//---------------------------------------------------------------------- 20 | # 21 | #from uvm_pkg import * 22 | #`include "uvm_macros.svh" 23 | # 24 | #`include "usb_xfer.sv" 25 | #`include "host.sv" 26 | #`include "device.sv" 27 | #`include "tb_env.sv" 28 | 29 | import cocotb 30 | from tb_env import tb_env 31 | from uvm import run_test 32 | 33 | @cocotb.test() 34 | async def tlm2_nb_simple_test(dut): 35 | env = tb_env("env") 36 | await run_test() 37 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/nonblocking_simple/tb_run.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2010-2011 Synopsys, Inc. 3 | // All Rights Reserved Worldwide 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the 6 | // "License"); you may not use this file except in 7 | // compliance with the License. You may obtain a copy of 8 | // the License at 9 | // 10 | // http://www.apache.org/licenses/LICENSE-2.0 11 | // 12 | // Unless required by applicable law or agreed to in 13 | // writing, software distributed under the License is 14 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 15 | // CONDITIONS OF ANY KIND, either express or implied. See 16 | // the License for the specific language governing 17 | // permissions and limitations under the License. 18 | //---------------------------------------------------------------------- 19 | 20 | import uvm_pkg::*; 21 | `include "uvm_macros.svh" 22 | 23 | `include "usb_xfer.sv" 24 | `include "host.sv" 25 | `include "device.sv" 26 | `include "tb_env.sv" 27 | 28 | program tb_run; 29 | 30 | initial 31 | begin 32 | static tb_env env = new("env"); 33 | 34 | run_test(); 35 | end 36 | 37 | endprogram 38 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/temporal_decoupling/apb_rw.sv: -------------------------------------------------------------------------------- 1 | // 2 | // ------------------------------------------------------------- 3 | // Copyright 2004-2011 Synopsys, Inc. 4 | // Copyright 2010 Mentor Graphics Corporation 5 | // Copyright 2010 Cadence Design Systems, Inc. 6 | // All Rights Reserved Worldwide 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in 10 | // compliance with the License. You may obtain a copy of 11 | // the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in 16 | // writing, software distributed under the License is 17 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 18 | // CONDITIONS OF ANY KIND, either express or implied. See 19 | // the License for the specific language governing 20 | // permissions and limitations under the License. 21 | // ------------------------------------------------------------- 22 | // 23 | 24 | package apb_pkg; 25 | 26 | import uvm_pkg::*; 27 | `include "uvm_macros.svh" 28 | 29 | class apb_rw extends uvm_sequence_item; 30 | 31 | typedef enum {READ, WRITE} kind_e; 32 | rand bit [31:0] addr; 33 | rand logic [31:0] data; 34 | rand kind_e kind; 35 | 36 | `uvm_object_utils_begin(apb_rw) 37 | `uvm_field_int(addr, UVM_ALL_ON | UVM_NOPACK); 38 | `uvm_field_int(data, UVM_ALL_ON | UVM_NOPACK); 39 | `uvm_field_enum(kind_e,kind, UVM_ALL_ON | UVM_NOPACK); 40 | `uvm_object_utils_end 41 | 42 | function new (string name = "apb_rw"); 43 | super.new(name); 44 | endfunction 45 | 46 | function string convert2string(); 47 | return $sformatf("kind=%s addr=%0h data=%0h",kind,addr,data); 48 | endfunction 49 | 50 | endclass: apb_rw 51 | 52 | endpackage 53 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/temporal_decoupling/tb_env.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2010 Mentor Graphics Corporation 3 | // Copyright 2010-2011 Synopsys, Inc 4 | // All Rights Reserved Worldwide 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the 7 | // "License"); you may not use this file except in 8 | // compliance with the License. You may obtain a copy of 9 | // the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in 14 | // writing, software distributed under the License is 15 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | // CONDITIONS OF ANY KIND, either express or implied. See 17 | // the License for the specific language governing 18 | // permissions and limitations under the License. 19 | //---------------------------------------------------------------------- 20 | 21 | class tb_env extends uvm_component; 22 | 23 | `uvm_component_utils(tb_env) 24 | 25 | initiator master; 26 | target slave; 27 | 28 | function new(string name = "tb_env", uvm_component parent = null); 29 | super.new(name, parent); 30 | endfunction 31 | 32 | function void build_phase(uvm_phase phase); 33 | master = initiator::type_id::create("master", this); 34 | slave = target::type_id::create("slave", this); 35 | endfunction 36 | 37 | function void connect_phase(uvm_phase phase); 38 | master.sock.connect(slave.sock); 39 | endfunction 40 | 41 | endclass 42 | -------------------------------------------------------------------------------- /test/examples/simple/tlm2/temporal_decoupling/tb_run.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------- 2 | // Copyright 2010 Mentor Graphics Corporation 3 | // Copyright 2010-2011 Synopsys, Inc. 4 | // All Rights Reserved Worldwide 5 | // 6 | // Licensed under the Apache License, Version 2.0 (the 7 | // "License"); you may not use this file except in 8 | // compliance with the License. You may obtain a copy of 9 | // the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in 14 | // writing, software distributed under the License is 15 | // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 16 | // CONDITIONS OF ANY KIND, either express or implied. See 17 | // the License for the specific language governing 18 | // permissions and limitations under the License. 19 | //---------------------------------------------------------------------- 20 | 21 | `include "apb_rw.sv" 22 | `include "initiator.sv" 23 | `include "target.sv" 24 | 25 | `timescale 1ns / 1ns 26 | 27 | program tb_run; 28 | 29 | import uvm_pkg::*; 30 | import init_pkg::*; 31 | import trgt_pkg::*; 32 | 33 | `include "tb_env.sv" 34 | 35 | initial 36 | begin 37 | static tb_env env = new("env"); 38 | 39 | run_test(); 40 | end 41 | 42 | endprogram 43 | -------------------------------------------------------------------------------- /test/hdl/uvm_test.v: -------------------------------------------------------------------------------- 1 | 2 | /* Mock module for testing uvm-python with cocotb and iverilog */ 3 | module uvm_test #( 4 | parameter DW = 16 5 | ) 6 | ( 7 | input clk, 8 | input rst, 9 | input[DW-1:0] data_in, 10 | output[DW-1:0] data_out 11 | ); 12 | 13 | reg[DW-1:0] data_reg; 14 | 15 | always@(posedge clk or negedge rst) 16 | if (!rst) 17 | data_reg <= 0; 18 | else 19 | data_reg <= data_in; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /test/sim_integration/module_top.sv: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------------- 2 | // File: module_top.sv 3 | // Created on 2020-01-08 4 | // Tuomas Poikela, tuomas.sakari.poikela@gmail.com 5 | // 6 | // Description: 7 | //--------------------------------------------------------------------------- 8 | 9 | `timescale 1ns/1ps 10 | 11 | module module_top(input clk, input rst); 12 | 13 | endmodule: module_top 14 | 15 | -------------------------------------------------------------------------------- /test/test_uvm_tlm.py: -------------------------------------------------------------------------------- 1 | 2 | import cocotb 3 | from cocotb.triggers import Timer, Join 4 | 5 | from uvm_testlib import * 6 | 7 | @cocotb.test(skip=False) 8 | def test_tlm_nb_put_basic(dut): 9 | consumer = UVMTestConsumer('consumer', None) 10 | producer = UVMTestProducer('producer', None) 11 | 12 | producer.put_b_port.connect(consumer.put_b_imp) 13 | producer.get_b_port.connect(consumer.get_b_imp) 14 | producer.put_b_port.resolve_bindings() 15 | producer.get_b_port.resolve_bindings() 16 | 17 | producer.put_port.connect(consumer.put_imp) 18 | producer.get_port.connect(consumer.get_imp) 19 | producer.put_port.resolve_bindings() 20 | producer.get_port.resolve_bindings() 21 | 22 | if producer.put_b_port.m_if is None: 23 | raise Exception('put_b_port.m_if does not exist') 24 | 25 | pproc = cocotb.fork(producer.run_phase(None)) 26 | #yield producer.run_phase(None) 27 | await consumer.wait_all_data() 28 | #yield [pproc.join(), wproc.join()] 29 | if consumer.count != 10: 30 | raise Exception('Consumer data count only {}'.format(consumer.count)) 31 | 32 | @cocotb.test(skip=False) 33 | def test_tlm_exports(dut): 34 | producer = UVMTestProducer('producer', None) 35 | exporter = UVMTestExporter('exporter', None) 36 | exporter.connect_phase(None) 37 | producer.put_port.connect(exporter.put_export) 38 | producer.put_port.resolve_bindings() 39 | 40 | pproc = cocotb.fork(producer.run_phase(None)) 41 | await exporter.wait_all_data() 42 | 43 | @cocotb.test(skip=False) 44 | def test_tlm_fifo(dut): 45 | fifo = UVMTLMAnalysisFIFO('fifo', None) 46 | fifo.write(1234); 47 | arr = [] 48 | if not fifo.try_get(arr): 49 | raise Exception('FIFO try-get failed') 50 | 51 | -------------------------------------------------------------------------------- /unit/test_uvm_analysis_port.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.tlm1.uvm_analysis_port import (UVMAnalysisImp, UVMAnalysisExport, 5 | UVMAnalysisPort) 6 | 7 | 8 | class TestUVMAnalysisPort(unittest.TestCase): 9 | 10 | def test_ports(self): 11 | from uvm.base.uvm_domain import UVMDomain 12 | from uvm.base.uvm_component import UVMComponent 13 | domains = UVMDomain.get_common_domain() 14 | 15 | class MyComp(UVMComponent): 16 | def build(self): 17 | self.analysis_imp = UVMAnalysisImp('ap', self) 18 | 19 | def write(self, t): 20 | self.written = True 21 | self.t = t 22 | 23 | imp = UVMComponent("port_parent", None) 24 | analysis_port = UVMAnalysisPort('aport', None) 25 | analysis_export = UVMAnalysisExport('my_export_in_test1', imp) 26 | targetComp = MyComp('my_comp', None) 27 | targetComp.build() 28 | analysis_port.connect(analysis_export) 29 | analysis_export.connect(targetComp.analysis_imp) 30 | #analysis_port.connect(targetComp.analysis_imp) 31 | analysis_port.resolve_bindings() 32 | 33 | analysis_port.write(12345) 34 | self.assertEqual(targetComp.written, True) 35 | self.assertEqual(targetComp.t, 12345) 36 | 37 | 38 | if __name__ == '__main__': 39 | unittest.main() 40 | -------------------------------------------------------------------------------- /unit/test_uvm_coreservice.py: -------------------------------------------------------------------------------- 1 | import unittest 2 | 3 | from uvm.base.uvm_coreservice import UVMCoreService 4 | 5 | 6 | class TestUVMCoreService(unittest.TestCase): 7 | 8 | def test_name(self): 9 | cs = UVMCoreService() 10 | root = cs.get_root() 11 | self.assertEqual(root.get_full_name(), "") 12 | 13 | 14 | if __name__ == '__main__': 15 | unittest.main() 16 | -------------------------------------------------------------------------------- /unit/test_uvm_domain.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_domain import UVMDomain 5 | from uvm.base.uvm_common_phases import UVMBuildPhase 6 | from uvm.base.uvm_phase import UVMPhase 7 | 8 | 9 | class TestUVMDomain(unittest.TestCase): 10 | 11 | 12 | def test_common(self): 13 | common = UVMDomain.get_common_domain() 14 | self.assertNotEqual(common, None) 15 | bld = common.find(UVMBuildPhase.get()) 16 | self.assertNotEqual(bld, None) 17 | 18 | 19 | def test_add_and_find(self): 20 | my_ph = UVMPhase('my_ph') 21 | dm = UVMDomain('my domain') 22 | dm.add(my_ph) 23 | my_ph2 = dm.find(my_ph) 24 | self.assertNotEqual(my_ph2, None) 25 | self.assertEqual(my_ph2.get_name(), 'my_ph') 26 | 27 | 28 | if __name__ == '__main__': 29 | unittest.main() 30 | -------------------------------------------------------------------------------- /unit/test_uvm_globals.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_globals import ( 5 | uvm_report_enabled, 6 | uvm_is_match 7 | ) 8 | 9 | from uvm.base.uvm_object_globals import ( 10 | UVM_INFO, UVM_MEDIUM, UVM_HIGH, 11 | UVM_FATAL 12 | ) 13 | 14 | 15 | class TestUVMGlobals(unittest.TestCase): 16 | 17 | def test_uvm_report_enabled(self): 18 | # Default verbosity that is set 19 | self.assertTrue(uvm_report_enabled(UVM_MEDIUM, UVM_INFO)) 20 | self.assertFalse(uvm_report_enabled(UVM_HIGH, UVM_INFO)) 21 | self.assertTrue(uvm_report_enabled(UVM_MEDIUM, UVM_FATAL)) 22 | 23 | 24 | def test_uvm_is_match(self): 25 | self.assertTrue(uvm_is_match("my_name*", "my_name.child1.c2")) 26 | self.assertFalse(uvm_is_match("your_name*", "my_name.child1.c2")) 27 | self.assertTrue(uvm_is_match("my_name????", "my_name.abc")) 28 | self.assertFalse(uvm_is_match("my_name??????", "my_name.abc")) 29 | self.assertTrue(uvm_is_match("zzz*www??yy", "zzz_abcdefg_wwwKKyy")) 30 | 31 | 32 | if __name__ == '__main__': 33 | unittest.main() 34 | -------------------------------------------------------------------------------- /unit/test_uvm_mailbox.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.base.uvm_mailbox import UVMMailbox 4 | 5 | 6 | class TestUVMMailbox(unittest.TestCase): 7 | 8 | def test_try_put(self): 9 | fifo = UVMMailbox(2) 10 | self.assertEqual(fifo.can_put(), True) 11 | self.assertEqual(fifo.can_get(), False) 12 | 13 | def test_try_get(self): 14 | fifo = UVMMailbox(2) 15 | self.assertEqual(fifo.can_get(), False) 16 | itemq = [] 17 | self.assertEqual(fifo.try_get(itemq), False) 18 | self.assertEqual(fifo.try_put(234), True) 19 | self.assertEqual(fifo.try_get(itemq), True) 20 | self.assertEqual(len(itemq), 1) 21 | self.assertEqual(itemq[0], 234) 22 | 23 | def test_unbounded(self): 24 | fifo = UVMMailbox() 25 | self.assertEqual(fifo.can_put(), True) 26 | for i in range(0, 10): 27 | self.assertEqual(fifo.try_put(i), True) 28 | arr = [] 29 | self.assertEqual(fifo.try_peek(arr), True) 30 | self.assertEqual(arr[0], 0) 31 | 32 | for i in range(0, 10): 33 | arr = [] 34 | self.assertEqual(fifo.try_get(arr), True) 35 | self.assertEqual(arr[0], i) 36 | 37 | 38 | 39 | if __name__ == '__main__': 40 | unittest.main() 41 | -------------------------------------------------------------------------------- /unit/test_uvm_misc.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.base.uvm_object_globals import ( 4 | UVM_DEC, UVM_BIN, UVM_HEX, UVM_OCT) 5 | from uvm.base.uvm_misc import ( 6 | uvm_leaf_scope, 7 | uvm_bitstream_to_string) 8 | 9 | 10 | class TestUVMMisc(unittest.TestCase): 11 | 12 | def test_uvm_leaf_scope(self): 13 | scope = uvm_leaf_scope("[ab]", "[") 14 | self.assertEqual(scope, "ab") 15 | scope = uvm_leaf_scope("[xx][ee][ab][cd]", "[") 16 | self.assertEqual(scope, "cd") 17 | #scope = uvm_leaf_scope("ab") 18 | scope = uvm_leaf_scope("a.b.leaf") 19 | self.assertEqual(scope, "leaf") 20 | scope = uvm_leaf_scope("leaf") 21 | self.assertEqual(scope, "leaf") 22 | #scope = uvm_leaf_scope("a#b#leaf", "#") 23 | #self.assertEqual(scope, "leaf") 24 | 25 | def test_uvm_bitstream_to_string(self): 26 | radix = [UVM_DEC, UVM_BIN, UVM_HEX, UVM_OCT] 27 | for rr in radix: 28 | num_str = uvm_bitstream_to_string(255, 8, rr) 29 | if rr == UVM_DEC: 30 | self.assertEqual(num_str, "{}".format(255)) 31 | elif rr == UVM_HEX: 32 | self.assertEqual(num_str, "{:X}".format(255)) 33 | elif rr == UVM_BIN: 34 | self.assertEqual(num_str, "{:b}".format(255)) 35 | 36 | num_str = uvm_bitstream_to_string(-245, 8, UVM_DEC) 37 | self.assertEqual(num_str, "-245") 38 | 39 | 40 | if __name__ == '__main__': 41 | unittest.main() 42 | -------------------------------------------------------------------------------- /unit/test_uvm_phase.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.base.uvm_phase import UVMPhase 4 | 5 | 6 | class TestUVMPhase(unittest.TestCase): 7 | 8 | def test_find(self): 9 | ph = UVMPhase() 10 | pred_ph = ph.find(ph) 11 | self.assertEqual(ph, pred_ph) 12 | ph1 = UVMPhase('unrelated') 13 | no_ph = ph.find(ph1) 14 | self.assertEqual(no_ph, None) 15 | 16 | 17 | if __name__ == '__main__': 18 | unittest.main() 19 | -------------------------------------------------------------------------------- /unit/test_uvm_ports.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_component import UVMComponent 5 | from uvm.tlm1.uvm_ports import ( 6 | UVMBlockingPutPort, UVMNonBlockingPutPort, 7 | UVMBlockingGetPort, UVMNonBlockingGetPort, 8 | ) 9 | 10 | from uvm.tlm1.uvm_imps import ( 11 | UVMNonBlockingPutImp, UVMNonBlockingGetImp 12 | ) 13 | 14 | 15 | class TestUVMPorts(unittest.TestCase): 16 | 17 | def test_non_blocking_put_port(self): 18 | source = UVMComponent('uvm_ports_comp', None) 19 | sink = UVMComponent('uvm_ports_comp2', None) 20 | 21 | def try_put(item): 22 | pass 23 | setattr(sink, 'try_put', try_put) 24 | 25 | put_port = UVMNonBlockingPutPort('my_port', source) 26 | put_imp = UVMNonBlockingPutImp('put_imp', sink) 27 | put_port.connect(put_imp) 28 | put_port.resolve_bindings() 29 | put_port.try_put(0x1234) 30 | # TODO add assert 31 | 32 | def test_blocking_put_port(self): 33 | comp = UVMComponent('comp', None) 34 | put_port = UVMBlockingPutPort('my_port', comp) 35 | self.assertEqual(put_port.is_port(), True) 36 | 37 | if __name__ == '__main__': 38 | unittest.main() 39 | -------------------------------------------------------------------------------- /unit/test_uvm_reg_block.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.reg.uvm_reg import UVMReg 4 | from uvm.reg.uvm_reg_block import UVMRegBlock 5 | from uvm.reg.uvm_reg_model import * 6 | 7 | 8 | class TestUVMRegBlock(unittest.TestCase): 9 | 10 | def test_add_reg(self): 11 | rb = UVMRegBlock("rb_blk") 12 | rb.create_map("", 0, 1, UVM_BIG_ENDIAN) 13 | reg1 = UVMReg("xx", 32, rb.get_full_name()) 14 | reg1.configure(rb, None, "acp") 15 | # reg1.build() 16 | rb.default_map.add_reg(reg1, 0x0000, "RW") 17 | print("len is now " + str(len(rb.regs))) 18 | rr = rb.get_reg_by_name('xx') 19 | self.assertEqual(rr.get_name(), 'xx') 20 | 21 | r_none = rb.get_reg_by_name('y_reg') 22 | self.assertEqual(r_none, None) 23 | 24 | def test_add_block(self): 25 | top_b = UVMRegBlock("top_reg_block") 26 | top_b.create_map("custom_map", 0x100, 4, UVM_LITTLE_ENDIAN) 27 | custom_map = top_b.get_map_by_name("custom_map") 28 | top_b.set_default_map(custom_map) 29 | self.assertIsNotNone(custom_map) 30 | for i in range(10): 31 | base_addr = i * 0x100 32 | sub_b = UVMRegBlock("sub_blk_" + str(i)) 33 | top_b.add_block(sub_b) 34 | top_b.configure(parent=None, hdl_path="") 35 | top_b.lock_model() 36 | 37 | 38 | if __name__ == '__main__': 39 | unittest.main() 40 | -------------------------------------------------------------------------------- /unit/test_uvm_reg_model.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.reg.uvm_reg_model import * 4 | 5 | 6 | class TestUVMRegModel(unittest.TestCase): 7 | 8 | 9 | def test_concat2string(self): 10 | concat = uvm_hdl_path_concat() 11 | path_sli = uvm_hdl_path_slice() 12 | path_sli.path = "dut" 13 | concat.add_path(path_sli.path) 14 | str_path = uvm_hdl_concat2string(concat) 15 | self.assertEqual(str_path, "dut") 16 | concat.add_path("test_reg") 17 | str_path = uvm_hdl_concat2string(concat) 18 | self.assertEqual(str_path, "{dut, test_reg}") 19 | 20 | 21 | if __name__ == '__main__': 22 | unittest.main() 23 | -------------------------------------------------------------------------------- /unit/test_uvm_reg_predictor.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.reg.uvm_reg_predictor import UVMRegPredictor, UVMPredictS 5 | 6 | from uvm.uvm_unit import (create_reg, create_reg_block, TestPacket, 7 | TestRegAdapter) 8 | 9 | 10 | class TestUVMRegPredictor(unittest.TestCase): 11 | 12 | def test_create_predictor(self): 13 | predict = UVMRegPredictor("predictor_123", None) 14 | self.assertEqual(predict.get_name(), "predictor_123") 15 | 16 | def test_predict(self): 17 | predict = UVMRegPredictor("predictor_345", None) 18 | predict.adapter = TestRegAdapter() 19 | rg = create_reg_block('my_block') 20 | rg.lock_model() 21 | predict.map = rg.default_map 22 | predict.bus_in.write(TestPacket(123, 0x0)) 23 | 24 | def test_check_phase(self): 25 | predict = UVMRegPredictor("predictor_567", None) 26 | predict.check_phase(phase=None) 27 | predict.m_pending[create_reg('test_reg')] = UVMPredictS() 28 | predict.check_phase(phase=None) 29 | 30 | 31 | if __name__ == '__main__': 32 | unittest.main() 33 | -------------------------------------------------------------------------------- /unit/test_uvm_registry.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_registry import UVMComponentRegistry, UVMObjectRegistry 5 | from uvm.macros.uvm_object_defines import uvm_component_utils, uvm_object_utils 6 | 7 | 8 | class TestUVMRegistry(unittest.TestCase): 9 | 10 | 11 | def test_object_registry(self): 12 | class ABC: 13 | def __init__(self, name): 14 | self.name = name 15 | self.value = 5 16 | uvm_object_utils(ABC) 17 | reg = UVMObjectRegistry(ABC, 'ABC') 18 | abc_obj = reg.create('obj_name') 19 | self.assertEqual(abc_obj.name, 'obj_name') 20 | self.assertEqual(isinstance(abc_obj, ABC), True) 21 | 22 | 23 | def test_component_registry(self): 24 | class ABC: 25 | def __init__(self, name, parent): 26 | self.name = name 27 | self.parent = parent 28 | uvm_component_utils(ABC) 29 | reg = UVMComponentRegistry(ABC, 'ABC') 30 | abc_comp = reg.create('inst_name', None) 31 | self.assertEqual(abc_comp.name, 'inst_name') 32 | self.assertEqual(abc_comp.parent, None) 33 | 34 | 35 | if __name__ == '__main__': 36 | unittest.main() 37 | -------------------------------------------------------------------------------- /unit/test_uvm_report_catcher.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.base.uvm_report_catcher import UVMReportCatcher 4 | 5 | 6 | class MyReportCatcher(UVMReportCatcher): 7 | 8 | def __init__(self, name='catcher'): 9 | super().__init__(name) 10 | 11 | def catch(self): 12 | self.sev = self.get_severity() 13 | self._id = self.get_id() 14 | 15 | 16 | class TestUVMReportCatcher(unittest.TestCase): 17 | 18 | def test_catcher(self): 19 | rpt_catcher = MyReportCatcher('catcher') 20 | 21 | 22 | if __name__ == '__main__': 23 | unittest.main() 24 | -------------------------------------------------------------------------------- /unit/test_uvm_report_handler.py: -------------------------------------------------------------------------------- 1 | 2 | 3 | import unittest 4 | 5 | from uvm.base.uvm_report_handler import UVMReportHandler 6 | from uvm.base.uvm_object_globals import * 7 | 8 | 9 | class TestUVMReportHandler(unittest.TestCase): 10 | 11 | def test_handler(self): 12 | rh = UVMReportHandler("handler") 13 | fhandle = rh.get_severity_id_file(UVM_ERROR, "") 14 | self.assertEqual(fhandle, rh.default_file_handle) 15 | verb = rh.get_verbosity_level() 16 | self.assertEqual(verb, rh.m_max_verbosity_level) 17 | rh.report(UVM_ERROR, "xxx", "id0", "Message") 18 | 19 | 20 | def test_action_overrides(self): 21 | rh = UVMReportHandler("handler") 22 | rh.set_severity_action(UVM_ERROR, UVM_LOG) 23 | rh.set_severity_id_action(UVM_ERROR, "XYZ", UVM_COUNT) 24 | 25 | verb = rh.get_action(UVM_ERROR, "ABC") 26 | self.assertEqual(verb, UVM_LOG) 27 | verb = rh.get_action(UVM_ERROR, "XYZ") 28 | self.assertEqual(verb, UVM_COUNT) 29 | 30 | 31 | if __name__ == '__main__': 32 | unittest.main() 33 | -------------------------------------------------------------------------------- /unit/test_uvm_report_message.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_report_message import UVMReportMessage 5 | from uvm.base.uvm_object_globals import UVM_LOG 6 | 7 | 8 | class TestUVMReportMessage(unittest.TestCase): 9 | 10 | def test_message(self): 11 | msg = UVMReportMessage() 12 | cont = msg.get_element_container() 13 | self.assertEqual(cont.size(), 0) 14 | msg.add("msg", {1: 2}, UVM_LOG) 15 | self.assertEqual(cont.size(), 1) 16 | 17 | def test_msg_copy(self): 18 | msg = UVMReportMessage.new_report_message() 19 | msg.set_message("My message is this") 20 | msg.set_verbosity(111) 21 | msg.set_filename('log.txt') 22 | msg_copy = msg.clone() 23 | 24 | self.assertEqual(msg_copy.get_name(), msg.get_name()) 25 | self.assertEqual(msg_copy.get_verbosity(), msg.get_verbosity()) 26 | self.assertEqual(msg_copy.get_filename(), msg.get_filename()) 27 | 28 | msg_copy = UVMReportMessage() 29 | msg_copy.copy(msg) 30 | self.assertEqual(msg_copy.get_message(), msg.get_message()) 31 | 32 | 33 | if __name__ == '__main__': 34 | unittest.main() 35 | -------------------------------------------------------------------------------- /unit/test_uvm_report_object.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.base.uvm_report_object import UVMReportObject 4 | from uvm.base.uvm_object_globals import ( 5 | UVM_INFO, UVM_ERROR, UVM_LOG, UVM_DISPLAY, UVM_COUNT, UVM_MEDIUM, UVM_HIGH) 6 | 7 | 8 | class TestUVMReportObject(unittest.TestCase): 9 | """ Unit tests for UVMReportObject """ 10 | 11 | def test_verbosity(self): 12 | obj = UVMReportObject('rpt') 13 | rh = obj.get_report_handler() 14 | verb = rh.get_verbosity_level(UVM_INFO, "") 15 | self.assertEqual(verb, UVM_MEDIUM) 16 | self.assertEqual(obj.uvm_report_enabled(UVM_MEDIUM, UVM_INFO), True) 17 | 18 | def test_report_enabled(self): 19 | obj = UVMReportObject('rpt') 20 | is_en = obj.uvm_report_enabled(UVM_MEDIUM, UVM_INFO, id="") 21 | self.assertEqual(is_en, True) 22 | is_en = obj.uvm_report_enabled(UVM_HIGH, UVM_INFO, id="") 23 | self.assertEqual(is_en, False) 24 | 25 | def test_report_severity(self): 26 | obj = UVMReportObject('rpt') 27 | act = obj.get_report_action(UVM_ERROR, id="") 28 | self.assertEqual(act, UVM_DISPLAY | UVM_COUNT) 29 | act = obj.get_report_action(UVM_INFO, id="") 30 | self.assertEqual(act, UVM_DISPLAY) 31 | 32 | obj.set_report_severity_action(UVM_ERROR, UVM_LOG) 33 | act = obj.get_report_action(UVM_ERROR, id="") 34 | self.assertEqual(act, UVM_LOG) 35 | 36 | 37 | 38 | if __name__ == '__main__': 39 | unittest.main() 40 | -------------------------------------------------------------------------------- /unit/test_uvm_resource_db.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_resource_db import (UVMResourceDb, ResourceDbClassFactory) 5 | 6 | 7 | class TestUVMResourceDb(unittest.TestCase): 8 | 9 | 10 | def test_create_class(self): 11 | DbInt = ResourceDbClassFactory('DbInt', ['_id', 'val2'], int) 12 | DbStr = ResourceDbClassFactory('DbStr', ['_id', 'val2'], str) 13 | my_db_int = DbInt(_id=123, val2='name') 14 | my_db_str = DbStr(_id=123, val2='name') 15 | self.assertEqual(my_db_int.T, int) 16 | self.assertEqual(my_db_str.T, str) 17 | my_db_int.set('*', 'value', 123) 18 | my_db_str.set('*', 'value', 'str_value') 19 | rsc_int = my_db_int.get_by_name('*', 'value') 20 | rsc_str = my_db_str.get_by_name('*', 'value') 21 | self.assertEqual(rsc_int.read(), 123) 22 | # TODO self.assertEqual(rsc_str.read(), 'str_value') 23 | -------------------------------------------------------------------------------- /unit/test_uvm_root.py: -------------------------------------------------------------------------------- 1 | 2 | # UNIT TESTS 3 | 4 | import unittest 5 | from uvm.base.uvm_root import UVMRoot 6 | 7 | 8 | class TestUVMRoot(unittest.TestCase): 9 | 10 | def test_name(self): 11 | root = UVMRoot() 12 | self.assertEqual(root.get_name(), "") 13 | 14 | def test_singleton(self): 15 | root1 = UVMRoot.m_uvm_get_root() 16 | root2 = UVMRoot.m_uvm_get_root() 17 | self.assertEqual(root1, root2) 18 | 19 | async def test_run_phase(self): 20 | root = UVMRoot() 21 | await root.run_phase() 22 | 23 | 24 | if __name__ == '__main__': 25 | unittest.main() 26 | -------------------------------------------------------------------------------- /unit/test_uvm_scope_stack.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_scope_stack import UVMScopeStack 5 | 6 | 7 | class TestUVMScopeStack(unittest.TestCase): 8 | 9 | def test_depth(self): 10 | stack = UVMScopeStack() 11 | self.assertEqual(stack.depth(), 0) 12 | 13 | def test_down_and_up(self): 14 | stack = UVMScopeStack() 15 | stack.down('xxx') 16 | stack.down('yyy') 17 | stack.down('zzz') 18 | self.assertEqual(stack.get(), 'xxx.yyy.zzz') 19 | self.assertEqual(stack.depth(), 3) 20 | stack.up() 21 | self.assertEqual(stack.get(), 'xxx.yyy') 22 | 23 | def test_down_and_up_element(self): 24 | stack = UVMScopeStack() 25 | stack.down('uvm_top') 26 | stack.down_element(4) 27 | self.assertEqual(stack.get(), 'uvm_top[4]') 28 | self.assertEqual(stack.depth(), 2) 29 | stack.up_element() 30 | self.assertEqual(stack.get(), 'uvm_top') 31 | 32 | 33 | if __name__ == '__main__': 34 | unittest.main() 35 | -------------------------------------------------------------------------------- /unit/test_uvm_sequencer_base.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.seq.uvm_sequencer_base import UVMSequencerBase 4 | 5 | from uvm.uvm_unit import MockObj 6 | 7 | class MockSeq(MockObj): 8 | 9 | def __init__(self, name='mock_seq', parent=None): 10 | super().__init__(name, parent) 11 | self.parent = parent 12 | 13 | def get_parent_sequence(self): 14 | return self.parent 15 | 16 | 17 | class TestUVMReg(unittest.TestCase): 18 | 19 | def test_init(self): 20 | sqr = UVMSequencerBase('new_sqr_123', None) 21 | self.assertFalse(sqr.is_grabbed()) 22 | seq1 = MockSeq('seq1') 23 | seq2 = MockSeq('seq2') 24 | self.assertFalse(sqr.is_child(seq1, seq2)) 25 | par_seq3 = MockSeq('par_seq3') 26 | seq4 = MockSeq('seq2', par_seq3) 27 | self.assertTrue(sqr.is_child(par_seq3, seq4)) 28 | 29 | 30 | if __name__ == '__main__': 31 | unittest.main() 32 | -------------------------------------------------------------------------------- /unit/test_uvm_spell_chkr.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.base.uvm_spell_chkr import UVMSpellChkr 5 | 6 | 7 | class TestUVMSpellChkr(unittest.TestCase): 8 | 9 | def test_check_exact_match(self): 10 | strtab = {'xxx': 1, 'yyy': 2} 11 | self.assertTrue(UVMSpellChkr.check(strtab, 'xxx')) 12 | self.assertFalse(UVMSpellChkr.check(strtab, 'vvv')) 13 | 14 | 15 | if __name__ == '__main__': 16 | unittest.main() 17 | -------------------------------------------------------------------------------- /unit/test_uvm_sqr_connections.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | 4 | from uvm.tlm1 import UVMSeqItemPullExport 5 | 6 | 7 | class TestUVMSeqItemPullExport(unittest.TestCase): 8 | 9 | def test_new(self): 10 | pull_exp = UVMSeqItemPullExport('pull_export', None) 11 | self.assertEqual(pull_exp.get_name(), 'pull_export') 12 | 13 | 14 | if __name__ == '__main__': 15 | unittest.main() 16 | -------------------------------------------------------------------------------- /unit/test_uvm_tlm_fifos.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.tlm1.uvm_tlm_fifos import (UVMTLMAnalysisFIFO, UVMTLMFIFO) 4 | 5 | 6 | class TestUVMTLMFIFO(unittest.TestCase): 7 | 8 | def test_flush(self): 9 | fifo = UVMTLMFIFO('tlm_fifo', None) 10 | fifo.flush() 11 | self.assertEqual(fifo.used(), 0) 12 | self.assertTrue(fifo.is_empty()) 13 | 14 | 15 | class TestUVMTLMAnalysisFIFO(unittest.TestCase): 16 | 17 | def test_write_and_get(self): 18 | fifo = UVMTLMAnalysisFIFO('fifo', None) 19 | fifo.write(12345) 20 | arr = [] 21 | self.assertEqual(fifo.try_get(arr), True) 22 | self.assertEqual(arr[0], 12345) 23 | self.assertEqual(fifo.can_get(), False) 24 | self.assertEqual(fifo.try_put('xxx'), True) 25 | self.assertEqual(fifo.can_get(), True) 26 | arr = [] 27 | self.assertEqual(fifo.try_get(arr), True) 28 | self.assertEqual(arr[0], 'xxx') 29 | 30 | def test_try_put(self): 31 | fifo = UVMTLMAnalysisFIFO('fifo2', None) 32 | for i in range(10): 33 | ok = fifo.try_put(i * 2 + 1) 34 | self.assertTrue(ok) 35 | for i in range(10): 36 | arr = [] 37 | ok = fifo.try_get(arr) 38 | self.assertEqual(arr[0], i * 2 + 1) 39 | -------------------------------------------------------------------------------- /unit/test_uvm_tlm_imps.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm import (UVM_IMP_COMMON, UVM_TLM_NONBLOCKING_PUT_MASK) 4 | 5 | 6 | class TestUVMTLMImps(unittest.TestCase): 7 | 8 | def test_uvm_imp_common(self): 9 | from uvm.base.uvm_port_base import UVMPortBase 10 | from uvm.base.uvm_component import UVMComponent 11 | 12 | class MyTest(): 13 | pass 14 | MyTest = UVM_IMP_COMMON(MyTest, UVM_TLM_NONBLOCKING_PUT_MASK, 'MyTest') 15 | obj = MyTest('MyPort', UVMComponent('xxx', None)) 16 | self.assertEqual(obj.get_type_name(), 'MyTest') 17 | self.assertEqual(obj.is_imp(), True) 18 | self.assertEqual(isinstance(obj, UVMPortBase), True) 19 | 20 | 21 | if __name__ == '__main__': 22 | unittest.main() 23 | -------------------------------------------------------------------------------- /unit/test_uvm_topdown_phase.py: -------------------------------------------------------------------------------- 1 | 2 | import unittest 3 | from uvm.base.uvm_component import UVMComponent 4 | from uvm.base.uvm_topdown_phase import UVMTopdownPhase 5 | from uvm.base.uvm_phase import UVMPhase 6 | from uvm.base.uvm_object_globals import * 7 | 8 | 9 | class TestUVMTopdownPhase(unittest.TestCase): 10 | 11 | 12 | def test_traverse(self): 13 | c1 = UVMComponent('uvm_test_top__test_uvm_topdown_phase', None) 14 | c2 = UVMComponent('sub_c1', c1) 15 | c3 = UVMComponent('sub_c2', c1) 16 | c4 = UVMComponent('sub_c2_c4', c2) 17 | td_phase = UVMTopdownPhase('MyPhase') 18 | states = [UVM_PHASE_STARTED, UVM_PHASE_READY_TO_END, UVM_PHASE_ENDED] 19 | phase = UVMPhase('MyActualPhase') 20 | for state in states: 21 | td_phase.traverse(c1, phase, state) 22 | 23 | children_c1 = [] 24 | c1.get_children(children_c1) 25 | 26 | children_c2 = [] 27 | c2.get_children(children_c2) 28 | self.assertEqual(len(children_c2), 1) 29 | self.assertEqual(children_c2[0].get_name(), c4.get_name()) 30 | 31 | 32 | if __name__ == '__main__': 33 | unittest.main() 34 | --------------------------------------------------------------------------------