├── .gitlab-ci.yml ├── .gitmodules ├── doc ├── address_allocation.md └── reference │ ├── Datasheets │ ├── Ethernet_DM9000A-DS-F01-101906.pdf │ ├── Flash_JS28F640J3D75.pdf │ ├── Graphics_tfp410.pdf │ ├── SRAM_IS61WV102416ALL.pdf │ └── USB_SL811HS.pdf │ ├── MIPS32 Spec │ ├── MIPS_Vol1.pdf │ ├── MIPS_Vol1_R2.pdf │ ├── MIPS_Vol2.pdf │ ├── MIPS_Vol2_R2.pdf │ ├── MIPS_Vol3.pdf │ └── MIPS_Vol3_R2.pdf │ ├── Vivado使用误区与进阶.pdf │ ├── pg060-floating-point.pdf │ ├── thinpad-offline-manual-2.pdf │ └── verilator_doc.pdf ├── src ├── ThinPad.sv ├── bus │ ├── data_bus.sv │ └── instruction_bus.sv ├── common_defs.svh ├── compile_option.svh ├── cpu │ ├── cp0 │ │ ├── cp0.sv │ │ ├── cp0_write_mask.sv │ │ └── lfsr.sv │ ├── cpu_defs.svh │ ├── ctrl.sv │ ├── ex │ │ ├── cpu_ex.sv │ │ ├── div_uu.v │ │ ├── ex_count_bit.sv │ │ ├── ex_ext.sv │ │ ├── ex_mem.sv │ │ ├── ex_multi_cyc.sv │ │ ├── fpu_ex.sv │ │ └── fpu_float2int.sv │ ├── except.sv │ ├── fpu_regs.sv │ ├── hilo.sv │ ├── id │ │ ├── branch.sv │ │ ├── cpu_id.sv │ │ ├── fcsr_mux.sv │ │ ├── fpu_id.sv │ │ ├── id_ex.sv │ │ ├── id_type_i.sv │ │ ├── id_type_j.sv │ │ ├── id_type_r.sv │ │ └── superscalar_ctrl.sv │ ├── if │ │ ├── cpu_if.sv │ │ ├── if_id.sv │ │ └── reg_pc.sv │ ├── ll_bit.sv │ ├── mem │ │ ├── cpu_mem.sv │ │ └── mem_wb.sv │ ├── mmu │ │ ├── mmu.sv │ │ ├── tlb.sv │ │ └── tlb_lookup.sv │ ├── regs.sv │ ├── trivial_mips.sv │ └── wb │ │ └── cpu_wb.sv ├── peripheral │ ├── bootrom_controller.sv │ ├── dummy_controller.sv │ ├── ethernet_controller.sv │ ├── flash_controller.sv │ ├── gpio_controller.sv │ ├── graphics_controller.sv │ ├── sram_controller.sv │ ├── timer_controller.sv │ ├── uart_controller.sv │ └── usb_controller.sv └── utility │ ├── color_mapper.sv │ ├── led_decoder.sv │ └── uart_transceiver.sv ├── testbench ├── README.md ├── behav_model │ ├── 28F640P30.v │ ├── include │ │ ├── BankLib.h │ │ ├── CUIcommandData.h │ │ ├── TimingData.h │ │ ├── UserData.h │ │ ├── data.h │ │ └── def.h │ └── sram_model.v ├── clock.sv ├── cloud │ └── cloud_test.py ├── cpu │ ├── fake_data_bus.sv │ ├── fake_inst_bus.sv │ ├── test_cpu.sv │ ├── test_cpu_one.sv │ ├── testcase │ │ ├── Makefile │ │ ├── across_tlb1.ans │ │ ├── across_tlb1.mem │ │ ├── across_tlb1.s │ │ ├── across_tlb2.ans │ │ ├── across_tlb2.mem │ │ ├── across_tlb2.s │ │ ├── across_tlb3.ans │ │ ├── across_tlb3.mem │ │ ├── across_tlb3.s │ │ ├── across_tlb4.ans │ │ ├── across_tlb4.mem │ │ ├── across_tlb4.s │ │ ├── across_tlb5.ans │ │ ├── across_tlb5.mem │ │ ├── across_tlb5.s │ │ ├── across_tlb6.ans │ │ ├── across_tlb6.mem │ │ ├── across_tlb6.s │ │ ├── build.sh │ │ ├── except.ans │ │ ├── except.mem │ │ ├── except.s │ │ ├── except_delayslot.ans │ │ ├── except_delayslot.mem │ │ ├── except_delayslot.s │ │ ├── extract_ans.awk │ │ ├── fpu_arith.ans │ │ ├── fpu_arith.mem │ │ ├── fpu_arith.s │ │ ├── fpu_arith2.ans │ │ ├── fpu_arith2.mem │ │ ├── fpu_arith2.s │ │ ├── fpu_compare.ans │ │ ├── fpu_compare.mem │ │ ├── fpu_compare.s │ │ ├── fpu_test1.ans │ │ ├── fpu_test1.mem │ │ ├── fpu_test2.ans │ │ ├── fpu_test2.mem │ │ ├── fpu_test2.s │ │ ├── fpu_test3.ans │ │ ├── fpu_test3.mem │ │ ├── fpu_test3.s │ │ ├── fpu_transfer.ans │ │ ├── fpu_transfer.mem │ │ ├── fpu_transfer.s │ │ ├── inst_arith.ans │ │ ├── inst_arith.mem │ │ ├── inst_arith.s │ │ ├── inst_ext.ans │ │ ├── inst_ext.mem │ │ ├── inst_ext.s │ │ ├── inst_jump.ans │ │ ├── inst_jump.mem │ │ ├── inst_jump.s │ │ ├── inst_llsc.ans │ │ ├── inst_llsc.mem │ │ ├── inst_llsc.s │ │ ├── inst_logical.ans │ │ ├── inst_logical.mem │ │ ├── inst_logical.s │ │ ├── inst_mem_aligned.ans │ │ ├── inst_mem_aligned.mem │ │ ├── inst_mem_aligned.s │ │ ├── inst_mem_unaligned.ans │ │ ├── inst_mem_unaligned.mem │ │ ├── inst_mem_unaligned.s │ │ ├── inst_move.ans │ │ ├── inst_move.mem │ │ ├── inst_move.s │ │ ├── inst_multicyc.ans │ │ ├── inst_multicyc.mem │ │ ├── inst_multicyc.s │ │ ├── inst_ori.ans │ │ ├── inst_ori.mem │ │ ├── inst_ori.s │ │ ├── inst_shift.ans │ │ ├── inst_shift.mem │ │ ├── inst_shift.s │ │ ├── inst_trap.ans │ │ ├── inst_trap.mem │ │ ├── inst_trap.s │ │ ├── interrupt.ans │ │ ├── interrupt.mem │ │ ├── interrupt.s │ │ ├── superscalar.ans │ │ ├── superscalar.mem │ │ ├── superscalar.s │ │ ├── timer.ans │ │ ├── timer.mem │ │ ├── timer.s │ │ ├── usermode.ans │ │ ├── usermode.mem │ │ └── usermode.s │ └── verilator │ │ ├── Makefile │ │ ├── cpu_tb.cpp │ │ ├── cpu_tb.sv │ │ ├── testbench.h │ │ └── verilator.vlt ├── peripheral │ └── peripheral_tb.sv └── thinpad │ ├── mem_init │ ├── base.bin │ ├── ext.bin │ └── flash.bin │ └── thinpad_tb.sv └── vivado ├── .gitignore ├── TrivialMIPS.hw └── TrivialMIPS.lpr ├── TrivialMIPS.ip_user_files └── README.txt ├── TrivialMIPS.srcs ├── bootrom.coe ├── constrs_1 │ └── new │ │ ├── PortConnection.xdc │ │ └── Timing.xdc └── ip │ ├── blk_mem_bootrom │ └── blk_mem_bootrom.xci │ ├── blk_mem_graphics │ └── blk_mem_graphics.xci │ ├── fifo_uart_rx │ └── fifo_uart_rx.xci │ ├── fifo_uart_tx │ └── fifo_uart_tx.xci │ ├── floating_point_add │ └── floating_point_add.xci │ ├── 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