├── .gitattributes ├── .gitignore ├── .gitlab-ci.yml ├── .gitmodules ├── AUTHORS ├── LICENSE ├── README.md ├── loongson ├── cpu_gs232 │ └── .gitignore ├── soc_axi_func │ ├── rtl │ │ ├── CONFREG │ │ │ └── confreg.v │ │ ├── axi_wrap │ │ │ └── axi_wrap.v │ │ ├── myCPU │ │ │ ├── ip_repo │ │ │ │ └── cpu_internal_crossbar │ │ │ │ │ └── cpu_internal_crossbar.xci │ │ │ └── mycpu_top.v │ │ ├── ram_wrap │ │ │ └── axi_wrap_ram.v │ │ ├── soc_axi_lite_top.v │ │ └── xilinx_ip │ │ │ ├── axi_clock_converter │ │ │ └── axi_clock_converter.xci │ │ │ ├── axi_crossbar_1x2 │ │ │ └── axi_crossbar_1x2.xci │ │ │ ├── axi_ram │ │ │ └── axi_ram.xci │ │ │ └── clk_pll │ │ │ └── clk_pll.xci │ ├── run_vivado │ │ ├── mycpu_prj1 │ │ │ ├── .gitignore │ │ │ ├── mycpu.xpr │ │ │ └── tb_top_behav.wcfg │ │ └── soc_lite.xdc │ └── testbench │ │ ├── golden_trace.txt │ │ ├── mycpu_tb.v │ │ └── nontrivial_mips_tb.sv ├── soc_axi_perf │ ├── rtl │ │ ├── CONFREG │ │ │ └── confreg.v │ │ ├── axi_wrap │ │ │ └── axi_wrap.v │ │ ├── myCPU │ │ │ ├── ip_repo │ │ │ │ └── cpu_internal_crossbar │ │ │ │ │ └── cpu_internal_crossbar.xci │ │ │ └── mycpu_top.v │ │ ├── ram_wrap │ │ │ └── axi_wrap_ram.v │ │ ├── soc_axi_lite_top.v │ │ └── xilinx_ip │ │ │ ├── axi_clock_converter │ │ │ └── axi_clock_converter.xci │ │ │ ├── axi_crossbar_1x2 │ │ │ └── axi_crossbar_1x2.xci │ │ │ ├── axi_ram │ │ │ └── axi_ram.xci │ │ │ └── clk_pll │ │ │ └── clk_pll.xci │ ├── run_vivado │ │ ├── mycpu_prj1 │ │ │ ├── .gitignore │ │ │ ├── mycpu.xpr │ │ │ └── run_allbench.tcl │ │ └── soc_lite.xdc │ └── testbench │ │ ├── mycpu_tb.v │ │ ├── nontrivial_mips_tb.sv │ │ ├── stats.sv │ │ └── trace_gen.sv ├── soc_run_os │ ├── rtl │ │ ├── AMBA │ │ │ ├── axi2apb.v │ │ │ └── axi_mux.v │ │ ├── APB_DEV │ │ │ ├── NAND │ │ │ │ └── nand.v │ │ │ ├── URT │ │ │ │ ├── raminfr.v │ │ │ │ ├── uart_defines.h │ │ │ │ ├── uart_receiver.v │ │ │ │ ├── uart_regs.v │ │ │ │ ├── uart_rfifo.v │ │ │ │ ├── uart_sync_flops.v │ │ │ │ ├── uart_tfifo.v │ │ │ │ ├── uart_top.v │ │ │ │ └── uart_transmitter.v │ │ │ ├── apb_dev_top.v │ │ │ ├── apb_mux2.v │ │ │ └── nand_module.v │ │ ├── CONFREG │ │ │ └── confreg.v │ │ ├── DMA │ │ │ └── dma.v │ │ ├── MAC │ │ │ ├── bd.v │ │ │ ├── csr.v │ │ │ ├── dma.v │ │ │ ├── ethernet_top.v │ │ │ ├── mac.v │ │ │ ├── mac2axi.v │ │ │ ├── mac_axi.v │ │ │ ├── mac_top.v │ │ │ ├── maccsr2axi.v │ │ │ ├── macdata2axi.v │ │ │ ├── rc.v │ │ │ ├── rfifo.v │ │ │ ├── rlsm.v │ │ │ ├── rstc.v │ │ │ ├── tc.v │ │ │ ├── tfifo.v │ │ │ ├── tlsm.v │ │ │ └── utility.v │ │ ├── SPI │ │ │ └── godson_sbridge_spi.v │ │ └── TOP │ │ │ ├── config.h │ │ │ └── soc_up_top.v │ ├── simu │ │ ├── run │ │ │ └── run_func │ │ │ │ ├── lib.list │ │ │ │ ├── ncompile │ │ │ │ ├── rtl.list │ │ │ │ ├── run.f │ │ │ │ └── sys.list │ │ ├── soft │ │ │ └── func │ │ │ │ ├── Makefile │ │ │ │ ├── config.h │ │ │ │ ├── convert.c │ │ │ │ ├── include │ │ │ │ ├── Calendar.h │ │ │ │ ├── Infrare.h │ │ │ │ ├── Interrupt.h │ │ │ │ ├── MonthData.h │ │ │ │ ├── SystemInit.h │ │ │ │ ├── adc.h │ │ │ │ ├── asm │ │ │ │ │ ├── interrupt.h │ │ │ │ │ ├── mipsregs.h │ │ │ │ │ ├── ns16550.h │ │ │ │ │ └── regdef.h │ │ │ │ ├── battery.h │ │ │ │ ├── cmdline.h │ │ │ │ ├── common.h │ │ │ │ ├── dg_rs232.h │ │ │ │ ├── flash.h │ │ │ │ ├── frame.h │ │ │ │ ├── isp.h │ │ │ │ ├── key.h │ │ │ │ ├── lcd.h │ │ │ │ ├── ls1d.h │ │ │ │ ├── temp_flow.h │ │ │ │ └── xmodem.h │ │ │ │ ├── lib │ │ │ │ ├── Makefile │ │ │ │ ├── memcmp.c │ │ │ │ ├── memcpy.c │ │ │ │ ├── memset.c │ │ │ │ ├── printbase.c │ │ │ │ ├── printf.c │ │ │ │ ├── printhex.c │ │ │ │ ├── putchar.c │ │ │ │ ├── puts.c │ │ │ │ ├── strcat.c │ │ │ │ ├── strchr.c │ │ │ │ ├── strcmp.c │ │ │ │ ├── strcspn.c │ │ │ │ ├── strspn.c │ │ │ │ ├── strtok.c │ │ │ │ └── udelay.c │ │ │ │ ├── main.c │ │ │ │ ├── nand_test.S │ │ │ │ ├── source │ │ │ │ ├── Calendar.c │ │ │ │ ├── Infrare.c │ │ │ │ ├── Interrupt.c │ │ │ │ ├── MonthData.c │ │ │ │ ├── SystemInit.c │ │ │ │ ├── adc.c │ │ │ │ ├── battery.c │ │ │ │ ├── cmdline.c │ │ │ │ ├── common.c │ │ │ │ ├── dg_rs232.c │ │ │ │ ├── flash.c │ │ │ │ ├── frame.c │ │ │ │ ├── isp.c │ │ │ │ ├── key.c │ │ │ │ ├── lcd.c │ │ │ │ ├── temp_flow.c │ │ │ │ └── xmodem.c │ │ │ │ ├── start.S │ │ │ │ └── test.lds │ │ └── testbench │ │ │ ├── MX25L6405D.v │ │ │ ├── ddr3_model.sv │ │ │ ├── ddr3_model_parameters.vh │ │ │ ├── ejtag_virtual_host.v │ │ │ ├── godson_system.v │ │ │ ├── nand_sim.v │ │ │ ├── uart_dev.v │ │ │ └── vmac │ │ │ ├── mac2ahb_package.v │ │ │ ├── mac_ram.v │ │ │ ├── mac_top.v │ │ │ ├── ram.vlog │ │ │ └── virtual_mac.v │ └── vivado_xpr │ │ ├── project_1 │ │ ├── project_1 │ │ │ ├── .gitignore │ │ │ └── project_1.xpr │ │ └── xilinx_ip │ │ │ ├── axi_interconnect_0 │ │ │ └── axi_interconnect_0.xci │ │ │ ├── clk_pll_33 │ │ │ └── clk_pll_33.xci │ │ │ ├── clk_wiz_0 │ │ │ └── clk_wiz_0.xci │ │ │ ├── dpram_512x32 │ │ │ └── dpram_512x32.xci │ │ │ ├── mig_axi_32 │ │ │ ├── mig_a.prj │ │ │ └── mig_axi_32.xci │ │ │ ├── sram_128x22 │ │ │ └── sram_128x22.xci │ │ │ ├── sram_128x32 │ │ │ └── sram_128x32.xci │ │ │ ├── sram_128x64 │ │ │ └── sram_128x64.xci │ │ │ └── sram_32x52bit │ │ │ └── sram_32x52bit.xci │ │ └── soc_up.xdc └── soft │ ├── func │ └── obj │ │ └── inst_ram.coe │ ├── memory_game │ └── obj │ │ └── axi_ram.coe │ └── perf_func │ └── obj │ ├── allbench │ └── axi_ram.coe │ ├── bitcount │ └── axi_ram.mif │ ├── bubble_sort │ └── axi_ram.mif │ ├── coremark │ └── axi_ram.mif │ ├── crc32 │ └── axi_ram.mif │ ├── dhrystone │ └── axi_ram.mif │ ├── quick_sort │ └── axi_ram.mif │ ├── select_sort │ └── axi_ram.mif │ ├── sha │ └── axi_ram.mif │ ├── stream_copy │ └── axi_ram.mif │ └── stringsearch │ └── axi_ram.mif ├── report ├── NSCSCC 2019 Final Report.pdf ├── acknowledgement.tex ├── auto_test.tex ├── bootloader.tex ├── code.tex ├── cpu.tex ├── figures │ ├── colorful-new.png │ ├── cpu-Interface.pdf │ ├── cpu-design.pdf │ ├── dcache.pdf │ ├── decaf.pdf │ ├── emit-prediction.png │ └── soc-structure.pdf ├── introduction.tex ├── main.tex ├── os_software.tex └── soc.tex ├── scripts ├── build_soc.tcl ├── check_simulation.sh ├── generate_all_ips.tcl ├── generate_bitstream.tcl ├── generate_perf_matrix.sh ├── matrix │ ├── config │ │ ├── 0 │ │ ├── 1 │ │ ├── 2 │ │ ├── 3 │ │ ├── 4 │ │ └── 5 │ └── result │ │ └── .gitkeep ├── run_perf_simulations.tcl └── run_simulation.tcl ├── src ├── asic │ └── asic.sv ├── cache │ ├── cache_controller.sv │ ├── dcache.sv │ ├── dcache_fifo.sv │ ├── dcache_pass.sv │ ├── icache.sv │ └── plru.sv ├── common_defs.svh ├── compile_options.svh ├── cpu │ ├── .gitignore │ ├── cp0 │ │ ├── cp0.sv │ │ └── cp0_write_mask.sv │ ├── cpu_core.sv │ ├── cpu_defs.svh │ ├── ctrl.sv │ ├── decode │ │ ├── decode_and_issue.sv │ │ ├── decode_branch.sv │ │ ├── decoder.sv │ │ ├── fpu_register_forward.sv │ │ ├── instr_issue.sv │ │ └── register_forward.sv │ ├── except.sv │ ├── exec │ │ ├── branch_resolver.sv │ │ ├── count_bit.sv │ │ ├── cp0_forward.sv │ │ ├── delayed_exec.sv │ │ ├── delayed_register_forward.sv │ │ ├── div_uu.v │ │ ├── float2int.sv │ │ ├── fpu_exec.sv │ │ ├── hilo_forward.sv │ │ ├── instr_exec.sv │ │ ├── multi_cycle_exec.sv │ │ └── resolve_delayslot.sv │ ├── fetch │ │ ├── bht.sv │ │ ├── branch_predictor.sv │ │ ├── btb.sv │ │ ├── instr_fetch.sv │ │ ├── multi_queue.sv │ │ ├── pc_generator.sv │ │ └── ras.sv │ ├── ip │ │ ├── floating_point_addsub │ │ │ └── floating_point_addsub.xci │ │ ├── floating_point_compare │ │ │ └── floating_point_compare.xci │ │ ├── floating_point_divide │ │ │ └── floating_point_divide.xci │ │ ├── floating_point_int2float │ │ │ └── floating_point_int2float.xci │ │ ├── floating_point_multiply │ │ │ └── floating_point_multiply.xci │ │ └── floating_point_sqrt │ │ │ └── floating_point_sqrt.xci │ ├── mem │ │ ├── dbus_mux.sv │ │ └── instr_mem.sv │ ├── mmu │ │ ├── mmu.sv │ │ ├── tlb.sv │ │ └── tlb_lookup.sv │ └── regs │ │ ├── hilo.sv │ │ ├── ll_bit.sv │ │ └── regfile.sv ├── nontrivial_mips.v ├── nontrivial_mips_impl.sv ├── soc_top.sv └── utils │ ├── dual_port_ram.sv │ ├── fifo_v3.sv │ ├── iobuf_helper.svh │ ├── lfsr.sv │ ├── reset_synchronizer.v │ └── single_port_ram.sv ├── testbench ├── cache │ ├── axi │ │ ├── axi_mem.v │ │ ├── identity_device.sv │ │ └── mem_device.sv │ ├── cases │ │ ├── gen │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── from_raw.cpp │ │ │ ├── random.cpp │ │ │ └── sequential.cpp │ │ ├── invalidate.data │ │ ├── mem_bitcount.data │ │ ├── mem_bubble_sort.data │ │ ├── mem_dc_coremark.data │ │ ├── mem_quick_sort.data │ │ ├── mem_select_sort.data │ │ ├── mem_stream_copy.data │ │ ├── mem_string_search.data │ │ ├── random.2.data │ │ ├── random.be.data │ │ ├── random.data │ │ ├── raw │ │ │ ├── mem_bitcount.txt │ │ │ ├── mem_bubble_sort.txt │ │ │ ├── mem_dc_coremark.txt │ │ │ ├── mem_quick_sort.txt │ │ │ ├── mem_select_sort.txt │ │ │ ├── mem_stream_copy.txt │ │ │ └── mem_string_search.txt │ │ ├── sequential.data │ │ └── simple.data │ ├── dcache_tb.sv │ └── icache_tb.sv └── cpu │ ├── cpu_clock.sv │ ├── instr_fetch │ ├── test_instr_fetch.sv │ └── testcases │ │ ├── Makefile │ │ ├── build.sh │ │ ├── generate_controlflow.py │ │ ├── jump.ans │ │ ├── jump.mem │ │ ├── jump.s │ │ ├── jump_reg.ans │ │ ├── jump_reg.mem │ │ └── jump_reg.s │ ├── mem │ ├── fake_dbus.sv │ └── fake_ibus.sv │ ├── multi_queue_tb.sv │ ├── test_cpu.sv │ └── testcases │ ├── Makefile │ ├── across_tlb │ ├── 1.ans │ ├── 1.mem │ ├── 1.s │ ├── 2.ans │ ├── 2.mem │ ├── 2.s │ ├── 3.ans │ ├── 3.mem │ ├── 3.s │ ├── 4.ans │ ├── 4.mem │ ├── 4.s │ ├── 5.ans │ ├── 5.mem │ ├── 5.s │ ├── 6.ans │ ├── 6.mem │ └── 6.s │ ├── branch │ ├── 1.ans │ ├── 1.mem │ ├── 1.s │ ├── 2.ans │ ├── 2.mem │ ├── 2.s │ ├── 3.ans │ ├── 3.mem │ ├── 3.s │ ├── 4.ans │ ├── 4.mem │ ├── 4.s │ ├── 5.ans │ ├── 5.mem │ ├── 5.s │ ├── 6.ans │ ├── 6.mem │ ├── 6.s │ ├── 7.ans │ ├── 7.mem │ └── 7.s │ ├── build.sh │ ├── delayed-exec │ ├── 1.ans │ ├── 1.mem │ ├── 1.s │ ├── 2.ans │ ├── 2.mem │ └── 2.s │ ├── except │ ├── delayslot.ans │ ├── delayslot.mem │ ├── delayslot.s │ ├── except.ans │ ├── except.mem │ ├── except.s │ ├── interrupt.ans │ ├── interrupt.mem │ ├── interrupt.s │ ├── timer.ans │ ├── timer.mem │ └── timer.s │ ├── extract_ans.awk │ ├── fpu │ ├── fpu_arith.ans │ ├── fpu_arith.mem │ ├── fpu_arith.s │ ├── fpu_arith2.ans │ ├── fpu_arith2.mem │ ├── fpu_arith2.s │ ├── fpu_compare.ans │ ├── fpu_compare.mem │ ├── fpu_compare.s │ ├── fpu_test1.ans │ ├── fpu_test1.mem │ ├── fpu_test1.s │ ├── fpu_test2.ans │ ├── fpu_test2.mem │ ├── fpu_test2.s │ ├── fpu_test3.ans │ ├── fpu_test3.mem │ ├── fpu_test3.s │ ├── fpu_transfer.ans │ ├── fpu_transfer.mem │ └── fpu_transfer.s │ ├── genans.sh │ ├── hazard │ ├── delayed_div.ans │ ├── delayed_div.mem │ ├── delayed_div.s │ ├── indirect_mem.ans │ ├── indirect_mem.mem │ ├── indirect_mem.s │ ├── mfc.ans │ ├── mfc.mem │ ├── mfc.s │ ├── mfc_ds.ans │ ├── mfc_ds.mem │ ├── mfc_ds.s │ ├── tlbwi.ans │ ├── tlbwi.mem │ ├── tlbwi.s │ ├── tlbwi_ds.ans │ ├── tlbwi_ds.mem │ └── tlbwi_ds.s │ ├── instr │ ├── arith.ans │ ├── arith.mem │ ├── arith.s │ ├── jump.ans │ ├── jump.mem │ ├── jump.s │ ├── llsc.ans │ ├── llsc.mem │ ├── llsc.s │ ├── logical.ans │ ├── logical.mem │ ├── logical.s │ ├── mem_aligned.ans │ ├── mem_aligned.mem │ ├── mem_aligned.s │ ├── mem_unaligned.ans │ ├── mem_unaligned.mem │ ├── mem_unaligned.s │ ├── move.ans │ ├── move.mem │ ├── move.s │ ├── multicyc.ans │ ├── multicyc.mem │ ├── multicyc.s │ ├── ori.ans │ ├── ori.mem │ ├── ori.s │ ├── shift.ans │ ├── shift.mem │ ├── shift.s │ ├── trap.ans │ ├── trap.mem │ └── trap.s │ ├── performance │ ├── call_btb.ans │ ├── call_btb.genans.py │ ├── call_btb.mem │ ├── call_btb.s │ ├── call_btb_conflict.ans │ ├── call_btb_conflict.genans.py │ ├── call_btb_conflict.mem │ ├── call_btb_conflict.s │ ├── call_ras.ans │ ├── call_ras.genans.py │ ├── call_ras.mem │ ├── call_ras.s │ ├── call_ras_unaligned.ans │ ├── call_ras_unaligned.genans.py │ ├── call_ras_unaligned.mem │ ├── call_ras_unaligned.s │ ├── loop.ans │ ├── loop.genans.py │ ├── loop.mem │ └── loop.s │ └── sys │ ├── random.ans │ ├── random.mem │ ├── random.s │ ├── usermode.ans │ ├── usermode.mem │ ├── usermode.s │ ├── wired.ans │ ├── wired.mem │ └── wired.s └── vivado ├── .gitignore ├── NonTrivialMIPS.srcs ├── constrs_1 │ └── new │ │ ├── fpga_pins.xdc │ │ └── io_timings.xdc └── sources_1 │ ├── bd │ ├── .gitignore │ ├── bd_soc │ │ ├── .gitignore │ │ ├── bd_soc.bd │ │ ├── bd_soc.bxml │ │ ├── ip │ │ │ ├── .gitignore │ │ │ ├── bd_soc_altera_ps2_0_0 │ │ │ │ ├── bd_soc_altera_ps2_0_0.xci │ │ │ │ ├── bd_soc_altera_ps2_0_0.xml │ │ │ │ └── src │ │ │ │ │ └── fifo_ps2_recv │ │ │ │ │ ├── fifo_ps2_recv.xci │ │ │ │ │ └── fifo_ps2_recv.xml │ │ │ ├── bd_soc_apb_peripheral_bridge_0 │ │ │ │ ├── bd_soc_apb_peripheral_bridge_0.xci │ │ │ │ └── bd_soc_apb_peripheral_bridge_0.xml │ │ │ ├── bd_soc_auto_cc_0 │ │ │ │ ├── bd_soc_auto_cc_0.xci │ │ │ │ └── bd_soc_auto_cc_0.xml │ │ │ ├── bd_soc_auto_cc_1 │ │ │ │ ├── bd_soc_auto_cc_1.xci │ │ │ │ └── bd_soc_auto_cc_1.xml │ │ │ ├── bd_soc_auto_ds_0 │ │ │ │ ├── bd_soc_auto_ds_0.xci │ │ │ │ └── bd_soc_auto_ds_0.xml │ │ │ ├── bd_soc_auto_ds_1 │ │ │ │ ├── bd_soc_auto_ds_1.xci │ │ │ │ └── bd_soc_auto_ds_1.xml │ │ │ ├── bd_soc_auto_ds_10 │ │ │ │ ├── bd_soc_auto_ds_10.xci │ │ │ │ └── bd_soc_auto_ds_10.xml │ │ │ ├── bd_soc_auto_ds_11 │ │ │ │ ├── bd_soc_auto_ds_11.xci │ │ │ │ └── bd_soc_auto_ds_11.xml │ │ │ ├── bd_soc_auto_ds_12 │ │ │ │ ├── bd_soc_auto_ds_12.xci │ │ │ │ └── bd_soc_auto_ds_12.xml │ │ │ ├── bd_soc_auto_ds_13 │ │ │ │ ├── bd_soc_auto_ds_13.xci │ │ │ │ └── bd_soc_auto_ds_13.xml │ │ │ ├── bd_soc_auto_ds_2 │ │ │ │ ├── bd_soc_auto_ds_2.xci │ │ │ │ └── bd_soc_auto_ds_2.xml │ │ │ ├── bd_soc_auto_ds_3 │ │ │ │ ├── bd_soc_auto_ds_3.xci │ │ │ │ └── bd_soc_auto_ds_3.xml │ │ │ ├── bd_soc_auto_ds_4 │ │ │ │ ├── bd_soc_auto_ds_4.xci │ │ │ │ └── bd_soc_auto_ds_4.xml │ │ │ ├── bd_soc_auto_ds_5 │ │ │ │ ├── bd_soc_auto_ds_5.xci │ │ │ │ └── bd_soc_auto_ds_5.xml │ │ │ ├── bd_soc_auto_ds_6 │ │ │ │ ├── bd_soc_auto_ds_6.xci │ │ │ │ └── bd_soc_auto_ds_6.xml │ │ │ ├── bd_soc_auto_ds_7 │ │ │ │ ├── bd_soc_auto_ds_7.xci │ │ │ │ └── bd_soc_auto_ds_7.xml │ │ │ ├── bd_soc_auto_ds_8 │ │ │ │ ├── bd_soc_auto_ds_8.xci │ │ │ │ └── bd_soc_auto_ds_8.xml │ │ │ ├── bd_soc_auto_ds_9 │ │ │ │ ├── bd_soc_auto_ds_9.xci │ │ │ │ └── bd_soc_auto_ds_9.xml │ │ │ ├── bd_soc_auto_pc_0 │ │ │ │ ├── bd_soc_auto_pc_0.xci │ │ │ │ └── bd_soc_auto_pc_0.xml │ │ │ ├── bd_soc_auto_pc_1 │ │ │ │ ├── bd_soc_auto_pc_1.xci │ │ │ │ └── bd_soc_auto_pc_1.xml │ │ │ ├── bd_soc_auto_pc_10 │ │ │ │ ├── bd_soc_auto_pc_10.xci │ │ │ │ └── bd_soc_auto_pc_10.xml │ │ │ ├── bd_soc_auto_pc_11 │ │ │ │ ├── bd_soc_auto_pc_11.xci │ │ │ │ └── bd_soc_auto_pc_11.xml │ │ │ ├── bd_soc_auto_pc_2 │ │ │ │ ├── bd_soc_auto_pc_2.xci │ │ │ │ └── bd_soc_auto_pc_2.xml │ │ │ ├── bd_soc_auto_pc_3 │ │ │ │ ├── bd_soc_auto_pc_3.xci │ │ │ │ └── bd_soc_auto_pc_3.xml │ │ │ ├── bd_soc_auto_pc_4 │ │ │ │ ├── bd_soc_auto_pc_4.xci │ │ │ │ └── bd_soc_auto_pc_4.xml │ │ │ ├── bd_soc_auto_pc_5 │ │ │ │ ├── bd_soc_auto_pc_5.xci │ │ │ │ └── bd_soc_auto_pc_5.xml │ │ │ ├── bd_soc_auto_pc_6 │ │ │ │ ├── bd_soc_auto_pc_6.xci │ │ │ │ └── bd_soc_auto_pc_6.xml │ │ │ ├── bd_soc_auto_pc_7 │ │ │ │ ├── bd_soc_auto_pc_7.xci │ │ │ │ └── bd_soc_auto_pc_7.xml │ │ │ ├── bd_soc_auto_pc_8 │ │ │ │ ├── bd_soc_auto_pc_8.xci │ │ │ │ └── bd_soc_auto_pc_8.xml │ │ │ ├── bd_soc_auto_pc_9 │ │ │ │ ├── bd_soc_auto_pc_9.xci │ │ │ │ └── bd_soc_auto_pc_9.xml │ │ │ ├── bd_soc_auto_us_cc_df_0 │ │ │ │ ├── bd_soc_auto_us_cc_df_0.xci │ │ │ │ └── bd_soc_auto_us_cc_df_0.xml │ │ │ ├── bd_soc_auto_us_cc_df_1 │ │ │ │ ├── bd_soc_auto_us_cc_df_1.xci │ │ │ │ └── bd_soc_auto_us_cc_df_1.xml │ │ │ ├── bd_soc_auto_us_cc_df_2 │ │ │ │ ├── bd_soc_auto_us_cc_df_2.xci │ │ │ │ └── bd_soc_auto_us_cc_df_2.xml │ │ │ ├── bd_soc_auto_us_df_0 │ │ │ │ ├── bd_soc_auto_us_df_0.xci │ │ │ │ └── bd_soc_auto_us_df_0.xml │ │ │ ├── bd_soc_axi_apb_bridge_0_0 │ │ │ │ ├── bd_soc_axi_apb_bridge_0_0.xci │ │ │ │ └── bd_soc_axi_apb_bridge_0_0.xml │ │ │ ├── bd_soc_axi_bram_ctrl_0_0 │ │ │ │ ├── bd_soc_axi_bram_ctrl_0_0.xci │ │ │ │ └── bd_soc_axi_bram_ctrl_0_0.xml │ │ │ ├── bd_soc_axi_bram_ctrl_0_1 │ │ │ │ ├── bd_soc_axi_bram_ctrl_0_1.xci │ │ │ │ └── bd_soc_axi_bram_ctrl_0_1.xml │ │ │ ├── bd_soc_axi_ethernetlite_0_0 │ │ │ │ ├── bd_soc_axi_ethernetlite_0_0.xci │ │ │ │ └── bd_soc_axi_ethernetlite_0_0.xml │ │ │ ├── bd_soc_axi_intc_0_0 │ │ │ │ ├── bd_soc_axi_intc_0_0.xci │ │ │ │ └── bd_soc_axi_intc_0_0.xml │ │ │ ├── bd_soc_axi_interconnect_0_0 │ │ │ │ ├── bd_soc_axi_interconnect_0_0.xci │ │ │ │ └── bd_soc_axi_interconnect_0_0.xml │ │ │ ├── bd_soc_axi_interconnect_0_1 │ │ │ │ ├── bd_soc_axi_interconnect_0_1.xci │ │ │ │ └── bd_soc_axi_interconnect_0_1.xml │ │ │ ├── bd_soc_axi_interconnect_0_2 │ │ │ │ ├── bd_soc_axi_interconnect_0_2.xci │ │ │ │ └── bd_soc_axi_interconnect_0_2.xml │ │ │ ├── bd_soc_axi_quad_spi_0_0 │ │ │ │ ├── bd_soc_axi_quad_spi_0_0.xci │ │ │ │ └── bd_soc_axi_quad_spi_0_0.xml │ │ │ ├── bd_soc_axi_quad_spi_0_1 │ │ │ │ ├── bd_soc_axi_quad_spi_0_1.xci │ │ │ │ └── bd_soc_axi_quad_spi_0_1.xml │ │ │ ├── bd_soc_axi_tft_0_0 │ │ │ │ ├── bd_soc_axi_tft_0_0.xci │ │ │ │ └── bd_soc_axi_tft_0_0.xml │ │ │ ├── bd_soc_axi_uart16550_0_0 │ │ │ │ ├── bd_soc_axi_uart16550_0_0.xci │ │ │ │ └── bd_soc_axi_uart16550_0_0.xml │ │ │ ├── bd_soc_blk_mem_gen_0_0 │ │ │ │ ├── bd_soc_blk_mem_gen_0_0.xci │ │ │ │ └── bd_soc_blk_mem_gen_0_0.xml │ │ │ ├── bd_soc_blk_mem_gen_0_1 │ │ │ │ ├── bd_soc_blk_mem_gen_0_1.xci │ │ │ │ └── bd_soc_blk_mem_gen_0_1.xml │ │ │ ├── bd_soc_bootrom_controller_0 │ │ │ │ ├── bd_soc_bootrom_controller_0.xci │ │ │ │ └── bd_soc_bootrom_controller_0.xml │ │ │ ├── bd_soc_bootrom_impl_0 │ │ │ │ ├── bd_soc_bootrom_impl_0.xci │ │ │ │ └── bd_soc_bootrom_impl_0.xml │ │ │ ├── bd_soc_cfg_flash_controller_0 │ │ │ │ ├── bd_soc_cfg_flash_controller_0.xci │ │ │ │ └── bd_soc_cfg_flash_controller_0.xml │ │ │ ├── bd_soc_clk_wiz_0_0 │ │ │ │ ├── bd_soc_clk_wiz_0_0.xci │ │ │ │ └── bd_soc_clk_wiz_0_0.xml │ │ │ ├── bd_soc_confreg_0_0 │ │ │ │ ├── bd_soc_confreg_0_0.xci │ │ │ │ └── bd_soc_confreg_0_0.xml │ │ │ ├── bd_soc_constant_true_0 │ │ │ │ ├── bd_soc_constant_true_0.xci │ │ │ │ └── bd_soc_constant_true_0.xml │ │ │ ├── bd_soc_ddr_controller_0 │ │ │ │ ├── bd_soc_ddr_controller_0.xci │ │ │ │ └── bd_soc_ddr_controller_0.xml │ │ │ ├── bd_soc_ddr_reset_synchronizer_0 │ │ │ │ ├── bd_soc_ddr_reset_synchronizer_0.xci │ │ │ │ └── bd_soc_ddr_reset_synchronizer_0.xml │ │ │ ├── bd_soc_ethernet_controller_0 │ │ │ │ ├── bd_soc_ethernet_controller_0.xci │ │ │ │ └── bd_soc_ethernet_controller_0.xml │ │ │ ├── bd_soc_external_interrupt_controller_0 │ │ │ │ ├── bd_soc_external_interrupt_controller_0.xci │ │ │ │ └── bd_soc_external_interrupt_controller_0.xml │ │ │ ├── bd_soc_frame_buffer_modifier_0 │ │ │ │ ├── bd_soc_frame_buffer_modifier_0.xci │ │ │ │ └── bd_soc_frame_buffer_modifier_0.xml │ │ │ ├── bd_soc_framebuffer_ila_0 │ │ │ │ ├── bd_0 │ │ │ │ │ ├── bd_e135.bd │ │ │ │ │ └── bd_e135.bxml │ │ │ │ ├── bd_soc_framebuffer_ila_0.xci │ │ │ │ └── bd_soc_framebuffer_ila_0.xml │ │ │ ├── bd_soc_framebuffer_reader_0 │ │ │ │ ├── bd_soc_framebuffer_reader_0.xci │ │ │ │ └── bd_soc_framebuffer_reader_0.xml │ │ │ ├── bd_soc_framebuffer_writer_0 │ │ │ │ ├── bd_soc_framebuffer_writer_0.xci │ │ │ │ └── bd_soc_framebuffer_writer_0.xml │ │ │ ├── bd_soc_interrupt_concat_0 │ │ │ │ ├── bd_soc_interrupt_concat_0.xci │ │ │ │ └── bd_soc_interrupt_concat_0.xml │ │ │ ├── bd_soc_jtag_axi_0_0 │ │ │ │ ├── bd_soc_jtag_axi_0_0.xci │ │ │ │ └── bd_soc_jtag_axi_0_0.xml │ │ │ ├── bd_soc_jtag_sys_0 │ │ │ │ ├── bd_soc_jtag_sys_0.xci │ │ │ │ └── bd_soc_jtag_sys_0.xml │ │ │ ├── bd_soc_lcd_controller_0 │ │ │ │ ├── bd_soc_lcd_controller_0.xci │ │ │ │ └── bd_soc_lcd_controller_0.xml │ │ │ ├── bd_soc_loongson_confrreg_0 │ │ │ │ ├── bd_soc_loongson_confrreg_0.xci │ │ │ │ └── bd_soc_loongson_confrreg_0.xml │ │ │ ├── bd_soc_main_mmcm_0 │ │ │ │ ├── bd_soc_main_mmcm_0.xci │ │ │ │ └── bd_soc_main_mmcm_0.xml │ │ │ ├── bd_soc_memory_bus_0 │ │ │ │ ├── bd_soc_memory_bus_0.xci │ │ │ │ └── bd_soc_memory_bus_0.xml │ │ │ ├── bd_soc_mig_7series_0_1 │ │ │ │ ├── bd_soc_mig_7series_0_1.xci │ │ │ │ ├── bd_soc_mig_7series_0_1.xml │ │ │ │ ├── bd_soc_mig_7series_0_1 │ │ │ │ │ ├── example_design │ │ │ │ │ │ └── sim │ │ │ │ │ │ │ └── xsim_files.prj │ │ │ │ │ └── mig.prj │ │ │ │ └── mig_a.prj │ │ │ ├── bd_soc_nontrivial_mips_0_0 │ │ │ │ ├── bd_soc_nontrivial_mips_0_0.xci │ │ │ │ └── bd_soc_nontrivial_mips_0_0.xml │ │ │ ├── bd_soc_nt35510_controller_0_0 │ │ │ │ ├── bd_soc_nt35510_controller_0_0.xci │ │ │ │ └── bd_soc_nt35510_controller_0_0.xml │ │ │ ├── bd_soc_ocm_controller_0 │ │ │ │ ├── bd_soc_ocm_controller_0.xci │ │ │ │ └── bd_soc_ocm_controller_0.xml │ │ │ ├── bd_soc_ocm_impl_0 │ │ │ │ ├── bd_soc_ocm_impl_0.xci │ │ │ │ └── bd_soc_ocm_impl_0.xml │ │ │ ├── bd_soc_proc_sys_reset_0_0 │ │ │ │ ├── bd_soc_proc_sys_reset_0_0.xci │ │ │ │ └── bd_soc_proc_sys_reset_0_0.xml │ │ │ ├── bd_soc_ps2_contoller_0 │ │ │ │ ├── bd_soc_ps2_contoller_0.xci │ │ │ │ └── bd_soc_ps2_contoller_0.xml │ │ │ ├── bd_soc_reset_negate_0 │ │ │ │ ├── bd_soc_reset_negate_0.xci │ │ │ │ └── bd_soc_reset_negate_0.xml │ │ │ ├── bd_soc_reset_synchronizer_0_0 │ │ │ │ ├── bd_soc_reset_synchronizer_0_0.xci │ │ │ │ └── bd_soc_reset_synchronizer_0_0.xml │ │ │ ├── bd_soc_reset_synchronizer_0_1 │ │ │ │ ├── bd_soc_reset_synchronizer_0_1.xci │ │ │ │ └── bd_soc_reset_synchronizer_0_1.xml │ │ │ ├── bd_soc_s00_data_fifo_0 │ │ │ │ ├── bd_soc_s00_data_fifo_0.xci │ │ │ │ └── bd_soc_s00_data_fifo_0.xml │ │ │ ├── bd_soc_s00_data_fifo_1 │ │ │ │ ├── bd_soc_s00_data_fifo_1.xci │ │ │ │ └── bd_soc_s00_data_fifo_1.xml │ │ │ ├── bd_soc_s01_data_fifo_0 │ │ │ │ ├── bd_soc_s01_data_fifo_0.xci │ │ │ │ └── bd_soc_s01_data_fifo_0.xml │ │ │ ├── bd_soc_s02_data_fifo_0 │ │ │ │ ├── bd_soc_s02_data_fifo_0.xci │ │ │ │ └── bd_soc_s02_data_fifo_0.xml │ │ │ ├── bd_soc_s03_data_fifo_0 │ │ │ │ ├── bd_soc_s03_data_fifo_0.xci │ │ │ │ └── bd_soc_s03_data_fifo_0.xml │ │ │ ├── bd_soc_spi_flash_controller_0 │ │ │ │ ├── bd_soc_spi_flash_controller_0.xci │ │ │ │ └── bd_soc_spi_flash_controller_0.xml │ │ │ ├── bd_soc_sys_reset_controller_0 │ │ │ │ ├── bd_soc_sys_reset_controller_0.xci │ │ │ │ └── bd_soc_sys_reset_controller_0.xml │ │ │ ├── bd_soc_system_ila_0_0 │ │ │ │ ├── bd_0 │ │ │ │ │ ├── bd_3fde.bd │ │ │ │ │ └── ip │ │ │ │ │ │ ├── ip_0 │ │ │ │ │ │ ├── bd_3fde_ila_lib_0.xci │ │ │ │ │ │ └── bd_3fde_ila_lib_0.xml │ │ │ │ │ │ ├── ip_1 │ │ │ │ │ │ ├── bd_3fde_g_inst_0.xci │ │ │ │ │ │ └── bd_3fde_g_inst_0.xml │ │ │ │ │ │ ├── ip_2 │ │ │ │ │ │ ├── bd_3fde_slot_0_aw_0.xci │ │ │ │ │ │ └── bd_3fde_slot_0_aw_0.xml │ │ │ │ │ │ ├── ip_3 │ │ │ │ │ │ ├── bd_3fde_slot_0_w_0.xci │ │ │ │ │ │ └── bd_3fde_slot_0_w_0.xml │ │ │ │ │ │ ├── ip_4 │ │ │ │ │ │ ├── bd_3fde_slot_0_b_0.xci │ │ │ │ │ │ └── bd_3fde_slot_0_b_0.xml │ │ │ │ │ │ ├── ip_5 │ │ │ │ │ │ ├── bd_3fde_slot_0_ar_0.xci │ │ │ │ │ │ └── bd_3fde_slot_0_ar_0.xml │ │ │ │ │ │ └── ip_6 │ │ │ │ │ │ ├── bd_3fde_slot_0_r_0.xci │ │ │ │ │ │ └── bd_3fde_slot_0_r_0.xml │ │ │ │ ├── bd_soc_system_ila_0_0.xci │ │ │ │ └── bd_soc_system_ila_0_0.xml │ │ │ ├── bd_soc_uart_controller_0 │ │ │ │ ├── bd_soc_uart_controller_0.xci │ │ │ │ └── bd_soc_uart_controller_0.xml │ │ │ ├── bd_soc_usb_controller_0 │ │ │ │ ├── bd_soc_usb_controller_0.xci │ │ │ │ └── bd_soc_usb_controller_0.xml │ │ │ ├── bd_soc_usb_reset_synchronizer_0 │ │ │ │ ├── bd_soc_usb_reset_synchronizer_0.xci │ │ │ │ └── bd_soc_usb_reset_synchronizer_0.xml │ │ │ ├── bd_soc_util_vector_logic_0_1 │ │ │ │ ├── bd_soc_util_vector_logic_0_1.xci │ │ │ │ └── bd_soc_util_vector_logic_0_1.xml │ │ │ ├── bd_soc_utmi_usb_controller_0_1 │ │ │ │ ├── bd_soc_utmi_usb_controller_0_1.xci │ │ │ │ └── bd_soc_utmi_usb_controller_0_1.xml │ │ │ ├── bd_soc_v_frmbuf_rd_0_0 │ │ │ │ ├── bd_soc_v_frmbuf_rd_0_0.xci │ │ │ │ └── bd_soc_v_frmbuf_rd_0_0.xml │ │ │ ├── bd_soc_v_frmbuf_wr_0_0 │ │ │ │ ├── bd_soc_v_frmbuf_wr_0_0.xci │ │ │ │ └── bd_soc_v_frmbuf_wr_0_0.xml │ │ │ ├── bd_soc_vga_controller_0 │ │ │ │ ├── bd_soc_vga_controller_0.xci │ │ │ │ └── bd_soc_vga_controller_0.xml │ │ │ ├── bd_soc_video_stream_modifier_0_0 │ │ │ │ ├── bd_soc_video_stream_modifier_0_0.xci │ │ │ │ └── bd_soc_video_stream_modifier_0_0.xml │ │ │ ├── bd_soc_vio_0_0 │ │ │ │ ├── bd_soc_vio_0_0.xci │ │ │ │ └── bd_soc_vio_0_0.xml │ │ │ ├── bd_soc_vio_reset_0 │ │ │ │ ├── bd_soc_vio_reset_0.xci │ │ │ │ └── bd_soc_vio_reset_0.xml │ │ │ ├── bd_soc_xbar_0 │ │ │ │ ├── bd_soc_xbar_0.xci │ │ │ │ └── bd_soc_xbar_0.xml │ │ │ ├── bd_soc_xbar_1 │ │ │ │ ├── bd_soc_xbar_1.xci │ │ │ │ └── bd_soc_xbar_1.xml │ │ │ ├── bd_soc_xbar_2 │ │ │ │ ├── bd_soc_xbar_2.xci │ │ │ │ └── bd_soc_xbar_2.xml │ │ │ ├── bd_soc_xlconcat_0_0 │ │ │ │ ├── bd_soc_xlconcat_0_0.xci │ │ │ │ └── bd_soc_xlconcat_0_0.xml │ │ │ ├── bd_soc_xlconcat_0_1 │ │ │ │ ├── bd_soc_xlconcat_0_1.xci │ │ │ │ └── bd_soc_xlconcat_0_1.xml │ │ │ ├── bd_soc_xlconstant_0_0 │ │ │ │ ├── bd_soc_xlconstant_0_0.xci │ │ │ │ └── bd_soc_xlconstant_0_0.xml │ │ │ └── bd_soc_xlconstant_0_1 │ │ │ │ ├── bd_soc_xlconstant_0_1.xci │ │ │ │ └── bd_soc_xlconstant_0_1.xml │ │ └── ui │ │ │ └── bd_309586ca.ui │ └── mref │ │ └── reset_synchronizer │ │ ├── component.xml │ │ └── xgui │ │ └── reset_synchronizer_v1_0.tcl │ └── bootrom.coe ├── NonTrivialMIPS.xpr └── ip_repo ├── altera_ps2 ├── component.xml ├── src │ ├── altera_up_ps2.v │ ├── altera_up_ps2_command_out.v │ ├── altera_up_ps2_data_in.v │ ├── fifo_ps2_recv │ │ ├── fifo_ps2_recv.xci │ │ └── fifo_ps2_recv.xml │ ├── ps2_tb.sv │ ├── ps2_tb_behav.wcfg │ └── testPS2qsys_ps2_0.v └── xgui │ ├── altera_ps2_v1_0.tcl │ └── testPS2qsys_ps2_0_v1_0.tcl ├── loongson_conf_reg ├── component.xml ├── confreg.v └── xgui │ ├── confreg_v1_0.tcl │ └── confreg_v1_1.tcl ├── loongson_cpu_gs232 ├── component.xml ├── src │ ├── sram_128x22 │ │ └── sram_128x22.xci │ ├── sram_128x32 │ │ └── sram_128x32.xci │ ├── sram_128x64 │ │ └── sram_128x64.xci │ └── sram_32x52bit │ │ └── sram_32x52bit.xci └── xgui │ └── loongson_cpu_gs232_v1_0.tcl ├── nontrivial_mips ├── component.xml ├── src │ ├── floating_point_addsub │ │ └── floating_point_addsub.xci │ ├── floating_point_compare │ │ └── floating_point_compare.xci │ ├── floating_point_divide │ │ └── floating_point_divide.xci │ ├── floating_point_int2float │ │ └── floating_point_int2float.xci │ ├── floating_point_multiply │ │ └── floating_point_multiply.xci │ └── floating_point_sqrt │ │ └── floating_point_sqrt.xci └── xgui │ └── nontrivial_mips_v1_0.tcl ├── nt35510_controller ├── component.xml ├── src │ └── nt35510_apb_adapter_v1_0.v └── xgui │ ├── nt35510_apb_adapter_v1_0_v1_0.tcl │ └── nt35510_controller_v1_0.tcl ├── usb_host_controller ├── component.xml ├── usbh_crc16.v ├── usbh_crc5.v ├── usbh_fifo.v ├── usbh_host.v ├── usbh_host_defs.v ├── usbh_sie.v ├── usbh_top.v └── xgui │ ├── usbh_top_v1_0.tcl │ └── utmi_usb_controller_v1_0.tcl ├── utmi.xml ├── utmi_rtl.xml ├── video_stream_modifier ├── component.xml ├── stream_ctl.v └── xgui │ ├── stream_ctl_v1_0.tcl │ └── video_stream_modifier_v1_0.tcl └── vv_index.xml /.gitattributes: -------------------------------------------------------------------------------- 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