├── README.textile ├── bench └── verilog │ ├── i2c_slave_model.v │ ├── spi_slave_model.v │ ├── tst_bench_top.v │ └── wb_master_model.v ├── doc ├── i2c_specs.pdf └── src │ └── I2C_specs.doc ├── rtl ├── verilog │ ├── i2c_master_bit_ctrl.v │ ├── i2c_master_byte_ctrl.v │ ├── i2c_master_defines.v │ ├── i2c_master_top.v │ └── timescale.v └── vhdl │ ├── I2C.VHD │ ├── i2c_master_avalon.vhd │ ├── i2c_master_avalon_hw.tcl │ ├── i2c_master_bit_ctrl.vhd │ ├── i2c_master_byte_ctrl.vhd │ ├── i2c_master_top.vhd │ ├── readme │ └── tst_ds1621.vhd ├── sim └── i2c_verilog │ └── run │ ├── bench.vcd │ ├── ncverilog.key │ ├── ncverilog.log │ └── run └── software └── include └── oc_i2c_master.h /README.textile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/trondd/oc-i2c/HEAD/README.textile -------------------------------------------------------------------------------- /bench/verilog/i2c_slave_model.v: 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