├── .gitignore ├── .nova └── Tasks │ └── PipelineC.json ├── LICENSE ├── README.md ├── roms ├── amiga.h ├── bounce.h ├── controller.h ├── cube3d.h ├── fill_test.h ├── mandelbrot_fast.h ├── screen_blending.h └── star.h ├── top_test.vhd ├── uxn.c ├── uxn_constants.h ├── uxn_device.h ├── uxn_opcodes.h ├── uxn_ram_device.h ├── uxn_ram_main.h ├── uxn_ram_screen.h └── uxn_stack.h /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | *.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | lextab.py 54 | yacctab.py 55 | *pipelinec_output_*/ 56 | work-obj08.cf 57 | out.txt 58 | -------------------------------------------------------------------------------- /.nova/Tasks/PipelineC.json: -------------------------------------------------------------------------------- 1 | { 2 | "actions" : { 3 | "build" : { 4 | "enabled" : true, 5 | "script" : "#!\/bin\/sh\nrm -rf pipelinec_output_uxn.c_1\nsleep 1\nrm lextab.py\nrm yacctab.py\nrm work-obj08.cf\nsleep 1\nopen -a docker && while ! docker info > \/dev\/null 2>&1; do sleep 1 ; done\ndocker run --rm -v $(pwd):\/workdir pipelinec uxn.c" 6 | }, 7 | "clean" : { 8 | "enabled" : true, 9 | "script" : "#!\/bin\/sh\nrm -rf pipelinec_output_uxn.c_1\nsleep 1\nrm lextab.py\nrm yacctab.py\nrm work-obj08.cf\nsleep 1" 10 | }, 11 | "run" : { 12 | "enabled" : true, 13 | "script" : "rm -rf pipelinec_output_uxn.c_1\nsleep 1\nrm lextab.py\nrm yacctab.py\nrm work-obj08.cf\nsleep 1\nopen -a docker && while ! docker info > \/dev\/null 2>&1; do sleep 1 ; done\ndocker run --rm -v $(pwd):\/workdir pipelinec uxn.c --sim --comb --ghdl\nsleep 1\nsed -i '' 's\/\\\/workdir\\\/\/\/g' .\/pipelinec_output_uxn.c_1\/vhdl_files.txt\nghdl -i --std=08 --work=work $(cat .\/pipelinec_output_uxn.c_1\/vhdl_files.txt) top_test.vhd\nghdl -m --std=08 --work=work top_test\nghdl -r --std=08 --work=work top_test --ieee-asserts=disable --stop-time=200ms" 14 | } 15 | }, 16 | "openLogOnRun" : "start" 17 | } 18 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Tom Salvo 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # uxn-fpga 2 | Very early work in progress implementation of [Varvara / UXN](https://100r.co/site/uxn.html) by [hundredrabbits](https://100r.co/site/home.html) in FPGA using [PipelineC](https://github.com/JulianKemmerer/PipelineC). Intended for importing into the [openfpga-varvara](https://github.com/tsalvo/openfpga-varvara) core for Analogue Pocket. 3 | 4 | ### Change test ROM (for GHDL simulation): 5 | Currently several ROMs are available as C arrays within `.h` files in the `roms/` directory: 6 | - `amiga.h` bouncing rotating ball 7 | - `bounce.h` uses screen vectors to move a bouncing ball once per frame 8 | - `controller.h` controller input test ROM 9 | - `cube3d.h` draws a 3D spinning cube (partially working) 10 | - `fill_test.h` draws a series of rectangles using the fill command 11 | - `mandelbrot_fast.h` (draws a mandelbrot set image, one pixel at a time) 12 | - `screen_blending.h` draws a series of sprites using different blending techniques 13 | - `star.h` draws 3 rotating stars, with UXN character sprites in the center 14 | 15 | To use a different ROM for GHDL simulation, just change the import statement in `uxn.c` to import the correct ROM, and set `DEBUG` = `1` in `uxn_constants.h`. 16 | 17 | ### build into VHDL files (for later importing into openfpga-uxn project for Analogue Pocket): 18 | ``` 19 | pipelinec uxn.c 20 | ``` 21 | 22 | ### build for GHDL simulation (requires additional plugins) 23 | ``` 24 | pipelinec uxn.c --sim --comb --ghdl 25 | ``` 26 | 27 | ### run GHDL simulation: 28 | ``` 29 | ghdl -i --std=08 --work=work [sequence of vhd files appended by top_test.vhd] 30 | ghdl -m --std=08 --work=work top_test 31 | ghdl -r --std=08 --work=work top_test --ieee-asserts=disable --stop-time=1ms 32 | ``` 33 | -------------------------------------------------------------------------------- /roms/amiga.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | //AMIGA DEMO 5 | 6 | #define ROM_SIZE 3380 7 | 8 | uint8_t read_rom_byte(uint16_t read_address) 9 | { 10 | static uint8_t uxn_rom[ROM_SIZE] = { 11 | 0x80, 0x01, 0x80, 0x0A, 12 | 0x11, 0xA0, 0x01, 0x48, 13 | 0x80, 0x20, 0x37, 0xA0, 14 | 0xAF, 0xF5, 0x80, 0x08, 15 | 0x37, 0xA0, 0xAF, 0x00, 16 | 0x80, 0x0A, 0x37, 0xA0, 17 | 0xAF, 0x05, 0x80, 0x0C, 18 | 0x37, 0xA0, 0x01, 0x40, 19 | 0x80, 0x22, 0x37, 0xA0, 20 | 0x01, 0x00, 0x80, 0x24, 21 | 0x37, 0xA0, 0x00, 0x20, 22 | 0x80, 0x00, 0x31, 0xA0, 23 | 0x00, 0x20, 0x80, 0x02, 24 | 0x31, 0xA0, 0x00, 0x03, 25 | 0x80, 0x04, 0x31, 0xA0, 26 | 0x00, 0x00, 0x80, 0x06, 27 | 0x31, 0x60, 0x01, 0xE7, 28 | 0x60, 0x01, 0x59, 0x00, 29 | 0x80, 0x09, 0x90, 0x80, 30 | 0x0A, 0x10, 0x18, 0x80, 31 | 0x0C, 0x9B, 0x1A, 0x19, 32 | 0x04, 0x11, 0x60, 0x00, 33 | 0x41, 0x00, 0xB0, 0xA0, 34 | 0xFF, 0xFF, 0x3E, 0x21, 35 | 0x05, 0x31, 0x6C, 0x26, 36 | 0xA0, 0x00, 0x10, 0x2B, 37 | 0x20, 0x00, 0x0D, 0x26, 38 | 0x80, 0x22, 0x36, 0xA0, 39 | 0x00, 0x50, 0x39, 0x2A, 40 | 0x20, 0x00, 0x01, 0x6C, 41 | 0x80, 0x0A, 0x90, 0x80, 42 | 0x0A, 0x1E, 0x04, 0x11, 43 | 0x80, 0x04, 0x40, 0xFF, 44 | 0xD5, 0x26, 0x80, 0x24, 45 | 0x36, 0xA0, 0x00, 0x50, 46 | 0x39, 0x2A, 0x20, 0x00, 47 | 0x03, 0x40, 0x00, 0x05, 48 | 0x80, 0x06, 0x40, 0xFF, 49 | 0xC1, 0x6C, 0x80, 0x00, 50 | 0x30, 0x80, 0x28, 0x37, 51 | 0x80, 0x02, 0x30, 0x80, 52 | 0x2A, 0x37, 0xA0, 0x03, 53 | 0x64, 0x80, 0x2C, 0x37, 54 | 0xA0, 0x71, 0x26, 0x17, 55 | 0x80, 0xF8, 0xA0, 0x40, 56 | 0x2F, 0x17, 0x01, 0x06, 57 | 0x20, 0xFF, 0xF7, 0x02, 58 | 0xA0, 0x76, 0x26, 0x17, 59 | 0x80, 0x04, 0xB0, 0xAF, 60 | 0x05, 0x31, 0x80, 0x00, 61 | 0xB0, 0x6F, 0x38, 0x60, 62 | 0xFF, 0x95, 0x05, 0x31, 63 | 0x80, 0x08, 0x90, 0x01, 64 | 0x06, 0x05, 0x11, 0x80, 65 | 0x06, 0x08, 0x20, 0x00, 66 | 0x03, 0x40, 0x00, 0x0F, 67 | 0x80, 0x00, 0x80, 0x08, 68 | 0x11, 0x80, 0x06, 0xB0, 69 | 0x21, 0xAF, 0x05, 0x31, 70 | 0x40, 0x00, 0x09, 0x80, 71 | 0x06, 0xB0, 0xAF, 0x05, 72 | 0x31, 0x40, 0x00, 0x00, 73 | 0x80, 0x02, 0xB0, 0x6F, 74 | 0x38, 0x60, 0xFF, 0x85, 75 | 0x05, 0x31, 0x80, 0x00, 76 | 0x30, 0xA0, 0x00, 0x08, 77 | 0x38, 0x80, 0x28, 0x37, 78 | 0x80, 0x02, 0x30, 0xA0, 79 | 0x00, 0x08, 0x38, 0x80, 80 | 0x2A, 0x37, 0xA0, 0x0E, 81 | 0x34, 0x80, 0x2C, 0x37, 82 | 0xA0, 0x66, 0x26, 0x17, 83 | 0x80, 0xF9, 0xA0, 0x4F, 84 | 0x2F, 0x17, 0x01, 0x06, 85 | 0x20, 0xFF, 0xF7, 0x02, 86 | 0x80, 0x09, 0x10, 0x06, 87 | 0x80, 0x06, 0x1B, 0x01, 88 | 0x80, 0x05, 0x1A, 0x80, 89 | 0x40, 0x18, 0x80, 0x19, 90 | 0x13, 0x80, 0x00, 0x30, 91 | 0x80, 0x28, 0x37, 0x80, 92 | 0x02, 0x30, 0x80, 0x2A, 93 | 0x37, 0xA0, 0x0C, 0xAC, 94 | 0x80, 0x2C, 0x37, 0xA0, 95 | 0x66, 0x26, 0x17, 0x80, 96 | 0xF9, 0xA0, 0x00, 0x2F, 97 | 0x17, 0x01, 0x06, 0x20, 98 | 0xFF, 0xF7, 0x02, 0x06, 99 | 0x80, 0x06, 0x1B, 0x80, 100 | 0x00, 0x08, 0x01, 0x80, 101 | 0x05, 0x1A, 0x80, 0x40, 102 | 0x18, 0x80, 0x26, 0x13, 103 | 0x80, 0x00, 0x30, 0x80, 104 | 0x28, 0x37, 0x80, 0x02, 105 | 0x30, 0x80, 0x2A, 0x37, 106 | 0x80, 0x06, 0x9B, 0x1A, 107 | 0x19, 0x80, 0x00, 0x04, 108 | 0xA0, 0x01, 0x88, 0x3A, 109 | 0xA0, 0x03, 0x7C, 0x38, 110 | 0x80, 0x2C, 0x37, 0xA0, 111 | 0x66, 0x26, 0x17, 0x80, 112 | 0xF9, 0xA0, 0x00, 0x2F, 113 | 0x17, 0x01, 0x06, 0x20, 114 | 0xFF, 0xF7, 0x02, 0x6C, 115 | 0xA0, 0x01, 0x26, 0x17, 116 | 0xA0, 0x03, 0x6C, 0x80, 117 | 0x2C, 0x37, 0x80, 0x24, 118 | 0x36, 0x80, 0x04, 0x3F, 119 | 0x03, 0x80, 0x04, 0x19, 120 | 0x80, 0x00, 0xA0, 0x00, 121 | 0x20, 0x80, 0x28, 0x37, 122 | 0x80, 0x00, 0x07, 0x80, 123 | 0x40, 0x3F, 0xA0, 0x00, 124 | 0x20, 0x38, 0x80, 0x2A, 125 | 0x37, 0x80, 0x22, 0x36, 126 | 0x80, 0x03, 0x3F, 0x03, 127 | 0x80, 0x08, 0x19, 0x80, 128 | 0x00, 0xA0, 0x0F, 0x2F, 129 | 0x17, 0x01, 0x8A, 0x20, 130 | 0xFF, 0xF7, 0x22, 0x01, 131 | 0x8A, 0x20, 0xFF, 0xD2, 132 | 0x22, 0xA0, 0x02, 0x26, 133 | 0x17, 0xA0, 0x03, 0x74, 134 | 0x80, 0x2C, 0x37, 0x80, 135 | 0x22, 0x36, 0x80, 0x04, 136 | 0x3F, 0x03, 0x80, 0x03, 137 | 0x19, 0x80, 0x00, 0xA0, 138 | 0x00, 0x27, 0x80, 0x2A, 139 | 0x37, 0x80, 0x00, 0x07, 140 | 0x80, 0x40, 0x3F, 0xA0, 141 | 0x00, 0x19, 0x38, 0x80, 142 | 0x28, 0x37, 0x80, 0x24, 143 | 0x36, 0x80, 0x03, 0x3F, 144 | 0x03, 0x80, 0x0A, 0x19, 145 | 0x80, 0x00, 0xA0, 0x0F, 146 | 0x2F, 0x17, 0x01, 0x8A, 147 | 0x20, 0xFF, 0xF7, 0x22, 148 | 0x01, 0x8A, 0x20, 0xFF, 149 | 0xD2, 0x22, 0x6C, 0xA0, 150 | 0x0C, 0xAC, 0xA0, 0x0E, 151 | 0x34, 0xA0, 0x01, 0x88, 152 | 0x60, 0x00, 0x1B, 0xA0, 153 | 0x01, 0x88, 0xA0, 0x00, 154 | 0x00, 0x26, 0xA0, 0x0E, 155 | 0x34, 0x38, 0xB4, 0xA0, 156 | 0xAA, 0x55, 0x3C, 0x24, 157 | 0x35, 0x21, 0x21, 0xAA, 158 | 0x20, 0xFF, 0xEE, 0x22, 159 | 0x22, 0x6C, 0x24, 0x2F, 160 | 0x27, 0x38, 0x24, 0x94, 161 | 0xEF, 0x15, 0x61, 0x21, 162 | 0xAA, 0x20, 0xFF, 0xF7, 163 | 0x22, 0x22, 0x62, 0x6C, 164 | 0xFF, 0xFF, 0xFF, 0xFF, 165 | 0xFF, 0xFF, 0xFF, 0xFF, 166 | 0x00, 0x00, 0x00, 0x00, 167 | 0x00, 0x00, 0x00, 0xFF, 168 | 0x01, 0x01, 0x01, 0x01, 169 | 0x01, 0x01, 0x01, 0x01, 170 | 0x00, 0x00, 0x00, 0x00, 171 | 0x00, 0x00, 0x00, 0x00, 172 | 0x00, 0x00, 0x00, 0x00, 173 | 0x03, 0x04, 0x08, 0x30, 174 | 0x00, 0x00, 0x07, 0x3F, 175 | 0x18, 0x0C, 0x1F, 0x3F, 176 | 0x00, 0xF4, 0xC1, 0x03, 177 | 0x07, 0x0F, 0xBF, 0x8F, 178 | 0x00, 0x40, 0x0C, 0xFC, 179 | 0xE2, 0xC1, 0xC1, 0xC1, 180 | 0x00, 0x00, 0x00, 0x00, 181 | 0x80, 0xA0, 0xE0, 0xE4, 182 | 0x00, 0x00, 0x00, 0x00, 183 | 0x00, 0x00, 0x00, 0x00, 184 | 0x00, 0x00, 0x00, 0x00, 185 | 0x01, 0x01, 0x03, 0x03, 186 | 0x60, 0xC0, 0x01, 0xE3, 187 | 0xFB, 0xF0, 0xF0, 0xE0, 188 | 0x7F, 0xFF, 0xFE, 0xFE, 189 | 0xFC, 0x78, 0x00, 0x0F, 190 | 0x81, 0x00, 0x00, 0x00, 191 | 0x00, 0x01, 0x01, 0x03, 192 | 0x80, 0x40, 0xF8, 0xFF, 193 | 0xFF, 0xFF, 0xFF, 0xFF, 194 | 0xF2, 0xF1, 0xF9, 0xF8, 195 | 0x1C, 0x00, 0x03, 0x03, 196 | 0x00, 0x00, 0x80, 0x80, 197 | 0x40, 0x20, 0xB0, 0xE0, 198 | 0x07, 0x07, 0x0F, 0x1F, 199 | 0x27, 0x20, 0x20, 0x60, 200 | 0xE0, 0xC0, 0xC0, 0x80, 201 | 0x80, 0x00, 0xE0, 0xFC, 202 | 0x0F, 0x1F, 0x1F, 0x3F, 203 | 0x3F, 0x3F, 0x7F, 0x7F, 204 | 0xE3, 0xFF, 0xF8, 0xF8, 205 | 0xF8, 0xF0, 0xF0, 0xF0, 206 | 0xFE, 0xFE, 0x7E, 0x0E, 207 | 0x00, 0x01, 0x01, 0x03, 208 | 0x01, 0x01, 0x01, 0x01, 209 | 0x01, 0xC1, 0xF9, 0xFE, 210 | 0xE0, 0xE0, 0xE0, 0xF0, 211 | 0xF0, 0xF0, 0xF0, 0xF8, 212 | 0x60, 0x60, 0x40, 0x41, 213 | 0x41, 0x41, 0x01, 0x39, 214 | 0xFF, 0xFF, 0xFF, 0xFF, 215 | 0xFE, 0xFE, 0xFE, 0xFE, 216 | 0x7F, 0x0F, 0x01, 0x00, 217 | 0x00, 0x00, 0x00, 0x00, 218 | 0xE0, 0xE0, 0xE0, 0x00, 219 | 0x3C, 0x3F, 0x7F, 0x7F, 220 | 0x03, 0x03, 0x07, 0x07, 221 | 0x07, 0x87, 0xFF, 0xF1, 222 | 0xFE, 0xFE, 0xFE, 0xFC, 223 | 0xFC, 0xFC, 0xFC, 0xFC, 224 | 0x18, 0x04, 0x06, 0x06, 225 | 0x0E, 0x0E, 0x0E, 0x0E, 226 | 0x3E, 0x1E, 0x1E, 0x1E, 227 | 0x1E, 0x0E, 0x0F, 0x0F, 228 | 0xFE, 0x1C, 0x00, 0x03, 229 | 0x03, 0x03, 0x03, 0x03, 230 | 0x00, 0x00, 0x00, 0x80, 231 | 0xF1, 0xFF, 0xFE, 0xFE, 232 | 0x7F, 0xFF, 0xFF, 0xFF, 233 | 0xFF, 0xFF, 0x3F, 0x07, 234 | 0xF0, 0xE0, 0xE0, 0xE0, 235 | 0xC0, 0xC0, 0x80, 0x80, 236 | 0x38, 0x00, 0x07, 0x0F, 237 | 0x0F, 0x1F, 0x1F, 0x3F, 238 | 0x0E, 0x0C, 0x0C, 0xFC, 239 | 0xE0, 0xC0, 0xC0, 0x80, 240 | 0x0F, 0x09, 0x04, 0x00, 241 | 0x00, 0x01, 0x00, 0x00, 242 | 0x03, 0x03, 0xC3, 0x7B, 243 | 0x3C, 0x3C, 0x9E, 0x1E, 244 | 0xFC, 0xFC, 0xFC, 0xFC, 245 | 0xF8, 0x18, 0x04, 0x0F, 246 | 0x00, 0x00, 0x01, 0x01, 247 | 0x03, 0x03, 0x07, 0x8F, 248 | 0x80, 0xE0, 0xFE, 0xFF, 249 | 0xFF, 0xFE, 0xFC, 0xF8, 250 | 0x3F, 0x7F, 0x7F, 0x3E, 251 | 0x06, 0x03, 0x07, 0x0E, 252 | 0x80, 0x00, 0x00, 0x00, 253 | 0x00, 0x00, 0x00, 0x00, 254 | 0x00, 0x00, 0x00, 0x00, 255 | 0x00, 0x00, 0x00, 0x00, 256 | 0x0E, 0x1E, 0x05, 0x00, 257 | 0x00, 0x00, 0x00, 0x00, 258 | 0x0F, 0x0F, 0x0F, 0x4F, 259 | 0x27, 0x03, 0x02, 0x00, 260 | 0xFF, 0xE1, 0xC0, 0x80, 261 | 0x03, 0x0F, 0x1E, 0x00, 262 | 0xF0, 0xE0, 0x00, 0xF9, 263 | 0xF8, 0xC0, 0x00, 0x00, 264 | 0x3C, 0x70, 0xE0, 0xC0, 265 | 0x00, 0x00, 0x00, 0x00, 266 | 0x00, 0x00, 0x00, 0x00, 267 | 0x00, 0x00, 0x00, 0x00, 268 | 0x00, 0x00, 0x00, 0x00, 269 | 0x00, 0x00, 0x00, 0x00, 270 | 0x00, 0x00, 0x00, 0x00, 271 | 0x02, 0x04, 0x08, 0x00, 272 | 0x00, 0x01, 0x0F, 0x7C, 273 | 0x10, 0x1C, 0x3F, 0xFF, 274 | 0x00, 0xE7, 0x83, 0x07, 275 | 0x0F, 0x3F, 0xFF, 0x0F, 276 | 0x00, 0x40, 0x0C, 0xDC, 277 | 0xC0, 0x83, 0x81, 0x01, 278 | 0x00, 0x00, 0x00, 0x00, 279 | 0x80, 0xA0, 0xC0, 0xE4, 280 | 0x00, 0x00, 0x00, 0x00, 281 | 0x00, 0x00, 0x00, 0x00, 282 | 0x00, 0x00, 0x00, 0x03, 283 | 0x01, 0x03, 0x03, 0x07, 284 | 0x41, 0x83, 0x07, 0xEF, 285 | 0xF3, 0xE0, 0xE0, 0xC0, 286 | 0xFE, 0xFE, 0xFC, 0xF8, 287 | 0xF0, 0x70, 0x18, 0x1F, 288 | 0x01, 0x01, 0x01, 0x03, 289 | 0x03, 0x03, 0x07, 0x07, 290 | 0x01, 0xC1, 0xF9, 0xFE, 291 | 0xFE, 0xFC, 0xFC, 0xFC, 292 | 0xE2, 0xF3, 0xF1, 0xF8, 293 | 0x18, 0x04, 0x07, 0x07, 294 | 0x00, 0x00, 0x00, 0x80, 295 | 0x40, 0x60, 0xB0, 0xC0, 296 | 0x07, 0x0F, 0x3F, 0x1F, 297 | 0x27, 0x21, 0x01, 0x01, 298 | 0xC0, 0x80, 0x80, 0x00, 299 | 0x00, 0x00, 0xE1, 0xFD, 300 | 0x3F, 0x3F, 0x7F, 0x7F, 301 | 0xFF, 0xFF, 0xFF, 0xFF, 302 | 0xEF, 0xF3, 0xF0, 0xE0, 303 | 0xE0, 0xC0, 0xC0, 0xC0, 304 | 0xFC, 0xFC, 0x7C, 0x0C, 305 | 0x06, 0x07, 0x07, 0x07, 306 | 0x03, 0x03, 0x03, 0x03, 307 | 0x03, 0xC3, 0xFB, 0xFC, 308 | 0xC0, 0xE0, 0xE0, 0xE4, 309 | 0xE0, 0xE0, 0xF0, 0xF0, 310 | 0x41, 0x41, 0x43, 0x43, 311 | 0x43, 0x43, 0x43, 0x3B, 312 | 0xFE, 0xFE, 0xFC, 0xFC, 313 | 0xFC, 0xFC, 0xF8, 0xF8, 314 | 0x7F, 0x0F, 0x01, 0x00, 315 | 0x00, 0x00, 0x00, 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0xFF, 0xFF, 416 | 0x1F, 0x3F, 0x3F, 0x3F, 417 | 0x7F, 0xFF, 0x8F, 0x01, 418 | 0xF0, 0xF0, 0xF0, 0xF0, 419 | 0xE0, 0xE0, 0xE0, 0xE0, 420 | 0x00, 0x1C, 0x1E, 0x1E, 421 | 0x1E, 0x1C, 0x3C, 0x3C, 422 | 0x78, 0x38, 0x38, 0x38, 423 | 0x3C, 0x1C, 0x1C, 0x1C, 424 | 0xF0, 0x00, 0x1C, 0x1F, 425 | 0x1F, 0x1F, 0x0F, 0x0F, 426 | 0x07, 0x07, 0x07, 0x8F, 427 | 0xFF, 0xF1, 0xF0, 0xE0, 428 | 0xFF, 0xFF, 0xFE, 0xFE, 429 | 0xFE, 0xFC, 0x3C, 0x00, 430 | 0x00, 0x00, 0x00, 0x00, 431 | 0x00, 0x00, 0x00, 0x01, 432 | 0x20, 0x38, 0x3F, 0x7F, 433 | 0x7F, 0xFF, 0xFF, 0xFE, 434 | 0x3C, 0x3C, 0x3C, 0xDC, 435 | 0x80, 0x04, 0x08, 0x00, 436 | 0x0C, 0x00, 0x01, 0x00, 437 | 0x00, 0x00, 0x00, 0x00, 438 | 0x0F, 0x0F, 0xCF, 0xF7, 439 | 0x70, 0x78, 0x38, 0x18, 440 | 0xE0, 0xE0, 0xE0, 0xE0, 441 | 0xE0, 0x20, 0x3C, 0x3F, 442 | 0x07, 0x07, 0x0F, 0x0F, 443 | 0x1F, 0x1F, 0x3F, 0xBF, 444 | 0x01, 0xE1, 0xFD, 0xF8, 445 | 0xF0, 0xF0, 0xE0, 0xC0, 446 | 0xFE, 0xFC, 0xFC, 0x38, 447 | 0x00, 0x0F, 0x1E, 0x3C, 448 | 0x10, 0x00, 0x20, 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0xFE, 582 | 0x0E, 0x1F, 0x3F, 0x3F, 583 | 0x7F, 0x7F, 0xFF, 0xFF, 584 | 0x0F, 0xDF, 0xE7, 0xE0, 585 | 0xC0, 0xC0, 0xC0, 0xC0, 586 | 0x86, 0x86, 0xC3, 0xC3, 587 | 0x21, 0x3C, 0x3F, 0x3F, 588 | 0x00, 0x00, 0x00, 0x80, 589 | 0xC0, 0xC0, 0x60, 0x00, 590 | 0x0E, 0x1C, 0x3C, 0x38, 591 | 0x00, 0x0F, 0x0F, 0x0F, 592 | 0x03, 0x07, 0x07, 0x0F, 593 | 0x0F, 0x1F, 0xFF, 0xE3, 594 | 0xFE, 0xFE, 0xFC, 0xFC, 595 | 0xF8, 0xF8, 0xF8, 0xF0, 596 | 0x1F, 0x03, 0x00, 0x00, 597 | 0x00, 0x00, 0x00, 0x01, 598 | 0x80, 0x80, 0x00, 0x70, 599 | 0xFE, 0xFF, 0xFF, 0xFF, 600 | 0x3F, 0x3F, 0x3F, 0x3F, 601 | 0x3F, 0xFF, 0xC7, 0x80, 602 | 0x08, 0x08, 0x88, 0x84, 603 | 0x84, 0x84, 0x84, 0x82, 604 | 0x0F, 0x0F, 0x0F, 0x0F, 605 | 0x1F, 0x1F, 0x5F, 0x67, 606 | 0xC0, 0xC0, 0xC0, 0xC0, 607 | 0xC0, 0x80, 0x80, 0x80, 608 | 0x70, 0x00, 0x1E, 0x1F, 609 | 0x1F, 0x1F, 0x3F, 0x3F, 610 | 0x01, 0x01, 0x03, 0xC3, 611 | 0xFF, 0xF8, 0xF8, 0xF8, 612 | 0xFF, 0xFF, 0xFF, 0xFF, 613 | 0xFF, 0x7F, 0x0F, 0x01, 614 | 0x80, 0x80, 0x80, 0x80, 615 | 0x00, 0x00, 0x00, 0x00, 616 | 0x62, 0x7E, 0x7C, 0x7C, 617 | 0x7C, 0xFC, 0xF8, 0xF8, 618 | 0x60, 0x30, 0x30, 0x30, 619 | 0x30, 0x18, 0x18, 0x18, 620 | 0x80, 0x60, 0x7C, 0x7F, 621 | 0x7F, 0x7F, 0x7F, 0x7F, 622 | 0x3F, 0x7F, 0x7F, 0xFF, 623 | 0x8F, 0x81, 0x80, 0x80, 624 | 0xF0, 0xF0, 0xF0, 0xE0, 625 | 0xE0, 0xE0, 0x00, 0x38, 626 | 0x01, 0x01, 0x03, 0x03, 627 | 0x03, 0x07, 0x07, 0x0F, 628 | 0xC0, 0xF8, 0xFF, 0xFE, 629 | 0xFE, 0xFC, 0xFC, 0xF8, 630 | 0xF8, 0xF8, 0xF8, 0x18, 631 | 0x04, 0x0C, 0x18, 0x10, 632 | 0x08, 0x02, 0x03, 0x01, 633 | 0x00, 0x00, 0x00, 0x00, 634 | 0x3F, 0x3F, 0xFF, 0xC7, 635 | 0xE0, 0x60, 0x70, 0x30, 636 | 0x00, 0x00, 0x00, 0x00, 637 | 0x00, 0xE0, 0xFD, 0xFE, 638 | 0x3F, 0x7F, 0x7F, 0xFF, 639 | 0xFF, 0xFF, 0xFF, 0x7E, 640 | 0x0F, 0xFF, 0xE1, 0xC0, 641 | 0x80, 0x80, 0x00, 0x01, 642 | 0xF8, 0xF0, 0xF0, 0x20, 643 | 0x38, 0x7F, 0xFC, 0xF8, 644 | 0x30, 0x20, 0x60, 0x40, 645 | 0xC0, 0x80, 0x00, 0x00, 646 | 0x00, 0x00, 0x00, 0x00, 647 | 0x00, 0x00, 0x00, 0x00, 648 | 0x18, 0x18, 0x02, 0x00, 649 | 0x00, 0x00, 0x00, 0x00, 650 | 0x7C, 0x7C, 0x7C, 0xB8, 651 | 0x40, 0x0F, 0x01, 0x00, 652 | 0x0E, 0x02, 0x0F, 0x1F, 653 | 0x3F, 0x7C, 0xD0, 0x00, 654 | 0x03, 0x07, 0xCF, 0xE7, 655 | 0x03, 0x18, 0x80, 0x00, 656 | 0xF0, 0xE0, 0xC0, 0x00, 657 | 0x00, 0x00, 0x00, 0x00, 658 | 0x00, 0x00, 0x00, 0x00, 659 | 0x00, 0x00, 0x00, 0x00, 660 | 0x00, 0x00, 0x00, 0x00, 661 | 0x00, 0x00, 0x00, 0x00, 662 | 0x00, 0x00, 0x00, 0x00, 663 | 0x00, 0x01, 0x03, 0x07, 664 | 0x00, 0x01, 0x18, 0xC0, 665 | 0xE1, 0xFB, 0xF0, 0xE0, 666 | 0x00, 0x87, 0x1F, 0x7E, 667 | 0xFC, 0xF8, 0x70, 0x10, 668 | 0x00, 0x80, 0x70, 0x12, 669 | 0x0D, 0x1F, 0x1F, 0x1F, 670 | 0x00, 0x00, 0x00, 0x00, 671 | 0x00, 0x40, 0x10, 0x0C, 672 | 0x00, 0x00, 0x00, 0x00, 673 | 0x00, 0x00, 0x00, 0x00, 674 | 0x00, 0x00, 0x01, 0x03, 675 | 0x03, 0x06, 0x06, 0x0C, 676 | 0x0F, 0x3F, 0x7F, 0x9E, 677 | 0x00, 0x03, 0x07, 0x07, 678 | 0xC0, 0x80, 0x00, 0x00, 679 | 0x00, 0x81, 0xFB, 0xFC, 680 | 0x3E, 0x7F, 0x7F, 0xFF, 681 | 0xFF, 0xFF, 0xFF, 0xFF, 682 | 0x3F, 0xFF, 0xC7, 0x80, 683 | 0x80, 0x80, 0x00, 0x00, 684 | 0x0C, 0x86, 0x87, 0x83, 685 | 0x63, 0x7D, 0x7E, 0x7E, 686 | 0x00, 0x00, 0x00, 0x80, 687 | 0x80, 0xC0, 0x60, 0x10, 688 | 0x0C, 0x18, 0x38, 0x30, 689 | 0x08, 0x0F, 0x0F, 0x1F, 690 | 0x0F, 0x0F, 0x1F, 0x1F, 691 | 0x3F, 0x3F, 0x9F, 0x83, 692 | 0xF8, 0xF8, 0xF8, 0xF0, 693 | 0xF0, 0xE0, 0xE0, 0xE0, 694 | 0x1F, 0x02, 0x01, 0x01, 695 | 0x03, 0x03, 0x03, 0x07, 696 | 0x00, 0x00, 0x80, 0xF0, 697 | 0xFE, 0xFF, 0xFF, 0xFF, 698 | 0x7E, 0x7F, 0x7F, 0x7F, 699 | 0x7F, 0x3F, 0x07, 0x00, 700 | 0x18, 0x08, 0x08, 0x0C, 701 | 0x0C, 0x04, 0x04, 0x06, 702 | 0x1F, 0x1F, 0x1F, 0x1F, 703 | 0x1F, 0x1F, 0x7F, 0x67, 704 | 0x80, 0x80, 0x80, 0x80, 705 | 0x00, 0x00, 0x00, 0x00, 706 | 0x40, 0x30, 0x3E, 0x7F, 707 | 0x7F, 0x7F, 0x7F, 0xFF, 708 | 0x07, 0x07, 0x0F, 0xCF, 709 | 0xF3, 0xF0, 0xE0, 0xE0, 710 | 0xFF, 0xFE, 0xFE, 0xFE, 711 | 0xFE, 0x7C, 0x0C, 0x02, 712 | 0x00, 0x00, 0x00, 0x00, 713 | 0x01, 0x01, 0x01, 0x01, 714 | 0xE6, 0xFE, 0xF8, 0xF8, 715 | 0xF8, 0xF8, 0xF8, 0xF8, 716 | 0x60, 0x20, 0x20, 0x30, 717 | 0x30, 0x10, 0x10, 0x18, 718 | 0x00, 0xE0, 0xFC, 0xFE, 719 | 0xFE, 0xFE, 0xFE, 0x7E, 720 | 0xFF, 0xFF, 0xFF, 0x7F, 721 | 0x0F, 0x01, 0x00, 0x00, 722 | 0xE0, 0xC0, 0xC0, 0xC0, 723 | 0x80, 0x80, 0x40, 0xF8, 724 | 0x07, 0x07, 0x07, 0x0F, 725 | 0x0F, 0x1F, 0x1F, 0x1F, 726 | 0xC1, 0xF9, 0xFC, 0xFC, 727 | 0xF8, 0xF8, 0xF0, 0xF0, 728 | 0xF8, 0xF0, 0xF0, 0x10, 729 | 0x0C, 0x1C, 0x18, 0x30, 730 | 0x08, 0x06, 0x03, 0x01, 731 | 0x01, 0x00, 0x00, 0x00, 732 | 0x7E, 0x7E, 0xBE, 0xC6, 733 | 0xC1, 0xE1, 0x61, 0x30, 734 | 0x00, 0x00, 0x01, 0x01, 735 | 0x01, 0xE3, 0xFF, 0xFC, 736 | 0xFF, 0xFF, 0xFF, 0xFF, 737 | 0xFF, 0xFE, 0xFE, 0x7C, 738 | 0x3F, 0xDF, 0x81, 0x00, 739 | 0x00, 0x00, 0x01, 0x03, 740 | 0xE0, 0xE0, 0xC0, 0x00, 741 | 0x79, 0xFE, 0xFC, 0xF0, 742 | 0x30, 0x60, 0x60, 0xC0, 743 | 0xC0, 0x80, 0x00, 0x00, 744 | 0x00, 0x00, 0x00, 0x00, 745 | 0x00, 0x00, 0x00, 0x00, 746 | 0x30, 0x08, 0x02, 0x00, 747 | 0x00, 0x00, 0x00, 0x00, 748 | 0xF8, 0xF8, 0xF8, 0xB0, 749 | 0x48, 0x0E, 0x01, 0x00, 750 | 0x08, 0x0E, 0x1F, 0x3F, 751 | 0x7E, 0xF8, 0xE1, 0x00, 752 | 0x07, 0x0F, 0xDF, 0x87, 753 | 0x03, 0x18, 0x80, 0x00, 754 | 0xE0, 0xC0, 0x80, 0x00, 755 | 0x00, 0x00, 0x00, 0x00, 756 | 0x00, 0x00, 0x00, 0x00, 757 | 0x00, 0x00, 0x00, 0x00, 758 | 0x00, 0x00, 0x00, 0x00, 759 | 0x00, 0x00, 0x00, 0x00, 760 | 0x00, 0x00, 0x00, 0x00, 761 | 0x03, 0x07, 0x0F, 0x3F, 762 | 0x00, 0x01, 0x1F, 0xFF, 763 | 0xFF, 0xFF, 0xFF, 0xFF, 764 | 0x00, 0xFF, 0xFF, 0xFF, 765 | 0xFF, 0xFF, 0xFF, 0xFF, 766 | 0x00, 0xC0, 0xFC, 0xFE, 767 | 0xFF, 0xFF, 0xFF, 0xFF, 768 | 0x00, 0x00, 0x00, 0x00, 769 | 0x80, 0xE0, 0xF8, 0xFC, 770 | 0x00, 0x00, 0x00, 0x00, 771 | 0x00, 0x00, 0x00, 0x00, 772 | 0x00, 0x00, 0x01, 0x03, 773 | 0x03, 0x07, 0x07, 0x0F, 774 | 0x7F, 0xFF, 0xFF, 0xFF, 775 | 0xFF, 0xFF, 0xFF, 0xFF, 776 | 0xFF, 0xFF, 0xFF, 0xFF, 777 | 0xFF, 0xFF, 0xFF, 0xFF, 778 | 0xFF, 0xFF, 0xFF, 0xFF, 779 | 0xFF, 0xFF, 0xFF, 0xFF, 780 | 0xFF, 0xFF, 0xFF, 0xFF, 781 | 0xFF, 0xFF, 0xFF, 0xFF, 782 | 0xFE, 0xFF, 0xFF, 0xFF, 783 | 0xFF, 0xFF, 0xFF, 0xFF, 784 | 0x00, 0x00, 0x80, 0x80, 785 | 0xC0, 0xE0, 0xF0, 0xF0, 786 | 0x0F, 0x1F, 0x3F, 0x3F, 787 | 0x3F, 0x3F, 0x7F, 0x7F, 788 | 0xFF, 0xFF, 0xFF, 0xFF, 789 | 0xFF, 0xFF, 0xFF, 0xFF, 790 | 0xFF, 0xFF, 0xFF, 0xFF, 791 | 0xFF, 0xFF, 0xFF, 0xFF, 792 | 0xFF, 0xFF, 0xFF, 0xFF, 793 | 0xFF, 0xFF, 0xFF, 0xFF, 794 | 0xFF, 0xFF, 0xFF, 0xFF, 795 | 0xFF, 0xFF, 0xFF, 0xFF, 796 | 0xFF, 0xFF, 0xFF, 0xFF, 797 | 0xFF, 0xFF, 0xFF, 0xFF, 798 | 0xF8, 0xF8, 0xF8, 0xFC, 799 | 0xFC, 0xFC, 0xFC, 0xFE, 800 | 0x7F, 0x7F, 0x7F, 0x7F, 801 | 0x7F, 0x7F, 0x7F, 0x7F, 802 | 0xFF, 0xFF, 0xFF, 0xFF, 803 | 0xFF, 0xFF, 0xFF, 0xFF, 804 | 0xFF, 0xFF, 0xFF, 0xFF, 805 | 0xFF, 0xFF, 0xFF, 0xFF, 806 | 0xFF, 0xFF, 0xFF, 0xFF, 807 | 0xFF, 0xFF, 0xFF, 0xFF, 808 | 0xFF, 0xFF, 0xFF, 0xFF, 809 | 0xFF, 0xFF, 0xFF, 0xFF, 810 | 0xFF, 0xFF, 0xFF, 0xFF, 811 | 0xFF, 0xFF, 0xFF, 0xFF, 812 | 0xFE, 0xFE, 0xFE, 0xFE, 813 | 0xFE, 0xFE, 0xFE, 0xFE, 814 | 0x7F, 0x3F, 0x3F, 0x3F, 815 | 0x3F, 0x1F, 0x1F, 0x1F, 816 | 0xFF, 0xFF, 0xFF, 0xFF, 817 | 0xFF, 0xFF, 0xFF, 0xFF, 818 | 0xFF, 0xFF, 0xFF, 0xFF, 819 | 0xFF, 0xFF, 0xFF, 0xFF, 820 | 0xFF, 0xFF, 0xFF, 0xFF, 821 | 0xFF, 0xFF, 0xFF, 0xFF, 822 | 0xFF, 0xFF, 0xFF, 0xFF, 823 | 0xFF, 0xFF, 0xFF, 0xFF, 824 | 0xFF, 0xFF, 0xFF, 0xFF, 825 | 0xFF, 0xFF, 0xFF, 0xFF, 826 | 0xFE, 0xFE, 0xFC, 0xFC, 827 | 0xFC, 0xFC, 0xF8, 0xF0, 828 | 0x0F, 0x0F, 0x07, 0x03, 829 | 0x01, 0x01, 0x00, 0x00, 830 | 0xFF, 0xFF, 0xFF, 0xFF, 831 | 0xFF, 0xFF, 0xFF, 0x7F, 832 | 0xFF, 0xFF, 0xFF, 0xFF, 833 | 0xFF, 0xFF, 0xFF, 0xFF, 834 | 0xFF, 0xFF, 0xFF, 0xFF, 835 | 0xFF, 0xFF, 0xFF, 0xFF, 836 | 0xFF, 0xFF, 0xFF, 0xFF, 837 | 0xFF, 0xFF, 0xFF, 0xFF, 838 | 0xFF, 0xFF, 0xFF, 0xFF, 839 | 0xFF, 0xFF, 0xFF, 0xFE, 840 | 0xF0, 0xE0, 0xE0, 0xC0, 841 | 0xC0, 0x80, 0x00, 0x00, 842 | 0x00, 0x00, 0x00, 0x00, 843 | 0x00, 0x00, 0x00, 0x00, 844 | 0x3F, 0x1F, 0x07, 0x01, 845 | 0x00, 0x00, 0x00, 0x00, 846 | 0xFF, 0xFF, 0xFF, 0xFF, 847 | 0x7F, 0x3F, 0x03, 0x00, 848 | 0xFF, 0xFF, 0xFF, 0xFF, 849 | 0xFF, 0xFF, 0xFF, 0x00, 850 | 0xFF, 0xFF, 0xFF, 0xFF, 851 | 0xFF, 0xF8, 0x80, 0x00, 852 | 0xFC, 0xF0, 0xE0, 0xC0, 853 | 0x00, 0x00, 0x00, 0x00, 854 | 0x00, 0x00, 0x00, 0x00, 855 | 0x00, 0x00, 0x00, 0x00, 856 | }; 857 | 858 | static uint32_t rdaddr; 859 | rdaddr = (uint32_t)(read_address); 860 | 861 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 862 | rdaddr, // read address 863 | 0, // write value 864 | 0 // write enable 865 | ); 866 | 867 | return rdata; 868 | } -------------------------------------------------------------------------------- /roms/bounce.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | /* BOUNCE (assembly) 5 | |0100 6 | ;L.screen.hook #20 DEO2 7 | LIT2r 0000 main_ POP2r BRK 8 | @L.screen.hook LIT2r 0000 on_screen_ POP2 POP2r BRK 9 | ( bss ) 10 | ( data ) 11 | @dy_ 12 | 0001 13 | @dx_ 14 | 0001 15 | @y_ 16 | 0000 17 | @x_ 18 | 0000 19 | @ball_color_ 20 | 01 21 | @bg_color_ 22 | 00 23 | @size_ 24 | 000c 25 | ( text ) 26 | @sext 27 | #80 ANDk EQU #ff MUL SWP JMP2r 28 | 29 | @on_screen_ ( -- result* ) 30 | OVR2r LIT2r 0004 SUB2r #0000 #28 DEO2 #0000 #2a DEO2 ;bg_color_ LDA sext 31 | #0080 ORA2 NIP #2e DEO ;x_ LDA2k ;dx_ LDA2 ADD2 SWP2 STA2 32 | ;y_ LDA2k ;dy_ LDA2 ADD2 SWP2 STA2 33 | #018f ;size_ LDA2 SUB2 #8000 EOR2 ;x_ LDA2 #8000 EOR2 LTH2 #00 ORA ?&true.2 34 | ;x_ LDA2 #0000 EQU2 #00 ORA ?&true.2 35 | #0000 !&end.2 36 | 37 | &true.2 38 | #0001 39 | 40 | &end.2 41 | #0000 EQU2 ?&end.1 42 | ;bg_color_ LDAk sext 43 | INC2 SWP2 STA 44 | POP ;ball_color_ LDAk sext 45 | INC2 SWP2 STA 46 | POP #0000 ;dx_ LDA2 SUB2 ;dx_ STA2 47 | 48 | &end.1 49 | #0167 ;size_ LDA2 SUB2 #8000 EOR2 ;y_ LDA2 #8000 EOR2 LTH2 #00 ORA ?&true.4 50 | ;y_ LDA2 #0000 EQU2 #00 ORA ?&true.4 51 | #0000 !&end.4 52 | 53 | &true.4 54 | #0001 55 | 56 | &end.4 57 | #0000 EQU2 ?&end.3 58 | ;bg_color_ LDAk sext 59 | INC2 SWP2 STA 60 | POP ;ball_color_ LDAk sext 61 | INC2 SWP2 STA 62 | POP #0000 ;dy_ LDA2 SUB2 ;dy_ STA2 63 | 64 | &end.3 65 | #8003 ;bg_color_ LDA sext 66 | #8000 EOR2 LTH2 #00 EQU ?&end.5 67 | #0000 ;bg_color_ STA 68 | POP 69 | 70 | &end.5 71 | #8003 ;ball_color_ LDA sext 72 | #8000 EOR2 LTH2 #00 EQU ?&end.6 73 | #0000 ;ball_color_ STA 74 | POP 75 | 76 | &end.6 77 | ;x_ LDA2 STH2kr INC2 INC2 STA2 78 | 79 | &begin.7 80 | STH2kr INC2 INC2 LDA2 #8000 EOR2 ;x_ LDA2 ;size_ LDA2 ADD2 #8000 EOR2 LTH2 #00 EQU ?&break.7 81 | ;y_ LDA2 STH2kr STA2 82 | 83 | &begin.8 84 | STH2kr LDA2 #8000 EOR2 ;y_ LDA2 ;size_ LDA2 ADD2 #8000 EOR2 LTH2 #00 EQU ?&break.8 85 | STH2kr INC2 INC2 LDA2 #28 DEO2 STH2kr LDA2 #2a DEO2 ;ball_color_ LDA #2e DEO 86 | 87 | &continue.8 88 | STH2kr LDA2k INC2k ROT2 STA2 89 | POP2 !&begin.8 90 | 91 | &break.8 92 | 93 | &continue.7 94 | STH2kr INC2 INC2 LDA2k INC2k ROT2 STA2 95 | POP2 !&begin.7 96 | 97 | &break.7 98 | #0000 99 | 100 | &return 101 | POP2r JMP2r 102 | 103 | @main_ ( -- result* ) 104 | OVR2r #08df #08 DEO2 #12bf #0a DEO2 #549d #0c DEO2 #0190 #22 DEO2 #0168 #24 DEO2 #0000 105 | 106 | &return 107 | POP2r JMP2r 108 | 109 | */ 110 | 111 | /* BOUNCE.C 112 | #include 113 | 114 | int size = 12; 115 | char bg_color = 0x00; 116 | char ball_color = 0x01; 117 | int x = 0; 118 | int y = 0; 119 | int dx = 1; 120 | int dy = 1; 121 | 122 | void on_screen(void) { 123 | 124 | set_screen_xy(0, 0); 125 | draw_pixel(BgFillBR | bg_color); 126 | 127 | x += dx; 128 | y += dy; 129 | 130 | if (x > (399 - size) || x == 0) { 131 | bg_color += 1; 132 | ball_color += 1; 133 | dx = -dx; 134 | } 135 | 136 | if (y > (359 - size) || y == 0) { 137 | bg_color += 1; 138 | ball_color += 1; 139 | dy = -dy; 140 | } 141 | 142 | if (bg_color > 0x03) { 143 | bg_color = 0x00; 144 | } 145 | 146 | if (ball_color > 0x03) { 147 | ball_color = 0x00; 148 | } 149 | 150 | for (int ball_x = x; ball_x < (x + size); ball_x++) { 151 | for (int ball_y = y; ball_y < (y + size); ball_y++) { 152 | set_screen_xy(ball_x, ball_y); 153 | draw_pixel(ball_color); 154 | } 155 | } 156 | } 157 | 158 | void main(void) { 159 | set_palette(0x08df, 0x12bf, 0x549d); 160 | set_screen_size(400, 360); 161 | } 162 | 163 | */ 164 | 165 | #define ROM_SIZE 512 166 | 167 | uint8_t read_rom_byte(uint16_t read_address) 168 | { 169 | static uint8_t uxn_rom[ROM_SIZE] = { 170 | 0xA0, 0x01, 0x0E, 0x80, 171 | 0x20, 0x37, 0xE0, 0x00, 172 | 0x00, 0x60, 0x01, 0xB6, 173 | 0x62, 0x00, 0xE0, 0x00, 174 | 0x00, 0x60, 0x00, 0x18, 175 | 0x22, 0x62, 0x00, 0x00, 176 | 0x01, 0x00, 0x01, 0x00, 177 | 0x00, 0x00, 0x00, 0x01, 178 | 0x00, 0x00, 0x0C, 0x80, 179 | 0x80, 0x9C, 0x08, 0x80, 180 | 0xFF, 0x1A, 0x04, 0x6C, 181 | 0x67, 0xE0, 0x00, 0x04, 182 | 0x79, 0xA0, 0x00, 0x00, 183 | 0x80, 0x28, 0x37, 0xA0, 184 | 0x00, 0x00, 0x80, 0x2A, 185 | 0x37, 0xA0, 0x01, 0x20, 186 | 0x14, 0x60, 0xFF, 0xDF, 187 | 0xA0, 0x00, 0x80, 0x3D, 188 | 0x03, 0x80, 0x2E, 0x17, 189 | 0xA0, 0x01, 0x1D, 0xB4, 190 | 0xA0, 0x01, 0x19, 0x34, 191 | 0x38, 0x24, 0x35, 0xA0, 192 | 0x01, 0x1B, 0xB4, 0xA0, 193 | 0x01, 0x17, 0x34, 0x38, 194 | 0x24, 0x35, 0xA0, 0x00, 195 | 0xFF, 0xA0, 0x01, 0x21, 196 | 0x34, 0x39, 0xA0, 0x80, 197 | 0x00, 0x3E, 0xA0, 0x01, 198 | 0x1D, 0x34, 0xA0, 0x80, 199 | 0x00, 0x3E, 0x2B, 0x80, 200 | 0x00, 0x1D, 0x20, 0x00, 201 | 0x14, 0xA0, 0x01, 0x1D, 202 | 0x34, 0xA0, 0x00, 0x00, 203 | 0x28, 0x80, 0x00, 0x1D, 204 | 0x20, 0x00, 0x06, 0xA0, 205 | 0x00, 0x00, 0x40, 0x00, 206 | 0x03, 0xA0, 0x00, 0x01, 207 | 0xA0, 0x00, 0x00, 0x28, 208 | 0x20, 0x00, 0x22, 0xA0, 209 | 0x01, 0x20, 0x94, 0x60, 210 | 0xFF, 0x81, 0x21, 0x24, 211 | 0x15, 0x02, 0xA0, 0x01, 212 | 0x1F, 0x94, 0x60, 0xFF, 213 | 0x76, 0x21, 0x24, 0x15, 214 | 0x02, 0xA0, 0x00, 0x00, 215 | 0xA0, 0x01, 0x19, 0x34, 216 | 0x39, 0xA0, 0x01, 0x19, 217 | 0x35, 0xA0, 0x00, 0xEF, 218 | 0xA0, 0x01, 0x21, 0x34, 219 | 0x39, 0xA0, 0x80, 0x00, 220 | 0x3E, 0xA0, 0x01, 0x1B, 221 | 0x34, 0xA0, 0x80, 0x00, 222 | 0x3E, 0x2B, 0x80, 0x00, 223 | 0x1D, 0x20, 0x00, 0x14, 224 | 0xA0, 0x01, 0x1B, 0x34, 225 | 0xA0, 0x00, 0x00, 0x28, 226 | 0x80, 0x00, 0x1D, 0x20, 227 | 0x00, 0x06, 0xA0, 0x00, 228 | 0x00, 0x40, 0x00, 0x03, 229 | 0xA0, 0x00, 0x01, 0xA0, 230 | 0x00, 0x00, 0x28, 0x20, 231 | 0x00, 0x22, 0xA0, 0x01, 232 | 0x20, 0x94, 0x60, 0xFF, 233 | 0x26, 0x21, 0x24, 0x15, 234 | 0x02, 0xA0, 0x01, 0x1F, 235 | 0x94, 0x60, 0xFF, 0x1B, 236 | 0x21, 0x24, 0x15, 0x02, 237 | 0xA0, 0x00, 0x00, 0xA0, 238 | 0x01, 0x17, 0x34, 0x39, 239 | 0xA0, 0x01, 0x17, 0x35, 240 | 0xA0, 0x80, 0x03, 0xA0, 241 | 0x01, 0x20, 0x14, 0x60, 242 | 0xFF, 0x01, 0xA0, 0x80, 243 | 0x00, 0x3E, 0x2B, 0x80, 244 | 0x00, 0x08, 0x20, 0x00, 245 | 0x08, 0xA0, 0x00, 0x00, 246 | 0xA0, 0x01, 0x20, 0x15, 247 | 0x02, 0xA0, 0x80, 0x03, 248 | 0xA0, 0x01, 0x1F, 0x14, 249 | 0x60, 0xFE, 0xE4, 0xA0, 250 | 0x80, 0x00, 0x3E, 0x2B, 251 | 0x80, 0x00, 0x08, 0x20, 252 | 0x00, 0x08, 0xA0, 0x00, 253 | 0x00, 0xA0, 0x01, 0x1F, 254 | 0x15, 0x02, 0xA0, 0x01, 255 | 0x1D, 0x34, 0xEF, 0x21, 256 | 0x21, 0x35, 0xEF, 0x21, 257 | 0x21, 0x34, 0xA0, 0x80, 258 | 0x00, 0x3E, 0xA0, 0x01, 259 | 0x1D, 0x34, 0xA0, 0x01, 260 | 0x21, 0x34, 0x38, 0xA0, 261 | 0x80, 0x00, 0x3E, 0x2B, 262 | 0x80, 0x00, 0x08, 0x20, 263 | 0x00, 0x47, 0xA0, 0x01, 264 | 0x1B, 0x34, 0xEF, 0x35, 265 | 0xEF, 0x34, 0xA0, 0x80, 266 | 0x00, 0x3E, 0xA0, 0x01, 267 | 0x1B, 0x34, 0xA0, 0x01, 268 | 0x21, 0x34, 0x38, 0xA0, 269 | 0x80, 0x00, 0x3E, 0x2B, 270 | 0x80, 0x00, 0x08, 0x20, 271 | 0x00, 0x1C, 0xEF, 0x21, 272 | 0x21, 0x34, 0x80, 0x28, 273 | 0x37, 0xEF, 0x34, 0x80, 274 | 0x2A, 0x37, 0xA0, 0x01, 275 | 0x1F, 0x14, 0x80, 0x2E, 276 | 0x17, 0xEF, 0xB4, 0xA1, 277 | 0x25, 0x35, 0x22, 0x40, 278 | 0xFF, 0xCA, 0xEF, 0x21, 279 | 0x21, 0xB4, 0xA1, 0x25, 280 | 0x35, 0x22, 0x40, 0xFF, 281 | 0x9D, 0xA0, 0x00, 0x00, 282 | 0x62, 0x6C, 0x67, 0xA0, 283 | 0x08, 0xDF, 0x80, 0x08, 284 | 0x37, 0xA0, 0x12, 0xBF, 285 | 0x80, 0x0A, 0x37, 0xA0, 286 | 0x54, 0x9D, 0x80, 0x0C, 287 | 0x37, 0xA0, 0x01, 0x00, 288 | 0x80, 0x22, 0x37, 0xA0, 289 | 0x00, 0xF0, 0x80, 0x24, 290 | 0x37, 0xA0, 0x00, 0x00, 291 | 0x62, 0x6C, 0x00, 0x00, 292 | 0x00, 0x00, 0x00, 0x00, 293 | 0x00, 0x00, 0x00, 0x00, 294 | 0x00, 0x00, 0x00, 0x00, 295 | 0x00, 0x00, 0x00, 0x00, 296 | 0x00, 0x00, 0x00, 0x00, 297 | 0x00, 0x00, 0x00, 0x00 298 | }; 299 | 300 | static uint32_t rdaddr; 301 | rdaddr = (uint32_t)(read_address); 302 | 303 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 304 | rdaddr, // read address 305 | 0, // write value 306 | 0 // write enable 307 | ); 308 | 309 | return rdata; 310 | } -------------------------------------------------------------------------------- /roms/controller.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | // Controller Device Test 5 | 6 | #define ROM_SIZE 824 7 | 8 | uint8_t read_rom_byte(uint16_t read_address) 9 | { 10 | static uint8_t uxn_rom[ROM_SIZE] = { 11 | 0xA0, 0x0F, 0xFF, 0x80, 12 | 0x08, 0x37, 0xA0, 0x0F, 13 | 0x0F, 0x80, 0x0A, 0x37, 14 | 0xA0, 0x0F, 0x0F, 0x80, 15 | 0x0C, 0x37, 0x80, 0x22, 16 | 0x36, 0x80, 0x01, 0x3F, 17 | 0x80, 0x00, 0x31, 0x80, 18 | 0x24, 0x36, 0x80, 0x01, 19 | 0x3F, 0x80, 0x02, 0x31, 20 | 0xA0, 0x00, 0x68, 0x80, 21 | 0x04, 0x31, 0xA0, 0x00, 22 | 0x30, 0x80, 0x06, 0x31, 23 | 0x80, 0x00, 0x30, 0x80, 24 | 0x04, 0x30, 0x80, 0x01, 25 | 0x3F, 0x39, 0x80, 0x08, 26 | 0x31, 0x80, 0x02, 0x30, 27 | 0x80, 0x06, 0x30, 0x80, 28 | 0x01, 0x3F, 0x39, 0x80, 29 | 0x0A, 0x31, 0x80, 0x08, 30 | 0x30, 0x80, 0x04, 0x30, 31 | 0x38, 0x80, 0x0C, 0x31, 32 | 0x80, 0x0A, 0x30, 0x80, 33 | 0x06, 0x30, 0x38, 0x80, 34 | 0x0E, 0x31, 0xA0, 0x01, 35 | 0x79, 0x80, 0x80, 0x37, 36 | 0x80, 0x08, 0x30, 0x80, 37 | 0x0A, 0x30, 0x80, 0x0C, 38 | 0x30, 0x80, 0x0E, 0x30, 39 | 0x80, 0x03, 0x60, 0x01, 40 | 0xA6, 0x60, 0x00, 0x11, 41 | 0x00, 0x60, 0x00, 0x0D, 42 | 0xA0, 0x08, 0x82, 0x16, 43 | 0x09, 0x20, 0x00, 0x04, 44 | 0xA0, 0x01, 0x0E, 0x17, 45 | 0x00, 0x80, 0x82, 0x16, 46 | 0x0F, 0x80, 0x08, 0x30, 47 | 0xA0, 0x00, 0x10, 0x38, 48 | 0x80, 0x28, 0x37, 0x80, 49 | 0x0A, 0x30, 0xA0, 0x00, 50 | 0x10, 0x38, 0x80, 0x2A, 51 | 0x37, 0xA0, 0x03, 0x87, 52 | 0x80, 0x2C, 0x37, 0x80, 53 | 0x03, 0xCF, 0x80, 0x04, 54 | 0x1F, 0x80, 0x01, 0x1C, 55 | 0x19, 0x80, 0x2F, 0x17, 56 | 0x80, 0x2A, 0x36, 0xA0, 57 | 0x00, 0x10, 0x38, 0x80, 58 | 0x2A, 0x37, 0xA0, 0x03, 59 | 0x8F, 0x80, 0x2C, 0x37, 60 | 0x80, 0x03, 0xCF, 0x80, 61 | 0x05, 0x1F, 0x80, 0x01, 62 | 0x1C, 0x19, 0x80, 0x2F, 63 | 0x17, 0x80, 0x2A, 0x36, 64 | 0xA0, 0x00, 0x08, 0x39, 65 | 0x80, 0x2A, 0x37, 0x80, 66 | 0x28, 0x36, 0xA0, 0x00, 67 | 0x08, 0x39, 0x80, 0x28, 68 | 0x37, 0xA0, 0x03, 0x97, 69 | 0x80, 0x2C, 0x37, 0x80, 70 | 0x03, 0xCF, 0x80, 0x06, 71 | 0x1F, 0x80, 0x01, 0x1C, 72 | 0x19, 0x80, 0x2F, 0x17, 73 | 0x80, 0x28, 0x36, 0xA0, 74 | 0x00, 0x10, 0x38, 0x80, 75 | 0x28, 0x37, 0xA0, 0x03, 76 | 0x9F, 0x80, 0x2C, 0x37, 77 | 0x80, 0x03, 0xCF, 0x80, 78 | 0x07, 0x1F, 0x80, 0x01, 79 | 0x1C, 0x19, 0x80, 0x2F, 80 | 0x17, 0x80, 0x28, 0x36, 81 | 0xA0, 0x00, 0x08, 0x39, 82 | 0x80, 0x28, 0x37, 0xA0, 83 | 0x03, 0x7F, 0x80, 0x2C, 84 | 0x37, 0xA0, 0x03, 0x2F, 85 | 0x17, 0x80, 0x02, 0x30, 86 | 0xA0, 0x00, 0x09, 0x38, 87 | 0x80, 0x2A, 0x37, 0x80, 88 | 0x00, 0x30, 0xA0, 0x00, 89 | 0x09, 0x39, 0x80, 0x28, 90 | 0x37, 0xA0, 0x03, 0xA7, 91 | 0x80, 0x2C, 0x37, 0x80, 92 | 0x03, 0xCF, 0x80, 0x03, 93 | 0x1F, 0x80, 0x01, 0x1C, 94 | 0x19, 0x80, 0x2F, 0x17, 95 | 0x80, 0x00, 0x30, 0xA0, 96 | 0x00, 0x04, 0x38, 0x80, 97 | 0x28, 0x37, 0xA0, 0x03, 98 | 0xA7, 0x80, 0x2C, 0x37, 99 | 0x80, 0x03, 0xCF, 0x80, 100 | 0x02, 0x1F, 0x80, 0x01, 101 | 0x1C, 0x19, 0x80, 0x2F, 102 | 0x17, 0x80, 0x02, 0x30, 103 | 0x80, 0x2A, 0x37, 0x80, 104 | 0x00, 0x30, 0xA0, 0x00, 105 | 0x18, 0x38, 0x80, 0x28, 106 | 0x37, 0xA0, 0x03, 0xAF, 107 | 0x80, 0x2C, 0x37, 0x80, 108 | 0x03, 0xCF, 0x80, 0x01, 109 | 0x1F, 0x80, 0x01, 0x1C, 110 | 0x19, 0x80, 0x2F, 0x17, 111 | 0x80, 0x2A, 0x36, 0xA0, 112 | 0x00, 0x0A, 0x38, 0x80, 113 | 0x2A, 0x37, 0xA0, 0x04, 114 | 0x0F, 0x80, 0x2C, 0x37, 115 | 0xA0, 0x03, 0x2F, 0x17, 116 | 0x80, 0x02, 0x30, 0x80, 117 | 0x2A, 0x37, 0x80, 0x00, 118 | 0x30, 0xA0, 0x00, 0x24, 119 | 0x38, 0x80, 0x28, 0x37, 120 | 0xA0, 0x03, 0xAF, 0x80, 121 | 0x2C, 0x37, 0x80, 0x03, 122 | 0x4F, 0x80, 0x01, 0x1C, 123 | 0x19, 0x80, 0x2F, 0x17, 124 | 0x80, 0x2A, 0x36, 0xA0, 125 | 0x00, 0x0A, 0x38, 0x80, 126 | 0x2A, 0x37, 0xA0, 0x04, 127 | 0x07, 0x80, 0x2C, 0x37, 128 | 0xA0, 0x03, 0x2F, 0x17, 129 | 0x80, 0x00, 0x30, 0xA0, 130 | 0x00, 0x10, 0x39, 0x80, 131 | 0x28, 0x37, 0x80, 0x02, 132 | 0x30, 0xA0, 0x00, 0x10, 133 | 0x39, 0x80, 0x2A, 0x37, 134 | 0xA0, 0x01, 0x26, 0x17, 135 | 0x80, 0x82, 0x36, 0x60, 136 | 0x00, 0x05, 0xA0, 0x00, 137 | 0x26, 0x17, 0x6C, 0x04, 138 | 0x60, 0x00, 0x00, 0x06, 139 | 0x80, 0x04, 0x1F, 0x60, 140 | 0x00, 0x00, 0x80, 0x00, 141 | 0x04, 0x80, 0x0F, 0x1C, 142 | 0x80, 0x30, 0x3F, 0xA0, 143 | 0x03, 0xB7, 0x38, 0x80, 144 | 0x2C, 0x37, 0xA0, 0x03, 145 | 0x2F, 0x17, 0x6C, 0x0F, 146 | 0x26, 0x80, 0x3C, 0x33, 147 | 0x80, 0x2B, 0x33, 0x26, 148 | 0x80, 0x49, 0x33, 0x80, 149 | 0x0F, 0x33, 0x26, 0x80, 150 | 0x31, 0x33, 0x80, 0x13, 151 | 0x33, 0x26, 0x80, 0x31, 152 | 0x33, 0x80, 0x05, 0x33, 153 | 0xA0, 0x00, 0x00, 0x21, 154 | 0xA0, 0x00, 0x00, 0x26, 155 | 0x80, 0x28, 0x37, 0xA0, 156 | 0x00, 0x00, 0x80, 0x2A, 157 | 0x37, 0xCF, 0x80, 0x2E, 158 | 0x97, 0xA0, 0x00, 0x00, 159 | 0x80, 0x2A, 0x37, 0x17, 160 | 0x21, 0xAA, 0x20, 0xFF, 161 | 0xE6, 0x22, 0x22, 0xA0, 162 | 0x00, 0x00, 0xA0, 0x00, 163 | 0x00, 0x26, 0x80, 0x2A, 164 | 0x37, 0xA0, 0x00, 0x00, 165 | 0x80, 0x28, 0x37, 0xCF, 166 | 0x80, 0x2E, 0x97, 0xA0, 167 | 0x00, 0x00, 0x80, 0x28, 168 | 0x37, 0x17, 0x21, 0xAA, 169 | 0x20, 0xFF, 0xE6, 0x22, 170 | 0x22, 0x42, 0x6C, 0xFF, 171 | 0xFF, 0xFF, 0xFF, 0xFF, 172 | 0xFF, 0xFF, 0xFF, 0x7E, 173 | 0xFF, 0xE7, 0xC3, 0xFF, 174 | 0xFF, 0xFF, 0xFF, 0xFF, 175 | 0xFF, 0xFF, 0xFF, 0xC3, 176 | 0xE7, 0xFF, 0x7E, 0x7F, 177 | 0xFF, 0xEF, 0xCF, 0xCF, 178 | 0xEF, 0xFF, 0x7F, 0xFE, 179 | 0xFF, 0xF7, 0xF3, 0xF3, 180 | 0xF7, 0xFF, 0xFE, 0x00, 181 | 0x00, 0x7E, 0xFF, 0xFF, 182 | 0x7E, 0x00, 0x00, 0x3C, 183 | 0x7E, 0xFF, 0xFF, 0xFF, 184 | 0xFF, 0x7E, 0x3C, 0x00, 185 | 0x7C, 0x82, 0x82, 0x82, 186 | 0x82, 0x82, 0x7C, 0x00, 187 | 0x30, 0x10, 0x10, 0x10, 188 | 0x10, 0x10, 0x10, 0x00, 189 | 0x7C, 0x82, 0x02, 0x7C, 190 | 0x80, 0x80, 0xFE, 0x00, 191 | 0x7C, 0x82, 0x02, 0x1C, 192 | 0x02, 0x82, 0x7C, 0x00, 193 | 0x0C, 0x14, 0x24, 0x44, 194 | 0x84, 0xFE, 0x04, 0x00, 195 | 0xFE, 0x80, 0x80, 0x7C, 196 | 0x02, 0x82, 0x7C, 0x00, 197 | 0x7C, 0x82, 0x80, 0xFC, 198 | 0x82, 0x82, 0x7C, 0x00, 199 | 0xFE, 0x02, 0x02, 0x04, 200 | 0x08, 0x10, 0x10, 0x00, 201 | 0x7C, 0x82, 0x82, 0x7C, 202 | 0x82, 0x82, 0x7C, 0x00, 203 | 0x7C, 0x82, 0x82, 0x7E, 204 | 0x02, 0x82, 0x7C, 0x00, 205 | 0x7C, 0x82, 0x02, 0x7E, 206 | 0x82, 0x82, 0x7E, 0x00, 207 | 0xFC, 0x82, 0x82, 0xFC, 208 | 0x82, 0x82, 0xFC, 0x00, 209 | 0x7C, 0x82, 0x80, 0x80, 210 | 0x80, 0x82, 0x7C, 0x00, 211 | 0xFC, 0x82, 0x82, 0x82, 212 | 0x82, 0x82, 0xFC, 0x00, 213 | 0xFE, 0x80, 0x80, 0xFE, 214 | 0x80, 0x80, 0xFE, 0x00, 215 | 0xFE, 0x80, 0x80, 0xF0, 216 | 0x80, 0x80, 0x80, 0x00, 217 | }; 218 | 219 | static uint32_t rdaddr; 220 | rdaddr = (uint32_t)(read_address); 221 | 222 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 223 | rdaddr, // read address 224 | 0, // write value 225 | 0 // write enable 226 | ); 227 | 228 | return rdata; 229 | } 230 | -------------------------------------------------------------------------------- /roms/cube3d.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | /* CUBE3D (assembly) 5 | ( Cube3d: Just a cube, y'know ) 6 | 7 | |00 @System &vector $2 &wst $1 &rst $1 &eaddr $2 &ecode $1 &pad $1 &r $2 &g $2 &b $2 &debug $1 &halt $1 8 | |20 @Screen &vector $2 &width $2 &height $2 &auto $1 &pad $1 &x $2 &y $2 &addr $2 &pixel $1 &sprite $1 9 | 10 | |0000 11 | 12 | @timer $1 13 | @cube &v0 $8 &v4 $8 14 | @center &x $2 &y $2 15 | 16 | |0100 17 | 18 | @on-reset ( -> ) 19 | ( | theme ) 20 | #4fcd .System/r DEO2 21 | #4fc3 .System/g DEO2 22 | #dfc2 .System/b DEO2 23 | ( | center ) 24 | .Screen/width DEI2 #01 SFT2 #0040 SUB2 .center/x STZ2 25 | .Screen/height DEI2 #01 SFT2 #0040 SUB2 .center/y STZ2 26 | ( | begin. ) 27 | ;on-frame .Screen/vector DEO2 28 | 29 | @on-frame ( -> ) 30 | ( | clear ) 31 | #0000 DUP2 .Screen/x DEO2 32 | .Screen/y DEO2 33 | #80 .Screen/pixel DEO 34 | ( | draw ) 35 | .timer LDZk INC SWP STZ 36 | 37 | BRK 38 | 39 | @ ( frame -- ) 40 | ( | create box ) 41 | #0800 42 | &loop ( -- ) 43 | STHk #00 .timer LDZ #00 STHkr INC #07 AND #60 SFT ADD2 #00ff AND2 ;table ADD2 LDA #01 SFT #00 .timer LDZ #00 STHkr #60 SFT ADD2 #00ff AND2 ;table ADD2 LDA #02 SFT #00 STHkr #62 SFT2 ADD2 .cube/v0 STHr DUP ADD ADD STZ2 44 | INC GTHk ?&loop 45 | POP2 46 | ( | vertices ) 47 | #0800 48 | &ver-loop ( -- ) 49 | DUP DUP ADD .cube ADD LDZ2 50 | INC GTHk ?&ver-loop 51 | POP2 52 | ( lines ) #0400 53 | &line-loop ( -- ) 54 | STHk .cube/v0 STHkr DUP ADD ADD .cube/v0 STHkr INC #03 AND DUP ADD ADD 55 | .cube/v0 STHkr DUP ADD ADD .cube/v4 STHkr DUP ADD ADD 56 | .cube/v4 STHkr DUP ADD ADD .cube/v4 STHr INC #03 AND DUP ADD ADD 57 | INC GTHk ?&line-loop 58 | POP2 JMP2r 59 | 60 | @ ( a b -- ) 61 | STH STH 62 | ( ) #00 STHkr LDZ .center/x LDZ2 ADD2 63 | ( ) #00 STHr INC LDZ .center/y LDZ2 ADD2 64 | ( ) #00 STHkr LDZ .center/x LDZ2 ADD2 65 | ( ) #00 STHr INC LDZ .center/y LDZ2 ADD2 #05 66 | JMP2r 67 | 68 | @ ( x y -- ) 69 | #00 SWP #0004 SUB2 .center/y LDZ2 ADD2 .Screen/y DEO2 70 | #00 SWP #0003 SUB2 .center/x LDZ2 ADD2 .Screen/x DEO2 71 | ;&icn .Screen/addr DEO2 72 | #05 .Screen/sprite DEO 73 | JMP2r 74 | &icn [ 0000 387c 7c7c 3800 ] 75 | 76 | @ ( x1* y1* x2* y2* color -- ) 77 | ,&color STR 78 | ,&y STR2 79 | ,&x STR2 80 | ,&y2 STR2 81 | ,&x2 STR2 82 | ,&x LDR2 ,&x2 LDR2 SUB2 abs2 ,&dx STR2 83 | #0000 ,&y LDR2 ,&y2 LDR2 SUB2 abs2 SUB2 ,&dy STR2 84 | #ffff [ LIT2 00 _&x2 ] LDR2 ,&x LDR2 lts2 DUP2 ADD2 ADD2 ,&sx STR2 85 | #ffff [ LIT2 00 _&y2 ] LDR2 ,&y LDR2 lts2 DUP2 ADD2 ADD2 ,&sy STR2 86 | [ LIT2 &dx $2 ] [ LIT2 &dy $2 ] ADD2 STH2 87 | &while ( -- ) 88 | [ LIT2 &x2 $2 ] DUP2 .Screen/x DEO2 89 | [ LIT2 &x $2 ] EQU2 [ LIT2 &y2 $2 ] DUP2 .Screen/y DEO2 90 | [ LIT2 &y $2 ] EQU2 [ LIT2 &color $1 -Screen/pixel ] DEO 91 | AND ?&end 92 | STH2kr DUP2 ADD2 DUP2 ,&dy LDR2 lts2 ?&skipy 93 | STH2r ,&dy LDR2 ADD2 STH2 ,&x2 LDR2 [ LIT2 &sx $2 ] ADD2 ,&x2 STR2 94 | &skipy ( -- ) 95 | ,&dx LDR2 gts2 ?&while 96 | STH2r ,&dx LDR2 ADD2 STH2 ,&y2 LDR2 [ LIT2 &sy $2 ] ADD2 ,&y2 STR2 97 | !&while 98 | &end POP2r JMP2r 99 | 100 | @abs2 ( a* -- f ) 101 | DUP2 #0f SFT2 EQU ?{ #0000 SWP2 SUB2 } 102 | JMP2r 103 | 104 | @lts2 ( a* b* -- f ) 105 | #8000 STH2k ADD2 SWP2 STH2r ADD2 GTH2 JMP2r 106 | 107 | @gts2 ( a* b* -- f ) 108 | #8000 STH2k ADD2 SWP2 STH2r ADD2 LTH2 JMP2r 109 | 110 | @table ( 256 xy ) 111 | [ 112 | f7f8 f9fa fbfc fcfd fefe ffff ffff ffff 113 | ffff ffff fffe fefd fcfc fbfa f9f8 f7f6 114 | f5f3 f2f0 efed ecea e8e6 e4e2 e0de dcda 115 | d8d5 d3d1 cecc c9c7 c4c1 bfbc b9b6 b3b0 116 | aeab a8a5 a29f 9c98 9592 8f8c 8986 8380 117 | 7c79 7673 706d 6a67 6360 5d5a 5754 514f 118 | 4c49 4643 403e 3b38 3633 312e 2c2a 2725 119 | 2321 1f1d 1b19 1715 1312 100f 0d0c 0a09 120 | 0807 0605 0403 0302 0101 0000 0000 0000 121 | 0000 0000 0001 0102 0303 0405 0607 0809 122 | 0a0c 0d0f 1012 1315 1719 1b1d 1f21 2325 123 | 272a 2c2e 3133 3638 3b3e 4043 4649 4c4f 124 | 5154 575a 5d60 6367 6a6d 7073 7679 7c7f 125 | 8386 898c 8f92 9598 9c9f a2a5 a8ab aeb0 126 | b3b6 b9bc bfc1 c4c7 c9cc ced1 d3d5 d8da 127 | dcde e0e2 e4e6 e8ea eced eff0 f2f3 f5f6 ] 128 | */ 129 | 130 | #define ROM_SIZE 1024 131 | 132 | uint8_t read_rom_byte(uint16_t read_address) 133 | { 134 | static uint8_t uxn_rom[ROM_SIZE] = { 135 | 0xA0, 0x4F, 0xCD, 0x80, 0x08, 0x37, 0xA0, 0x4F, 136 | 0xC3, 0x80, 0x0A, 0x37, 0xA0, 0xDF, 0xC2, 0x80, 137 | 0x0C, 0x37, 0x80, 0x22, 0x36, 0x80, 0x01, 0x3F, 138 | 0xA0, 0x00, 0x40, 0x39, 0x80, 0x11, 0x31, 0x80, 139 | 0x24, 0x36, 0x80, 0x01, 0x3F, 0xA0, 0x00, 0x40, 140 | 0x39, 0x80, 0x13, 0x31, 0xA0, 0x01, 0x32, 0x80, 141 | 0x20, 0x37, 0xA0, 0x00, 0x00, 0x26, 0x80, 0x28, 142 | 0x37, 0x80, 0x2A, 0x37, 0x80, 0x80, 0x80, 0x2E, 143 | 0x17, 0x80, 0x00, 0x90, 0x01, 0x04, 0x11, 0x60, 144 | 0x00, 0x01, 0x00, 0xA0, 0x08, 0x00, 0x8F, 0x80, 145 | 0x00, 0x80, 0x00, 0x10, 0x80, 0x00, 0xCF, 0x01, 146 | 0x80, 0x07, 0x1C, 0x80, 0x60, 0x1F, 0x38, 0xA0, 147 | 0x00, 0xFF, 0x3C, 0xA0, 0x03, 0x1A, 0x38, 0x14, 148 | 0x80, 0x01, 0x1F, 0x80, 0x00, 0x80, 0x00, 0x10, 149 | 0x80, 0x00, 0xCF, 0x80, 0x60, 0x1F, 0x38, 0xA0, 150 | 0x00, 0xFF, 0x3C, 0xA0, 0x03, 0x1A, 0x38, 0x14, 151 | 0x80, 0x02, 0x1F, 0x80, 0x00, 0xCF, 0x80, 0x62, 152 | 0x3F, 0x38, 0x80, 0x01, 0x4F, 0x06, 0x18, 0x18, 153 | 0x31, 0x01, 0x8A, 0x20, 0xFF, 0xB8, 0x22, 0xA0, 154 | 0x08, 0x00, 0x06, 0x06, 0x18, 0x80, 0x01, 0x18, 155 | 0x30, 0x60, 0x00, 0x70, 0x01, 0x8A, 0x20, 0xFF, 156 | 0xF1, 0x22, 0xA0, 0x04, 0x00, 0x8F, 0x80, 0x01, 157 | 0xCF, 0x06, 0x18, 0x18, 0x80, 0x01, 0xCF, 0x01, 158 | 0x80, 0x03, 0x1C, 0x06, 0x18, 0x18, 0x60, 0x00, 159 | 0x29, 0x80, 0x01, 0xCF, 0x06, 0x18, 0x18, 0x80, 160 | 0x09, 0xCF, 0x06, 0x18, 0x18, 0x60, 0x00, 0x1A, 161 | 0x80, 0x09, 0xCF, 0x06, 0x18, 0x18, 0x80, 0x09, 162 | 0x4F, 0x01, 0x80, 0x03, 0x1C, 0x06, 0x18, 0x18, 163 | 0x60, 0x00, 0x07, 0x01, 0x8A, 0x20, 0xFF, 0xC5, 164 | 0x22, 0x6C, 0x0F, 0x0F, 0x80, 0x00, 0xCF, 0x10, 165 | 0x80, 0x11, 0x30, 0x38, 0x80, 0x00, 0x4F, 0x01, 166 | 0x10, 0x80, 0x13, 0x30, 0x38, 0x80, 0x00, 0xCF, 167 | 0x10, 0x80, 0x11, 0x30, 0x38, 0x80, 0x00, 0x4F, 168 | 0x01, 0x10, 0x80, 0x13, 0x30, 0x38, 0x80, 0x05, 169 | 0x60, 0x00, 0x31, 0x6C, 0x80, 0x00, 0x04, 0xA0, 170 | 0x00, 0x04, 0x39, 0x80, 0x13, 0x30, 0x38, 0x80, 171 | 0x2A, 0x37, 0x80, 0x00, 0x04, 0xA0, 0x00, 0x03, 172 | 0x39, 0x80, 0x11, 0x30, 0x38, 0x80, 0x28, 0x37, 173 | 0xA0, 0x02, 0x3C, 0x80, 0x2C, 0x37, 0x80, 0x05, 174 | 0x80, 0x2F, 0x17, 0x6C, 0x00, 0x00, 0x38, 0x7C, 175 | 0x7C, 0x7C, 0x38, 0x00, 0x80, 0x6F, 0x13, 0x80, 176 | 0x68, 0x33, 0x80, 0x5A, 0x33, 0x80, 0x5B, 0x33, 177 | 0x80, 0x4D, 0x33, 0x80, 0x51, 0x32, 0x80, 0x47, 178 | 0x32, 0x39, 0x60, 0x00, 0x9B, 0x80, 0x38, 0x33, 179 | 0xA0, 0x00, 0x00, 0x80, 0x4C, 0x32, 0x80, 0x42, 180 | 0x32, 0x39, 0x60, 0x00, 0x8B, 0x39, 0x80, 0x2A, 181 | 0x33, 0xA0, 0xFF, 0xFF, 0xA0, 0x00, 0x28, 0x32, 182 | 0x80, 0x2C, 0x32, 0x60, 0x00, 0x88, 0x26, 0x38, 183 | 0x38, 0x80, 0x50, 0x33, 0xA0, 0xFF, 0xFF, 0xA0, 184 | 0x00, 0x20, 0x32, 0x80, 0x24, 0x32, 0x60, 0x00, 185 | 0x75, 0x26, 0x38, 0x38, 0x80, 0x56, 0x33, 0xA0, 186 | 0x00, 0x00, 0xA0, 0x00, 0x00, 0x38, 0x2F, 0xA0, 187 | 0x00, 0x00, 0x26, 0x80, 0x28, 0x37, 0xA0, 0x00, 188 | 0x00, 0x28, 0xA0, 0x00, 0x00, 0x26, 0x80, 0x2A, 189 | 0x37, 0xA0, 0x00, 0x00, 0x28, 0xA0, 0x00, 0x2E, 190 | 0x17, 0x1C, 0x20, 0x00, 0x39, 0xEF, 0x26, 0x38, 191 | 0x26, 0x80, 0xD7, 0x32, 0x60, 0x00, 0x3F, 0x20, 192 | 0x00, 0x10, 0x6F, 0x80, 0xCD, 0x32, 0x38, 0x2F, 193 | 0x80, 0xCD, 0x32, 0xA0, 0x00, 0x00, 0x38, 0x80, 194 | 0xC6, 0x33, 0x80, 0xBB, 0x32, 0x60, 0x00, 0x30, 195 | 0x20, 0xFF, 0xBC, 0x6F, 0x80, 0xB1, 0x32, 0x38, 196 | 0x2F, 0x80, 0xBF, 0x32, 0xA0, 0x00, 0x00, 0x38, 197 | 0x80, 0xB8, 0x33, 0x40, 0xFF, 0xA9, 0x62, 0x6C, 198 | 0x26, 0x80, 0x0F, 0x3F, 0x08, 0x20, 0x00, 0x05, 199 | 0xA0, 0x00, 0x00, 0x24, 0x39, 0x6C, 0xA0, 0x80, 200 | 0x00, 0xAF, 0x38, 0x24, 0x6F, 0x38, 0x2A, 0x6C, 201 | 0xA0, 0x80, 0x00, 0xAF, 0x38, 0x24, 0x6F, 0x38, 202 | 0x2B, 0x6C, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 203 | 0xFC, 0xFD, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 204 | 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 205 | 0xFE, 0xFD, 0xFC, 0xFC, 0xFB, 0xFA, 0xF9, 0xF8, 206 | 0xF7, 0xF6, 0xF5, 0xF3, 0xF2, 0xF0, 0xEF, 0xED, 207 | 0xEC, 0xEA, 0xE8, 0xE6, 0xE4, 0xE2, 0xE0, 0xDE, 208 | 0xDC, 0xDA, 0xD8, 0xD5, 0xD3, 0xD1, 0xCE, 0xCC, 209 | 0xC9, 0xC7, 0xC4, 0xC1, 0xBF, 0xBC, 0xB9, 0xB6, 210 | 0xB3, 0xB0, 0xAE, 0xAB, 0xA8, 0xA5, 0xA2, 0x9F, 211 | 0x9C, 0x98, 0x95, 0x92, 0x8F, 0x8C, 0x89, 0x86, 212 | 0x83, 0x80, 0x7C, 0x79, 0x76, 0x73, 0x70, 0x6D, 213 | 0x6A, 0x67, 0x63, 0x60, 0x5D, 0x5A, 0x57, 0x54, 214 | 0x51, 0x4F, 0x4C, 0x49, 0x46, 0x43, 0x40, 0x3E, 215 | 0x3B, 0x38, 0x36, 0x33, 0x31, 0x2E, 0x2C, 0x2A, 216 | 0x27, 0x25, 0x23, 0x21, 0x1F, 0x1D, 0x1B, 0x19, 217 | 0x17, 0x15, 0x13, 0x12, 0x10, 0x0F, 0x0D, 0x0C, 218 | 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 219 | 0x03, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 220 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 221 | 0x01, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07, 222 | 0x08, 0x09, 0x0A, 0x0C, 0x0D, 0x0F, 0x10, 0x12, 223 | 0x13, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F, 0x21, 224 | 0x23, 0x25, 0x27, 0x2A, 0x2C, 0x2E, 0x31, 0x33, 225 | 0x36, 0x38, 0x3B, 0x3E, 0x40, 0x43, 0x46, 0x49, 226 | 0x4C, 0x4F, 0x51, 0x54, 0x57, 0x5A, 0x5D, 0x60, 227 | 0x63, 0x67, 0x6A, 0x6D, 0x70, 0x73, 0x76, 0x79, 228 | 0x7C, 0x7F, 0x83, 0x86, 0x89, 0x8C, 0x8F, 0x92, 229 | 0x95, 0x98, 0x9C, 0x9F, 0xA2, 0xA5, 0xA8, 0xAB, 230 | 0xAE, 0xB0, 0xB3, 0xB6, 0xB9, 0xBC, 0xBF, 0xC1, 231 | 0xC4, 0xC7, 0xC9, 0xCC, 0xCE, 0xD1, 0xD3, 0xD5, 232 | 0xD8, 0xDA, 0xDC, 0xDE, 0xE0, 0xE2, 0xE4, 0xE6, 233 | 0xE8, 0xEA, 0xEC, 0xED, 0xEF, 0xF0, 0xF2, 0xF3, 234 | 0xF5, 0xF6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 235 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 236 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 237 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 238 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 239 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 240 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 241 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 242 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 243 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 244 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 245 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 246 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 247 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 248 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 249 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 250 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 251 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 252 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 253 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 254 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 255 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 256 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 257 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 258 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 259 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 260 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 261 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 262 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 263 | }; 264 | 265 | static uint32_t rdaddr; 266 | rdaddr = (uint32_t)(read_address); 267 | 268 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 269 | rdaddr, // read address 270 | 0, // write value 271 | 0 // write enable 272 | ); 273 | 274 | return rdata; 275 | } -------------------------------------------------------------------------------- /roms/fill_test.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | /* Fill Drawing test (assembly) 5 | |0100 6 | LIT2r 0000 main_ POP2r BRK 7 | ( bss ) 8 | ( data ) 9 | ( text ) 10 | 11 | @main_ ( -- result* ) 12 | OVR2r #2ce9 #08 DEO2 #01c0 #0a DEO2 #7ce5 #0c DEO2 #0190 #22 DEO2 #0168 #24 DEO2 #0000 #28 DEO2 #0000 #2a DEO2 #802e DEO #0014 #28 DEO2 #0014 #2a DEO2 #812e DEO #0028 #28 DEO2 #0028 #2a DEO2 #822e DEO #003c #28 DEO2 #003c #2a DEO2 #832e DEO #0050 #28 DEO2 #0050 #2a DEO2 #802e DEO #0064 #28 DEO2 #0064 #2a DEO2 #812e DEO #0078 #28 DEO2 #0078 #2a DEO2 #822e DEO #008c #28 DEO2 #008c #2a DEO2 #832e DEO #00a0 #28 DEO2 #00a0 #2a DEO2 #b02e DEO #008c #28 DEO2 #008c #2a DEO2 #b32e DEO #0078 #28 DEO2 #0078 #2a DEO2 #b22e DEO #0064 #28 DEO2 #0064 #2a DEO2 #b12e DEO #0050 #28 DEO2 #0050 #2a DEO2 #b02e DEO #003c #28 DEO2 #003c #2a DEO2 #b32e DEO #0028 #28 DEO2 #0028 #2a DEO2 #b22e DEO #0014 #28 DEO2 #0014 #2a DEO2 #b12e DEO #0000 13 | 14 | &return 15 | POP2r JMP2r 16 | */ 17 | 18 | /* Fill Drawing Test (chibicc) 19 | #include 20 | 21 | void main() { 22 | set_palette(0x2ce9, 0x01c0, 0x7ce5); 23 | set_screen_size(400, 360); 24 | set_screen_xy(0, 0); 25 | draw_pixel(BgFillBR | 0x00); 26 | set_screen_xy(20, 20); 27 | draw_pixel(BgFillBR | 0x01); 28 | set_screen_xy(40, 40); 29 | draw_pixel(BgFillBR | 0x02); 30 | set_screen_xy(60, 60); 31 | draw_pixel(BgFillBR | 0x03); 32 | set_screen_xy(80, 80); 33 | draw_pixel(BgFillBR | 0x00); 34 | set_screen_xy(100, 100); 35 | draw_pixel(BgFillBR | 0x01); 36 | set_screen_xy(120, 120); 37 | draw_pixel(BgFillBR | 0x02); 38 | set_screen_xy(140, 140); 39 | draw_pixel(BgFillBR | 0x03); 40 | 41 | set_screen_xy(160, 160); 42 | draw_pixel(BgFillTL | 0x00); 43 | set_screen_xy(140, 140); 44 | draw_pixel(BgFillTL | 0x03); 45 | set_screen_xy(120, 120); 46 | draw_pixel(BgFillTL | 0x02); 47 | set_screen_xy(100, 100); 48 | draw_pixel(BgFillTL | 0x01); 49 | set_screen_xy(80, 80); 50 | draw_pixel(BgFillTL | 0x00); 51 | set_screen_xy(60, 60); 52 | draw_pixel(BgFillTL | 0x03); 53 | set_screen_xy(40, 40); 54 | draw_pixel(BgFillTL | 0x02); 55 | set_screen_xy(20, 20); 56 | draw_pixel(BgFillTL | 0x01); 57 | } 58 | */ 59 | #define ROM_SIZE 512 60 | 61 | uint8_t read_rom_byte(uint16_t read_address) 62 | { 63 | static uint8_t uxn_rom[ROM_SIZE] = { 64 | 0xE0, 0x00, 0x00, 0x60, 0x00, 0x02, 0x62, 0x00, 65 | 0x67, 0xA0, 0x2C, 0xE9, 0x80, 0x08, 0x37, 0xA0, 66 | 0x01, 0xC0, 0x80, 0x0A, 0x37, 0xA0, 0x7C, 0xE5, 67 | 0x80, 0x0C, 0x37, 0xA0, 0x01, 0x90, 0x80, 0x22, 68 | 0x37, 0xA0, 0x01, 0x68, 0x80, 0x24, 0x37, 0xA0, 69 | 0x00, 0x00, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x00, 70 | 0x80, 0x2A, 0x37, 0xA0, 0x80, 0x2E, 0x17, 0xA0, 71 | 0x00, 0x14, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x14, 72 | 0x80, 0x2A, 0x37, 0xA0, 0x81, 0x2E, 0x17, 0xA0, 73 | 0x00, 0x28, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x28, 74 | 0x80, 0x2A, 0x37, 0xA0, 0x82, 0x2E, 0x17, 0xA0, 75 | 0x00, 0x3C, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x3C, 76 | 0x80, 0x2A, 0x37, 0xA0, 0x83, 0x2E, 0x17, 0xA0, 77 | 0x00, 0x50, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x50, 78 | 0x80, 0x2A, 0x37, 0xA0, 0x80, 0x2E, 0x17, 0xA0, 79 | 0x00, 0x64, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x64, 80 | 0x80, 0x2A, 0x37, 0xA0, 0x81, 0x2E, 0x17, 0xA0, 81 | 0x00, 0x78, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x78, 82 | 0x80, 0x2A, 0x37, 0xA0, 0x82, 0x2E, 0x17, 0xA0, 83 | 0x00, 0x8C, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x8C, 84 | 0x80, 0x2A, 0x37, 0xA0, 0x83, 0x2E, 0x17, 0xA0, 85 | 0x00, 0xA0, 0x80, 0x28, 0x37, 0xA0, 0x00, 0xA0, 86 | 0x80, 0x2A, 0x37, 0xA0, 0xB0, 0x2E, 0x17, 0xA0, 87 | 0x00, 0x8C, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x8C, 88 | 0x80, 0x2A, 0x37, 0xA0, 0xB3, 0x2E, 0x17, 0xA0, 89 | 0x00, 0x78, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x78, 90 | 0x80, 0x2A, 0x37, 0xA0, 0xB2, 0x2E, 0x17, 0xA0, 91 | 0x00, 0x64, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x64, 92 | 0x80, 0x2A, 0x37, 0xA0, 0xB1, 0x2E, 0x17, 0xA0, 93 | 0x00, 0x50, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x50, 94 | 0x80, 0x2A, 0x37, 0xA0, 0xB0, 0x2E, 0x17, 0xA0, 95 | 0x00, 0x3C, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x3C, 96 | 0x80, 0x2A, 0x37, 0xA0, 0xB3, 0x2E, 0x17, 0xA0, 97 | 0x00, 0x28, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x28, 98 | 0x80, 0x2A, 0x37, 0xA0, 0xB2, 0x2E, 0x17, 0xA0, 99 | 0x00, 0x14, 0x80, 0x28, 0x37, 0xA0, 0x00, 0x14, 100 | 0x80, 0x2A, 0x37, 0xA0, 0xB1, 0x2E, 0x17, 0xA0, 101 | 0x00, 0x00, 0x62, 0x6C, 0x00, 0x00, 0x00, 0x00, 102 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 103 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 104 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 105 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 106 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 107 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 108 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 109 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 110 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 111 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 112 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 113 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 114 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 115 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 116 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 117 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 118 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 119 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 120 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 121 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 122 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 123 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 124 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 125 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 126 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 127 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 128 | }; 129 | 130 | static uint32_t rdaddr; 131 | rdaddr = (uint32_t)(read_address); 132 | 133 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 134 | rdaddr, // read address 135 | 0, // write value 136 | 0 // write enable 137 | ); 138 | 139 | return rdata; 140 | } -------------------------------------------------------------------------------- /roms/mandelbrot_fast.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | #include 4 | 5 | /* Mandelbrot Fast (assembly) 6 | |0100 7 | LIT2r 0000 main_ POP2r BRK 8 | ( bss ) 9 | @tmp_ $2 10 | @yy_ $2 11 | @xx_ $2 12 | @i_ $2 13 | @y_ $2 14 | @x_ $2 15 | @y0_ $2 16 | @x0_ $2 17 | ( data ) 18 | ( text ) 19 | 20 | @main_ ( -- result* ) 21 | OVR2r #08df #08 DEO2 #12bf #0a DEO2 #549d #0c DEO2 #0190 #22 DEO2 #0168 #24 DEO2 #fee8 ;x0_ STA2 22 | 23 | &begin.1 24 | ;x0_ LDA2 #8000 EOR2 #8078 LTH2 #00 EQU ?&break.1 25 | #ff4c ;y0_ STA2 26 | 27 | &begin.2 28 | ;y0_ LDA2 #8000 EOR2 #8000 GTH2 #00 SWP #01 EOR #0000 EQU2 ?&break.2 29 | #0000 ;x_ STA2 30 | #0000 ;y_ STA2 31 | #0000 ;i_ STA2 32 | 33 | &begin.3 34 | ;i_ LDA2 #8000 EOR2 #8019 LTH2 #00 EQU ?&break.3 35 | #8400 ;x_ LDA2 ;x_ LDA2 mul_ 36 | ;xx_ STA2k 37 | POP2 ;y_ LDA2 ;y_ LDA2 mul_ 38 | ;yy_ STA2k 39 | POP2 ADD2 #8000 EOR2 LTH2 #00 EQU ?&end.4 40 | !&break.3 41 | 42 | &end.4 43 | ;xx_ LDA2 ;yy_ LDA2 SUB2 ;x0_ LDA2 #10 SFT2 ADD2 ;tmp_ STA2 44 | ;y_ LDA2 ;x_ LDA2 mul_ 45 | #10 SFT2 ;y0_ LDA2 #10 SFT2 ADD2 ;y_ STA2 46 | ;tmp_ LDA2 ;x_ STA2 47 | 48 | &continue.3 49 | ;i_ LDA2k INC2 SWP2 STA2 50 | !&begin.3 51 | 52 | &break.3 53 | ;i_ LDA2 ;x0_ LDA2 ;y0_ LDA2 ADD2 #0001 AND2 ADD2 #03 SFT2 ;tmp_ STA2 54 | ;x0_ LDA2 #0118 ADD2 #28 DEO2 ;y0_ LDA2 #00b4 ADD2 #2a DEO2 ;tmp_ LDA2 NIP #2e DEO #00b4 ;y0_ LDA2 SUB2 #2a DEO2 ;tmp_ LDA2 NIP #2e DEO 55 | 56 | &continue.2 57 | ;y0_ LDA2k INC2 SWP2 STA2 58 | !&begin.2 59 | 60 | &break.2 61 | 62 | &continue.1 63 | ;x0_ LDA2k INC2 SWP2 STA2 64 | !&begin.1 65 | 66 | &break.1 67 | #0000 68 | 69 | &return 70 | POP2r JMP2r 71 | ( Multiply two 8.8 fixed point numbers. ) 72 | @mul_ ( y* x* -> x-times-y* ) 73 | LIT2r 0001 74 | SWP2 DUP2 #8000 LTH2 ?&posx 75 | #0000 SWP2 SUB2 LIT2r ffff MUL2r &posx 76 | SWP2 DUP2 #8000 LTH2 ?&posy 77 | #0000 SWP2 SUB2 LIT2r ffff MUL2r &posy 78 | ( xx yy ) 79 | OVR2k OVR2k 80 | ( xx yy xx yy xx yy xx yy ) 81 | #00ff AND2 SWP2 #00ff AND2 MUL2 #08 SFT2 82 | ( xx yy xx yy xx yy AA ) 83 | ROT2 #08 SFT2 ROT2 #00ff AND2 MUL2 ADD2 84 | ( xx yy xx yy AA+BB ) 85 | ROT2 #00ff AND2 ROT2 #08 SFT2 MUL2 ADD2 86 | ( xx yy AA+BB+CC ) 87 | ROT2 #08 SFT2 ROT2 #08 SFT2 MUL2 #80 SFT2 ADD2 88 | ( AA+BB+CC+DD ) 89 | STH2r MUL2 90 | JMP2r 91 | 92 | */ 93 | 94 | /* 95 | #include 96 | 97 | void main(void) { 98 | set_palette(0x08df, 0x12bf, 0x549d); 99 | set_screen_size(400, 360); 100 | for (x0 = -280; x0 < 120; ++x0) { 101 | for (y0 = -180; y0 <= 0; ++y0) { 102 | x = 0; 103 | y = 0; 104 | for (i = 0; i < 25; ++i) { 105 | if ((xx = mul(x, x)) + (yy = mul(y, y)) > 4 * 256) 106 | break; 107 | tmp = xx - yy + x0 * 2; 108 | y = 2 * mul(x, y) + y0 * 2; 109 | x = tmp; 110 | } 111 | tmp = (unsigned)(i + (x0 + y0 & 1)) / 8; 112 | set_screen_xy(x0 + 280, y0 + 180); 113 | draw_pixel(tmp); 114 | set_screen_y(180 - y0); 115 | draw_pixel(tmp); 116 | } 117 | } 118 | } 119 | 120 | */ 121 | 122 | #define ROM_SIZE 512 123 | uint8_t read_rom_byte(uint16_t read_address) 124 | { 125 | static uint8_t uxn_rom[ROM_SIZE] = { 126 | 0xE0, 0x00, 0x00, 0x60, 0x00, 0x12, 0x62, 0x00, 127 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 128 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 129 | 0x67, 0xA0, 0x08, 0xDF, 0x80, 0x08, 0x37, 0xA0, 130 | 0x12, 0xBF, 0x80, 0x0A, 0x37, 0xA0, 0x54, 0x9D, 131 | 0x80, 0x0C, 0x37, 0xA0, 0x01, 0x90, 0x80, 0x22, 132 | 0x37, 0xA0, 0x01, 0x68, 0x80, 0x24, 0x37, 0xA0, 133 | 0xFE, 0xE8, 0xA0, 0x01, 0x16, 0x35, 0xA0, 0x01, 134 | 0x16, 0x34, 0xA0, 0x80, 0x00, 0x3E, 0xA0, 0x80, 135 | 0x78, 0x2B, 0x80, 0x00, 0x08, 0x20, 0x01, 0x18, 136 | 0xA0, 0xFF, 0x4C, 0xA0, 0x01, 0x14, 0x35, 0xA0, 137 | 0x01, 0x14, 0x34, 0xA0, 0x80, 0x00, 0x3E, 0xA0, 138 | 0x80, 0x00, 0x2A, 0x80, 0x00, 0x04, 0x80, 0x01, 139 | 0x1E, 0xA0, 0x00, 0x00, 0x28, 0x20, 0x00, 0xEE, 140 | 0xA0, 0x00, 0x00, 0xA0, 0x01, 0x12, 0x35, 0xA0, 141 | 0x00, 0x00, 0xA0, 0x01, 0x10, 0x35, 0xA0, 0x00, 142 | 0x00, 0xA0, 0x01, 0x0E, 0x35, 0xA0, 0x01, 0x0E, 143 | 0x34, 0xA0, 0x80, 0x00, 0x3E, 0xA0, 0x80, 0x19, 144 | 0x2B, 0x80, 0x00, 0x08, 0x20, 0x00, 0x73, 0xA0, 145 | 0x84, 0x00, 0xA0, 0x01, 0x12, 0x34, 0xA0, 0x01, 146 | 0x12, 0x34, 0x60, 0x00, 0xC8, 0xA0, 0x01, 0x0C, 147 | 0xB5, 0x22, 0xA0, 0x01, 0x10, 0x34, 0xA0, 0x01, 148 | 0x10, 0x34, 0x60, 0x00, 0xB8, 0xA0, 0x01, 0x0A, 149 | 0xB5, 0x22, 0x38, 0xA0, 0x80, 0x00, 0x3E, 0x2B, 150 | 0x80, 0x00, 0x08, 0x20, 0x00, 0x03, 0x40, 0x00, 151 | 0x41, 0xA0, 0x01, 0x0C, 0x34, 0xA0, 0x01, 0x0A, 152 | 0x34, 0x39, 0xA0, 0x01, 0x16, 0x34, 0x80, 0x10, 153 | 0x3F, 0x38, 0xA0, 0x01, 0x08, 0x35, 0xA0, 0x01, 154 | 0x10, 0x34, 0xA0, 0x01, 0x12, 0x34, 0x60, 0x00, 155 | 0x84, 0x80, 0x10, 0x3F, 0xA0, 0x01, 0x14, 0x34, 156 | 0x80, 0x10, 0x3F, 0x38, 0xA0, 0x01, 0x10, 0x35, 157 | 0xA0, 0x01, 0x08, 0x34, 0xA0, 0x01, 0x12, 0x35, 158 | 0xA0, 0x01, 0x0E, 0xB4, 0x21, 0x24, 0x35, 0x40, 159 | 0xFF, 0x7B, 0xA0, 0x01, 0x0E, 0x34, 0xA0, 0x01, 160 | 0x16, 0x34, 0xA0, 0x01, 0x14, 0x34, 0x38, 0xA0, 161 | 0x00, 0x01, 0x3C, 0x38, 0x80, 0x03, 0x3F, 0xA0, 162 | 0x01, 0x08, 0x35, 0xA0, 0x01, 0x16, 0x34, 0xA0, 163 | 0x01, 0x18, 0x38, 0x80, 0x28, 0x37, 0xA0, 0x01, 164 | 0x14, 0x34, 0xA0, 0x00, 0xB4, 0x38, 0x80, 0x2A, 165 | 0x37, 0xA0, 0x01, 0x08, 0x34, 0x03, 0x80, 0x2E, 166 | 0x17, 0xA0, 0x00, 0xB4, 0xA0, 0x01, 0x14, 0x34, 167 | 0x39, 0x80, 0x2A, 0x37, 0xA0, 0x01, 0x08, 0x34, 168 | 0x03, 0x80, 0x2E, 0x17, 0xA0, 0x01, 0x14, 0xB4, 169 | 0x21, 0x24, 0x35, 0x40, 0xFE, 0xF9, 0xA0, 0x01, 170 | 0x16, 0xB4, 0x21, 0x24, 0x35, 0x40, 0xFE, 0xD6, 171 | 0xA0, 0x00, 0x00, 0x62, 0x6C, 0xE0, 0x00, 0x01, 172 | 0x24, 0x26, 0xA0, 0x80, 0x00, 0x2B, 0x20, 0x00, 173 | 0x09, 0xA0, 0x00, 0x00, 0x24, 0x39, 0xE0, 0xFF, 174 | 0xFF, 0x7A, 0x24, 0x26, 0xA0, 0x80, 0x00, 0x2B, 175 | 0x20, 0x00, 0x09, 0xA0, 0x00, 0x00, 0x24, 0x39, 176 | 0xE0, 0xFF, 0xFF, 0x7A, 0xA7, 0xA7, 0xA0, 0x00, 177 | 0xFF, 0x3C, 0x24, 0xA0, 0x00, 0xFF, 0x3C, 0x3A, 178 | 0x80, 0x08, 0x3F, 0x25, 0x80, 0x08, 0x3F, 0x25, 179 | 0xA0, 0x00, 0xFF, 0x3C, 0x3A, 0x38, 0x25, 0xA0, 180 | 0x00, 0xFF, 0x3C, 0x25, 0x80, 0x08, 0x3F, 0x3A, 181 | 0x38, 0x25, 0x80, 0x08, 0x3F, 0x25, 0x80, 0x08, 182 | 0x3F, 0x3A, 0x80, 0x80, 0x3F, 0x38, 0x6F, 0x3A, 183 | 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 184 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 185 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 186 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 187 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 188 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 189 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 190 | }; 191 | 192 | static uint32_t rdaddr; 193 | rdaddr = (uint32_t)(read_address); 194 | 195 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 196 | rdaddr, // read address 197 | 0, // write value 198 | 0 // write enable 199 | ); 200 | 201 | return rdata; 202 | } -------------------------------------------------------------------------------- /roms/screen_blending.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | // Screen Blending Device Test 5 | 6 | #define ROM_SIZE 508 7 | 8 | uint8_t read_rom_byte(uint16_t read_address) 9 | { 10 | static uint8_t uxn_rom[ROM_SIZE] = { 11 | 0xA0, 0xF0, 0x7F, 0x80, 12 | 0x08, 0x37, 0xA0, 0xF0, 13 | 0xD6, 0x80, 0x0A, 0x37, 14 | 0xA0, 0xF0, 0xB2, 0x80, 15 | 0x0C, 0x37, 0xA0, 0x01, 16 | 0x00, 0x80, 0x22, 0x37, 17 | 0xA0, 0x01, 0x0C, 0x80, 18 | 0x24, 0x37, 0x80, 0x02, 19 | 0x60, 0x00, 0xD8, 0xA0, 20 | 0x00, 0x80, 0x80, 0x28, 21 | 0x37, 0xA0, 0x00, 0x00, 22 | 0x80, 0x2A, 0x37, 0x80, 23 | 0x03, 0x60, 0x00, 0xC7, 24 | 0xA0, 0x10, 0x00, 0x80, 25 | 0x00, 0x07, 0x80, 0x03, 26 | 0x1C, 0x80, 0x50, 0x3F, 27 | 0xA0, 0x00, 0x08, 0x38, 28 | 0x80, 0x28, 0x37, 0x80, 29 | 0x00, 0x07, 0x80, 0x02, 30 | 0x1F, 0x80, 0x50, 0x3F, 31 | 0xA0, 0x00, 0x08, 0x38, 32 | 0x80, 0x2A, 0x37, 0x06, 33 | 0x80, 0x80, 0x1D, 0x80, 34 | 0x0F, 0x1C, 0x60, 0x00, 35 | 0xB7, 0x01, 0x8A, 0x20, 36 | 0xFF, 0xD1, 0x22, 0xA0, 37 | 0x10, 0x00, 0x80, 0x00, 38 | 0x07, 0x80, 0x03, 0x1C, 39 | 0x80, 0x50, 0x3F, 0xA0, 40 | 0x00, 0x88, 0x38, 0x80, 41 | 0x28, 0x37, 0x80, 0x00, 42 | 0x07, 0x80, 0x02, 0x1F, 43 | 0x80, 0x50, 0x3F, 0xA0, 44 | 0x00, 0x08, 0x38, 0x80, 45 | 0x2A, 0x37, 0x06, 0x80, 46 | 0xC0, 0x1D, 0x80, 0x0F, 47 | 0x1C, 0x60, 0x00, 0x84, 48 | 0x01, 0x8A, 0x20, 0xFF, 49 | 0xD1, 0x22, 0xA0, 0x10, 50 | 0x00, 0x80, 0x00, 0x07, 51 | 0x80, 0x03, 0x1C, 0x80, 52 | 0x50, 0x3F, 0xA0, 0x00, 53 | 0x08, 0x38, 0x80, 0x28, 54 | 0x37, 0x80, 0x00, 0x07, 55 | 0x80, 0x02, 0x1F, 0x80, 56 | 0x50, 0x3F, 0xA0, 0x00, 57 | 0x88, 0x38, 0x80, 0x2A, 58 | 0x37, 0x06, 0x80, 0x80, 59 | 0x1D, 0x60, 0x00, 0x54, 60 | 0x01, 0x8A, 0x20, 0xFF, 61 | 0xD4, 0x22, 0xA0, 0x10, 62 | 0x00, 0x80, 0x00, 0x07, 63 | 0x80, 0x03, 0x1C, 0x80, 64 | 0x50, 0x3F, 0xA0, 0x00, 65 | 0x88, 0x38, 0x80, 0x28, 66 | 0x37, 0x80, 0x00, 0x07, 67 | 0x80, 0x02, 0x1F, 0x80, 68 | 0x50, 0x3F, 0xA0, 0x00, 69 | 0x88, 0x38, 0x80, 0x2A, 70 | 0x37, 0x06, 0x80, 0xC0, 71 | 0x1D, 0x60, 0x00, 0x24, 72 | 0x01, 0x8A, 0x20, 0xFF, 73 | 0xD4, 0x22, 0x00, 0x80, 74 | 0x0F, 0x13, 0x80, 0xF2, 75 | 0x80, 0x26, 0x17, 0xA0, 76 | 0x02, 0x61, 0x80, 0x2C, 77 | 0x37, 0xA0, 0x22, 0x00, 78 | 0x80, 0x00, 0x80, 0x2F, 79 | 0x17, 0x01, 0x8A, 0x20, 80 | 0xFF, 0xF6, 0x22, 0x6C, 81 | 0x80, 0x01, 0x80, 0x26, 82 | 0x17, 0xA0, 0x02, 0x69, 83 | 0x80, 0x2C, 0x37, 0x06, 84 | 0x80, 0x2F, 0x17, 0x06, 85 | 0x80, 0x10, 0x1D, 0x80, 86 | 0x2F, 0x17, 0x80, 0x2A, 87 | 0xB6, 0xA0, 0x00, 0x08, 88 | 0x38, 0x05, 0x37, 0x06, 89 | 0x80, 0x20, 0x1D, 0x80, 90 | 0x2F, 0x17, 0x06, 0x80, 91 | 0x30, 0x1D, 0x80, 0x2F, 92 | 0x17, 0x80, 0x2A, 0xB6, 93 | 0xA0, 0x00, 0x0C, 0x38, 94 | 0x05, 0x37, 0x80, 0x00, 95 | 0x04, 0x80, 0x30, 0x1F, 96 | 0xA0, 0x02, 0x79, 0x38, 97 | 0x80, 0x2C, 0x37, 0x80, 98 | 0x09, 0x80, 0x2F, 0x17, 99 | 0x6C, 0x03, 0x06, 0x0C, 100 | 0x18, 0x30, 0x60, 0xC0, 101 | 0x81, 0x07, 0x1F, 0x3C, 102 | 0x70, 0x60, 0xE3, 0xC7, 103 | 0xC7, 0x00, 0x00, 0x03, 104 | 0x0F, 0x1F, 0x1F, 0x3F, 105 | 0x3F, 0x00, 0x7C, 0x82, 106 | 0x82, 0x82, 0x82, 0x82, 107 | 0x7C, 0x00, 0x30, 0x10, 108 | 0x10, 0x10, 0x10, 0x10, 109 | 0x10, 0x00, 0x7C, 0x82, 110 | 0x02, 0x7C, 0x80, 0x80, 111 | 0xFE, 0x00, 0x7C, 0x82, 112 | 0x02, 0x1C, 0x02, 0x82, 113 | 0x7C, 0x00, 0x0C, 0x14, 114 | 0x24, 0x44, 0x84, 0xFE, 115 | 0x04, 0x00, 0xFE, 0x80, 116 | 0x80, 0x7C, 0x02, 0x82, 117 | 0x7C, 0x00, 0x7C, 0x82, 118 | 0x80, 0xFC, 0x82, 0x82, 119 | 0x7C, 0x00, 0x7C, 0x82, 120 | 0x02, 0x1E, 0x02, 0x02, 121 | 0x02, 0x00, 0x7C, 0x82, 122 | 0x82, 0x7C, 0x82, 0x82, 123 | 0x7C, 0x00, 0x7C, 0x82, 124 | 0x82, 0x7E, 0x02, 0x82, 125 | 0x7C, 0x00, 0x7C, 0x82, 126 | 0x02, 0x7E, 0x82, 0x82, 127 | 0x7E, 0x00, 0xFC, 0x82, 128 | 0x82, 0xFC, 0x82, 0x82, 129 | 0xFC, 0x00, 0x7C, 0x82, 130 | 0x80, 0x80, 0x80, 0x82, 131 | 0x7C, 0x00, 0xFC, 0x82, 132 | 0x82, 0x82, 0x82, 0x82, 133 | 0xFC, 0x00, 0x7C, 0x82, 134 | 0x80, 0xF0, 0x80, 0x82, 135 | 0x7C, 0x00, 0x7C, 0x82, 136 | 0x80, 0xF0, 0x80, 0x80, 137 | 0x80, 0x00, 0x00, 0x00, 138 | }; 139 | 140 | static uint32_t rdaddr; 141 | rdaddr = (uint32_t)(read_address); 142 | 143 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 144 | rdaddr, // read address 145 | 0, // write value 146 | 0 // write enable 147 | ); 148 | 149 | return rdata; 150 | } 151 | -------------------------------------------------------------------------------- /roms/star.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | // star demo for chibicc-uxn by hikari_no_yume (2023-06-10 ~ 2023-06-14) 5 | 6 | /* STAR (assembly) 7 | |0100 8 | ;L.screen.hook #20 DEO2 9 | LIT2r 0000 main_ POP2r BRK 10 | @L.screen.hook LIT2r 0000 on_screen_ POP2 POP2r BRK 11 | ( bss ) 12 | ( data ) 13 | @t_ 14 | 00 15 | @SPRITE_ 16 | 81 81 81 81 81 81 81 7f 17 | @SIN_TABLE_ 18 | 00 03 06 09 0c 0f 12 15 18 1c 1f 22 25 28 2b 2e 19 | 30 33 36 39 3c 3f 41 44 47 49 4c 4e 51 53 55 58 20 | 5a 5c 5e 60 62 64 66 68 6a 6c 6d 6f 70 72 73 75 21 | 76 77 78 79 7a 7b 7c 7c 7d 7e 7e 7f 7f 7f 7f 7f 22 | 23 | ( text ) 24 | @sext 25 | #80 ANDk EQU #ff MUL SWP JMP2r 26 | @ashr 27 | SWP2 28 | #8000 AND2k EQU2 #ff MUL DUP 29 | DUP2 ROT2 EOR2 ROT2 30 | NIP #0f AND SFT2 31 | EOR2 32 | JMP2r 33 | 34 | @sin_ ( a* -- result* ) 35 | OVR2r LIT2r 0002 SUB2r STH2kr STA 36 | POP ;SIN_TABLE_ LDAkr STHr #40 AND ?&then.1 37 | LDAkr STHr sext 38 | !&end.1 39 | 40 | &then.1 41 | LDAkr STHr sext 42 | #ffff EOR2 43 | 44 | &end.1 45 | #003f AND2 ADD2 LDA sext 46 | LDAkr STHr #80 AND ?&then.2 47 | #0001 !&end.2 48 | 49 | &then.2 50 | #ffff 51 | 52 | &end.2 53 | MUL2 !&return 54 | #0000 55 | 56 | &return 57 | NIP sext 58 | POP2r JMP2r 59 | 60 | @cos_ ( a* -- result* ) 61 | OVR2r LIT2r 0002 SUB2r STH2kr STA 62 | POP LDAkr STHr sext 63 | #0040 ADD2 sin_ 64 | !&return 65 | #0000 66 | 67 | &return 68 | NIP sext 69 | POP2r JMP2r 70 | 71 | @line_low_ ( pixel* y1* x1* y0* x0* -- result* ) 72 | OVR2r LIT2r 0016 SUB2r STH2kr #0014 ADD2 STA2 73 | STH2kr #0012 ADD2 STA2 74 | STH2kr #0010 ADD2 STA2 75 | STH2kr #000e ADD2 STA2 76 | STH2kr #000c ADD2 STA 77 | POP STH2kr #0010 ADD2 LDA2 STH2kr #0014 ADD2 LDA2 SUB2 STH2kr #000a ADD2 STA2 78 | STH2kr #000e ADD2 LDA2 STH2kr #0012 ADD2 LDA2 SUB2 STH2kr #0008 ADD2 STA2 79 | #0001 STH2kr #0006 ADD2 STA2 80 | STH2kr #0008 ADD2 LDA2 #8000 EOR2 #8000 LTH2 #00 EQU ?&end.1 81 | #ffff STH2kr #0006 ADD2 STA2 82 | #0000 STH2kr #0008 ADD2 LDA2 SUB2 STH2kr #0008 ADD2 STA2 83 | 84 | &end.1 85 | STH2kr #0008 ADD2 LDA2 #10 SFT2 STH2kr #000a ADD2 LDA2 SUB2 STH2kr #0004 ADD2 STA2 86 | STH2kr #0012 ADD2 LDA2 STH2kr INC2 INC2 STA2 87 | STH2kr #0014 ADD2 LDA2 STH2kr STA2 88 | 89 | &begin.2 90 | STH2kr LDA2 #8000 EOR2 STH2kr #0010 ADD2 LDA2 #8000 EOR2 GTH2 #00 SWP #01 EOR #0000 EQU2 ?&break.2 91 | STH2kr LDA2 #28 DEO2 STH2kr INC2 INC2 LDA2 #2a DEO2 STH2kr #000c ADD2 LDA #2e DEO #8000 STH2kr #0004 ADD2 LDA2 #8000 EOR2 LTH2 ?&then.3 92 | STH2kr #0004 ADD2 LDA2k STH2kr #0008 ADD2 LDA2 #10 SFT2 ADD2 SWP2 STA2 93 | !&end.3 94 | 95 | &then.3 96 | STH2kr INC2 INC2 LDA2k STH2kr #0006 ADD2 LDA2 ADD2 SWP2 STA2 97 | STH2kr #0004 ADD2 LDA2k STH2kr #0008 ADD2 LDA2 STH2kr #000a ADD2 LDA2 SUB2 #10 SFT2 ADD2 SWP2 STA2 98 | 99 | &end.3 100 | 101 | &continue.2 102 | STH2kr LDA2k INC2k ROT2 STA2 103 | POP2 !&begin.2 104 | 105 | &break.2 106 | #0000 107 | 108 | &return 109 | POP2r JMP2r 110 | 111 | @line_high_ ( pixel* y1* x1* y0* x0* -- result* ) 112 | OVR2r LIT2r 0016 SUB2r STH2kr #0014 ADD2 STA2 113 | STH2kr #0012 ADD2 STA2 114 | STH2kr #0010 ADD2 STA2 115 | STH2kr #000e ADD2 STA2 116 | STH2kr #000c ADD2 STA 117 | POP STH2kr #0010 ADD2 LDA2 STH2kr #0014 ADD2 LDA2 SUB2 STH2kr #000a ADD2 STA2 118 | STH2kr #000e ADD2 LDA2 STH2kr #0012 ADD2 LDA2 SUB2 STH2kr #0008 ADD2 STA2 119 | #0001 STH2kr #0006 ADD2 STA2 120 | STH2kr #000a ADD2 LDA2 #8000 EOR2 #8000 LTH2 #00 EQU ?&end.1 121 | #ffff STH2kr #0006 ADD2 STA2 122 | #0000 STH2kr #000a ADD2 LDA2 SUB2 STH2kr #000a ADD2 STA2 123 | 124 | &end.1 125 | STH2kr #000a ADD2 LDA2 #10 SFT2 STH2kr #0008 ADD2 LDA2 SUB2 STH2kr #0004 ADD2 STA2 126 | STH2kr #0014 ADD2 LDA2 STH2kr INC2 INC2 STA2 127 | STH2kr #0012 ADD2 LDA2 STH2kr STA2 128 | 129 | &begin.2 130 | STH2kr LDA2 #8000 EOR2 STH2kr #000e ADD2 LDA2 #8000 EOR2 GTH2 #00 SWP #01 EOR #0000 EQU2 ?&break.2 131 | STH2kr INC2 INC2 LDA2 #28 DEO2 STH2kr LDA2 #2a DEO2 STH2kr #000c ADD2 LDA #2e DEO #8000 STH2kr #0004 ADD2 LDA2 #8000 EOR2 LTH2 ?&then.3 132 | STH2kr #0004 ADD2 LDA2k STH2kr #000a ADD2 LDA2 #10 SFT2 ADD2 SWP2 STA2 133 | !&end.3 134 | 135 | &then.3 136 | STH2kr INC2 INC2 LDA2k STH2kr #0006 ADD2 LDA2 ADD2 SWP2 STA2 137 | STH2kr #0004 ADD2 LDA2k STH2kr #000a ADD2 LDA2 STH2kr #0008 ADD2 LDA2 SUB2 #10 SFT2 ADD2 SWP2 STA2 138 | 139 | &end.3 140 | 141 | &continue.2 142 | STH2kr LDA2k INC2k ROT2 STA2 143 | POP2 !&begin.2 144 | 145 | &break.2 146 | #0000 147 | 148 | &return 149 | POP2r JMP2r 150 | 151 | @line_ ( pixel* y1* x1* y0* x0* -- result* ) 152 | OVR2r LIT2r 000e SUB2r STH2kr #000c ADD2 STA2 153 | STH2kr #000a ADD2 STA2 154 | STH2kr #0008 ADD2 STA2 155 | STH2kr #0006 ADD2 STA2 156 | STH2kr #0004 ADD2 STA 157 | POP STH2kr #0006 ADD2 LDA2 STH2kr #000a ADD2 LDA2 SUB2 STH2kr INC2 INC2 STA2 158 | STH2kr INC2 INC2 LDA2 #8000 EOR2 #8000 LTH2 #00 EQU ?&end.1 159 | #0000 STH2kr INC2 INC2 LDA2 SUB2 STH2kr INC2 INC2 STA2 160 | 161 | &end.1 162 | STH2kr #0008 ADD2 LDA2 STH2kr #000c ADD2 LDA2 SUB2 STH2kr STA2 163 | STH2kr LDA2 #8000 EOR2 #8000 LTH2 #00 EQU ?&end.2 164 | #0000 STH2kr LDA2 SUB2 STH2kr STA2 165 | 166 | &end.2 167 | STH2kr INC2 INC2 LDA2 #8000 EOR2 STH2kr LDA2 #8000 EOR2 LTH2 ?&then.3 168 | STH2kr #0006 ADD2 LDA2 #8000 EOR2 STH2kr #000a ADD2 LDA2 #8000 EOR2 LTH2 ?&then.4 169 | STH2kr #0004 ADD2 LDA sext 170 | STH2kr #0006 ADD2 LDA2 STH2kr #0008 ADD2 LDA2 STH2kr #000a ADD2 LDA2 STH2kr #000c ADD2 LDA2 line_high_ 171 | POP2 !&end.4 172 | 173 | &then.4 174 | STH2kr #0004 ADD2 LDA sext 175 | STH2kr #000a ADD2 LDA2 STH2kr #000c ADD2 LDA2 STH2kr #0006 ADD2 LDA2 STH2kr #0008 ADD2 LDA2 line_high_ 176 | POP2 177 | 178 | &end.4 179 | !&end.3 180 | 181 | &then.3 182 | STH2kr #0008 ADD2 LDA2 #8000 EOR2 STH2kr #000c ADD2 LDA2 #8000 EOR2 LTH2 ?&then.5 183 | STH2kr #0004 ADD2 LDA sext 184 | STH2kr #0006 ADD2 LDA2 STH2kr #0008 ADD2 LDA2 STH2kr #000a ADD2 LDA2 STH2kr #000c ADD2 LDA2 line_low_ 185 | POP2 !&end.5 186 | 187 | &then.5 188 | STH2kr #0004 ADD2 LDA sext 189 | STH2kr #000a ADD2 LDA2 STH2kr #000c ADD2 LDA2 STH2kr #0006 ADD2 LDA2 STH2kr #0008 ADD2 LDA2 line_low_ 190 | POP2 191 | 192 | &end.5 193 | 194 | &end.3 195 | #0000 196 | 197 | &return 198 | POP2r JMP2r 199 | 200 | @on_screen_ ( -- result* ) 201 | OVR2r LIT2r 0012 SUB2r ;t_ LDAk sext 202 | INC2k ROT2 STA 203 | POP POP2 #0000 #28 DEO2 #0000 #2a DEO2 #802e DEO #0100 SWP STH2kr #0010 ADD2 STA 204 | POP #0000 STH2kr #000a ADD2 STA2 205 | 206 | &begin.1 207 | STH2kr #000a ADD2 LDA2 #000b LTH2 #00 EQU ?&break.1 208 | ;t_ LDA sext 209 | STH2kr #000a ADD2 LDA2 #000a OVR2 OVR2 DIV2 MUL2 SUB2 #80 SFT2 #000a DIV2 ADD2 STH2kr #0008 ADD2 STA 210 | POP STH2kr #0008 ADD2 LDA #00 SWP sin_ 211 | STH2kr #000a ADD2 LDA2 #0001 AND2 ashr 212 | STH2kr #0006 ADD2 STA2 213 | STH2kr #0008 ADD2 LDA #00 SWP cos_ 214 | STH2kr #000a ADD2 LDA2 #0001 AND2 ashr 215 | STH2kr #0004 ADD2 STA2 216 | STH2kr #0010 ADD2 LDA ?&then.2 217 | #0003 STH2kr #0004 ADD2 LDA2 #00b3 ADD2 STH2kr #0006 ADD2 LDA2 #00c7 ADD2 STH2kr #000c ADD2 LDA2 #00b3 ADD2 STH2kr #000e ADD2 LDA2 #00c7 ADD2 line_ 218 | POP2 #0002 STH2kr #0004 ADD2 LDA2 #0003 MUL2 #0002 ashr 219 | #00b3 ADD2 STH2kr #0006 ADD2 LDA2 #0003 MUL2 #0002 ashr 220 | #00c7 ADD2 STH2kr #000c ADD2 LDA2 #0003 MUL2 #0002 ashr 221 | #00b3 ADD2 STH2kr #000e ADD2 LDA2 #0003 MUL2 #0002 ashr 222 | #00c7 ADD2 line_ 223 | POP2 #0001 STH2kr #0004 ADD2 LDA2 #0001 ashr 224 | #00b3 ADD2 STH2kr #0006 ADD2 LDA2 #0001 ashr 225 | #00c7 ADD2 STH2kr #000c ADD2 LDA2 #0001 ashr 226 | #00b3 ADD2 STH2kr #000e ADD2 LDA2 #0001 ashr 227 | #00c7 ADD2 line_ 228 | POP2 !&end.2 229 | 230 | &then.2 231 | #0000 SWP STH2kr #0010 ADD2 STA 232 | POP 233 | 234 | &end.2 235 | STH2kr #0006 ADD2 LDA2 STH2kr #000e ADD2 STA2 236 | STH2kr #0004 ADD2 LDA2 STH2kr #000c ADD2 STA2 237 | 238 | &continue.1 239 | STH2kr #000a ADD2 LDA2k INC2k ROT2 STA2 240 | POP2 !&begin.1 241 | 242 | &break.1 243 | ;SPRITE_ #2c DEO2 #00b9 #28 DEO2 #00af #2a DEO2 #012f DEO ;t_ LDA sext 244 | #0020 ADD2 sin_ 245 | #0005 ashr 246 | STH2kr INC2 INC2 STA2 247 | ;t_ LDA sext 248 | #0020 ADD2 cos_ 249 | #0005 ashr 250 | STH2kr STA2 251 | #0003 STH2kr LDA2 #00b3 ADD2 STH2kr INC2 INC2 LDA2 #00c7 ADD2 #00b3 STH2kr LDA2 SUB2 #0001 SUB2 #00c7 STH2kr INC2 INC2 LDA2 SUB2 #0001 SUB2 line_ 252 | POP2 ;t_ LDA sext 253 | #0060 ADD2 sin_ 254 | #0005 ashr 255 | STH2kr INC2 INC2 STA2 256 | ;t_ LDA sext 257 | #0060 ADD2 cos_ 258 | #0005 ashr 259 | STH2kr STA2 260 | #0003 STH2kr LDA2 #00b3 ADD2 STH2kr INC2 INC2 LDA2 #00c7 ADD2 #00b3 STH2kr LDA2 SUB2 #0001 SUB2 #00c7 STH2kr INC2 INC2 LDA2 SUB2 #0001 SUB2 line_ 261 | POP2 ;SPRITE_ #2c DEO2 #00cd #28 DEO2 #00af #2a DEO2 #312f DEO #0000 262 | 263 | &return 264 | POP2r JMP2r 265 | 266 | @main_ ( -- result* ) 267 | OVR2r #0aaf #08 DEO2 #0ffc #0a DEO2 #0faa #0c DEO2 #0190 #22 DEO2 #0168 #24 DEO2 #0000 268 | 269 | &return 270 | POP2r JMP2r 271 | */ 272 | 273 | /* STAR.C 274 | // star demo for chibicc-uxn by hikari_no_yume (2023-06-10 ~ 2023-06-14) 275 | 276 | #include 277 | 278 | // generated with JS: x="";for(i=0;i<64;i++)x+=((Math.sin(i*Math.PI/128)*128)|0)+","; 279 | char SIN_TABLE[64] = {0,3,6,9,12,15,18,21,24,28,31,34,37,40,43,46,48,51,54,57,60,63,65,68,71,73,76,78,81,83,85,88,90,92,94,96,98,100,102,104,106,108,109,111,112,114,115,117,118,119,120,121,122,123,124,124,125,126,126,127,127,127,127,127,}; 280 | char sin(char a) 281 | { 282 | return SIN_TABLE[(a & 0x40 ? ~a : a) & 0x3f] * (a & 0x80 ? -1 : 1); 283 | } 284 | char cos(char a) 285 | { 286 | return sin(a + 0x40); 287 | } 288 | 289 | // https://en.wikipedia.org/wiki/Bresenham%27s_line_algorithm#All_cases 290 | void line_low(int x0, int y0, int x1, int y1, char pixel) 291 | { 292 | int dx = x1 - x0; 293 | int dy = y1 - y0; 294 | int yi = 1; 295 | if (dy < 0) { 296 | yi = -1; 297 | dy = -dy; 298 | } 299 | int d = (2 * dy) - dx; 300 | int y = y0; 301 | for (int x = x0; x <= x1; x++) { 302 | set_screen_xy(x, y); 303 | draw_pixel(pixel); 304 | if (d > 0) { 305 | y += yi; 306 | d += 2 * (dy - dx); 307 | } else { 308 | d += 2 * dy; 309 | } 310 | } 311 | } 312 | void line_high(int x0, int y0, int x1, int y1, char pixel) 313 | { 314 | int dx = x1 - x0; 315 | int dy = y1 - y0; 316 | int xi = 1; 317 | if (dx < 0) { 318 | xi = -1; 319 | dx = -dx; 320 | } 321 | int d = (2 * dx) - dy; 322 | int x = x0; 323 | for (int y = y0; y <= y1; y++) { 324 | set_screen_xy(x, y); 325 | draw_pixel(pixel); 326 | if (d > 0) { 327 | x += xi; 328 | d += 2 * (dx - dy); 329 | } else { 330 | d += 2 * dx; 331 | } 332 | } 333 | } 334 | void line(int x0, int y0, int x1, int y1, char pixel) 335 | { 336 | int y1y0 = y1 - y0; 337 | if (y1y0 < 0) y1y0 = -y1y0; 338 | int x1x0 = x1 - x0; 339 | if (x1x0 < 0) x1x0 = -x1x0; 340 | if (y1y0 < x1x0) { 341 | if (x0 > x1) 342 | line_low(x1, y1, x0, y0, pixel); 343 | else 344 | line_low(x0, y0, x1, y1, pixel); 345 | } else { 346 | if (y0 > y1) 347 | line_high(x1, y1, x0, y0, pixel); 348 | else 349 | line_high(x0, y0, x1, y1, pixel); 350 | } 351 | } 352 | 353 | char SPRITE[8] = { 354 | 0b10000001, 355 | 0b10000001, 356 | 0b10000001, 357 | 0b10000001, 358 | 0b10000001, 359 | 0b10000001, 360 | 0b10000001, 361 | 0b01111111, 362 | }; 363 | 364 | char t = 0; 365 | 366 | void on_screen(void) 367 | { 368 | t++; 369 | 370 | // clear layer 0 371 | set_screen_xy(0, 0); 372 | draw_pixel(BgFillBR); 373 | // draw star 374 | _Bool first = 1; 375 | int last_x; 376 | int last_y; 377 | for (unsigned i = 0; i < 11; i++) { 378 | unsigned char angle = t + (256 * (i % 10)) / 10; 379 | int x = sin(angle) >> (i & 1); 380 | int y = cos(angle) >> (i & 1); 381 | if (first) { 382 | first = 0; 383 | } else { 384 | line(199 + last_x, 179 + last_y, 199 + x, 179 + y, 0x03); 385 | line(199 + (last_x * 3 >> 2), 179 + (last_y * 3 >> 2), 199 + (x * 3 >> 2), 179 + (y * 3 >> 2), 0x02); 386 | line(199 + (last_x >> 1), 179 + (last_y >> 1), 199 + (x >> 1), 179 + (y >> 1), 0x01); 387 | } 388 | last_x = x; 389 | last_y = y; 390 | } 391 | // draw u 392 | set_screen_addr(SPRITE); 393 | set_screen_xy(185, 175); 394 | draw_sprite(0x01); 395 | // draw x 396 | int x = sin(t + 0x20) >> 5; 397 | int y = cos(t + 0x20) >> 5; 398 | line(199 - x - 1, 179 - y - 1, 199 + x, 179 + y, 0x03); 399 | x = sin(t + 0x60) >> 5; 400 | y = cos(t + 0x60) >> 5; 401 | line(199 - x - 1, 179 - y - 1, 199 + x, 179 + y, 0x03); 402 | // draw n 403 | set_screen_addr(SPRITE); 404 | set_screen_xy(205, 175); 405 | draw_sprite(0x31); 406 | } 407 | 408 | void main(void) 409 | { 410 | set_palette(0x0aaf, 0x0ffc, 0x0faa); 411 | set_screen_size(400, 360); 412 | } 413 | 414 | */ 415 | 416 | #define ROM_SIZE 2048 417 | 418 | uint8_t read_rom_byte(uint16_t read_address) 419 | { 420 | static uint8_t uxn_rom[ROM_SIZE] = { 421 | 0xA0, 0x01, 0x0E, 0x80, 422 | 0x20, 0x37, 0xE0, 0x00, 423 | 0x00, 0x60, 0x07, 0x38, 424 | 0x62, 0x00, 0xE0, 0x00, 425 | 0x00, 0x60, 0x04, 0x9D, 426 | 0x22, 0x62, 0x00, 0x00, 427 | 0x81, 0x81, 0x81, 0x81, 428 | 0x81, 0x81, 0x81, 0x7F, 429 | 0x00, 0x03, 0x06, 0x09, 430 | 0x0C, 0x0F, 0x12, 0x15, 431 | 0x18, 0x1C, 0x1F, 0x22, 432 | 0x25, 0x28, 0x2B, 0x2E, 433 | 0x30, 0x33, 0x36, 0x39, 434 | 0x3C, 0x3F, 0x41, 0x44, 435 | 0x47, 0x49, 0x4C, 0x4E, 436 | 0x51, 0x53, 0x55, 0x58, 437 | 0x5A, 0x5C, 0x5E, 0x60, 438 | 0x62, 0x64, 0x66, 0x68, 439 | 0x6A, 0x6C, 0x6D, 0x6F, 440 | 0x70, 0x72, 0x73, 0x75, 441 | 0x76, 0x77, 0x78, 0x79, 442 | 0x7A, 0x7B, 0x7C, 0x7C, 443 | 0x7D, 0x7E, 0x7E, 0x7F, 444 | 0x7F, 0x7F, 0x7F, 0x7F, 445 | 0x80, 0x80, 0x9C, 0x08, 446 | 0x80, 0xFF, 0x1A, 0x04, 447 | 0x6C, 0x24, 0xA0, 0x80, 448 | 0x00, 0xBC, 0x28, 0x80, 449 | 0xFF, 0x1A, 0x06, 0x26, 450 | 0x25, 0x3E, 0x25, 0x03, 451 | 0x80, 0x0F, 0x1C, 0x3F, 452 | 0x3E, 0x6C, 0x67, 0xE0, 453 | 0x00, 0x02, 0x79, 0xEF, 454 | 0x15, 0x02, 0xA0, 0x01, 455 | 0x20, 0xD4, 0x4F, 0x80, 456 | 0x40, 0x1C, 0x20, 0x00, 457 | 0x08, 0xD4, 0x4F, 0x60, 458 | 0xFF, 0xCA, 0x40, 0x00, 459 | 0x09, 0xD4, 0x4F, 0x60, 460 | 0xFF, 0xC2, 0xA0, 0xFF, 461 | 0xFF, 0x3E, 0xA0, 0x00, 462 | 0x3F, 0x3C, 0x38, 0x14, 463 | 0x60, 0xFF, 0xB5, 0xD4, 464 | 0x4F, 0x80, 0x80, 0x1C, 465 | 0x20, 0x00, 0x06, 0xA0, 466 | 0x00, 0x01, 0x40, 0x00, 467 | 0x03, 0xA0, 0xFF, 0xFF, 468 | 0x3A, 0x40, 0x00, 0x03, 469 | 0xA0, 0x00, 0x00, 0x03, 470 | 0x60, 0xFF, 0x99, 0x62, 471 | 0x6C, 0x67, 0xE0, 0x00, 472 | 0x02, 0x79, 0xEF, 0x15, 473 | 0x02, 0xD4, 0x4F, 0x60, 474 | 0xFF, 0x8A, 0xA0, 0x00, 475 | 0x40, 0x38, 0x60, 0xFF, 476 | 0xA1, 0x40, 0x00, 0x03, 477 | 0xA0, 0x00, 0x00, 0x03, 478 | 0x60, 0xFF, 0x79, 0x62, 479 | 0x6C, 0x67, 0xE0, 0x00, 480 | 0x16, 0x79, 0xEF, 0xA0, 481 | 0x00, 0x14, 0x38, 0x35, 482 | 0xEF, 0xA0, 0x00, 0x12, 483 | 0x38, 0x35, 0xEF, 0xA0, 484 | 0x00, 0x10, 0x38, 0x35, 485 | 0xEF, 0xA0, 0x00, 0x0E, 486 | 0x38, 0x35, 0xEF, 0xA0, 487 | 0x00, 0x0C, 0x38, 0x15, 488 | 0x02, 0xEF, 0xA0, 0x00, 489 | 0x10, 0x38, 0x34, 0xEF, 490 | 0xA0, 0x00, 0x14, 0x38, 491 | 0x34, 0x39, 0xEF, 0xA0, 492 | 0x00, 0x0A, 0x38, 0x35, 493 | 0xEF, 0xA0, 0x00, 0x0E, 494 | 0x38, 0x34, 0xEF, 0xA0, 495 | 0x00, 0x12, 0x38, 0x34, 496 | 0x39, 0xEF, 0xA0, 0x00, 497 | 0x08, 0x38, 0x35, 0xA0, 498 | 0x00, 0x01, 0xEF, 0xA0, 499 | 0x00, 0x06, 0x38, 0x35, 500 | 0xEF, 0xA0, 0x00, 0x08, 501 | 0x38, 0x34, 0xA0, 0x80, 502 | 0x00, 0x3E, 0xA0, 0x80, 503 | 0x00, 0x2B, 0x80, 0x00, 504 | 0x08, 0x20, 0x00, 0x19, 505 | 0xA0, 0xFF, 0xFF, 0xEF, 506 | 0xA0, 0x00, 0x06, 0x38, 507 | 0x35, 0xA0, 0x00, 0x00, 508 | 0xEF, 0xA0, 0x00, 0x08, 509 | 0x38, 0x34, 0x39, 0xEF, 510 | 0xA0, 0x00, 0x08, 0x38, 511 | 0x35, 0xEF, 0xA0, 0x00, 512 | 0x08, 0x38, 0x34, 0x80, 513 | 0x10, 0x3F, 0xEF, 0xA0, 514 | 0x00, 0x0A, 0x38, 0x34, 515 | 0x39, 0xEF, 0xA0, 0x00, 516 | 0x04, 0x38, 0x35, 0xEF, 517 | 0xA0, 0x00, 0x12, 0x38, 518 | 0x34, 0xEF, 0x21, 0x21, 519 | 0x35, 0xEF, 0xA0, 0x00, 520 | 0x14, 0x38, 0x34, 0xEF, 521 | 0x35, 0xEF, 0x34, 0xA0, 522 | 0x80, 0x00, 0x3E, 0xEF, 523 | 0xA0, 0x00, 0x10, 0x38, 524 | 0x34, 0xA0, 0x80, 0x00, 525 | 0x3E, 0x2A, 0x80, 0x00, 526 | 0x04, 0x80, 0x01, 0x1E, 527 | 0xA0, 0x00, 0x00, 0x28, 528 | 0x20, 0x00, 0x6A, 0xEF, 529 | 0x34, 0x80, 0x28, 0x37, 530 | 0xEF, 0x21, 0x21, 0x34, 531 | 0x80, 0x2A, 0x37, 0xEF, 532 | 0xA0, 0x00, 0x0C, 0x38, 533 | 0x14, 0x80, 0x2E, 0x17, 534 | 0xA0, 0x80, 0x00, 0xEF, 535 | 0xA0, 0x00, 0x04, 0x38, 536 | 0x34, 0xA0, 0x80, 0x00, 537 | 0x3E, 0x2B, 0x20, 0x00, 538 | 0x15, 0xEF, 0xA0, 0x00, 539 | 0x04, 0x38, 0xB4, 0xEF, 540 | 0xA0, 0x00, 0x08, 0x38, 541 | 0x34, 0x80, 0x10, 0x3F, 542 | 0x38, 0x24, 0x35, 0x40, 543 | 0x00, 0x26, 0xEF, 0x21, 544 | 0x21, 0xB4, 0xEF, 0xA0, 545 | 0x00, 0x06, 0x38, 0x34, 546 | 0x38, 0x24, 0x35, 0xEF, 547 | 0xA0, 0x00, 0x04, 0x38, 548 | 0xB4, 0xEF, 0xA0, 0x00, 549 | 0x08, 0x38, 0x34, 0xEF, 550 | 0xA0, 0x00, 0x0A, 0x38, 551 | 0x34, 0x39, 0x80, 0x10, 552 | 0x3F, 0x38, 0x24, 0x35, 553 | 0xEF, 0xB4, 0xA1, 0x25, 554 | 0x35, 0x22, 0x40, 0xFF, 555 | 0x78, 0xA0, 0x00, 0x00, 556 | 0x62, 0x6C, 0x67, 0xE0, 557 | 0x00, 0x16, 0x79, 0xEF, 558 | 0xA0, 0x00, 0x14, 0x38, 559 | 0x35, 0xEF, 0xA0, 0x00, 560 | 0x12, 0x38, 0x35, 0xEF, 561 | 0xA0, 0x00, 0x10, 0x38, 562 | 0x35, 0xEF, 0xA0, 0x00, 563 | 0x0E, 0x38, 0x35, 0xEF, 564 | 0xA0, 0x00, 0x0C, 0x38, 565 | 0x15, 0x02, 0xEF, 0xA0, 566 | 0x00, 0x10, 0x38, 0x34, 567 | 0xEF, 0xA0, 0x00, 0x14, 568 | 0x38, 0x34, 0x39, 0xEF, 569 | 0xA0, 0x00, 0x0A, 0x38, 570 | 0x35, 0xEF, 0xA0, 0x00, 571 | 0x0E, 0x38, 0x34, 0xEF, 572 | 0xA0, 0x00, 0x12, 0x38, 573 | 0x34, 0x39, 0xEF, 0xA0, 574 | 0x00, 0x08, 0x38, 0x35, 575 | 0xA0, 0x00, 0x01, 0xEF, 576 | 0xA0, 0x00, 0x06, 0x38, 577 | 0x35, 0xEF, 0xA0, 0x00, 578 | 0x0A, 0x38, 0x34, 0xA0, 579 | 0x80, 0x00, 0x3E, 0xA0, 580 | 0x80, 0x00, 0x2B, 0x80, 581 | 0x00, 0x08, 0x20, 0x00, 582 | 0x19, 0xA0, 0xFF, 0xFF, 583 | 0xEF, 0xA0, 0x00, 0x06, 584 | 0x38, 0x35, 0xA0, 0x00, 585 | 0x00, 0xEF, 0xA0, 0x00, 586 | 0x0A, 0x38, 0x34, 0x39, 587 | 0xEF, 0xA0, 0x00, 0x0A, 588 | 0x38, 0x35, 0xEF, 0xA0, 589 | 0x00, 0x0A, 0x38, 0x34, 590 | 0x80, 0x10, 0x3F, 0xEF, 591 | 0xA0, 0x00, 0x08, 0x38, 592 | 0x34, 0x39, 0xEF, 0xA0, 593 | 0x00, 0x04, 0x38, 0x35, 594 | 0xEF, 0xA0, 0x00, 0x14, 595 | 0x38, 0x34, 0xEF, 0x21, 596 | 0x21, 0x35, 0xEF, 0xA0, 597 | 0x00, 0x12, 0x38, 0x34, 598 | 0xEF, 0x35, 0xEF, 0x34, 599 | 0xA0, 0x80, 0x00, 0x3E, 600 | 0xEF, 0xA0, 0x00, 0x0E, 601 | 0x38, 0x34, 0xA0, 0x80, 602 | 0x00, 0x3E, 0x2A, 0x80, 603 | 0x00, 0x04, 0x80, 0x01, 604 | 0x1E, 0xA0, 0x00, 0x00, 605 | 0x28, 0x20, 0x00, 0x6A, 606 | 0xEF, 0x21, 0x21, 0x34, 607 | 0x80, 0x28, 0x37, 0xEF, 608 | 0x34, 0x80, 0x2A, 0x37, 609 | 0xEF, 0xA0, 0x00, 0x0C, 610 | 0x38, 0x14, 0x80, 0x2E, 611 | 0x17, 0xA0, 0x80, 0x00, 612 | 0xEF, 0xA0, 0x00, 0x04, 613 | 0x38, 0x34, 0xA0, 0x80, 614 | 0x00, 0x3E, 0x2B, 0x20, 615 | 0x00, 0x15, 0xEF, 0xA0, 616 | 0x00, 0x04, 0x38, 0xB4, 617 | 0xEF, 0xA0, 0x00, 0x0A, 618 | 0x38, 0x34, 0x80, 0x10, 619 | 0x3F, 0x38, 0x24, 0x35, 620 | 0x40, 0x00, 0x26, 0xEF, 621 | 0x21, 0x21, 0xB4, 0xEF, 622 | 0xA0, 0x00, 0x06, 0x38, 623 | 0x34, 0x38, 0x24, 0x35, 624 | 0xEF, 0xA0, 0x00, 0x04, 625 | 0x38, 0xB4, 0xEF, 0xA0, 626 | 0x00, 0x0A, 0x38, 0x34, 627 | 0xEF, 0xA0, 0x00, 0x08, 628 | 0x38, 0x34, 0x39, 0x80, 629 | 0x10, 0x3F, 0x38, 0x24, 630 | 0x35, 0xEF, 0xB4, 0xA1, 631 | 0x25, 0x35, 0x22, 0x40, 632 | 0xFF, 0x78, 0xA0, 0x00, 633 | 0x00, 0x62, 0x6C, 0x67, 634 | 0xE0, 0x00, 0x0E, 0x79, 635 | 0xEF, 0xA0, 0x00, 0x0C, 636 | 0x38, 0x35, 0xEF, 0xA0, 637 | 0x00, 0x0A, 0x38, 0x35, 638 | 0xEF, 0xA0, 0x00, 0x08, 639 | 0x38, 0x35, 0xEF, 0xA0, 640 | 0x00, 0x06, 0x38, 0x35, 641 | 0xEF, 0xA0, 0x00, 0x04, 642 | 0x38, 0x15, 0x02, 0xEF, 643 | 0xA0, 0x00, 0x06, 0x38, 644 | 0x34, 0xEF, 0xA0, 0x00, 645 | 0x0A, 0x38, 0x34, 0x39, 646 | 0xEF, 0x21, 0x21, 0x35, 647 | 0xEF, 0x21, 0x21, 0x34, 648 | 0xA0, 0x80, 0x00, 0x3E, 649 | 0xA0, 0x80, 0x00, 0x2B, 650 | 0x80, 0x00, 0x08, 0x20, 651 | 0x00, 0x0C, 0xA0, 0x00, 652 | 0x00, 0xEF, 0x21, 0x21, 653 | 0x34, 0x39, 0xEF, 0x21, 654 | 0x21, 0x35, 0xEF, 0xA0, 655 | 0x00, 0x08, 0x38, 0x34, 656 | 0xEF, 0xA0, 0x00, 0x0C, 657 | 0x38, 0x34, 0x39, 0xEF, 658 | 0x35, 0xEF, 0x34, 0xA0, 659 | 0x80, 0x00, 0x3E, 0xA0, 660 | 0x80, 0x00, 0x2B, 0x80, 661 | 0x00, 0x08, 0x20, 0x00, 662 | 0x08, 0xA0, 0x00, 0x00, 663 | 0xEF, 0x34, 0x39, 0xEF, 664 | 0x35, 0xEF, 0x21, 0x21, 665 | 0x34, 0xA0, 0x80, 0x00, 666 | 0x3E, 0xEF, 0x34, 0xA0, 667 | 0x80, 0x00, 0x3E, 0x2B, 668 | 0x20, 0x00, 0x68, 0xEF, 669 | 0xA0, 0x00, 0x06, 0x38, 670 | 0x34, 0xA0, 0x80, 0x00, 671 | 0x3E, 0xEF, 0xA0, 0x00, 672 | 0x0A, 0x38, 0x34, 0xA0, 673 | 0x80, 0x00, 0x3E, 0x2B, 674 | 0x20, 0x00, 0x28, 0xEF, 675 | 0xA0, 0x00, 0x04, 0x38, 676 | 0x14, 0x60, 0xFC, 0x60, 677 | 0xEF, 0xA0, 0x00, 0x06, 678 | 0x38, 0x34, 0xEF, 0xA0, 679 | 0x00, 0x08, 0x38, 0x34, 680 | 0xEF, 0xA0, 0x00, 0x0A, 681 | 0x38, 0x34, 0xEF, 0xA0, 682 | 0x00, 0x0C, 0x38, 0x34, 683 | 0x60, 0xFE, 0x03, 0x22, 684 | 0x40, 0x00, 0x25, 0xEF, 685 | 0xA0, 0x00, 0x04, 0x38, 686 | 0x14, 0x60, 0xFC, 0x38, 687 | 0xEF, 0xA0, 0x00, 0x0A, 688 | 0x38, 0x34, 0xEF, 0xA0, 689 | 0x00, 0x0C, 0x38, 0x34, 690 | 0xEF, 0xA0, 0x00, 0x06, 691 | 0x38, 0x34, 0xEF, 0xA0, 692 | 0x00, 0x08, 0x38, 0x34, 693 | 0x60, 0xFD, 0xDB, 0x22, 694 | 0x40, 0x00, 0x65, 0xEF, 695 | 0xA0, 0x00, 0x08, 0x38, 696 | 0x34, 0xA0, 0x80, 0x00, 697 | 0x3E, 0xEF, 0xA0, 0x00, 698 | 0x0C, 0x38, 0x34, 0xA0, 699 | 0x80, 0x00, 0x3E, 0x2B, 700 | 0x20, 0x00, 0x28, 0xEF, 701 | 0xA0, 0x00, 0x04, 0x38, 702 | 0x14, 0x60, 0xFB, 0xF8, 703 | 0xEF, 0xA0, 0x00, 0x06, 704 | 0x38, 0x34, 0xEF, 0xA0, 705 | 0x00, 0x08, 0x38, 0x34, 706 | 0xEF, 0xA0, 0x00, 0x0A, 707 | 0x38, 0x34, 0xEF, 0xA0, 708 | 0x00, 0x0C, 0x38, 0x34, 709 | 0x60, 0xFC, 0x66, 0x22, 710 | 0x40, 0x00, 0x25, 0xEF, 711 | 0xA0, 0x00, 0x04, 0x38, 712 | 0x14, 0x60, 0xFB, 0xD0, 713 | 0xEF, 0xA0, 0x00, 0x0A, 714 | 0x38, 0x34, 0xEF, 0xA0, 715 | 0x00, 0x0C, 0x38, 0x34, 716 | 0xEF, 0xA0, 0x00, 0x06, 717 | 0x38, 0x34, 0xEF, 0xA0, 718 | 0x00, 0x08, 0x38, 0x34, 719 | 0x60, 0xFC, 0x3E, 0x22, 720 | 0xA0, 0x00, 0x00, 0x62, 721 | 0x6C, 0x67, 0xE0, 0x00, 722 | 0x12, 0x79, 0xA0, 0x01, 723 | 0x17, 0x94, 0x60, 0xFB, 724 | 0xA3, 0xA1, 0x25, 0x15, 725 | 0x02, 0x22, 0xA0, 0x00, 726 | 0x00, 0x80, 0x28, 0x37, 727 | 0xA0, 0x00, 0x00, 0x80, 728 | 0x2A, 0x37, 0xA0, 0x80, 729 | 0x2E, 0x17, 0xA0, 0x01, 730 | 0x00, 0x04, 0xEF, 0xA0, 731 | 0x00, 0x10, 0x38, 0x15, 732 | 0x02, 0xA0, 0x00, 0x00, 733 | 0xEF, 0xA0, 0x00, 0x0A, 734 | 0x38, 0x35, 0xEF, 0xA0, 735 | 0x00, 0x0A, 0x38, 0x34, 736 | 0xA0, 0x00, 0x0B, 0x2B, 737 | 0x80, 0x00, 0x08, 0x20, 738 | 0x01, 0x6B, 0xA0, 0x01, 739 | 0x17, 0x14, 0x60, 0xFB, 740 | 0x63, 0xEF, 0xA0, 0x00, 741 | 0x0A, 0x38, 0x34, 0xA0, 742 | 0x00, 0x0A, 0x27, 0x27, 743 | 0x3B, 0x3A, 0x39, 0x80, 744 | 0x80, 0x3F, 0xA0, 0x00, 745 | 0x0A, 0x3B, 0x38, 0xEF, 746 | 0xA0, 0x00, 0x08, 0x38, 747 | 0x15, 0x02, 0xEF, 0xA0, 748 | 0x00, 0x08, 0x38, 0x14, 749 | 0x80, 0x00, 0x04, 0x60, 750 | 0xFB, 0x58, 0xEF, 0xA0, 751 | 0x00, 0x0A, 0x38, 0x34, 752 | 0xA0, 0x00, 0x01, 0x3C, 753 | 0x60, 0xFB, 0x36, 0xEF, 754 | 0xA0, 0x00, 0x06, 0x38, 755 | 0x35, 0xEF, 0xA0, 0x00, 756 | 0x08, 0x38, 0x14, 0x80, 757 | 0x00, 0x04, 0x60, 0xFB, 758 | 0x84, 0xEF, 0xA0, 0x00, 759 | 0x0A, 0x38, 0x34, 0xA0, 760 | 0x00, 0x01, 0x3C, 0x60, 761 | 0xFB, 0x17, 0xEF, 0xA0, 762 | 0x00, 0x04, 0x38, 0x35, 763 | 0xEF, 0xA0, 0x00, 0x10, 764 | 0x38, 0x14, 0x20, 0x00, 765 | 0xD0, 0xA0, 0x00, 0x03, 766 | 0xEF, 0xA0, 0x00, 0x04, 767 | 0x38, 0x34, 0xA0, 0x00, 768 | 0x80, 0x38, 0xEF, 0xA0, 769 | 0x00, 0x06, 0x38, 0x34, 770 | 0xA0, 0x00, 0x80, 0x38, 771 | 0xEF, 0xA0, 0x00, 0x0C, 772 | 0x38, 0x34, 0xA0, 0x00, 773 | 0x80, 0x38, 0xEF, 0xA0, 774 | 0x00, 0x0E, 0x38, 0x34, 775 | 0xA0, 0x00, 0x80, 0x38, 776 | 0x60, 0xFD, 0xC4, 0x22, 777 | 0xA0, 0x00, 0x02, 0xEF, 778 | 0xA0, 0x00, 0x04, 0x38, 779 | 0x34, 0xA0, 0x00, 0x03, 780 | 0x3A, 0xA0, 0x00, 0x02, 781 | 0x60, 0xFA, 0xC6, 0xA0, 782 | 0x00, 0x80, 0x38, 0xEF, 783 | 0xA0, 0x00, 0x06, 0x38, 784 | 0x34, 0xA0, 0x00, 0x03, 785 | 0x3A, 0xA0, 0x00, 0x02, 786 | 0x60, 0xFA, 0xB2, 0xA0, 787 | 0x00, 0x80, 0x38, 0xEF, 788 | 0xA0, 0x00, 0x0C, 0x38, 789 | 0x34, 0xA0, 0x00, 0x03, 790 | 0x3A, 0xA0, 0x00, 0x02, 791 | 0x60, 0xFA, 0x9E, 0xA0, 792 | 0x00, 0x80, 0x38, 0xEF, 793 | 0xA0, 0x00, 0x0E, 0x38, 794 | 0x34, 0xA0, 0x00, 0x03, 795 | 0x3A, 0xA0, 0x00, 0x02, 796 | 0x60, 0xFA, 0x8A, 0xA0, 797 | 0x00, 0x80, 0x38, 0x60, 798 | 0xFD, 0x6D, 0x22, 0xA0, 799 | 0x00, 0x01, 0xEF, 0xA0, 800 | 0x00, 0x04, 0x38, 0x34, 801 | 0xA0, 0x00, 0x01, 0x60, 802 | 0xFA, 0x73, 0xA0, 0x00, 803 | 0x80, 0x38, 0xEF, 0xA0, 804 | 0x00, 0x06, 0x38, 0x34, 805 | 0xA0, 0x00, 0x01, 0x60, 806 | 0xFA, 0x63, 0xA0, 0x00, 807 | 0x80, 0x38, 0xEF, 0xA0, 808 | 0x00, 0x0C, 0x38, 0x34, 809 | 0xA0, 0x00, 0x01, 0x60, 810 | 0xFA, 0x53, 0xA0, 0x00, 811 | 0x80, 0x38, 0xEF, 0xA0, 812 | 0x00, 0x0E, 0x38, 0x34, 813 | 0xA0, 0x00, 0x01, 0x60, 814 | 0xFA, 0x43, 0xA0, 0x00, 815 | 0x80, 0x38, 0x60, 0xFD, 816 | 0x26, 0x22, 0x40, 0x00, 817 | 0x0B, 0xA0, 0x00, 0x00, 818 | 0x04, 0xEF, 0xA0, 0x00, 819 | 0x10, 0x38, 0x15, 0x02, 820 | 0xEF, 0xA0, 0x00, 0x06, 821 | 0x38, 0x34, 0xEF, 0xA0, 822 | 0x00, 0x0E, 0x38, 0x35, 823 | 0xEF, 0xA0, 0x00, 0x04, 824 | 0x38, 0x34, 0xEF, 0xA0, 825 | 0x00, 0x0C, 0x38, 0x35, 826 | 0xEF, 0xA0, 0x00, 0x0A, 827 | 0x38, 0xB4, 0xA1, 0x25, 828 | 0x35, 0x22, 0x40, 0xFE, 829 | 0x85, 0xA0, 0x01, 0x18, 830 | 0x80, 0x2C, 0x37, 0xA0, 831 | 0x00, 0x6F, 0x80, 0x28, 832 | 0x37, 0xA0, 0x00, 0x7C, 833 | 0x80, 0x2A, 0x37, 0xA0, 834 | 0x01, 0x2F, 0x17, 0xA0, 835 | 0x01, 0x17, 0x14, 0x60, 836 | 0xF9, 0xE2, 0xA0, 0x00, 837 | 0x20, 0x38, 0x60, 0xF9, 838 | 0xF9, 0xA0, 0x00, 0x05, 839 | 0x60, 0xF9, 0xDE, 0xEF, 840 | 0x21, 0x21, 0x35, 0xA0, 841 | 0x01, 0x17, 0x14, 0x60, 842 | 0xF9, 0xCA, 0xA0, 0x00, 843 | 0x20, 0x38, 0x60, 0xFA, 844 | 0x2C, 0xA0, 0x00, 0x05, 845 | 0x60, 0xF9, 0xC6, 0xEF, 846 | 0x35, 0xA0, 0x00, 0x03, 847 | 0xEF, 0x34, 0xA0, 0x00, 848 | 0x80, 0x38, 0xEF, 0x21, 849 | 0x21, 0x34, 0xA0, 0x00, 850 | 0x80, 0x38, 0xA0, 0x00, 851 | 0x80, 0xEF, 0x34, 0x39, 852 | 0xA0, 0x00, 0x01, 0x39, 853 | 0xA0, 0x00, 0x80, 0xEF, 854 | 0x21, 0x21, 0x34, 0x39, 855 | 0xA0, 0x00, 0x01, 0x39, 856 | 0x60, 0xFC, 0x84, 0x22, 857 | 0xA0, 0x01, 0x17, 0x14, 858 | 0x60, 0xF9, 0x89, 0xA0, 859 | 0x00, 0x60, 0x38, 0x60, 860 | 0xF9, 0xA0, 0xA0, 0x00, 861 | 0x05, 0x60, 0xF9, 0x85, 862 | 0xEF, 0x21, 0x21, 0x35, 863 | 0xA0, 0x01, 0x17, 0x14, 864 | 0x60, 0xF9, 0x71, 0xA0, 865 | 0x00, 0x60, 0x38, 0x60, 866 | 0xF9, 0xD3, 0xA0, 0x00, 867 | 0x05, 0x60, 0xF9, 0x6D, 868 | 0xEF, 0x35, 0xA0, 0x00, 869 | 0x03, 0xEF, 0x34, 0xA0, 870 | 0x00, 0x80, 0x38, 0xEF, 871 | 0x21, 0x21, 0x34, 0xA0, 872 | 0x00, 0x80, 0x38, 0xA0, 873 | 0x00, 0x80, 0xEF, 0x34, 874 | 0x39, 0xA0, 0x00, 0x01, 875 | 0x39, 0xA0, 0x00, 0x80, 876 | 0xEF, 0x21, 0x21, 0x34, 877 | 0x39, 0xA0, 0x00, 0x01, 878 | 0x39, 0x60, 0xFC, 0x2B, 879 | 0x22, 0xA0, 0x01, 0x18, 880 | 0x80, 0x2C, 0x37, 0xA0, 881 | 0x00, 0x89, 0x80, 0x28, 882 | 0x37, 0xA0, 0x00, 0x7C, 883 | 0x80, 0x2A, 0x37, 0xA0, 884 | 0x31, 0x2F, 0x17, 0xA0, 885 | 0x00, 0x00, 0x62, 0x6C, 886 | 0x67, 0xA0, 0x0A, 0xAF, 887 | 0x80, 0x08, 0x37, 0xA0, 888 | 0x0F, 0xFC, 0x80, 0x0A, 889 | 0x37, 0xA0, 0x0F, 0xAA, 890 | 0x80, 0x0C, 0x37, 0xA0, 891 | 0x01, 0x00, 0x80, 0x22, 892 | 0x37, 0xA0, 0x00, 0xF0, 893 | 0x80, 0x24, 0x37, 0xA0, 894 | 0x00, 0x00, 0x62, 0x6C, 895 | 896 | 0x00, 0x00, 0x00, 0x00, 897 | 0x00, 0x00, 0x00, 0x00, 898 | 0x00, 0x00, 0x00, 0x00, 899 | 0x00, 0x00, 0x00, 0x00, 900 | 0x00, 0x00, 0x00, 0x00, 901 | 0x00, 0x00, 0x00, 0x00, 902 | 0x00, 0x00, 0x00, 0x00, 903 | 0x00, 0x00, 0x00, 0x00, 904 | 0x00, 0x00, 0x00, 0x00, 905 | 0x00, 0x00, 0x00, 0x00, 906 | 0x00, 0x00, 0x00, 0x00, 907 | 0x00, 0x00, 0x00, 0x00, 908 | 0x00, 0x00, 0x00, 0x00, 909 | 0x00, 0x00, 0x00, 0x00, 910 | 0x00, 0x00, 0x00, 0x00, 911 | 0x00, 0x00, 0x00, 0x00, 912 | 0x00, 0x00, 0x00, 0x00, 913 | 0x00, 0x00, 0x00, 0x00, 914 | 0x00, 0x00, 0x00, 0x00, 915 | 0x00, 0x00, 0x00, 0x00, 916 | 0x00, 0x00, 0x00, 0x00, 917 | 0x00, 0x00, 0x00, 0x00, 918 | 0x00, 0x00, 0x00, 0x00, 919 | 0x00, 0x00, 0x00, 0x00, 920 | 0x00, 0x00, 0x00, 0x00, 921 | 0x00, 0x00, 0x00, 0x00, 922 | 0x00, 0x00, 0x00, 0x00, 923 | 0x00, 0x00, 0x00, 0x00, 924 | 0x00, 0x00, 0x00, 0x00, 925 | 0x00, 0x00, 0x00, 0x00, 926 | 0x00, 0x00, 0x00, 0x00, 927 | 0x00, 0x00, 0x00, 0x00, 928 | 0x00, 0x00, 0x00, 0x00, 929 | 0x00, 0x00, 0x00, 0x00, 930 | 0x00, 0x00, 0x00, 0x00, 931 | 0x00, 0x00, 0x00, 0x00, 932 | 0x00, 0x00, 0x00, 0x00, 933 | 0x00, 0x00, 0x00, 0x00 934 | }; 935 | 936 | static uint32_t rdaddr; 937 | rdaddr = (uint32_t)(read_address); 938 | 939 | uint8_t rdata = uxn_rom_RAM_SP_RF_1( 940 | rdaddr, // read address 941 | 0, // write value 942 | 0 // write enable 943 | ); 944 | 945 | return rdata; 946 | } -------------------------------------------------------------------------------- /top_test.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity top_test is 6 | end entity; 7 | 8 | architecture sim of top_test is 9 | signal test_clk : std_logic := '0'; 10 | signal test_controller_button : unsigned(0 downto 0) := to_unsigned(0, 1); 11 | signal test_is_visible_pixel : unsigned(0 downto 0) := to_unsigned(1, 1); 12 | signal test_is_vsync: unsigned(0 downto 0) := to_unsigned(0, 1); 13 | signal test_is_hsync: unsigned(0 downto 0) := to_unsigned(0, 1); 14 | signal test_rom_load_valid_byte : unsigned(0 downto 0) := to_unsigned(0, 1); 15 | signal test_rom_load_address : unsigned(15 downto 0) := x"0000"; 16 | signal test_rom_load_value : unsigned(7 downto 0) := x"00"; 17 | constant clk_period : time := 65 ns; 18 | begin 19 | -- The Device Under Test (DUT) 20 | i_top : entity work.top 21 | port map( 22 | clk_None => test_clk, 23 | uxn_top_controller0_up => test_controller_button, 24 | uxn_top_controller0_down => test_controller_button, 25 | uxn_top_controller0_left => test_controller_button, 26 | uxn_top_controller0_right => test_controller_button, 27 | uxn_top_controller0_a => test_controller_button, 28 | uxn_top_controller0_b => test_controller_button, 29 | uxn_top_controller0_x => test_controller_button, 30 | uxn_top_controller0_y => test_controller_button, 31 | uxn_top_controller0_l => test_controller_button, 32 | uxn_top_controller0_r => test_controller_button, 33 | uxn_top_controller0_select => test_controller_button, 34 | uxn_top_controller0_start => test_controller_button, 35 | uxn_top_is_visible_pixel => test_is_visible_pixel, 36 | uxn_top_vsync => test_is_vsync, 37 | uxn_top_hsync => test_is_hsync, 38 | uxn_top_rom_load_valid_byte => test_rom_load_valid_byte, 39 | uxn_top_rom_load_address => test_rom_load_address, 40 | uxn_top_rom_load_value => test_rom_load_value 41 | ); 42 | test_clk <= not test_clk after clk_period / 2; 43 | end architecture; -------------------------------------------------------------------------------- /uxn.c: -------------------------------------------------------------------------------- 1 | #include "uintN_t.h" // uintN_t types for any N 2 | #include "intN_t.h" // intN_t types for any N 3 | 4 | #include "uxn_opcodes.h" 5 | #include "uxn_ram_main.h" 6 | #include "uxn_constants.h" 7 | #include 8 | 9 | #if DEBUG 10 | #include "roms/screen_blending.h" 11 | #endif 12 | 13 | // RULES: 14 | // - cannot write to a global variable from more than one function (unless you use clock domain crossing) 15 | // - no switch statements (C AST node cannot be parsed to logic) 16 | // - only one return per function 17 | // - no ++ or -- operators 18 | 19 | // Build with Docker pipelinec image: 20 | // docker run -v $(pwd):/workdir pipelinec pipelinec uxn.c 21 | 22 | // note about RAMs 23 | // https://github.com/JulianKemmerer/PipelineC/wiki/Automatically-Generated-Functionality#rams 24 | 25 | typedef struct boot_step_result_t { 26 | uint1_t is_valid_byte; // is the most recent byte valid? 27 | uint1_t is_finished; // is the last byte read? 28 | uint8_t rom_byte; // the most recent byte read 29 | uint16_t ram_address; // RAM address to copy byte to (if valid) 30 | } boot_step_result_t; 31 | 32 | boot_step_result_t step_boot() { 33 | static uint1_t boot_phase = 0; 34 | static uint16_t rom_address = 0; 35 | static boot_step_result_t result = {0, 0, 0, 0xFF}; // why ram_address starts at "0xFF"? first ROM byte goes to RAM 0x0100, but keep the RAM address behind by 1 due to latency 36 | 37 | result.rom_byte = read_rom_byte(rom_address); 38 | rom_address += boot_phase; // increase when boot phase is 1, not when it's zero (allow for two reads) 39 | result.ram_address += boot_phase; 40 | result.is_finished = boot_phase == 0 ? 0 : (rom_address > (ROM_SIZE - 1) ? 1 : 0); 41 | result.is_valid_byte = boot_phase; 42 | boot_phase += 1; 43 | 44 | return result; 45 | } 46 | 47 | typedef struct cpu_step_result_t { 48 | uint1_t is_ram_write; 49 | uint16_t u16_addr; // ram address read / write, or vram address write 50 | 51 | uint1_t is_vram_write; 52 | uint1_t vram_write_layer; 53 | 54 | uint1_t is_device_ram_write; 55 | uint8_t device_ram_address; 56 | 57 | uint1_t is_waiting; 58 | 59 | uint8_t u8_value; 60 | 61 | } cpu_step_result_t; 62 | 63 | cpu_step_result_t step_cpu(uint8_t previous_ram_read_value, uint8_t previous_device_ram_read, uint32_t time, uint8_t controller0_buttons, uint1_t is_new_frame, uint1_t has_screen_vector, uint1_t has_controller_vector, uint16_t screen_vector, uint16_t controller_vector) { 64 | static uint16_t pc = 0x0100; 65 | static uint8_t ins = 0; 66 | static uint12_t step_cpu_phase = 0; 67 | static uint1_t is_ins_done = 0, is_waiting = 0, pending_frame = 0, pending_controller = 0; 68 | static uint8_t last_controller0 = 0; 69 | static cpu_step_result_t cpu_step_result = {0, 0, 0, 0, 0, 0, 0, 0}; 70 | 71 | if (has_controller_vector & (controller0_buttons != last_controller0 ? 1 : 0)) { 72 | pending_controller = 1; 73 | } 74 | 75 | pending_frame = is_new_frame & has_screen_vector; 76 | pc = is_waiting ? (pending_frame ? screen_vector : (pending_controller ? controller_vector : pc)) : pc; 77 | is_waiting = pending_frame | pending_controller ? 0 : is_waiting; 78 | pending_controller = pc == controller_vector ? 0 : pending_controller; 79 | 80 | last_controller0 = controller0_buttons; 81 | 82 | if (step_cpu_phase == 0) { 83 | is_ins_done = 0; 84 | cpu_step_result.u16_addr = pc; // START 85 | cpu_step_result.is_ram_write = 0; 86 | cpu_step_result.is_vram_write = 0; 87 | cpu_step_result.is_device_ram_write = 0; 88 | } 89 | else if (step_cpu_phase == 1) { 90 | pc += 1; 91 | } 92 | else { 93 | ins = step_cpu_phase == 2 ? previous_ram_read_value : ins; 94 | eval_opcode_result_t eval_opcode_result = eval_opcode_phased(step_cpu_phase - 2, ins, pc, controller0_buttons, time, previous_ram_read_value, previous_device_ram_read); 95 | pc = eval_opcode_result.is_pc_updated ? eval_opcode_result.u16_value : pc; 96 | cpu_step_result.is_ram_write = eval_opcode_result.is_ram_write; 97 | cpu_step_result.u16_addr = eval_opcode_result.u16_value; 98 | cpu_step_result.is_vram_write = eval_opcode_result.is_vram_write; 99 | cpu_step_result.vram_write_layer = eval_opcode_result.vram_write_layer; 100 | cpu_step_result.device_ram_address = eval_opcode_result.device_ram_address; 101 | cpu_step_result.is_device_ram_write = eval_opcode_result.is_device_ram_write; 102 | cpu_step_result.u8_value = eval_opcode_result.u8_value; 103 | is_waiting = eval_opcode_result.is_waiting; 104 | is_ins_done = eval_opcode_result.is_opc_done; 105 | } 106 | 107 | if (is_ins_done | is_waiting) { 108 | step_cpu_phase = 0; 109 | } else { 110 | step_cpu_phase = (pc(15, 8) == 0) ? 0 : (step_cpu_phase + 1); // stop if PC == 0 111 | } 112 | 113 | cpu_step_result.is_waiting = is_waiting; 114 | 115 | return cpu_step_result; 116 | } 117 | 118 | typedef struct draw_command_t { 119 | uint16_t vram_address; 120 | uint2_t color; 121 | uint1_t layer; 122 | uint1_t is_fill; 123 | uint1_t fill_left; 124 | uint1_t fill_top; 125 | uint1_t is_valid; 126 | } draw_command_t; 127 | 128 | uint2_t step_gpu( 129 | uint1_t is_active_drawing_area, 130 | uint1_t is_vram_write, 131 | uint1_t vram_write_layer, 132 | uint16_t vram_address, 133 | uint8_t vram_value, 134 | uint1_t has_screen_vector, 135 | uint1_t is_cpu_waiting, 136 | uint1_t vsync, // cycle 0 of every frame (new frame) 137 | uint1_t hsync // cycle 3 of every horizontal line (new line) 138 | ) { 139 | static uint2_t gpu_color = 0; 140 | static uint15_t queue_read_ptr = 0; 141 | static uint15_t queue_write_ptr = 0; 142 | static draw_command_t current_queue_item = {0, 0, 0, 0, 0, 0, 0}; 143 | static uint24_t queue_write_value = 0; 144 | static uint24_t queue_read_value = 0; 145 | static uint1_t queue_write_enable = 0; 146 | static uint2_t queue_phase = 0, bg_pixel_color = 0, fg_pixel_color = 0, adjusted_write_value_bg = 0, adjusted_write_value_fg = 0; 147 | static uint1_t adjusted_write_enable_bg = 0, adjusted_write_enable_fg = 0; 148 | static uint17_t adjusted_read_address = 0, adjusted_write_address = 0; 149 | 150 | // current fill 151 | static uint8_t fill_x0, fill_y0, fill_x1, fill_y1, x, y; 152 | static uint2_t fill_color; 153 | static uint1_t is_new_fill_row, is_last_fill_col, is_fill_active, fill_layer, is_fill_top, is_fill_left, is_fill_pixel0, is_fill_pixel1; 154 | static uint16_t pixel_counter = 0; // 256*256, max = 65535, visible pixels only 155 | static uint20_t cycle_counter = 0; // max 1024x1024, includes all pixels 156 | static uint20_t buffer_swap_begin_cycle = 0; // cycle at which we begin swapping buffers 157 | static uint16_t buffer_swap_cycle = 0; 158 | static uint16_t tmp16 = 0; 159 | static uint1_t is_caught_up = 0, is_read_ready = 0, is_copy_phase = 0, is_copy_start_cycle = 0, can_swap_buffers = 0; 160 | 161 | is_caught_up = queue_read_ptr == queue_write_ptr ? 1 : 0; 162 | is_read_ready = queue_phase == 2 ? 1 : 0; 163 | 164 | if (~current_queue_item.is_valid & ~is_caught_up & is_read_ready & ~is_copy_phase) { // ready for next item 165 | current_queue_item.vram_address = queue_read_value(15, 0); 166 | current_queue_item.color = queue_read_value(17, 16); 167 | current_queue_item.fill_top = queue_read_value(18); 168 | current_queue_item.fill_left = queue_read_value(19); 169 | current_queue_item.is_fill = queue_read_value(20); 170 | current_queue_item.layer = queue_read_value(21); 171 | current_queue_item.is_valid = 1; 172 | queue_phase = 0; 173 | queue_read_ptr += 1; 174 | } 175 | 176 | if (is_vram_write) { // queue up new draw command (if given) 177 | queue_write_value = uint24_uint16_0(0, vram_address); 178 | queue_write_value = uint24_uint5_16(queue_write_value, vram_value(4, 0)); // 0b000FLTCC (F = Fill, L = Left, T = Top, C = Color) 179 | queue_write_value = uint24_uint1_21(queue_write_value, vram_write_layer); 180 | queue_phase = is_caught_up ? 0 : queue_phase; 181 | queue_write_ptr += 1; 182 | } 183 | 184 | queue_write_enable = is_vram_write; 185 | queue_phase = queue_phase == 2 ? 2 : queue_phase + 1; 186 | tmp16 = current_queue_item.vram_address; 187 | 188 | if (current_queue_item.is_valid & current_queue_item.is_fill & ~is_fill_active & ~is_copy_phase) { 189 | is_fill_top = current_queue_item.fill_top; 190 | is_fill_left = current_queue_item.fill_left; 191 | fill_y1 = is_fill_top ? tmp16(15, 8) : 255; 192 | fill_x1 = is_fill_left ? tmp16(7, 0) : 255; 193 | fill_y0 = is_fill_top ? 0 : tmp16(15, 8); 194 | fill_x0 = is_fill_left ? 0 : tmp16(7, 0); 195 | fill_layer = current_queue_item.layer; 196 | fill_color = current_queue_item.color; 197 | is_new_fill_row = 0; 198 | is_last_fill_col = 0; 199 | y = fill_y0; 200 | x = fill_x0; 201 | is_fill_active = 1; 202 | } else if (current_queue_item.is_valid & ~current_queue_item.is_fill & ~is_copy_phase) { 203 | y = tmp16(15, 8); 204 | x = tmp16(7, 0); 205 | } 206 | 207 | // READ: from upper buffer if copy phase, lower buffer otherwise 208 | adjusted_read_address = uint17_uint16_0(0, is_copy_phase ? buffer_swap_cycle : pixel_counter); 209 | adjusted_read_address = uint17_uint1_16(adjusted_read_address, is_copy_phase); 210 | 211 | // WRITE: to lower buffer if copy phase, upper buffer otherwise 212 | adjusted_write_address = is_copy_phase ? uint17_uint16_0(0, buffer_swap_cycle - 2) : uint17_uint8_8(0, y); 213 | adjusted_write_address = is_copy_phase ? adjusted_write_address : uint17_uint8_0(adjusted_write_address, x); 214 | adjusted_write_address = uint17_uint1_16(adjusted_write_address, ~is_copy_phase); 215 | 216 | is_new_fill_row = (x == fill_x1) ? 1 : 0; 217 | is_last_fill_col = (y == fill_y1) ? 1 : 0; 218 | y = (is_new_fill_row & ~is_copy_phase) ? (y + 1) : y; 219 | x = is_copy_phase ? x : (is_new_fill_row ? fill_x0 : x + 1); 220 | is_fill_pixel0 = is_fill_active & (~fill_layer); 221 | is_fill_pixel1 = is_fill_active & fill_layer; 222 | 223 | adjusted_write_value_bg = is_copy_phase ? bg_pixel_color : (is_fill_pixel0 ? fill_color : current_queue_item.color); 224 | adjusted_write_value_fg = is_copy_phase ? fg_pixel_color : (is_fill_pixel1 ? fill_color : current_queue_item.color); 225 | 226 | adjusted_write_enable_bg = is_copy_phase | is_fill_pixel0 | (~is_fill_active & current_queue_item.is_valid & (~current_queue_item.layer)); 227 | adjusted_write_enable_fg = is_copy_phase | is_fill_pixel1 | (~is_fill_active & current_queue_item.is_valid & current_queue_item.layer); 228 | 229 | bg_pixel_color = bg_vram_update( 230 | adjusted_read_address, // read address 231 | adjusted_write_address, // write address 232 | adjusted_write_value_bg, // write value 233 | adjusted_write_enable_bg // write enable 234 | ); 235 | 236 | fg_pixel_color = fg_vram_update( 237 | adjusted_read_address, // read address 238 | adjusted_write_address, // write address 239 | adjusted_write_value_fg, // write value 240 | adjusted_write_enable_fg // write enable 241 | ); 242 | 243 | queue_read_value = draw_queue_update( 244 | queue_read_ptr, // read address 245 | queue_write_ptr, // write address 246 | queue_write_value, // write value 247 | queue_write_enable // write enable 248 | ); 249 | 250 | pixel_counter = vsync ? 0 : (is_active_drawing_area ? (pixel_counter + 1) : pixel_counter); 251 | buffer_swap_begin_cycle = vsync ? cycle_counter - 65538 : buffer_swap_begin_cycle; 252 | cycle_counter = vsync ? 0 : cycle_counter + 1; 253 | is_copy_start_cycle = cycle_counter == buffer_swap_begin_cycle ? 1 : 0; 254 | 255 | can_swap_buffers = is_copy_start_cycle ? ((is_cpu_waiting | ~has_screen_vector) ? 1 : ~can_swap_buffers) : can_swap_buffers; 256 | is_copy_phase = ~vsync & (is_copy_phase | (is_copy_start_cycle & can_swap_buffers)); 257 | 258 | buffer_swap_cycle = (vsync | is_copy_start_cycle) ? 0 : (buffer_swap_cycle + is_copy_phase); 259 | 260 | is_fill_active = is_fill_active ? ~(is_new_fill_row & is_last_fill_col) : 0; 261 | current_queue_item.is_valid = is_fill_active; 262 | gpu_color = fg_pixel_color == 0 ? bg_pixel_color : fg_pixel_color; 263 | 264 | return gpu_color; 265 | } 266 | 267 | typedef struct vector_snoop_result_t { 268 | uint16_t screen; 269 | uint16_t controller; 270 | uint1_t has_screen_vector; 271 | uint1_t has_controller_vector; 272 | } vector_snoop_result_t; 273 | 274 | vector_snoop_result_t vector_snoop(uint8_t device_ram_address, uint8_t device_ram_value, uint1_t is_device_ram_write) { 275 | static vector_snoop_result_t vectors = {0, 0, 0, 0}; 276 | 277 | if (is_device_ram_write) { 278 | if (device_ram_address == 0x20) { 279 | vectors.screen = uint16_uint8_8(vectors.screen, device_ram_value); 280 | vectors.has_screen_vector = device_ram_value == 0 ? 0 : 1; 281 | } else if (device_ram_address == 0x21) { 282 | vectors.screen = uint16_uint8_0(vectors.screen, device_ram_value); 283 | } else if (device_ram_address == 0x80) { 284 | vectors.controller = uint16_uint8_8(vectors.controller, device_ram_value); 285 | vectors.has_controller_vector = device_ram_value == 0 ? 0 : 1; 286 | } else if (device_ram_address == 0x81) { 287 | vectors.controller = uint16_uint8_0(vectors.controller, device_ram_value); 288 | } 289 | } 290 | 291 | return vectors; 292 | } 293 | 294 | uint16_t palette_snoop(uint8_t device_ram_address, uint8_t device_ram_value, uint1_t is_device_ram_write, uint2_t gpu_step_color) { 295 | static uint12_t color[4] = {0xFFF, 0x000, 0x7DB, 0xF62}; 296 | static uint5_t device_ram_addr_7dt3 = 0; 297 | static uint4_t color_cmp_0 = 0, color_cmp_1 = 0; 298 | static uint2_t device_ram_addr_2dt1 = 0, index0 = 0, index1 = 0; 299 | static uint1_t is_palette_range = 0, device_ram_addr_0 = 0; 300 | 301 | device_ram_addr_7dt3 = device_ram_address(7, 3); 302 | is_palette_range = device_ram_addr_7dt3 == 1 ? 1 : 0; 303 | 304 | if (is_device_ram_write & is_palette_range) { 305 | device_ram_addr_2dt1 = device_ram_address(2, 1); 306 | device_ram_addr_0 = device_ram_address(0); 307 | color_cmp_0 = device_ram_value(7, 4); 308 | color_cmp_1 = device_ram_value(3, 0); 309 | index0 = uint2_uint1_1(0, device_ram_addr_0); 310 | index1 = index0 | 0b01; 311 | if (device_ram_addr_2dt1 == 0) { 312 | color[index0] = uint12_uint4_8(color[index0], color_cmp_0); 313 | color[index1] = uint12_uint4_8(color[index1], color_cmp_1); 314 | } 315 | else if (device_ram_addr_2dt1 == 1) { 316 | color[index0] = uint12_uint4_4(color[index0], color_cmp_0); 317 | color[index1] = uint12_uint4_4(color[index1], color_cmp_1); 318 | } 319 | else if (device_ram_addr_2dt1 == 2) { 320 | color[index0] = uint12_uint4_0(color[index0], color_cmp_0); 321 | color[index1] = uint12_uint4_0(color[index1], color_cmp_1); 322 | } 323 | } 324 | 325 | return color[gpu_step_color]; 326 | } 327 | 328 | uint8_t bcd_to_decimal(uint8_t bcd_value) { 329 | uint8_t tens_digit = 0x0A * uint8_uint4_0(0, bcd_value(7, 4)); 330 | uint8_t ones_digit = uint8_uint4_0(0, bcd_value(3, 0)); 331 | return tens_digit + ones_digit; 332 | } 333 | 334 | uint32_t step_time(uint1_t bcd_is_valid, uint32_t bcd_time, uint1_t vsync) { 335 | 336 | static uint8_t ticks = 0; 337 | static uint8_t seconds = 0; 338 | static uint8_t minutes = 0; 339 | static uint8_t hours = 0; 340 | static uint8_t day_of_week = 0; 341 | static uint32_t result = 0; 342 | static uint1_t has_set_time = 0; 343 | 344 | if (bcd_is_valid & ~has_set_time) { 345 | ticks = 0; 346 | day_of_week = bcd_to_decimal(bcd_time(31, 24)); // TODO: maybe this could be simplified 347 | hours = bcd_to_decimal(bcd_time(23, 16)); 348 | minutes = bcd_to_decimal(bcd_time(15, 8)); 349 | seconds = bcd_to_decimal(bcd_time(7, 0)); 350 | result = uint32_uint8_0(0, seconds); 351 | result = uint32_uint8_8(result, minutes); 352 | result = uint32_uint8_16(result, hours); 353 | result = uint32_uint8_24(result, day_of_week); 354 | has_set_time = 1; 355 | } else if (vsync) { 356 | ticks += 1; 357 | seconds = ticks == 60 ? seconds + 1 : seconds; 358 | minutes = seconds == 60 ? minutes + 1 : minutes; 359 | hours = minutes == 60 ? hours + 1 : hours; 360 | day_of_week = hours == 24 ? day_of_week + 1 : day_of_week; 361 | ticks = ticks == 60 ? 0 : ticks; 362 | seconds = seconds == 60 ? 0 : seconds; 363 | minutes = minutes == 60 ? 0 : minutes; 364 | hours = hours == 24 ? 0 : hours; 365 | day_of_week = day_of_week == 7 ? 0 : day_of_week; 366 | // TODO: increment and populate day / month / year 367 | 368 | result = uint32_uint8_0(0, seconds); 369 | result = uint32_uint8_8(result, minutes); 370 | result = uint32_uint8_16(result, hours); 371 | result = uint32_uint8_24(result, day_of_week); 372 | } 373 | 374 | return result; 375 | } 376 | 377 | // #pragma PART "5CGXFC9E7F35C8" // TODO: try quartus step here for Cyclone V 378 | #pragma MAIN uxn_top 379 | uint16_t uxn_top( 380 | uint1_t rtc_valid, // is_valid 381 | uint32_t rtc_time_bcd, // BCD of current time - example 0x00235959 (bits 26 through 24 = day of week 0-6) 382 | uint1_t controller0_up, 383 | uint1_t controller0_down, 384 | uint1_t controller0_left, 385 | uint1_t controller0_right, 386 | uint1_t controller0_a, 387 | uint1_t controller0_b, 388 | uint1_t controller0_x, 389 | uint1_t controller0_y, 390 | uint1_t controller0_l, 391 | uint1_t controller0_r, 392 | uint1_t controller0_select, 393 | uint1_t controller0_start, 394 | uint1_t vsync, // cycle 0 of every frame (new frame) 395 | uint1_t hsync, // cycle 3 of every horizontal line (new line) 396 | uint1_t is_visible_pixel, 397 | uint1_t rom_load_valid_byte, 398 | uint16_t rom_load_address, 399 | uint8_t rom_load_value 400 | ) { 401 | static uint24_t boot_check = 0; 402 | static uint16_t uxn_eval_result = 0; 403 | static uint1_t is_booted = 0; 404 | static uint2_t gpu_color; 405 | static cpu_step_result_t cpu_step_result; 406 | static uint1_t is_ram_write = 0; 407 | static uint16_t u16_addr = 0x00FF; // ram address, or occasionally vram write addr 408 | static vector_snoop_result_t vectors = {0, 0, 0, 0}; 409 | static uint8_t ram_write_value = 0; 410 | static uint8_t ram_read_value = 0; 411 | static uint8_t device_ram_address = 0; 412 | static uint8_t device_ram_read_value = 0; 413 | static uint1_t is_device_ram_write = 0; 414 | static uint1_t is_vram_write = 0; 415 | static uint1_t vram_write_layer = 0; 416 | static uint8_t vram_value = 0; 417 | static uint8_t controller0_buttons = 0; 418 | static uint32_t time_reg = 0; 419 | 420 | time_reg = step_time(rtc_valid, rtc_time_bcd, vsync); 421 | 422 | if (~is_booted) { 423 | #if DEBUG 424 | // (C-Array-Style) 425 | boot_step_result_t boot_step_result = step_boot(); 426 | is_ram_write = boot_step_result.is_valid_byte; 427 | u16_addr = boot_step_result.ram_address; 428 | ram_write_value = boot_step_result.rom_byte; 429 | is_booted = boot_step_result.is_finished; 430 | #else 431 | boot_check = rom_load_valid_byte ? 0 : boot_check + 1; 432 | is_ram_write = rom_load_valid_byte; 433 | u16_addr = rom_load_address + 0x0100; 434 | ram_write_value = rom_load_value; 435 | is_booted = boot_check == 0xFFFFFF ? 1 : 0; 436 | #endif 437 | } else { 438 | controller0_buttons = uint8_uint1_0(0, controller0_a); 439 | controller0_buttons = uint8_uint1_1(controller0_buttons, controller0_b); 440 | controller0_buttons = uint8_uint1_2(controller0_buttons, controller0_start); 441 | controller0_buttons = uint8_uint1_3(controller0_buttons, controller0_select); 442 | controller0_buttons = uint8_uint1_4(controller0_buttons, controller0_up); 443 | controller0_buttons = uint8_uint1_5(controller0_buttons, controller0_down); 444 | controller0_buttons = uint8_uint1_6(controller0_buttons, controller0_left); 445 | controller0_buttons = uint8_uint1_7(controller0_buttons, controller0_right); 446 | cpu_step_result = step_cpu(ram_read_value, device_ram_read_value, time_reg, controller0_buttons, vsync, vectors.has_screen_vector, vectors.has_controller_vector, vectors.screen, vectors.controller); 447 | is_ram_write = cpu_step_result.is_ram_write; 448 | u16_addr = cpu_step_result.u16_addr; 449 | device_ram_address = cpu_step_result.device_ram_address; 450 | is_device_ram_write = cpu_step_result.is_device_ram_write; 451 | ram_write_value = cpu_step_result.u8_value; 452 | is_vram_write = cpu_step_result.is_vram_write; 453 | vram_write_layer = cpu_step_result.vram_write_layer; 454 | vram_value = cpu_step_result.u8_value; 455 | } 456 | 457 | ram_read_value = main_ram_update( 458 | u16_addr, 459 | ram_write_value, // shared register, write only to either ram or device ram in one cycle 460 | is_ram_write 461 | ); 462 | 463 | device_ram_read_value = device_ram_update( 464 | device_ram_address, 465 | ram_write_value, // shared register, write only to either ram or device ram in one cycle 466 | is_device_ram_write 467 | ); 468 | 469 | gpu_color = step_gpu(is_visible_pixel, is_vram_write, vram_write_layer, u16_addr, vram_value, vectors.has_screen_vector, cpu_step_result.is_waiting, vsync, hsync); 470 | uxn_eval_result = palette_snoop(device_ram_address, ram_write_value, is_device_ram_write, gpu_color); 471 | vectors = vector_snoop(device_ram_address, ram_write_value, is_device_ram_write); 472 | 473 | return uxn_eval_result; 474 | } -------------------------------------------------------------------------------- /uxn_constants.h: -------------------------------------------------------------------------------- 1 | #define DEBUG 0 -------------------------------------------------------------------------------- /uxn_device.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | #include 4 | 5 | #pragma once 6 | #include "uxn_ram_device.h" 7 | #pragma once 8 | #include "uxn_ram_screen.h" 9 | #pragma once 10 | #include "uxn_stack.h" 11 | 12 | typedef struct device_in_result_t { 13 | uint8_t device_ram_address; 14 | 15 | uint8_t dei_value; 16 | uint1_t is_dei_done; 17 | } device_in_result_t; 18 | 19 | typedef struct device_out_result_t { 20 | uint1_t is_device_ram_write; 21 | uint8_t device_ram_address; 22 | 23 | uint1_t is_vram_write; 24 | uint1_t vram_write_layer; 25 | uint16_t u16_addr; // vram_address or ram_address 26 | uint8_t u8_value; // device ram write value, RAM write value 27 | 28 | uint1_t is_deo_done; 29 | } device_out_result_t; 30 | 31 | typedef struct screen_blit_result_t { 32 | 33 | uint1_t is_vram_write; 34 | uint1_t vram_write_layer; 35 | uint16_t u16_addr; // vram_address write, or ram_address read 36 | 37 | uint8_t u8_value; 38 | 39 | uint1_t is_blit_done; 40 | } screen_blit_result_t; 41 | 42 | screen_blit_result_t screen_2bpp(uint12_t phase, uint16_t x1, uint16_t y1, uint4_t color, uint1_t fx, uint1_t fy, uint16_t ram_addr, uint8_t previous_ram_read) { 43 | static uint8_t blending[80] = { 44 | 0, 0, 0, 0, 1, 0, 1, 1, 2, 2, 0, 2, 3, 3, 3, 0, 45 | 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 46 | 1, 2, 3, 1, 1, 2, 3, 1, 1, 2, 3, 1, 1, 2, 3, 1, 47 | 2, 3, 1, 2, 2, 3, 1, 2, 2, 3, 1, 2, 2, 3, 1, 2, 48 | 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 49 | }; 50 | static uint16_t x, y; 51 | static uint1_t opaque = 0; 52 | static uint16_t c = 0; 53 | static uint8_t ch = 0; 54 | static uint8_t color8; 55 | static screen_blit_result_t result; 56 | static uint12_t phase_minus_two = 0; 57 | static uint4_t phase7_downto_4 = 0; 58 | static uint5_t phase7_downto_3 = 0; 59 | static uint3_t phase2_downto_0 = 0; 60 | static uint8_t phase7_downto_3_u8 = 0; 61 | static uint8_t sprite_rows[16]; 62 | static uint1_t is_x_in_bounds = 0, is_y_in_bounds = 0, is_new_row = 0; 63 | 64 | color8 = color; 65 | phase7_downto_4 = phase(7, 4); 66 | phase7_downto_3 = phase(7, 3); 67 | phase2_downto_0 = phase(2, 0); 68 | phase7_downto_3_u8 = phase7_downto_3; 69 | phase_minus_two = phase - 2; 70 | 71 | if (phase_minus_two(7, 4) == 0) { // phase 2 through 17 72 | sprite_rows[phase_minus_two] = previous_ram_read; 73 | } 74 | 75 | if (phase == 0) { 76 | opaque = blending[0x40 + color8]; 77 | x = x1 + (fx ? 0x0000 : 0x0007); 78 | y = y1 + (fy ? 0x0007 : 0x0000); 79 | } 80 | 81 | if (phase7_downto_4 == 0) { // if phase < 16 82 | result.is_vram_write = 0; 83 | result.u8_value = 0; 84 | result.is_blit_done = 0; 85 | result.u16_addr = ram_addr + phase; // RAM read 86 | } else { 87 | is_new_row = phase2_downto_0 == 0b00 ? 1 : 0; 88 | if (is_new_row) { 89 | c = uint16_uint8_8(0, sprite_rows[phase7_downto_3_u8 + 0x06]); 90 | c = uint16_uint8_0(c, sprite_rows[phase7_downto_3_u8 - 0x02]); 91 | } 92 | x = is_new_row ? (x1 + (fx ? 0x0000 : 0x0007)) : x; 93 | is_x_in_bounds = (x(15, 8) == 0x00) ? 1 : 0; 94 | is_y_in_bounds = (y(15, 8) == 0x00) ? 1 : 0; 95 | ch = uint8_uint1_5(0, c(8)); 96 | ch = uint8_uint1_4(ch, c(0)); 97 | result.u16_addr = uint16_uint8_8(0, y(7, 0)); 98 | result.u16_addr = uint16_uint8_0(result.u16_addr, x(7, 0)); 99 | result.is_vram_write = is_x_in_bounds & is_y_in_bounds & (opaque | (ch == 0x00 ? 0 : 1)); 100 | result.u8_value = blending[color8 + ch]; 101 | y = phase2_downto_0 == 0b111 ? (fy ? (y - 1) : (y + 1)) : y; 102 | result.is_blit_done = phase == 0x04F ? 1 : 0; 103 | x = (fx ? (x + 1) : (x - 1)); 104 | c >>= 1; 105 | } 106 | 107 | return result; 108 | } 109 | 110 | screen_blit_result_t screen_1bpp(uint12_t phase, uint16_t x1, uint16_t y1, uint4_t color, uint1_t fx, uint1_t fy, uint16_t ram_addr, uint8_t previous_ram_read) 111 | { 112 | static uint2_t blending[48] = { 113 | 0, 0, 0, 0, 1, 0, 1, 1, 2, 2, 0, 2, 3, 3, 3, 0, 114 | 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 115 | 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 116 | }; 117 | static uint16_t x, y; 118 | static uint1_t opaque = 0; 119 | static uint8_t c = 0; 120 | static uint8_t color8 = 0; 121 | static screen_blit_result_t result; 122 | static uint12_t phase_minus_two = 0; 123 | static uint5_t phase7_downto_3 = 0; 124 | static uint3_t phase2_downto_0 = 0; 125 | static uint8_t sprite_rows[8]; 126 | static uint1_t is_x_in_bounds = 0; 127 | static uint1_t is_y_in_bounds = 0; 128 | 129 | color8 = color; 130 | phase7_downto_3 = phase(7, 3); 131 | phase2_downto_0 = phase(2, 0); 132 | phase_minus_two = phase - 2; 133 | 134 | if (phase_minus_two(7, 3) == 0) { // phase 2 through 9 135 | sprite_rows[phase_minus_two] = previous_ram_read; 136 | } 137 | 138 | if (phase == 0) { 139 | opaque = blending[0x20 + color8]; 140 | x = x1 + (fx ? 0x0000 : 0x0007); 141 | y = y1 + (fy ? 0x0007 : 0x0000); 142 | } 143 | 144 | if (phase7_downto_3 == 0) { // if phase < 8 145 | result.is_vram_write = 0; 146 | result.u8_value = 0; 147 | result.is_blit_done = 0; 148 | result.u16_addr = ram_addr + phase; // RAM read 149 | } else { 150 | c = phase2_downto_0 == 0b000 ? sprite_rows[phase7_downto_3 - 1] : c; 151 | x = phase2_downto_0 == 0b000 ? (x1 + (fx ? 0x0000 : 0x0007)) : x; 152 | is_x_in_bounds = x(15, 8) == 0x00 ? 1 : 0; 153 | is_y_in_bounds = y(15, 8) == 0x00 ? 1 : 0; 154 | result.u16_addr = uint16_uint8_8(0, y(7, 0)); 155 | result.u16_addr = uint16_uint8_0(result.u16_addr, x(7, 0)); 156 | result.is_vram_write = is_x_in_bounds & is_y_in_bounds & (opaque | c(0)); 157 | result.u8_value = blending[color8 + (c(0) ? 0x10 : 0x00)]; 158 | y = phase2_downto_0 == 0b111 ? (fy ? (y - 1) : (y + 1)) : y; 159 | result.is_blit_done = phase == 0x047 ? 1 : 0; 160 | c >>= 1; 161 | x = (fx ? (x + 1) : (x - 1)); 162 | } 163 | 164 | return result; 165 | } 166 | 167 | device_out_result_t pixel_deo(uint4_t device_port, uint12_t phase, uint8_t previous_device_ram_read, uint8_t previous_ram_read) { 168 | static uint8_t x, y, ctrl, auto_advance, tmp8, tmp8b; 169 | static uint4_t phase4; 170 | static uint2_t color; 171 | static uint1_t ctrl_mode, flip_x, flip_y, layer, is_auto_x, is_auto_y, is_x_in_bounds, is_y_in_bounds; 172 | static device_out_result_t result = {0, 0, 0, 0, 0, 0, 0}; 173 | phase4 = phase(3, 0); 174 | 175 | if (phase4 == 0x0) { 176 | result.is_vram_write = 0; 177 | result.is_device_ram_write = 0; 178 | result.device_ram_address = 0x28; // x (hi) 179 | result.is_deo_done = 0; 180 | } 181 | else if (phase4 == 0x1) { 182 | result.device_ram_address = 0x29; // x (lo) 183 | } 184 | else if (phase4 == 0x2) { 185 | result.device_ram_address = 0x2A; // y (hi) 186 | x = (uint16_t)(previous_device_ram_read); 187 | x <<= 8; 188 | is_x_in_bounds = previous_device_ram_read == 0 ? 1 : 0; 189 | } 190 | else if (phase4 == 0x3) { 191 | result.device_ram_address = 0x2B; // y (lo) 192 | x |= (uint16_t)(previous_device_ram_read); 193 | } 194 | else if (phase4 == 0x4) { 195 | result.device_ram_address = 0x2E; // ctrl 196 | y = (uint16_t)(previous_device_ram_read); 197 | y <<= 8; 198 | is_y_in_bounds = previous_device_ram_read == 0 ? 1 : 0; 199 | } 200 | else if (phase4 == 0x5) { 201 | y |= (uint16_t)(previous_device_ram_read); 202 | result.device_ram_address = 0x26; // auto 203 | } 204 | else if (phase4 == 0x6) { 205 | ctrl = previous_device_ram_read; 206 | ctrl_mode = ctrl(7); 207 | layer = ctrl(6); 208 | flip_y = ctrl(5); 209 | flip_x = ctrl(4); 210 | color = ctrl(1, 0); 211 | // extra bits for fill mode 0b000FXYCC (F = Is Fill, X = Flip X, Y = Flip Y) 212 | tmp8 = uint8_uint2_0(0, color); 213 | tmp8 = uint8_uint1_2(tmp8, flip_y); 214 | tmp8 = uint8_uint1_3(tmp8, flip_x); 215 | tmp8 = uint8_uint1_4(tmp8, ctrl_mode); 216 | tmp8b = ~(ctrl_mode & ~is_x_in_bounds) ? x : 0xFF; 217 | is_x_in_bounds = ctrl_mode ? (flip_x | is_x_in_bounds) : is_x_in_bounds; 218 | is_y_in_bounds = ctrl_mode ? (flip_y | is_y_in_bounds) : is_y_in_bounds; 219 | result.u16_addr = uint16_uint8_0(0, x); 220 | result.u16_addr = uint16_uint8_8(result.u16_addr, y); 221 | result.vram_write_layer = layer; 222 | result.device_ram_address = 0; 223 | result.is_vram_write = is_x_in_bounds & is_y_in_bounds; 224 | result.is_deo_done = ctrl_mode; 225 | result.u8_value = tmp8; 226 | } 227 | else if (phase4 == 0x7) { 228 | auto_advance = previous_device_ram_read; 229 | is_auto_x = auto_advance(0); 230 | is_auto_y = auto_advance(1); 231 | result.is_vram_write = 0; 232 | result.u16_addr = 0; 233 | result.is_device_ram_write = is_auto_x | is_auto_y; 234 | is_x_in_bounds = is_auto_x & is_x_in_bounds & (x == 0xFF ? 1 : 0) ? 0 : is_x_in_bounds; 235 | is_y_in_bounds = is_auto_y & is_y_in_bounds & (y == 0xFF ? 1 : 0) ? 0 : is_y_in_bounds; 236 | result.u8_value = (is_auto_x ? ~is_x_in_bounds : ~is_y_in_bounds); 237 | result.device_ram_address = is_auto_x ? 0x28 : 0x2A; 238 | result.is_deo_done = ~(is_auto_x | is_auto_y); 239 | } 240 | else if (phase4 == 0x8) { 241 | result.is_device_ram_write = is_auto_x | is_auto_y; 242 | result.u8_value = is_auto_x ? (x + 1) : (y + 1); 243 | result.device_ram_address = is_auto_x ? 0x29 : 0x2B; 244 | result.is_deo_done = ~(is_auto_x | is_auto_y); 245 | } 246 | else if (phase4 == 0x9) { 247 | // auto y if we did auto x last cycle 248 | result.is_device_ram_write = is_auto_y & is_auto_x; 249 | result.device_ram_address = 0x2A; 250 | result.u8_value = ~is_y_in_bounds; // y (hi) 251 | result.is_deo_done = 0; 252 | } 253 | else if (phase4 == 0xA) { 254 | // auto y if we did auto x last cycle 255 | result.is_device_ram_write = is_auto_y & is_auto_x; 256 | result.device_ram_address = 0x2B; 257 | result.u8_value = y + 1; // y (lo) 258 | result.is_deo_done = 1; 259 | } 260 | 261 | return result; 262 | } 263 | 264 | device_out_result_t sprite_deo(uint4_t device_port, uint12_t phase, uint8_t previous_device_ram_read, uint8_t previous_ram_read) { 265 | static uint16_t x, y, ram_addr, ram_addr_incr, tmp16, tmp16b; 266 | static uint12_t tmp12; 267 | static uint8_t ctrl, auto_advance, x_sprite_incr, y_sprite_incr; 268 | static uint4_t color, auto_length, tmp4; 269 | static uint1_t ctrl_mode, flip_x, flip_y, layer, is_blit_done, is_last_blit; 270 | static device_out_result_t result = {0, 0, 0, 0, 0, 0, 0}; 271 | static screen_blit_result_t screen_blit_result; 272 | 273 | if (phase == 0x000) { 274 | is_blit_done = 0; 275 | result.is_vram_write = 0; 276 | result.is_device_ram_write = 0; 277 | result.device_ram_address = 0x28; // x (hi) 278 | result.is_deo_done = 0; 279 | } 280 | else if (phase == 0x001) { 281 | result.device_ram_address = 0x29; // x (lo) 282 | } 283 | else if (phase == 0x002) { 284 | x = (uint16_t)(previous_device_ram_read); 285 | x <<= 8; 286 | result.device_ram_address = 0x2A; // y (hi) 287 | } 288 | else if (phase == 0x003) { 289 | x |= (uint16_t)(previous_device_ram_read); 290 | result.device_ram_address = 0x2B; // y (lo) 291 | } 292 | else if (phase == 0x004) { 293 | y = (uint16_t)(previous_device_ram_read); 294 | y <<= 8; 295 | result.device_ram_address = 0x2F; // ctrl 296 | } 297 | else if (phase == 0x005) { 298 | y |= (uint16_t)(previous_device_ram_read); 299 | result.device_ram_address = 0x2C; // ram_addr (hi) 300 | } 301 | else if (phase == 0x006) { 302 | ctrl = previous_device_ram_read; 303 | ctrl_mode = ctrl(7); 304 | layer = ctrl(6); 305 | flip_y = ctrl(5); 306 | flip_x = ctrl(4); 307 | color = ctrl(3, 0); 308 | result.device_ram_address = 0x2D; // ram_addr (lo) 309 | } 310 | else if (phase == 0x007) { 311 | ram_addr = (uint16_t)(previous_device_ram_read); 312 | ram_addr <<= 8; 313 | result.device_ram_address = 0x26; // auto 314 | } 315 | else if (phase == 0x008) { 316 | ram_addr |= (uint16_t)(previous_device_ram_read); 317 | tmp12 = 0x009; 318 | tmp4 = 0; 319 | tmp16 = x; 320 | tmp16b = y; 321 | is_blit_done = 0; 322 | is_last_blit = 0; 323 | } 324 | else { 325 | auto_advance = phase == 0x009 ? previous_device_ram_read : auto_advance; 326 | auto_length = auto_advance(7, 4); // rML 327 | x_sprite_incr = uint4_uint1_3(0, auto_advance(0)); // rDX 328 | y_sprite_incr = uint4_uint1_3(0, auto_advance(1)); // rDY 329 | ram_addr_incr = (auto_advance(2) ? (ctrl_mode ? 0x0010 : 0x0008) : 0); 330 | if (is_blit_done) { 331 | if (tmp12 == phase) { 332 | tmp16 = flip_x ? (tmp16 - y_sprite_incr) : (tmp16 + y_sprite_incr); 333 | tmp16b = flip_y ? (tmp16b - x_sprite_incr) : (tmp16b + x_sprite_incr); 334 | x = (is_last_blit ? (flip_x ? (x - x_sprite_incr) : (x + x_sprite_incr)) : x); 335 | y = (is_last_blit ? (flip_y ? (y - y_sprite_incr) : (y + y_sprite_incr)) : y); 336 | result.is_vram_write = 0; 337 | result.u16_addr = 0; 338 | result.is_device_ram_write = 1; 339 | result.device_ram_address = 0x28; 340 | result.u8_value = x(15, 8); // x (hi) WRITE 341 | } 342 | else if (tmp12 == phase - 1) { 343 | result.is_device_ram_write = 1; 344 | result.device_ram_address = 0x29; 345 | result.u8_value = x(7, 0); // x (lo) WRITE 346 | } 347 | else if (tmp12 == phase - 2) { 348 | result.is_device_ram_write = 1; 349 | result.device_ram_address = 0x2A; 350 | result.u8_value = y(15, 8); // y (hi) WRITE 351 | } 352 | else if (tmp12 == phase - 3) { 353 | result.is_device_ram_write = 1; 354 | result.device_ram_address = 0x2B; 355 | result.u8_value = y(7, 0); // y (lo) WRITE 356 | } 357 | else if (tmp12 == phase - 4) { 358 | ram_addr += ram_addr_incr; 359 | result.is_device_ram_write = 1; 360 | result.device_ram_address = 0x2C; // ram_addr (hi) WRITE 361 | result.u8_value = ram_addr(15, 8); 362 | } 363 | else if (tmp12 == phase - 5) { 364 | result.is_device_ram_write = 1; 365 | result.device_ram_address = 0x2D; // ram_addr (lo) WRITE 366 | result.u8_value = ram_addr(7, 0); 367 | } 368 | else if (tmp12 == phase - 6) { 369 | tmp4 += 1; 370 | screen_blit_result.is_blit_done = 0; 371 | result.is_device_ram_write = 0; 372 | result.device_ram_address = 0x00; 373 | result.is_deo_done = is_last_blit; 374 | } 375 | } else { 376 | if (ctrl_mode) { 377 | screen_blit_result = screen_2bpp(phase - tmp12, tmp16, tmp16b, color, flip_x, flip_y, ram_addr, previous_ram_read); // 80 cycles 378 | } else { 379 | screen_blit_result = screen_1bpp(phase - tmp12, tmp16, tmp16b, color, flip_x, flip_y, ram_addr, previous_ram_read); // 72 cycles 380 | } 381 | 382 | result.device_ram_address = 0; 383 | result.is_device_ram_write = 0; 384 | result.is_vram_write = screen_blit_result.is_vram_write; 385 | result.u16_addr = screen_blit_result.u16_addr; 386 | result.vram_write_layer = layer; 387 | result.u8_value = screen_blit_result.u8_value; 388 | is_last_blit = auto_length == tmp4 ? 1 : 0; 389 | } 390 | 391 | tmp12 = is_blit_done ^ screen_blit_result.is_blit_done ? phase + 1 : tmp12; 392 | is_blit_done = screen_blit_result.is_blit_done; 393 | } 394 | 395 | return result; 396 | } 397 | 398 | device_out_result_t screen_deo(uint4_t device_port, uint12_t phase, uint8_t previous_device_ram_read, uint8_t previous_ram_read) { 399 | static device_out_result_t result = {0, 0, 0, 0, 0, 0, 0}; 400 | if (device_port == 0xE) { 401 | result = pixel_deo(device_port, phase, previous_device_ram_read, previous_ram_read); 402 | } else if (device_port == 0xF) { 403 | result = sprite_deo(device_port, phase, previous_device_ram_read, previous_ram_read); 404 | } else { 405 | result.is_vram_write = 0; 406 | result.is_device_ram_write = 0; 407 | result.is_deo_done = 1; 408 | } 409 | 410 | return result; 411 | } 412 | 413 | device_out_result_t emu_deo(uint4_t device_index, uint4_t device_port, uint12_t phase, uint8_t previous_device_ram_read, uint8_t previous_ram_read) { 414 | static device_out_result_t result = {0, 0, 0, 0, 0, 0, 0}; 415 | 416 | if (device_index == 0x2) { // SCREEN 417 | result = screen_deo(device_port, phase, previous_device_ram_read, previous_ram_read); 418 | } else { 419 | result.is_vram_write = 0; 420 | result.is_device_ram_write = 0; 421 | result.is_deo_done = 1; 422 | } 423 | 424 | return result; 425 | } 426 | 427 | device_out_result_t device_out(uint8_t device_address, uint8_t value, uint12_t phase, uint8_t previous_device_ram_read, uint8_t previous_ram_read) { 428 | static device_out_result_t result = {0, 0, 0, 0, 0, 0, 0}; 429 | static uint4_t device_index, device_port; 430 | static uint1_t deo_mask[16] = {0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1}; 431 | 432 | if (phase == 0x000) { 433 | result.is_vram_write = 0; 434 | result.is_device_ram_write = 1; 435 | result.device_ram_address = device_address; 436 | result.u8_value = value; 437 | device_index = device_address(7, 4); 438 | result.is_deo_done = deo_mask[device_index]; 439 | } 440 | else { 441 | device_port = (uint4_t)(device_address); 442 | result = emu_deo(device_index, device_port, phase - 1, previous_device_ram_read, previous_ram_read); 443 | } 444 | 445 | return result; 446 | } 447 | 448 | device_in_result_t generic_dei(uint8_t device_address, uint8_t phase, uint8_t previous_device_ram_read) { 449 | 450 | device_in_result_t result; 451 | result.device_ram_address = phase == 0 ? device_address : 0; 452 | result.dei_value = phase == 2 ? previous_device_ram_read : 0; 453 | result.is_dei_done = phase == 2 ? 1 : 0; 454 | 455 | return result; 456 | } 457 | 458 | device_in_result_t system_dei(uint8_t device_address, uint8_t phase, uint8_t stack_ptr0, uint8_t stack_ptr1, uint8_t previous_device_ram_read) { 459 | static device_in_result_t result = {0, 0, 0}; 460 | if (device_address == 0x04) { 461 | result.device_ram_address = 0; 462 | result.dei_value = stack_ptr0; 463 | result.is_dei_done = 1; 464 | } 465 | else if (device_address == 0x05) { 466 | result.device_ram_address = 0; 467 | result.dei_value = stack_ptr1; 468 | result.is_dei_done = 1; 469 | } 470 | else { 471 | result = generic_dei(device_address, phase, previous_device_ram_read); 472 | } 473 | 474 | return result; 475 | } 476 | 477 | device_in_result_t screen_dei(uint8_t device_address, uint8_t phase, uint8_t previous_device_ram_read) { 478 | static device_in_result_t result = {0, 0, 0}; 479 | static uint4_t device_port = 0; 480 | device_port = (uint4_t)device_address; 481 | if (device_port == 0x2) { // screen width (256, or 0x0100) (high byte) 482 | result.device_ram_address = 0; 483 | result.dei_value = 0x01; 484 | result.is_dei_done = 1; 485 | } 486 | else if (device_port == 0x3) { // screen width (256, or 0x0100) (low byte) 487 | result.device_ram_address = 0; 488 | result.dei_value = 0x00; 489 | result.is_dei_done = 1; 490 | } 491 | else if (device_port == 0x4) { // screen height (256, or 0x0100) (high byte) 492 | result.device_ram_address = 0; 493 | result.dei_value = 0x01; 494 | result.is_dei_done = 1; 495 | } 496 | else if (device_port == 0x5) { // screen height (256, or 0x0100) (low byte) 497 | result.device_ram_address = 0; 498 | result.dei_value = 0x00; 499 | result.is_dei_done = 1; 500 | } 501 | else { 502 | result = generic_dei(device_address, phase, previous_device_ram_read); 503 | } 504 | 505 | return result; 506 | } 507 | 508 | device_in_result_t controller_dei(uint8_t device_address, uint8_t phase, uint8_t controller0_buttons, uint8_t previous_device_ram_read) { 509 | static device_in_result_t result = {0, 0, 0}; 510 | static uint4_t device_port = 0; 511 | device_port = (uint4_t)device_address; 512 | 513 | if (device_port == 0x2) { // button RLDUTSBA (right, left, down, up, start, select, B, A) 514 | result.device_ram_address = 0; 515 | result.dei_value = controller0_buttons; 516 | result.is_dei_done = 1; 517 | } 518 | else { 519 | result = generic_dei(device_address, phase, previous_device_ram_read); 520 | } 521 | 522 | return result; 523 | } 524 | 525 | device_in_result_t datetime_dei(uint8_t device_address, uint8_t phase, uint32_t time, uint8_t previous_device_ram_read) { 526 | static device_in_result_t result = {0, 0, 0}; 527 | 528 | result.device_ram_address = 0; 529 | result.dei_value = 0; 530 | result.is_dei_done = 1; 531 | if (device_address == 0xC4) { // hour 532 | result.dei_value = time(23, 16); 533 | } 534 | else if (device_address == 0xC5) { // minute 535 | result.dei_value = time(15, 8); 536 | } 537 | else if (device_address == 0xC6) { // second 538 | result.dei_value = time(7, 0); 539 | } 540 | else if (device_address == 0xC7) { // day of week, beginning Sunday 541 | result.dei_value = time(31, 24); 542 | } 543 | 544 | return result; 545 | } 546 | 547 | device_in_result_t device_in(uint8_t device_address, uint8_t phase, uint8_t controller0_buttons, uint32_t time, uint8_t stack_ptr0, uint8_t stack_ptr1, uint8_t previous_device_ram_read) { 548 | static uint4_t device; 549 | static device_in_result_t result = {0, 0, 0}; 550 | 551 | device = device_address(7, 4); 552 | 553 | if (device == 0x0) { 554 | result = system_dei(device_address, phase, stack_ptr0, stack_ptr1, previous_device_ram_read); 555 | } 556 | else if (device == 0x2) { 557 | result = screen_dei(device_address, phase, previous_device_ram_read); 558 | } 559 | else if (device == 0x8) { 560 | result = controller_dei(device_address, phase, controller0_buttons, previous_device_ram_read); 561 | } 562 | else if (device == 0xC) { 563 | result = datetime_dei(device_address, phase, time, previous_device_ram_read); 564 | } 565 | else { 566 | result = generic_dei(device_address, phase, previous_device_ram_read); 567 | } 568 | 569 | return result; 570 | } -------------------------------------------------------------------------------- /uxn_ram_device.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | // 256 bytes Device RAM 5 | uint8_t device_ram_update(uint8_t device_address, uint8_t value, uint1_t write_enable) { 6 | static uint8_t device_ram[256]; 7 | static uint32_t rwaddr; 8 | static uint8_t wdata; 9 | rwaddr = (uint32_t)(device_address); 10 | wdata = value; 11 | 12 | uint8_t rdata = device_ram_RAM_SP_RF_1( 13 | rwaddr, // rw address 14 | wdata, // write value 15 | write_enable // write enable 16 | ); 17 | 18 | return rdata; 19 | } 20 | -------------------------------------------------------------------------------- /uxn_ram_main.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | // 64KB Main RAM 5 | uint8_t main_ram_update(uint16_t ram_address, uint8_t value, uint1_t write_enable) { 6 | static uint8_t main_ram[65536]; 7 | static uint32_t rwaddr; 8 | static uint8_t wdata; 9 | rwaddr = (uint32_t)(ram_address); 10 | wdata = value; 11 | 12 | uint8_t rdata = main_ram_RAM_SP_RF_1( 13 | rwaddr, // rw address 14 | wdata, // write value 15 | write_enable // write enable 16 | ); 17 | 18 | return rdata; 19 | } 20 | -------------------------------------------------------------------------------- /uxn_ram_screen.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | // 256 x 256 (double-buffering) 5 | #define SCREEN_RAM_SIZE 65536 * 2 6 | #define DRAW_QUEUE_SIZE 32768 7 | 8 | uint24_t draw_queue_update( 9 | uint15_t read_address, 10 | uint15_t write_address, 11 | uint24_t write_value, 12 | uint1_t write_enable 13 | ) { 14 | static uint24_t draw_queue_ram[DRAW_QUEUE_SIZE]; 15 | static uint32_t waddr = 0; 16 | static uint32_t wdata = 0; 17 | static uint32_t raddr = 0; 18 | raddr = (uint32_t)read_address; 19 | waddr = (uint32_t)write_address; 20 | wdata = write_value; 21 | 22 | uint24_t rdata = draw_queue_ram_RAM_DP_RF_1( 23 | raddr, // read address 24 | waddr, // write address 25 | wdata, // write value 26 | write_enable // write enable 27 | ); 28 | 29 | return rdata; 30 | } 31 | 32 | uint2_t bg_vram_update( 33 | uint17_t read_address, 34 | uint17_t write_address, 35 | uint2_t write_value, 36 | uint1_t write_enable 37 | ) { 38 | static uint2_t bg_vram[SCREEN_RAM_SIZE]; 39 | static uint32_t waddr = 0; 40 | static uint32_t wdata = 0; 41 | static uint32_t raddr = 0; 42 | raddr = (uint32_t)read_address; 43 | waddr = (uint32_t)write_address; 44 | wdata = (uint32_t)write_value; 45 | 46 | uint2_t rdata = bg_vram_RAM_DP_RF_1( 47 | raddr, // read address 48 | waddr, // write address 49 | wdata, // write value 50 | write_enable // write enable 51 | ); 52 | 53 | return rdata; 54 | } 55 | 56 | uint2_t fg_vram_update( 57 | uint17_t read_address, 58 | uint17_t write_address, 59 | uint2_t write_value, 60 | uint1_t write_enable 61 | ) { 62 | static uint2_t fg_vram[SCREEN_RAM_SIZE]; 63 | static uint32_t waddr = 0; 64 | static uint32_t wdata = 0; 65 | static uint32_t raddr = 0; 66 | raddr = (uint32_t)read_address; 67 | waddr = (uint32_t)write_address; 68 | wdata = (uint32_t)write_value; 69 | 70 | uint2_t rdata = fg_vram_RAM_DP_RF_1( 71 | raddr, // read address 72 | waddr, // write address 73 | wdata, // write value 74 | write_enable // write enable 75 | ); 76 | 77 | return rdata; 78 | } -------------------------------------------------------------------------------- /uxn_stack.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "uintN_t.h" // uintN_t types for any N 3 | 4 | // 512 bytes Stack RAM (256 for work stack, 256 for return stack) 5 | uint8_t stack_ram_update(uint9_t stack_address, uint8_t value, uint1_t write_enable) { 6 | static uint8_t stack_ram[512]; 7 | static uint32_t rwaddr; 8 | static uint8_t wdata; 9 | rwaddr = (uint32_t)(stack_address); 10 | wdata = value; 11 | 12 | uint8_t rdata = stack_ram_RAM_SP_RF_1( 13 | rwaddr, // rw address 14 | wdata, // write value 15 | write_enable // write enable 16 | ); 17 | 18 | return rdata; 19 | } 20 | --------------------------------------------------------------------------------