├── .gitignore ├── DisplayM0APP ├── .cproject ├── .project ├── .settings │ └── language.settings.xml ├── DisplayM0APP_Flash.ld └── src │ ├── cr_startup_lpc43xx-m0app.c │ ├── crp.c │ ├── display-m0app.c │ ├── icons.c │ ├── numfont20x24.c │ └── numfont32x24.c ├── FMReceiverMC ├── .cproject ├── .project ├── FMReceiver.ld ├── FMReceiver_Flash.ld ├── include │ ├── receiver.h │ └── vadc.h └── src │ ├── clkcfg.c │ ├── cr_start_m0.c │ ├── cr_start_m0.h │ ├── cr_startup_lpc43xx.c │ ├── crp.c │ ├── dsp.c │ ├── main.c │ └── ui.c ├── README.md └── doc └── LPC-Link2-FM.jpg /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | .DS_Store 3 | .dep 4 | .metadata 5 | Release 6 | Debug 7 | -------------------------------------------------------------------------------- /DisplayM0APP/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | DisplayM0APP 4 | 5 | 6 | CMSIS_DSPLIB_CM0 7 | CMSIS_LPC43xx_DriverLib-M0 8 | 9 | 10 | 11 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 12 | clean,full,incremental, 13 | 14 | 15 | 16 | 17 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 18 | full,incremental, 19 | 20 | 21 | 22 | 23 | 24 | org.eclipse.cdt.core.cnature 25 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 26 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 27 | 28 | 29 | -------------------------------------------------------------------------------- /DisplayM0APP/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /DisplayM0APP/DisplayM0APP_Flash.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Modified for placing code on flash. 3 | * GENERATED FILE - DO NOT EDIT 4 | * (c) Code Red Technologies Ltd, 2008-13 5 | * (c) NXP Semiconductors 2013-2016 6 | * Generated linker script file for LPC4370-M0 7 | * Created from generic_c.ld (LPCXpresso v7.4 (0 [Build 229] [2014-09-16] )) 8 | * By LPCXpresso v7.4.0 [Build 229] [2014-09-16] on Fri Jul 15 09:19:43 JST 2016 9 | */ 10 | 11 | GROUP( 12 | libcr_semihost.a 13 | libcr_c.a 14 | libcr_eabihelpers.a 15 | ) 16 | 17 | MEMORY 18 | { 19 | /* Define each memory region */ 20 | FlashB (rx) : ORIGIN = 0x140F0000, LENGTH = 0x10000 /* 64K bytes at tail of flash */ 21 | RAMLoc128B (rwx) : ORIGIN = 0x10010000, LENGTH = 0x10000 /* 64K bytes */ 22 | RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */ 23 | } 24 | /* Define a symbol for the top of each memory region */ 25 | __top_FlashB = 0x140F0000 + 0x10000; 26 | __top_RAMLoc128B = 0x10010000 + 0x10000; 27 | __top_RamLoc72 = 0x10080000 + 0x12000; 28 | 29 | ENTRY(ResetISR) 30 | 31 | SECTIONS 32 | { 33 | 34 | /* MAIN TEXT SECTION */ 35 | .text : ALIGN(4) 36 | { 37 | FILL(0xff) 38 | __vectors_start__ = ABSOLUTE(.) ; 39 | KEEP(*(.isr_vector)) 40 | 41 | /* Global Section Table */ 42 | . = ALIGN(4) ; 43 | __section_table_start = .; 44 | __data_section_table = .; 45 | LONG(LOADADDR(.data)); 46 | LONG( ADDR(.data)); 47 | LONG( SIZEOF(.data)); 48 | LONG(LOADADDR(.data_RAM2)); 49 | LONG( ADDR(.data_RAM2)); 50 | LONG( SIZEOF(.data_RAM2)); 51 | __data_section_table_end = .; 52 | __bss_section_table = .; 53 | LONG( ADDR(.bss)); 54 | LONG( SIZEOF(.bss)); 55 | LONG( ADDR(.bss_RAM2)); 56 | LONG( SIZEOF(.bss_RAM2)); 57 | __bss_section_table_end = .; 58 | __section_table_end = . ; 59 | /* End of Global Section Table */ 60 | 61 | *(.after_vectors*) 62 | 63 | } >FlashB 64 | 65 | .text : ALIGN(4) 66 | { 67 | *(.text*) 68 | *(.rodata .rodata.* .constdata .constdata.*) 69 | . = ALIGN(4); 70 | } >FlashB 71 | 72 | /* 73 | * for exception handling/unwind - some Newlib functions (in common 74 | * with C++ and STDC++) use this. 75 | */ 76 | .ARM.extab : ALIGN(4) 77 | { 78 | *(.ARM.extab* .gnu.linkonce.armextab.*) 79 | } > FlashB 80 | __exidx_start = .; 81 | 82 | .ARM.exidx : ALIGN(4) 83 | { 84 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 85 | } > FlashB 86 | __exidx_end = .; 87 | 88 | _etext = .; 89 | 90 | 91 | /* DATA section for RamLoc72 */ 92 | .data_RAM2 : ALIGN(4) 93 | { 94 | FILL(0xff) 95 | *(.ramfunc.$RAM2) 96 | *(.ramfunc.$RamLoc72) 97 | *(.data.$RAM2*) 98 | *(.data.$RamLoc72*) 99 | . = ALIGN(4) ; 100 | } > RamLoc72 AT>FlashB 101 | 102 | /* MAIN DATA SECTION */ 103 | 104 | 105 | .uninit_RESERVED : ALIGN(4) 106 | { 107 | KEEP(*(.bss.$RESERVED*)) 108 | . = ALIGN(4) ; 109 | _end_uninit_RESERVED = .; 110 | } > RAMLoc128B 111 | 112 | 113 | /* Main DATA section (RAMLoc128B) */ 114 | .data : ALIGN(4) 115 | { 116 | FILL(0xff) 117 | _data = . ; 118 | *(vtable) 119 | *(.ramfunc*) 120 | *(.data*) 121 | . = ALIGN(4) ; 122 | _edata = . ; 123 | } > RAMLoc128B AT>FlashB 124 | 125 | /* BSS section for RamLoc72 */ 126 | .bss_RAM2 : ALIGN(4) 127 | { 128 | *(.bss.$RAM2*) 129 | *(.bss.$RamLoc72*) 130 | . = ALIGN(4) ; 131 | } > RamLoc72 132 | 133 | /* MAIN BSS SECTION */ 134 | .bss : ALIGN(4) 135 | { 136 | _bss = .; 137 | *(.bss*) 138 | *(COMMON) 139 | . = ALIGN(4) ; 140 | _ebss = .; 141 | PROVIDE(end = .); 142 | } > RAMLoc128B 143 | 144 | /* NOINIT section for RamLoc72 */ 145 | .noinit_RAM2 (NOLOAD) : ALIGN(4) 146 | { 147 | *(.noinit.$RAM2*) 148 | *(.noinit.$RamLoc72*) 149 | . = ALIGN(4) ; 150 | } > RamLoc72 151 | 152 | /* DEFAULT NOINIT SECTION */ 153 | .noinit (NOLOAD): ALIGN(4) 154 | { 155 | _noinit = .; 156 | *(.noinit*) 157 | . = ALIGN(4) ; 158 | _end_noinit = .; 159 | } > RAMLoc128B 160 | 161 | PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); 162 | PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RAMLoc128B - 0); 163 | } 164 | -------------------------------------------------------------------------------- /DisplayM0APP/src/cr_startup_lpc43xx-m0app.c: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // LPC43xx (Cortex M0 APP) Startup code for use with LPCXpresso IDE 3 | // 4 | // Version : 140630 5 | //***************************************************************************** 6 | // 7 | // Copyright(C) NXP Semiconductors, 2013-2014 8 | // All rights reserved. 9 | // 10 | // Software that is described herein is for illustrative purposes only 11 | // which provides customers with programming information regarding the 12 | // LPC products. This software is supplied "AS IS" without any warranties of 13 | // any kind, and NXP Semiconductors and its licensor disclaim any and 14 | // all warranties, express or implied, including all implied warranties of 15 | // merchantability, fitness for a particular purpose and non-infringement of 16 | // intellectual property rights. NXP Semiconductors assumes no responsibility 17 | // or liability for the use of the software, conveys no license or rights under any 18 | // patent, copyright, mask work right, or any other intellectual property rights in 19 | // or to any products. NXP Semiconductors reserves the right to make changes 20 | // in the software without notification. NXP Semiconductors also makes no 21 | // representation or warranty that such application will be suitable for the 22 | // specified use without further testing or modification. 23 | // 24 | // Permission to use, copy, modify, and distribute this software and its 25 | // documentation is hereby granted, under NXP Semiconductors' and its 26 | // licensor's relevant copyrights in the software, without fee, provided that it 27 | // is used in conjunction with NXP Semiconductors microcontrollers. This 28 | // copyright, permission, and disclaimer notice must appear in all copies of 29 | // this code. 30 | //***************************************************************************** 31 | #if defined (__cplusplus) 32 | #ifdef __REDLIB__ 33 | #error Redlib does not support C++ 34 | #else 35 | //***************************************************************************** 36 | // 37 | // The entry point for the C++ library startup 38 | // 39 | //***************************************************************************** 40 | extern "C" { 41 | extern void __libc_init_array(void); 42 | } 43 | #endif 44 | #endif 45 | 46 | #define WEAK __attribute__ ((weak)) 47 | #define ALIAS(f) __attribute__ ((weak, alias (#f))) 48 | 49 | //***************************************************************************** 50 | #if defined (__cplusplus) 51 | extern "C" { 52 | #endif 53 | 54 | //***************************************************************************** 55 | #if defined (__USE_CMSIS) || defined (__USE_LPCOPEN) 56 | // Declaration of external SystemInit function 57 | extern void SystemInit(void); 58 | #endif 59 | //***************************************************************************** 60 | // 61 | // Forward declaration of the default handlers. These are aliased. 62 | // When the application defines a handler (with the same name), this will 63 | // automatically take precedence over these weak definitions 64 | // 65 | //***************************************************************************** 66 | void ResetISR(void); 67 | #if defined (__USE_LPCOPEN) 68 | WEAK void NMI_Handler(void); 69 | WEAK void HardFault_Handler(void); 70 | WEAK void SVC_Handler(void); 71 | WEAK void PendSV_Handler(void); 72 | // Note - Systick Peripheral not implemented on LPC43xx M0app cpu 73 | WEAK void IntDefaultHandler(void); 74 | #else 75 | WEAK void M0_NMI_Handler(void); 76 | WEAK void M0_HardFault_Handler (void); 77 | WEAK void M0_SVC_Handler(void); 78 | WEAK void M0_PendSV_Handler(void); 79 | // Note - Systick Peripheral not implemented on LPC43xx M0app cpu 80 | WEAK void M0_IntDefaultHandler(void); 81 | #endif 82 | 83 | //***************************************************************************** 84 | // 85 | // Forward declaration of the specific IRQ handlers. These are aliased 86 | // to the IntDefaultHandler, which is a 'forever' loop. When the application 87 | // defines a handler (with the same name), this will automatically take 88 | // precedence over these weak definitions 89 | // 90 | //***************************************************************************** 91 | #if defined (__USE_LPCOPEN) 92 | void RTC_IRQHandler(void) ALIAS(IntDefaultHandler); 93 | void MX_CORE_IRQHandler(void) ALIAS(IntDefaultHandler); 94 | void DMA_IRQHandler(void) ALIAS(IntDefaultHandler); 95 | void FLASHEEPROM_IRQHandler(void) ALIAS(IntDefaultHandler); 96 | void ETH_IRQHandler(void) ALIAS(IntDefaultHandler); 97 | void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler); 98 | void LCD_IRQHandler(void) ALIAS(IntDefaultHandler); 99 | void USB0_IRQHandler(void) ALIAS(IntDefaultHandler); 100 | void USB1_IRQHandler(void) ALIAS(IntDefaultHandler); 101 | void SCT_IRQHandler(void) ALIAS(IntDefaultHandler); 102 | void RIT_IRQHandler(void) ALIAS(IntDefaultHandler); 103 | void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler); 104 | void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler); 105 | void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler); 106 | void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler); 107 | void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler); 108 | void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler); 109 | void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler); 110 | void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler); 111 | void SPI_IRQHandler (void) ALIAS(IntDefaultHandler); 112 | void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler); 113 | void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler); 114 | void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler); 115 | void UART0_IRQHandler(void) ALIAS(IntDefaultHandler); 116 | void UART1_IRQHandler(void) ALIAS(IntDefaultHandler); 117 | void UART2_IRQHandler(void) ALIAS(IntDefaultHandler); 118 | void UART3_IRQHandler(void) ALIAS(IntDefaultHandler); 119 | void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler); 120 | void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler); 121 | void SPIFI_ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler); 122 | void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler); 123 | #else 124 | void M0_RTC_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 125 | void M0_M4CORE_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 126 | void M0_DMA_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 127 | void M0_ETH_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 128 | void M0_SDIO_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 129 | void M0_LCD_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 130 | void M0_USB0_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 131 | void M0_USB1_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 132 | void M0_SCT_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 133 | void M0_RIT_OR_WWDT_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 134 | void M0_TIMER0_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 135 | void M0_GINT1_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 136 | void M0_TIMER3_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 137 | void M0_MCPWM_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 138 | void M0_ADC0_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 139 | void M0_I2C0_OR_I2C1_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 140 | void M0_SGPIO_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 141 | void M0_SPI_OR_DAC_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 142 | void M0_ADC1_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 143 | void M0_SSP0_OR_SSP1_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 144 | void M0_EVENTROUTER_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 145 | void M0_USART0_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 146 | void M0_USART2_OR_C_CAN1_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 147 | void M0_USART3_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 148 | void M0_I2S0_OR_I2S1_OR_QEI_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 149 | void M0_C_CAN0_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 150 | void M0_SPIFI_OR_VADC_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 151 | void M0_M0SUB_IRQHandler(void) ALIAS(M0_IntDefaultHandler); 152 | #endif 153 | //***************************************************************************** 154 | // 155 | // The entry point for the application. 156 | // __main() is the entry point for Redlib based applications 157 | // main() is the entry point for Newlib based applications 158 | // 159 | //***************************************************************************** 160 | #if defined (__REDLIB__) 161 | extern void __main(void); 162 | #endif 163 | extern int main(void); 164 | //***************************************************************************** 165 | // 166 | // External declaration for the pointer to the stack top from the Linker Script 167 | // 168 | //***************************************************************************** 169 | extern void _vStackTop(void); 170 | 171 | //***************************************************************************** 172 | #if defined (__cplusplus) 173 | } // extern "C" 174 | #endif 175 | //***************************************************************************** 176 | // 177 | // The vector table. 178 | // This relies on the linker script to place at correct location in memory. 179 | // 180 | //***************************************************************************** 181 | extern void (* const g_pfnVectors[])(void); 182 | __attribute__ ((section(".isr_vector"))) 183 | void (* const g_pfnVectors[])(void) = { 184 | #if defined (__USE_LPCOPEN) 185 | // Core Level - CM0 186 | &_vStackTop, // The initial stack pointer 187 | ResetISR, // 1 The reset handler 188 | NMI_Handler, // The NMI handler 189 | HardFault_Handler, // The hard fault handler 190 | 0, // 4 Reserved 191 | 0, // 5 Reserved 192 | 0, // 6 Reserved 193 | 0, // 7 Reserved 194 | 0, // 8 Reserved 195 | 0, // 9 Reserved 196 | 0, // 10 Reserved 197 | SVC_Handler, // SVCall handler 198 | 0, // Reserved 199 | 0, // Reserved 200 | PendSV_Handler, // The PendSV handler 201 | 0, // Reserved - Systick not implemented... 202 | // .. on LPC43xx M0app cpu 203 | 204 | // Chip Level - 43xx M0 core 205 | RTC_IRQHandler, // 16 RTC 206 | MX_CORE_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY) 207 | DMA_IRQHandler, // 18 General Purpose DMA 208 | 0, // 19 Reserved 209 | FLASHEEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts 210 | ETH_IRQHandler, // 21 Ethernet 211 | SDIO_IRQHandler, // 22 SD/MMC 212 | LCD_IRQHandler, // 23 LCD 213 | USB0_IRQHandler, // 24 USB0 214 | USB1_IRQHandler, // 25 USB1 215 | SCT_IRQHandler, // 26 State Configurable Timer 216 | RIT_IRQHandler, // 27 ORed Repetitive Interrupt Timer, WWDT 217 | TIMER0_IRQHandler, // 28 Timer0 218 | GINT1_IRQHandler, // 29 GINT1 219 | GPIO4_IRQHandler, // 30 GPIO4 220 | TIMER3_IRQHandler, // 31 Timer 3 221 | MCPWM_IRQHandler, // 32 Motor Control PWM 222 | ADC0_IRQHandler, // 33 A/D Converter 0 223 | I2C0_IRQHandler, // 34 ORed I2C0, I2C1 224 | SGPIO_IRQHandler, // 35 SGPIO (LPC43XX ONLY) 225 | SPI_IRQHandler, // 36 ORed SPI, DAC (LPC43XX ONLY) 226 | ADC1_IRQHandler, // 37 A/D Converter 1 227 | SSP0_IRQHandler, // 38 ORed SSP0, SSP1 228 | EVRT_IRQHandler, // 39 Event Router 229 | UART0_IRQHandler, // 40 UART0 230 | UART1_IRQHandler, // 41 UART1 231 | UART2_IRQHandler, // 42 UART2 232 | UART3_IRQHandler, // 43 USRT3 233 | I2S0_IRQHandler, // 44 ORed I2S0, I2S1 234 | CAN0_IRQHandler, // 45 C_CAN0 235 | SPIFI_ADCHS_IRQHandler, // 46 SPIFI OR ADCHS interrupt 236 | M0SUB_IRQHandler, // 47 M0SUB core 237 | }; 238 | #else 239 | // Core Level - CM0 240 | &_vStackTop, // The initial stack pointer 241 | ResetISR, // 1 The reset handler 242 | M0_NMI_Handler, // 2 The NMI handler 243 | M0_HardFault_Handler, // 3 The hard fault handler 244 | 0, // 4 Reserved 245 | 0, // 5 Reserved 246 | 0, // 6 Reserved 247 | 0, // 7 Reserved 248 | 0, // 8 Reserved 249 | 0, // 9 Reserved 250 | 0, // 10 Reserved 251 | M0_SVC_Handler, // 11 SVCall handler 252 | 0, // 12 Reserved 253 | 0, // 13 Reserved 254 | M0_PendSV_Handler, // 14 The PendSV handler 255 | 0, // Reserved - Systick not implemented... 256 | // .. on LPC43xx M0app cpu 257 | // Chip Level - LPC43 (CM0 APP) 258 | M0_RTC_IRQHandler, // 16 RTC 259 | M0_M4CORE_IRQHandler, // 17 Interrupt from M4 Core 260 | M0_DMA_IRQHandler, // 18 General Purpose DMA 261 | 0, // 19 Reserved 262 | 0, // 20 Reserved 263 | M0_ETH_IRQHandler, // 21 Ethernet 264 | M0_SDIO_IRQHandler, // 22 SD/MMC 265 | M0_LCD_IRQHandler, // 23 LCD 266 | M0_USB0_IRQHandler, // 24 USB0 267 | M0_USB1_IRQHandler, // 25 USB1 268 | M0_SCT_IRQHandler , // 26 State Configurable Timer 269 | M0_RIT_OR_WWDT_IRQHandler, // 27 Repetitive Interrupt Timer 270 | M0_TIMER0_IRQHandler, // 28 Timer0 271 | M0_GINT1_IRQHandler, // 29 GINT1 272 | M0_TIMER3_IRQHandler, // 30 Timer3 273 | 0, // 31 Reserved 274 | 0 , // 32 Reserved 275 | M0_MCPWM_IRQHandler, // 33 Motor Control PWM 276 | M0_ADC0_IRQHandler, // 34 ADC0 277 | M0_I2C0_OR_I2C1_IRQHandler, // 35 I2C0 or I2C1 278 | M0_SGPIO_IRQHandler, // 36 Serial GPIO 279 | M0_SPI_OR_DAC_IRQHandler, // 37 SPI or DAC 280 | M0_ADC1_IRQHandler, // 38 ADC1 281 | M0_SSP0_OR_SSP1_IRQHandler, // 39 SSP0 or SSP1 282 | M0_EVENTROUTER_IRQHandler, // 40 Event Router 283 | M0_USART0_IRQHandler, // 41 USART0 284 | M0_USART2_OR_C_CAN1_IRQHandler, // 42 USART2 or C CAN1 285 | M0_USART3_IRQHandler, // 43 USART3 286 | M0_I2S0_OR_I2S1_OR_QEI_IRQHandler, // 44 I2S0 or I2S1 or QEI 287 | M0_C_CAN0_IRQHandler, // 45 C CAN0 288 | M0_SPIFI_OR_VADC_IRQHandler, // 46 289 | M0_M0SUB_IRQHandler, // 47 Interrupt from M0SUB 290 | }; 291 | #endif 292 | //***************************************************************************** 293 | // Functions to carry out the initialization of RW and BSS data sections. These 294 | // are written as separate functions rather than being inlined within the 295 | // ResetISR() function in order to cope with MCUs with multiple banks of 296 | // memory. 297 | //***************************************************************************** 298 | __attribute__ ((section(".after_vectors"))) 299 | void data_init(unsigned int romstart, unsigned int start, unsigned int len) { 300 | unsigned int *pulDest = (unsigned int*) start; 301 | unsigned int *pulSrc = (unsigned int*) romstart; 302 | unsigned int loop; 303 | for (loop = 0; loop < len; loop = loop + 4) 304 | *pulDest++ = *pulSrc++; 305 | } 306 | 307 | __attribute__ ((section(".after_vectors"))) 308 | void bss_init(unsigned int start, unsigned int len) { 309 | unsigned int *pulDest = (unsigned int*) start; 310 | unsigned int loop; 311 | for (loop = 0; loop < len; loop = loop + 4) 312 | *pulDest++ = 0; 313 | } 314 | 315 | //***************************************************************************** 316 | // The following symbols are constructs generated by the linker, indicating 317 | // the location of various points in the "Global Section Table". This table is 318 | // created by the linker via the Code Red managed linker script mechanism. It 319 | // contains the load address, execution address and length of each RW data 320 | // section and the execution and length of each BSS (zero initialized) section. 321 | //***************************************************************************** 322 | extern unsigned int __data_section_table; 323 | extern unsigned int __data_section_table_end; 324 | extern unsigned int __bss_section_table; 325 | extern unsigned int __bss_section_table_end; 326 | 327 | //***************************************************************************** 328 | // Reset entry point for your code. 329 | // Sets up a simple runtime environment and initializes the C/C++ 330 | // library. 331 | // 332 | //***************************************************************************** 333 | void 334 | ResetISR(void) { 335 | 336 | // ****************************** 337 | // Modify CREG->M0APPMAP so that M0 looks in correct place 338 | // for its vector table when an exception is triggered. 339 | // Note that we do not use the CMSIS register access mechanism, 340 | // as there is no guarantee that the project has been configured 341 | // to use CMSIS. 342 | unsigned int *pCREG_M0APPMAP = (unsigned int *) 0x40043404; 343 | // CMSIS : CREG->M0APPMAP =

344 | *pCREG_M0APPMAP = (unsigned int)g_pfnVectors; 345 | 346 | // 347 | // Copy the data sections from flash to SRAM. 348 | // 349 | unsigned int LoadAddr, ExeAddr, SectionLen; 350 | unsigned int *SectionTableAddr; 351 | 352 | // Load base address of Global Section Table 353 | SectionTableAddr = &__data_section_table; 354 | 355 | // Copy the data sections from flash to SRAM. 356 | while (SectionTableAddr < &__data_section_table_end) { 357 | LoadAddr = *SectionTableAddr++; 358 | ExeAddr = *SectionTableAddr++; 359 | SectionLen = *SectionTableAddr++; 360 | data_init(LoadAddr, ExeAddr, SectionLen); 361 | } 362 | // At this point, SectionTableAddr = &__bss_section_table; 363 | // Zero fill the bss segment 364 | while (SectionTableAddr < &__bss_section_table_end) { 365 | ExeAddr = *SectionTableAddr++; 366 | SectionLen = *SectionTableAddr++; 367 | bss_init(ExeAddr, SectionLen); 368 | } 369 | 370 | // ********************************************************** 371 | // No need to call SystemInit() here, as master CM4 cpu will 372 | // have done the main system set up before enabling CM0. 373 | // ********************************************************** 374 | 375 | #if defined (__cplusplus) 376 | // 377 | // Call C++ library initialisation 378 | // 379 | __libc_init_array(); 380 | #endif 381 | 382 | #if defined (__REDLIB__) 383 | // Call the Redlib library, which in turn calls main() 384 | __main() ; 385 | #else 386 | main(); 387 | #endif 388 | 389 | // 390 | // main() shouldn't return, but if it does, we'll just enter an infinite loop 391 | // 392 | while (1) { 393 | ; 394 | } 395 | } 396 | 397 | //***************************************************************************** 398 | // Default exception handlers. Override the ones here by defining your own 399 | // handler routines in your application code. 400 | //***************************************************************************** 401 | __attribute__ ((section(".after_vectors"))) 402 | #if defined (__USE_LPCOPEN) 403 | void NMI_Handler(void) 404 | #else 405 | void M0_NMI_Handler(void) 406 | #endif 407 | { while(1) { } 408 | } 409 | 410 | __attribute__ ((section(".after_vectors"))) 411 | #if defined (__USE_LPCOPEN) 412 | void HardFault_Handler(void) 413 | #else 414 | void M0_HardFault_Handler(void) 415 | #endif 416 | { while(1) { } 417 | } 418 | 419 | __attribute__ ((section(".after_vectors"))) 420 | #if defined (__USE_LPCOPEN) 421 | void SVC_Handler(void) 422 | #else 423 | void M0_SVC_Handler(void) 424 | #endif 425 | { while(1) { } 426 | } 427 | 428 | __attribute__ ((section(".after_vectors"))) 429 | #if defined (__USE_LPCOPEN) 430 | void PendSV_Handler(void) 431 | #else 432 | void M0_PendSV_Handler(void) 433 | #endif 434 | { while(1) { } 435 | } 436 | 437 | //***************************************************************************** 438 | // 439 | // Processor ends up here if an unexpected interrupt occurs or a specific 440 | // handler is not present in the application code. 441 | // 442 | //***************************************************************************** 443 | __attribute__ ((section(".after_vectors"))) 444 | #if defined (__USE_LPCOPEN) 445 | void IntDefaultHandler(void) 446 | #else 447 | void M0_IntDefaultHandler(void) 448 | #endif 449 | { while(1) { } 450 | } 451 | 452 | -------------------------------------------------------------------------------- /DisplayM0APP/src/crp.c: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // crp.c 3 | // 4 | // Source file to create CRP word expected by LPCXpresso IDE linker 5 | //***************************************************************************** 6 | // 7 | // Copyright(C) NXP Semiconductors, 2013 8 | // All rights reserved. 9 | // 10 | // Software that is described herein is for illustrative purposes only 11 | // which provides customers with programming information regarding the 12 | // LPC products. This software is supplied "AS IS" without any warranties of 13 | // any kind, and NXP Semiconductors and its licensor disclaim any and 14 | // all warranties, express or implied, including all implied warranties of 15 | // merchantability, fitness for a particular purpose and non-infringement of 16 | // intellectual property rights. NXP Semiconductors assumes no responsibility 17 | // or liability for the use of the software, conveys no license or rights under any 18 | // patent, copyright, mask work right, or any other intellectual property rights in 19 | // or to any products. NXP Semiconductors reserves the right to make changes 20 | // in the software without notification. NXP Semiconductors also makes no 21 | // representation or warranty that such application will be suitable for the 22 | // specified use without further testing or modification. 23 | // 24 | // Permission to use, copy, modify, and distribute this software and its 25 | // documentation is hereby granted, under NXP Semiconductors' and its 26 | // licensor's relevant copyrights in the software, without fee, provided that it 27 | // is used in conjunction with NXP Semiconductors microcontrollers. This 28 | // copyright, permission, and disclaimer notice must appear in all copies of 29 | // this code. 30 | //***************************************************************************** 31 | 32 | #if defined (__CODE_RED) 33 | #include 34 | // Variable to store CRP value in. Will be placed automatically 35 | // by the linker when "Enable Code Read Protect" selected. 36 | // See crp.h header for more information 37 | __CRP const unsigned int CRP_WORD = CRP_NO_CRP ; 38 | #endif 39 | -------------------------------------------------------------------------------- /DisplayM0APP/src/display-m0app.c: -------------------------------------------------------------------------------- 1 | /* 2 | =============================================================================== 3 | Name : main.c 4 | Author : $(author) 5 | Version : 6 | Copyright : $(copyright) 7 | Description : main definition 8 | =============================================================================== 9 | */ 10 | 11 | #ifdef __USE_CMSIS 12 | #include "LPC43xx.h" 13 | #endif 14 | 15 | #include 16 | 17 | #include 18 | 19 | #include "lpc43xx_gpio.h" 20 | 21 | #include "lpc43xx_cgu.h" 22 | 23 | #include "lpc43xx_i2c.h" 24 | #include "lpc43xx_rgu.h" 25 | #include "lpc43xx_scu.h" 26 | #include "lpc43xx_ssp.h" 27 | #include 28 | 29 | #include "receiver.h" 30 | 31 | extern uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM]; 32 | 33 | #define BG_ACTIVE 0x8208 34 | #define BG_NORMAL 0x0000 35 | 36 | 37 | 38 | volatile uint32_t msTicks; // counter for 1ms SysTicks 39 | 40 | #if 0 41 | // **************** 42 | // SysTick_Handler - just increment SysTick counter 43 | void SysTick_Handler(void) { 44 | msTicks++; 45 | } 46 | #else 47 | void M0_RIT_OR_WWDT_IRQHandler(void) { 48 | msTicks++; 49 | LPC_RITIMER->CTRL = 50 | (1 << 0) /* RITINT */ 51 | | (1 << 1) /* RITENCLR */ 52 | | (1 << 2) /* RITENBR */ 53 | | (1 << 3) /* RITEN */ 54 | ; 55 | } 56 | 57 | void RITConfig() { 58 | LPC_RITIMER->COMPVAL = 204000*2; // 1000Hz @ 204MHz 59 | LPC_RITIMER->COUNTER = 0; 60 | LPC_RITIMER->CTRL = 61 | (0 << 0) /* RITINT */ 62 | | (1 << 1) /* RITENCLR */ 63 | | (1 << 2) /* RITENBR */ 64 | | (1 << 3) /* RITEN */ 65 | ; 66 | NVIC_SetPriority(RITIMER_IRQn, 0); 67 | NVIC_EnableIRQ(RITIMER_IRQn); 68 | } 69 | #endif 70 | 71 | // **************** 72 | // systick_delay - creates a delay of the appropriate number of Systicks (happens every 1 ms) 73 | void systick_delay(uint32_t delayTicks) { 74 | uint32_t currentTicks; 75 | 76 | currentTicks = msTicks; // read current tick counter 77 | // Now loop until required number of ticks passes. 78 | while ((msTicks - currentTicks) < delayTicks); 79 | } 80 | 81 | 82 | #define RESET_ASSERT GPIO_ClearValue(0, 1<<14) 83 | #define RESET_NEGATE GPIO_SetValue(0, 1<<14) 84 | #define CS_LOW //GPIO_ClearValue(0, 1<<15) 85 | #define CS_HIGH //GPIO_SetValue(0, 1<<15) 86 | #define DC_CMD GPIO_ClearValue(1, 1<<11) 87 | #define DC_DATA GPIO_SetValue(1, 1<<11) 88 | #define BACKLIGHT_ON GPIO_SetValue(3, 1<<5) 89 | #define BACKLIGHT_OFF GPIO_ClearValue(3, 1<<5) 90 | 91 | void 92 | ssp_senddata(int x) 93 | { 94 | SSP_SendData(LPC_SSP1, x); 95 | while (LPC_SSP1->SR & SSP_SR_BSY) 96 | ; 97 | } 98 | 99 | void 100 | ssp_senddata16(int x) 101 | { 102 | uint32_t CR0 = LPC_SSP1->CR0; 103 | LPC_SSP1->CR0 = (CR0 & 0xfff0) | SSP_DATABIT_16; 104 | SSP_SendData(LPC_SSP1, x); 105 | while (LPC_SSP1->SR & SSP_SR_BSY) 106 | ; 107 | LPC_SSP1->CR0 = CR0; 108 | } 109 | 110 | void 111 | ssp_databit8(void) 112 | { 113 | LPC_SSP1->CR0 = (LPC_SSP1->CR0 & 0xfff0) | SSP_DATABIT_8; 114 | } 115 | 116 | void 117 | ssp_databit16(void) 118 | { 119 | LPC_SSP1->CR0 = (LPC_SSP1->CR0 & 0xfff0) | SSP_DATABIT_16; 120 | } 121 | 122 | void 123 | spi_init() 124 | { 125 | SSP_CFG_Type ssp_config; 126 | 127 | scu_pinmux(1, 3, SSP_IO, FUNC5); // SSP1_MISO 128 | scu_pinmux(1, 4, SSP_IO, FUNC5); // SSP1_MOSI 129 | scu_pinmux(1, 20, SSP_IO, FUNC1); // SSP1_SSEL 130 | //scu_pinmux(1, 20, SSP_IO, FUNC0); // CS <- G0_15 131 | scu_pinmux(15, 4, CLK_OUT, FUNC0); // SSP1_SCK 132 | GPIO_SetDir(3, 1<<5, 1); // LED 133 | GPIO_SetDir(1, 1<<11, 1); // D/C 134 | GPIO_SetDir(0, 1<<14, 1); // RESET 135 | //GPIO_SetDir(0, 1<<15, 1); // CS 136 | 137 | SSP_ConfigStructInit(&ssp_config); 138 | ssp_config.ClockRate = 30000000; // 30MHz 139 | SSP_Init(LPC_SSP1, &ssp_config); 140 | 141 | SSP_Cmd(LPC_SSP1, ENABLE); 142 | } 143 | 144 | void 145 | spi_test() 146 | { 147 | while (1) { 148 | ssp_senddata(0xf0); 149 | ssp_senddata(0x55); 150 | CS_LOW; 151 | GPIO_SetValue(3, 1<<5); 152 | GPIO_SetValue(1, 1<<11); 153 | GPIO_SetValue(0, 1<<14); 154 | systick_delay(10); 155 | ssp_senddata(0xaa); 156 | ssp_senddata(0x0f); 157 | CS_HIGH; 158 | GPIO_ClearValue(3, 1<<5); 159 | GPIO_ClearValue(1, 1<<11); 160 | GPIO_ClearValue(0, 1<<14); 161 | systick_delay(20); 162 | } 163 | } 164 | 165 | void 166 | send_command(uint8_t cmd, int len, const uint8_t *data) 167 | { 168 | CS_LOW; 169 | DC_CMD; 170 | ssp_senddata(cmd); 171 | DC_DATA; 172 | while (len-- > 0) { 173 | ssp_senddata(*data++); 174 | } 175 | //CS_HIGH; 176 | } 177 | 178 | void 179 | send_command16(uint8_t cmd, int data) 180 | { 181 | CS_LOW; 182 | DC_CMD; 183 | ssp_senddata(cmd); 184 | DC_DATA; 185 | ssp_senddata16(data); 186 | CS_HIGH; 187 | } 188 | 189 | const uint8_t ili9341_init_seq[] = { 190 | // cmd, len, data..., 191 | // Power control B 192 | 0xCF, 3, 0x00, 0x83, 0x30, 193 | // Power on sequence control 194 | 0xED, 4, 0x64, 0x03, 0x12, 0x81, 195 | //0xED, 4, 0x55, 0x01, 0x23, 0x01, 196 | // Driver timing control A 197 | 0xE8, 3, 0x85, 0x01, 0x79, 198 | //0xE8, 3, 0x84, 0x11, 0x7a, 199 | // Power control A 200 | 0xCB, 5, 0x39, 0x2C, 0x00, 0x34, 0x02, 201 | // Pump ratio control 202 | 0xF7, 1, 0x20, 203 | // Driver timing control B 204 | 0xEA, 2, 0x00, 0x00, 205 | // POWER_CONTROL_1 206 | 0xC0, 1, 0x26, 207 | // POWER_CONTROL_2 208 | 0xC1, 1, 0x11, 209 | // VCOM_CONTROL_1 210 | 0xC5, 2, 0x35, 0x3E, 211 | // VCOM_CONTROL_2 212 | 0xC7, 1, 0xBE, 213 | // MEMORY_ACCESS_CONTROL 214 | //0x36, 1, 0x48 + 0x20, 215 | 0x36, 1, 0x28, 216 | // COLMOD_PIXEL_FORMAT_SET : 16 bit pixel 217 | 0x3A, 1, 0x55, 218 | // Frame Rate 219 | 0xB1, 2, 0x00, 0x1B, 220 | // Gamma Function Disable 221 | 0xF2, 1, 0x08, 222 | // gamma set for curve 01/2/04/08 223 | 0x26, 1, 0x01, 224 | // positive gamma correction 225 | 0xE0, 15, 0x1F, 0x1A, 0x18, 0x0A, 0x0F, 0x06, 0x45, 0x87, 0x32, 0x0A, 0x07, 0x02, 0x07, 0x05, 0x00, 226 | // negativ gamma correction 227 | 0xE1, 15, 0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3A, 0x78, 0x4D, 0x05, 0x18, 0x0D, 0x38, 0x3A, 0x1F, 228 | 229 | // Column Address Set 230 | 0x2A, 4, 0x00, 0x00, 0x01, 0x3f, // width 320 231 | // Page Address Set 232 | 0x2B, 4, 0x00, 0x00, 0x00, 0xef, // height 240 233 | 234 | // entry mode 235 | 0xB7, 1, 0x06, 236 | // display function control 237 | 0xB6, 4, 0x0A, 0x82, 0x27, 0x00, 238 | // sleep out 239 | 0x11, 0, 240 | 0 // sentinel 241 | }; 242 | 243 | void 244 | ili9341_init() 245 | { 246 | DC_DATA; 247 | RESET_ASSERT; 248 | systick_delay(1); 249 | RESET_NEGATE; 250 | 251 | send_command(0x01, 0, NULL); // SW reset 252 | systick_delay(5); 253 | send_command(0x28, 0, NULL); // display off 254 | 255 | const uint8_t *p; 256 | for (p = ili9341_init_seq; *p; ) { 257 | send_command(p[0], p[1], &p[2]); 258 | p += 2 + p[1]; 259 | } 260 | 261 | systick_delay(100); 262 | send_command(0x29, 0, NULL); // display on 263 | BACKLIGHT_ON; 264 | } 265 | 266 | void ili9341_pixel(int x, int y, int color) 267 | { 268 | uint8_t xx[4] = { x >> 8, x, (x+1) >> 8, (x+1) }; 269 | uint8_t yy[4] = { y >> 8, y, (y+1) >> 8, (y+1) }; 270 | uint8_t cc[2] = { color >> 8, color }; 271 | send_command(0x2A, 4, xx); 272 | send_command(0x2B, 4, yy); 273 | send_command(0x2C, 2, cc); 274 | //send_command16(0x2C, color); 275 | } 276 | 277 | 278 | void 279 | ili9341_test() 280 | { 281 | //while (1) { 282 | int x, y; 283 | for (y = 0; y < 320; y++) { 284 | for (x = 0; x < 240; x++) { 285 | ili9341_pixel(x, y, (y<<8)|x); 286 | } 287 | } 288 | 289 | // systick_delay(100); 290 | //} 291 | } 292 | 293 | uint16_t spi_buffer[2048]; 294 | 295 | void 296 | spi_dma_setup() 297 | { 298 | NVIC_DisableIRQ(DMA_IRQn); 299 | GPDMA_Init(); 300 | LPC_GPDMA->CONFIG |= 0x01 << 1; /* Enable DMA channels, little endian */ 301 | while ( !(LPC_GPDMA->CONFIG & (0x01 << 1)) ); 302 | NVIC_SetPriority(DMA_IRQn, 1); 303 | NVIC_EnableIRQ(DMA_IRQn); 304 | } 305 | 306 | void 307 | spi_dma_transfer(void *data, int length, int noincrement) 308 | { 309 | #if 0 310 | GPDMA_Channel_CFG_Type ssp_dma_cfg; 311 | ssp_dma_cfg.ChannelNum = 0; 312 | ssp_dma_cfg.SrcMemAddr = data; 313 | ssp_dma_cfg.DstConn = GPDMA_CONN_SSP1_Tx; 314 | ssp_dma_cfg.DstMemAddr = &LPC_SSP1->DR; 315 | ssp_dma_cfg.TransferSize = length; 316 | ssp_dma_cfg.TransferWidth = GPDMA_WIDTH_HALFWORD; 317 | //ssp_dma_cfg.TransferWidth = GPDMA_WIDTH_WORD; 318 | //ssp_dma_cfg.TransferType = GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL; 319 | ssp_dma_cfg.TransferType = GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA; 320 | ssp_dma_cfg.DMALLI = 0; 321 | GPDMA_Setup(&ssp_dma_cfg); 322 | GPDMA_ChannelCmd(0, ENABLE); 323 | #endif 324 | 325 | #define GPDMA_SSP1_TX_CHANNEL 12 326 | //LPC_CREG->DMAMUX &= ~3<<(GPDMA_SSP1_TX_CHANNEL*2); 327 | //LPC_CREG->DMAMUX |= 0<<(GPDMA_SSP1_TX_CHANNEL*2); 328 | LPC_GPDMA->C1SRCADDR = (uint32_t)data; 329 | LPC_GPDMA->C1DESTADDR = (uint32_t)&LPC_SSP1->DR; // write into SSP1 330 | LPC_GPDMA->C1LLI = 0; 331 | LPC_GPDMA->C1CONTROL = (length >> 1) | // Transfersize (does not matter when flow control is handled by peripheral) 332 | (0x2 << 12) | // Source Burst Size 333 | (0x0 << 15) | // Destination Burst Size 334 | (0x2 << 18) | // Source width // 32 bit width 335 | (0x1 << 21) | // Destination width // 16 bits 336 | (0x0 << 24) | // Source AHB master 0 / 1 337 | (0x1 << 25) | // Dest AHB master 0 / 1 338 | (noincrement?0:(0x1 << 26)) | // Source increment(LAST Sample) 339 | (0x0 << 27) | // Destination increment 340 | (0x1UL << 31); // Terminal count interrupt enabled 341 | LPC_GPDMA->C1CONFIG = (0x1) | // Enable bit 342 | (0x0 << 1) | // SRCPERIPHERAL - memory 343 | (GPDMA_SSP1_TX_CHANNEL << 6) | // Destination peripheral - memory - no setting 344 | (0x1 << 11) | // Flow control - peripheral to memory - DMA control 345 | // (0x5 << 11) | // Flow control - peripheral to memory - peripheral control 346 | (0x0 << 14) | // Int error mask 347 | (0x1 << 15); // ITC - term count error mask 348 | SSP_DMACmd(LPC_SSP1, SSP_DMA_TX, ENABLE); 349 | 350 | // software trigger 351 | LPC_GPDMA->SOFTBREQ = 1<INTTCSTAT & GPDMA_DMACIntTCStat_Ch(1)) 357 | // LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(1); 358 | } 359 | 360 | void 361 | spi_dma_sync() 362 | { 363 | while (!(LPC_GPDMA->INTTCSTAT & GPDMA_DMACIntTCStat_Ch(1))) 364 | ; //__WFI(); 365 | LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(1); 366 | //while (LPC_SSP1->SR & SSP_SR_BSY) 367 | // ; 368 | } 369 | 370 | void 371 | spi_dma_stop() 372 | { 373 | SSP_DMACmd(LPC_SSP1, SSP_DMA_TX, DISABLE); 374 | } 375 | 376 | #if 0 377 | void DMA_IRQHandler (void) 378 | { 379 | if (LPC_GPDMA->INTERRSTAT & GPDMA_DMACIntErrStat_Ch(1)) 380 | { 381 | LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(1); 382 | } 383 | 384 | if (LPC_GPDMA->INTTCSTAT & GPDMA_DMACIntTCStat_Ch(1)) 385 | { 386 | LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(1); 387 | } 388 | } 389 | #endif 390 | 391 | void 392 | ili9341_dma_test() 393 | { 394 | int sx = 40, ex = 200; 395 | uint8_t xx[4] = { sx >> 8, sx, ex >> 8, ex }; 396 | int x; 397 | int y = 0; 398 | spi_dma_setup(); 399 | 400 | //while (1) { 401 | for (y = 0; y < 320; y++) { 402 | int sy = y, ey = sy + 1; 403 | uint8_t yy[4] = { sy >> 8, sy, ey >> 8, ey }; 404 | for (x = 0; x < 160; x++) { 405 | //int c = ((~x & 0x7) ? 0x7 : 0x0) | (~x & ~0x7); 406 | //spi_buffer[x] = (y<<8)|(c&0xff); 407 | spi_buffer[x] = (x<<8)|y; 408 | } 409 | 410 | ssp_databit8(); 411 | send_command(0x2A, 4, xx); 412 | send_command(0x2B, 4, yy); 413 | send_command(0x2C, 3, xx); 414 | ssp_databit16(); 415 | spi_dma_transfer(spi_buffer, 160, 0); 416 | spi_dma_sync(); 417 | } 418 | //systick_delay(10); 419 | //} 420 | //spi_dma_stop(); 421 | } 422 | 423 | void 424 | ili9341_draw_bitmap(int x, int y, int w, int h, uint16_t *buf) 425 | { 426 | int ex = x + w-1; 427 | int ey = y + h-1; 428 | uint8_t xx[4] = { x >> 8, x, ex >> 8, ex }; 429 | uint8_t yy[4] = { y >> 8, y, ey >> 8, ey }; 430 | ssp_databit8(); 431 | send_command(0x2A, 4, xx); 432 | send_command(0x2B, 4, yy); 433 | send_command(0x2C, 0, NULL); 434 | ssp_databit16(); 435 | spi_dma_transfer(buf, w*h, 0); 436 | spi_dma_sync(); 437 | } 438 | 439 | void 440 | ili9341_fill(int x, int y, int w, int h, uint16_t color) 441 | { 442 | uint16_t buf[2] = { color, color }; //32bit buffer 443 | int ex = x + w-1; 444 | int ey = y + h-1; 445 | uint8_t xx[4] = { x >> 8, x, ex >> 8, ex }; 446 | uint8_t yy[4] = { y >> 8, y, ey >> 8, ey }; 447 | ssp_databit8(); 448 | send_command(0x2A, 4, xx); 449 | send_command(0x2B, 4, yy); 450 | send_command(0x2C, 0, NULL); 451 | ssp_databit16(); 452 | spi_dma_transfer(buf, w*h, 1); 453 | spi_dma_sync(); 454 | } 455 | 456 | extern const UNS_16 x5x7_bits []; 457 | extern const uint32_t numfont20x24[][24]; 458 | extern const uint32_t numfont32x24[][24]; 459 | extern const uint32_t icons48x20[][20*2]; 460 | 461 | typedef struct { 462 | uint16_t width; 463 | uint16_t height; 464 | uint16_t scaley; 465 | uint16_t slide; 466 | uint16_t stride; 467 | const uint32_t *bitmap; 468 | } font_t; 469 | 470 | const font_t NF20x24 = { 20, 24, 1, 24, 1, (const uint32_t *)numfont20x24 }; 471 | const font_t NF32x24 = { 32, 24, 1, 24, 1, (const uint32_t *)numfont32x24 }; 472 | const font_t NF32x48 = { 32, 48, 2, 24, 1, (const uint32_t *)numfont32x24 }; 473 | const font_t ICON48x20 = { 48, 20, 1, 40, 2, (const uint32_t *)icons48x20 }; 474 | 475 | void 476 | ili9341_drawfont_dma(uint8_t ch, const font_t *font, int x, int y, uint16_t fg, uint16_t bg) 477 | { 478 | int ex = x + font->width-1; 479 | int ey = y + font->height-1; 480 | uint8_t xx[4] = { x >> 8, x, ex >> 8, ex }; 481 | uint8_t yy[4] = { y >> 8, y, ey >> 8, ey }; 482 | uint16_t *buf = spi_buffer; 483 | uint32_t bits; 484 | const uint32_t *bitmap = &font->bitmap[font->slide * ch]; 485 | int c, r, j, b; 486 | 487 | for (c = 0; c < font->slide; c += font->stride) { 488 | for (j = 0; j < font->scaley; j++) { 489 | int cc = c; 490 | for (r = 0; r < font->width;) { 491 | bits = bitmap[cc++]; 492 | for (b = 0; b < 32 && r < font->width; b++,r++) { 493 | *buf++ = (0x80000000UL & bits) ? fg : bg; 494 | bits <<= 1; 495 | } 496 | } 497 | } 498 | } 499 | ssp_databit8(); 500 | send_command(0x2A, 4, xx); 501 | send_command(0x2B, 4, yy); 502 | send_command(0x2C, 0, NULL); 503 | ssp_databit16(); 504 | //spi_dma_transfer(spi_buffer, 4); 505 | //spi_dma_sync(); 506 | spi_dma_transfer(spi_buffer, buf - spi_buffer, 0); 507 | spi_dma_sync(); 508 | } 509 | 510 | void 511 | ili9341_drawfont_string(char *str, const font_t *font, int x, int y, uint16_t fg, uint16_t bg) 512 | { 513 | while (*str) { 514 | char c = *str++; 515 | if (c >= '0' && c <= '9') 516 | ili9341_drawfont_dma(c - '0', font, x, y, fg, bg); 517 | else if (c > 0 && c < 7) 518 | ili9341_drawfont_dma(c + 9, font, x, y, fg, bg); 519 | else if (c == '.') 520 | ili9341_drawfont_dma(10, font, x, y, fg, bg); 521 | else if (c == '-') 522 | ili9341_drawfont_dma(11, font, x, y, fg, bg); 523 | else 524 | ili9341_fill(x, y, font->width, font->height, bg); 525 | x += font->width; 526 | } 527 | } 528 | 529 | void 530 | ili9341_drawchar_dma(uint8_t ch, int x, int y, uint16_t fg, uint16_t bg) 531 | { 532 | int ex = x + 4; 533 | int ey = y + 7; 534 | uint8_t xx[4] = { x >> 8, x, ex >> 8, ex }; 535 | uint8_t yy[4] = { y >> 8, y, ey >> 8, ey }; 536 | uint16_t *buf = spi_buffer; 537 | 538 | uint16_t bits; 539 | int c, r; 540 | for(c = 0; c < 7; c++) { 541 | bits = x5x7_bits[(ch * 7) + c]; 542 | for (r = 0; r < 5; r++) { 543 | *buf++ = (0x8000 & bits) ? fg : bg; 544 | bits <<= 1; 545 | } 546 | } 547 | ssp_databit8(); 548 | send_command(0x2A, 4, xx); 549 | send_command(0x2B, 4, yy); 550 | send_command(0x2C, 0, NULL); 551 | ssp_databit16(); 552 | spi_dma_transfer(spi_buffer, 35, 0); 553 | spi_dma_sync(); 554 | } 555 | 556 | void 557 | ili9341_drawstring_dma(char *str, int x, int y, uint16_t fg, uint16_t bg) 558 | { 559 | //spi_dma_setup(); 560 | while (*str) { 561 | ili9341_drawchar_dma(*str, x, y, fg, bg); 562 | x += 5; 563 | str++; 564 | } 565 | } 566 | 567 | void 568 | ili9341_drawchar(uint8_t ch, int x, int y, uint16_t fg, uint16_t bg) 569 | { 570 | uint16_t bits; 571 | int c, r; 572 | for(c = 0; c < 7; c++) { 573 | bits = x5x7_bits[(ch * 7) + c]; 574 | for (r = 0; r < 5; r++) { 575 | ili9341_pixel(x+r, y+c, (0x8000 & bits) ? fg : bg); 576 | bits <<= 1; 577 | } 578 | } 579 | } 580 | 581 | void 582 | ili9341_drawstring(char *str, int x, int y, uint16_t fg, uint16_t bg) 583 | { 584 | while (*str) { 585 | ili9341_drawchar(*str, x, y, fg, bg); 586 | x += 5; 587 | str++; 588 | } 589 | } 590 | 591 | 592 | void 593 | ili9341_bulk_test() 594 | { 595 | int x, y; 596 | //while (1) { 597 | for(y = 0; y < 320; y++) { 598 | int sx = 0, ex = 240; 599 | int sy = y, ey = y+1; 600 | uint8_t xx[4] = { sx >> 8, sx, ex >> 8, ex }; 601 | uint8_t yy[4] = { sy >> 8, sy, ey >> 8, ey }; 602 | ssp_databit8(); 603 | send_command(0x2A, 4, xx); 604 | send_command(0x2B, 4, yy); 605 | send_command(0x2C, 0, NULL); 606 | ssp_databit16(); 607 | for (x = 0; x < 240; x++) 608 | ssp_senddata((y<<8)|x); 609 | } 610 | //systick_delay(100); 611 | //} 612 | } 613 | 614 | // result is 8.8 format 615 | static inline uint16_t 616 | log2_q31(uint32_t x) 617 | { 618 | uint32_t mask = 0xffff0000; 619 | uint16_t bit = 16; 620 | uint16_t y = 32;//-15; 621 | uint8_t i; 622 | 623 | if (x == 0) 624 | return 0; 625 | // 16 626 | if ((x & mask) == 0) { 627 | x <<= bit; 628 | y -= bit; 629 | } 630 | bit >>= 1; 631 | mask <<= bit; 632 | // 8 633 | if ((x & mask) == 0) { 634 | x <<= bit; 635 | y -= bit; 636 | } 637 | bit >>= 1; 638 | mask <<= bit; 639 | // 4 640 | if ((x & mask) == 0) { 641 | x <<= bit; 642 | y -= bit; 643 | } 644 | bit >>= 1; 645 | mask <<= bit; 646 | // 2 647 | if ((x & mask) == 0) { 648 | x <<= bit; 649 | y -= bit; 650 | } 651 | bit >>= 1; 652 | mask <<= bit; 653 | // 1 654 | if ((x & mask) == 0) { 655 | x <<= bit; 656 | y -= bit; 657 | } 658 | // msb should be 1. take next 8 bits. 659 | i = (x >> 23) & 0xff; 660 | // lookup logarythm table 661 | return (y << 8) | i; 662 | } 663 | 664 | arm_cfft_radix4_instance_q31 cfft_inst; 665 | 666 | //#define mag(r,i) (q31_t)(((q63_t)r*r)>>33)+(q31_t)(((q63_t)i*i)>>33) 667 | 668 | void 669 | draw_spectrogram() 670 | { 671 | q31_t *buf = SPDISPINFO->buffer; 672 | arm_cfft_radix4_q31(&cfft_inst, buf); 673 | //arm_cmplx_mag_q31(buf, buf, 1024); 674 | // arm_cmplx_mag_squared_q31(buf, buf, 1024); 675 | //draw_samples(); 676 | //return; 677 | uint16_t gainshift = SPDISPINFO->p.overgain; 678 | int i = SPDISPINFO->p.offset; 679 | int stride = SPDISPINFO->p.stride; 680 | uint16_t (*block)[32] = (uint16_t (*)[32])spi_buffer; 681 | int sx, x, y; 682 | for (sx = 0; sx < 320; sx += 32) { 683 | for (x = 0; x < 32; x++) { 684 | q31_t ii = buf[(i&1023)*2]; 685 | q31_t qq = buf[(i&1023)*2+1]; 686 | q31_t mag = ((int64_t)ii*ii + (int64_t)qq*qq)>>(33-gainshift); 687 | //q31_t mag = buf[i & 1023]; 688 | int v = log2_q31(mag) >> 6; 689 | if (v > 64) v = 64; 690 | for (y = 0; y < v; y++) 691 | block[63-y][x] = 0xffff; 692 | for ( ; y < 64; y++) 693 | block[63-y][x] = 0; 694 | i += stride; 695 | } 696 | ili9341_draw_bitmap(sx, 72, 32, 64, (uint16_t*)block); 697 | } 698 | } 699 | 700 | #define RGB565(r,g,b) ( (((r)<<8)&0xf800) | (((g)<<3)&0x07e0) | ((b)&0x001f) ) 701 | 702 | const struct { uint8_t r,g,b; } colormap[] = { 703 | { 0, 0, 0 }, 704 | { 0, 0, 255 }, 705 | { 0, 255, 0 }, 706 | { 255, 0, 0 }, 707 | { 255, 255, 255 } 708 | }; 709 | 710 | uint16_t 711 | pick_color(int mag) /* mag: 0 - 63 */ 712 | { 713 | int idx = (mag >> 4) & 0x3; 714 | int prop = mag & 0x0f; 715 | int nprop = 0x10 - prop; 716 | int r = colormap[idx].r * nprop + colormap[idx+1].r * prop; 717 | int g = colormap[idx].g * nprop + colormap[idx+1].g * prop; 718 | int b = colormap[idx].b * nprop + colormap[idx+1].b * prop; 719 | return RGB565(r>>4, g>>4, b>>4); 720 | } 721 | 722 | void 723 | waterfall_init(void) 724 | { 725 | // Vertical Scroll Definition 726 | uint16_t tfa = 152; 727 | uint16_t vsa = 240 - tfa; 728 | uint16_t bfa = 80; 729 | uint8_t vsd[6] = { tfa>>8, tfa, vsa>>8, vsa, bfa>>8, bfa }; 730 | send_command(0x33, 6, vsd); 731 | } 732 | 733 | int vsa = 152; 734 | 735 | void 736 | draw_waterfall(void) 737 | { 738 | int x; 739 | q31_t *buf = SPDISPINFO->buffer; 740 | uint16_t *block = spi_buffer; 741 | int i = SPDISPINFO->p.offset; 742 | int stride = SPDISPINFO->p.stride; 743 | uint16_t gainshift = SPDISPINFO->p.overgain; 744 | 745 | for (x = 0; x < 320; x++) { 746 | q31_t ii = buf[(i&1023)*2]; 747 | q31_t qq = buf[(i&1023)*2+1]; 748 | q31_t mag = ((int64_t)ii*ii + (int64_t)qq*qq)>>(33-gainshift); 749 | //q31_t mag = buf[i & 1023]; 750 | int v = log2_q31(mag) >> 6; 751 | if (v > 63) v = 63; 752 | *block++ = pick_color(v); 753 | i += stride; 754 | } 755 | 756 | vsa++; 757 | if (vsa >= 240) 758 | vsa = 152; 759 | 760 | // Vertical Scroll Address 761 | uint8_t vscrsadd[2] = { vsa>>8, vsa }; 762 | send_command(0x37, 2, vscrsadd); 763 | 764 | ili9341_draw_bitmap(0, vsa, 320, 1, spi_buffer); 765 | } 766 | 767 | void 768 | draw_tick(void) 769 | { 770 | char str[10]; 771 | int x = SPDISPINFO->p.origin; 772 | int base = SPDISPINFO->p.tickbase; 773 | int xx; 774 | uint16_t bg = UISTAT->mode == SPDISP ? BG_ACTIVE : BG_NORMAL; 775 | 776 | ili9341_fill(0, 136, 320, 16, bg); 777 | sprintf(str, "%d%s", base, SPDISPINFO->p.unitname); 778 | xx = x - strlen(str) * 5 / 2; 779 | if (xx < 0) xx = 0; 780 | ili9341_drawstring_dma(str, xx, 142, 0xffff, bg); 781 | ili9341_fill(x, 136, 2, 5, 0xffff); 782 | 783 | base += SPDISPINFO->p.tickunit; 784 | x += SPDISPINFO->p.tickstep; 785 | while (x < 320) { 786 | sprintf(str, "%d", base); 787 | ili9341_fill(x, 136, 2, 5, 0xffff); 788 | ili9341_drawstring_dma(str, x, 142, 0xffff, bg); 789 | base += SPDISPINFO->p.tickunit; 790 | x += SPDISPINFO->p.tickstep; 791 | } 792 | x = SPDISPINFO->p.origin; 793 | base = SPDISPINFO->p.tickbase; 794 | base -= SPDISPINFO->p.tickunit; 795 | x -= SPDISPINFO->p.tickstep; 796 | while (x >= 0) { 797 | sprintf(str, "%d", base); 798 | ili9341_fill(x, 136, 2, 5, 0xffff); 799 | ili9341_drawstring_dma(str, x, 142, 0xffff, bg); 800 | base -= SPDISPINFO->p.tickunit; 801 | x -= SPDISPINFO->p.tickstep; 802 | } 803 | } 804 | 805 | void 806 | draw_freq(void) 807 | { 808 | char str[10]; 809 | uint16_t bg = UISTAT->mode == FREQ ? BG_ACTIVE : BG_NORMAL; 810 | int i; 811 | const uint16_t xsim[] = { 0, 16, 0, 0, 16, 0, 0, 0 }; 812 | uint16_t x = 0; 813 | sprintf(str, "%8d", UISTAT->freq); 814 | for (i = 0; i < 8; i++) { 815 | int8_t c = str[i] - '0'; 816 | uint16_t fg = 0xffff; 817 | if (UISTAT->mode == FREQ && UISTAT->digit == 7-i) 818 | fg = 0xfe40; 819 | 820 | if (c >= 0 && c <= 9) 821 | ili9341_drawfont_dma(c, &NF32x48, x, 0, fg, bg); 822 | else 823 | ili9341_fill(x, 0, 32, 48, bg); 824 | x += 32; 825 | 826 | // fill gaps 827 | if (xsim[i] > 0) { 828 | ili9341_fill(x, 0, xsim[i], 48, bg); 829 | x += xsim[i]; 830 | } 831 | } 832 | // draw Hz symbol 833 | ili9341_drawfont_dma(10, &NF32x48, x, 0, 0xffff, bg); 834 | } 835 | 836 | void 837 | draw_info(void) 838 | { 839 | char str[10]; 840 | int x = 0; 841 | int y = 48; 842 | uint16_t bg = UISTAT->mode == GAIN ? BG_ACTIVE : BG_NORMAL; 843 | ili9341_drawfont_dma(14, &NF20x24, x, y, 0xfffe, bg); 844 | x += 20; 845 | if (UISTAT->gain != -7) 846 | sprintf(str, "%2d", UISTAT->gain); 847 | else 848 | // -infinity 849 | sprintf(str, "-\003", UISTAT->gain); 850 | ili9341_drawfont_string(str, &NF20x24, x, y, 0xfffe, bg); 851 | x += 40; 852 | ili9341_drawfont_dma(13, &NF20x24, x, y, 0xfffe, bg); 853 | x += 20; 854 | 855 | bg = UISTAT->mode == MOD ? BG_ACTIVE : BG_NORMAL; 856 | ili9341_drawfont_dma(UISTAT->modulation, &ICON48x20, x+2, y+2, 0xffe0, bg); 857 | x += 48+4; 858 | 859 | bg = UISTAT->mode == AGCMODE ? BG_ACTIVE : BG_NORMAL; 860 | ili9341_drawfont_dma(UISTAT->agcmode + 2, &ICON48x20, x+2, y+2, 0xffff, bg); 861 | x += 48+4; 862 | 863 | bg = UISTAT->mode == RFGAIN ? BG_ACTIVE : BG_NORMAL; 864 | ili9341_drawfont_dma(15, &NF20x24, x, y, 0x07ff, bg); 865 | x += 20; 866 | sprintf(str, "%3d ", -6 * (int32_t)UISTAT->rfgain); 867 | ili9341_drawfont_string(str, &NF20x24, x, y, 0x07ff, bg); 868 | x += 60; 869 | ili9341_drawfont_dma(13, &NF20x24, x, y, 0x07ff, bg); 870 | x += 20; 871 | } 872 | 873 | void 874 | clear_background(void) 875 | { 876 | int i = 0; 877 | for (i = 0; i < 12; i++) { 878 | ili9341_fill(0, i*10, 320, 10, 0x0000); 879 | } 880 | } 881 | 882 | 883 | //volatile int count; 884 | 885 | // event handler sent from M4 core 886 | void M0_M4CORE_IRQHandler(void) { 887 | LPC_CREG->M4TXEVENT = 0; 888 | //ili9341_drawfont_dma(count++ % 10, &NF32x48, 192, 0, 0xffC0, 0x0000); 889 | 890 | if (SPDISPINFO->update_flag & FLAG_SPDISP) { 891 | draw_spectrogram(); 892 | draw_waterfall(); 893 | SPDISPINFO->update_flag &= ~FLAG_SPDISP; 894 | } 895 | if (SPDISPINFO->update_flag & FLAG_UI) { 896 | draw_tick(); 897 | draw_freq(); 898 | draw_info(); 899 | SPDISPINFO->update_flag &= ~FLAG_UI; 900 | } 901 | } 902 | 903 | //volatile int8_t pending_launch = 0; 904 | 905 | int main(void) { 906 | //char buf[16]; 907 | //int i; 908 | 909 | //while (pending_launch) 910 | // ; 911 | 912 | CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = 12000000; 913 | CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 204000000; 914 | 915 | //printf("Hello M0APP\n"); 916 | 917 | // Setup SysTick Timer to interrupt at 1 msec intervals 918 | //SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE)/1000); 919 | RITConfig(); 920 | 921 | systick_delay(1000); 922 | 923 | arm_cfft_radix4_init_q31(&cfft_inst, 1024, FALSE, TRUE); 924 | 925 | //RGU_SoftReset(RGU_SIG_I2C0); 926 | 927 | //NVIC_SetPriority(DMA_IRQn, ((0x01<<3)|0x01)); 928 | 929 | scu_pinmux(1, 7, GPIO_PUP, FUNC0); // GPIO1-0 930 | scu_pinmux(1, 8, GPIO_PUP, FUNC0); // GPIO1-1 931 | scu_pinmux(1, 9, GPIO_PUP, FUNC0); // GPIO1-2 932 | 933 | spi_init(); 934 | ili9341_init(); 935 | waterfall_init(); 936 | clear_background(); 937 | 938 | //spi_test(); 939 | #if 0 940 | ili9341_drawfont_dma(0, &ICON48x20, 0, 48, 0xffe0, 0x0000); // LSB 941 | ili9341_drawfont_dma(1, &ICON48x20, 48, 48, 0x07ff, 0x0000); // USB 942 | ili9341_drawfont_dma(2, &ICON48x20, 96, 48, 0xffff, 0x0000); // OFF 943 | ili9341_drawfont_dma(3, &ICON48x20, 48*3, 48, 0xffff, 0x0000); // FAST 944 | ili9341_drawfont_dma(4, &ICON48x20, 48*4, 48, 0xffff, 0x0000); // SLOW 945 | ili9341_drawfont_dma(5, &ICON48x20, 48*5, 48, 0xffff, 0x0000); // MID 946 | #endif 947 | #if 0 948 | //ili9341_test(); 949 | //ili9341_dma_test(); 950 | //ili9341_bulk_test(); 951 | //ili9341_drawstring_dma("Hello", 100, 100, 0xffff, 0x0000); 952 | for (i = 0; i < 10; i++) 953 | ili9341_drawfont_dma(i, &NF20x24, i*20, 48, 0xffe0, 0x0000); 954 | for (i = 0; i < 5; i++) 955 | ili9341_drawfont_dma(i, &NF32x48, i*32, 0, 0xffff, 0x0000); 956 | //for (i = 0; i < 5; i++) 957 | // ili9341_drawfont_dma(i+5, &NF32x48, i*32, 92, 0xffff, 0x0000); 958 | #endif 959 | 960 | NVIC_SetPriority(M0_M4CORE_IRQn, 4); 961 | NVIC_EnableIRQ(M0_M4CORE_IRQn); 962 | #if 0 963 | while (1) { 964 | for (i = 0; i < 10; i++) { 965 | ili9341_drawfont_dma(i, &NF32x48, 0, 140, 0xffff, 0x0000); 966 | systick_delay(200); 967 | } 968 | } 969 | #endif 970 | #if 0 971 | 972 | GPIO_SetDir(0,1<<8, 1); 973 | GPIO_ClearValue(0,1<<8); 974 | 975 | GPIO_SetDir(1,0x7, 0); 976 | GPIO_SetDir(1,1<<3, 1); 977 | GPIO_SetDir(1,1<<4, 1); 978 | GPIO_ClearValue(1,1<<3); 979 | GPIO_ClearValue(1,1<<4); 980 | #endif 981 | //i2clcd_init(); 982 | //i2clcd_str("Hello"); 983 | 984 | // Force the counter to be placed into memory 985 | //volatile static int i = 0 ; 986 | // Enter an infinite loop, just incrementing a counter 987 | while(1) { 988 | #if 0 989 | #if 1 990 | int status = btn_check(); 991 | if (status == 0) 992 | continue; 993 | if (status & EVT_BUTTON_SINGLE_CLICK) 994 | i += 10; 995 | if (status & EVT_BUTTON_DOUBLE_CLICK) 996 | i -= 10; 997 | if (status & EVT_BUTTON_DOWN_LONG) 998 | i = 0; 999 | if (status & ENCODER_UP) 1000 | i++; 1001 | if (status & ENCODER_DOWN) 1002 | i--; 1003 | #else 1004 | systick_delay(500); 1005 | GPIO_SetValue(0,1<<8); 1006 | GPIO_SetValue(1,1<<3); 1007 | systick_delay(500); 1008 | GPIO_ClearValue(1,1<<3); 1009 | GPIO_SetValue(1,1<<4); 1010 | systick_delay(500); 1011 | GPIO_SetValue(1,1<<3); 1012 | systick_delay(500); 1013 | GPIO_ClearValue(0,1<<8); 1014 | GPIO_ClearValue(1,1<<3); 1015 | GPIO_ClearValue(1,1<<4); 1016 | i++ ; 1017 | #endif 1018 | #endif 1019 | #if 0 1020 | sprintf(buf, "%d ", i); 1021 | i2clcd_pos(0, 1); 1022 | //i2clcd_data(0x30 + (i % 10)); 1023 | i2clcd_str(buf); 1024 | //value = GPIO_ReadValue(1); 1025 | //sprintf(buf, "%d", value & 0x7); 1026 | //i2clcd_data(' '); 1027 | //i2clcd_str(buf); 1028 | #endif 1029 | } 1030 | return 0 ; 1031 | } 1032 | 1033 | #ifdef DEBUG 1034 | void check_failed(uint8_t *file, uint32_t line) 1035 | { 1036 | /* User can add his own implementation to report the file name and line number, 1037 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 1038 | 1039 | /* Infinite loop */ 1040 | while(1); 1041 | } 1042 | #endif 1043 | -------------------------------------------------------------------------------- /DisplayM0APP/src/icons.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | 21 | #include 22 | 23 | const uint32_t icons48x20[][2*20] = { 24 | { // LSB 25 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 26 | 0b00111111111111111111111101111111, 0b11111111111111000000000000000000, 27 | 0b01111100001111111111110000011110, 0b00000001111111100000000000000000, 28 | 0b01111100001111111111000000000110, 0b00000000011111100000000000000000, 29 | 0b11111100001111111110000000000010, 0b00000000001111110000000000000000, 30 | 0b11111100001111111100000110000010, 0b00000000000111110000000000000000, 31 | 0b11111100001111111100001111000010, 0b00011100000111110000000000000000, 32 | 0b11111100001111111100000111111110, 0b00011110000111110000000000000000, 33 | 34 | 0b11111100001111111110000001111110, 0b00011100001111110000000000000000, 35 | 0b11111100001111111111000000011110, 0b00000000011111110000000000000000, 36 | 0b11111100001111111111110000001110, 0b00000000011111110000000000000000, 37 | 0b11111100001111111111111100000110, 0b00011100001111110000000000000000, 38 | 0b11111100001111111111111110000010, 0b00011110000111110000000000000000, 39 | 0b11111100001111111100001111000010, 0b00011100000111110000000000000000, 40 | 0b11111100000000000100000110000010, 0b00000000000111110000000000000000, 41 | 0b11111100000000000110000000000110, 0b00000000001111110000000000000000, 42 | 43 | 0b01111100000000000111000000001110, 0b00000000011111100000000000000000, 44 | 0b01111100000000000111100000011110, 0b00000001111111100000000000000000, 45 | 0b00111111111111111111111101111111, 0b11111111111111000000000000000000, 46 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 47 | }, 48 | { // USB 49 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 50 | 0b00111111111111111111111101111111, 0b11111111111111000000000000000000, 51 | 0b01111000011110000111100000001110, 0b00000001111111100000000000000000, 52 | 0b01111000011110000111000000000110, 0b00000000011111100000000000000000, 53 | 0b11111000011110000110000000000010, 0b00000000001111110000000000000000, 54 | 0b11111000011110000100000110000010, 0b00000000000111110000000000000000, 55 | 0b11111000011110000100001111000010, 0b00011100000111110000000000000000, 56 | 0b11111000011110000100000111111110, 0b00011110000111110000000000000000, 57 | 58 | 0b11111000011110000110000011111110, 0b00011100001111110000000000000000, 59 | 0b11111000011110000111000000111110, 0b00000000011111110000000000000000, 60 | 0b11111000011110000111100000001110, 0b00000000011111110000000000000000, 61 | 0b11111000011110000111111000000110, 0b00011100001111110000000000000000, 62 | 0b11111000011110000111111110000010, 0b00011110000111110000000000000000, 63 | 0b11111000001100000100001111000010, 0b00011100000111110000000000000000, 64 | 0b11111000000000000100000110000010, 0b00000000000111110000000000000000, 65 | 0b11111100000000001110000000000010, 0b00000000001111110000000000000000, 66 | 67 | 0b01111110000000011111000000000110, 0b00000000011111100000000000000000, 68 | 0b01111111000000111111100000001110, 0b00000001111111100000000000000000, 69 | 0b00111111111111111111111101111111, 0b11111111111111000000000000000000, 70 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 71 | }, 72 | { // OFF 73 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 74 | 0b00100000000000000000000000000000, 0b00000000000011000000000000000000, 75 | 0b01000000011111000001111111111101, 0b11111111110000100000000000000000, 76 | 0b10000001111111110001111111111101, 0b11111111110000100000000000000000, 77 | 0b10000011111111111001111111111101, 0b11111111110000010000000000000000, 78 | 0b10000111110001111101111111111101, 0b11111111110000010000000000000000, 79 | 0b10000111100000111101111000000001, 0b11100000000000010000000000000000, 80 | 0b10000111100000111101111000000001, 0b11100000000000010000000000000000, 81 | 82 | 0b10000111100000111101111000000001, 0b11100000000000010000000000000000, 83 | 0b10000111100000111101111111111001, 0b11111111100000010000000000000000, 84 | 0b10000111100000111101111111111001, 0b11111111100000010000000000000000, 85 | 0b10000111100000111101111111111001, 0b11111111100000010000000000000000, 86 | 0b10000111100000111101111111111001, 0b11111111100000010000000000000000, 87 | 0b10000111100000111101111000000001, 0b11100000000000010000000000000000, 88 | 0b10000111110001111101111000000001, 0b11100000000000010000000000000000, 89 | 0b10000011111111111001111000000001, 0b11100000000000010000000000000000, 90 | 91 | 0b01000001111111110001111000000001, 0b11100000000000100000000000000000, 92 | 0b01000000011111000001111000000001, 0b11100000000000100000000000000000, 93 | 0b00110000000000000000000000000000, 0b00000000000011000000000000000000, 94 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 95 | }, 96 | { // SLOW 97 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 98 | 0b00100000000000000000000000000000, 0b00000000000011000000000000000000, 99 | 0b01000001111000011100000000111110, 0b00111000001110100000000000000000, 100 | 0b10000111111110011100000001111111, 0b00111000001110100000000000000000, 101 | 0b10001111111111011100000011111111, 0b10111000001110010000000000000000, 102 | 0b10001111111111011100000011111111, 0b10111011101110010000000000000000, 103 | 0b10001110001111011100000011100011, 0b10111011101110010000000000000000, 104 | 0b10001111000111011100000011100011, 0b10111011101110010000000000000000, 105 | 106 | 0b10000111110000011100000011100011, 0b10111011101110010000000000000000, 107 | 0b10000011111100011100000011100011, 0b10111011101110010000000000000000, 108 | 0b10000001111100011100000011100011, 0b10111011101110010000000000000000, 109 | 0b10000000111110011100000011100011, 0b10111111111110010000000000000000, 110 | 0b10001110001111011100000011100011, 0b10111111111110010000000000000000, 111 | 0b10001111000111011100000011100011, 0b10011111111100010000000000000000, 112 | 0b10001111111111011111111011111111, 0b10011111111100010000000000000000, 113 | 0b10001111111111011111111011111111, 0b10011110111100010000000000000000, 114 | 115 | 0b01000111111110011111111001111111, 0b00011100011100100000000000000000, 116 | 0b01000001111000011111111000111110, 0b00011100011100100000000000000000, 117 | 0b00110000000000000000000000000000, 0b00000000000011000000000000000000, 118 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 119 | }, 120 | { // MID 121 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 122 | 0b00100000000000000000000000000000, 0b00000000000011000000000000000000, 123 | 0b01000111100000001111011111111011, 0b11111100000000100000000000000000, 124 | 0b10000111110000011111011111111011, 0b11111111000000100000000000000000, 125 | 0b10000111110000011111011111111011, 0b11111111110000010000000000000000, 126 | 0b10000111111000111111000111100011, 0b11111111110000010000000000000000, 127 | 0b10000111111000111111000111100011, 0b11000111111000010000000000000000, 128 | 0b10000111111101111111000111100011, 0b11000011111000010000000000000000, 129 | 130 | 0b10000111111111111111000111100011, 0b11000001111000010000000000000000, 131 | 0b10000111111111111111000111100011, 0b11000001111000010000000000000000, 132 | 0b10000111101111101111000111100011, 0b11000001111000010000000000000000, 133 | 0b10000111101111101111000111100011, 0b11000001111000010000000000000000, 134 | 0b10000111100111001111000111100011, 0b11000011111000010000000000000000, 135 | 0b10000111100111001111000111100011, 0b11000111111000010000000000000000, 136 | 0b10000111100111001111000111100011, 0b11111111110000010000000000000000, 137 | 0b10000111100000001111011111111011, 0b11111111110000010000000000000000, 138 | 139 | 0b01000111100000001111011111111011, 0b11111111000000100000000000000000, 140 | 0b01000111100000001111011111111011, 0b11111100000000100000000000000000, 141 | 0b00110000000000000000000000000000, 0b00000000000011000000000000000000, 142 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 143 | }, 144 | { // FAST 145 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 146 | 0b00100000000000000000000000000000, 0b00000000000011000000000000000000, 147 | 0b01001111111110001111000000011110, 0b00011111111100100000000000000000, 148 | 0b10001111111110001111000001111111, 0b10011111111100100000000000000000, 149 | 0b10001111111110011111100011111111, 0b11011111111100010000000000000000, 150 | 0b10001111111110011111100011111111, 0b11011111111100010000000000000000, 151 | 0b10001110000000011111100011100011, 0b11000011100000010000000000000000, 152 | 0b10001110000000111001110011110001, 0b11000011100000010000000000000000, 153 | 154 | 0b10001110000000111001110001111100, 0b00000011100000010000000000000000, 155 | 0b10001111111100111001110000111111, 0b00000011100000010000000000000000, 156 | 0b10001111111100111001110000011111, 0b00000011100000010000000000000000, 157 | 0b10001111111100111001110000001111, 0b10000011100000010000000000000000, 158 | 0b10001111111101111111111011100011, 0b11000011100000010000000000000000, 159 | 0b10001110000001111111111011110001, 0b11000011100000010000000000000000, 160 | 0b10001110000001111111111011111111, 0b11000011100000010000000000000000, 161 | 0b10001110000001110000111011111111, 0b11000011100000010000000000000000, 162 | 163 | 0b01001110000001110000111001111111, 0b10000011100000100000000000000000, 164 | 0b01001110000001110000111000011110, 0b00000011100000100000000000000000, 165 | 0b00110000000000000000000000000000, 0b00000000000011000000000000000000, 166 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 167 | }, 168 | { // WFM 169 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 170 | 0b00111111111111111111111101111111, 0b11111111111111000000000000000000, 171 | 0b01111000011110000111100000001110, 0b00000001111111100000000000000000, 172 | 0b01111000011110000111000000000110, 0b00000000011111100000000000000000, 173 | 0b11111000011110000110000000000010, 0b00000000001111110000000000000000, 174 | 0b11111000011110000100000110000010, 0b00000000000111110000000000000000, 175 | 0b11111000011110000100001111000010, 0b00011100000111110000000000000000, 176 | 0b11111000011110000100000111111110, 0b00011110000111110000000000000000, 177 | 178 | 0b11111000011110000110000011111110, 0b00011100001111110000000000000000, 179 | 0b11111000011110000111000000111110, 0b00000000011111110000000000000000, 180 | 0b11111000011110000111100000001110, 0b00000000011111110000000000000000, 181 | 0b11111000011110000111111000000110, 0b00011100001111110000000000000000, 182 | 0b11111000011110000111111110000010, 0b00011110000111110000000000000000, 183 | 0b11111000001100000100001111000010, 0b00011100000111110000000000000000, 184 | 0b11111000000000000100000110000010, 0b00000000000111110000000000000000, 185 | 0b11111100000000001110000000000010, 0b00000000001111110000000000000000, 186 | 187 | 0b01111110000000011111000000000110, 0b00000000011111100000000000000000, 188 | 0b01111111000000111111100000001110, 0b00000001111111100000000000000000, 189 | 0b00111111111111111111111101111111, 0b11111111111111000000000000000000, 190 | 0b00001111111111111111111111111111, 0b11111111111100001000000000000000, 191 | }, 192 | }; 193 | 194 | #if 0 195 | const uint32_t icons64x24[][2*24] = { 196 | { // LSB 197 | 0b00001111111111111111111111111111, 0b11111111111111111111111111110000, 198 | 0b00111111111111111111111111111111, 0b11111111111111111111111111111100, 199 | 0b00111111111111111111111111111111, 0b11111111111111111111111111111100, 200 | 0b01111111100001111111111111110000, 0b01111111000000000011111111111110, 201 | 0b01111111100001111111111110000000, 0b00001111000000000000011111111110, 202 | 0b11111111100001111111111100000000, 0b00000111000000000000001111111111, 203 | 0b11111111100001111111111000000000, 0b00000011000000000000000111111111, 204 | 0b11111111100001111111111000001111, 0b10000011000011111100000111111111, 205 | 206 | 0b11111111100001111111111000000111, 0b11000011000011111110000111111111, 207 | 0b11111111100001111111111000000001, 0b11111111000011111000000111111111, 208 | 0b11111111100001111111111110000000, 0b11111111000000000000011111111111, 209 | 0b11111111100001111111111111100000, 0b00111111000000000000111111111111, 210 | 0b11111111100001111111111111111000, 0b00011111000000000000011111111111, 211 | 0b11111111100001111111111111111110, 0b00000111000011111000001111111111, 212 | 0b11111111100001111111111000011111, 0b00000011000011111110000111111111, 213 | 0b11111111100001111111111000001111, 0b10000011000011111100000111111111, 214 | 215 | 0b11111111100000000000001000000000, 0b00000011000000000000000111111111, 216 | 0b11111111100000000000001100000000, 0b00000111000000000000001111111111, 217 | 0b01111111100000000000001111000000, 0b00001111000000000000011111111110, 218 | 0b01111111100000000000001111111000, 0b01111111000000000011111111111110, 219 | 0b00111111111111111111111111111111, 0b11111111111111111111111111111100, 220 | 0b00111111111111111111111111111111, 0b11111111111111111111111111111100, 221 | 0b00001111111111111111111111111111, 0b11111111111111111111111111110000, 222 | 0b00000000000000000000000000000000, 0b00000000000000000000000000000000, 223 | }, 224 | }; 225 | const uint32_t icons64x16[][2*16] = { 226 | { // LSB 227 | 0b00001111111111111111111111111111, 0b11111111111111111111111111110000, 228 | 0b00111111111111111111111111111111, 0b11111111111111111111111111111100, 229 | 0b01110001111111111111111111100000, 0b00000111111000000000000001111110, 230 | 0b01110001111111111111111100000000, 0b00000000111000000000000000011110, 231 | 0b11110001111111111111110000000000, 0b00000000011000000000000000001111, 232 | 0b11110001111111111111110000011111, 0b11111000011000111111111110001111, 233 | 0b11110001111111111111111000000111, 0b11111100011000111111111100001111, 234 | 0b11110001111111111111111110000000, 0b00011111111000000000000000011111, 235 | 236 | 0b11110001111111111111111111110000, 0b00000011111000000000000000011111, 237 | 0b11110001111111111111110001111111, 0b10000000111000111111111100001111, 238 | 0b11110001111111111111110000111111, 0b11110000011000111111111110001111, 239 | 0b11110000000000000000111000000000, 0b00000000011000000000000000001111, 240 | 0b01110000000000000000111100000000, 0b00000000111000000000000000011110, 241 | 0b01110000000000000000111111100000, 0b00000111111000000000000001111110, 242 | 0b00111111111111111111111111111111, 0b11111111111111111111111111111100, 243 | 0b00001111111111111111111111111111, 0b11111111111111111111111111110000, 244 | } 245 | }; 246 | 247 | const uint32_t icons32x12[][12] = { 248 | { // LSB 249 | 0b00111111111111111111111111111000, 250 | 0b01100111111110000111100000111100, 251 | 0b11100111111100000011100000011110, 252 | 0b11100111111000110001100111001110, 253 | 0b11100111111001111001100111001110, 254 | 0b11100111111000111111100000011110, 255 | 0b11100111111100000111100000011110, 256 | 0b11100111111111110000100111001110, 257 | 258 | 0b11100111111001111000100111001110, 259 | 0b11100000001000000000100000001110, 260 | 0b01100000001110000011100000111100, 261 | 0b00111111111111111111111111111000, 262 | }, 263 | }; 264 | #endif 265 | -------------------------------------------------------------------------------- /DisplayM0APP/src/numfont20x24.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | 21 | #include 22 | 23 | const uint32_t numfont20x24[][24] = { 24 | { // 0 25 | 0b00000111111111000000100000000000, 26 | 0b00011111111111110000000000000000, 27 | 0b00111111111111111000000000000000, 28 | 0b01111111111111111100000000000000, 29 | 0b01111110000011111100000000000000, 30 | 0b11111100000001111110000000000000, 31 | 0b11111000000000111110000000000000, 32 | 0b11111000000000111110000000000000, 33 | 34 | 0b11111000000000111110000000000000, 35 | 0b11111000000000111110000000000000, 36 | 0b11111000000000111110000000000000, 37 | 0b11111000000000111110000000000000, 38 | 0b11111000000000111110000000000000, 39 | 0b11111000000000111110000000000000, 40 | 0b11111000000000111110000000000000, 41 | 0b11111000000000111110000000000000, 42 | 43 | 0b11111100000001111110000000000000, 44 | 0b01111110000011111100000000000000, 45 | 0b01111111111111111100000000000000, 46 | 0b00111111111111111000000000000000, 47 | 0b00011111111111110000000000000000, 48 | 0b00000111111111000000100000000000, 49 | 0b00000000000000000000000000000000, 50 | 0b00000000000000000000000000000000 51 | }, 52 | { // 1 53 | 0b00000000011111000000100000000000, 54 | 0b00000000111111000000000000000000, 55 | 0b00000000111111000000000000000000, 56 | 0b00000001111111000000000000000000, 57 | 0b00000111111111000000000000000000, 58 | 0b00011111111111000000000000000000, 59 | 0b00011111111111000000000000000000, 60 | 0b00011111111111000000000000000000, 61 | 62 | 0b00011111011111000000000000000000, 63 | 0b00011111011111000000000000000000, 64 | 0b00000000011111000000000000000000, 65 | 0b00000000011111000000000000000000, 66 | 0b00000000011111000000000000000000, 67 | 0b00000000011111000000000000000000, 68 | 0b00000000011111000000000000000000, 69 | 0b00000000011111000000000000000000, 70 | 71 | 0b00000000011111000000000000000000, 72 | 0b00000000011111000000000000000000, 73 | 0b00000000011111000000000000000000, 74 | 0b00000000011111000000000000000000, 75 | 0b00000000011111000000000000000000, 76 | 0b00000000011111000000000000000000, 77 | 0b00000000000000000000000000000000, 78 | 0b00000000000000000000000000000000 79 | }, 80 | { // 2 81 | 0b00000011111110000000100000000000, 82 | 0b00001111111111100000000000000000, 83 | 0b00111111111111111000000000000000, 84 | 0b01111111111111111100000000000000, 85 | 0b01111110000011111100000000000000, 86 | 0b11111100000001111110000000000000, 87 | 0b11111000000000111110000000000000, 88 | 0b11111000000001111110000000000000, 89 | 90 | 0b00000000000011111110000000000000, 91 | 0b00000000001111111100000000000000, 92 | 0b00000001111111111000000000000000, 93 | 0b00000111111111100000000000000000, 94 | 0b00011111111100000000000000000000, 95 | 0b00111111110000000000000000000000, 96 | 0b01111111000000000000000000000000, 97 | 0b11111100000000000000000000000000, 98 | 99 | 0b11111000000000000000000000000000, 100 | 0b11111000000000000000000000000000, 101 | 0b11111111111111111110000000000000, 102 | 0b11111111111111111110000000000000, 103 | 0b11111111111111111110000000000000, 104 | 0b11111111111111111110000000000000, 105 | 0b00000000000000000000000000000000, 106 | 0b00000000000000000000000000000000 107 | }, 108 | { // 3 109 | 0b00000011111110000000100000000000, 110 | 0b00001111111111100000000000000000, 111 | 0b00111111111111111000000000000000, 112 | 0b01111111111111111100000000000000, 113 | 0b01111110000011111100000000000000, 114 | 0b11111100000001111110000000000000, 115 | 0b11111000000000111110000000000000, 116 | 0b11111000000001111110000000000000, 117 | 118 | 0b00000000000011111100000000000000, 119 | 0b00000000111111111100000000000000, 120 | 0b00000000111111110000000000000000, 121 | 0b00000000111111110000000000000000, 122 | 0b00000000111111111000000000000000, 123 | 0b00000000000011111100000000000000, 124 | 0b11111000000000111110000000000000, 125 | 0b11111000000000111110000000000000, 126 | 127 | 0b11111000000000111110000000000000, 128 | 0b11111100000001111110000000000000, 129 | 0b01111111111111111100000000000000, 130 | 0b00111111111111111000000000000000, 131 | 0b00001111111111110000000000000000, 132 | 0b00000001111110000000100000000000, 133 | 0b00000000000000000000000000000000, 134 | 0b00000000000000000000000000000000 135 | }, 136 | { // 4 137 | 0b00000000000011110000100000000000, 138 | 0b00000000000111110000000000000000, 139 | 0b00000000001111110000000000000000, 140 | 0b00000000011111110000000000000000, 141 | 0b00000000111111110000000000000000, 142 | 0b00000001111111110000000000000000, 143 | 0b00000011111111110000000000000000, 144 | 0b00000111111111110000000000000000, 145 | 146 | 0b00001111110111110000000000000000, 147 | 0b00011111100111110000000000000000, 148 | 0b00111111000111110000000000000000, 149 | 0b01111110000111110000000000000000, 150 | 0b11111100000111110000000000000000, 151 | 0b11111000000111110000000000000000, 152 | 0b11111111111111111110000000000000, 153 | 0b11111111111111111110000000000000, 154 | 155 | 0b11111111111111111110000000000000, 156 | 0b11111111111111111110000000000000, 157 | 0b00000000000111110000000000000000, 158 | 0b00000000000111110000000000000000, 159 | 0b00000000000111110000000000000000, 160 | 0b00000000000111110000000000000000, 161 | 0b00000000000000000000000000000000, 162 | 0b00000000000000000000000000000000 163 | }, 164 | { // 5 165 | 0b11111111111111111110100000000000, 166 | 0b11111111111111111110000000000000, 167 | 0b11111111111111111110000000000000, 168 | 0b11111111111111111110000000000000, 169 | 0b11110000000000000000000000000000, 170 | 0b11110000000000000000000000000000, 171 | 0b11110000000000000000000000000000, 172 | 0b11110011111110000000000000000000, 173 | 174 | 0b11111111111111110000000000000000, 175 | 0b11111111111111111000000000000000, 176 | 0b11111111111111111100000000000000, 177 | 0b11111110000011111100000000000000, 178 | 0b00000000000001111110000000000000, 179 | 0b00000000000000111110000000000000, 180 | 0b00000000000000111110000000000000, 181 | 0b11111000000000111110000000000000, 182 | 183 | 0b11111000000001111110000000000000, 184 | 0b11111100000111111110000000000000, 185 | 0b01111111111111111100000000000000, 186 | 0b00111111111111111000000000000000, 187 | 0b00001111111111110000000000000000, 188 | 0b00000001111110000000100000000000, 189 | 0b00000000000000000000000000000000, 190 | 0b00000000000000000000000000000000 191 | }, 192 | { // 6 193 | 0b00000011111111100000100000000000, 194 | 0b00011111111111111000000000000000, 195 | 0b00111111111111111100000000000000, 196 | 0b01111111111111111100000000000000, 197 | 0b01111110000001111100000000000000, 198 | 0b11111100000000000000000000000000, 199 | 0b11111000000000000000000000000000, 200 | 0b11111000000000000000000000000000, 201 | 202 | 0b11111011111110000000000000000000, 203 | 0b11111111111111110000000000000000, 204 | 0b11111111111111111000000000000000, 205 | 0b11111111111111111100000000000000, 206 | 0b11111110000111111100000000000000, 207 | 0b11111100000001111110000000000000, 208 | 0b11111000000000111110000000000000, 209 | 0b11111000000000111110000000000000, 210 | 211 | 0b11111100000001111110000000000000, 212 | 0b11111110000011111110000000000000, 213 | 0b01111111111111111100000000000000, 214 | 0b00111111111111111000000000000000, 215 | 0b00001111111111110000000000000000, 216 | 0b00000001111110000000100000000000, 217 | 0b00000000000000000000000000000000, 218 | 0b00000000000000000000000000000000 219 | }, 220 | { // 7 221 | 0b11111111111111111110100000000000, 222 | 0b11111111111111111110000000000000, 223 | 0b11111111111111111110000000000000, 224 | 0b11111111111111111110000000000000, 225 | 0b00000000000001111110000000000000, 226 | 0b00000000000011111100000000000000, 227 | 0b00000000000111111000000000000000, 228 | 0b00000000001111110000000000000000, 229 | 230 | 0b00000000011111100000000000000000, 231 | 0b00000000011111000000000000000000, 232 | 0b00000000111111000000000000000000, 233 | 0b00000000111110000000000000000000, 234 | 0b00000001111110000000000000000000, 235 | 0b00000001111100000000000000000000, 236 | 0b00000001111100000000000000000000, 237 | 0b00000011111100000000000000000000, 238 | 239 | 0b00000011111000000000000000000000, 240 | 0b00000011111000000000000000000000, 241 | 0b00000011111000000000000000000000, 242 | 0b00000011111000000000000000000000, 243 | 0b00000011111000000000000000000000, 244 | 0b00000011111000000000000000000000, 245 | 0b00000000000000000000000000000000, 246 | 0b00000000000000000000000000000000 247 | }, 248 | { // 8 249 | 0b00000011111110000000100000000000, 250 | 0b00001111111111100000000000000000, 251 | 0b00111111111111111000000000000000, 252 | 0b01111111111111111100000000000000, 253 | 0b01111110000011111100000000000000, 254 | 0b11111100000001111110000000000000, 255 | 0b11111000000000111110000000000000, 256 | 0b01111100000001111100000000000000, 257 | 258 | 0b01111110000011111100000000000000, 259 | 0b00111111111111111000000000000000, 260 | 0b00011111111111110000000000000000, 261 | 0b00011111111111110000000000000000, 262 | 0b00111111111111111000000000000000, 263 | 0b01111110000011111100000000000000, 264 | 0b11111100000001111110000000000000, 265 | 0b11111000000000111110000000000000, 266 | 267 | 0b11111000000000111110000000000000, 268 | 0b11111100000001111110000000000000, 269 | 0b01111111111111111100000000000000, 270 | 0b00111111111111111000000000000000, 271 | 0b00011111111111110000000000000000, 272 | 0b00000111111111000000100000000000, 273 | 0b00000000000000000000000000000000, 274 | 0b00000000000000000000000000000000 275 | }, 276 | { // 9 277 | 0b00000011111110000000100000000000, 278 | 0b00001111111111100000000000000000, 279 | 0b00111111111111111000000000000000, 280 | 0b01111111111111111100000000000000, 281 | 0b01111110000011111100000000000000, 282 | 0b11111100000001111110000000000000, 283 | 0b11111000000000111110000000000000, 284 | 0b11111000000000111110000000000000, 285 | 286 | 0b11111100000000111110000000000000, 287 | 0b11111110000001111110000000000000, 288 | 0b01111111111111111110000000000000, 289 | 0b00111111111111111110000000000000, 290 | 0b00001111111111111110000000000000, 291 | 0b00000011111111111110000000000000, 292 | 0b00000000000000111110000000000000, 293 | 0b00000000000000111110000000000000, 294 | 295 | 0b11111000000001111110000000000000, 296 | 0b11111100000011111100000000000000, 297 | 0b11111111111111111100000000000000, 298 | 0b01111111111111111000000000000000, 299 | 0b00111111111111110000000000000000, 300 | 0b00001111111111000000100000000000, 301 | 0b00000000000000000000000000000000, 302 | 0b00000000000000000000000000000000 303 | }, 304 | { // . (period) = \001 305 | 0b00000000000000000000100000000000, 306 | 0b00000000000000000000000000000000, 307 | 0b00000000000000000000000000000000, 308 | 0b00000000000000000000000000000000, 309 | 0b00000000000000000000000000000000, 310 | 0b00000000000000000000000000000000, 311 | 0b00000000000000000000000000000000, 312 | 0b00000000000000000000000000000000, 313 | 314 | 0b00000000000000000000000000000000, 315 | 0b00000000000000000000000000000000, 316 | 0b00000000000000000000000000000000, 317 | 0b00000000000000000000000000000000, 318 | 0b00000000000000000000000000000000, 319 | 0b00000000000000000000000000000000, 320 | 0b00000000000000000000000000000000, 321 | 0b00000000000000000000000000000000, 322 | 323 | 0b00000000000000000000000000000000, 324 | 0b00000000000000000000000000000000, 325 | 0b00000001110000000000000000000000, 326 | 0b00000011111000000000000000000000, 327 | 0b00000011111000000000000000000000, 328 | 0b00000001110000000000100000000000, 329 | 0b00000000000000000000000000000000, 330 | 0b00000000000000000000000000000000 331 | }, 332 | { // - (minus) = \002 333 | 0b00000000000000000000100000000000, 334 | 0b00000000000000000000000000000000, 335 | 0b00000000000000000000000000000000, 336 | 0b00000000000000000000000000000000, 337 | 0b00000000000000000000000000000000, 338 | 0b00000000000000000000000000000000, 339 | 0b00000000000000000000000000000000, 340 | 0b00000000000000000000000000000000, 341 | 342 | 0b00000000000000000000000000000000, 343 | 0b00000000000000000000000000000000, 344 | 0b00111111111111111100000000000000, 345 | 0b00111111111111111100000000000000, 346 | 0b00111111111111111100000000000000, 347 | 0b00111111111111111100000000000000, 348 | 0b00000000000000000000000000000000, 349 | 0b00000000000000000000000000000000, 350 | 351 | 0b00000000000000000000000000000000, 352 | 0b00000000000000000000000000000000, 353 | 0b00000000000000000000000000000000, 354 | 0b00000000000000000000000000000000, 355 | 0b00000000000000000000000000000000, 356 | 0b00000000000000000000100000000000, 357 | 0b00000000000000000000000000000000, 358 | 0b00000000000000000000000000000000 359 | }, 360 | { // infinity = \003 361 | 0b00000000000000000000100000000000, 362 | 0b00000000000000000000000000000000, 363 | 0b00000000000000000000000000000000, 364 | 0b00000000000000000000000000000000, 365 | 0b00000000000000000000000000000000, 366 | 0b00000111100011110000000000000000, 367 | 0b00001111110111111000000000000000, 368 | 0b00011111110111111100000000000000, 369 | 370 | 0b00111000111100011100000000000000, 371 | 0b01111000111000011110000000000000, 372 | 0b01110000011000001110000000000000, 373 | 0b01110000011000001110000000000000, 374 | 0b01110000011000001110000000000000, 375 | 0b01110000011000001110000000000000, 376 | 0b01111000011100011110000000000000, 377 | 0b00111000111100011100000000000000, 378 | 379 | 0b00111111101111111100000000000000, 380 | 0b00011111101111111000000000000000, 381 | 0b00001111000111100000000000000000, 382 | 0b00000000000000000000000000000000, 383 | 0b00000000000000000000000000000000, 384 | 0b00000000000000000000100000000000, 385 | 0b00000000000000000000000000000000, 386 | 0b00000000000000000000000000000000 387 | }, 388 | { // dB = \004 389 | 0b00000000000000000000000000000000, 390 | 0b00000000000000000000000000000000, 391 | 0b00000000000000000000000000000000, 392 | 0b00000000000000000000000000000000, 393 | 0b00000000000000000000000000000000, 394 | 0b00000000000000000000000000000000, 395 | 0b00000000000000000000000000000000, 396 | 0b00000011101111110000000000000000, 397 | 398 | 0b00000011101111111000000000000000, 399 | 0b00000011101111111100000000000000, 400 | 0b00000011101110011110000000000000, 401 | 0b00000011101110001110000000000000, 402 | 0b00111111101110011110000000000000, 403 | 0b01111111101111111110000000000000, 404 | 0b11111111101111111000000000000000, 405 | 0b11110011101111111100000000000000, 406 | 407 | 0b11100011101110011110000000000000, 408 | 0b11100011101110001110000000000000, 409 | 0b11110011101110011110000000000000, 410 | 0b01111111101111111110000000000000, 411 | 0b01111111101111111100000000000000, 412 | 0b00111101101111110000100000000000, 413 | 0b00000000000000000000000000000000, 414 | 0b00000000000000000000000000000000 415 | }, 416 | { // speaker = \005 417 | 0b00000000000000000000000000000000, 418 | 0b00000000000000111000000000000000, 419 | 0b00000000000001111000000000000000, 420 | 0b00000000000011011000000000000000, 421 | 0b00000000000110011000000000000000, 422 | 0b00000000001100011000000000000000, 423 | 0b00011111111000011000000000000000, 424 | 0b00011111110000011000000000000000, 425 | 426 | 0b00011000110000011000000000000000, 427 | 0b00011000110000011000000000000000, 428 | 0b00011000110000011000000000000000, 429 | 0b00011000110000011000000000000000, 430 | 0b00011000110000011000000000000000, 431 | 0b00011000110000011000000000000000, 432 | 0b00011111110000011000000000000000, 433 | 0b00011111111000011000000000000000, 434 | 435 | 0b00000000001100011000000000000000, 436 | 0b00000000000110011000000000000000, 437 | 0b00000000000011011000000000000000, 438 | 0b00000000000001111000000000000000, 439 | 0b00000000000000111000000000000000, 440 | 0b00000000000000000000100000000000, 441 | 0b00000000000000000000000000000000, 442 | 0b00000000000000000000000000000000 443 | }, 444 | { // antenna = \006 445 | 0b00000000000000000000000000000000, 446 | 0b00000000000000000000000000000000, 447 | 0b00000000000000000000000000000000, 448 | 0b00000000000000000000000000000000, 449 | 0b00000000000000000000000000000000, 450 | 0b00000000000000000000000000000000, 451 | 0b00111111111111111100000000000000, 452 | 0b00111111111111111100000000000000, 453 | 454 | 0b00110000011000001100000000000000, 455 | 0b00011000011000011000000000000000, 456 | 0b00001100011000110000000000000000, 457 | 0b00000110011001100000000000000000, 458 | 0b00000011011011000000000000000000, 459 | 0b00000001111110000000000000000000, 460 | 0b00000000111100000000000000000000, 461 | 0b00000000011000000000000000000000, 462 | 463 | 0b00000000011000000000000000000000, 464 | 0b00000000011000000000000000000000, 465 | 0b00000000011000000000000000000000, 466 | 0b00000000011000000000000000000000, 467 | 0b00000000011000000000000000000000, 468 | 0b00000000011000000000100000000000, 469 | 0b00000000000000000000000000000000, 470 | 0b00000000000000000000000000000000 471 | }, 472 | 473 | }; 474 | 475 | -------------------------------------------------------------------------------- /DisplayM0APP/src/numfont32x24.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | 21 | #include 22 | 23 | const uint32_t numfont32x24[][24] = { 24 | { // 0 25 | 0b00000000001111111111000000000000, 26 | 0b00000001111111111111111000000000, 27 | 0b00000111111111111111111110000000, 28 | 0b00011111111111111111111111100000, 29 | 0b00111111111000000001111111110000, 30 | 0b01111111100000000000011111111000, 31 | 0b01111111000000000000001111111000, 32 | 0b11111111000000000000001111111100, 33 | 34 | 0b11111110000000000000000111111100, 35 | 0b11111110000000000000000111111100, 36 | 0b11111110000000000000000111111100, 37 | 0b11111110000000000000000111111100, 38 | 0b11111110000000000000000111111100, 39 | 0b11111110000000000000000111111100, 40 | 0b11111111000000000000001111111100, 41 | 0b01111111000000000000001111111000, 42 | 43 | 0b01111111100000000000011111111000, 44 | 0b00111111111000000001111111110000, 45 | 0b00011111111111111111111111100000, 46 | 0b00000111111111111111111110000000, 47 | 0b00000001111111111111111000000000, 48 | 0b00000000001111111111000000000000, 49 | 0b00000000000000000000000000000000, 50 | 0b00000000000000000000000000000000 51 | }, 52 | { // 1 53 | 0b00000000000001111111000000000000, 54 | 0b00000000000011111111000000000000, 55 | 0b00000000000011111111000000000000, 56 | 0b00000000001111111111000000000000, 57 | 0b00000000011111111111000000000000, 58 | 0b00000001111111111111000000000000, 59 | 0b00000111111111111111000000000000, 60 | 0b00000111111111111111000000000000, 61 | 62 | 0b00000111111111111111000000000000, 63 | 0b00000111111011111111000000000000, 64 | 0b00000000000011111111000000000000, 65 | 0b00000000000011111111000000000000, 66 | 0b00000000000011111111000000000000, 67 | 0b00000000000011111111000000000000, 68 | 0b00000000000011111111000000000000, 69 | 0b00000000000011111111000000000000, 70 | 71 | 0b00000000000011111111000000000000, 72 | 0b00000000000011111111000000000000, 73 | 0b00000000000011111111000000000000, 74 | 0b00000000000011111111000000000000, 75 | 0b00000000000011111111000000000000, 76 | 0b00000000000011111111000000000000, 77 | 0b00000000000000000000000000000000, 78 | 0b00000000000000000000000000000000 79 | }, 80 | { // 2 81 | 0b00000000001111111111000000000000, 82 | 0b00000001111111111111111000000000, 83 | 0b00000111111111111111111110000000, 84 | 0b00011111111111111111111111100000, 85 | 0b00111111111000000001111111110000, 86 | 0b01111111100000000000011111111000, 87 | 0b11111111000000000000011111111000, 88 | 0b11111111000000000000111111111000, 89 | 90 | 0b00000000000000000011111111110000, 91 | 0b00000000000000011111111111000000, 92 | 0b00000000000011111111111100000000, 93 | 0b00000000111111111111100000000000, 94 | 0b00000011111111111100000000000000, 95 | 0b00001111111111100000000000000000, 96 | 0b00111111111100000000000000000000, 97 | 0b01111111110000000000000000000000, 98 | 99 | 0b11111111100000000000000000000000, 100 | 0b11111111000000000000000000000000, 101 | 0b11111111111111111111111111111100, 102 | 0b11111111111111111111111111111100, 103 | 0b11111111111111111111111111111100, 104 | 0b11111111111111111111111111111100, 105 | 0b00000000000000000000000000000000, 106 | 0b00000000000000000000000000000000 107 | }, 108 | { // 3 109 | 0b00000000001111111111000000000000, 110 | 0b00000001111111111111111000000000, 111 | 0b00000111111111111111111110000000, 112 | 0b00011111111111111111111111100000, 113 | 0b00111111111000000001111111110000, 114 | 0b01111111100000000000011111111000, 115 | 0b11111111000000000000001111111000, 116 | 0b11111111000000000000001111111000, 117 | 118 | 0b00000000000000000000111111110000, 119 | 0b00000000000000111111111111000000, 120 | 0b00000000000000111111111100000000, 121 | 0b00000000000000111111111100000000, 122 | 0b00000000000000111111111111000000, 123 | 0b00000000000000000000111111110000, 124 | 0b11111111000000000000001111111000, 125 | 0b11111111000000000000001111111000, 126 | 127 | 0b01111111100000000000011111111000, 128 | 0b00111111111000000001111111110000, 129 | 0b00011111111111111111111111100000, 130 | 0b00000111111111111111111110000000, 131 | 0b00000001111111111111111000000000, 132 | 0b00000000001111111111000000000000, 133 | 0b00000000000000000000000000000000, 134 | 0b00000000000000000000000000000000 135 | }, 136 | { // 4 137 | 0b00000000000000000011111110000000, 138 | 0b00000000000000000111111110000000, 139 | 0b00000000000000011111111110000000, 140 | 0b00000000000000111111111110000000, 141 | 0b00000000000011111111111110000000, 142 | 0b00000000000111111111111110000000, 143 | 0b00000000011111111001111110000000, 144 | 0b00000000111111110001111110000000, 145 | 146 | 0b00000011111111000001111110000000, 147 | 0b00000111111110000001111110000000, 148 | 0b00011111111000000001111110000000, 149 | 0b00111111110000000001111110000000, 150 | 0b11111111000000000001111110000000, 151 | 0b11111110000000000001111110000000, 152 | 0b11111111111111111111111111111000, 153 | 0b11111111111111111111111111111000, 154 | 155 | 0b11111111111111111111111111111000, 156 | 0b11111111111111111111111111111000, 157 | 0b00000000000000000001111110000000, 158 | 0b00000000000000000001111110000000, 159 | 0b00000000000000000001111110000000, 160 | 0b00000000000000000001111110000000, 161 | 0b00000000000000000000000000000000, 162 | 0b00000000000000000000000000000000 163 | }, 164 | { // 5 165 | 0b11111111111111111111111111111000, 166 | 0b11111111111111111111111111111000, 167 | 0b11111111111111111111111111111000, 168 | 0b11111111111111111111111111111000, 169 | 0b11111110000000000000000000000000, 170 | 0b11111110000000000000000000000000, 171 | 0b11111110000000000000000000000000, 172 | 0b11111110011111111111000000000000, 173 | 174 | 0b11111111111111111111111100000000, 175 | 0b11111111111111111111111111000000, 176 | 0b11111111111111111111111111100000, 177 | 0b11111111100000000011111111110000, 178 | 0b00000000000000000000111111111000, 179 | 0b00000000000000000000011111111000, 180 | 0b00000000000000000000001111111000, 181 | 0b11111111000000000000001111111000, 182 | 183 | 0b01111111100000000000011111111000, 184 | 0b00111111111000000001111111110000, 185 | 0b00011111111111111111111111100000, 186 | 0b00000111111111111111111110000000, 187 | 0b00000001111111111111111000000000, 188 | 0b00000000001111111111000000000000, 189 | 0b00000000000000000000000000000000, 190 | 0b00000000000000000000000000000000 191 | }, 192 | { // 6 193 | 0b00000000001111111111000000000000, 194 | 0b00000001111111111111111000000000, 195 | 0b00001111111111111111111110000000, 196 | 0b00111111111111111111111111100000, 197 | 0b01111111111000000001111111110000, 198 | 0b11111111100000000000000000000000, 199 | 0b11111111000000000000000000000000, 200 | 0b11111110000000000000000000000000, 201 | 202 | 0b11111110011111111111110000000000, 203 | 0b11111111111111111111111110000000, 204 | 0b11111111111111111111111111100000, 205 | 0b11111111111111111111111111110000, 206 | 0b11111111110000000001111111111000, 207 | 0b11111111000000000000011111111000, 208 | 0b11111111000000000000001111111000, 209 | 0b11111111000000000000001111111000, 210 | 211 | 0b01111111100000000000011111111000, 212 | 0b00111111111000000001111111110000, 213 | 0b00011111111111111111111111100000, 214 | 0b00000111111111111111111110000000, 215 | 0b00000001111111111111111000000000, 216 | 0b00000000001111111111000000000000, 217 | 0b00000000000000000000000000000000, 218 | 0b00000000000000000000000000000000 219 | }, 220 | { // 7 221 | 0b11111111111111111111111111111100, 222 | 0b11111111111111111111111111111100, 223 | 0b11111111111111111111111111111100, 224 | 0b11111111111111111111111111111100, 225 | 0b00000000000000000000011111111100, 226 | 0b00000000000000000001111111111100, 227 | 0b00000000000000000111111111100000, 228 | 0b00000000000000011111111110000000, 229 | 230 | 0b00000000000000111111111000000000, 231 | 0b00000000000001111111100000000000, 232 | 0b00000000000011111111000000000000, 233 | 0b00000000000111111110000000000000, 234 | 0b00000000000111111110000000000000, 235 | 0b00000000001111111100000000000000, 236 | 0b00000000001111111100000000000000, 237 | 0b00000000001111111100000000000000, 238 | 239 | 0b00000000011111111000000000000000, 240 | 0b00000000011111111000000000000000, 241 | 0b00000000011111111000000000000000, 242 | 0b00000000011111111000000000000000, 243 | 0b00000000011111111000000000000000, 244 | 0b00000000011111111000000000000000, 245 | 0b00000000000000000000000000000000, 246 | 0b00000000000000000000000000000000 247 | }, 248 | { // 8 249 | 0b00000000001111111111000000000000, 250 | 0b00000001111111111111111000000000, 251 | 0b00000111111111111111111110000000, 252 | 0b00011111111111111111111111100000, 253 | 0b00111111111000000001111111110000, 254 | 0b01111111100000000000011111111000, 255 | 0b01111111000000000000001111111000, 256 | 0b01111111100000000000011111111000, 257 | 258 | 0b00111111111000000001111111110000, 259 | 0b00011111111111111111111111100000, 260 | 0b00000111111111111111111110000000, 261 | 0b00000111111111111111111110000000, 262 | 0b00011111111111111111111111100000, 263 | 0b01111111111000000001111111111000, 264 | 0b11111111100000000000011111111100, 265 | 0b11111111000000000000001111111100, 266 | 267 | 0b11111111100000000000011111111100, 268 | 0b11111111111000000001111111111100, 269 | 0b01111111111111111111111111111000, 270 | 0b00111111111111111111111111110000, 271 | 0b00001111111111111111111111000000, 272 | 0b00000001111111111111111000000000, 273 | 0b00000000000000000000000000000000, 274 | 0b00000000000000000000000000000000 275 | }, 276 | { // 9 277 | 0b00000000011111111111110000000000, 278 | 0b00000011111111111111111110000000, 279 | 0b00001111111111111111111111100000, 280 | 0b00111111111111111111111111110000, 281 | 0b01111111111000000001111111111000, 282 | 0b01111111100000000000011111111000, 283 | 0b11111111000000000000001111111100, 284 | 0b11111111000000000000001111111100, 285 | 286 | 0b11111111100000000000011111111100, 287 | 0b11111111111000000001111111111100, 288 | 0b01111111111111111111111111111100, 289 | 0b00111111111111111111111111111100, 290 | 0b00001111111111111111111111111100, 291 | 0b00000000111111111111111111111100, 292 | 0b00000000000000000000000111111100, 293 | 0b00000000000000000000001111111000, 294 | 295 | 0b01111111100000000000011111111000, 296 | 0b00111111111000000001111111110000, 297 | 0b00011111111111111111111111100000, 298 | 0b00000111111111111111111110000000, 299 | 0b00000001111111111111111000000000, 300 | 0b00000000001111111111000000000000, 301 | 0b00000000000000000000000000000000, 302 | 0b00000000000000000000000000000000 303 | }, 304 | { // Hz = \001 305 | 0b00000000000000000000000000000000, 306 | 0b00000000000000000000000000000000, 307 | 0b00000000000000000000000000000000, 308 | 0b00000000000000000000000000000000, 309 | 0b00000000000000000000000000000000, 310 | 0b00000000000000000000000000000000, 311 | 0b00000000000000000000000000000000, 312 | 0b11111000000111110000000000000000, 313 | 314 | 0b11111000000111110000000000000000, 315 | 0b11111000000111110111111111111110, 316 | 0b11111000000111110111111111111110, 317 | 0b11111000000111110111111111111110, 318 | 0b11111000000111110000000011111100, 319 | 0b11111111111111110000000111111000, 320 | 0b11111111111111110000001111110000, 321 | 0b11111111111111110000011111100000, 322 | 323 | 0b11111000000111110000111111000000, 324 | 0b11111000000111110001111110000000, 325 | 0b11111000000111110011111100000000, 326 | 0b11111000000111110111111111111110, 327 | 0b11111000000111110111111111111110, 328 | 0b11111000000111110111111111111110, 329 | 0b00000000000000000000000000000000, 330 | 0b00000000000000000000000000000000 331 | }, 332 | }; 333 | 334 | -------------------------------------------------------------------------------- /FMReceiverMC/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | FMReceiverMC 4 | 5 | 6 | CMSIS_LPC43xx_DriverLib 7 | DisplayM0APP 8 | 9 | 10 | 11 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 12 | clean,full,incremental, 13 | 14 | 15 | 16 | 17 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 18 | full,incremental, 19 | 20 | 21 | 22 | 23 | 24 | org.eclipse.cdt.core.cnature 25 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 26 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 27 | 28 | 29 | -------------------------------------------------------------------------------- /FMReceiverMC/FMReceiver.ld: -------------------------------------------------------------------------------- 1 | /* from FMReceiver_Release_Flash2RAM_lib.ld */ 2 | 3 | GROUP( 4 | libcr_semihost.a 5 | libcr_c.a 6 | libcr_eabihelpers.a 7 | ) 8 | 9 | 10 | /* from FMReceiver_Release_Flash2RAM_mem.ld */ 11 | 12 | MEMORY 13 | { 14 | /* Define each memory region */ 15 | Flash_1MB (rx) : ORIGIN = 0x14000000, LENGTH = 0x100000 /* 1M bytes */ 16 | RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes */ 17 | RAMLoc128B (rwx) : ORIGIN = 0x10010000, LENGTH = 0x10000 /* 64K bytes */ 18 | RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */ 19 | 20 | 21 | } 22 | /* Define a symbol for the top of each memory region */ 23 | __top_Flash_1MB = 0x14000000 + 0x100000; 24 | __top_RamLoc128 = 0x10000000 + 0x10000; 25 | __top_RAMLoc128B = 0x10010000 + 0x10000; 26 | __top_RamLoc72 = 0x10080000 + 0x12000; 27 | 28 | /* from FMReceiver_Release_Flash2RAM.ld */ 29 | 30 | ENTRY(ResetISR) 31 | 32 | SECTIONS 33 | { 34 | 35 | /* MAIN TEXT SECTION */ 36 | .text : ALIGN(4) 37 | { 38 | FILL(0xff) 39 | __vectors_start__ = ABSOLUTE(.) ; 40 | KEEP(*(.isr_vector)) 41 | 42 | /* Global Section Table */ 43 | . = ALIGN(4) ; 44 | __section_table_start = .; 45 | __data_section_table = .; 46 | LONG(LOADADDR(.text_RAM)); 47 | LONG( ADDR(.text_RAM)); 48 | LONG( SIZEOF(.text_RAM)); 49 | LONG(LOADADDR(.text_RAM2)); 50 | LONG( ADDR(.text_RAM2)); 51 | LONG( SIZEOF(.text_RAM2)); 52 | LONG(LOADADDR(.data)); 53 | LONG( ADDR(.data)); 54 | LONG( SIZEOF(.data)); 55 | LONG(LOADADDR(.data_RAM2)); 56 | LONG( ADDR(.data_RAM2)); 57 | LONG( SIZEOF(.data_RAM2)); 58 | __data_section_table_end = .; 59 | __bss_section_table = .; 60 | LONG( ADDR(.bss)); 61 | LONG( SIZEOF(.bss)); 62 | LONG( ADDR(.bss_RAM2)); 63 | LONG( SIZEOF(.bss_RAM2)); 64 | __bss_section_table_end = .; 65 | __section_table_end = . ; 66 | /* End of Global Section Table */ 67 | 68 | *(.after_vectors*) 69 | 70 | } >Flash_1MB 71 | 72 | .text_RAM : ALIGN(4) 73 | { 74 | . = ALIGN(4); 75 | *(.text*) 76 | *(.rodata .rodata.* .constdata .constdata.*) 77 | 78 | } > RamLoc128 AT>Flash_1MB 79 | 80 | .text_RAM2 : ALIGN(4) 81 | { 82 | FILL(0xff) 83 | __core_m0app_START__ = .; 84 | KEEP(*(.core_m0app)) 85 | __core_m0app_END__ = .; 86 | ASSERT(!(__core_m0app_START__ == __core_m0app_END__), "No slave code for _core_m0app"); 87 | ASSERT( (ABSOLUTE(__core_m0app_START__) == __vectors_start___core_m0app), "M0APP execute address differs from address provided in source image"); 88 | } > RAMLoc128B AT>Flash_1MB 89 | 90 | /* 91 | * for exception handling/unwind - some Newlib functions (in common 92 | * with C++ and STDC++) use this. 93 | */ 94 | .ARM.extab : ALIGN(4) 95 | { 96 | *(.ARM.extab* .gnu.linkonce.armextab.*) 97 | } > Flash_1MB 98 | __exidx_start = .; 99 | 100 | .ARM.exidx : ALIGN(4) 101 | { 102 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 103 | } > Flash_1MB 104 | __exidx_end = .; 105 | 106 | _etext = .; 107 | 108 | 109 | /* DATA section for RamLoc72 */ 110 | .data_RAM2 : ALIGN(4) 111 | { 112 | FILL(0xff) 113 | *(.ramfunc.$RAM2) 114 | *(.ramfunc.$RamLoc72) 115 | *(.data.$RAM2*) 116 | *(.data.$RamLoc72*) 117 | . = ALIGN(4) ; 118 | } > RamLoc72 AT>Flash_1MB 119 | 120 | /* MAIN DATA SECTION */ 121 | 122 | 123 | .uninit_RESERVED : ALIGN(4) 124 | { 125 | KEEP(*(.bss.$RESERVED*)) 126 | . = ALIGN(4) ; 127 | _end_uninit_RESERVED = .; 128 | } > RamLoc128 129 | 130 | 131 | /* Main DATA section (RamLoc128) */ 132 | .data : ALIGN(4) 133 | { 134 | FILL(0xff) 135 | _data = . ; 136 | *(vtable) 137 | *(.ramfunc*) 138 | *(.data*) 139 | . = ALIGN(4) ; 140 | _edata = . ; 141 | } > RamLoc128 AT>Flash_1MB 142 | 143 | /* BSS section for RamLoc72 */ 144 | .bss_RAM2 : ALIGN(4) 145 | { 146 | *(.bss.$RAM2*) 147 | *(.bss.$RamLoc72*) 148 | . = ALIGN(4) ; 149 | } > RamLoc72 150 | 151 | /* MAIN BSS SECTION */ 152 | .bss : ALIGN(4) 153 | { 154 | _bss = .; 155 | *(.bss*) 156 | *(COMMON) 157 | . = ALIGN(4) ; 158 | _ebss = .; 159 | PROVIDE(end = .); 160 | } > RamLoc128 161 | 162 | /* NOINIT section for RamLoc72 */ 163 | .noinit_RAM2 (NOLOAD) : ALIGN(4) 164 | { 165 | *(.noinit.$RAM2*) 166 | *(.noinit.$RamLoc72*) 167 | . = ALIGN(4) ; 168 | } > RamLoc72 169 | 170 | /* DEFAULT NOINIT SECTION */ 171 | .noinit (NOLOAD): ALIGN(4) 172 | { 173 | _noinit = .; 174 | *(.noinit*) 175 | . = ALIGN(4) ; 176 | _end_noinit = .; 177 | } > RamLoc128 178 | 179 | PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); 180 | PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0); 181 | } 182 | -------------------------------------------------------------------------------- /FMReceiverMC/FMReceiver_Flash.ld: -------------------------------------------------------------------------------- 1 | /* from FMReceiver_Release_Flash2RAM_lib.ld */ 2 | 3 | GROUP( 4 | libcr_semihost.a 5 | libcr_c.a 6 | libcr_eabihelpers.a 7 | ) 8 | 9 | 10 | /* from FMReceiver_Release_Flash2RAM_mem.ld */ 11 | 12 | MEMORY 13 | { 14 | /* Define each memory region */ 15 | Flash_1MB (rx) : ORIGIN = 0x14000000, LENGTH = 0x0F0000 /* 1M-64k bytes */ 16 | FlashB (rx) : ORIGIN = 0x140F0000, LENGTH = 0x10000 /* 64k bytes for M0APP */ 17 | RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes */ 18 | RAMLoc128B (rwx) : ORIGIN = 0x10010000, LENGTH = 0x10000 /* 64K bytes */ 19 | RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */ 20 | } 21 | /* Define a symbol for the top of each memory region */ 22 | __top_Flash_1MB = 0x14000000 + 0x100000; 23 | __top_RamLoc128 = 0x10000000 + 0x10000; 24 | __top_RAMLoc128B = 0x10010000 + 0x10000; 25 | __top_RamLoc72 = 0x10080000 + 0x12000; 26 | 27 | /* from FMReceiver_Release_Flash2RAM.ld */ 28 | 29 | ENTRY(ResetISR) 30 | 31 | SECTIONS 32 | { 33 | 34 | /* MAIN TEXT SECTION */ 35 | .text : ALIGN(4) 36 | { 37 | FILL(0xff) 38 | __vectors_start__ = ABSOLUTE(.) ; 39 | KEEP(*(.isr_vector)) 40 | 41 | /* Global Section Table */ 42 | . = ALIGN(4) ; 43 | __section_table_start = .; 44 | __data_section_table = .; 45 | LONG(LOADADDR(.text_RAM)); 46 | LONG( ADDR(.text_RAM)); 47 | LONG( SIZEOF(.text_RAM)); 48 | LONG(LOADADDR(.text_RAM2)); 49 | LONG( ADDR(.text_RAM2)); 50 | LONG( SIZEOF(.text_RAM2)); 51 | LONG(LOADADDR(.data)); 52 | LONG( ADDR(.data)); 53 | LONG( SIZEOF(.data)); 54 | LONG(LOADADDR(.data_RAM2)); 55 | LONG( ADDR(.data_RAM2)); 56 | LONG( SIZEOF(.data_RAM2)); 57 | __data_section_table_end = .; 58 | __bss_section_table = .; 59 | LONG( ADDR(.bss)); 60 | LONG( SIZEOF(.bss)); 61 | LONG( ADDR(.bss_RAM2)); 62 | LONG( SIZEOF(.bss_RAM2)); 63 | __bss_section_table_end = .; 64 | __section_table_end = . ; 65 | /* End of Global Section Table */ 66 | 67 | *(.after_vectors*) 68 | 69 | } >Flash_1MB 70 | 71 | .text_RAM : ALIGN(4) 72 | { 73 | . = ALIGN(4); 74 | *(.text*) 75 | *(.rodata .rodata.* .constdata .constdata.*) 76 | 77 | } > RamLoc128 AT>Flash_1MB 78 | 79 | .text_M0APP : ALIGN(4) 80 | { 81 | __core_m0app_START__ = .; 82 | KEEP(*(.core_m0app)) 83 | __core_m0app_END__ = .; 84 | ASSERT(!(__core_m0app_START__ == __core_m0app_END__), "No slave code for _core_m0app"); 85 | ASSERT( (ABSOLUTE(__core_m0app_START__) == __vectors_start___core_m0app), "M0APP execute address differs from address provided in source image"); 86 | } >FlashB 87 | 88 | /* next section should be named .data_M0APP, but error occurs */ 89 | .text_RAM2 : ALIGN(4) 90 | { 91 | FILL(0xff) 92 | KEEP(*(.core_m0app.data)) 93 | } >RAMLoc128B AT>FlashB 94 | 95 | /* 96 | * for exception handling/unwind - some Newlib functions (in common 97 | * with C++ and STDC++) use this. 98 | */ 99 | .ARM.extab : ALIGN(4) 100 | { 101 | *(.ARM.extab* .gnu.linkonce.armextab.*) 102 | } > Flash_1MB 103 | __exidx_start = .; 104 | 105 | .ARM.exidx : ALIGN(4) 106 | { 107 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 108 | } > Flash_1MB 109 | __exidx_end = .; 110 | 111 | _etext = .; 112 | 113 | 114 | /* DATA section for RamLoc72 */ 115 | .data_RAM2 : ALIGN(4) 116 | { 117 | FILL(0xff) 118 | *(.ramfunc.$RAM2) 119 | *(.ramfunc.$RamLoc72) 120 | *(.data.$RAM2*) 121 | *(.data.$RamLoc72*) 122 | . = ALIGN(4) ; 123 | } > RamLoc72 AT>Flash_1MB 124 | 125 | /* MAIN DATA SECTION */ 126 | 127 | 128 | .uninit_RESERVED : ALIGN(4) 129 | { 130 | KEEP(*(.bss.$RESERVED*)) 131 | . = ALIGN(4) ; 132 | _end_uninit_RESERVED = .; 133 | } > RamLoc128 134 | 135 | 136 | /* Main DATA section (RamLoc128) */ 137 | .data : ALIGN(4) 138 | { 139 | FILL(0xff) 140 | _data = . ; 141 | *(vtable) 142 | *(.ramfunc*) 143 | *(.data*) 144 | . = ALIGN(4) ; 145 | _edata = . ; 146 | } > RamLoc128 AT>Flash_1MB 147 | 148 | /* BSS section for RamLoc72 */ 149 | .bss_RAM2 : ALIGN(4) 150 | { 151 | *(.bss.$RAM2*) 152 | *(.bss.$RamLoc72*) 153 | . = ALIGN(4) ; 154 | } > RamLoc72 155 | 156 | /* MAIN BSS SECTION */ 157 | .bss : ALIGN(4) 158 | { 159 | _bss = .; 160 | *(.bss*) 161 | *(COMMON) 162 | . = ALIGN(4) ; 163 | _ebss = .; 164 | PROVIDE(end = .); 165 | } > RamLoc128 166 | 167 | /* NOINIT section for RamLoc72 */ 168 | .noinit_RAM2 (NOLOAD) : ALIGN(4) 169 | { 170 | *(.noinit.$RAM2*) 171 | *(.noinit.$RamLoc72*) 172 | . = ALIGN(4) ; 173 | } > RamLoc72 174 | 175 | /* DEFAULT NOINIT SECTION */ 176 | .noinit (NOLOAD): ALIGN(4) 177 | { 178 | _noinit = .; 179 | *(.noinit*) 180 | . = ALIGN(4) ; 181 | _end_noinit = .; 182 | } > RamLoc128 183 | 184 | PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .); 185 | PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0); 186 | } 187 | -------------------------------------------------------------------------------- /FMReceiverMC/include/receiver.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | 21 | #ifndef __RECEIVER_H__ 22 | #define __RECEIVER_H__ 23 | 24 | #include 25 | #include 26 | 27 | #define EXTCLK_10MHZ 0 28 | //#define I2S_SLAVE 1 29 | 30 | #define STEREO 1 31 | 32 | #if EXTCLK_10MHZ 33 | #define AUDIO_RATE 48077 34 | #else 35 | #define AUDIO_RATE 48000 36 | #endif 37 | 38 | #define IF_RATE (13 * AUDIO_RATE / 2) 39 | #define CIC_DECIMATION_RATIO 16 40 | #define FIR_DECIMATION_RATIO 2 41 | #if EXTCLK_10MHZ 42 | #define ADC_RATE 10000000 43 | #else 44 | #define ADC_RATE (CIC_DECIMATION_RATIO * FIR_DECIMATION_RATIO * IF_RATE) 45 | #endif 46 | 47 | #define CAPTUREBUFFER_SIZE 0x10000 48 | #define CAPTUREBUFFER0 ((uint8_t*)0x20000000) 49 | #define CAPTUREBUFFER1 ((uint8_t*)0x20008000) 50 | #define CAPTUREBUFFER_SIZEHALF 0x8000 51 | 52 | #define NCO_SIN_TABLE ((int16_t*)0x1008F000) 53 | #define NCO_COS_TABLE ((int16_t*)0x1008F800) 54 | #define NCO_TABLE_SIZE 0x800 55 | #define NCO_SAMPLES 1024 56 | //#define NCO_AMPL 32 57 | //#define NCO_AMPL 64 58 | #define NCO_AMPL (SHRT_MAX / 128) 59 | //#define NCO_AMPL (SHRT_MAX / 64) 60 | //#define NCO_AMPL (SHRT_MAX / 32) 61 | //#define NCO_AMPL (SHRT_MAX / 16) 62 | //#define NCO_AMPL (SHRT_MAX / 4) 63 | 64 | #define I_FIR_STATE ((q15_t*)0x10080000) 65 | #define I_FIR_BUFFER ((q15_t*)0x10080040) 66 | #define Q_FIR_STATE ((q15_t*)0x10081000) 67 | #define Q_FIR_BUFFER ((q15_t*)0x10081040) 68 | /* 0x10000 / 2 / 16 */ 69 | #define FIR_BUFFER_SIZE 0x800 70 | #define FIR_STATE_SIZE 0x40 71 | #define FIR_GAINBITS 5 /* 0 ~ 6 */ 72 | 73 | #define DEMOD_BUFFER ((q15_t*)0x10088000) 74 | #define DEMOD_BUFFER_SIZE 0x800 75 | //#define DEMOD_GAINBITS 6 /* 0 ~ 6 */ 76 | #define DEMOD_GAINBITS 9 /* 0 ~ 10 */ 77 | 78 | #define RESAMPLE_STATE ((q15_t*)0x10089000) 79 | #define RESAMPLE_STATE_SIZE 0x100 80 | #define RESAMPLE_BUFFER ((q15_t*)0x10089100) 81 | #define RESAMPLE_BUFFER_SIZE 0x400 82 | #define RESAMPLE_GAINBITS 1 /* 0 ~ 6 */ 83 | 84 | #define RESAMPLE2_STATE ((q15_t*)0x10089500) 85 | #define RESAMPLE2_STATE_SIZE 0x100 86 | #define RESAMPLE2_BUFFER ((q15_t*)0x10089600) 87 | #define RESAMPLE2_BUFFER_SIZE 0x400 88 | 89 | #define AUDIO_BUFFER ((q15_t*)0x1008A000) 90 | #define AUDIO_BUFFER_SIZE 0x2000 91 | #define AUDIO_TEST_BUFFER ((q15_t*)0x1008C000) 92 | 93 | typedef enum { 94 | MOD_LSB, 95 | MOD_USB, 96 | MOD_MAX 97 | } modulation_t; 98 | 99 | typedef struct { 100 | enum { FREQ, GAIN, MOD, AGCMODE, RFGAIN, SPDISP, TESTP, DEBUGMODE, CHANNEL, MODE_MAX } mode; 101 | int gain; 102 | int channel; 103 | uint32_t freq; 104 | modulation_t modulation; 105 | int digit; /* 0~5 */ 106 | enum { AGC_MANUAL, AGC_SLOW, AGC_MID, AGC_FAST } agcmode; 107 | int rfgain; 108 | float32_t ncoampl; 109 | enum { SPDISP_CAP, SPDISP_CIC, SPDISP_DEMOD, SPDISP_RESAMP, SPDISP_AUDIO, SPDISP_MODE_MAX } spdispmode; 110 | int tp; 111 | int debugmode; 112 | } uistat_t; 113 | 114 | #define UISTAT ((uistat_t*)0x10083f00) 115 | 116 | typedef struct { 117 | uint32_t sample_freq; 118 | int16_t offset; 119 | int16_t stride; 120 | int16_t overgain; 121 | 122 | int16_t origin; 123 | int16_t tickstep; 124 | int16_t tickbase; 125 | int16_t tickunit; 126 | const char *unitname; 127 | } spectrumdisplay_param_t; 128 | 129 | // when event sent with SEV from M4 core, filled following data 130 | typedef struct { 131 | q31_t *buffer; 132 | uint32_t buffer_rest; 133 | uint8_t update_flag; 134 | uint8_t ui_update_flag; 135 | spectrumdisplay_param_t p; 136 | } spectrumdisplay_info_t; 137 | 138 | #define FLAG_SPDISP (1<<0) 139 | #define FLAG_UI (1<<1) 140 | 141 | #define SPDISPINFO ((spectrumdisplay_info_t*)0x10083f80) 142 | 143 | // r:2048 c:1024 samples (8192 byte with q31_t) 144 | #define SPDISP_BUFFER_SIZE 8192 145 | #define SPDISP_BUFFER ((q31_t*)0x10084000) 146 | 147 | 148 | // dsp.c 149 | extern void DMA_IRQHandler(void); 150 | extern void nco_set_frequency(float32_t freq); 151 | extern void generate_test_tone(int freq); 152 | extern void dsp_init(); 153 | 154 | extern void update_adc_dc_offset(void); 155 | extern void audio_set_gain(int gain); 156 | 157 | #define AUDIO_GAIN_MAX 29 158 | #define AUDIO_GAIN_MIN -7 159 | #define AUDIO_GAIN_REF 7 160 | 161 | // ui.c 162 | extern void ui_init(); 163 | extern void ui_process(); 164 | 165 | // clkcfg.h 166 | extern void setup_systemclock(); 167 | extern void setup_pll0audio(uint32_t msel, uint32_t nsel, uint32_t psel); 168 | extern void setup_i2s_clock(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode); 169 | 170 | 171 | extern volatile int32_t capture_count; 172 | 173 | 174 | typedef struct { 175 | uint16_t write_current; 176 | uint16_t write_total; 177 | uint16_t read_total; 178 | uint16_t read_current; 179 | uint16_t rebuffer_count; 180 | } audio_state_t; 181 | 182 | typedef struct { 183 | uint32_t last; 184 | int32_t carrier; 185 | } fm_demod_state_t; 186 | 187 | typedef struct { 188 | #if 0 189 | float32_t carrier_i; 190 | float32_t carrier_q; 191 | float32_t step_cos; 192 | float32_t step_sin; 193 | float32_t basestep_cos; 194 | float32_t basestep_sin; 195 | float32_t delta_cos[12]; 196 | float32_t delta_sin[12]; 197 | #else 198 | uint32_t phase_accum; 199 | uint32_t phase_step; 200 | uint32_t phase_step_default; 201 | #endif 202 | int16_t corr; 203 | int16_t corr_ave; 204 | int16_t corr_std; 205 | int32_t sdi; 206 | int32_t sdq; 207 | } stereo_separate_state_t; 208 | 209 | typedef struct { 210 | q15_t *dest; 211 | int16_t *nco_base; 212 | int32_t dest_idx; 213 | int32_t s0; 214 | int32_t s1; 215 | int32_t s2; 216 | int32_t d0; 217 | int32_t d1; 218 | int32_t d2; 219 | uint32_t dc_offset; 220 | } cic_state_t; 221 | 222 | extern cic_state_t cic_i; 223 | extern cic_state_t cic_q; 224 | 225 | 226 | 227 | #define LED_INIT() (LPC_GPIO_PORT->DIR[0] |= (1UL << 8)) 228 | #define LED_ON() (LPC_GPIO_PORT->SET[0] |= (1UL << 8)) 229 | #define LED_OFF() (LPC_GPIO_PORT->CLR[0] = (1UL << 8)) 230 | #define LED_TOGGLE() (LPC_GPIO_PORT->NOT[0] = (1UL << 8)) 231 | 232 | #define ROTLED_INIT() (LPC_GPIO_PORT->DIR[1] |= (1UL << 3)|(1UL << 4)) 233 | #define ROTLED_RED() do{LPC_GPIO_PORT->SET[1] |= (1UL << 3);LPC_GPIO_PORT->CLR[1] = (1UL << 4);}while(0) 234 | #define ROTLED_GREEN() do{LPC_GPIO_PORT->SET[1] |= (1UL << 4);LPC_GPIO_PORT->CLR[1] = (1UL << 3);}while(0) 235 | #define ROTLED_OFF() (LPC_GPIO_PORT->CLR[1] = (1UL << 3)|(1UL << 4)) 236 | 237 | #define TESTPOINT_INIT() \ 238 | do {scu_pinmux(0x6, 11, PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | FILTER_ENABLE, FUNC0); \ 239 | LPC_GPIO_PORT->DIR[3] |= (1UL << 7); \ 240 | LPC_GPIO_PORT->SET[3] |= (1UL << 7); } while(0) 241 | #define TESTPOINT_ON() (LPC_GPIO_PORT->SET[3] |= (1UL << 7)) 242 | #define TESTPOINT_OFF() (LPC_GPIO_PORT->CLR[3] = (1UL << 7)) 243 | #define TESTPOINT_TOGGLE() (LPC_GPIO_PORT->NOT[3] = (1UL << 7)) 244 | #define TESTPOINT_SPIKE() TESTPOINT_TOGGLE();TESTPOINT_TOGGLE() 245 | 246 | #define DMA_HALT() (LPC_GPDMA->C0CONFIG |= (1 << 18)) 247 | #define DMA_RUN() (LPC_GPDMA->C0CONFIG &= ~(1 << 18)) 248 | 249 | #endif /* __RECEIVER_H__ */ 250 | -------------------------------------------------------------------------------- /FMReceiverMC/include/vadc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | /* 21 | * @copyright Copyright 2013 Embedded Artists AB 22 | * 23 | * Permission to use, copy, modify, and distribute this software and its 24 | * documentation is hereby granted, without fee, provided that it 25 | * is used in conjunction with NXP Semiconductors microcontrollers. This 26 | * copyright, permission, and disclaimer notice must appear in all copies of 27 | * this code. 28 | * 29 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 30 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 31 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 32 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 33 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 34 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 35 | * THE SOFTWARE. 36 | */ 37 | 38 | #ifndef __VADC_H__ 39 | #define __VADC_H__ 40 | 41 | // ------------------------------------------------------------------------------------------------ 42 | // ----- VADC ----- 43 | // ------------------------------------------------------------------------------------------------ 44 | 45 | /** 46 | * @brief Product name title=UM????? Chapter title=?????? Modification date=12/11/2012 Major revision=? Minor revision=? (VADC) 47 | 0x400F0000 48 | */ 49 | typedef struct { /*!< (@ 0x400F0000) VADC Structure */ 50 | __O uint32_t FLUSH; /*!< (@ 0x400F0000) Flushes FIFO */ 51 | __IO uint32_t DMA_REQ; /*!< (@ 0x400F0004) Set or clear DMA write request */ 52 | __I uint32_t FIFO_STS; /*!< (@ 0x400F0008) Indicates FIFO fullness status */ 53 | __IO uint32_t FIFO_CFG; /*!< (@ 0x400F000C) Configures FIFO fullness level that triggers interrupt and packing 1 or 2 samples per word. */ 54 | __O uint32_t TRIGGER; /*!< (@ 0x400F0010) Enable software trigger to start descriptor processing */ 55 | __IO uint32_t DSCR_STS; /*!< (@ 0x400F0014) Indicates active descriptor table and descriptor entry */ 56 | __IO uint32_t POWER_DOWN; /*!< (@ 0x400F0018) Set or clear power down mode */ 57 | __IO uint32_t CONFIG; /*!< (@ 0x400F001C) Configures external trigger mode, store channel ID in FIFO and wakeup recovery time from power down. */ 58 | __IO uint32_t THR_A; /*!< (@ 0x400F0020) Configures window comparator A levels. */ 59 | __IO uint32_t THR_B; /*!< (@ 0x400F0024) Configures window comparator B levels. */ 60 | __I uint32_t LAST_SAMPLE[6]; /*!< (@ 0x400F0028) Contains last converted sample of input M [M=0..5) and result of window comparator. */ 61 | __I uint32_t RESERVED0[48]; 62 | __IO uint32_t ADC_DEBUG; /*!< (@ 0x400F0100) Reserved (ADC Debug pin inputs) */ 63 | __IO uint32_t ADC_SPEED; /*!< (@ 0x400F0104) ADC speed control */ 64 | __IO uint32_t POWER_CONTROL; /*!< (@ 0x400F0108) Configures ADC power vs. speed, DC-in biasing, output format and power gating. */ 65 | __I uint32_t RESERVED1[61]; 66 | __I uint32_t FIFO_OUTPUT[16]; /*!< (@ 0x400F0200 - 0x400F023C) FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples */ 67 | __I uint32_t RESERVED2[48]; 68 | __IO uint32_t DESCRIPTOR_0[8]; /*!< (@ 0x400F0300) Table0 descriptor n, n= 0 to 7 */ 69 | __IO uint32_t DESCRIPTOR_1[8]; /*!< (@ 0x400F0320) Table1 descriptor n, n= 0 to 7 */ 70 | __I uint32_t RESERVED3[752]; 71 | __O uint32_t CLR_EN0; /*!< (@ 0x400F0F00) Interrupt0 clear mask */ 72 | __O uint32_t SET_EN0; /*!< (@ 0x400F0F04) Interrupt0 set mask */ 73 | __I uint32_t MASK0; /*!< (@ 0x400F0F08) Interrupt0 mask */ 74 | __I uint32_t STATUS0; /*!< (@ 0x400F0F0C) Interrupt0 status. Interrupt0 contains FIFO fullness, descriptor status and ADC range under/overflow */ 75 | __O uint32_t CLR_STAT0; /*!< (@ 0x400F0F10) Interrupt0 clear status */ 76 | __O uint32_t SET_STAT0; /*!< (@ 0x400F0F14) Interrupt0 set status */ 77 | __I uint32_t RESERVED4[2]; 78 | __O uint32_t CLR_EN1; /*!< (@ 0x400F0F20) Interrupt1 mask clear enable. */ 79 | __O uint32_t SET_EN1; /*!< (@ 0x400F0F24) Interrupt1 mask set enable */ 80 | __I uint32_t MASK1; /*!< (@ 0x400F0F28) Interrupt1 mask */ 81 | __I uint32_t STATUS1; /*!< (@ 0x400F0F2C) Interrupt1 status. Interrupt1 contains window comparator results and register last LAST_SAMPLE[M] overrun. */ 82 | __O uint32_t CLR_STAT1; /*!< (@ 0x400F0F30) Interrupt1 clear status */ 83 | __O uint32_t SET_STAT1; /*!< (@ 0x400F0F34) Interrupt1 set status */ 84 | } LPC_VADC_Type; 85 | 86 | #define LPC_VADC_BASE 0x400F0000 87 | #define LPC_VADC ((LPC_VADC_Type *) LPC_VADC_BASE) 88 | 89 | #define CGU_BASE_VADC CGU_BASE_ENET_CSR 90 | #define VADC_IRQn RESERVED7_IRQn 91 | 92 | #define VADC_DMA_WRITE 7 93 | #define VADC_DMA_READ 8 94 | #define VADC_DMA_READ_SRC (LPC_VADC_BASE + 512) /* VADC FIFO */ 95 | 96 | #define RGU_SIG_VADC 60 97 | 98 | 99 | #define STATUS0_FIFO_FULL_MASK (1<<0) 100 | #define STATUS0_FIFO_EMPTY_MASK (1<<1) 101 | #define STATUS0_FIFO_OVERFLOW_MASK (1<<2) 102 | #define STATUS0_DESCR_DONE_MASK (1<<3) 103 | #define STATUS0_DESCR_ERROR_MASK (1<<4) 104 | #define STATUS0_ADC_OVF_MASK (1<<5) 105 | #define STATUS0_ADC_UNF_MASK (1<<6) 106 | 107 | #define STATUS0_CLEAR_MASK 0x7f 108 | 109 | #define STATUS1_THCMP_BRANGE(__ch) ((1<<0) << (5 * (__ch))) 110 | #define STATUS1_THCMP_ARANGE(__ch) ((1<<1) << (5 * (__ch))) 111 | #define STATUS1_THCMP_DCROSS(__ch) ((1<<2) << (5 * (__ch))) 112 | #define STATUS1_THCMP_UCROSS(__ch) ((1<<3) << (5 * (__ch))) 113 | #define STATUS1_THCMP_OVERRUN(__ch) ((1<<4) << (5 * (__ch))) 114 | 115 | #define STATUS1_CLEAR_MASK 0x1fffffff 116 | 117 | #endif /* __VADC_H__ */ 118 | -------------------------------------------------------------------------------- /FMReceiverMC/src/clkcfg.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | /* 21 | * @copyright Copyright 2013 Embedded Artists AB 22 | * 23 | * Permission to use, copy, modify, and distribute this software and its 24 | * documentation is hereby granted, without fee, provided that it 25 | * is used in conjunction with NXP Semiconductors microcontrollers. This 26 | * copyright, permission, and disclaimer notice must appear in all copies of 27 | * this code. 28 | * 29 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 30 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 31 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 32 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 33 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 34 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 35 | * THE SOFTWARE. 36 | */ 37 | 38 | #include 39 | #include 40 | #include 41 | #include 42 | #include 43 | 44 | #include "receiver.h" 45 | #include "vadc.h" 46 | 47 | /*! Frequency of external xtal */ 48 | #define XTAL_FREQ (12000000UL) 49 | 50 | extern uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM]; 51 | 52 | 53 | 54 | void setup_systemclock() 55 | { 56 | /* enable the crystal oscillator */ 57 | CGU_SetXTALOSC(XTAL_FREQ); 58 | CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); 59 | 60 | /* connect the cpu to the xtal */ 61 | CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M4); 62 | 63 | /* connect the PLL to the xtal */ 64 | CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1); 65 | 66 | /* configure the PLL to 120 MHz */ 67 | CGU_SetPLL1(10); 68 | while((LPC_CGU->PLL1_STAT&1) == 0x0); 69 | 70 | /* enable the PLL */ 71 | CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE); 72 | 73 | /* connect to the CPU core */ 74 | CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4); 75 | 76 | SystemCoreClock = 120000000; 77 | 78 | /* wait one msec */ 79 | emc_WaitUS(1000); 80 | 81 | /* Change the clock to 204 MHz */ 82 | CGU_SetPLL1(17); 83 | while((LPC_CGU->PLL1_STAT&1) == 0x0); 84 | 85 | SystemCoreClock = 204000000; 86 | 87 | CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = SystemCoreClock; 88 | } 89 | 90 | #define PLL0_MSEL_MAX (1<<15) 91 | #define PLL0_NSEL_MAX (1<<8) 92 | #define PLL0_PSEL_MAX (1<<5) 93 | 94 | static uint32_t FindMDEC(uint32_t msel) 95 | { 96 | /* multiplier: compute mdec from msel */ 97 | uint32_t x = 0x4000; 98 | uint32_t im; 99 | 100 | switch (msel) 101 | { 102 | case 0: 103 | return 0xffffffff; 104 | case 1: 105 | return 0x18003; 106 | case 2: 107 | return 0x10003; 108 | default: 109 | for (im = msel; im <= PLL0_MSEL_MAX; im++) 110 | { 111 | x = (((x ^ x>>1) & 1) << 14) | (x>>1 & 0xFFFF); 112 | } 113 | return x; 114 | } 115 | } 116 | 117 | static uint32_t FindNDEC(uint32_t nsel) 118 | { 119 | /* pre-divider: compute ndec from nsel */ 120 | uint32_t x = 0x80; 121 | uint32_t in; 122 | 123 | switch (nsel) 124 | { 125 | case 0: 126 | return 0xffffffff; 127 | case 1: 128 | return 0x302; 129 | case 2: 130 | return 0x202; 131 | default: 132 | for (in = nsel; in <= PLL0_NSEL_MAX; in++) 133 | { 134 | x = (((x ^ x>>2 ^ x>>3 ^ x>>4) & 1) << 7) | (x>>1 & 0xFF); 135 | } 136 | return x; 137 | } 138 | } 139 | 140 | static uint32_t FindPDEC(uint32_t psel) 141 | { 142 | /* post-divider: compute pdec from psel */ 143 | uint32_t x = 0x10; 144 | uint32_t ip; 145 | 146 | switch (psel) 147 | { 148 | case 0: 149 | return 0xffffffff; 150 | case 1: 151 | return 0x62; 152 | case 2: 153 | return 0x42; 154 | default: 155 | for (ip = psel; ip <= PLL0_PSEL_MAX; ip++) 156 | { 157 | x = (((x ^ x>>2) & 1) << 4) | (x>>1 & 0x3F); 158 | } 159 | return x; 160 | } 161 | } 162 | 163 | void setup_pll0audio(uint32_t msel, uint32_t nsel, uint32_t psel) 164 | { 165 | uint32_t ClkSrc; 166 | 167 | //CGU_EnableEntity(CGU_BASE_PERIPH, DISABLE); 168 | CGU_EnableEntity(CGU_BASE_VADC, DISABLE); 169 | 170 | #if 0//EXTCLK_10MHZ 171 | scu_pinmux(0xF, 4, MD_PLN_FAST, FUNC1); // GP_CLKIN 172 | CGU_ClockSourceFrequency[CGU_CLKSRC_GP_CLKIN] = 10000000*4; 173 | ClkSrc = CGU_CLKSRC_GP_CLKIN; 174 | #else 175 | /* source = XTAL OSC 12 MHz */ 176 | ClkSrc = CGU_CLKSRC_XTAL_OSC; 177 | #endif 178 | 179 | /* disable clock, disable skew enable, power down pll, 180 | * (dis/en)able post divider, (dis/en)able pre-divider, 181 | * disable free running mode, disable bandsel, 182 | * enable up limmiter, disable bypass 183 | */ 184 | LPC_CGU->PLL0AUDIO_CTRL = (ClkSrc << 24) | _BIT(0); /* power down */ 185 | 186 | /* set NDEC, PDEC and MDEC register */ 187 | LPC_CGU->PLL0AUDIO_NP_DIV = (FindNDEC(nsel)<<12) | (FindPDEC(psel) << 0); 188 | LPC_CGU->PLL0AUDIO_MDIV = FindMDEC(msel); 189 | 190 | LPC_CGU->PLL0AUDIO_CTRL = (ClkSrc << 24) | (6<< 12); // fractional divider off and bypassed 191 | 192 | /* wait for lock */ 193 | while (!(LPC_CGU->PLL0AUDIO_STAT & 1)); 194 | 195 | /* enable clock output */ 196 | LPC_CGU->PLL0AUDIO_CTRL |= (1<<4); /* CLKEN */ 197 | 198 | CGU_ClockSourceFrequency[CGU_CLKSRC_PLL0_AUDIO] = 199 | msel * (CGU_ClockSourceFrequency[ClkSrc] / (psel * nsel)); 200 | 201 | //CGU_UpdateClock(); 202 | 203 | // Re-enable the clocks that uses PLL0AUDIO 204 | //CGU_EnableEntity(CGU_BASE_PERIPH, ENABLE); 205 | CGU_EnableEntity(CGU_BASE_VADC, ENABLE); 206 | } 207 | 208 | void setup_i2s_clock(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode) 209 | { 210 | #if 0 211 | /* Calculate bit rate 212 | * The formula is: 213 | * bit_rate = channel*wordwidth - 1 214 | * 48kHz sample rate for 16 bit stereo date requires 215 | * a bit rate of 48000*16*2=1536MHz (MCLK) 216 | */ 217 | uint32_t i2sPclk; 218 | uint64_t divider; 219 | uint8_t bitrate, wordwidth; 220 | uint32_t x, y; 221 | uint16_t dif; 222 | uint16_t error; 223 | uint16_t x_divide, y_divide; 224 | uint16_t ErrorOptimal = 0xFFFF; 225 | int32_t N; 226 | 227 | //CGU_EntityConnect(CGU_CLKSRC_PLL0_AUDIO, CGU_BASE_APB1); 228 | //CGU_EntityConnect(CGU_CLKSRC_GP_CLKIN, CGU_BASE_APB1); 229 | //CGU_EntityConnect(CGU_CLKSRC_GP_CLKIN, CGU_BASE_APLL); 230 | i2sPclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_I2S); 231 | wordwidth = 16; 232 | //wordwidth = 16 * 2; 233 | bitrate = 2 * wordwidth - 1; 234 | 235 | /* Calculate X and Y divider 236 | * The MCLK rate for the I2S transmitter is determined by the value 237 | * in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE 238 | * setting depends on the desired audio sample rate desired, the format 239 | * (stereo/mono) used, and the data size. 240 | * The formula is: 241 | * I2S_MCLK = PCLK * (X/Y) / 2 242 | * We have: 243 | * I2S_MCLK = Freq * bit_rate * I2Sx->TXBITRATE; 244 | * So: (X/Y) = (Freq * bit_rate * I2Sx->TXBITRATE)/PCLK*2 245 | * We use a loop function to chose the most suitable X,Y value 246 | */ 247 | 248 | /* divider is a fixed point number with 16 fractional bits */ 249 | divider = ((uint64_t)(Freq *( bitrate+1) * 2)<<16) / i2sPclk; 250 | 251 | /* find N that make x/y <= 1 -> divider <= 2^16 */ 252 | for(N=64;N>0;N--){ 253 | if((divider*N) < (1<<16)) break; 254 | } 255 | 256 | if(N == 0) return; 257 | 258 | divider *= N; 259 | 260 | for (y = 255; y > 0; y--) { 261 | x = y * divider; 262 | if(x & (0xFF000000)) continue; 263 | dif = x & 0xFFFF; 264 | if(dif>0x8000) error = 0x10000-dif; 265 | else error = dif; 266 | if (error == 0) 267 | { 268 | y_divide = y; 269 | break; 270 | } 271 | else if (error < ErrorOptimal) 272 | { 273 | ErrorOptimal = error; 274 | y_divide = y; 275 | } 276 | } 277 | x_divide = ((uint64_t)y_divide * Freq *( bitrate+1)* N * 2)/i2sPclk; 278 | if(x_divide >= 256) x_divide = 0xFF; 279 | if(x_divide == 0) x_divide = 1; 280 | #else 281 | // 12MHz * (64 / 125) / 2 / 1 / 64 = 48kHz 282 | uint16_t x_divide = 64; 283 | uint16_t y_divide = 125; 284 | int32_t N = 2; 285 | CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_APB1); 286 | #endif 287 | if (TRMode == I2S_TX_MODE)// Transmitter 288 | { 289 | I2Sx->TXBITRATE = N - 1; 290 | //I2Sx->TXBITRATE = 0; // for I2S slave 291 | I2Sx->TXRATE = y_divide | (x_divide << 8); 292 | } else //Receiver 293 | { 294 | I2Sx->RXBITRATE = N - 1; 295 | I2Sx->RXRATE = y_divide | (x_divide << 8); 296 | } 297 | } 298 | -------------------------------------------------------------------------------- /FMReceiverMC/src/cr_start_m0.c: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // +--+ 3 | // | ++----+ 4 | // +-++ | 5 | // | | 6 | // +-+--+ | 7 | // | +--+--+ 8 | // +----+ Copyright (c) 2013 Code Red Technologies Ltd. 9 | // 10 | // cr_start_m0.c 11 | // 12 | // Provides function for CM4 'master' CPU in an NXP LPC43xx MCU to release 13 | // CM0 'slave' CPUs from reset and begin executing. 14 | // 15 | // Version : 130410 16 | // 17 | // Software License Agreement 18 | // 19 | // The software is owned by Code Red Technologies and/or its suppliers, and is 20 | // protected under applicable copyright laws. All rights are reserved. Any 21 | // use in violation of the foregoing restrictions may subject the user to criminal 22 | // sanctions under applicable laws, as well as to civil liability for the breach 23 | // of the terms and conditions of this license. 24 | // 25 | // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 26 | // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 27 | // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 28 | // USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT 29 | // TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH 30 | // CODE RED TECHNOLOGIES LTD. 31 | // 32 | //***************************************************************************** 33 | 34 | #include "cr_start_m0.h" 35 | 36 | // Provide defines for accessing peripheral registers necessary to release 37 | // CM0 slave processors from reset. Note that this code does not use the 38 | // CMSIS register access mechanism, as there is no guarantee that the 39 | // project has been configured to use CMSIS. 40 | #define RGU_RESET_CTRL1 (*((volatile uint32_t *) 0x40053104)) 41 | #define RGU_RESET_ACTIVE_STATUS1 (*((volatile uint32_t *) 0x40053154)) 42 | #define RGU_RESET_CTRL0 (*((volatile uint32_t *) 0x40053100)) 43 | #define RGU_RESET_ACTIVE_STATUS0 (*((volatile uint32_t *) 0x40053150)) 44 | #define CREG_M0APPMEMMAP (*((volatile uint32_t *) 0x40043404)) 45 | #define CREG_M0SUBMEMMAP (*((volatile uint32_t *) 0x40043308)) 46 | 47 | /******************************************************************* 48 | * Static function to Release SLAVE processor from reset 49 | *******************************************************************/ 50 | static void startSlave(uint32_t slavenum) { 51 | 52 | volatile uint32_t u32REG, u32Val; 53 | 54 | if (slavenum <= SLAVE_M0SUB) { 55 | 56 | if (slavenum == SLAVE_M0APP) { 57 | /* Release Slave from reset, first read status */ 58 | /* Notice, this is a read only register !!! */ 59 | u32REG = RGU_RESET_ACTIVE_STATUS1; 60 | 61 | /* If the M0 is being held in reset, release it */ 62 | /* 1 = no reset, 0 = reset */ 63 | while (!(u32REG & (1u << 24))) { 64 | u32Val = (~(u32REG) & (~(1 << 24))); 65 | RGU_RESET_CTRL1 = u32Val; 66 | u32REG = RGU_RESET_ACTIVE_STATUS1; 67 | }; 68 | } 69 | else { // (slavenum == SLAVE_M0SUB) 70 | /* Release Slave from reset, first read status */ 71 | /* Notice, this is a read only register !!! */ 72 | u32REG = RGU_RESET_ACTIVE_STATUS0; 73 | 74 | /* If the M0 is being held in reset, release it */ 75 | /* 1 = no reset, 0 = reset */ 76 | while (!(u32REG & (1u << 12))) { 77 | u32Val = (~(u32REG) & (~(1 << 12))); 78 | RGU_RESET_CTRL0 = u32Val; 79 | u32REG = RGU_RESET_ACTIVE_STATUS0; 80 | }; 81 | 82 | } 83 | } 84 | } 85 | 86 | /******************************************************************* 87 | * Static function to put the SLAVE processor back in reset 88 | *******************************************************************/ 89 | static void haltSlave(uint32_t slavenum) { 90 | 91 | volatile uint32_t u32REG, u32Val; 92 | 93 | if (slavenum <= SLAVE_M0SUB) { 94 | 95 | if (slavenum == SLAVE_M0APP) { 96 | 97 | /* Check if M0 is reset by reading status */ 98 | u32REG = RGU_RESET_ACTIVE_STATUS1; 99 | 100 | /* If the M0 has reset not asserted, halt it... */ 101 | /* in u32REG, status register, 1 = no reset */ 102 | while ((u32REG & (1u << 24))) { 103 | u32Val = ((~u32REG) | (1 << 24)); 104 | RGU_RESET_CTRL1 = u32Val; 105 | u32REG = RGU_RESET_ACTIVE_STATUS1; 106 | } 107 | } else { // (slavenum == SLAVE_M0SUB) 108 | /* Check if M0 is reset by reading status */ 109 | u32REG = RGU_RESET_ACTIVE_STATUS0; 110 | 111 | /* If the M0 has reset not asserted, halt it... */ 112 | /* in u32REG, status register, 1 = no reset */ 113 | while ((u32REG & (1u << 12))) { 114 | u32Val = ((~u32REG) | (1 << 12)); 115 | RGU_RESET_CTRL0 = u32Val; 116 | u32REG = RGU_RESET_ACTIVE_STATUS0; 117 | } 118 | 119 | } 120 | } 121 | 122 | } 123 | 124 | /******************************************************************* 125 | * Function to start required CM0 slave cpu executing 126 | *******************************************************************/ 127 | void cr_start_m0(uint32_t slavenum, uint8_t *CM0image_start) { 128 | 129 | if (slavenum <= SLAVE_M0SUB) { 130 | 131 | // Make sure M0 is not running 132 | haltSlave(slavenum); 133 | 134 | // Set M0's vector table to point to start of M0 image 135 | if (slavenum == SLAVE_M0APP) { 136 | CREG_M0APPMEMMAP = (uint32_t) CM0image_start; 137 | } else { // (slavenum == SLAVE_M0SUB) 138 | CREG_M0SUBMEMMAP = (uint32_t) CM0image_start; 139 | } 140 | // Release M0 from reset 141 | startSlave(slavenum); 142 | } 143 | } 144 | -------------------------------------------------------------------------------- /FMReceiverMC/src/cr_start_m0.h: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // 3 | // cr_start_m0.h 4 | // 5 | // Provides function for CM4 'master' CPU in an NXP LPC43xx MCU to release 6 | // CM0 'slave' CPUs from reset and begin executing. 7 | // 8 | // Version : 130731 9 | // 10 | //***************************************************************************** 11 | // 12 | // Copyright(C) NXP Semiconductors, 2013 13 | // All rights reserved. 14 | // 15 | // Software that is described herein is for illustrative purposes only 16 | // which provides customers with programming information regarding the 17 | // LPC products. This software is supplied "AS IS" without any warranties of 18 | // any kind, and NXP Semiconductors and its licensor disclaim any and 19 | // all warranties, express or implied, including all implied warranties of 20 | // merchantability, fitness for a particular purpose and non-infringement of 21 | // intellectual property rights. NXP Semiconductors assumes no responsibility 22 | // or liability for the use of the software, conveys no license or rights under any 23 | // patent, copyright, mask work right, or any other intellectual property rights in 24 | // or to any products. NXP Semiconductors reserves the right to make changes 25 | // in the software without notification. NXP Semiconductors also makes no 26 | // representation or warranty that such application will be suitable for the 27 | // specified use without further testing or modification. 28 | // 29 | // Permission to use, copy, modify, and distribute this software and its 30 | // documentation is hereby granted, under NXP Semiconductors' and its 31 | // licensor's relevant copyrights in the software, without fee, provided that it 32 | // is used in conjunction with NXP Semiconductors microcontrollers. This 33 | // copyright, permission, and disclaimer notice must appear in all copies of 34 | // this code. 35 | //***************************************************************************** 36 | 37 | #ifndef CR_START_M0_H_ 38 | #define CR_START_M0_H_ 39 | 40 | #define SLAVE_M0APP 0 41 | #define SLAVE_M0SUB 1 42 | 43 | #include 44 | 45 | #ifdef __cplusplus 46 | extern "C" 47 | { 48 | #endif 49 | 50 | extern uint8_t __core_m0app_START__; 51 | extern uint8_t __core_m0sub_START__; 52 | 53 | /******************************************************************* 54 | * Function to start required CM0 slave cpu executing 55 | *******************************************************************/ 56 | void cr_start_m0(uint32_t slavenum, uint8_t *CM0image_start); 57 | 58 | #ifdef __cplusplus 59 | } 60 | #endif 61 | 62 | #endif /* CR_START_M0_H_ */ 63 | -------------------------------------------------------------------------------- /FMReceiverMC/src/cr_startup_lpc43xx.c: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // +--+ 3 | // | ++----+ 4 | // +-++ | 5 | // | | 6 | // +-+--+ | 7 | // | +--+--+ 8 | // +----+ Copyright (c) 2011-13 Code Red Technologies Ltd. 9 | // 10 | // LPC43xx (Cortex-M4) Microcontroller Startup code for use with Red Suite 11 | // 12 | // Version : 130320 13 | // 14 | // Software License Agreement 15 | // 16 | // The software is owned by Code Red Technologies and/or its suppliers, and is 17 | // protected under applicable copyright laws. All rights are reserved. Any 18 | // use in violation of the foregoing restrictions may subject the user to criminal 19 | // sanctions under applicable laws, as well as to civil liability for the breach 20 | // of the terms and conditions of this license. 21 | // 22 | // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 23 | // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 24 | // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 25 | // USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT 26 | // TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH 27 | // CODE RED TECHNOLOGIES LTD. 28 | // 29 | //***************************************************************************** 30 | #if defined (__cplusplus) 31 | #ifdef __REDLIB__ 32 | #error Redlib does not support C++ 33 | #else 34 | //***************************************************************************** 35 | // 36 | // The entry point for the C++ library startup 37 | // 38 | //***************************************************************************** 39 | extern "C" { 40 | extern void __libc_init_array(void); 41 | } 42 | #endif 43 | #endif 44 | 45 | #define WEAK __attribute__ ((weak)) 46 | #define ALIAS(f) __attribute__ ((weak, alias (#f))) 47 | 48 | // Code Red - if CMSIS is being used, then SystemInit() routine 49 | // will be called by startup code rather than in application's main() 50 | #if defined (__USE_CMSIS) 51 | #include "LPC43xx.h" 52 | #endif 53 | 54 | //***************************************************************************** 55 | #if defined (__cplusplus) 56 | extern "C" { 57 | #endif 58 | 59 | //***************************************************************************** 60 | // 61 | // Forward declaration of the default handlers. These are aliased. 62 | // When the application defines a handler (with the same name), this will 63 | // automatically take precedence over these weak definitions 64 | // 65 | //***************************************************************************** 66 | void ResetISR(void); 67 | WEAK void NMI_Handler(void); 68 | WEAK void HardFault_Handler(void); 69 | WEAK void MemManage_Handler(void); 70 | WEAK void BusFault_Handler(void); 71 | WEAK void UsageFault_Handler(void); 72 | WEAK void SVC_Handler(void); 73 | WEAK void DebugMon_Handler(void); 74 | WEAK void PendSV_Handler(void); 75 | WEAK void SysTick_Handler(void); 76 | WEAK void IntDefaultHandler(void); 77 | 78 | //***************************************************************************** 79 | // 80 | // Forward declaration of the specific IRQ handlers. These are aliased 81 | // to the IntDefaultHandler, which is a 'forever' loop. When the application 82 | // defines a handler (with the same name), this will automatically take 83 | // precedence over these weak definitions 84 | // 85 | //***************************************************************************** 86 | void DAC_IRQHandler(void) ALIAS(IntDefaultHandler); 87 | void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler); 88 | void DMA_IRQHandler(void) ALIAS(IntDefaultHandler); 89 | void EZH_IRQHandler(void) ALIAS(IntDefaultHandler); 90 | void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler); 91 | void ETH_IRQHandler(void) ALIAS(IntDefaultHandler); 92 | void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler); 93 | void LCD_IRQHandler(void) ALIAS(IntDefaultHandler); 94 | void USB0_IRQHandler(void) ALIAS(IntDefaultHandler); 95 | void USB1_IRQHandler(void) ALIAS(IntDefaultHandler); 96 | void SCT_IRQHandler(void) ALIAS(IntDefaultHandler); 97 | void RIT_IRQHandler(void) ALIAS(IntDefaultHandler); 98 | void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler); 99 | void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler); 100 | void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler); 101 | void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler); 102 | void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler); 103 | void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler); 104 | void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler); 105 | void SPI_IRQHandler (void) ALIAS(IntDefaultHandler); 106 | void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler); 107 | void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler); 108 | void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler); 109 | void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler); 110 | void UART0_IRQHandler(void) ALIAS(IntDefaultHandler); 111 | void UART1_IRQHandler(void) ALIAS(IntDefaultHandler); 112 | void UART2_IRQHandler(void) ALIAS(IntDefaultHandler); 113 | void UART3_IRQHandler(void) ALIAS(IntDefaultHandler); 114 | void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler); 115 | void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler); 116 | void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler); 117 | void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler); 118 | void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler); 119 | void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler); 120 | void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler); 121 | void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler); 122 | void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler); 123 | void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler); 124 | void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler); 125 | void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler); 126 | void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler); 127 | void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler); 128 | void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler); 129 | void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler); 130 | void VADC_IRQHandler(void) ALIAS(IntDefaultHandler); 131 | void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler); 132 | void RTC_IRQHandler(void) ALIAS(IntDefaultHandler); 133 | void WDT_IRQHandler(void) ALIAS(IntDefaultHandler); 134 | void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler); 135 | void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler); 136 | void QEI_IRQHandler(void) ALIAS(IntDefaultHandler); 137 | 138 | //***************************************************************************** 139 | // 140 | // The entry point for the application. 141 | // __main() is the entry point for Redlib based applications 142 | // main() is the entry point for Newlib based applications 143 | // 144 | //***************************************************************************** 145 | #if defined (__REDLIB__) 146 | extern void __main(void); 147 | #endif 148 | extern int main(void); 149 | //***************************************************************************** 150 | // 151 | // External declaration for the pointer to the stack top from the Linker Script 152 | // 153 | //***************************************************************************** 154 | extern void _vStackTop(void); 155 | 156 | //***************************************************************************** 157 | #if defined (__cplusplus) 158 | } // extern "C" 159 | #endif 160 | //***************************************************************************** 161 | // 162 | // The vector table. 163 | // This relies on the linker script to place at correct location in memory. 164 | // 165 | //***************************************************************************** 166 | extern void (* const g_pfnVectors[])(void); 167 | __attribute__ ((section(".isr_vector"))) 168 | void (* const g_pfnVectors[])(void) = { 169 | // Core Level - CM4 170 | &_vStackTop, // The initial stack pointer 171 | ResetISR, // The reset handler 172 | NMI_Handler, // The NMI handler 173 | HardFault_Handler, // The hard fault handler 174 | MemManage_Handler, // The MPU fault handler 175 | BusFault_Handler, // The bus fault handler 176 | UsageFault_Handler, // The usage fault handler 177 | 0, // Reserved 178 | 0, // Reserved 179 | 0, // Reserved 180 | 0, // Reserved 181 | SVC_Handler, // SVCall handler 182 | DebugMon_Handler, // Debug monitor handler 183 | 0, // Reserved 184 | PendSV_Handler, // The PendSV handler 185 | SysTick_Handler, // The SysTick handler 186 | 187 | // Chip Level - LPC43 (M4) 188 | DAC_IRQHandler, // 16 189 | M0CORE_IRQHandler, // 17 190 | DMA_IRQHandler, // 18 191 | EZH_IRQHandler, // 19 192 | FLASH_EEPROM_IRQHandler, // 20 193 | ETH_IRQHandler, // 21 194 | SDIO_IRQHandler, // 22 195 | LCD_IRQHandler, // 23 196 | USB0_IRQHandler, // 24 197 | USB1_IRQHandler, // 25 198 | SCT_IRQHandler, // 26 199 | RIT_IRQHandler, // 27 200 | TIMER0_IRQHandler, // 28 201 | TIMER1_IRQHandler, // 29 202 | TIMER2_IRQHandler, // 30 203 | TIMER3_IRQHandler, // 31 204 | MCPWM_IRQHandler, // 32 205 | ADC0_IRQHandler, // 33 206 | I2C0_IRQHandler, // 34 207 | I2C1_IRQHandler, // 35 208 | SPI_IRQHandler, // 36 209 | ADC1_IRQHandler, // 37 210 | SSP0_IRQHandler, // 38 211 | SSP1_IRQHandler, // 39 212 | UART0_IRQHandler, // 40 213 | UART1_IRQHandler, // 41 214 | UART2_IRQHandler, // 42 215 | UART3_IRQHandler, // 43 216 | I2S0_IRQHandler, // 44 217 | I2S1_IRQHandler, // 45 218 | SPIFI_IRQHandler, // 46 219 | SGPIO_IRQHandler, // 47 220 | GPIO0_IRQHandler, // 48 221 | GPIO1_IRQHandler, // 49 222 | GPIO2_IRQHandler, // 50 223 | GPIO3_IRQHandler, // 51 224 | GPIO4_IRQHandler, // 52 225 | GPIO5_IRQHandler, // 53 226 | GPIO6_IRQHandler, // 54 227 | GPIO7_IRQHandler, // 55 228 | GINT0_IRQHandler, // 56 229 | GINT1_IRQHandler, // 57 230 | EVRT_IRQHandler, // 58 231 | CAN1_IRQHandler, // 59 232 | 0, // 60 233 | VADC_IRQHandler, // 61 234 | ATIMER_IRQHandler, // 62 235 | RTC_IRQHandler, // 63 236 | 0, // 64 237 | WDT_IRQHandler, // 65 238 | M0SUB_IRQHandler, // 66 239 | CAN0_IRQHandler, // 67 240 | QEI_IRQHandler, // 68 241 | }; 242 | 243 | //***************************************************************************** 244 | // Functions to carry out the initialization of RW and BSS data sections. These 245 | // are written as separate functions rather than being inlined within the 246 | // ResetISR() function in order to cope with MCUs with multiple banks of 247 | // memory. 248 | //***************************************************************************** 249 | __attribute__ ((section(".after_vectors"))) 250 | void data_init(unsigned int romstart, unsigned int start, unsigned int len) { 251 | unsigned int *pulDest = (unsigned int*) start; 252 | unsigned int *pulSrc = (unsigned int*) romstart; 253 | unsigned int loop; 254 | for (loop = 0; loop < len; loop = loop + 4) 255 | *pulDest++ = *pulSrc++; 256 | } 257 | 258 | __attribute__ ((section(".after_vectors"))) 259 | void bss_init(unsigned int start, unsigned int len) { 260 | unsigned int *pulDest = (unsigned int*) start; 261 | unsigned int loop; 262 | for (loop = 0; loop < len; loop = loop + 4) 263 | *pulDest++ = 0; 264 | } 265 | 266 | //***************************************************************************** 267 | // The following symbols are constructs generated by the linker, indicating 268 | // the location of various points in the "Global Section Table". This table is 269 | // created by the linker via the Code Red managed linker script mechanism. It 270 | // contains the load address, execution address and length of each RW data 271 | // section and the execution and length of each BSS (zero initialized) section. 272 | //***************************************************************************** 273 | extern unsigned int __data_section_table; 274 | extern unsigned int __data_section_table_end; 275 | extern unsigned int __bss_section_table; 276 | extern unsigned int __bss_section_table_end; 277 | 278 | //***************************************************************************** 279 | // Reset entry point for your code. 280 | // Sets up a simple runtime environment and initializes the C/C++ 281 | // library. 282 | // 283 | //***************************************************************************** 284 | __attribute__ ((section(".after_vectors"))) 285 | void 286 | ResetISR(void) { 287 | 288 | // ************************************************************* 289 | // The following conditional block of code manually resets as 290 | // much of the peripheral set of the LPC43 as possible. This is 291 | // done because the LPC43 does not provide a means of triggering 292 | // a full system reset under debugger control, which can cause 293 | // problems in certain circumstances when debugging. 294 | // 295 | // You can prevent this code block being included if you require 296 | // (for example when creating a final executable which you will 297 | // not debug) by setting the define 'DONT_RESET_ON_RESTART'. 298 | // 299 | #ifndef DONT_RESET_ON_RESTART 300 | 301 | // Disable interrupts 302 | __asm volatile ("cpsid i"); 303 | // equivalent to CMSIS '__disable_irq()' function 304 | 305 | unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100; 306 | // LPC_RGU->RESET_CTRL0 @ 0x40053100 307 | // LPC_RGU->RESET_CTRL1 @ 0x40053104 308 | // Note that we do not use the CMSIS register access mechanism, 309 | // as there is no guarantee that the project has been configured 310 | // to use CMSIS. 311 | 312 | // Write to LPC_RGU->RESET_CTRL0 313 | *(RESET_CONTROL+0) = 0x10DF1000; 314 | // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST| 315 | // USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST 316 | 317 | // Write to LPC_RGU->RESET_CTRL1 318 | *(RESET_CONTROL+1) = 0x01DFF7FF; 319 | // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST| 320 | // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST| 321 | // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST| 322 | // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST 323 | 324 | // Clear all pending interrupts in the NVIC 325 | volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280; 326 | unsigned int irqpendloop; 327 | for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) { 328 | *(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF; 329 | } 330 | 331 | // Reenable interrupts 332 | __asm volatile ("cpsie i"); 333 | // equivalent to CMSIS '__enable_irq()' function 334 | 335 | #endif // ifndef DONT_RESET_ON_RESTART 336 | // ************************************************************* 337 | 338 | 339 | // 340 | // Copy the data sections from flash to SRAM. 341 | // 342 | unsigned int LoadAddr, ExeAddr, SectionLen; 343 | unsigned int *SectionTableAddr; 344 | 345 | // Load base address of Global Section Table 346 | SectionTableAddr = &__data_section_table; 347 | 348 | // Copy the data sections from flash to SRAM. 349 | while (SectionTableAddr < &__data_section_table_end) { 350 | LoadAddr = *SectionTableAddr++; 351 | ExeAddr = *SectionTableAddr++; 352 | SectionLen = *SectionTableAddr++; 353 | data_init(LoadAddr, ExeAddr, SectionLen); 354 | } 355 | // At this point, SectionTableAddr = &__bss_section_table; 356 | // Zero fill the bss segment 357 | while (SectionTableAddr < &__bss_section_table_end) { 358 | ExeAddr = *SectionTableAddr++; 359 | SectionLen = *SectionTableAddr++; 360 | bss_init(ExeAddr, SectionLen); 361 | } 362 | 363 | #if defined (__VFP_FP__) && !defined (__SOFTFP__) 364 | /* 365 | * Code to enable the Cortex-M4 FPU only included 366 | * if appropriate build options have been selected. 367 | * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) 368 | */ 369 | // CPACR is located at address 0xE000ED88 370 | asm("LDR.W R0, =0xE000ED88"); 371 | // Read CPACR 372 | asm("LDR R1, [R0]"); 373 | // Set bits 20-23 to enable CP10 and CP11 coprocessors 374 | asm(" ORR R1, R1, #(0xF << 20)"); 375 | // Write back the modified value to the CPACR 376 | asm("STR R1, [R0]"); 377 | #endif // (__VFP_FP__) && !(__SOFTFP__) 378 | 379 | // ****************************** 380 | // Check to see if we are running the code from a non-zero 381 | // address (eg RAM, external flash), in which case we need 382 | // to modify the VTOR register to tell the CPU that the 383 | // vector table is located at a non-0x0 address. 384 | 385 | // Note that we do not use the CMSIS register access mechanism, 386 | // as there is no guarantee that the project has been configured 387 | // to use CMSIS. 388 | unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; 389 | if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { 390 | // CMSIS : SCB->VTOR =

391 | *pSCB_VTOR = (unsigned int)g_pfnVectors; 392 | } 393 | 394 | #ifdef __USE_CMSIS 395 | SystemInit(); 396 | #endif 397 | 398 | #if defined (__cplusplus) 399 | // 400 | // Call C++ library initialisation 401 | // 402 | __libc_init_array(); 403 | #endif 404 | 405 | #if defined (__REDLIB__) 406 | // Call the Redlib library, which in turn calls main() 407 | __main() ; 408 | #else 409 | main(); 410 | #endif 411 | 412 | // 413 | // main() shouldn't return, but if it does, we'll just enter an infinite loop 414 | // 415 | while (1) { 416 | ; 417 | } 418 | } 419 | 420 | //***************************************************************************** 421 | // Default exception handlers. Override the ones here by defining your own 422 | // handler routines in your application code. 423 | //***************************************************************************** 424 | __attribute__ ((section(".after_vectors"))) 425 | void NMI_Handler(void) 426 | { 427 | while(1) 428 | { 429 | } 430 | } 431 | __attribute__ ((section(".after_vectors"))) 432 | void HardFault_Handler(void) 433 | { 434 | while(1) 435 | { 436 | } 437 | } 438 | __attribute__ ((section(".after_vectors"))) 439 | void MemManage_Handler(void) 440 | { 441 | while(1) 442 | { 443 | } 444 | } 445 | __attribute__ ((section(".after_vectors"))) 446 | void BusFault_Handler(void) 447 | { 448 | while(1) 449 | { 450 | } 451 | } 452 | __attribute__ ((section(".after_vectors"))) 453 | void UsageFault_Handler(void) 454 | { 455 | while(1) 456 | { 457 | } 458 | } 459 | __attribute__ ((section(".after_vectors"))) 460 | void SVC_Handler(void) 461 | { 462 | while(1) 463 | { 464 | } 465 | } 466 | __attribute__ ((section(".after_vectors"))) 467 | void DebugMon_Handler(void) 468 | { 469 | while(1) 470 | { 471 | } 472 | } 473 | __attribute__ ((section(".after_vectors"))) 474 | void PendSV_Handler(void) 475 | { 476 | while(1) 477 | { 478 | } 479 | } 480 | __attribute__ ((section(".after_vectors"))) 481 | void SysTick_Handler(void) 482 | { 483 | while(1) 484 | { 485 | } 486 | } 487 | 488 | //***************************************************************************** 489 | // 490 | // Processor ends up here if an unexpected interrupt occurs or a specific 491 | // handler is not present in the application code. 492 | // 493 | //***************************************************************************** 494 | __attribute__ ((section(".after_vectors"))) 495 | void IntDefaultHandler(void) 496 | { 497 | while(1) 498 | { 499 | } 500 | } 501 | -------------------------------------------------------------------------------- /FMReceiverMC/src/crp.c: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // crp.c 3 | // 4 | // Source file to create CRP word expected by LPCXpresso IDE linker 5 | //***************************************************************************** 6 | // 7 | // Copyright(C) NXP Semiconductors, 2013 8 | // All rights reserved. 9 | // 10 | // Software that is described herein is for illustrative purposes only 11 | // which provides customers with programming information regarding the 12 | // LPC products. This software is supplied "AS IS" without any warranties of 13 | // any kind, and NXP Semiconductors and its licensor disclaim any and 14 | // all warranties, express or implied, including all implied warranties of 15 | // merchantability, fitness for a particular purpose and non-infringement of 16 | // intellectual property rights. NXP Semiconductors assumes no responsibility 17 | // or liability for the use of the software, conveys no license or rights under any 18 | // patent, copyright, mask work right, or any other intellectual property rights in 19 | // or to any products. NXP Semiconductors reserves the right to make changes 20 | // in the software without notification. NXP Semiconductors also makes no 21 | // representation or warranty that such application will be suitable for the 22 | // specified use without further testing or modification. 23 | // 24 | // Permission to use, copy, modify, and distribute this software and its 25 | // documentation is hereby granted, under NXP Semiconductors' and its 26 | // licensor's relevant copyrights in the software, without fee, provided that it 27 | // is used in conjunction with NXP Semiconductors microcontrollers. This 28 | // copyright, permission, and disclaimer notice must appear in all copies of 29 | // this code. 30 | //***************************************************************************** 31 | 32 | #if defined (__CODE_RED) 33 | #include 34 | // Variable to store CRP value in. Will be placed automatically 35 | // by the linker when "Enable Code Read Protect" selected. 36 | // See crp.h header for more information 37 | __CRP const unsigned int CRP_WORD = CRP_NO_CRP ; 38 | #endif 39 | -------------------------------------------------------------------------------- /FMReceiverMC/src/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | /* 21 | * @copyright Copyright 2013 Embedded Artists AB 22 | * 23 | * Permission to use, copy, modify, and distribute this software and its 24 | * documentation is hereby granted, without fee, provided that it 25 | * is used in conjunction with NXP Semiconductors microcontrollers. This 26 | * copyright, permission, and disclaimer notice must appear in all copies of 27 | * this code. 28 | * 29 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 30 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 31 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 32 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 33 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 34 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 35 | * THE SOFTWARE. 36 | */ 37 | 38 | #ifdef __USE_CMSIS 39 | #include "LPC43xx.h" 40 | #endif 41 | 42 | #include 43 | #include 44 | #include 45 | #include 46 | #include 47 | #include 48 | #include "lpc43xx_i2s.h" 49 | #include "lpc43xx_i2c.h" 50 | 51 | #include 52 | 53 | #if defined (LPC43_MULTICORE_M0APP) | defined (LPC43_MULTICORE_M0SUB) 54 | #include "cr_start_m0.h" 55 | #endif 56 | 57 | #include 58 | #include 59 | 60 | #include "receiver.h" 61 | #include "vadc.h" 62 | 63 | #if EXTCLK_10MHZ 64 | // PLL0AUDIO: 40MHz = (40MHz / 25) * (500 * 2) / (10 * 2) 65 | #define PLL0_MSEL 500 66 | #define PLL0_NSEL 50 67 | #define PLL0_PSEL 10 68 | #define ADCCLK_MATCHVALUE (4 - 1) // 40MHz / 2 = 10MHz 69 | #elif 1 70 | // PLL0AUDIO: 39.936MHz = (12MHz / 25) * (416 * 2) / (5 * 2) 71 | #define PLL0_MSEL 416 72 | #define PLL0_NSEL 25 73 | #define PLL0_PSEL 5 74 | #define ADCCLK_MATCHVALUE (4 - 1) // 39.936MHz / 4 = 9.984MHz 75 | #elif 0 76 | // PLL0AUDIO: 40MHz = (12MHz / 15) * (400 * 2) / (8 * 2) 77 | #define PLL0_MSEL 400 78 | #define PLL0_NSEL 15 79 | #define PLL0_PSEL 8 80 | #endif 81 | 82 | #define FIFO_SIZE 8 83 | 84 | #define DMA_LLI_NUM 16 85 | static GPDMA_LLI_Type DMA_LTable[DMA_LLI_NUM]; 86 | 87 | volatile int32_t capture_count; 88 | 89 | 90 | void VADC_SetupDMA(void) 91 | { 92 | int i; 93 | uint32_t transfersize; 94 | uint32_t blocksize; 95 | uint8_t *buffer; 96 | 97 | NVIC_DisableIRQ(DMA_IRQn); 98 | LPC_GPDMA->C0CONFIG = 0; 99 | 100 | /* clear all interrupts on channel 0 */ 101 | LPC_GPDMA->INTTCCLEAR = 0x01; 102 | LPC_GPDMA->INTERRCLR = 0x01; 103 | 104 | /* Setup the DMAMUX */ 105 | LPC_CREG->DMAMUX &= ~(0x3<<(VADC_DMA_WRITE*2)); 106 | LPC_CREG->DMAMUX |= 0x3<<(VADC_DMA_WRITE*2); /* peripheral 7 vADC Write(0x3) */ 107 | LPC_CREG->DMAMUX &= ~(0x3<<(VADC_DMA_READ*2)); 108 | LPC_CREG->DMAMUX |= 0x3<<(VADC_DMA_READ*2); /* peripheral 8 vADC read(0x3) */ 109 | 110 | LPC_GPDMA->CONFIG = 0x01; /* Enable DMA channels, little endian */ 111 | while ( !(LPC_GPDMA->CONFIG & 0x01) ); 112 | 113 | // The size of the transfer is in multiples of 32bit copies (hence the /4) 114 | // and must be even multiples of FIFO_SIZE. 115 | buffer = CAPTUREBUFFER0; 116 | blocksize = CAPTUREBUFFER_SIZE / DMA_LLI_NUM; 117 | transfersize = blocksize / 4; 118 | 119 | for (i = 0; i < DMA_LLI_NUM; i++) 120 | { 121 | if (i == DMA_LLI_NUM / 2) 122 | buffer = CAPTUREBUFFER1; 123 | DMA_LTable[i].SrcAddr = VADC_DMA_READ_SRC; 124 | DMA_LTable[i].DstAddr = (uint32_t)buffer; 125 | DMA_LTable[i].NextLLI = (uint32_t)(&DMA_LTable[(i+1) % DMA_LLI_NUM]); 126 | DMA_LTable[i].Control = (transfersize << 0) | // Transfersize (does not matter when flow control is handled by peripheral) 127 | (0x2 << 12) | // Source Burst Size 128 | (0x2 << 15) | // Destination Burst Size 129 | //(0x0 << 15) | // Destination Burst Size 130 | (0x2 << 18) | // Source width // 32 bit width 131 | (0x2 << 21) | // Destination width // 32 bits 132 | (0x1 << 24) | // Source AHB master 0 / 1 133 | (0x0 << 25) | // Dest AHB master 0 / 1 134 | (0x0 << 26) | // Source increment(LAST Sample) 135 | (0x1 << 27) | // Destination increment 136 | (0x0UL << 31); // Terminal count interrupt disabled 137 | buffer += blocksize; 138 | } 139 | 140 | // Let the last LLI in the chain cause a terminal count interrupt to 141 | // notify when the capture buffer is completely filled 142 | DMA_LTable[DMA_LLI_NUM/2 - 1].Control |= (0x1UL << 31); // Terminal count interrupt enabled 143 | DMA_LTable[DMA_LLI_NUM - 1].Control |= (0x1UL << 31); // Terminal count interrupt enabled 144 | 145 | LPC_GPDMA->C0SRCADDR = DMA_LTable[0].SrcAddr; 146 | LPC_GPDMA->C0DESTADDR = DMA_LTable[0].DstAddr; 147 | LPC_GPDMA->C0CONTROL = DMA_LTable[0].Control; 148 | LPC_GPDMA->C0LLI = (uint32_t)(&DMA_LTable[1]); // must be pointing to the second LLI as the first is used when initializing 149 | LPC_GPDMA->C0CONFIG = (0x1) | // Enable bit 150 | (VADC_DMA_READ << 1) | // SRCPERIPHERAL - set to 8 - VADC 151 | (0x0 << 6) | // Destination peripheral - memory - no setting 152 | (0x2 << 11) | // Flow control - peripheral to memory - DMA control 153 | // (0x6 << 11) | // Flow control - peripheral to memory - peripheral control 154 | (0x1 << 14) | // Int error mask 155 | (0x1 << 15); // ITC - term count error mask 156 | 157 | NVIC_EnableIRQ(DMA_IRQn); 158 | } 159 | 160 | void VADC_Init(void) 161 | { 162 | #if EXTCLK_10MHZ 163 | scu_pinmux(0xF, 4, MD_PLN_FAST, FUNC1); // GP_CLKIN 164 | CGU_EntityConnect(CGU_CLKSRC_GP_CLKIN, CGU_BASE_VADC); 165 | #else 166 | CGU_EntityConnect(CGU_CLKSRC_PLL0_AUDIO, CGU_BASE_VADC); 167 | #endif 168 | CGU_EnableEntity(CGU_BASE_VADC, ENABLE); 169 | 170 | // RGU_SoftReset(RGU_SIG_DMA); 171 | // while(RGU_GetSignalStatus(RGU_SIG_DMA)); 172 | 173 | // Reset the VADC block 174 | RGU_SoftReset(RGU_SIG_VADC); 175 | while(RGU_GetSignalStatus(RGU_SIG_VADC)); 176 | 177 | // Disable the VADC interrupt 178 | NVIC_DisableIRQ(VADC_IRQn); 179 | LPC_VADC->CLR_EN0 = STATUS0_CLEAR_MASK; // disable interrupt0 180 | LPC_VADC->CLR_STAT0 = STATUS0_CLEAR_MASK; // clear interrupt status 181 | while(LPC_VADC->STATUS0 & 0x7d); // wait for status to clear, have to exclude FIFO_EMPTY (bit 1) 182 | LPC_VADC->CLR_EN1 = STATUS1_CLEAR_MASK; // disable interrupt1 183 | LPC_VADC->CLR_STAT1 = STATUS1_CLEAR_MASK; // clear interrupt status 184 | while(LPC_VADC->STATUS1); // wait for status to clear 185 | 186 | // Make sure the VADC is not powered down 187 | LPC_VADC->POWER_DOWN = 188 | (0<<0); /* PD_CTRL: 0=disable power down, 1=enable power down */ 189 | 190 | // Clear FIFO 191 | LPC_VADC->FLUSH = 1; 192 | 193 | // FIFO Settings 194 | LPC_VADC->FIFO_CFG = 195 | (1<<0) | /* PACKED_READ: 0= 1 sample packed into 32 bit, 1= 2 samples packed into 32 bit */ 196 | (FIFO_SIZE<<1); /* FIFO_LEVEL: When FIFO contains this or more samples raise FIFO_FULL irq and DMA_Read_Req, default is 8 */ 197 | 198 | // Descriptors: 199 | LPC_VADC->DSCR_STS = 200 | (0<<0) | /* ACT_TABLE: 0=table 0 is active, 1=table 1 is active */ 201 | (0<<1); /* ACT_DESCRIPTOR: ID of the descriptor that is active */ 202 | 203 | LPC_VADC->CONFIG = /* configuration register */ 204 | (1<<0) | /* TRIGGER_MASK: 0=triggers off, 1=SW trigger, 2=EXT trigger, 3=both triggers */ 205 | (0<<2) | /* TRIGGER_MODE: 0=rising, 1=falling, 2=low, 3=high external trigger */ 206 | (0<<4) | /* TRIGGER_SYNC: 0=no sync, 1=sync external trigger input */ 207 | (0<<5) | /* CHANNEL_ID_EN: 0=don't add, 1=add channel id to FIFO output data */ 208 | (0x90<<6); /* RECOVERY_TIME: ADC recovery time from power down, default is 0x90 */ 209 | 210 | LPC_VADC->DESCRIPTOR_0[0] = 211 | (0<<0) | /* CHANNEL_NR: 0=convert input 0, 1=convert input 1, ..., 5=convert input 5 */ 212 | (0<<3) | /* HALT: 0=continue with next descriptor after this one, 1=halt after this and restart at a new trigger */ 213 | (0<<4) | /* INTERRUPT: 1=raise interrupt when ADC result is available */ 214 | (0<<5) | /* POWER_DOWN: 1=power down after this conversion */ 215 | (1<<6) | /* BRANCH: 0=continue with next descriptor (wraps around after top) */ 216 | /* 1=branch to the first descriptor in this table */ 217 | /* 2=swap tables and branch to the first descriptor of the new table */ 218 | /* 3=reserved (do not store sample). continue with next descriptor (wraps around the top) */ 219 | (ADCCLK_MATCHVALUE<<8) | /* MATCH_VALUE: Evaluate this desciptor when descriptor timer value is equal to match value */ 220 | (0<<22) | /* THRESHOLD_SEL: 0=no comparison, 1=THR_A, 2=THR_B */ 221 | (1<<24) | /* RESET_TIME: 1=reset descriptor timer */ 222 | (1UL<<31); /* UPDATE_TABLE: 1=update table with all 8 descriptors of this table */ 223 | 224 | LPC_VADC->ADC_SPEED = 225 | 0x0E; /* DGECx: For CRS=3 all should be 0xF, for CRS=4 all should be 0xE, */ 226 | /* for all other cases it should be 0 */ 227 | 228 | LPC_VADC->POWER_CONTROL = 229 | (4 << 0) | /* CRS: current setting for power versus speed programming */ 230 | (1 << 4) | /* DCINNEG: 0=no dc bias, 1=dc bias on vin_neg slide */ 231 | (0 << 10) | /* DCINPOS: 0=no dc bias, 1=dc bias on vin_pos slide */ 232 | (0 << 16) | /* TWOS: 0=offset binary, 1=two's complement */ 233 | (1 << 17) | /* POWER_SWITCH: 0=ADC is power gated, 1=ADC is active */ 234 | (1 << 18); /* BGAP_SWITCH: 0=ADC bandgap reg is power gated, 1=ADC bandgap is active */ 235 | } 236 | 237 | void VADC_Start(void) 238 | { 239 | capture_count = 0; 240 | LPC_VADC->TRIGGER = 1; 241 | } 242 | 243 | void VADC_Stop(void) 244 | { 245 | // disable DMA 246 | LPC_GPDMA->C0CONFIG |= (1 << 18); //halt further requests 247 | 248 | NVIC_DisableIRQ(I2S0_IRQn); 249 | NVIC_DisableIRQ(DMA_IRQn); 250 | //NVIC_DisableIRQ(VADC_IRQn); 251 | 252 | LPC_VADC->TRIGGER = 0; 253 | // Clear FIFO 254 | LPC_VADC->FLUSH = 1; 255 | // power down VADC 256 | LPC_VADC->POWER_CONTROL = 0; 257 | 258 | // Reset the VADC block 259 | RGU_SoftReset(RGU_SIG_VADC); 260 | while(RGU_GetSignalStatus(RGU_SIG_VADC)); 261 | } 262 | 263 | static int I2CWrite(uint8_t addr, uint8_t data0, uint8_t data1) 264 | { 265 | I2C_M_SETUP_Type txsetup; 266 | uint8_t buf[2]; 267 | txsetup.sl_addr7bit = addr; 268 | txsetup.tx_data = buf; 269 | txsetup.tx_length = sizeof buf; 270 | txsetup.rx_data = NULL; 271 | txsetup.rx_length = 0; 272 | txsetup.retransmissions_max = 3; 273 | buf[0] = data0; 274 | buf[1] = data1; 275 | if (I2C_MasterTransferData(LPC_I2C0, &txsetup, I2C_TRANSFER_POLLING) == SUCCESS){ 276 | return (0); 277 | } else { 278 | return (-1); 279 | } 280 | } 281 | 282 | // -7 ~ 29 283 | void audio_set_gain(int gain) 284 | { 285 | if (gain < -6) 286 | gain = 0x40; // mute 287 | else if (gain > 29) 288 | gain = 29; 289 | else 290 | gain &= 0x3f; 291 | 292 | I2CWrite(0x18, 0x00, 0x01); /* Select Page 1 */ 293 | I2CWrite(0x18, 0x10, gain); /* HPL Driver Gain */ 294 | I2CWrite(0x18, 0x11, gain); /* HPR Driver Gain */ 295 | } 296 | 297 | static void i2s_init(uint32_t rate) 298 | { 299 | I2S_CFG_Type i2sCfg; 300 | I2S_MODEConf_Type i2sMode; 301 | 302 | // Initialize I2C peripheral 303 | I2C_Init(LPC_I2C0, 100000); 304 | 305 | /* Enable I2C0 operation */ 306 | I2C_Cmd(LPC_I2C0, ENABLE); 307 | I2CWrite(0x18, 0x00, 0x00); /* Initialize to Page 0 */ 308 | I2CWrite(0x18, 0x01, 0x01); /* Initialize the device through software reset */ 309 | I2CWrite(0x18, 0x04, 0x43); /* PLL Clock High, MCLK, PLL */ 310 | #if EXTCLK_10MHZ 311 | // MCLK is 40MHz 312 | I2CWrite(0x18, 0x05, 0x91); /* Power up PLL, P=1,R=1 */ 313 | I2CWrite(0x18, 0x06, 0x02); /* J=2 */ 314 | I2CWrite(0x18, 0x07, 0); /* D=0 */ 315 | I2CWrite(0x18, 0x08, 0); 316 | I2CWrite(0x18, 0x0b, 0x81); /* Power up the NDAC divider with value 1 */ 317 | I2CWrite(0x18, 0x0c, 0x8d); /* Power up the MDAC divider with value 13 */ 318 | #ifdef I2S_SLAVE 319 | // codec work as i2s master 320 | I2CWrite(0x18, 0x1b, 0x0c); /* Set the BCLK,WCLK as output */ 321 | I2CWrite(0x18, 0x1e, 0x80 + 52); /* Enable the BCLKN divider with value 52 */ 322 | #endif 323 | #else 324 | // MCLK is 12MHz 325 | I2CWrite(0x18, 0x05, 0x91); /* Power up PLL, P=1,R=1 */ 326 | I2CWrite(0x18, 0x06, 0x07); /* J=7 */ 327 | I2CWrite(0x18, 0x07, 6); /* D=(6 <<8) + 144 */ 328 | I2CWrite(0x18, 0x08, 144); 329 | I2CWrite(0x18, 0x0b, 0x82); /* Power up the NDAC divider with value 2 */ 330 | I2CWrite(0x18, 0x0c, 0x87); /* Power up the MDAC divider with value 7 */ 331 | #endif 332 | I2CWrite(0x18, 0x0d, 0x00); /* Program the OSR of DAC to 128 */ 333 | I2CWrite(0x18, 0x0e, 0x80); 334 | I2CWrite(0x18, 0x3c, 0x08); /* Set the DAC Mode to PRB_P8 */ 335 | I2CWrite(0x18, 0x25, 0xee); /* DAC power up */ 336 | I2CWrite(0x18, 0x00, 0x01); /* Select Page 1 */ 337 | I2CWrite(0x18, 0x01, 0x08); /* Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/ 338 | I2CWrite(0x18, 0x02, 0x01); /* Enable Master Analog Power Control */ 339 | I2CWrite(0x18, 0x7b, 0x01); /* Set the REF charging time to 40ms */ 340 | I2CWrite(0x18, 0x14, 0x25); /* HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. */ 341 | // I2CWrite(0x18, 0x0a, 0x00); /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to Input Common Mode */ 342 | I2CWrite(0x18, 0x0a, 0x33); /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */ 343 | I2CWrite(0x18, 0x0c, 0x08); /* Route Left DAC to HPL */ 344 | I2CWrite(0x18, 0x0d, 0x08); /* Route Right DAC to HPR */ 345 | I2CWrite(0x18, 0x03, 0x00); /* Set the DAC PTM mode to PTM_P3/4 */ 346 | I2CWrite(0x18, 0x04, 0x00); 347 | I2CWrite(0x18, 0x10, 0x0a); /* Set the HPL gain to 0dB */ 348 | I2CWrite(0x18, 0x11, 0x0a); /* Set the HPR gain to 0dB */ 349 | I2CWrite(0x18, 0x09, 0x30); /* Power up HPL and HPR drivers */ 350 | I2CWrite(0x18, 0x00, 0x00); /* Select Page 0 */ 351 | I2CWrite(0x18, 0x3f, 0xd6); /* Power up the Left and Right DAC Channels with route the Left Audio digital data to Left Channel DAC and Right Audio digital data to Right Channel DAC */ 352 | I2CWrite(0x18, 0x40, 0x00); /* Unmute the DAC digital volume control */ 353 | 354 | // Configure I2S pins 355 | scu_pinmux(0x3, 0, MD_PLN_FAST, FUNC2); // SCK 356 | scu_pinmux(0x3, 1, MD_PLN_FAST, FUNC0); // WS 357 | scu_pinmux(0x3, 2, MD_PLN_FAST, FUNC0); // SD 358 | 359 | #if EXTCLK_10MHZ 360 | // supply GPCLK_IN:40MHz as MCLK 361 | LPC_CGU->BASE_OUT_CLK = CGU_CLKSRC_GP_CLKIN << 24; 362 | #else 363 | // for MCLK output XTAL_OSC(12MHz) to TP_CLK0 364 | LPC_CGU->BASE_OUT_CLK = CGU_CLKSRC_XTAL_OSC << 24; 365 | //LPC_CGU->BASE_OUT_CLK = CGU_CLKSRC_PLL0_AUDIO << 24; 366 | #endif 367 | LPC_SCU->SFSCLK_0 = 0x1; 368 | 369 | // Initialize I2S 370 | I2S_Init(LPC_I2S0); 371 | 372 | // Configure I2S 373 | i2sCfg.wordwidth = I2S_WORDWIDTH_16; 374 | #if STEREO 375 | i2sCfg.mono = I2S_STEREO; 376 | #else 377 | i2sCfg.mono = I2S_MONO; 378 | #endif 379 | i2sCfg.stop = I2S_STOP_ENABLE; 380 | i2sCfg.reset = I2S_RESET_ENABLE; 381 | #ifdef I2S_SLAVE 382 | i2sCfg.ws_sel = I2S_SLAVE_MODE; 383 | #else 384 | i2sCfg.ws_sel = I2S_MASTER_MODE; 385 | #endif 386 | i2sCfg.mute = I2S_MUTE_DISABLE; 387 | I2S_Config(LPC_I2S0, I2S_TX_MODE, &i2sCfg); 388 | 389 | // Configure operating mode 390 | i2sMode.clksel = I2S_CLKSEL_FRDCLK; 391 | i2sMode.fpin = I2S_4PIN_DISABLE; 392 | i2sMode.mcena = I2S_MCLK_DISABLE; 393 | //i2sMode.mcena = I2S_MCLK_ENABLE; 394 | I2S_ModeConfig(LPC_I2S0, &i2sMode, I2S_TX_MODE); 395 | 396 | #ifndef I2S_SLAVE 397 | // Configure sampling frequency 398 | setup_i2s_clock(LPC_I2S0, rate, I2S_TX_MODE); 399 | #endif 400 | 401 | I2S_Stop(LPC_I2S0, I2S_TX_MODE); 402 | 403 | I2S_IRQConfig(LPC_I2S0, I2S_TX_MODE, 4); 404 | I2S_IRQCmd(LPC_I2S0, I2S_TX_MODE, ENABLE); 405 | I2S_Start(LPC_I2S0); 406 | NVIC_EnableIRQ(I2S0_IRQn); 407 | } 408 | 409 | void cos_sin_test(uint32_t *buf, int len); 410 | 411 | int main(void) { 412 | setup_systemclock(); 413 | #ifndef I2S_SLAVE 414 | setup_pll0audio(PLL0_MSEL, PLL0_NSEL, PLL0_PSEL); 415 | #endif 416 | // Setup SysTick Timer to interrupt at 1 msec intervals 417 | SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE) / 1000); 418 | 419 | // Start M0APP slave processor 420 | #if defined (LPC43_MULTICORE_M0APP) 421 | cr_start_m0(SLAVE_M0APP,&__core_m0app_START__); 422 | #endif 423 | 424 | // Start M0SUB slave processor 425 | #if defined (LPC43_MULTICORE_M0SUB) 426 | cr_start_m0(SLAVE_M0SUB,&__core_m0sub_START__); 427 | #endif 428 | 429 | //cos_sin_test(AUDIO_TEST_BUFFER, AUDIO_BUFFER_SIZE / sizeof(uint32_t)); 430 | 431 | // interrupt priority: the highest for DMA, i2s 432 | NVIC_SetPriority(DMA_IRQn, ((0x01<<3)|0x01)); 433 | NVIC_SetPriority(I2S0_IRQn, ((0x02<<3)|0x01)); 434 | 435 | TESTPOINT_INIT(); 436 | LED_INIT(); 437 | //printf("Hello SDR!\n"); 438 | 439 | VADC_Init(); 440 | VADC_SetupDMA(); 441 | 442 | ui_init(); 443 | dsp_init(); 444 | 445 | //generate_test_tone((float)AUDIO_RATE/48); 446 | //i2s_init(AUDIO_RATE); 447 | i2s_init(48000); 448 | 449 | VADC_Start(); 450 | 451 | while(1) { 452 | ui_process(); 453 | __WFI(); 454 | //if ((capture_count % 1024) < 512) { 455 | // GPIO_SetValue(0,1<<8); 456 | //} else { 457 | // GPIO_ClearValue(0,1<<8); 458 | //} 459 | 460 | //printf("%08x %08x\n", LPC_VADC->FIFO_OUTPUT[0], LPC_VADC->FIFO_OUTPUT[1]); 461 | //emc_WaitUS(500000); 462 | } 463 | VADC_Stop(); 464 | return 0 ; 465 | } 466 | 467 | 468 | #ifdef DEBUG 469 | void check_failed(uint8_t *file, uint32_t line) 470 | { 471 | /* User can add his own implementation to report the file name and line number, 472 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 473 | 474 | /* Infinite loop */ 475 | while(1); 476 | } 477 | #endif 478 | 479 | -------------------------------------------------------------------------------- /FMReceiverMC/src/ui.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com 3 | * All rights reserved. 4 | * 5 | * This is free software; you can redistribute it and/or modify 6 | * it under the terms of the GNU General Public License as published by 7 | * the Free Software Foundation; either version 3, or (at your option) 8 | * any later version. 9 | * 10 | * The software is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with GNU Radio; see the file COPYING. If not, write to 17 | * the Free Software Foundation, Inc., 51 Franklin Street, 18 | * Boston, MA 02110-1301, USA. 19 | */ 20 | 21 | #ifdef __USE_CMSIS 22 | #include "LPC43xx.h" 23 | #endif 24 | 25 | #include 26 | #include "lpc43xx_gpio.h" 27 | #include "lpc43xx_cgu.h" 28 | #include "lpc43xx_i2c.h" 29 | #include "lpc43xx_rgu.h" 30 | #include "lpc43xx_scu.h" 31 | 32 | #include "receiver.h" 33 | 34 | 35 | volatile uint32_t msTicks; // counter for 1ms SysTicks 36 | 37 | // **************** 38 | // SysTick_Handler - just increment SysTick counter 39 | __attribute__ ((section(".after_vectors"))) 40 | void SysTick_Handler(void) { 41 | msTicks++; 42 | } 43 | 44 | // **************** 45 | // systick_delay - creates a delay of the appropriate number of Systicks (happens every 1 ms) 46 | void systick_delay(uint32_t delayTicks) { 47 | uint32_t currentTicks; 48 | 49 | currentTicks = msTicks; // read current tick counter 50 | // Now loop until required number of ticks passes. 51 | while ((msTicks - currentTicks) < delayTicks); 52 | } 53 | 54 | Status i2clcd_data(uint8_t data) 55 | { 56 | I2C_M_SETUP_Type setup; 57 | uint8_t buf[2]; 58 | buf[0] = 0x40; 59 | buf[1] = data; 60 | setup.sl_addr7bit = 0x7c >> 1; 61 | setup.tx_data = buf; 62 | setup.tx_length = 2; 63 | setup.rx_data = NULL; 64 | setup.rx_length = 0; 65 | setup.retransmissions_max = 3; 66 | return I2C_MasterTransferData(LPC_I2C0, &setup, I2C_TRANSFER_POLLING); 67 | } 68 | 69 | void i2clcd_str(char *p) 70 | { 71 | while (*p) { 72 | i2clcd_data(*p++); 73 | } 74 | } 75 | 76 | Status i2clcd_cmd(uint8_t cmd) 77 | { 78 | I2C_M_SETUP_Type setup; 79 | Status s; 80 | uint8_t buf[2]; 81 | buf[0] = 0; 82 | buf[1] = cmd; 83 | setup.sl_addr7bit = 0x7c >> 1; 84 | setup.tx_data = buf; 85 | setup.tx_length = 2; 86 | setup.rx_data = NULL; 87 | setup.rx_length = 0; 88 | setup.retransmissions_max = 3; 89 | s = I2C_MasterTransferData(LPC_I2C0, &setup, I2C_TRANSFER_POLLING); 90 | if (s != SUCCESS) { 91 | //printf("I2C Failed\n"); 92 | } 93 | return s; 94 | } 95 | 96 | void i2clcd_pos(uint8_t x, uint8_t y) 97 | { 98 | i2clcd_cmd(0x80 | (0x40 * y) | x); 99 | } 100 | 101 | void i2clcd_init() 102 | { 103 | I2C_Init(LPC_I2C0, 10000); 104 | I2C_Cmd(LPC_I2C0, ENABLE); 105 | systick_delay(40); 106 | i2clcd_cmd(0x38); 107 | i2clcd_cmd(0x39); 108 | i2clcd_cmd(0x14); 109 | i2clcd_cmd(0x70); 110 | i2clcd_cmd(0x56); 111 | i2clcd_cmd(0x6c); 112 | systick_delay(200); 113 | i2clcd_cmd(0x38); 114 | i2clcd_cmd(0x0c); 115 | i2clcd_cmd(0x01); 116 | systick_delay(2); 117 | } 118 | 119 | #define NO_EVENT 0 120 | #define EVT_BUTTON_SINGLE_CLICK 0x01 121 | #define EVT_BUTTON_DOUBLE_CLICK 0x02 122 | #define EVT_BUTTON_DOWN_LONG 0x04 123 | #define ENCODER_UP 0x10 124 | #define ENCODER_DOWN 0x20 125 | 126 | #define BUTTON_DOWN_LONG_TICKS 2000 127 | #define BUTTON_DOUBLE_TICKS 500 128 | #define BUTTON_DEBOUNCE_TICKS 10 129 | 130 | #define ENCODER0 0x01 131 | #define ENCODER1 0x02 132 | #define BUTTON0 0x04 133 | 134 | static uint8_t last_button = 0b111; 135 | static uint32_t last_button_down_ticks; 136 | 137 | int btn_check() 138 | { 139 | int cur_button = GPIO_ReadValue(1) & 0b00000111; 140 | int status = 0; 141 | int changed = last_button ^ cur_button; 142 | if (changed & BUTTON0) { 143 | if (msTicks >= last_button_down_ticks + BUTTON_DEBOUNCE_TICKS) { 144 | if (cur_button & BUTTON0) { 145 | // button released 146 | status |= EVT_BUTTON_SINGLE_CLICK; 147 | } else { 148 | // button pushed 149 | if (msTicks < last_button_down_ticks + BUTTON_DOUBLE_TICKS) { 150 | status |= EVT_BUTTON_DOUBLE_CLICK; 151 | } else { 152 | last_button_down_ticks = msTicks; 153 | } 154 | } 155 | } 156 | } else { 157 | // button unchanged 158 | if (!(cur_button & BUTTON0) 159 | && msTicks >= last_button_down_ticks + BUTTON_DOWN_LONG_TICKS) { 160 | status |= EVT_BUTTON_DOWN_LONG; 161 | } 162 | } 163 | 164 | if ((changed & ENCODER0) && !(cur_button & ENCODER0)) { 165 | if (msTicks > last_button_down_ticks + 1) { 166 | int e = cur_button & 0x03; 167 | //printf("%d\n", e); 168 | if (e == 0) 169 | status |= ENCODER_UP; 170 | else if (e == 2) 171 | status |= ENCODER_DOWN; 172 | last_button_down_ticks = msTicks; 173 | } 174 | } 175 | 176 | last_button = cur_button; 177 | return status; 178 | } 179 | 180 | #define CHANNEL_MAX 9 181 | #define TP_MAX 16 182 | #define FREQ_STEP 100000 183 | 184 | static float32_t channel_freqs[CHANNEL_MAX] = { 185 | 80.4e6f, 186 | 82.5e6f, 187 | 85.2e6f, 188 | 80.0e6f, 189 | 81.3e6f, 190 | 76.1e6f, 191 | 77.1e6f, 192 | 145e6f, 193 | }; 194 | 195 | extern audio_state_t audio_state; 196 | extern fm_demod_state_t fm_demod_state; 197 | extern stereo_separate_state_t stereo_separate_state; 198 | 199 | void 200 | ui_update() 201 | { 202 | char buf[16]; 203 | switch (UISTAT->mode) { 204 | case GAIN: 205 | if (UISTAT->gain < -6) 206 | sprintf(buf, "Vol:mute"); 207 | else 208 | sprintf(buf, "Vol:%ddB", UISTAT->gain); 209 | break; 210 | case FREQ: 211 | sprintf(buf, "%2.1fMHz", UISTAT->freq / 1000000); 212 | break; 213 | case CHANNEL: 214 | sprintf(buf, "Ch%d %2.1f", UISTAT->channel, UISTAT->freq / 1000000); 215 | break; 216 | case TESTP: 217 | switch (UISTAT->tp) { 218 | case 0: 219 | sprintf(buf, "CAP:%04x", *(uint16_t*)CAPTUREBUFFER0); 220 | break; 221 | case 1: 222 | sprintf(buf, "CIC:%04x", *(uint16_t*)0x10080040); 223 | break; 224 | case 2: 225 | sprintf(buf, "FIR:%04x", *(uint16_t*)0x10088000); 226 | break; 227 | case 3: 228 | sprintf(buf, "DEM:%04x", *(uint16_t*)0x10089100); 229 | break; 230 | case 4: 231 | sprintf(buf, "AUD:%04x", *(uint16_t*)0x1008A000); 232 | break; 233 | case 5: 234 | sprintf(buf, "RBF:%d", audio_state.rebuffer_count); 235 | break; 236 | case 6: 237 | { 238 | uint16_t d = audio_state.write_current - audio_state.read_current; 239 | d %= AUDIO_BUFFER_SIZE / 2; 240 | sprintf(buf, "D:%d", d); 241 | break; 242 | } 243 | case 7: 244 | sprintf(buf, "CR:%d", fm_demod_state.carrier); 245 | break; 246 | case 8: 247 | sprintf(buf, "ST:%d", stereo_separate_state.corr); 248 | break; 249 | case 9: 250 | sprintf(buf, "SAV:%d", stereo_separate_state.corr_ave); 251 | break; 252 | case 10: 253 | sprintf(buf, "SSD:%d", stereo_separate_state.corr_std); 254 | break; 255 | #if 0 256 | case 11: 257 | sprintf(buf, "NA:%f", stereo_separate_state.carrier_i*stereo_separate_state.carrier_i+stereo_separate_state.carrier_q*stereo_separate_state.carrier_q); 258 | break; 259 | case 12: 260 | sprintf(buf, "SA:%f", stereo_separate_state.step_cos*stereo_separate_state.step_cos+stereo_separate_state.step_sin*stereo_separate_state.step_sin); 261 | break; 262 | #else 263 | case 11: 264 | sprintf(buf, "SI%d", stereo_separate_state.sdi); 265 | break; 266 | case 12: 267 | sprintf(buf, "SQ%d", stereo_separate_state.sdq); 268 | break; 269 | #endif 270 | case 13: 271 | sprintf(buf, "OFS:%04x", cic_i.dc_offset & 0xffff); 272 | break; 273 | default: 274 | sprintf(buf, "undef"); 275 | break; 276 | } 277 | break; 278 | case DEBUGMODE: 279 | switch (UISTAT->debugmode) { 280 | case 0: 281 | sprintf(buf, "DMA:RUN"); 282 | break; 283 | case 1: 284 | sprintf(buf, "DMA:HALT"); 285 | break; 286 | case 2: 287 | sprintf(buf, "DMA:TONE"); 288 | break; 289 | } 290 | break; 291 | default: 292 | return; 293 | } 294 | i2clcd_pos(0, 1); 295 | i2clcd_str(buf); 296 | i2clcd_str(" "); 297 | 298 | if (stereo_separate_state.corr_std < 1000) { 299 | ROTLED_GREEN(); 300 | } else if (fm_demod_state.carrier > 10000) { 301 | ROTLED_RED(); 302 | } else { 303 | ROTLED_OFF(); 304 | } 305 | } 306 | 307 | void 308 | ui_init() 309 | { 310 | scu_pinmux(1, 7, GPIO_PUP, FUNC0); // GPIO1-0 311 | scu_pinmux(1, 8, GPIO_PUP, FUNC0); // GPIO1-1 312 | scu_pinmux(1, 9, GPIO_PUP, FUNC0); // GPIO1-2 313 | LED_INIT(); 314 | ROTLED_INIT(); 315 | 316 | i2clcd_init(); 317 | i2clcd_str("HelloSDR"); 318 | 319 | UISTAT->mode = CHANNEL; 320 | UISTAT->gain = 10; 321 | UISTAT->channel = 1; 322 | UISTAT->freq = 82500000; 323 | UISTAT->modulation = MOD_LSB; 324 | UISTAT->digit = 5; 325 | UISTAT->agcmode = 0; 326 | UISTAT->rfgain = 0; 327 | UISTAT->spdispmode = SPDISP_RESAMP; 328 | UISTAT->tp = 0; 329 | UISTAT->debugmode = 0; 330 | ui_update(); 331 | 332 | nco_set_frequency(UISTAT->freq); 333 | audio_set_gain(UISTAT->gain); 334 | } 335 | 336 | void 337 | ui_process() 338 | { 339 | int status = btn_check(); 340 | if (status != 0) { 341 | if (status & EVT_BUTTON_SINGLE_CLICK) { 342 | UISTAT->mode = (UISTAT->mode + 1) % MODE_MAX; 343 | } else if (UISTAT->mode == GAIN) { 344 | if ((status & ENCODER_UP) && UISTAT->gain < AUDIO_GAIN_MAX) 345 | UISTAT->gain++; 346 | if ((status & ENCODER_DOWN) && UISTAT->gain > AUDIO_GAIN_MIN) 347 | UISTAT->gain--; 348 | audio_set_gain(UISTAT->gain); 349 | } else if (UISTAT->mode == FREQ) { 350 | if ((status & ENCODER_UP)) 351 | UISTAT->freq += FREQ_STEP; 352 | if ((status & ENCODER_DOWN)) 353 | UISTAT->freq -= FREQ_STEP; 354 | nco_set_frequency(UISTAT->freq); 355 | } else if (UISTAT->mode == CHANNEL) { 356 | if ((status & ENCODER_UP) && UISTAT->channel < CHANNEL_MAX) { 357 | UISTAT->channel++; 358 | UISTAT->freq = channel_freqs[UISTAT->channel]; 359 | nco_set_frequency(UISTAT->freq); 360 | } 361 | if ((status & ENCODER_DOWN) && UISTAT->channel > 0) { 362 | UISTAT->channel--; 363 | UISTAT->freq = channel_freqs[UISTAT->channel]; 364 | nco_set_frequency(UISTAT->freq); 365 | } 366 | } else if (UISTAT->mode == SPDISP) { 367 | if ((status & ENCODER_UP) && UISTAT->spdispmode < SPDISP_MODE_MAX-1) { 368 | UISTAT->spdispmode++; 369 | } 370 | if ((status & ENCODER_DOWN) && UISTAT->spdispmode > 0) { 371 | UISTAT->spdispmode--; 372 | } 373 | SPDISPINFO->ui_update_flag = TRUE; 374 | } else if (UISTAT->mode == TESTP) { 375 | if (status & ENCODER_UP) 376 | UISTAT->tp++; 377 | if (status & ENCODER_DOWN) 378 | UISTAT->tp--; 379 | UISTAT->tp &= TP_MAX-1; // assume 2^n 380 | } else if (UISTAT->mode == DEBUGMODE) { 381 | if ((status & ENCODER_UP) && UISTAT->debugmode < 2) { 382 | UISTAT->debugmode++; 383 | DMA_HALT(); 384 | if (UISTAT->debugmode == 2) { 385 | generate_test_tone(1000.0f); 386 | } 387 | } 388 | if ((status & ENCODER_DOWN) && UISTAT->debugmode > 0) { 389 | UISTAT->debugmode--; 390 | if (UISTAT->debugmode == 0) 391 | DMA_RUN(); 392 | } 393 | } 394 | SPDISPINFO->ui_update_flag = TRUE; 395 | ui_update(); 396 | } else if (capture_count % 512 == 0) { 397 | ui_update(); 398 | //update_adc_dc_offset(); 399 | } 400 | 401 | //systick_delay(1); 402 | } 403 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | LPC4370 SDR - Standalone SDR experiment using multicore MCU - FM version 2 | ========================================================== 3 | 4 |

5 |

6 |

7 | 8 | # About 9 | 10 | MCU based Standalone SDR implementation with LCD using multicore and integrated high speed ADC. 11 | 12 | This project is derived from article of Interface magazine (Aug 2016) from CQ publishing. 13 | 14 | 15 | # Prerequisite 16 | 17 | * Hardware 18 | * LPC-Link2 19 | * I2S Codec & LCD daughterboard 20 | * IDE 21 | * LPCXpresso 22 | 23 | # How to build 24 | 25 | Launch lpcxpresso, activate free edition. 26 | 27 | ## Import libraries 28 | 29 | Import projects to workspace from Quickstart pane. 30 | 31 | * CMSIS_DSPLIB_CM0 32 | * CMSIS_DSPLIB_CM4 33 | * CMSIS_LPC43xx_DriverLib 34 | * CMSIS_LPC43xx_DriverLib-M0 35 | 36 | ## Import projects 37 | 38 | Download .zip, and import it to workspace. 39 | 40 | ## Build projects 41 | 42 | Build each project. 43 | 44 | * DisplayM0APP (M0 App core) 45 | * FMReceiverMC (M4) 46 | -------------------------------------------------------------------------------- /doc/LPC-Link2-FM.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ttrftech/LPC4370SDR-FM/f4b11a885d03bbaec9e8f1aa710d511d870baf32/doc/LPC-Link2-FM.jpg --------------------------------------------------------------------------------