├── .gitignore ├── Img ├── logic.png └── logic2.png ├── LICENSE ├── README.md └── stm32_i2c_slave_example ├── .cproject ├── .project ├── Core ├── Inc │ ├── i2c_slave.h │ ├── main.h │ ├── protocol.h │ ├── registers.h │ ├── stm32f3xx_hal_conf.h │ └── stm32f3xx_it.h ├── Src │ ├── i2c_slave.c │ ├── main.c │ ├── protocol.c │ ├── registers.c │ ├── stm32f3xx_hal_msp.c │ ├── stm32f3xx_it.c │ ├── syscalls.c │ ├── sysmem.c │ └── system_stm32f3xx.c └── Startup │ └── startup_stm32f303retx.s ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F3xx │ │ │ ├── Include │ │ │ ├── stm32f303xe.h │ │ │ ├── stm32f3xx.h │ │ │ └── system_stm32f3xx.h │ │ │ └── License.md │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ └── LICENSE.txt └── STM32F3xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32f3xx_hal.h │ ├── stm32f3xx_hal_cortex.h │ ├── stm32f3xx_hal_def.h │ ├── stm32f3xx_hal_dma.h │ ├── stm32f3xx_hal_dma_ex.h │ ├── stm32f3xx_hal_exti.h │ ├── stm32f3xx_hal_flash.h │ ├── stm32f3xx_hal_flash_ex.h │ ├── stm32f3xx_hal_gpio.h │ ├── stm32f3xx_hal_gpio_ex.h │ ├── stm32f3xx_hal_i2c.h │ ├── stm32f3xx_hal_i2c_ex.h │ ├── stm32f3xx_hal_pwr.h │ ├── stm32f3xx_hal_pwr_ex.h │ ├── stm32f3xx_hal_rcc.h │ ├── stm32f3xx_hal_rcc_ex.h │ ├── stm32f3xx_hal_tim.h │ └── stm32f3xx_hal_tim_ex.h │ ├── License.md │ └── Src │ ├── stm32f3xx_hal.c │ ├── stm32f3xx_hal_cortex.c │ ├── stm32f3xx_hal_dma.c │ ├── stm32f3xx_hal_exti.c │ ├── stm32f3xx_hal_flash.c │ ├── stm32f3xx_hal_flash_ex.c │ ├── stm32f3xx_hal_gpio.c │ ├── stm32f3xx_hal_i2c.c │ ├── stm32f3xx_hal_i2c_ex.c │ ├── stm32f3xx_hal_pwr.c │ ├── stm32f3xx_hal_pwr_ex.c │ ├── stm32f3xx_hal_rcc.c │ ├── stm32f3xx_hal_rcc_ex.c │ ├── stm32f3xx_hal_tim.c │ └── stm32f3xx_hal_tim_ex.c ├── STM32F303RETX_FLASH.ld └── stm32_i2c_slave_example.ioc /.gitignore: -------------------------------------------------------------------------------- 1 | stm32_i2c_slave_example/.mxproject 2 | stm32_i2c_slave_example/Debug/** 3 | stm32_i2c_slave_example/.settings/ 4 | stm32_i2c_slave_example/Release/** 5 | 6 | -------------------------------------------------------------------------------- /Img/logic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tunerok/stm32_i2c_slave_examlpe/41a83ece599918cc8536a5752978397f2574ee68/Img/logic.png -------------------------------------------------------------------------------- /Img/logic2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tunerok/stm32_i2c_slave_examlpe/41a83ece599918cc8536a5752978397f2574ee68/Img/logic2.png -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Artem Ashirov 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ### stm32_i2c_slave_examlpe 2 | 3 | 4 | ``` 5 | root@orangepione:~# i2cdetect -y 2 6 | 0 1 2 3 4 5 6 7 8 9 a b c d e f 7 | 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 8 | 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 | 20: -- 44 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 | 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 11 | 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 | 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 13 | 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 14 | 70: -- -- -- -- -- -- -- -- 15 | root@orangepione:~# i2cget -y 2 0x44 0x00 16 | 0x01 17 | root@orangepione:~# i2cget -y 2 0x44 0x01 w 18 | 0x0000 19 | root@orangepione:~# i2cget -y 2 0x44 0x11 w 20 | 0x3344 21 | root@orangepione:~# i2cset -y 2 0x44 0x01 0x0055 w 22 | root@orangepione:~# i2cget -y 2 0x44 0x01 w 23 | 0x0055 24 | root@orangepione:~# i2cget -y 2 0x44 0x11 w 25 | 0x3345 26 | ``` 27 | 28 | 29 | **i2cset -y 2 0x44 0x01 0x0055 w** 30 | ![Logic](Img/logic.png) 31 | 32 | **i2cget -y 2 0x44 0x01 w** 33 | ![Logic](Img/logic2.png) 34 | 35 | What was really hard to find was an adequate example of implementing an i2c slave on STM32 using interrupts. There were several examples of blocking implementations and a couple of questions on st-community. 36 | 37 | But a more or less working project, where there is an implementation of **several** registers of the slave device, and even with a **different level of access** - this was very lacking. 38 | 39 | In general, I reached the bottom of the comedy. I liked how it worked on **mbedOS**, so I got into the sources (https://github.com/ARMmbed/mbed-os and https://github.com/ARMmbed/mbed-hal). And he began to read the code sadly and sweepingly cut unnecessary dependencies. 40 | 41 | The operating logic is as follows - there are interrupt handlers in the current ones, the main work of which is related to reading and setting records in the registers of the slave device. In the main program loop, only the line is checked for errors and dependency status. 42 | 43 | In general, we got a small example, more or less universal for STM32 devices. This project was made for the most popular **Nucleo-F303RE** debug board on Aliexpress. 44 | 45 | Checked on STM32L433, STM32F302R8 46 | 47 | *** 48 | 49 | Вот что действительно было тяжело найти, так это адекватный пример реализации i2c подчиненного устройства на STM32 с использованием прерываний. Нашлись несколько примеров блокирующих реализаций и пара вопросов на st-community. 50 | 51 | А вот более-менее рабочий проект, где есть реализация **нескольких** регистров ведомого устройства, да еще и с **разным уровнем доступа** – такого очень не хватало. 52 | 53 | В общем, я достиг комедии дна. Мне понравилось, как работало на **mbedOS**, поэтому, я полез в исходники (https://github.com/ARMmbed/mbed-os и https://github.com/ARMmbed/mbed-hal). И начал грустно вычитывать код и размашисто резать лишние зависимости. 54 | 55 | Логика работы следующая – есть обработчики прерываний в которых происходит основная работа связанная с чтением и установкой значений в регистры подчиненного устройства. В основном цикле программы происходит лишь проверка линии на ошибки и состояние зависания. 56 | 57 | В общем, получился небольшой пример, более-менее универсальный для STM32-устройств. Данный проект сделан для самой популярной на Алиэкспесс платы-отладки **Nucleo-F303RE** 58 | 59 | Проверено на STM32L433, STM32F302R8 60 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | stm32_i2c_slave_example 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | com.st.stm32cube.ide.mcu.MCUProjectNature 23 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature 24 | org.eclipse.cdt.core.cnature 25 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature 26 | com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature 27 | com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature 28 | com.st.stm32cube.ide.mcu.MCURootProjectNature 29 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 30 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 31 | 32 | 33 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Inc/i2c_slave.h: -------------------------------------------------------------------------------- 1 | #ifndef INC_I2C_SLAVE_H_ 2 | #define INC_I2C_SLAVE_H_ 3 | 4 | #include "main.h" 5 | #include "registers.h" 6 | 7 | //Change this, or write your OWN 1us delay func (i2c_slave.c inside) 8 | #define SYSTICKCLOCK 80000000ULL 9 | #define SYSTICKPERUS (SYSTICKCLOCK / 1000000UL) 10 | #define BYTE_TIMEOUT_US (SYSTICKPERUS * 3 * 10) 11 | 12 | #define I2C_RX_BUSY_CNTR 150 13 | 14 | 15 | typedef struct i2c_s { 16 | volatile reg_idx_t curr_idx; 17 | volatile uint8_t reg_addr_rcvd; 18 | volatile uint8_t reg_address; 19 | volatile uint8_t ready_to_answer; 20 | volatile uint8_t ready_to_write; 21 | I2C_HandleTypeDef *i2c_handler; 22 | }i2c_t; 23 | 24 | 25 | 26 | int i2c_slave_init(I2C_HandleTypeDef *hi2c); 27 | void i2c_slave_check_timeout(void); 28 | 29 | 30 | #endif /* INC_I2C_SLAVE_H_ */ 31 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2022 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __MAIN_H 23 | #define __MAIN_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f3xx_hal.h" 31 | 32 | /* Private includes ----------------------------------------------------------*/ 33 | /* USER CODE BEGIN Includes */ 34 | 35 | /* USER CODE END Includes */ 36 | 37 | /* Exported types ------------------------------------------------------------*/ 38 | /* USER CODE BEGIN ET */ 39 | 40 | /* USER CODE END ET */ 41 | 42 | /* Exported constants --------------------------------------------------------*/ 43 | /* USER CODE BEGIN EC */ 44 | 45 | /* USER CODE END EC */ 46 | 47 | /* Exported macro ------------------------------------------------------------*/ 48 | /* USER CODE BEGIN EM */ 49 | 50 | /* USER CODE END EM */ 51 | 52 | /* Exported functions prototypes ---------------------------------------------*/ 53 | void Error_Handler(void); 54 | 55 | /* USER CODE BEGIN EFP */ 56 | 57 | /* USER CODE END EFP */ 58 | 59 | /* Private defines -----------------------------------------------------------*/ 60 | /* USER CODE BEGIN Private defines */ 61 | 62 | /* USER CODE END Private defines */ 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __MAIN_H */ 69 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Inc/protocol.h: -------------------------------------------------------------------------------- 1 | #ifndef INC_PROTOCOL_H_ 2 | #define INC_PROTOCOL_H_ 3 | 4 | #include 5 | #include "registers.h" 6 | #include "i2c_slave.h" 7 | 8 | //Data processing in registers 9 | void protocol_reg_ctrl(reg_idx_t idx); 10 | 11 | #endif /* INC_PROTOCOL_H_ */ 12 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Inc/registers.h: -------------------------------------------------------------------------------- 1 | #ifndef INC_REGISTERS_H_ 2 | #define INC_REGISTERS_H_ 3 | 4 | #include 5 | 6 | //Register Addresses 7 | #define REG_VERSION_ADDR 0x00 8 | #define REG_UINT16_RW_ADDR 0x01 9 | #define REG_INT16_RW_ADDR 0x02 10 | #define REG_BOOL_RW_ADDR 0x03 11 | #define REG_CHAR_RW_ADDR 0x04 12 | #define REG_UINT16_RO_ADDR 0x11 13 | #define REG_INT16_RO_ADDR 0x12 14 | #define REG_BOOL_RO_ADDR 0x13 15 | #define REG_CHAR_RO_ADDR 0x14 16 | 17 | //Register value types 18 | typedef enum val_type_t { 19 | EMPTY, 20 | UNDEFINED, 21 | BOOL, 22 | UINT16, 23 | INT16, 24 | CHAR 25 | } val_type_t; 26 | 27 | 28 | //Register indices 29 | typedef enum reg_idx_t { 30 | NONE = -1, 31 | ECHO = 0, 32 | VERSION, 33 | UINT16_RW, 34 | INT16_RW, 35 | BOOL_RW, 36 | CHAR_RW, 37 | UINT16_RO, 38 | INT16_RO, 39 | BOOL_RO, 40 | CHAR_RO, 41 | REGISTER_NUM 42 | } reg_idx_t; 43 | 44 | //Access to registers 45 | typedef enum reg_mode_t { 46 | RESERVED = 0, 47 | WRITE_ONLY, 48 | READ_ONLY, 49 | FULL_ACCESS 50 | } reg_mode_t; 51 | 52 | //Type for register values 53 | typedef union var_t { 54 | uint8_t bool_val; 55 | uint16_t uint16_val; 56 | int16_t int16_val; 57 | char char_val; 58 | } var_t; 59 | 60 | 61 | //Register structure 62 | typedef struct reg_t reg_t; 63 | 64 | struct reg_t { 65 | uint8_t access; //Access 66 | uint8_t reg_addr; //Address 67 | val_type_t value_type; //Value type 68 | const var_t def_val; //Default values 69 | var_t value; //Current values 70 | }; 71 | 72 | 73 | reg_idx_t reg_get_idx(uint8_t address); 74 | void reg_factory(void); 75 | int reg_get_len(reg_idx_t idx); 76 | 77 | 78 | #endif 79 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Inc/stm32f3xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f3xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_IT_H 22 | #define __STM32F3xx_IT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Private includes ----------------------------------------------------------*/ 29 | /* USER CODE BEGIN Includes */ 30 | 31 | /* USER CODE END Includes */ 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN ET */ 35 | 36 | /* USER CODE END ET */ 37 | 38 | /* Exported constants --------------------------------------------------------*/ 39 | /* USER CODE BEGIN EC */ 40 | 41 | /* USER CODE END EC */ 42 | 43 | /* Exported macro ------------------------------------------------------------*/ 44 | /* USER CODE BEGIN EM */ 45 | 46 | /* USER CODE END EM */ 47 | 48 | /* Exported functions prototypes ---------------------------------------------*/ 49 | void NMI_Handler(void); 50 | void HardFault_Handler(void); 51 | void MemManage_Handler(void); 52 | void BusFault_Handler(void); 53 | void UsageFault_Handler(void); 54 | void SVC_Handler(void); 55 | void DebugMon_Handler(void); 56 | void PendSV_Handler(void); 57 | void SysTick_Handler(void); 58 | void I2C1_EV_IRQHandler(void); 59 | void I2C1_ER_IRQHandler(void); 60 | /* USER CODE BEGIN EFP */ 61 | 62 | /* USER CODE END EFP */ 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __STM32F3xx_IT_H */ 69 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/i2c_slave.c: -------------------------------------------------------------------------------- 1 | /* 2 | * i2c_slave.c 3 | * 4 | * Created on: Oct 14, 2022 5 | * Author: ashirov 6 | */ 7 | 8 | #include "i2c_slave.h" 9 | #include "registers.h" 10 | 11 | 12 | volatile i2c_t I2C_slave_obj; 13 | 14 | extern reg_t g_i2c_reg_data[]; 15 | 16 | // Delay has to constant expression 17 | static void inline __attribute__((always_inline)) delayus(unsigned us_mul_5) 18 | { 19 | uint32_t ticks = SYSTICKPERUS * us_mul_5; 20 | uint32_t start_tick = SysTick->VAL; 21 | 22 | while(SysTick->VAL - start_tick < ticks); 23 | } 24 | 25 | 26 | void i2c_slave_clear(void){ 27 | I2C_slave_obj.reg_address = 0; 28 | I2C_slave_obj.curr_idx = NONE; 29 | I2C_slave_obj.ready_to_answer = 0; 30 | I2C_slave_obj.ready_to_write = 0; 31 | 32 | } 33 | 34 | int i2c_slave_init(I2C_HandleTypeDef *hi2c){ 35 | I2C_slave_obj.i2c_handler = hi2c; 36 | i2c_slave_clear(); 37 | } 38 | 39 | static void ResetI2C(I2C_HandleTypeDef* rev_i2c){ 40 | HAL_I2C_DeInit(rev_i2c); 41 | HAL_I2C_Init(rev_i2c); 42 | } 43 | 44 | 45 | void i2c_slave_check_timeout(void){ 46 | 47 | static int rx_busy_counter = 0; 48 | HAL_I2C_StateTypeDef status = HAL_OK; 49 | 50 | status = HAL_I2C_GetState(I2C_slave_obj.i2c_handler); 51 | 52 | if (status == HAL_I2C_STATE_BUSY_RX_LISTEN){ 53 | rx_busy_counter++; 54 | } 55 | else{ 56 | rx_busy_counter = 0; 57 | } 58 | 59 | if (rx_busy_counter > I2C_RX_BUSY_CNTR){ 60 | HAL_I2C_DisableListen_IT(I2C_slave_obj.i2c_handler); 61 | HAL_I2C_DeInit(I2C_slave_obj.i2c_handler); 62 | HAL_I2C_Init(I2C_slave_obj.i2c_handler); 63 | HAL_I2C_EnableListen_IT(I2C_slave_obj.i2c_handler); 64 | rx_busy_counter = 0; 65 | } 66 | } 67 | 68 | //****************** 69 | //-------i2c-------- 70 | //****************** 71 | 72 | 73 | void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode){ 74 | UNUSED(AddrMatchCode); 75 | // Если мастер пишет, слушаем необходимое количество байт 76 | if(TransferDirection == I2C_DIRECTION_TRANSMIT){ 77 | // Первый запрос на запись всегда составляет 1 байт запрошенного регистрового адреса. 78 | // Сохранить его в I2C_slave_obj.reg_address 79 | if(!I2C_slave_obj.reg_addr_rcvd) 80 | HAL_I2C_Slave_Sequential_Receive_IT(hi2c, &I2C_slave_obj.reg_address, 1, I2C_FIRST_FRAME); 81 | } 82 | else { 83 | // Если мастер отправляет запрос на чтение, вернуть значение данных в запрошенном регистре. 84 | I2C_slave_obj.curr_idx = reg_get_idx(I2C_slave_obj.reg_address); 85 | if ((I2C_slave_obj.curr_idx != NONE)&& (I2C_slave_obj.curr_idx != ECHO)&& (g_i2c_reg_data[I2C_slave_obj.curr_idx].access != WRITE_ONLY)){ 86 | HAL_I2C_Slave_Sequential_Transmit_IT(hi2c, (uint8_t*)&g_i2c_reg_data[I2C_slave_obj.curr_idx].value.uint16_val, reg_get_len(I2C_slave_obj.curr_idx), I2C_LAST_FRAME); 87 | } 88 | } 89 | } 90 | 91 | void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c){ 92 | // Это вызывается после основного запроса на запись. в первый раз это будет адрес регистра. 93 | // Второй раз, если это запрос на запись, это будет полезная нагрузка 94 | if(!I2C_slave_obj.reg_addr_rcvd){ 95 | // Если reg_addr_rcvd имеет значение false, это означает, что мастер ждет данные 96 | I2C_slave_obj.reg_addr_rcvd = 1; 97 | I2C_slave_obj.curr_idx = reg_get_idx(I2C_slave_obj.reg_address); 98 | if ((I2C_slave_obj.curr_idx != NONE)&& (I2C_slave_obj.curr_idx != ECHO)&& (g_i2c_reg_data[I2C_slave_obj.curr_idx].access != READ_ONLY)){ 99 | HAL_I2C_Slave_Sequential_Receive_IT(hi2c, (uint8_t*)&g_i2c_reg_data[I2C_slave_obj.curr_idx].value.uint16_val, reg_get_len(I2C_slave_obj.curr_idx), I2C_NEXT_FRAME); 100 | } 101 | } else { 102 | // Если reg_addr_rcvd установлен, это означает, что этот обратный вызов был возвращен после получения данных регистра 103 | I2C_slave_obj.reg_addr_rcvd = 0; 104 | //добавим быструю обработку 105 | protocol_reg_ctrl(I2C_slave_obj.curr_idx); 106 | I2C_slave_obj.curr_idx = NONE; 107 | 108 | 109 | } 110 | HAL_I2C_EnableListen_IT(hi2c); 111 | } 112 | 113 | void HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c){ 114 | HAL_I2C_EnableListen_IT(hi2c); 115 | } 116 | 117 | void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c){ 118 | I2C_slave_obj.reg_addr_rcvd = 0; 119 | HAL_I2C_EnableListen_IT(hi2c); 120 | } 121 | 122 | void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) 123 | { 124 | //HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ 125 | //HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ 126 | //HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ 127 | //HAL_I2C_ERROR_AF 0x00000004U /*!< Ack Failure error */ 128 | //HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ 129 | //HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ 130 | //HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ 131 | uint32_t error_code = HAL_I2C_GetError(hi2c); 132 | if (error_code != HAL_I2C_ERROR_AF){} 133 | HAL_I2C_EnableListen_IT(hi2c); 134 | } 135 | 136 | 137 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "main.h" 21 | 22 | /* Private includes ----------------------------------------------------------*/ 23 | /* USER CODE BEGIN Includes */ 24 | #include "i2c_slave.h" 25 | #include "protocol.h" 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN PTD */ 30 | 31 | /* USER CODE END PTD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN PD */ 35 | 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | int i2c_event = 0; 42 | 43 | /* USER CODE END PM */ 44 | 45 | /* Private variables ---------------------------------------------------------*/ 46 | I2C_HandleTypeDef hi2c1; 47 | 48 | /* USER CODE BEGIN PV */ 49 | 50 | /* USER CODE END PV */ 51 | 52 | /* Private function prototypes -----------------------------------------------*/ 53 | void SystemClock_Config(void); 54 | static void MX_GPIO_Init(void); 55 | static void MX_I2C1_Init(void); 56 | /* USER CODE BEGIN PFP */ 57 | 58 | /* USER CODE END PFP */ 59 | 60 | /* Private user code ---------------------------------------------------------*/ 61 | /* USER CODE BEGIN 0 */ 62 | 63 | /* USER CODE END 0 */ 64 | 65 | /** 66 | * @brief The application entry point. 67 | * @retval int 68 | */ 69 | int main(void) 70 | { 71 | /* USER CODE BEGIN 1 */ 72 | 73 | /* USER CODE END 1 */ 74 | 75 | /* MCU Configuration--------------------------------------------------------*/ 76 | 77 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 78 | HAL_Init(); 79 | 80 | /* USER CODE BEGIN Init */ 81 | 82 | /* USER CODE END Init */ 83 | 84 | /* Configure the system clock */ 85 | SystemClock_Config(); 86 | 87 | /* USER CODE BEGIN SysInit */ 88 | 89 | /* USER CODE END SysInit */ 90 | 91 | /* Initialize all configured peripherals */ 92 | MX_GPIO_Init(); 93 | MX_I2C1_Init(); 94 | /* USER CODE BEGIN 2 */ 95 | 96 | //Restoring regs factory settings 97 | reg_factory(); 98 | //Init i2c-slave 99 | i2c_slave_init(&hi2c1); 100 | //Start i2c irq 101 | HAL_I2C_EnableListen_IT(&hi2c1); 102 | /* USER CODE END 2 */ 103 | 104 | /* Infinite loop */ 105 | /* USER CODE BEGIN WHILE */ 106 | while (1) 107 | { 108 | 109 | //i2c bus hang check 110 | i2c_slave_check_timeout(); 111 | 112 | 113 | /* USER CODE END WHILE */ 114 | 115 | /* USER CODE BEGIN 3 */ 116 | } 117 | /* USER CODE END 3 */ 118 | } 119 | 120 | /** 121 | * @brief System Clock Configuration 122 | * @retval None 123 | */ 124 | void SystemClock_Config(void) 125 | { 126 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 127 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 128 | RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 129 | 130 | /** Initializes the RCC Oscillators according to the specified parameters 131 | * in the RCC_OscInitTypeDef structure. 132 | */ 133 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 134 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; 135 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 136 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 137 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 138 | { 139 | Error_Handler(); 140 | } 141 | 142 | /** Initializes the CPU, AHB and APB buses clocks 143 | */ 144 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 145 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 146 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 147 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 148 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 149 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 150 | 151 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 152 | { 153 | Error_Handler(); 154 | } 155 | PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 156 | PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 157 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 158 | { 159 | Error_Handler(); 160 | } 161 | } 162 | 163 | /** 164 | * @brief I2C1 Initialization Function 165 | * @param None 166 | * @retval None 167 | */ 168 | static void MX_I2C1_Init(void) 169 | { 170 | 171 | /* USER CODE BEGIN I2C1_Init 0 */ 172 | 173 | /* USER CODE END I2C1_Init 0 */ 174 | 175 | /* USER CODE BEGIN I2C1_Init 1 */ 176 | 177 | /* USER CODE END I2C1_Init 1 */ 178 | hi2c1.Instance = I2C1; 179 | hi2c1.Init.Timing = 0x0000020B; 180 | hi2c1.Init.OwnAddress1 = 136; 181 | hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 182 | hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 183 | hi2c1.Init.OwnAddress2 = 0; 184 | hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 185 | hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 186 | hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 187 | if (HAL_I2C_Init(&hi2c1) != HAL_OK) 188 | { 189 | Error_Handler(); 190 | } 191 | 192 | /** Configure Analogue filter 193 | */ 194 | if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 195 | { 196 | Error_Handler(); 197 | } 198 | 199 | /** Configure Digital filter 200 | */ 201 | if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 202 | { 203 | Error_Handler(); 204 | } 205 | /* USER CODE BEGIN I2C1_Init 2 */ 206 | 207 | /* USER CODE END I2C1_Init 2 */ 208 | 209 | } 210 | 211 | /** 212 | * @brief GPIO Initialization Function 213 | * @param None 214 | * @retval None 215 | */ 216 | static void MX_GPIO_Init(void) 217 | { 218 | 219 | /* GPIO Ports Clock Enable */ 220 | __HAL_RCC_GPIOA_CLK_ENABLE(); 221 | __HAL_RCC_GPIOB_CLK_ENABLE(); 222 | 223 | } 224 | 225 | /* USER CODE BEGIN 4 */ 226 | 227 | /* USER CODE END 4 */ 228 | 229 | /** 230 | * @brief This function is executed in case of error occurrence. 231 | * @retval None 232 | */ 233 | void Error_Handler(void) 234 | { 235 | /* USER CODE BEGIN Error_Handler_Debug */ 236 | /* User can add his own implementation to report the HAL error return state */ 237 | __disable_irq(); 238 | while (1) 239 | { 240 | } 241 | /* USER CODE END Error_Handler_Debug */ 242 | } 243 | 244 | #ifdef USE_FULL_ASSERT 245 | /** 246 | * @brief Reports the name of the source file and the source line number 247 | * where the assert_param error has occurred. 248 | * @param file: pointer to the source file name 249 | * @param line: assert_param error line source number 250 | * @retval None 251 | */ 252 | void assert_failed(uint8_t *file, uint32_t line) 253 | { 254 | /* USER CODE BEGIN 6 */ 255 | /* User can add his own implementation to report the file name and line number, 256 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 257 | /* USER CODE END 6 */ 258 | } 259 | #endif /* USE_FULL_ASSERT */ 260 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/protocol.c: -------------------------------------------------------------------------------- 1 | #include "protocol.h" 2 | 3 | extern reg_t g_i2c_reg_data[]; 4 | 5 | void protocol_reg_ctrl(reg_idx_t idx){ 6 | switch (idx){ 7 | case UINT16_RW: 8 | g_i2c_reg_data[UINT16_RO].value.uint16_val++; 9 | break; 10 | case INT16_RW: 11 | g_i2c_reg_data[INT16_RO].value.int16_val++; 12 | break; 13 | default: 14 | break; 15 | } 16 | } 17 | 18 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/registers.c: -------------------------------------------------------------------------------- 1 | #include "registers.h" 2 | 3 | volatile reg_t g_i2c_reg_data[] = 4 | { 5 | [VERSION] = { READ_ONLY, REG_VERSION_ADDR, CHAR, {.char_val = 0x01}, {0} }, 6 | [UINT16_RW] = { FULL_ACCESS, REG_UINT16_RW_ADDR, UINT16, {.uint16_val = 0x00}, {0} }, 7 | [INT16_RW] = { FULL_ACCESS, REG_INT16_RW_ADDR, INT16, {.int16_val = 0x00}, {0} }, 8 | [BOOL_RW] = { FULL_ACCESS, REG_BOOL_RW_ADDR, BOOL, {.bool_val = 0x00}, {0} }, 9 | [CHAR_RW] = { FULL_ACCESS, REG_CHAR_RW_ADDR, CHAR, {.char_val = 0x00}, {0} }, 10 | [UINT16_RO] = { READ_ONLY, REG_UINT16_RO_ADDR, UINT16, {.uint16_val = 0x3344}, {0} }, 11 | [INT16_RO] = { READ_ONLY, REG_INT16_RO_ADDR, INT16, {.int16_val = 0x2233}, {0} }, 12 | [BOOL_RO] = { READ_ONLY, REG_BOOL_RO_ADDR, BOOL, {.bool_val = 0x01}, {0} }, 13 | [CHAR_RO] = { READ_ONLY, REG_CHAR_RO_ADDR, CHAR, {.char_val = 0x15}, {0} }, 14 | }; 15 | 16 | reg_idx_t reg_get_idx(uint8_t address){ 17 | for(int i = 1; i < REGISTER_NUM; i++){ 18 | if (g_i2c_reg_data[i].reg_addr == address){ 19 | return i; 20 | } 21 | } 22 | return NONE; 23 | } 24 | 25 | int reg_get_len(reg_idx_t idx){ 26 | int data_len = 0; 27 | switch (g_i2c_reg_data[idx].value_type){ 28 | case BOOL: 29 | case CHAR: 30 | data_len = 1; 31 | break; 32 | case UINT16: 33 | case INT16: 34 | data_len = 2; 35 | break; 36 | default: 37 | break; 38 | } 39 | return data_len; 40 | } 41 | 42 | 43 | //Restoring factory settings 44 | void reg_factory(void) { 45 | for (int idx = 1; idx < REGISTER_NUM - 1; idx++) { 46 | reg_idx_t reg_idx = idx; 47 | switch (g_i2c_reg_data[reg_idx].value_type) { 48 | case UNDEFINED: 49 | break; 50 | case BOOL: 51 | g_i2c_reg_data[reg_idx].value.bool_val = 52 | g_i2c_reg_data[reg_idx].def_val.bool_val; 53 | break; 54 | case UINT16: 55 | g_i2c_reg_data[reg_idx].value.uint16_val = 56 | g_i2c_reg_data[reg_idx].def_val.uint16_val; 57 | break; 58 | case INT16: 59 | g_i2c_reg_data[reg_idx].value.int16_val = 60 | g_i2c_reg_data[reg_idx].def_val.int16_val; 61 | break; 62 | case CHAR: 63 | g_i2c_reg_data[reg_idx].value.char_val = 64 | g_i2c_reg_data[reg_idx].def_val.char_val; 65 | break; 66 | default: 67 | break; 68 | } 69 | } 70 | } 71 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/stm32f3xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f3xx_hal_msp.c 5 | * @brief This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2022 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | /* USER CODE BEGIN Includes */ 24 | 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN TD */ 29 | 30 | /* USER CODE END TD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN Define */ 34 | 35 | /* USER CODE END Define */ 36 | 37 | /* Private macro -------------------------------------------------------------*/ 38 | /* USER CODE BEGIN Macro */ 39 | 40 | /* USER CODE END Macro */ 41 | 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* USER CODE BEGIN PV */ 44 | 45 | /* USER CODE END PV */ 46 | 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* USER CODE BEGIN PFP */ 49 | 50 | /* USER CODE END PFP */ 51 | 52 | /* External functions --------------------------------------------------------*/ 53 | /* USER CODE BEGIN ExternalFunctions */ 54 | 55 | /* USER CODE END ExternalFunctions */ 56 | 57 | /* USER CODE BEGIN 0 */ 58 | 59 | /* USER CODE END 0 */ 60 | /** 61 | * Initializes the Global MSP. 62 | */ 63 | void HAL_MspInit(void) 64 | { 65 | /* USER CODE BEGIN MspInit 0 */ 66 | 67 | /* USER CODE END MspInit 0 */ 68 | 69 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 70 | __HAL_RCC_PWR_CLK_ENABLE(); 71 | 72 | /* System interrupt init*/ 73 | 74 | /* USER CODE BEGIN MspInit 1 */ 75 | 76 | /* USER CODE END MspInit 1 */ 77 | } 78 | 79 | /** 80 | * @brief I2C MSP Initialization 81 | * This function configures the hardware resources used in this example 82 | * @param hi2c: I2C handle pointer 83 | * @retval None 84 | */ 85 | void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) 86 | { 87 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 88 | if(hi2c->Instance==I2C1) 89 | { 90 | /* USER CODE BEGIN I2C1_MspInit 0 */ 91 | 92 | /* USER CODE END I2C1_MspInit 0 */ 93 | 94 | __HAL_RCC_GPIOA_CLK_ENABLE(); 95 | __HAL_RCC_GPIOB_CLK_ENABLE(); 96 | /**I2C1 GPIO Configuration 97 | PA15 ------> I2C1_SCL 98 | PB7 ------> I2C1_SDA 99 | */ 100 | GPIO_InitStruct.Pin = GPIO_PIN_15; 101 | GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 102 | GPIO_InitStruct.Pull = GPIO_NOPULL; 103 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 104 | GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 105 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 106 | 107 | GPIO_InitStruct.Pin = GPIO_PIN_7; 108 | GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 109 | GPIO_InitStruct.Pull = GPIO_NOPULL; 110 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 111 | GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 112 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 113 | 114 | /* Peripheral clock enable */ 115 | __HAL_RCC_I2C1_CLK_ENABLE(); 116 | /* I2C1 interrupt Init */ 117 | HAL_NVIC_SetPriority(I2C1_EV_IRQn, 0, 0); 118 | HAL_NVIC_EnableIRQ(I2C1_EV_IRQn); 119 | HAL_NVIC_SetPriority(I2C1_ER_IRQn, 0, 0); 120 | HAL_NVIC_EnableIRQ(I2C1_ER_IRQn); 121 | /* USER CODE BEGIN I2C1_MspInit 1 */ 122 | 123 | /* USER CODE END I2C1_MspInit 1 */ 124 | } 125 | 126 | } 127 | 128 | /** 129 | * @brief I2C MSP De-Initialization 130 | * This function freeze the hardware resources used in this example 131 | * @param hi2c: I2C handle pointer 132 | * @retval None 133 | */ 134 | void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) 135 | { 136 | if(hi2c->Instance==I2C1) 137 | { 138 | /* USER CODE BEGIN I2C1_MspDeInit 0 */ 139 | 140 | /* USER CODE END I2C1_MspDeInit 0 */ 141 | /* Peripheral clock disable */ 142 | __HAL_RCC_I2C1_CLK_DISABLE(); 143 | 144 | /**I2C1 GPIO Configuration 145 | PA15 ------> I2C1_SCL 146 | PB7 ------> I2C1_SDA 147 | */ 148 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15); 149 | 150 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); 151 | 152 | /* I2C1 interrupt DeInit */ 153 | HAL_NVIC_DisableIRQ(I2C1_EV_IRQn); 154 | HAL_NVIC_DisableIRQ(I2C1_ER_IRQn); 155 | /* USER CODE BEGIN I2C1_MspDeInit 1 */ 156 | 157 | /* USER CODE END I2C1_MspDeInit 1 */ 158 | } 159 | 160 | } 161 | 162 | /* USER CODE BEGIN 1 */ 163 | 164 | /* USER CODE END 1 */ 165 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/stm32f3xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f3xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | #include "stm32f3xx_it.h" 23 | /* Private includes ----------------------------------------------------------*/ 24 | /* USER CODE BEGIN Includes */ 25 | /* USER CODE END Includes */ 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* USER CODE BEGIN TD */ 29 | 30 | /* USER CODE END TD */ 31 | 32 | /* Private define ------------------------------------------------------------*/ 33 | /* USER CODE BEGIN PD */ 34 | 35 | /* USER CODE END PD */ 36 | 37 | /* Private macro -------------------------------------------------------------*/ 38 | /* USER CODE BEGIN PM */ 39 | 40 | /* USER CODE END PM */ 41 | 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* USER CODE BEGIN PV */ 44 | 45 | /* USER CODE END PV */ 46 | 47 | /* Private function prototypes -----------------------------------------------*/ 48 | /* USER CODE BEGIN PFP */ 49 | 50 | /* USER CODE END PFP */ 51 | 52 | /* Private user code ---------------------------------------------------------*/ 53 | /* USER CODE BEGIN 0 */ 54 | 55 | /* USER CODE END 0 */ 56 | 57 | /* External variables --------------------------------------------------------*/ 58 | extern I2C_HandleTypeDef hi2c1; 59 | /* USER CODE BEGIN EV */ 60 | 61 | /* USER CODE END EV */ 62 | 63 | /******************************************************************************/ 64 | /* Cortex-M4 Processor Interruption and Exception Handlers */ 65 | /******************************************************************************/ 66 | /** 67 | * @brief This function handles Non maskable interrupt. 68 | */ 69 | void NMI_Handler(void) 70 | { 71 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 72 | 73 | /* USER CODE END NonMaskableInt_IRQn 0 */ 74 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 75 | while (1) 76 | { 77 | } 78 | /* USER CODE END NonMaskableInt_IRQn 1 */ 79 | } 80 | 81 | /** 82 | * @brief This function handles Hard fault interrupt. 83 | */ 84 | void HardFault_Handler(void) 85 | { 86 | /* USER CODE BEGIN HardFault_IRQn 0 */ 87 | 88 | /* USER CODE END HardFault_IRQn 0 */ 89 | while (1) 90 | { 91 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 92 | /* USER CODE END W1_HardFault_IRQn 0 */ 93 | } 94 | } 95 | 96 | /** 97 | * @brief This function handles Memory management fault. 98 | */ 99 | void MemManage_Handler(void) 100 | { 101 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 102 | 103 | /* USER CODE END MemoryManagement_IRQn 0 */ 104 | while (1) 105 | { 106 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 107 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 108 | } 109 | } 110 | 111 | /** 112 | * @brief This function handles Pre-fetch fault, memory access fault. 113 | */ 114 | void BusFault_Handler(void) 115 | { 116 | /* USER CODE BEGIN BusFault_IRQn 0 */ 117 | 118 | /* USER CODE END BusFault_IRQn 0 */ 119 | while (1) 120 | { 121 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 122 | /* USER CODE END W1_BusFault_IRQn 0 */ 123 | } 124 | } 125 | 126 | /** 127 | * @brief This function handles Undefined instruction or illegal state. 128 | */ 129 | void UsageFault_Handler(void) 130 | { 131 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 132 | 133 | /* USER CODE END UsageFault_IRQn 0 */ 134 | while (1) 135 | { 136 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 137 | /* USER CODE END W1_UsageFault_IRQn 0 */ 138 | } 139 | } 140 | 141 | /** 142 | * @brief This function handles System service call via SWI instruction. 143 | */ 144 | void SVC_Handler(void) 145 | { 146 | /* USER CODE BEGIN SVCall_IRQn 0 */ 147 | 148 | /* USER CODE END SVCall_IRQn 0 */ 149 | /* USER CODE BEGIN SVCall_IRQn 1 */ 150 | 151 | /* USER CODE END SVCall_IRQn 1 */ 152 | } 153 | 154 | /** 155 | * @brief This function handles Debug monitor. 156 | */ 157 | void DebugMon_Handler(void) 158 | { 159 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 160 | 161 | /* USER CODE END DebugMonitor_IRQn 0 */ 162 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 163 | 164 | /* USER CODE END DebugMonitor_IRQn 1 */ 165 | } 166 | 167 | /** 168 | * @brief This function handles Pendable request for system service. 169 | */ 170 | void PendSV_Handler(void) 171 | { 172 | /* USER CODE BEGIN PendSV_IRQn 0 */ 173 | 174 | /* USER CODE END PendSV_IRQn 0 */ 175 | /* USER CODE BEGIN PendSV_IRQn 1 */ 176 | 177 | /* USER CODE END PendSV_IRQn 1 */ 178 | } 179 | 180 | /** 181 | * @brief This function handles System tick timer. 182 | */ 183 | void SysTick_Handler(void) 184 | { 185 | /* USER CODE BEGIN SysTick_IRQn 0 */ 186 | 187 | /* USER CODE END SysTick_IRQn 0 */ 188 | HAL_IncTick(); 189 | /* USER CODE BEGIN SysTick_IRQn 1 */ 190 | 191 | /* USER CODE END SysTick_IRQn 1 */ 192 | } 193 | 194 | /******************************************************************************/ 195 | /* STM32F3xx Peripheral Interrupt Handlers */ 196 | /* Add here the Interrupt Handlers for the used peripherals. */ 197 | /* For the available peripheral interrupt handler names, */ 198 | /* please refer to the startup file (startup_stm32f3xx.s). */ 199 | /******************************************************************************/ 200 | 201 | /** 202 | * @brief This function handles I2C1 event global interrupt / I2C1 wake-up interrupt through EXTI line 23. 203 | */ 204 | void I2C1_EV_IRQHandler(void) 205 | { 206 | /* USER CODE BEGIN I2C1_EV_IRQn 0 */ 207 | 208 | /* USER CODE END I2C1_EV_IRQn 0 */ 209 | HAL_I2C_EV_IRQHandler(&hi2c1); 210 | /* USER CODE BEGIN I2C1_EV_IRQn 1 */ 211 | 212 | /* USER CODE END I2C1_EV_IRQn 1 */ 213 | } 214 | 215 | /** 216 | * @brief This function handles I2C1 error interrupt. 217 | */ 218 | void I2C1_ER_IRQHandler(void) 219 | { 220 | /* USER CODE BEGIN I2C1_ER_IRQn 0 */ 221 | 222 | /* USER CODE END I2C1_ER_IRQn 0 */ 223 | HAL_I2C_ER_IRQHandler(&hi2c1); 224 | /* USER CODE BEGIN I2C1_ER_IRQn 1 */ 225 | 226 | /* USER CODE END I2C1_ER_IRQn 1 */ 227 | } 228 | 229 | /* USER CODE BEGIN 1 */ 230 | 231 | /* USER CODE END 1 */ 232 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | 33 | 34 | /* Variables */ 35 | extern int __io_putchar(int ch) __attribute__((weak)); 36 | extern int __io_getchar(void) __attribute__((weak)); 37 | 38 | 39 | char *__env[1] = { 0 }; 40 | char **environ = __env; 41 | 42 | 43 | /* Functions */ 44 | void initialise_monitor_handles() 45 | { 46 | } 47 | 48 | int _getpid(void) 49 | { 50 | return 1; 51 | } 52 | 53 | int _kill(int pid, int sig) 54 | { 55 | errno = EINVAL; 56 | return -1; 57 | } 58 | 59 | void _exit (int status) 60 | { 61 | _kill(status, -1); 62 | while (1) {} /* Make sure we hang here */ 63 | } 64 | 65 | __attribute__((weak)) int _read(int file, char *ptr, int len) 66 | { 67 | int DataIdx; 68 | 69 | for (DataIdx = 0; DataIdx < len; DataIdx++) 70 | { 71 | *ptr++ = __io_getchar(); 72 | } 73 | 74 | return len; 75 | } 76 | 77 | __attribute__((weak)) int _write(int file, char *ptr, int len) 78 | { 79 | int DataIdx; 80 | 81 | for (DataIdx = 0; DataIdx < len; DataIdx++) 82 | { 83 | __io_putchar(*ptr++); 84 | } 85 | return len; 86 | } 87 | 88 | int _close(int file) 89 | { 90 | return -1; 91 | } 92 | 93 | 94 | int _fstat(int file, struct stat *st) 95 | { 96 | st->st_mode = S_IFCHR; 97 | return 0; 98 | } 99 | 100 | int _isatty(int file) 101 | { 102 | return 1; 103 | } 104 | 105 | int _lseek(int file, int ptr, int dir) 106 | { 107 | return 0; 108 | } 109 | 110 | int _open(char *path, int flags, ...) 111 | { 112 | /* Pretend like we always fail */ 113 | return -1; 114 | } 115 | 116 | int _wait(int *status) 117 | { 118 | errno = ECHILD; 119 | return -1; 120 | } 121 | 122 | int _unlink(char *name) 123 | { 124 | errno = ENOENT; 125 | return -1; 126 | } 127 | 128 | int _times(struct tms *buf) 129 | { 130 | return -1; 131 | } 132 | 133 | int _stat(char *file, struct stat *st) 134 | { 135 | st->st_mode = S_IFCHR; 136 | return 0; 137 | } 138 | 139 | int _link(char *old, char *new) 140 | { 141 | errno = EMLINK; 142 | return -1; 143 | } 144 | 145 | int _fork(void) 146 | { 147 | errno = EAGAIN; 148 | return -1; 149 | } 150 | 151 | int _execve(char *name, char **argv, char **env) 152 | { 153 | errno = ENOMEM; 154 | return -1; 155 | } 156 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Generated by STM32CubeIDE 5 | * @brief STM32CubeIDE System Memory calls file 6 | * 7 | * For more information about which C functions 8 | * need which of these lowlevel functions 9 | * please consult the newlib libc manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | 27 | /** 28 | * Pointer to the current high watermark of the heap usage 29 | */ 30 | static uint8_t *__sbrk_heap_end = NULL; 31 | 32 | /** 33 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc 34 | * and others from the C library 35 | * 36 | * @verbatim 37 | * ############################################################################ 38 | * # .data # .bss # newlib heap # MSP stack # 39 | * # # # # Reserved by _Min_Stack_Size # 40 | * ############################################################################ 41 | * ^-- RAM start ^-- _end _estack, RAM end --^ 42 | * @endverbatim 43 | * 44 | * This implementation starts allocating at the '_end' linker symbol 45 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack 46 | * The implementation considers '_estack' linker symbol to be RAM end 47 | * NOTE: If the MSP stack, at any point during execution, grows larger than the 48 | * reserved size, please increase the '_Min_Stack_Size'. 49 | * 50 | * @param incr Memory size 51 | * @return Pointer to allocated memory 52 | */ 53 | void *_sbrk(ptrdiff_t incr) 54 | { 55 | extern uint8_t _end; /* Symbol defined in the linker script */ 56 | extern uint8_t _estack; /* Symbol defined in the linker script */ 57 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ 58 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 59 | const uint8_t *max_heap = (uint8_t *)stack_limit; 60 | uint8_t *prev_heap_end; 61 | 62 | /* Initialize heap end at first call */ 63 | if (NULL == __sbrk_heap_end) 64 | { 65 | __sbrk_heap_end = &_end; 66 | } 67 | 68 | /* Protect heap from growing into the reserved MSP stack */ 69 | if (__sbrk_heap_end + incr > max_heap) 70 | { 71 | errno = ENOMEM; 72 | return (void *)-1; 73 | } 74 | 75 | prev_heap_end = __sbrk_heap_end; 76 | __sbrk_heap_end += incr; 77 | 78 | return (void *)prev_heap_end; 79 | } 80 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Core/Src/system_stm32f3xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f3xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 6 | * 7 | * 1. This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32f3xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. 22 | * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to 23 | * configure the system clock before to branch to main program. 24 | * 25 | * 3. This file configures the system clock as follows: 26 | *============================================================================= 27 | * Supported STM32F3xx device 28 | *----------------------------------------------------------------------------- 29 | * System Clock source | HSI 30 | *----------------------------------------------------------------------------- 31 | * SYSCLK(Hz) | 8000000 32 | *----------------------------------------------------------------------------- 33 | * HCLK(Hz) | 8000000 34 | *----------------------------------------------------------------------------- 35 | * AHB Prescaler | 1 36 | *----------------------------------------------------------------------------- 37 | * APB2 Prescaler | 1 38 | *----------------------------------------------------------------------------- 39 | * APB1 Prescaler | 1 40 | *----------------------------------------------------------------------------- 41 | * USB Clock | DISABLE 42 | *----------------------------------------------------------------------------- 43 | *============================================================================= 44 | ****************************************************************************** 45 | * @attention 46 | * 47 | *

© Copyright (c) 2016 STMicroelectronics. 48 | * All rights reserved.

49 | * 50 | * This software component is licensed by ST under BSD 3-Clause license, 51 | * the "License"; You may not use this file except in compliance with the 52 | * License. You may obtain a copy of the License at: 53 | * opensource.org/licenses/BSD-3-Clause 54 | * 55 | ****************************************************************************** 56 | */ 57 | 58 | /** @addtogroup CMSIS 59 | * @{ 60 | */ 61 | 62 | /** @addtogroup stm32f3xx_system 63 | * @{ 64 | */ 65 | 66 | /** @addtogroup STM32F3xx_System_Private_Includes 67 | * @{ 68 | */ 69 | 70 | #include "stm32f3xx.h" 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @addtogroup STM32F3xx_System_Private_TypesDefinitions 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @addtogroup STM32F3xx_System_Private_Defines 85 | * @{ 86 | */ 87 | #if !defined (HSE_VALUE) 88 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. 89 | This value can be provided and adapted by the user application. */ 90 | #endif /* HSE_VALUE */ 91 | 92 | #if !defined (HSI_VALUE) 93 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. 94 | This value can be provided and adapted by the user application. */ 95 | #endif /* HSI_VALUE */ 96 | 97 | /* Note: Following vector table addresses must be defined in line with linker 98 | configuration. */ 99 | /*!< Uncomment the following line if you need to relocate the vector table 100 | anywhere in Flash or Sram, else the vector table is kept at the automatic 101 | remap of boot address selected */ 102 | /* #define USER_VECT_TAB_ADDRESS */ 103 | 104 | #if defined(USER_VECT_TAB_ADDRESS) 105 | /*!< Uncomment the following line if you need to relocate your vector Table 106 | in Sram else user remap will be done in Flash. */ 107 | /* #define VECT_TAB_SRAM */ 108 | #if defined(VECT_TAB_SRAM) 109 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. 110 | This value must be a multiple of 0x200. */ 111 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 112 | This value must be a multiple of 0x200. */ 113 | #else 114 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 115 | This value must be a multiple of 0x200. */ 116 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 117 | This value must be a multiple of 0x200. */ 118 | #endif /* VECT_TAB_SRAM */ 119 | #endif /* USER_VECT_TAB_ADDRESS */ 120 | 121 | /******************************************************************************/ 122 | /** 123 | * @} 124 | */ 125 | 126 | /** @addtogroup STM32F3xx_System_Private_Macros 127 | * @{ 128 | */ 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /** @addtogroup STM32F3xx_System_Private_Variables 135 | * @{ 136 | */ 137 | /* This variable is updated in three ways: 138 | 1) by calling CMSIS function SystemCoreClockUpdate() 139 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 140 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 141 | Note: If you use this function to configure the system clock there is no need to 142 | call the 2 first functions listed above, since SystemCoreClock variable is 143 | updated automatically. 144 | */ 145 | uint32_t SystemCoreClock = 8000000; 146 | 147 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 148 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 149 | 150 | /** 151 | * @} 152 | */ 153 | 154 | /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes 155 | * @{ 156 | */ 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /** @addtogroup STM32F3xx_System_Private_Functions 163 | * @{ 164 | */ 165 | 166 | /** 167 | * @brief Setup the microcontroller system 168 | * @param None 169 | * @retval None 170 | */ 171 | void SystemInit(void) 172 | { 173 | /* FPU settings --------------------------------------------------------------*/ 174 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 175 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 176 | #endif 177 | 178 | /* Configure the Vector Table location -------------------------------------*/ 179 | #if defined(USER_VECT_TAB_ADDRESS) 180 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 181 | #endif /* USER_VECT_TAB_ADDRESS */ 182 | } 183 | 184 | /** 185 | * @brief Update SystemCoreClock variable according to Clock Register Values. 186 | * The SystemCoreClock variable contains the core clock (HCLK), it can 187 | * be used by the user application to setup the SysTick timer or configure 188 | * other parameters. 189 | * 190 | * @note Each time the core clock (HCLK) changes, this function must be called 191 | * to update SystemCoreClock variable value. Otherwise, any configuration 192 | * based on this variable will be incorrect. 193 | * 194 | * @note - The system frequency computed by this function is not the real 195 | * frequency in the chip. It is calculated based on the predefined 196 | * constant and the selected clock source: 197 | * 198 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 199 | * 200 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 201 | * 202 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 203 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 204 | * 205 | * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value 206 | * 8 MHz) but the real value may vary depending on the variations 207 | * in voltage and temperature. 208 | * 209 | * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value 210 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real 211 | * frequency of the crystal used. Otherwise, this function may 212 | * have wrong result. 213 | * 214 | * - The result of this function could be not correct when using fractional 215 | * value for HSE crystal. 216 | * 217 | * @param None 218 | * @retval None 219 | */ 220 | void SystemCoreClockUpdate (void) 221 | { 222 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; 223 | 224 | /* Get SYSCLK source -------------------------------------------------------*/ 225 | tmp = RCC->CFGR & RCC_CFGR_SWS; 226 | 227 | switch (tmp) 228 | { 229 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ 230 | SystemCoreClock = HSI_VALUE; 231 | break; 232 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ 233 | SystemCoreClock = HSE_VALUE; 234 | break; 235 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ 236 | /* Get PLL clock source and multiplication factor ----------------------*/ 237 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; 238 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 239 | pllmull = ( pllmull >> 18) + 2; 240 | 241 | #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) 242 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; 243 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) 244 | { 245 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 246 | SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; 247 | } 248 | else 249 | { 250 | /* HSI oscillator clock selected as PREDIV1 clock entry */ 251 | SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; 252 | } 253 | #else 254 | if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) 255 | { 256 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 257 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 258 | } 259 | else 260 | { 261 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; 262 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 263 | SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; 264 | } 265 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 266 | break; 267 | default: /* HSI used as system clock */ 268 | SystemCoreClock = HSI_VALUE; 269 | break; 270 | } 271 | /* Compute HCLK clock frequency ----------------*/ 272 | /* Get HCLK prescaler */ 273 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 274 | /* HCLK clock frequency */ 275 | SystemCoreClock >>= tmp; 276 | } 277 | 278 | /** 279 | * @} 280 | */ 281 | 282 | /** 283 | * @} 284 | */ 285 | 286 | /** 287 | * @} 288 | */ 289 | 290 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 291 | 292 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/tunerok/stm32_i2c_slave_examlpe/41a83ece599918cc8536a5752978397f2574ee68/stm32_i2c_slave_example/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f3xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32f3xx_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef __SYSTEM_STM32F3XX_H 32 | #define __SYSTEM_STM32F3XX_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32F3xx_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32F3xx_System_Exported_types 48 | * @{ 49 | */ 50 | /* This variable is updated in three ways: 51 | 1) by calling CMSIS function SystemCoreClockUpdate() 52 | 3) by calling HAL API function HAL_RCC_GetHCLKFreq() 53 | 3) by calling HAL API function HAL_RCC_ClockConfig() 54 | Note: If you use this function to configure the system clock; then there 55 | is no need to call the 2 first functions listed above, since SystemCoreClock 56 | variable is updated automatically. 57 | */ 58 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 59 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 60 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 61 | 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F3xx_System_Exported_Constants 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F3xx_System_Exported_Macros 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @addtogroup STM32F3xx_System_Exported_Functions 84 | * @{ 85 | */ 86 | 87 | extern void SystemInit(void); 88 | extern void SystemCoreClockUpdate(void); 89 | /** 90 | * @} 91 | */ 92 | 93 | #ifdef __cplusplus 94 | } 95 | #endif 96 | 97 | #endif /*__SYSTEM_STM32F3XX_H */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 107 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Device/ST/STM32F3xx/License.md: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. 66 | 67 | END OF TERMS AND CONDITIONS 68 | 69 | APPENDIX: 70 | 71 | Copyright [2019] [STMicroelectronics] 72 | 73 | Licensed under the Apache License, Version 2.0 (the "License"); 74 | you may not use this file except in compliance with the License. 75 | You may obtain a copy of the License at 76 | 77 | http://www.apache.org/licenses/LICENSE-2.0 78 | 79 | Unless required by applicable law or agreed to in writing, software 80 | distributed under the License is distributed on an "AS IS" BASIS, 81 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 82 | See the License for the specific language governing permissions and 83 | limitations under the License. 84 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright {yyyy} {name of copyright owner} 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2016 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F3xx_HAL_DEF 23 | #define __STM32F3xx_HAL_DEF 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f3xx.h" 31 | #include "Legacy/stm32_hal_legacy.h" 32 | #include 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | 36 | /** 37 | * @brief HAL Status structures definition 38 | */ 39 | typedef enum 40 | { 41 | HAL_OK = 0x00U, 42 | HAL_ERROR = 0x01U, 43 | HAL_BUSY = 0x02U, 44 | HAL_TIMEOUT = 0x03 45 | } HAL_StatusTypeDef; 46 | 47 | /** 48 | * @brief HAL Lock structures definition 49 | */ 50 | typedef enum 51 | { 52 | HAL_UNLOCKED = 0x00U, 53 | HAL_LOCKED = 0x01 54 | } HAL_LockTypeDef; 55 | 56 | /* Exported macro ------------------------------------------------------------*/ 57 | 58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 59 | 60 | #define HAL_MAX_DELAY 0xFFFFFFFFU 61 | 62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == BIT) 63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 64 | 65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ 66 | do{ \ 67 | (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ 68 | (__DMA_HANDLE_).Parent = (__HANDLE__); \ 69 | } while(0U) 70 | 71 | /** @brief Reset the Handle's State field. 72 | * @param __HANDLE__ specifies the Peripheral Handle. 73 | * @note This macro can be used for the following purpose: 74 | * - When the Handle is declared as local variable; before passing it as parameter 75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 76 | * to set to 0 the Handle's "State" field. 77 | * Otherwise, "State" field may have any random value and the first time the function 78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 79 | * (i.e. HAL_PPP_MspInit() will not be executed). 80 | * - When there is a need to reconfigure the low level hardware: instead of calling 81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 84 | * @retval None 85 | */ 86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 87 | 88 | #if (USE_RTOS == 1U) 89 | #error " USE_RTOS should be 0 in the current HAL release " 90 | #else 91 | #define __HAL_LOCK(__HANDLE__) \ 92 | do{ \ 93 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 94 | { \ 95 | return HAL_BUSY; \ 96 | } \ 97 | else \ 98 | { \ 99 | (__HANDLE__)->Lock = HAL_LOCKED; \ 100 | } \ 101 | }while (0U) 102 | 103 | #define __HAL_UNLOCK(__HANDLE__) \ 104 | do{ \ 105 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 106 | }while (0U) 107 | #endif /* USE_RTOS */ 108 | 109 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 110 | #ifndef __weak 111 | #define __weak __attribute__((weak)) 112 | #endif 113 | #ifndef __packed 114 | #define __packed __attribute__((packed)) 115 | #endif 116 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 117 | #ifndef __weak 118 | #define __weak __attribute__((weak)) 119 | #endif /* __weak */ 120 | #ifndef __packed 121 | #define __packed __attribute__((__packed__)) 122 | #endif /* __packed */ 123 | #endif /* __GNUC__ */ 124 | 125 | 126 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 127 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 128 | #ifndef __ALIGN_BEGIN 129 | #define __ALIGN_BEGIN 130 | #endif 131 | #ifndef __ALIGN_END 132 | #define __ALIGN_END __attribute__ ((aligned (4))) 133 | #endif 134 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 135 | #ifndef __ALIGN_END 136 | #define __ALIGN_END __attribute__ ((aligned (4))) 137 | #endif /* __ALIGN_END */ 138 | #ifndef __ALIGN_BEGIN 139 | #define __ALIGN_BEGIN 140 | #endif /* __ALIGN_BEGIN */ 141 | #else 142 | #ifndef __ALIGN_END 143 | #define __ALIGN_END 144 | #endif /* __ALIGN_END */ 145 | #ifndef __ALIGN_BEGIN 146 | #if defined (__CC_ARM) /* ARM Compiler V5*/ 147 | #define __ALIGN_BEGIN __align(4) 148 | #elif defined (__ICCARM__) /* IAR Compiler */ 149 | #define __ALIGN_BEGIN 150 | #endif /* __CC_ARM */ 151 | #endif /* __ALIGN_BEGIN */ 152 | #endif /* __GNUC__ */ 153 | 154 | /** 155 | * @brief __NOINLINE definition 156 | */ 157 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 158 | /* ARM V4/V5 and V6 & GNU Compiler 159 | ------------------------------- 160 | */ 161 | #define __NOINLINE __attribute__ ( (noinline) ) 162 | 163 | #elif defined ( __ICCARM__ ) 164 | /* ICCARM Compiler 165 | --------------- 166 | */ 167 | #define __NOINLINE _Pragma("optimize = no_inline") 168 | 169 | #endif 170 | 171 | #ifdef __cplusplus 172 | } 173 | #endif 174 | 175 | #endif /* ___STM32F3xx_HAL_DEF */ 176 | 177 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 178 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_dma_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of DMA HAL extension module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_HAL_DMA_EX_H 22 | #define __STM32F3xx_HAL_DMA_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup DMAEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /* Exported macro ------------------------------------------------------------*/ 42 | /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros 43 | * @{ 44 | */ 45 | /* Interrupt & Flag management */ 46 | 47 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 48 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 49 | defined(STM32F373xC) || defined(STM32F378xx) 50 | /** 51 | * @brief Returns the current DMA Channel transfer complete flag. 52 | * @param __HANDLE__ DMA handle 53 | * @retval The specified transfer complete flag index. 54 | */ 55 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 56 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 57 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 58 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 59 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 60 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 61 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 62 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ 63 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 64 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 65 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 66 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 67 | DMA_FLAG_TC5) 68 | 69 | /** 70 | * @brief Returns the current DMA Channel half transfer complete flag. 71 | * @param __HANDLE__ DMA handle 72 | * @retval The specified half transfer complete flag index. 73 | */ 74 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 75 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 76 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 77 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 78 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 79 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 80 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 81 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ 82 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 83 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 84 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 85 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 86 | DMA_FLAG_HT5) 87 | 88 | /** 89 | * @brief Returns the current DMA Channel transfer error flag. 90 | * @param __HANDLE__ DMA handle 91 | * @retval The specified transfer error flag index. 92 | */ 93 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 94 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 95 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 96 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 97 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 98 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 99 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 100 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ 101 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 102 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 103 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 104 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 105 | DMA_FLAG_TE5) 106 | 107 | /** 108 | * @brief Return the current DMA Channel Global interrupt flag. 109 | * @param __HANDLE__ DMA handle 110 | * @retval The specified transfer error flag index. 111 | */ 112 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 113 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ 114 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ 115 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ 116 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ 117 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ 118 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ 119 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ 120 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ 121 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ 122 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ 123 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ 124 | DMA_FLAG_GL5) 125 | 126 | /** 127 | * @brief Get the DMA Channel pending flags. 128 | * @param __HANDLE__ DMA handle 129 | * @param __FLAG__ Get the specified flag. 130 | * This parameter can be any combination of the following values: 131 | * @arg DMA_FLAG_TCx: Transfer complete flag 132 | * @arg DMA_FLAG_HTx: Half transfer complete flag 133 | * @arg DMA_FLAG_TEx: Transfer error flag 134 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. 135 | * @retval The state of FLAG (SET or RESET). 136 | */ 137 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 138 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ 139 | (DMA1->ISR & (__FLAG__))) 140 | 141 | /** 142 | * @brief Clears the DMA Channel pending flags. 143 | * @param __HANDLE__ DMA handle 144 | * @param __FLAG__ specifies the flag to clear. 145 | * This parameter can be any combination of the following values: 146 | * @arg DMA_FLAG_TCx: Transfer complete flag 147 | * @arg DMA_FLAG_HTx: Half transfer complete flag 148 | * @arg DMA_FLAG_TEx: Transfer error flag 149 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. 150 | * @retval None 151 | */ 152 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 153 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ 154 | (DMA1->IFCR = (__FLAG__))) 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | #else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */ 161 | /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices 162 | * @{ 163 | */ 164 | 165 | /** 166 | * @brief Returns the current DMA Channel transfer complete flag. 167 | * @param __HANDLE__ DMA handle 168 | * @retval The specified transfer complete flag index. 169 | */ 170 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 171 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 172 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 173 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 174 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 175 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 176 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 177 | DMA_FLAG_TC7) 178 | 179 | /** 180 | * @brief Returns the current DMA Channel half transfer complete flag. 181 | * @param __HANDLE__ DMA handle 182 | * @retval The specified half transfer complete flag index. 183 | */ 184 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 185 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 186 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 187 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 188 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 189 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 190 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 191 | DMA_FLAG_HT7) 192 | 193 | /** 194 | * @brief Returns the current DMA Channel transfer error flag. 195 | * @param __HANDLE__ DMA handle 196 | * @retval The specified transfer error flag index. 197 | */ 198 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 199 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 200 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 201 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 202 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 203 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 204 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 205 | DMA_FLAG_TE7) 206 | 207 | /** 208 | * @brief Return the current DMA Channel Global interrupt flag. 209 | * @param __HANDLE__ DMA handle 210 | * @retval The specified transfer error flag index. 211 | */ 212 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 213 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ 214 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ 215 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ 216 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ 217 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ 218 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ 219 | DMA_FLAG_GL7) 220 | 221 | /** 222 | * @brief Get the DMA Channel pending flags. 223 | * @param __HANDLE__ DMA handle 224 | * @param __FLAG__ Get the specified flag. 225 | * This parameter can be any combination of the following values: 226 | * @arg DMA_FLAG_TCx: Transfer complete flag 227 | * @arg DMA_FLAG_HTx: Half transfer complete flag 228 | * @arg DMA_FLAG_TEx: Transfer error flag 229 | * Where x can be 1_7 to select the DMA Channel flag. 230 | * @retval The state of FLAG (SET or RESET). 231 | */ 232 | 233 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 234 | 235 | /** 236 | * @brief Clears the DMA Channel pending flags. 237 | * @param __HANDLE__ DMA handle 238 | * @param __FLAG__ specifies the flag to clear. 239 | * This parameter can be any combination of the following values: 240 | * @arg DMA_FLAG_TCx: Transfer complete flag 241 | * @arg DMA_FLAG_HTx: Half transfer complete flag 242 | * @arg DMA_FLAG_TEx: Transfer error flag 243 | * Where x can be 1_7 to select the DMA Channel flag. 244 | * @retval None 245 | */ 246 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 247 | 248 | /** 249 | * @} 250 | */ 251 | 252 | #endif 253 | 254 | /** 255 | * @} 256 | */ 257 | 258 | /** 259 | * @} 260 | */ 261 | 262 | /** 263 | * @} 264 | */ 265 | 266 | #ifdef __cplusplus 267 | } 268 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 269 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ 270 | /* STM32F373xC || STM32F378xx */ 271 | 272 | #endif /* __STM32F3xx_HAL_DMA_H */ 273 | 274 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 275 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_flash.h 4 | * @author MCD Application Team 5 | * @brief Header file of Flash HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_HAL_FLASH_H 22 | #define __STM32F3xx_HAL_FLASH_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup FLASH 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup FLASH_Private_Constants 40 | * @{ 41 | */ 42 | #define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ 43 | /** 44 | * @} 45 | */ 46 | 47 | /** @addtogroup FLASH_Private_Macros 48 | * @{ 49 | */ 50 | 51 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ 52 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ 53 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 54 | 55 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ 56 | ((__LATENCY__) == FLASH_LATENCY_1) || \ 57 | ((__LATENCY__) == FLASH_LATENCY_2)) 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | /* Exported types ------------------------------------------------------------*/ 64 | /** @defgroup FLASH_Exported_Types FLASH Exported Types 65 | * @{ 66 | */ 67 | 68 | /** 69 | * @brief FLASH Procedure structure definition 70 | */ 71 | typedef enum 72 | { 73 | FLASH_PROC_NONE = 0U, 74 | FLASH_PROC_PAGEERASE = 1U, 75 | FLASH_PROC_MASSERASE = 2U, 76 | FLASH_PROC_PROGRAMHALFWORD = 3U, 77 | FLASH_PROC_PROGRAMWORD = 4U, 78 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U 79 | } FLASH_ProcedureTypeDef; 80 | 81 | /** 82 | * @brief FLASH handle Structure definition 83 | */ 84 | typedef struct 85 | { 86 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 87 | 88 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ 89 | 90 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ 91 | 92 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ 93 | 94 | HAL_LockTypeDef Lock; /*!< FLASH locking object */ 95 | 96 | __IO uint32_t ErrorCode; /*!< FLASH error code 97 | This parameter can be a value of @ref FLASH_Error_Codes */ 98 | } FLASH_ProcessTypeDef; 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /* Exported constants --------------------------------------------------------*/ 105 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 106 | * @{ 107 | */ 108 | 109 | /** @defgroup FLASH_Error_Codes FLASH Error Codes 110 | * @{ 111 | */ 112 | 113 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ 114 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ 115 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** @defgroup FLASH_Type_Program FLASH Type Program 122 | * @{ 123 | */ 124 | #define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR |= FLASH_ACR_HLFCYA) 185 | 186 | /** 187 | * @brief Disable the FLASH half cycle access. 188 | * @retval None 189 | */ 190 | #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) 191 | 192 | /** 193 | * @} 194 | */ 195 | 196 | /** @defgroup FLASH_EM_Latency FLASH Latency 197 | * @brief macros to handle FLASH Latency 198 | * @{ 199 | */ 200 | 201 | /** 202 | * @brief Set the FLASH Latency. 203 | * @param __LATENCY__ FLASH Latency 204 | * This parameter can be one of the following values: 205 | * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle 206 | * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle 207 | * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles 208 | * @retval None 209 | */ 210 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) 211 | 212 | 213 | /** 214 | * @brief Get the FLASH Latency. 215 | * @retval FLASH Latency 216 | * This parameter can be one of the following values: 217 | * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle 218 | * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle 219 | * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles 220 | */ 221 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 222 | 223 | /** 224 | * @} 225 | */ 226 | 227 | /** @defgroup FLASH_Prefetch FLASH Prefetch 228 | * @brief macros to handle FLASH Prefetch buffer 229 | * @{ 230 | */ 231 | /** 232 | * @brief Enable the FLASH prefetch buffer. 233 | * @retval None 234 | */ 235 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) 236 | 237 | /** 238 | * @brief Disable the FLASH prefetch buffer. 239 | * @retval None 240 | */ 241 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) 242 | 243 | /** 244 | * @} 245 | */ 246 | 247 | /** @defgroup FLASH_Interrupt FLASH Interrupts 248 | * @brief macros to handle FLASH interrupts 249 | * @{ 250 | */ 251 | 252 | /** 253 | * @brief Enable the specified FLASH interrupt. 254 | * @param __INTERRUPT__ FLASH interrupt 255 | * This parameter can be any combination of the following values: 256 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 257 | * @arg @ref FLASH_IT_ERR Error Interrupt 258 | * @retval none 259 | */ 260 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) 261 | 262 | /** 263 | * @brief Disable the specified FLASH interrupt. 264 | * @param __INTERRUPT__ FLASH interrupt 265 | * This parameter can be any combination of the following values: 266 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 267 | * @arg @ref FLASH_IT_ERR Error Interrupt 268 | * @retval none 269 | */ 270 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) 271 | 272 | /** 273 | * @brief Get the specified FLASH flag status. 274 | * @param __FLAG__ specifies the FLASH flag to check. 275 | * This parameter can be one of the following values: 276 | * @arg @ref FLASH_FLAG_BSY FLASH Busy flag 277 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 278 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 279 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag 280 | * @retval The new state of __FLAG__ (SET or RESET). 281 | */ 282 | #define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) 283 | 284 | /** 285 | * @brief Clear the specified FLASH flag. 286 | * @param __FLAG__ specifies the FLASH flags to clear. 287 | * This parameter can be any combination of the following values: 288 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 289 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 290 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag 291 | * @retval none 292 | */ 293 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /* Include FLASH HAL Extended module */ 304 | #include "stm32f3xx_hal_flash_ex.h" 305 | 306 | /* Exported functions --------------------------------------------------------*/ 307 | /** @addtogroup FLASH_Exported_Functions 308 | * @{ 309 | */ 310 | 311 | /** @addtogroup FLASH_Exported_Functions_Group1 312 | * @{ 313 | */ 314 | /* IO operation functions *****************************************************/ 315 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 316 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 317 | 318 | /* FLASH IRQ handler function */ 319 | void HAL_FLASH_IRQHandler(void); 320 | /* Callbacks in non blocking modes */ 321 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 322 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 323 | 324 | /** 325 | * @} 326 | */ 327 | 328 | /** @addtogroup FLASH_Exported_Functions_Group2 329 | * @{ 330 | */ 331 | /* Peripheral Control functions ***********************************************/ 332 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); 333 | HAL_StatusTypeDef HAL_FLASH_Lock(void); 334 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 335 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 336 | HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 337 | 338 | /** 339 | * @} 340 | */ 341 | 342 | /** @addtogroup FLASH_Exported_Functions_Group3 343 | * @{ 344 | */ 345 | /* Peripheral State and Error functions ***************************************/ 346 | uint32_t HAL_FLASH_GetError(void); 347 | 348 | /** 349 | * @} 350 | */ 351 | 352 | /** 353 | * @} 354 | */ 355 | 356 | /* Private function -------------------------------------------------*/ 357 | /** @addtogroup FLASH_Private_Functions 358 | * @{ 359 | */ 360 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 361 | 362 | /** 363 | * @} 364 | */ 365 | 366 | /** 367 | * @} 368 | */ 369 | 370 | /** 371 | * @} 372 | */ 373 | 374 | #ifdef __cplusplus 375 | } 376 | #endif 377 | 378 | #endif /* __STM32F3xx_HAL_FLASH_H */ 379 | 380 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 381 | 382 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_i2c_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of I2C HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32F3xx_HAL_I2C_EX_H 22 | #define STM32F3xx_HAL_I2C_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup I2CEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants 42 | * @{ 43 | */ 44 | 45 | /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter 46 | * @{ 47 | */ 48 | #define I2C_ANALOGFILTER_ENABLE 0x00000000U 49 | #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 50 | /** 51 | * @} 52 | */ 53 | 54 | /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus 55 | * @{ 56 | */ 57 | #define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ 58 | #define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 59 | #define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 60 | #define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 61 | #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 62 | #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ 63 | #if defined(SYSCFG_CFGR1_I2C2_FMP) 64 | #define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ 65 | #else 66 | #define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ 67 | #endif /* SYSCFG_CFGR1_I2C2_FMP */ 68 | #if defined(SYSCFG_CFGR1_I2C3_FMP) 69 | #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ 70 | #else 71 | #define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ 72 | #endif /* SYSCFG_CFGR1_I2C3_FMP */ 73 | /** 74 | * @} 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /* Exported macro ------------------------------------------------------------*/ 82 | /** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros 83 | * @{ 84 | */ 85 | 86 | /** 87 | * @} 88 | */ 89 | 90 | /* Exported functions --------------------------------------------------------*/ 91 | /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions 92 | * @{ 93 | */ 94 | 95 | /** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions 96 | * @{ 97 | */ 98 | /* Peripheral Control functions ************************************************/ 99 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); 100 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); 101 | /** 102 | * @} 103 | */ 104 | 105 | /** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions 106 | * @{ 107 | */ 108 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); 109 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); 110 | /** 111 | * @} 112 | */ 113 | 114 | /** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions 115 | * @{ 116 | */ 117 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); 118 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); 119 | /** 120 | * @} 121 | */ 122 | 123 | /** 124 | * @} 125 | */ 126 | 127 | /* Private constants ---------------------------------------------------------*/ 128 | /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants 129 | * @{ 130 | */ 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /* Private macros ------------------------------------------------------------*/ 137 | /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros 138 | * @{ 139 | */ 140 | #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ 141 | ((FILTER) == I2C_ANALOGFILTER_DISABLE)) 142 | 143 | #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 144 | 145 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ 146 | ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ 147 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ 148 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ 149 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ 150 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ 151 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ 152 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) 153 | /** 154 | * @} 155 | */ 156 | 157 | /* Private Functions ---------------------------------------------------------*/ 158 | /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions 159 | * @{ 160 | */ 161 | /* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */ 162 | /** 163 | * @} 164 | */ 165 | 166 | /** 167 | * @} 168 | */ 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | #ifdef __cplusplus 175 | } 176 | #endif 177 | 178 | #endif /* STM32F3xx_HAL_I2C_EX_H */ 179 | 180 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 181 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_pwr.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_HAL_PWR_H 22 | #define __STM32F3xx_HAL_PWR_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup PWR PWR 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /** @defgroup PWR_Exported_Constants PWR Exported Constants 42 | * @{ 43 | */ 44 | 45 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins 46 | * @{ 47 | */ 48 | 49 | #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */ 50 | #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */ 51 | #define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */ 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode 57 | * @{ 58 | */ 59 | #define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */ 60 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */ 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 66 | * @{ 67 | */ 68 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */ 69 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */ 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 75 | * @{ 76 | */ 77 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */ 78 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */ 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @defgroup PWR_Flag PWR Flag 84 | * @{ 85 | */ 86 | #define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */ 87 | #define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */ 88 | #define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */ 89 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */ 90 | /** 91 | * @} 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /* Exported macro ------------------------------------------------------------*/ 99 | /** @defgroup PWR_Exported_Macro PWR Exported Macro 100 | * @{ 101 | */ 102 | 103 | /** @brief Check PWR flag is set or not. 104 | * @param __FLAG__ specifies the flag to check. 105 | * This parameter can be one of the following values: 106 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 107 | * was received from the WKUP pin or from the RTC alarm (Alarm A 108 | * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. 109 | * An additional wakeup event is detected if the WKUP pin is enabled 110 | * (by setting the EWUP bit) when the WKUP pin level is already high. 111 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 112 | * resumed from StandBy mode. 113 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 114 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 115 | * For this reason, this bit is equal to 0 after Standby or reset 116 | * until the PVDE bit is set. 117 | * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference 118 | * voltage VREFINT is ready. 119 | * @retval The new state of __FLAG__ (TRUE or FALSE). 120 | */ 121 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) 122 | 123 | /** @brief Clear the PWR's pending flags. 124 | * @param __FLAG__ specifies the flag to clear. 125 | * This parameter can be one of the following values: 126 | * @arg PWR_FLAG_WU: Wake Up flag 127 | * @arg PWR_FLAG_SB: StandBy flag 128 | */ 129 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) 130 | 131 | /** 132 | * @} 133 | */ 134 | 135 | /* Private macros --------------------------------------------------------*/ 136 | /** @addtogroup PWR_Private_Macros PWR Private Macros 137 | * @{ 138 | */ 139 | 140 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 141 | ((PIN) == PWR_WAKEUP_PIN2) || \ 142 | ((PIN) == PWR_WAKEUP_PIN3)) 143 | 144 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ 145 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 146 | 147 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 148 | 149 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /* Include PWR HAL Extended module */ 156 | #include "stm32f3xx_hal_pwr_ex.h" 157 | 158 | /* Exported functions --------------------------------------------------------*/ 159 | 160 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions 161 | * @{ 162 | */ 163 | 164 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 165 | * @{ 166 | */ 167 | 168 | /* Initialization and de-initialization functions *****************************/ 169 | void HAL_PWR_DeInit(void); 170 | 171 | /** 172 | * @} 173 | */ 174 | 175 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 176 | * @{ 177 | */ 178 | 179 | /* Peripheral Control functions **********************************************/ 180 | void HAL_PWR_EnableBkUpAccess(void); 181 | void HAL_PWR_DisableBkUpAccess(void); 182 | 183 | /* WakeUp pins configuration functions ****************************************/ 184 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); 185 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 186 | 187 | /* Low Power modes configuration functions ************************************/ 188 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 189 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 190 | void HAL_PWR_EnterSTANDBYMode(void); 191 | 192 | void HAL_PWR_EnableSleepOnExit(void); 193 | void HAL_PWR_DisableSleepOnExit(void); 194 | void HAL_PWR_EnableSEVOnPend(void); 195 | void HAL_PWR_DisableSEVOnPend(void); 196 | /** 197 | * @} 198 | */ 199 | 200 | /** 201 | * @} 202 | */ 203 | 204 | /** 205 | * @} 206 | */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | #ifdef __cplusplus 213 | } 214 | #endif 215 | 216 | 217 | #endif /* __STM32F3xx_HAL_PWR_H */ 218 | 219 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 220 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_pwr_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_HAL_PWR_EX_H 22 | #define __STM32F3xx_HAL_PWR_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup PWREx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | 41 | /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 42 | * @{ 43 | */ 44 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 45 | defined(STM32F302xC) || defined(STM32F303xC) || \ 46 | defined(STM32F303x8) || defined(STM32F334x8) || \ 47 | defined(STM32F301x8) || defined(STM32F302x8) || \ 48 | defined(STM32F373xC) 49 | /** 50 | * @brief PWR PVD configuration structure definition 51 | */ 52 | typedef struct 53 | { 54 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level 55 | This parameter can be a value of @ref PWREx_PVD_detection_level */ 56 | 57 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 58 | This parameter can be a value of @ref PWREx_PVD_Mode */ 59 | }PWR_PVDTypeDef; 60 | #endif /* STM32F302xE || STM32F303xE || */ 61 | /* STM32F302xC || STM32F303xC || */ 62 | /* STM32F303x8 || STM32F334x8 || */ 63 | /* STM32F301x8 || STM32F302x8 || */ 64 | /* STM32F373xC */ 65 | 66 | /** 67 | * @} 68 | */ 69 | 70 | /* Exported constants --------------------------------------------------------*/ 71 | /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 72 | * @{ 73 | */ 74 | 75 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 76 | defined(STM32F302xC) || defined(STM32F303xC) || \ 77 | defined(STM32F303x8) || defined(STM32F334x8) || \ 78 | defined(STM32F301x8) || defined(STM32F302x8) || \ 79 | defined(STM32F373xC) 80 | 81 | /** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level 82 | * @{ 83 | */ 84 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */ 85 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */ 86 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */ 87 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */ 88 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */ 89 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */ 90 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */ 91 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */ 92 | /** 93 | * @} 94 | */ 95 | 96 | /** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode 97 | * @{ 98 | */ 99 | #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 100 | #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 101 | #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 102 | #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 103 | #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 104 | #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 105 | #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 106 | /** 107 | * @} 108 | */ 109 | 110 | #define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ 111 | 112 | #endif /* STM32F302xE || STM32F303xE || */ 113 | /* STM32F302xC || STM32F303xC || */ 114 | /* STM32F303x8 || STM32F334x8 || */ 115 | /* STM32F301x8 || STM32F302x8 || */ 116 | /* STM32F373xC */ 117 | 118 | #if defined(STM32F373xC) || defined(STM32F378xx) 119 | /** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx 120 | * @{ 121 | */ 122 | #define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */ 123 | #define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */ 124 | #define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */ 125 | /** 126 | * @} 127 | */ 128 | #endif /* STM32F373xC || STM32F378xx */ 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /* Exported macro ------------------------------------------------------------*/ 135 | /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 136 | * @{ 137 | */ 138 | 139 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 140 | defined(STM32F302xC) || defined(STM32F303xC) || \ 141 | defined(STM32F303x8) || defined(STM32F334x8) || \ 142 | defined(STM32F301x8) || defined(STM32F302x8) || \ 143 | defined(STM32F373xC) 144 | 145 | /** 146 | * @brief Enable interrupt on PVD Exti Line 16. 147 | * @retval None. 148 | */ 149 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) 150 | 151 | /** 152 | * @brief Disable interrupt on PVD Exti Line 16. 153 | * @retval None. 154 | */ 155 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) 156 | 157 | /** 158 | * @brief Generate a Software interrupt on selected EXTI line. 159 | * @retval None. 160 | */ 161 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) 162 | 163 | /** 164 | * @brief Enable event on PVD Exti Line 16. 165 | * @retval None. 166 | */ 167 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) 168 | 169 | /** 170 | * @brief Disable event on PVD Exti Line 16. 171 | * @retval None. 172 | */ 173 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) 174 | 175 | /** 176 | * @brief Disable the PVD Extended Interrupt Rising Trigger. 177 | * @retval None. 178 | */ 179 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 180 | 181 | /** 182 | * @brief Disable the PVD Extended Interrupt Falling Trigger. 183 | * @retval None. 184 | */ 185 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 186 | 187 | /** 188 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 189 | * @retval None 190 | */ 191 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 192 | 193 | /** 194 | * @brief PVD EXTI line configuration: set falling edge trigger. 195 | * @retval None. 196 | */ 197 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) 198 | 199 | /** 200 | * @brief PVD EXTI line configuration: set rising edge trigger. 201 | * @retval None. 202 | */ 203 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) 204 | 205 | /** 206 | * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. 207 | * @retval None 208 | */ 209 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 210 | 211 | /** 212 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. 213 | * @retval EXTI PVD Line Status. 214 | */ 215 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) 216 | 217 | /** 218 | * @brief Clear the PVD EXTI flag. 219 | * @retval None. 220 | */ 221 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) 222 | 223 | #endif /* STM32F302xE || STM32F303xE || */ 224 | /* STM32F302xC || STM32F303xC || */ 225 | /* STM32F303x8 || STM32F334x8 || */ 226 | /* STM32F301x8 || STM32F302x8 || */ 227 | /* STM32F373xC */ 228 | 229 | /** 230 | * @} 231 | */ 232 | 233 | /* Private macros --------------------------------------------------------*/ 234 | /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 235 | * @{ 236 | */ 237 | 238 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 239 | defined(STM32F302xC) || defined(STM32F303xC) || \ 240 | defined(STM32F303x8) || defined(STM32F334x8) || \ 241 | defined(STM32F301x8) || defined(STM32F302x8) || \ 242 | defined(STM32F373xC) 243 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ 244 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ 245 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ 246 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 247 | 248 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ 249 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ 250 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ 251 | ((MODE) == PWR_PVD_MODE_NORMAL)) 252 | #endif /* STM32F302xE || STM32F303xE || */ 253 | /* STM32F302xC || STM32F303xC || */ 254 | /* STM32F303x8 || STM32F334x8 || */ 255 | /* STM32F301x8 || STM32F302x8 || */ 256 | /* STM32F373xC */ 257 | 258 | #if defined(STM32F373xC) || defined(STM32F378xx) 259 | #define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \ 260 | ((SDADC) == PWR_SDADC_ANALOG2) || \ 261 | ((SDADC) == PWR_SDADC_ANALOG3)) 262 | #endif /* STM32F373xC || STM32F378xx */ 263 | 264 | 265 | /** 266 | * @} 267 | */ 268 | 269 | /* Exported functions --------------------------------------------------------*/ 270 | 271 | /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 272 | * @{ 273 | */ 274 | 275 | /** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions 276 | * @{ 277 | */ 278 | /* Peripheral Extended control functions **************************************/ 279 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 280 | defined(STM32F302xC) || defined(STM32F303xC) || \ 281 | defined(STM32F303x8) || defined(STM32F334x8) || \ 282 | defined(STM32F301x8) || defined(STM32F302x8) || \ 283 | defined(STM32F373xC) 284 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 285 | void HAL_PWR_EnablePVD(void); 286 | void HAL_PWR_DisablePVD(void); 287 | void HAL_PWR_PVD_IRQHandler(void); 288 | void HAL_PWR_PVDCallback(void); 289 | #endif /* STM32F302xE || STM32F303xE || */ 290 | /* STM32F302xC || STM32F303xC || */ 291 | /* STM32F303x8 || STM32F334x8 || */ 292 | /* STM32F301x8 || STM32F302x8 || */ 293 | /* STM32F373xC */ 294 | 295 | #if defined(STM32F373xC) || defined(STM32F378xx) 296 | void HAL_PWREx_EnableSDADC(uint32_t Analogx); 297 | void HAL_PWREx_DisableSDADC(uint32_t Analogx); 298 | #endif /* STM32F373xC || STM32F378xx */ 299 | 300 | /** 301 | * @} 302 | */ 303 | 304 | /** 305 | * @} 306 | */ 307 | 308 | /** 309 | * @} 310 | */ 311 | 312 | /** 313 | * @} 314 | */ 315 | 316 | #ifdef __cplusplus 317 | } 318 | #endif 319 | 320 | #endif /* __STM32F3xx_HAL_PWR_EX_H */ 321 | 322 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 323 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/License.md: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 STMicroelectronics 2 | 3 | This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_i2c_ex.c 4 | * @author MCD Application Team 5 | * @brief I2C Extended HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of I2C Extended peripheral: 8 | * + Filter Mode Functions 9 | * + WakeUp Mode Functions 10 | * + FastModePlus Functions 11 | * 12 | @verbatim 13 | ============================================================================== 14 | ##### I2C peripheral Extended features ##### 15 | ============================================================================== 16 | 17 | [..] Comparing to other previous devices, the I2C interface for STM32F3xx 18 | devices contains the following additional features 19 | 20 | (+) Possibility to disable or enable Analog Noise Filter 21 | (+) Use of a configured Digital Noise Filter 22 | (+) Disable or enable wakeup from Stop mode(s) 23 | (+) Disable or enable Fast Mode Plus 24 | 25 | ##### How to use this driver ##### 26 | ============================================================================== 27 | [..] This driver provides functions to configure Noise Filter and Wake Up Feature 28 | (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() 29 | (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() 30 | (#) Configure the enable or disable of I2C Wake Up Mode using the functions : 31 | (++) HAL_I2CEx_EnableWakeUp() 32 | (++) HAL_I2CEx_DisableWakeUp() 33 | (#) Configure the enable or disable of fast mode plus driving capability using the functions : 34 | (++) HAL_I2CEx_EnableFastModePlus() 35 | (++) HAL_I2CEx_DisableFastModePlus() 36 | @endverbatim 37 | ****************************************************************************** 38 | * @attention 39 | * 40 | *

© Copyright (c) 2016 STMicroelectronics. 41 | * All rights reserved.

42 | * 43 | * This software component is licensed by ST under BSD 3-Clause license, 44 | * the "License"; You may not use this file except in compliance with the 45 | * License. You may obtain a copy of the License at: 46 | * opensource.org/licenses/BSD-3-Clause 47 | * 48 | ****************************************************************************** 49 | */ 50 | 51 | /* Includes ------------------------------------------------------------------*/ 52 | #include "stm32f3xx_hal.h" 53 | 54 | /** @addtogroup STM32F3xx_HAL_Driver 55 | * @{ 56 | */ 57 | 58 | /** @defgroup I2CEx I2CEx 59 | * @brief I2C Extended HAL module driver 60 | * @{ 61 | */ 62 | 63 | #ifdef HAL_I2C_MODULE_ENABLED 64 | 65 | /* Private typedef -----------------------------------------------------------*/ 66 | /* Private define ------------------------------------------------------------*/ 67 | /* Private macro -------------------------------------------------------------*/ 68 | /* Private variables ---------------------------------------------------------*/ 69 | /* Private function prototypes -----------------------------------------------*/ 70 | /* Private functions ---------------------------------------------------------*/ 71 | 72 | /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions 73 | * @{ 74 | */ 75 | 76 | /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions 77 | * @brief Filter Mode Functions 78 | * 79 | @verbatim 80 | =============================================================================== 81 | ##### Filter Mode Functions ##### 82 | =============================================================================== 83 | [..] This section provides functions allowing to: 84 | (+) Configure Noise Filters 85 | 86 | @endverbatim 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @brief Configure I2C Analog noise filter. 92 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 93 | * the configuration information for the specified I2Cx peripheral. 94 | * @param AnalogFilter New state of the Analog filter. 95 | * @retval HAL status 96 | */ 97 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) 98 | { 99 | /* Check the parameters */ 100 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 101 | assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); 102 | 103 | if (hi2c->State == HAL_I2C_STATE_READY) 104 | { 105 | /* Process Locked */ 106 | __HAL_LOCK(hi2c); 107 | 108 | hi2c->State = HAL_I2C_STATE_BUSY; 109 | 110 | /* Disable the selected I2C peripheral */ 111 | __HAL_I2C_DISABLE(hi2c); 112 | 113 | /* Reset I2Cx ANOFF bit */ 114 | hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 115 | 116 | /* Set analog filter bit*/ 117 | hi2c->Instance->CR1 |= AnalogFilter; 118 | 119 | __HAL_I2C_ENABLE(hi2c); 120 | 121 | hi2c->State = HAL_I2C_STATE_READY; 122 | 123 | /* Process Unlocked */ 124 | __HAL_UNLOCK(hi2c); 125 | 126 | return HAL_OK; 127 | } 128 | else 129 | { 130 | return HAL_BUSY; 131 | } 132 | } 133 | 134 | /** 135 | * @brief Configure I2C Digital noise filter. 136 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 137 | * the configuration information for the specified I2Cx peripheral. 138 | * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. 139 | * @retval HAL status 140 | */ 141 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) 142 | { 143 | uint32_t tmpreg; 144 | 145 | /* Check the parameters */ 146 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 147 | assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); 148 | 149 | if (hi2c->State == HAL_I2C_STATE_READY) 150 | { 151 | /* Process Locked */ 152 | __HAL_LOCK(hi2c); 153 | 154 | hi2c->State = HAL_I2C_STATE_BUSY; 155 | 156 | /* Disable the selected I2C peripheral */ 157 | __HAL_I2C_DISABLE(hi2c); 158 | 159 | /* Get the old register value */ 160 | tmpreg = hi2c->Instance->CR1; 161 | 162 | /* Reset I2Cx DNF bits [11:8] */ 163 | tmpreg &= ~(I2C_CR1_DNF); 164 | 165 | /* Set I2Cx DNF coefficient */ 166 | tmpreg |= DigitalFilter << 8U; 167 | 168 | /* Store the new register value */ 169 | hi2c->Instance->CR1 = tmpreg; 170 | 171 | __HAL_I2C_ENABLE(hi2c); 172 | 173 | hi2c->State = HAL_I2C_STATE_READY; 174 | 175 | /* Process Unlocked */ 176 | __HAL_UNLOCK(hi2c); 177 | 178 | return HAL_OK; 179 | } 180 | else 181 | { 182 | return HAL_BUSY; 183 | } 184 | } 185 | /** 186 | * @} 187 | */ 188 | 189 | /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions 190 | * @brief WakeUp Mode Functions 191 | * 192 | @verbatim 193 | =============================================================================== 194 | ##### WakeUp Mode Functions ##### 195 | =============================================================================== 196 | [..] This section provides functions allowing to: 197 | (+) Configure Wake Up Feature 198 | 199 | @endverbatim 200 | * @{ 201 | */ 202 | 203 | /** 204 | * @brief Enable I2C wakeup from Stop mode(s). 205 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 206 | * the configuration information for the specified I2Cx peripheral. 207 | * @retval HAL status 208 | */ 209 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) 210 | { 211 | /* Check the parameters */ 212 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 213 | 214 | if (hi2c->State == HAL_I2C_STATE_READY) 215 | { 216 | /* Process Locked */ 217 | __HAL_LOCK(hi2c); 218 | 219 | hi2c->State = HAL_I2C_STATE_BUSY; 220 | 221 | /* Disable the selected I2C peripheral */ 222 | __HAL_I2C_DISABLE(hi2c); 223 | 224 | /* Enable wakeup from stop mode */ 225 | hi2c->Instance->CR1 |= I2C_CR1_WUPEN; 226 | 227 | __HAL_I2C_ENABLE(hi2c); 228 | 229 | hi2c->State = HAL_I2C_STATE_READY; 230 | 231 | /* Process Unlocked */ 232 | __HAL_UNLOCK(hi2c); 233 | 234 | return HAL_OK; 235 | } 236 | else 237 | { 238 | return HAL_BUSY; 239 | } 240 | } 241 | 242 | /** 243 | * @brief Disable I2C wakeup from Stop mode(s). 244 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 245 | * the configuration information for the specified I2Cx peripheral. 246 | * @retval HAL status 247 | */ 248 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) 249 | { 250 | /* Check the parameters */ 251 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 252 | 253 | if (hi2c->State == HAL_I2C_STATE_READY) 254 | { 255 | /* Process Locked */ 256 | __HAL_LOCK(hi2c); 257 | 258 | hi2c->State = HAL_I2C_STATE_BUSY; 259 | 260 | /* Disable the selected I2C peripheral */ 261 | __HAL_I2C_DISABLE(hi2c); 262 | 263 | /* Enable wakeup from stop mode */ 264 | hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); 265 | 266 | __HAL_I2C_ENABLE(hi2c); 267 | 268 | hi2c->State = HAL_I2C_STATE_READY; 269 | 270 | /* Process Unlocked */ 271 | __HAL_UNLOCK(hi2c); 272 | 273 | return HAL_OK; 274 | } 275 | else 276 | { 277 | return HAL_BUSY; 278 | } 279 | } 280 | /** 281 | * @} 282 | */ 283 | 284 | /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions 285 | * @brief Fast Mode Plus Functions 286 | * 287 | @verbatim 288 | =============================================================================== 289 | ##### Fast Mode Plus Functions ##### 290 | =============================================================================== 291 | [..] This section provides functions allowing to: 292 | (+) Configure Fast Mode Plus 293 | 294 | @endverbatim 295 | * @{ 296 | */ 297 | 298 | /** 299 | * @brief Enable the I2C fast mode plus driving capability. 300 | * @param ConfigFastModePlus Selects the pin. 301 | * This parameter can be one of the @ref I2CEx_FastModePlus values 302 | * @note For I2C1, fast mode plus driving capability can be enabled on all selected 303 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 304 | * on each one of the following pins PB6, PB7, PB8 and PB9. 305 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 306 | * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 307 | * @note For all I2C2 pins fast mode plus driving capability can be enabled 308 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 309 | * @note For all I2C3 pins fast mode plus driving capability can be enabled 310 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 311 | * @retval None 312 | */ 313 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) 314 | { 315 | /* Check the parameter */ 316 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 317 | 318 | /* Enable SYSCFG clock */ 319 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 320 | 321 | /* Enable fast mode plus driving capability for selected pin */ 322 | SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 323 | } 324 | 325 | /** 326 | * @brief Disable the I2C fast mode plus driving capability. 327 | * @param ConfigFastModePlus Selects the pin. 328 | * This parameter can be one of the @ref I2CEx_FastModePlus values 329 | * @note For I2C1, fast mode plus driving capability can be disabled on all selected 330 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 331 | * on each one of the following pins PB6, PB7, PB8 and PB9. 332 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 333 | * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 334 | * @note For all I2C2 pins fast mode plus driving capability can be disabled 335 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 336 | * @note For all I2C3 pins fast mode plus driving capability can be disabled 337 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 338 | * @retval None 339 | */ 340 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) 341 | { 342 | /* Check the parameter */ 343 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 344 | 345 | /* Enable SYSCFG clock */ 346 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 347 | 348 | /* Disable fast mode plus driving capability for selected pin */ 349 | CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 350 | } 351 | /** 352 | * @} 353 | */ 354 | /** 355 | * @} 356 | */ 357 | 358 | #endif /* HAL_I2C_MODULE_ENABLED */ 359 | /** 360 | * @} 361 | */ 362 | 363 | /** 364 | * @} 365 | */ 366 | 367 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 368 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_pwr_ex.c 4 | * @author MCD Application Team 5 | * @brief Extended PWR HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the Power Controller (PWR) peripheral: 8 | * + Extended Initialization and de-initialization functions 9 | * + Extended Peripheral Control functions 10 | * 11 | ****************************************************************************** 12 | * @attention 13 | * 14 | *

© Copyright (c) 2016 STMicroelectronics. 15 | * All rights reserved.

16 | * 17 | * This software component is licensed by ST under BSD 3-Clause license, 18 | * the "License"; You may not use this file except in compliance with the 19 | * License. You may obtain a copy of the License at: 20 | * opensource.org/licenses/BSD-3-Clause 21 | * 22 | ****************************************************************************** 23 | */ 24 | 25 | /* Includes ------------------------------------------------------------------*/ 26 | #include "stm32f3xx_hal.h" 27 | 28 | /** @addtogroup STM32F3xx_HAL_Driver 29 | * @{ 30 | */ 31 | 32 | /** @defgroup PWREx PWREx 33 | * @brief PWREx HAL module driver 34 | * @{ 35 | */ 36 | 37 | #ifdef HAL_PWR_MODULE_ENABLED 38 | 39 | /* Private typedef -----------------------------------------------------------*/ 40 | /* Private define ------------------------------------------------------------*/ 41 | /** @defgroup PWREx_Private_Constants PWR Extended Private Constants 42 | * @{ 43 | */ 44 | #define PVD_MODE_IT (0x00010000U) 45 | #define PVD_MODE_EVT (0x00020000U) 46 | #define PVD_RISING_EDGE (0x00000001U) 47 | #define PVD_FALLING_EDGE (0x00000002U) 48 | /** 49 | * @} 50 | */ 51 | 52 | /* Private macro -------------------------------------------------------------*/ 53 | /* Private variables ---------------------------------------------------------*/ 54 | /* Private function prototypes -----------------------------------------------*/ 55 | /* Exported functions ---------------------------------------------------------*/ 56 | 57 | /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions 58 | * @{ 59 | */ 60 | 61 | /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions 62 | * @brief Extended Peripheral Control functions 63 | * 64 | @verbatim 65 | 66 | =============================================================================== 67 | ##### Peripheral Extended control functions ##### 68 | =============================================================================== 69 | *** PVD configuration (present on all other devices than STM32F3x8 devices) *** 70 | ========================= 71 | [..] 72 | (+) The PVD is used to monitor the VDD power supply by comparing it to a 73 | threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 74 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 75 | than the PVD threshold. This event is internally connected to the EXTI 76 | line16 and can generate an interrupt if enabled. This is done through 77 | __HAL_PWR_PVD_EXTI_ENABLE_IT() macro 78 | (+) The PVD is stopped in Standby mode. 79 | -@- PVD is not available on STM32F3x8 Product Line 80 | 81 | 82 | *** Voltage regulator *** 83 | ========================= 84 | [..] 85 | (+) The voltage regulator is always enabled after Reset. It works in three different 86 | modes. 87 | In Run mode, the regulator supplies full power to the 1.8V domain (core, memories 88 | and digital peripherals). 89 | In Stop mode, the regulator supplies low power to the 1.8V domain, preserving 90 | contents of registers and SRAM. 91 | In Stop mode, the regulator is powered off. The contents of the registers and SRAM 92 | are lost except for the Standby circuitry and the Backup Domain. 93 | Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the 94 | microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage. 95 | 96 | 97 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 98 | than the PVD threshold. This event is internally connected to the EXTI 99 | line16 and can generate an interrupt if enabled. This is done through 100 | __HAL_PWR_PVD_EXTI_ENABLE_IT() macro 101 | (+) The PVD is stopped in Standby mode. 102 | 103 | 104 | *** SDADC power configuration *** 105 | ================================ 106 | [..] 107 | (+) On STM32F373xC/STM32F378xx devices, there are up to 108 | 3 SDADC instances that can be enabled/disabled. 109 | 110 | @endverbatim 111 | * @{ 112 | */ 113 | 114 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 115 | defined(STM32F302xC) || defined(STM32F303xC) || \ 116 | defined(STM32F303x8) || defined(STM32F334x8) || \ 117 | defined(STM32F301x8) || defined(STM32F302x8) || \ 118 | defined(STM32F373xC) 119 | 120 | /** 121 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 122 | * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 123 | * information for the PVD. 124 | * @note Refer to the electrical characteristics of your device datasheet for 125 | * more details about the voltage threshold corresponding to each 126 | * detection level. 127 | * @retval None 128 | */ 129 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 130 | { 131 | /* Check the parameters */ 132 | assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 133 | assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 134 | 135 | /* Set PLS[7:5] bits according to PVDLevel value */ 136 | MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 137 | 138 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 139 | __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 140 | __HAL_PWR_PVD_EXTI_DISABLE_IT(); 141 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 142 | 143 | /* Configure interrupt mode */ 144 | if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 145 | { 146 | __HAL_PWR_PVD_EXTI_ENABLE_IT(); 147 | } 148 | 149 | /* Configure event mode */ 150 | if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 151 | { 152 | __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 153 | } 154 | 155 | /* Configure the edge */ 156 | if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 157 | { 158 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 159 | } 160 | 161 | if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 162 | { 163 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 164 | } 165 | } 166 | 167 | /** 168 | * @brief Enables the Power Voltage Detector(PVD). 169 | * @retval None 170 | */ 171 | void HAL_PWR_EnablePVD(void) 172 | { 173 | SET_BIT(PWR->CR, PWR_CR_PVDE); 174 | } 175 | 176 | /** 177 | * @brief Disables the Power Voltage Detector(PVD). 178 | * @retval None 179 | */ 180 | void HAL_PWR_DisablePVD(void) 181 | { 182 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); 183 | } 184 | 185 | /** 186 | * @brief This function handles the PWR PVD interrupt request. 187 | * @note This API should be called under the PVD_IRQHandler(). 188 | * @retval None 189 | */ 190 | void HAL_PWR_PVD_IRQHandler(void) 191 | { 192 | /* Check PWR exti flag */ 193 | if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 194 | { 195 | /* PWR PVD interrupt user callback */ 196 | HAL_PWR_PVDCallback(); 197 | 198 | /* Clear PWR Exti pending bit */ 199 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 200 | } 201 | } 202 | 203 | /** 204 | * @brief PWR PVD interrupt callback 205 | * @retval None 206 | */ 207 | __weak void HAL_PWR_PVDCallback(void) 208 | { 209 | /* NOTE : This function Should not be modified, when the callback is needed, 210 | the HAL_PWR_PVDCallback could be implemented in the user file 211 | */ 212 | } 213 | 214 | #endif /* STM32F302xE || STM32F303xE || */ 215 | /* STM32F302xC || STM32F303xC || */ 216 | /* STM32F303x8 || STM32F334x8 || */ 217 | /* STM32F301x8 || STM32F302x8 || */ 218 | /* STM32F373xC */ 219 | 220 | #if defined(STM32F373xC) || defined(STM32F378xx) 221 | 222 | /** 223 | * @brief Enables the SDADC peripheral functionaliy 224 | * @param Analogx specifies the SDADC peripheral instance. 225 | * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. 226 | * @retval None 227 | */ 228 | void HAL_PWREx_EnableSDADC(uint32_t Analogx) 229 | { 230 | /* Check the parameters */ 231 | assert_param(IS_PWR_SDADC_ANALOG(Analogx)); 232 | 233 | /* Enable PWR clock interface for SDADC use */ 234 | __HAL_RCC_PWR_CLK_ENABLE(); 235 | 236 | PWR->CR |= Analogx; 237 | } 238 | 239 | /** 240 | * @brief Disables the SDADC peripheral functionaliy 241 | * @param Analogx specifies the SDADC peripheral instance. 242 | * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. 243 | * @retval None 244 | */ 245 | void HAL_PWREx_DisableSDADC(uint32_t Analogx) 246 | { 247 | /* Check the parameters */ 248 | assert_param(IS_PWR_SDADC_ANALOG(Analogx)); 249 | 250 | PWR->CR &= ~Analogx; 251 | } 252 | 253 | #endif /* STM32F373xC || STM32F378xx */ 254 | 255 | /** 256 | * @} 257 | */ 258 | 259 | /** 260 | * @} 261 | */ 262 | 263 | #endif /* HAL_PWR_MODULE_ENABLED */ 264 | /** 265 | * @} 266 | */ 267 | 268 | /** 269 | * @} 270 | */ 271 | 272 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 273 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/STM32F303RETX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | ** @file : LinkerScript.ld 5 | ** 6 | ** @author : Auto-generated by STM32CubeIDE 7 | ** 8 | ** @brief : Linker script for STM32F303RETx Device from STM32F3 series 9 | ** 512Kbytes FLASH 10 | ** 16Kbytes CCMRAM 11 | ** 64Kbytes RAM 12 | ** 13 | ** Set heap size, stack size and stack location according 14 | ** to application requirements. 15 | ** 16 | ** Set memory bank area and size if external memory is used 17 | ** 18 | ** Target : STMicroelectronics STM32 19 | ** 20 | ** Distribution: The file is distributed as is, without any warranty 21 | ** of any kind. 22 | ** 23 | ****************************************************************************** 24 | ** @attention 25 | ** 26 | ** Copyright (c) 2022 STMicroelectronics. 27 | ** All rights reserved. 28 | ** 29 | ** This software is licensed under terms that can be found in the LICENSE file 30 | ** in the root directory of this software component. 31 | ** If no LICENSE file comes with this software, it is provided AS-IS. 32 | ** 33 | ****************************************************************************** 34 | */ 35 | 36 | /* Entry Point */ 37 | ENTRY(Reset_Handler) 38 | 39 | /* Highest address of the user mode stack */ 40 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ 41 | 42 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 43 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 44 | 45 | /* Memories definition */ 46 | MEMORY 47 | { 48 | CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 16K 49 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K 50 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K 51 | } 52 | 53 | /* Sections */ 54 | SECTIONS 55 | { 56 | /* The startup code into "FLASH" Rom type memory */ 57 | .isr_vector : 58 | { 59 | . = ALIGN(4); 60 | KEEP(*(.isr_vector)) /* Startup code */ 61 | . = ALIGN(4); 62 | } >FLASH 63 | 64 | /* The program code and other data into "FLASH" Rom type memory */ 65 | .text : 66 | { 67 | . = ALIGN(4); 68 | *(.text) /* .text sections (code) */ 69 | *(.text*) /* .text* sections (code) */ 70 | *(.glue_7) /* glue arm to thumb code */ 71 | *(.glue_7t) /* glue thumb to arm code */ 72 | *(.eh_frame) 73 | 74 | KEEP (*(.init)) 75 | KEEP (*(.fini)) 76 | 77 | . = ALIGN(4); 78 | _etext = .; /* define a global symbols at end of code */ 79 | } >FLASH 80 | 81 | /* Constant data into "FLASH" Rom type memory */ 82 | .rodata : 83 | { 84 | . = ALIGN(4); 85 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 86 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 87 | . = ALIGN(4); 88 | } >FLASH 89 | 90 | .ARM.extab : { 91 | . = ALIGN(4); 92 | *(.ARM.extab* .gnu.linkonce.armextab.*) 93 | . = ALIGN(4); 94 | } >FLASH 95 | 96 | .ARM : { 97 | . = ALIGN(4); 98 | __exidx_start = .; 99 | *(.ARM.exidx*) 100 | __exidx_end = .; 101 | . = ALIGN(4); 102 | } >FLASH 103 | 104 | .preinit_array : 105 | { 106 | . = ALIGN(4); 107 | PROVIDE_HIDDEN (__preinit_array_start = .); 108 | KEEP (*(.preinit_array*)) 109 | PROVIDE_HIDDEN (__preinit_array_end = .); 110 | . = ALIGN(4); 111 | } >FLASH 112 | 113 | .init_array : 114 | { 115 | . = ALIGN(4); 116 | PROVIDE_HIDDEN (__init_array_start = .); 117 | KEEP (*(SORT(.init_array.*))) 118 | KEEP (*(.init_array*)) 119 | PROVIDE_HIDDEN (__init_array_end = .); 120 | . = ALIGN(4); 121 | } >FLASH 122 | 123 | .fini_array : 124 | { 125 | . = ALIGN(4); 126 | PROVIDE_HIDDEN (__fini_array_start = .); 127 | KEEP (*(SORT(.fini_array.*))) 128 | KEEP (*(.fini_array*)) 129 | PROVIDE_HIDDEN (__fini_array_end = .); 130 | . = ALIGN(4); 131 | } >FLASH 132 | 133 | /* Used by the startup to initialize data */ 134 | _sidata = LOADADDR(.data); 135 | 136 | /* Initialized data sections into "RAM" Ram type memory */ 137 | .data : 138 | { 139 | . = ALIGN(4); 140 | _sdata = .; /* create a global symbol at data start */ 141 | *(.data) /* .data sections */ 142 | *(.data*) /* .data* sections */ 143 | *(.RamFunc) /* .RamFunc sections */ 144 | *(.RamFunc*) /* .RamFunc* sections */ 145 | 146 | . = ALIGN(4); 147 | _edata = .; /* define a global symbol at data end */ 148 | 149 | } >RAM AT> FLASH 150 | 151 | _siccmram = LOADADDR(.ccmram); 152 | 153 | /* CCM-RAM section 154 | * 155 | * IMPORTANT NOTE! 156 | * If initialized variables will be placed in this section, 157 | * the startup code needs to be modified to copy the init-values. 158 | */ 159 | .ccmram : 160 | { 161 | . = ALIGN(4); 162 | _sccmram = .; /* create a global symbol at ccmram start */ 163 | *(.ccmram) 164 | *(.ccmram*) 165 | 166 | . = ALIGN(4); 167 | _eccmram = .; /* create a global symbol at ccmram end */ 168 | } >CCMRAM AT> FLASH 169 | 170 | /* Uninitialized data section into "RAM" Ram type memory */ 171 | . = ALIGN(4); 172 | .bss : 173 | { 174 | /* This is used by the startup in order to initialize the .bss section */ 175 | _sbss = .; /* define a global symbol at bss start */ 176 | __bss_start__ = _sbss; 177 | *(.bss) 178 | *(.bss*) 179 | *(COMMON) 180 | 181 | . = ALIGN(4); 182 | _ebss = .; /* define a global symbol at bss end */ 183 | __bss_end__ = _ebss; 184 | } >RAM 185 | 186 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ 187 | ._user_heap_stack : 188 | { 189 | . = ALIGN(8); 190 | PROVIDE ( end = . ); 191 | PROVIDE ( _end = . ); 192 | . = . + _Min_Heap_Size; 193 | . = . + _Min_Stack_Size; 194 | . = ALIGN(8); 195 | } >RAM 196 | 197 | /* Remove information from the compiler libraries */ 198 | /DISCARD/ : 199 | { 200 | libc.a ( * ) 201 | libm.a ( * ) 202 | libgcc.a ( * ) 203 | } 204 | 205 | .ARM.attributes 0 : { *(.ARM.attributes) } 206 | } 207 | -------------------------------------------------------------------------------- /stm32_i2c_slave_example/stm32_i2c_slave_example.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | File.Version=6 3 | I2C1.I2C_Speed_Mode=I2C_Fast 4 | I2C1.IPParameters=OwnAddress,I2C_Speed_Mode,Timing 5 | I2C1.OwnAddress=0x44 6 | I2C1.Timing=0x0000020B 7 | KeepUserPlacement=false 8 | Mcu.CPN=STM32F303RET6 9 | Mcu.Family=STM32F3 10 | Mcu.IP0=I2C1 11 | Mcu.IP1=NVIC 12 | Mcu.IP2=RCC 13 | Mcu.IP3=SYS 14 | Mcu.IPNb=4 15 | Mcu.Name=STM32F303R(D-E)Tx 16 | Mcu.Package=LQFP64 17 | Mcu.Pin0=PA13 18 | Mcu.Pin1=PA14 19 | Mcu.Pin2=PA15 20 | Mcu.Pin3=PB7 21 | Mcu.Pin4=VP_SYS_VS_Systick 22 | Mcu.PinsNb=5 23 | Mcu.ThirdPartyNb=0 24 | Mcu.UserConstants= 25 | Mcu.UserName=STM32F303RETx 26 | MxCube.Version=6.5.0 27 | MxDb.Version=DB.6.0.50 28 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 29 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 30 | NVIC.ForceEnableDMAVector=true 31 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 32 | NVIC.I2C1_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true 33 | NVIC.I2C1_EV_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true 34 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 35 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 36 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 37 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 38 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 39 | NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true 40 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true 41 | PA13.Mode=Serial_Wire 42 | PA13.Signal=SYS_JTMS-SWDIO 43 | PA14.Mode=Serial_Wire 44 | PA14.Signal=SYS_JTCK-SWCLK 45 | PA15.Mode=I2C 46 | PA15.Signal=I2C1_SCL 47 | PB7.Mode=I2C 48 | PB7.Signal=I2C1_SDA 49 | PinOutPanel.RotationAngle=0 50 | ProjectManager.AskForMigrate=true 51 | ProjectManager.BackupPrevious=false 52 | ProjectManager.CompilerOptimize=6 53 | ProjectManager.ComputerToolchain=false 54 | ProjectManager.CoupleFile=false 55 | ProjectManager.CustomerFirmwarePackage= 56 | ProjectManager.DefaultFWLocation=true 57 | ProjectManager.DeletePrevious=true 58 | ProjectManager.DeviceId=STM32F303RETx 59 | ProjectManager.FirmwarePackage=STM32Cube FW_F3 V1.11.3 60 | ProjectManager.FreePins=false 61 | ProjectManager.HalAssertFull=false 62 | ProjectManager.HeapSize=0x200 63 | ProjectManager.KeepUserCode=true 64 | ProjectManager.LastFirmware=true 65 | ProjectManager.LibraryCopy=1 66 | ProjectManager.MainLocation=Core/Src 67 | ProjectManager.NoMain=false 68 | ProjectManager.PreviousToolchain= 69 | ProjectManager.ProjectBuild=false 70 | ProjectManager.ProjectFileName=stm32_i2c_slave_example.ioc 71 | ProjectManager.ProjectName=stm32_i2c_slave_example 72 | ProjectManager.RegisterCallBack= 73 | ProjectManager.StackSize=0x400 74 | ProjectManager.TargetToolchain=STM32CubeIDE 75 | ProjectManager.ToolChainLocation= 76 | ProjectManager.UnderRoot=true 77 | ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false 78 | RCC.ADC12outputFreq_Value=16000000 79 | RCC.ADC34outputFreq_Value=16000000 80 | RCC.AHBFreq_Value=8000000 81 | RCC.APB1Freq_Value=8000000 82 | RCC.APB2Freq_Value=8000000 83 | RCC.CortexFreq_Value=8000000 84 | RCC.FamilyName=M 85 | RCC.HSE_VALUE=8000000 86 | RCC.HSI_VALUE=8000000 87 | RCC.I2C1Freq_Value=8000000 88 | RCC.I2C2Freq_Value=8000000 89 | RCC.I2C3Freq_Value=8000000 90 | RCC.IPParameters=ADC12outputFreq_Value,ADC34outputFreq_Value,AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,CortexFreq_Value,FamilyName,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LSE_VALUE,LSI_VALUE,PLLCLKFreq_Value,PLLMCOFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOOutput2Freq_Value 91 | RCC.LSE_VALUE=32768 92 | RCC.LSI_VALUE=40000 93 | RCC.PLLCLKFreq_Value=16000000 94 | RCC.PLLMCOFreq_Value=16000000 95 | RCC.RTCFreq_Value=40000 96 | RCC.RTCHSEDivFreq_Value=250000 97 | RCC.SYSCLKFreq_VALUE=8000000 98 | RCC.UART4Freq_Value=8000000 99 | RCC.UART5Freq_Value=8000000 100 | RCC.USART1Freq_Value=8000000 101 | RCC.USART2Freq_Value=8000000 102 | RCC.USART3Freq_Value=8000000 103 | RCC.USBFreq_Value=16000000 104 | RCC.VCOOutput2Freq_Value=8000000 105 | VP_SYS_VS_Systick.Mode=SysTick 106 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 107 | board=custom 108 | isbadioc=false 109 | --------------------------------------------------------------------------------