2 |
3 | This is a quickstart guide to easily deploy ρ-VEX, mainly focused on the utilization
4 | with a Xilinx University Program Virtex-II Pro FPGA board by Digilent. If
5 | you want to use this guide together with another FPGA platform, you should first add
6 | the definitions of your board to the workflow as described later.
7 |
8 |
Table of Contents
9 |
10 |
11 | ## Requirements ##
12 | * A [Xilinx University Program Virtex-II Pro board](http://www.digilentinc.com/Products/Detail.cfm?av1=Products&Nav2=Programmable&Prod=XUPV2P)
13 | * PC running Linux or Windows1
14 | * Xilinx ISE Suite (tested with 8.1.03i, should work with later versions too)
15 |
16 | 1 When you want to make use of the Makefile method described below on a Windows machine, a Cygwin installation should be present with GNU Make. Xilinx EDK automatically installs a version of Cygwin. However, some GNU tools like `cat` are not included. This results in an error while bundling the log files after synthesis. This can be safely ignored.
17 |
18 | ## Quickstart - Deploying ρ-VEX on an FPGA ##
19 | - [Download](https://github.com/tvanas/r-vex/archive/MSc.zip) a release snapshot of ρ-VEX, or clone the [master](https://github.com/tvanas/r-vex/tree/master) branch.
20 | - Inside the r-VEX/src/ directory, synthesize ρ-VEX by entering the following command:
21 | ```
22 | make v2p
23 | ```
24 | - After the synthesis process has completed, the generated bit-file can be uploaded to the FPGA board by entering:
25 | ```
26 | make fpga
27 | ```
28 | - Connect a serial cable to the RS-232 interface on the XUP V2P board. Connect the other side of the cable to a PC, and start a terminal application, like Minicom (Linux), Putty or Hyperterminal (Windows). Connect using the following settings: _115200 bps transfer rate, 8 data bits, no parity_
29 | - Press button SW2 on the XUP V2P board, which acts as the reset button. In the terminal application, you will see the contents of the first 16 data memory addresses, as well as a cycle counter.
30 |
31 | By default, an application to calculate the 45th Fibonacci number is loaded and pre-synthesized. The VEX assembly source file of the default application is [fibonacci.s](https://github.com/tvanas/r-vex/blob/master/demos/fibonacci.s), which can be found in the [demos](https://github.com/tvanas/r-vex/tree/master/demos) directory. The output of ρ-VEX transmitted over the UART is the following:
32 |
33 | ```
34 | r-VEX
35 | -----
36 | Cycles: 0x00000231
37 |
38 | Data memory dump
39 |
40 | addr | contents
41 | -----+-----------
42 | 0x00 | 0x43A53F82
43 | 0x01 | 0x00000000
44 | 0x02 | 0x00000000
45 | 0x03 | 0x00000000
46 | 0x04 | 0x00000000
47 | 0x05 | 0x00000000
48 | 0x06 | 0x00000000
49 | 0x07 | 0x00000000
50 | 0x08 | 0x00000000
51 | 0x09 | 0x00000000
52 | 0x0A | 0x00000000
53 | 0x0B | 0x00000000
54 | 0x0C | 0x00000000
55 | 0x0D | 0x00000000
56 | 0x0E | 0x00000000
57 | 0x0F | 0x00000000
58 | ```
59 |
60 | ## Assembling and Running Other Code ##
61 |
62 | The instruction memory ROM can be found in the file [i\_mem.vhd](https://github.com/tvanas/r-vex/blob/master/r-VEX/src/i_mem.vhd). A new instruction ROM file can be generated by the ρ-ASM tool. This tool requires a UNIX operating system with the GNU C libraries.
63 |
64 | - To compile ρ-ASM, go to the [r-ASM/src/](https://github.com/tvanas/r-vex/tree/master/r-ASM/src) directory, and enter the command
65 | ```
66 | make
67 | ```
68 | - To assemble a VEX assembly file, run ρ-ASM by entering the following command:
69 | ```
70 | ./rasm
71 | ```
72 | - By default, the resulting instruction ROM is written to `i_mem.vhd` in the current directory. Copy or move this file to the ρ-VEX source directory. When using the standard repository structure, this can be accomplished by entering
73 | ```
74 | mv i_mem.vhd ../../r-VEX/src/
75 | ```
76 | - Now, repeat the steps from the Quickstart described earlier.
77 |
78 | To see more options of ρ-ASM (like enabling debug output) run the application without any arguments. Some demo applications with their corresponding outputs can be found in the [demos](https://github.com/tvanas/r-vex/tree/master/demos) directory.
79 |
80 | ## Using ρ-OPS ##
81 | This guide on adding ρ-OPS to an ρ-VEX implementation is based on the example of adding the **FIB3** and **FIB4** operations, as used in our Fibonacci's Sequence benchmark application.
82 |
83 | ### Adapting ρ-VEX ###
84 | - Determine what Functional Units will execute the operation. An unused ρ-OPS opcode can be optained from OperationsSemantics.
85 | - In [r-vex\_pkg.vhd](https://github.com/tvanas/r-vex/blob/master/r-VEX/src/r-vex_pkg.vhd), constant definitions should be added for the new operations:
86 | ```
87 | constant ALU_FIB4 : std_logic_vector(6 downto 0) := "1000010";
88 | constant ALU_FIB3 : std_logic_vector(6 downto 0) := "1101100";
89 | ```
90 | - In the determined Functional Unit, support for the new operations should be added in the corresponding VHDL file. In our benchmark, lines 9 - 12 are added in [alu.vhd](https://github.com/tvanas/r-vex/blob/master/r-VEX/src/alu.vhd) from the code snippet below.
91 | ```
92 | alu_control : process(clk, reset)
93 | begin
94 | if (reset = '1') then
95 | out_valid <= '0';
96 | result_s <= (others => '0');
97 | cout_s <= '0';
98 | elsif (clk = '1' and clk'event) then
99 | ...
100 | elsif std_match(aluop, ALU_FIB4) then
101 | result_s <= f_FIB4 (src1, src2);
102 | elsif std_match(aluop, ALU_FIB3) then
103 | result_s <= f_FIB3 (src1, src2);
104 | ...
105 | end if;
106 | end process alu_control;
107 | ```
108 | - Functions and function prototypes should be added to the corresponding file. In our example, the code below was added to [alu\_operations.vhd](https://github.com/tvanas/r-vex/blob/master/r-VEX/src/alu_operations.vhd).
109 | ```
110 | function f_FIB4 ( s1, s2 : std_logic_vector(31 downto 0))
111 | return std_logic_vector;
112 |
113 | function f_FIB3 ( s1, s2 : std_logic_vector(31 downto 0))
114 | return std_logic_vector;
115 |
116 | ...
117 |
118 | function f_FIB4 ( s1, s2 : std_logic_vector(31 downto 0))
119 | return std_logic_vector is
120 | begin
121 | return (s1 + s2 + s2 + s1 + s2 + s2 + s1 + s2);
122 | end function f_FIB4;
123 |
124 | function f_FIB3 ( s1, s2 : std_logic_vector(31 downto 0))
125 | return std_logic_vector is
126 | begin
127 | return (s1 + s2 + s2 + s1 + s2);
128 | end function f_FIB3;
129 | ```
130 |
131 |
132 | ### Adapting ρ-ASM ###
133 | To adapt ρ-ASM to support the new ρ-OPS, two small additions should be made in [syllable.h](https://github.com/tvanas/r-vex/blob/master/r-ASM/src/syllable.h). A new opcode define should be made, as well as an addition of the new opcode's mnemonic to the `operation_table` lookup table (lines 11 - 12).
134 |
135 | ```
136 | #define FIB3 108
137 | #define FIB4 66
138 |
139 | ...
140 |
141 | static struct operation_t {
142 | const char *operation;
143 | int opcode;
144 | } operation_table[] = {
145 | ...
146 | { "fib3", FIB3 },
147 | { "fib4", FIB4 },
148 | ...
149 | };
150 | ```
151 |
152 | ## Running Modelsim Simulations ##
153 |
154 | To run Modelsim simulations within the workflow, you should have installed a version of Mentor Graphics Modelsim (we simulated with the SE 6.3d edition). To run the simulations using the system wrapper testbench [r-VEX/testbenches/tb\_system.vhd](https://github.com/tvanas/r-vex/blob/master/r-VEX/testbenches/tb_system.vhd) (which simulates the execution of the current instruction memory in [i\_mem.vhd](https://github.com/tvanas/r-vex/blob/master/r-VEX/src/i_mem.vhd)), enter the following command in [r-VEX/src/](https://github.com/tvanas/r-vex/tree/master/r-VEX/src):
155 | ```
156 | make modelsim
157 | ```
158 |
159 | ## Adding Support For Other FPGA Boards ##
160 |
161 | To add support for other FPGA boards with Xilinx a FPGA in this workflow, the file [r-VEX/src/Makefile](https://github.com/tvanas/r-vex/blob/master/r-VEX/src/Makefile) should be edited. The following changes should be applied:
162 |
163 | - Choose a mnemonic for your new target. For example, we used `v2p` for the XUP V2P board containing a Virtex-II Pro FPGA. This mnemonic will be referred to as ``. Check the Xilinx identifier for this FPGA. For example, the identifier for the Virtex-II Pro chip we used is _xc2vp30-ff896-7_. This identifier will be referred to as ``.
164 | - Add the Xilinx FPGA identifier as a new variable. Use the following template:
165 | ```
166 | XIL_PART_r-vex_ =
167 | ```
168 | - Add a 'help' text to the `default` _Make_ target.
169 | - Create a new _Make_ target according to this template:
170 | ```
171 | : r-vex_.deps r-vex_.bit log_.txt
172 | ```
173 | - Create a new _Make_ target `r-vex_.ut` and let it write your preferred options to the `.ut` file.2
174 | - Create a new _Make_ target `r-vex_.xst` and let it write your preferred options to the XST configuration file.2
175 | - Create a new _Make_ target `r-vex_.ucf` and let it write your UCF user constraints to the `.ucf` file.2
176 | - Create a new _Make_ target `r-vex_.cmd` and let it write the commands for Xilinx IMPACT to program your FPGA.2
177 | - Set the constant `ACTIVE_LOW` in [r-VEX/src/r-vex\_pkg.vhd](https://github.com/tvanas/r-vex/blob/master/r-VEX/src/r-vex_pkg.vhd#L41) (line 41) to `1` in case the board uses 'active low' logic (like the XUP V2P board) or to `0` in case the board uses 'active high' logic. **If this constant is defined wrong, your board won't do anything.**
178 |
179 |
180 | 2As a reference, you could use the _Make_ target with the mnemonic `v2p`.
181 |
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/README.md:
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1 | # ρ-VEX: A Reconfigurable and Extensible VLIW Processor #
2 |
3 | ρ-VEX is an open source VLIW processor with an accompanied development framework. The project started as the MSc project of Thijs van As while he was at the [Computer Engineering Laboratory](http://ce.et.tudelft.nl) at Delft University of Technology.
4 |
5 | Today, multiple research groups are still [actively working](https://scholar.google.com/scholar?oi=bibs&hl=en&cites=5509474927382744618) on extending and improving the ρ-VEX framework.
6 |
7 | This project was originally hosted on Google Code (at r-vex.googlecode.com).
8 |
9 | ## About ρ-VEX ##
10 | ρ-VEX is an open source reconfigurable and extensible Very-Long Instruction Word (VLIW) processor, accompanied by a development framework consisting of a VEX assembler, ρ-ASM. The processor architecture is based on the VEX ISA, as introduced by [J.A. Fisher et al.](http://www.vliw.org/). The VEX ISA offers a scalable technology platform for embedded VLIW processors, that allows variation in many aspects, including instruction issue-width, organization of functional units, and instruction set. The ρ-VEX source code is described in VHDL. ρ-ASM is written in C.
11 |
12 | A software development compiler toolchain for VEX is made publicly available by [Hewlett-Packard](http://www.hpl.hp.com/downloads/vex/). The reasons VEX was chosen as the ISA are merely its extensibility and the quality of the available compiler. The design provides mechanisms that allow parametric extensibility of ρ-VEX. Both reconfigurable operations, as well as the versatility of VEX machine models are supported by ρ-VEX. The processor and framework are targeted at VLIW prototyping research and embedded processor design.
13 |
14 | The name ρ-VEX stands for 'reconfigurable VEX' processor. Because the letter _Rho_ (_P_ or _ρ_) is the Greek analogous for the Roman _R_ or _r_, ρ-VEX is pronounced as _r-VEX_. This is also the correct spelling when no Greek letters can be used.
15 |
16 | ## Getting Started ##
17 | To start experimenting with ρ-VEX, read the [Quickstart Guide](https://github.com/tvanas/r-vex/blob/master/QuickstartGuide.md) and [download](https://github.com/tvanas/r-vex/archive/MSc.zip) a release snapshot, or clone [master](https://github.com/tvanas/r-vex/tree/master). When you have a [Xilinx University Program Virtex-II Pro Board by Digilent](http://www.digilentinc.com/Products/Detail.cfm?av1=Products&Nav2=Programmable&Prod=XUPV2P), you should have ρ-VEX running within moments.
18 |
19 | ## Documentation ##
20 | * [ρ-VEX Quickstart Guide](https://github.com/tvanas/r-vex/blob/master/QuickstartGuide.md)
21 | * [ρ-VEX Machine Operations and Semantics](https://github.com/tvanas/r-vex/blob/master/OperationsAndSemantics.md)
22 | * [Thijs' MSc Thesis with extensive documentation about ρ-VEX' design and implementation](https://github.com/tvanas/r-vex/blob/master/downloads/thesis_tvanas.pdf?raw=true)
23 | * [ρ-VEX: A Reconfigurable and Extensible VLIW Softcore Processor](https://github.com/tvanas/r-vex/blob/master/downloads/r-vex_icfpt08.pdf?raw=true) (published at [ICFPT'08](http://www.icfpt.org/))
24 | * [instruction\_layout.txt](https://github.com/tvanas/r-vex/blob/master/doc/instruction_layout.txt)
25 | * [syllable\_layout.txt](https://github.com/tvanas/r-vex/blob/master/doc/syllable_layout.txt)
26 |
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/demos/dummy.s:
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1 | # Dummy demo
2 | # -----------------------
3 | #
4 | # Data memory contents after running:
5 | # 0x00: 0xFF
6 | # 0x01: 0x0F
7 | # 0x02: 0xEF1
8 |
9 | add $r0.15 = $r0.0, 1
10 | mov $r0.1 = $r0.0
11 | mov $r0.2 = $r0.0
12 | ;;
13 | add $r0.1 = $r0.0, 255
14 | ;;
15 | add $r0.2 = $r0.0, 15
16 | ;;
17 | mpyll $r0.3 = $r0.1, $r0.2 # $r0.3 = $r0.1 * $r0.2
18 | ;;
19 | stw 0x0[$r0.15] = $r0.1
20 | ;;
21 | stw 0x4[$r0.15] = $r0.2
22 | ;;
23 | stw 0x8[$r0.15] = $r0.3
24 | ;;
25 |
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/demos/fibonacci.s:
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1 | # Fibonacci Sequence demo
2 | # -----------------------
3 | #
4 | # Calculates 45th Fibonacci number, and stores it in data memory at address 0x00
5 |
6 | add $r0.15 = $r0.0, 1
7 | mov $r0.1 = $r0.0
8 | add $r0.10 = $r0.0, 44 # 44 + 1 iterations
9 | add $r0.2 = $r0.0, 1
10 | ;;
11 | LABEL_BEGIN:
12 | add $r0.2 = $r0.1, $r0.2
13 | add $r0.3 = $r0.0, $r0.2
14 | cmpeq $b0.0 = $r0.9, $r0.10 # if ($r0.9 == $r0.10) $b0.0 = 1;
15 | br $b0.0, LABEL_END # if ($b0.0 == 1) goto LABEL_END;
16 | ;;
17 | add $r0.9 = $r0.9, 1
18 | add $r0.1 = $r0.0, $r0.3
19 | goto LABEL_BEGIN
20 | ;;
21 | LABEL_END:
22 | stw 0x0[$r0.15] = $r0.1
23 | mov $r0.9 = $r0.0
24 | ;;
25 |
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/demos/reference_outputs/dummy.txt:
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1 | r-VEX
2 | -----
3 | Cycles: 0x0000002D
4 |
5 | Data memory dump
6 |
7 | addr | contents
8 | -----+-----------
9 | 0x00 | 0x000000FF
10 | 0x01 | 0x0000000F
11 | 0x02 | 0x00000EF1
12 | 0x03 | 0x00000000
13 | 0x04 | 0x00000000
14 | 0x05 | 0x00000000
15 | 0x06 | 0x00000000
16 | 0x07 | 0x00000000
17 | 0x08 | 0x00000000
18 | 0x09 | 0x00000000
19 | 0x0A | 0x00000000
20 | 0x0B | 0x00000000
21 | 0x0C | 0x00000000
22 | 0x0D | 0x00000000
23 | 0x0E | 0x00000000
24 | 0x0F | 0x00000000
25 |
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/demos/reference_outputs/fibonacci.txt:
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1 | r-VEX
2 | -----
3 | Cycles: 0x00000231
4 |
5 | Data memory dump
6 |
7 | addr | contents
8 | -----+-----------
9 | 0x00 | 0x43A53F82
10 | 0x01 | 0x00000000
11 | 0x02 | 0x00000000
12 | 0x03 | 0x00000000
13 | 0x04 | 0x00000000
14 | 0x05 | 0x00000000
15 | 0x06 | 0x00000000
16 | 0x07 | 0x00000000
17 | 0x08 | 0x00000000
18 | 0x09 | 0x00000000
19 | 0x0A | 0x00000000
20 | 0x0B | 0x00000000
21 | 0x0C | 0x00000000
22 | 0x0D | 0x00000000
23 | 0x0E | 0x00000000
24 | 0x0F | 0x00000000
25 |
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/doc/diagrams/r-vex_instructions.svg:
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1 |
2 |
3 |
262 |
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1 |
2 |
3 |
122 |
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/doc/instruction_layout.txt:
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1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Instruction layout
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | --------------------------------------------------------------------------------
15 | -- instruction_layout.txt
16 | --------------------------------------------------------------------------------
17 |
18 | This document describes the instrction layout for the r-VEX
19 | processor. An instruction for an 4-wide r-VEX consists of
20 | 4 syllables.
21 |
22 | -----------------------------------------------------------
23 | General information
24 | -----------------------------------------------------------
25 |
26 | A syllable has a width of 32 bits, so an instruction has a width of 128 bits:
27 |
28 | 127 96 64 32 0
29 | ^ ^ ^ ^ ^
30 | | | | | |
31 | |[syllable 3]|[syllable 2]|[syllable 1]|[syllable 0]|
32 | | | | | |
33 |
34 | A standard VEX cluster [1] consists of 4 ALU units and 2 MUL units.
35 |
36 |
37 | -----------------------------------------------------------
38 | Allowed instruction types per syllable
39 | -----------------------------------------------------------
40 |
41 | syllable 0: ALU, CTRL
42 | syllable 1: ALU, MUL
43 | syllable 2: ALU, MUL
44 | syllable 3: ALU, MEM
45 |
46 | The r-VEX assembler should take care of syllable ordering inside the
47 | instructions.
48 |
49 | -----------------------------------------------------------
50 | References
51 | -----------------------------------------------------------
52 |
53 | [1] J.A. Fisher, P. Faraboschi and C. Young. Embedded Computing, A VLIW
54 | Approach to Architecture, Compilers and Tools. Morgan Kaufmann, 2004.
55 |
56 |
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1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Quickstart Guide for XUP V2P FPGA board
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | --------------------------------------------------------------------------------
15 | -- quickstart_xupv2p.txt
16 | --------------------------------------------------------------------------------
17 |
18 | This is a quickstart guide for the Xilinx University Program Virtex-II Pro board
19 | by Digilent [1].
20 |
21 | -----------------------------------------------------------
22 | Requirements
23 | -----------------------------------------------------------
24 | - a Xilinx University Program Virtex-II Pro board [1]
25 | - PC running Linux or Windows*
26 | - Xilinx ISE Suite (tested with 8.103i, should work with later versions too)
27 |
28 | * When you want to make use of the Makefile method described below on a Windows
29 | machine, a cygwin installation should be present with GNU Make.
30 |
31 | -----------------------------------------------------------
32 | Quickstart
33 | -----------------------------------------------------------
34 |
35 | 1: Acquire the latest snapshot from the Downloads section at the r-VEX website,
36 | or checkout the latest code from the Subversion repository.
37 |
38 | 2: Inside the r-VEX/src/ directory, synthesize r-VEX by entering the following
39 | command:
40 | make v2p
41 |
42 | 3: After the synthesis process has completed, the generated bit-file can be
43 | uploaded to the FPGA board by entering:
44 | make fpga
45 |
46 | 4: Connect a serial cable to the RS-232 interface on the XUP V2P board. Connect
47 | the other side of the cable to a PC, and start a terminal application, like
48 | Minicom (*NIX), Putty or Hyperterminal (Windows). Connect using the fol-
49 | lowing settings:
50 | 115200 bps transfer rate, 8 data bits, no parity
51 |
52 | 5: Press button SW2 on the XUP V2P board, which acts as the reset button. In
53 | the terminal application, you will see the contents of the first 16 data
54 | memory addresses, as well as a cycle counter.
55 |
56 | By default, an application is loaded and pre-synthesized to calculate the
57 | 45th Fibonacci number, so memory address 0x00 will contain the value
58 | 0x43A53F82.
59 |
60 | -----------------------------------------------------------
61 | References
62 | -----------------------------------------------------------
63 |
64 | [1] Digilent Inc., Xilinx University Program Virtex-II Pro board,
65 | http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P
66 |
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/r-ASM/src/Makefile:
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1 | CC = gcc
2 | CFLAGS = -ggdb
3 |
4 | SRCS = util.c syllable.c vhdl.c rasm.c
5 | OBJS = util.o syllable.o vhdl.o rasm.o
6 |
7 | rasm: $(OBJS)
8 | $(CC) -o rasm $(CFLAGS) $(OBJS)
9 |
10 | clean:
11 | rm -f *.o *.vhd *~ rasm
12 |
13 |
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/r-ASM/src/rasm.h:
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1 | /* r-ASM | The r-VEX assembler/instruction memory generator
2 | *
3 | * Copyright (c) 2008, Thijs van As
4 | *
5 | * Computer Engineering Laboratory
6 | * Delft University of Technology
7 | * Delft, The Netherlands
8 | *
9 | * http://r-vex.googlecode.com
10 | *
11 | * r-ASM is free software: you can redistribute it and/or modify
12 | * it under the terms of the GNU General Public License as published by
13 | * the Free Software Foundation, either version 3 of the License, or
14 | * (at your option) any later version.
15 | *
16 | * This program is distributed in the hope that it will be useful,
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 | * GNU General Public License for more details.
20 | *
21 | * You should have received a copy of the GNU General Public License
22 | * along with this program. If not, see .
23 | *
24 | * rasm.h
25 | */
26 |
27 | #ifndef __RASM_H__
28 | #define __RASM_H__
29 |
30 | #include "syllable.h"
31 |
32 | #define MAX_LABELS 128 /* maximum numbers of labels */
33 |
34 | typedef struct label_t {
35 | char name[64];
36 | unsigned address;
37 | } label_t;
38 |
39 | label_t labels[MAX_LABELS];
40 | int num_labels;
41 |
42 | char syllable_buffer[NUM_SLOTS][100];
43 | char syllable_final[NUM_SLOTS][100];
44 | int syllable_func[NUM_SLOTS];
45 | int syllable_fill[NUM_SLOTS];
46 | int syllable_count;
47 |
48 | FILE *in_asm, *out_vhd;
49 |
50 | #endif /* __RASM_H__ */
51 |
--------------------------------------------------------------------------------
/r-ASM/src/syllable.c:
--------------------------------------------------------------------------------
1 | /* r-ASM | The r-VEX assembler/instruction memory generator
2 | *
3 | * Copyright (c) 2008, Thijs van As
4 | *
5 | * Computer Engineering Laboratory
6 | * Faculty of Electrical Engineering, Mathematics and Computer Science
7 | * Delft University of Technology
8 | * Delft, The Netherlands
9 | *
10 | * http://r-vex.googlecode.com
11 | *
12 | * r-ASM is free software: you can redistribute it and/or modify
13 | * it under the terms of the GNU General Public License as published by
14 | * the Free Software Foundation, either version 3 of the License, or
15 | * (at your option) any later version.
16 | *
17 | * This program is distributed in the hope that it will be useful,
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | * GNU General Public License for more details.
21 | *
22 | * You should have received a copy of the GNU General Public License
23 | * along with this program. If not, see .
24 | *
25 | * syllable.c
26 | */
27 |
28 | #define INCLUDE_TABLE
29 | #include "syllable.h"
30 |
31 | int determine_func(int opcode) {
32 | if (((opcode >= ADD) && (opcode <= ADDCG)) || (opcode == SLCT) || (opcode == SLCTF) || (opcode == NOP)) {
33 | return ALU;
34 | }
35 | else if ((opcode >= MPYLL) && (opcode <= MPYHS)) {
36 | return MUL;
37 | }
38 | else if ((opcode >= GOTO) && (opcode <= RECV)) {
39 | return CTRL;
40 | }
41 | else if ((opcode >= LDW) && (opcode <= PFT)) {
42 | return MEM;
43 | }
44 | }
45 |
46 | static int operation_compare(const void *a, const void *b)
47 | {
48 | const char *key = a;
49 | const struct operation_t *operation = b;
50 |
51 | return strcmp(key, operation->operation);
52 | }
53 |
54 | int operation_to_opcode(const char *operation)
55 | {
56 | struct operation_t *op;
57 |
58 | op = (struct operation_t *)bsearch(operation, operation_table,
59 | sizeof(operation_table) / sizeof(struct operation_t), sizeof(struct operation_t),
60 | operation_compare);
61 |
62 | if (!op) {
63 | return -1;
64 | }
65 |
66 | return op->opcode;
67 | }
68 |
69 |
--------------------------------------------------------------------------------
/r-ASM/src/syllable.h:
--------------------------------------------------------------------------------
1 | /* r-ASM | syllable and opcode definitions
2 | *
3 | * See syllable_layout.txt for more information about the r-VEX syllable
4 | * layout scheme.
5 | *
6 | * Copyright (c) 2008, Thijs van As
7 | *
8 | * Computer Engineering Laboratory
9 | * Delft University of Technology
10 | * Delft, The Netherlands
11 | *
12 | * http://r-vex.googlecode.com
13 | *
14 | * r-ASM is free software: you can redistribute it and/or modify
15 | * it under the terms of the GNU General Public License as published by
16 | * the Free Software Foundation, either version 3 of the License, or
17 | * (at your option) any later version.
18 | *
19 | * This program is distributed in the hope that it will be useful,
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | * GNU General Public License for more details.
23 | *
24 | * You should have received a copy of the GNU General Public License
25 | * along with this program. If not, see .
26 | *
27 | * syllable.h
28 | */
29 |
30 | #ifndef __SYLLABLE_H__
31 | #define __SYLLABLE_H__
32 |
33 | /* number of GR registers */
34 | #define NUM_GR 32 /* 32 default in current r-VEX configuration */
35 |
36 | /*
37 | * issue slots
38 | * (all slots are ALU slots)
39 | */
40 | #define NUM_SLOTS 4 /* default VLIW 4 issue */
41 |
42 | #define CTRL_SLOT 3 /* slot 0 in hardware */
43 | #define MUL0_SLOT 2 /* slot 1 in hardware */
44 | #define MUL1_SLOT 1 /* slot 2 in hardware */
45 | #define MEM_SLOT 0 /* slot 3 in hardware */
46 |
47 | /*
48 | * syllable types
49 | */
50 | #define RTYPE 1
51 | #define ISTYPE 2
52 | #define ILTYPE 3
53 | #define BRANCH 4
54 | #define RTYPE_BS 5
55 | #define MEMTYPE 6
56 |
57 | /*
58 | * functional type
59 | */
60 | #define ALU 1
61 | #define MUL 2
62 | #define CTRL 3
63 | #define MEM 4
64 |
65 | /*
66 | * immediate switch types
67 | * values according to 'immediate switch' bits
68 | */
69 | #define NO_IMM 0
70 | #define SHORT_IMM 1
71 | #define BRANCH_IMM 2
72 | #define LONG_IMM 3
73 |
74 | /*
75 | * opcodes
76 | */
77 |
78 | /* special operations */
79 | #define NOP 0x00000000
80 | #define STOP 53
81 |
82 | /* ALU opcodes */
83 | #define ADD 65
84 | #define AND 67
85 | #define ANDC 68
86 | #define MAX 69
87 | #define MAXU 70
88 | #define MIN 71
89 | #define MINU 72
90 | #define OR 73
91 | #define ORC 74
92 | #define SH1ADD 75
93 | #define SH2ADD 76
94 | #define SH3ADD 77
95 | #define SH4ADD 78
96 | #define SHL 79
97 | #define SHR 80
98 | #define SHRU 81
99 | #define SUB 82
100 | #define SXTB 83
101 | #define SXTH 84
102 | #define ZXTB 85
103 | #define ZXTH 86
104 | #define XOR 87
105 | #define MOV 88
106 |
107 | #define CMPEQ 89
108 | #define CMPGE 90
109 | #define CMPGEU 91
110 | #define CMPGT 92
111 | #define CMPGTU 93
112 | #define CMPLE 94
113 | #define CMPLEU 95
114 | #define CMPLT 96
115 | #define CMPLTU 97
116 | #define CMPNE 98
117 | #define NANDL 99
118 | #define NORL 100
119 | #define ORL 102
120 | #define MTB 103
121 | #define ANDL 104
122 |
123 | #define ADDCG 120
124 | #define DIVS 112
125 | #define SLCT 56
126 | #define SLCTF 48
127 |
128 | /* MUL opcodes */
129 | #define MPYLL 1
130 | #define MPYLLU 2
131 | #define MPYLH 3
132 | #define MPYLHU 4
133 | #define MPYHH 5
134 | #define MPYHHU 6
135 | #define MPYL 7
136 | #define MPYLU 8
137 | #define MPYH 9
138 | #define MPYHU 10
139 | #define MPYHS 11
140 |
141 | /* Control opcodes */
142 | #define GOTO 33
143 | #define IGOTO 34
144 | #define CALL 35
145 | #define ICALL 36
146 | #define BR 37
147 | #define BRF 38
148 | #define RETURN 39
149 | #define RFI 40
150 | #define XNOP 41
151 |
152 | #define SEND 42
153 | #define RECV 43
154 |
155 | /* Memory opcodes */
156 | #define LDW 17
157 | #define LDH 18
158 | #define LDHU 19
159 | #define LDB 20
160 | #define LDBU 21
161 | #define STW 22
162 | #define STH 23
163 | #define STB 24
164 | #define PFT 25
165 |
166 | #define SYL_FOLLOW 28
167 |
168 | #ifdef INCLUDE_TABLE
169 | static struct operation_t {
170 | const char *operation;
171 | int opcode;
172 | } operation_table[] = {
173 | { "add", ADD },
174 | { "addcg", ADDCG },
175 | { "and", AND },
176 | { "andc", ANDC },
177 | { "andl", ANDL },
178 | { "br", BR },
179 | { "brf", BRF },
180 | { "call", CALL },
181 | { "cmpeq", CMPEQ },
182 | { "cmpge", CMPGE },
183 | { "cmpgeu", CMPGEU },
184 | { "cmpgt", CMPGT },
185 | { "cmpgtu", CMPGTU },
186 | { "cmple", CMPLE },
187 | { "cmpleu", CMPLEU },
188 | { "cmplt", CMPLT },
189 | { "cmpltu", CMPLTU },
190 | { "cmpne", CMPNE },
191 | { "divs", DIVS },
192 | { "goto", GOTO },
193 | { "icall", ICALL },
194 | { "igoto", IGOTO },
195 | { "ldb", LDB },
196 | { "ldbu", LDBU },
197 | { "ldh", LDH },
198 | { "ldhu", LDHU },
199 | { "ldw", LDW },
200 | { "max", MAX },
201 | { "maxu", MAXU },
202 | { "min", MIN },
203 | { "minu", MINU },
204 | { "mov", MOV },
205 | { "mpyh", MPYH },
206 | { "mpyhh", MPYHH },
207 | { "mpyhhu", MPYHHU },
208 | { "mpyhs", MPYHS },
209 | { "mpyhu", MPYHU },
210 | { "mpyl", MPYL },
211 | { "mpylh", MPYLH },
212 | { "mpylhu", MPYLHU },
213 | { "mpyll", MPYLL },
214 | { "mpyllu", MPYLLU },
215 | { "mpylu", MPYLU },
216 | { "mtb", MTB },
217 | { "nandl", NANDL },
218 | { "nop", NOP },
219 | { "norl", NORL },
220 | { "or", OR },
221 | { "orc", ORC },
222 | { "orl", ORL },
223 | { "pft", PFT },
224 | { "recv", RECV },
225 | { "return", RETURN },
226 | { "rfi", RFI },
227 | { "send", SEND },
228 | { "sh1add", SH1ADD },
229 | { "sh2add", SH2ADD },
230 | { "sh3add", SH3ADD },
231 | { "sh4add", SH4ADD },
232 | { "shl", SHL },
233 | { "shr", SHR },
234 | { "shru", SHRU },
235 | { "slct", SLCT },
236 | { "slctf", SLCTF },
237 | { "stb", STB },
238 | { "sth", STH },
239 | { "stop", STOP },
240 | { "stw", STW },
241 | { "sub", SUB },
242 | { "sxtb", SXTB },
243 | { "sxth", SXTH },
244 | { "xnop", XNOP },
245 | { "xor", XOR },
246 | { "zxtb", ZXTB },
247 | { "zxth", ZXTH },
248 | };
249 | #endif /* INCLUDE_TABLE */
250 |
251 | int determine_func(int opcode);
252 | int operation_to_opcode(const char *operation);
253 |
254 | #endif /* __SYLLABLE_H__ */
255 |
--------------------------------------------------------------------------------
/r-ASM/src/util.c:
--------------------------------------------------------------------------------
1 | /* r-ASM | The r-VEX assembler/instruction memory generator
2 | *
3 | * Copyright (c) 2008, Thijs van As
4 | *
5 | * Computer Engineering Laboratory
6 | * Faculty of Electrical Engineering, Mathematics and Computer Science
7 | * Delft University of Technology
8 | * Delft, The Netherlands
9 | *
10 | * http://r-vex.googlecode.com
11 | *
12 | * r-ASM is free software: you can redistribute it and/or modify
13 | * it under the terms of the GNU General Public License as published by
14 | * the Free Software Foundation, either version 3 of the License, or
15 | * (at your option) any later version.
16 | *
17 | * This program is distributed in the hope that it will be useful,
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | * GNU General Public License for more details.
21 | *
22 | * You should have received a copy of the GNU General Public License
23 | * along with this program. If not, see .
24 | *
25 | * util.c
26 | */
27 |
28 | #include
29 | #include
30 | #include
31 |
32 | /* integer to binary conversion) */
33 | char* itob(unsigned num, int bits)
34 | {
35 | char *result;
36 | int i = 0;
37 |
38 | result = malloc(bits+1);
39 |
40 | for (i = 0; i < bits; i++) {
41 | if ((1 << (bits - 1 - i)) & num) {
42 | result[i] = '1';
43 | }
44 | else {
45 | result[i] = '0';
46 | }
47 | }
48 |
49 | result[i] = '\0';
50 | return result;
51 | }
52 |
53 | /* removes spaces and comments (#) from string */
54 | void delete_spaces(char *string)
55 | {
56 | char *t = string;
57 |
58 | while (*string != '\0') {
59 | if (*string == '#') {
60 | break;
61 | }
62 | else if (*string != ' ' && *string != '\t') {
63 | *t++ = *string;
64 | }
65 |
66 | string++;
67 | }
68 |
69 | *t = '\0';
70 | }
71 |
72 | /* fetches a line from file, strips comments and spaces */
73 | int fetchline(FILE *in, char *line)
74 | {
75 | int i;
76 | char c;
77 |
78 | i = 0;
79 |
80 | while ((c = getc(in)) != EOF && c != '\n') {
81 | line[i++] = c;
82 | }
83 |
84 | line[i] = '\0';
85 |
86 | delete_spaces(line);
87 |
88 | return i;
89 | }
90 |
91 |
--------------------------------------------------------------------------------
/r-ASM/src/util.h:
--------------------------------------------------------------------------------
1 | /* r-ASM | The r-VEX assembler/instruction memory generator
2 | *
3 | * Copyright (c) 2008, Thijs van As
4 | *
5 | * Computer Engineering Laboratory
6 | * Delft University of Technology
7 | * Delft, The Netherlands
8 | *
9 | * http://r-vex.googlecode.com
10 | *
11 | * r-ASM is free software: you can redistribute it and/or modify
12 | * it under the terms of the GNU General Public License as published by
13 | * the Free Software Foundation, either version 3 of the License, or
14 | * (at your option) any later version.
15 | *
16 | * This program is distributed in the hope that it will be useful,
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 | * GNU General Public License for more details.
20 | *
21 | * You should have received a copy of the GNU General Public License
22 | * along with this program. If not, see .
23 | *
24 | * util.h
25 | */
26 |
27 | #ifndef __UTIL_H__
28 | #define __UTIL_H__
29 |
30 | char* itob(unsigned num, int bits);
31 | void delete_spaces(char *string);
32 | int fetchline(FILE *in, char *line);
33 |
34 | #endif /* __UTIL_H__ */
35 |
--------------------------------------------------------------------------------
/r-ASM/src/vhdl.c:
--------------------------------------------------------------------------------
1 | /* r-ASM | The r-VEX assembler/instruction memory generator
2 | *
3 | * Copyright (c) 2008, Thijs van As
4 | *
5 | * Computer Engineering Laboratory
6 | * Faculty of Electrical Engineering, Mathematics and Computer Science
7 | * Delft University of Technology
8 | * Delft, The Netherlands
9 | *
10 | * http://r-vex.googlecode.com
11 | *
12 | * r-ASM is free software: you can redistribute it and/or modify
13 | * it under the terms of the GNU General Public License as published by
14 | * the Free Software Foundation, either version 3 of the License, or
15 | * (at your option) any later version.
16 | *
17 | * This program is distributed in the hope that it will be useful,
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 | * GNU General Public License for more details.
21 | *
22 | * You should have received a copy of the GNU General Public License
23 | * along with this program. If not, see .
24 | *
25 | * vhdl.c
26 | */
27 |
28 | #include
29 | #include
30 | #include
31 | #include
32 |
33 | #include "rasm.h"
34 |
35 | /* prints vhdl header to file */
36 | void vhdl_header(char *src_file, char *flags, char *dest_file)
37 | {
38 | char date[30];
39 | size_t i;
40 | struct tm tim;
41 | time_t now;
42 |
43 | now = time(NULL);
44 | tim = *(localtime(&now));
45 | i = strftime(date, 30, "%b %d, %Y @ %H:%M:%S\n", &tim);
46 |
47 |
48 | fprintf(out_vhd, "\
49 | --------------------------------------------------------------------------------\n\
50 | -- r-VEX | Instruction ROM\n\
51 | --------------------------------------------------------------------------------\n\
52 | -- \n\
53 | -- This file was assembled by r-ASM, the r-VEX assembler/\n\
54 | -- instruction ROM generator.\n\
55 | -- \n\
56 | -- source file: %s\n\
57 | -- r-ASM flags: %s\n\
58 | -- date & time: %s\
59 | -- \n\
60 | -- r-VEX & r-ASM are\n\
61 | -- Copyright (c) 2008, Thijs van As \n\
62 | -- \n\
63 | -- Computer Engineering Laboratory\n\
64 | -- Faculty of Electrical Engineering, Mathematics and Computer Science\n\
65 | -- Delft University of Technology\n\
66 | -- Delft, The Netherlands\n\
67 | -- \n\
68 | -- http://r-vex.googlecode.com\n\
69 | -- \n\
70 | -- r-VEX is free hardware: you can redistribute it and/or modify\n\
71 | -- it under the terms of the GNU General Public License as published by\n\
72 | -- the Free Software Foundation, either version 3 of the License, or\n\
73 | -- (at your option) any later version.\n\
74 | -- \n\
75 | -- This program is distributed in the hope that it will be useful,\n\
76 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of\n\
77 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n\
78 | -- GNU General Public License for more details.\n\
79 | -- \n\
80 | -- You should have received a copy of the GNU General Public License\n\
81 | -- along with this program. If not, see .\n\
82 | -- \n\
83 | --------------------------------------------------------------------------------\n\
84 | -- %s (generated by r-ASM)\n\
85 | --------------------------------------------------------------------------------\n\
86 | \n\
87 | library ieee;\n\
88 | use ieee.std_logic_1164.all;\n\
89 | \n\
90 | entity i_mem is\n\
91 | \tport ( reset : in std_logic; -- system reset\n\
92 | \t address : in std_logic_vector(7 downto 0); -- address of instruction to be read\n\
93 | \n\
94 | \t instr : out std_logic_vector(127 downto 0)); -- instruction (4 syllables)\n\
95 | end entity i_mem;\n\
96 | \n\
97 | \n\
98 | architecture behavioural of i_mem is\n\
99 | begin\n\
100 | \tmemory : process(address, reset)\n\
101 | \tbegin\n\
102 | \t\tif (reset = '1') then\n\
103 | \t\t\tinstr <= x\"00000000000000000000000000000000\";\n\
104 | \t\telse\n\
105 | \t\t\tcase address is\n", src_file, flags, date, dest_file);
106 |
107 | }
108 |
109 | /* prints vhdl footer to file */
110 | void vhdl_footer()
111 | {
112 | char *footer = "\
113 | \t\t\t\twhen others => instr <= \"00000000000000000000000000000010\"& -- nop\n\
114 | \t\t\t\t \"00000000000000000000000000000000\"& -- nop\n\
115 | \t\t\t\t \"00000000000000000000000000000000\"& -- nop\n\
116 | \t\t\t\t \"00111110000000000000000000000001\"; -- stop\n\
117 | \t\t\tend case;\n\
118 | \t\tend if;\n\
119 | \tend process memory;\n\
120 | end architecture behavioural;\n\n\
121 | ";
122 | fprintf(out_vhd, footer);
123 | }
124 |
125 |
--------------------------------------------------------------------------------
/r-ASM/src/vhdl.h:
--------------------------------------------------------------------------------
1 | /* r-ASM | The r-VEX assembler/instruction memory generator
2 | *
3 | * Copyright (c) 2008, Thijs van As
4 | *
5 | * Computer Engineering Laboratory
6 | * Delft University of Technology
7 | * Delft, The Netherlands
8 | *
9 | * http://r-vex.googlecode.com
10 | *
11 | * r-ASM is free software: you can redistribute it and/or modify
12 | * it under the terms of the GNU General Public License as published by
13 | * the Free Software Foundation, either version 3 of the License, or
14 | * (at your option) any later version.
15 | *
16 | * This program is distributed in the hope that it will be useful,
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 | * GNU General Public License for more details.
20 | *
21 | * You should have received a copy of the GNU General Public License
22 | * along with this program. If not, see .
23 | *
24 | * vhdl.h
25 | */
26 |
27 | #ifndef __VHDL_H__
28 | #define __VHDL_H__
29 |
30 | void vhdl_header(char *src_file, char *flags, char *dest_file);
31 | void vhdl_footer();
32 |
33 | #endif /* __VHDL_H__ */
34 |
--------------------------------------------------------------------------------
/r-VEX/src/Makefile:
--------------------------------------------------------------------------------
1 | OBJS = r-vex_pkg.vhd \
2 | alu_operations.vhd \
3 | mul_operations.vhd \
4 | ctrl_operations.vhd \
5 | mem_operations.vhd \
6 | alu.vhd \
7 | mul.vhd \
8 | ctrl.vhd \
9 | mem.vhd \
10 | pc.vhd \
11 | registers_br.vhd \
12 | registers_gr.vhd \
13 | fetch.vhd \
14 | decode.vhd \
15 | execute.vhd \
16 | writeback.vhd \
17 | r-vex.vhd \
18 | d_mem.vhd \
19 | i_mem.vhd \
20 | clk_div.vhd \
21 | uart/clk_18432.vhd \
22 | uart/uart_pkg.vhd \
23 | uart/uart_tx.vhd \
24 | uart/uart.vhd \
25 | system.vhd
26 |
27 | XIL_PART_r-vex_v2p = xc2vp30-ff896-7
28 |
29 | default:
30 | @echo -e "\n---------------------------------"
31 | @echo -e "r-VEX stand-alone system deployer"
32 | @echo -e "---------------------------------"
33 | @echo -e "\nUsage: make "
34 | @echo -e "\nTargets: v2p | Xilinx Virtex-II Pro VP30 Development Board"
35 | @echo -e "\n modelsim | Run modelsim simulation"
36 | @echo -e " vcom | Compile files for Modelsim"
37 | @echo -e "\n fpga | Download bitstream to FPGA"
38 | @echo -e " unlock | Unlock download cable"
39 | @echo -e "\n clean | Clean generated project files\n"
40 |
41 |
42 | v2p: r-vex_v2p.deps r-vex_v2p.bit log_v2p.txt
43 |
44 | fpga:
45 | impact -batch r-vex_fpga.cmd
46 |
47 | unlock: unlock_cable.cmd
48 | impact -batch unlock_cable.cmd
49 |
50 | log_%.txt:
51 | @echo -e "--- Synthesize ---" > $@
52 | @echo -e "\n" >> $@
53 | @cat r-vex_$*.srp >> $@
54 | @echo -e "\n" >> $@
55 |
56 | @echo -e "\n\n--- Translate ---" >> $@
57 | @echo -e "\n" >> $@
58 | @cat r-vex_$*.bld >> $@
59 | @echo -e "\n" >> $@
60 |
61 | @echo -e "\n\n--- Map ---" >> $@
62 | @echo -e "\n" >> $@
63 | @cat r-vex_$*_map.mrp >> $@
64 | @echo -e "\n" >> $@
65 |
66 | @echo -e "\n\n--- Place & Route ---" >> $@
67 | @echo -e "\n" >> $@
68 | @cat r-vex_$*.par >> $@
69 | @echo -e "\n" >> $@
70 |
71 | @echo -e "\n\n--- Unrouted Networks ---" >> $@
72 | @echo -e "\n" >> $@
73 | @cat r-vex_$*.unroutes >> $@
74 | @echo -e "\n" >> $@
75 |
76 | @echo -e "\n\n--- Bitgen ---" >> $@
77 | @echo -e "\n" >> log_$*.txt
78 | @cat r-vex_$*.bgn >> $@
79 | @echo -e "\n\n\n" >> $@
80 | @echo -e "\n\nLog file created in $@\n"
81 |
82 | clean:
83 | rm -f r-vex_v2p*
84 | rm -f r-vex_fpga.cmd
85 | rm -f unlock_cable.cmd
86 | rm -rf __cf
87 | rm -rf __ngo
88 | rm -rf __xst
89 | rm -f _impact*
90 | rm -f *.bgn
91 | rm -f *.bit
92 | rm -f *.bld
93 | rm -f *.drc
94 | rm -f *_map.mrp
95 | rm -f *_map.ncd
96 | rm -f *_map.ngm
97 | rm -f *.ncd
98 | rm -f *.ngc
99 | rm -f *.ngd
100 | rm -f *.ngr
101 | rm -f *.pad
102 | rm -f *_pad.csv
103 | rm -f *_pad.txt
104 | rm -f *.par
105 | rm -f *.pcf
106 | rm -f *.srp
107 | rm -f *.unroutes
108 | rm -f *_usage.xml
109 | rm -f *.xpi
110 | rm -f log_*
111 | rm -f *~ # temporary backup saves
112 | rm -rf work # modelsim
113 | rm -f vsim.wlf # modelsim
114 | rm -f r-vex.do # modelsim
115 | rm -f transcript # modelsim
116 |
117 | %.deps: %.prj %.lso %.ucf %.ut %.xst %.cmd
118 | @echo -e "--- auxiliary files generated ---"
119 |
120 | %.bgn %.bit %.drc: %.ncd %.ut
121 | bitgen -f $*.ut $<
122 |
123 | %.ncd %.pad %_pad.csv %_pad.txt %.par %.xpi: %_map.ncd %.pcf
124 | par -w -ol std -t 1 $< $@ $*.pcf
125 |
126 | %_map.mrp %_map.ncd %_map.ngm %.pcf: %.ngd
127 | map -p ${XIL_PART_$*} -cm area -pr b -k 4 -c 100 -o $*_map.ncd $< $*.pcf
128 |
129 | %.bld %.ngd: %.ngc %.ucf
130 | ngdbuild -aul -dd __ngo -uc $*.ucf -p ${XIL_PART_$*} $< $@
131 |
132 | %.ngc %.ngr: %.xst ${OBJS}
133 | xst -ifn $<
134 |
135 | %.prj:
136 | @echo -e "vhdl work \"r-vex_pkg.vhd\" \
137 | \nvhdl work \"alu_operations.vhd\" \
138 | \nvhdl work \"mul_operations.vhd\" \
139 | \nvhdl work \"ctrl_operations.vhd\" \
140 | \nvhdl work \"mem_operations.vhd\" \
141 | \nvhdl work \"alu.vhd\" \
142 | \nvhdl work \"mul.vhd\" \
143 | \nvhdl work \"ctrl.vhd\" \
144 | \nvhdl work \"mem.vhd\" \
145 | \nvhdl work \"pc.vhd\" \
146 | \nvhdl work \"registers_br.vhd\" \
147 | \nvhdl work \"registers_gr.vhd\" \
148 | \nvhdl work \"fetch.vhd\" \
149 | \nvhdl work \"decode.vhd\" \
150 | \nvhdl work \"execute.vhd\" \
151 | \nvhdl work \"writeback.vhd\" \
152 | \nvhdl work \"r-vex.vhd\" \
153 | \nvhdl work \"d_mem.vhd\" \
154 | \nvhdl work \"i_mem.vhd\" \
155 | \nvhdl work \"clk_div.vhd\" \
156 | \nvhdl work \"uart/clk_18432.vhd\" \
157 | \nvhdl work \"uart/uart_pkg.vhd\" \
158 | \nvhdl work \"uart/uart_tx.vhd\" \
159 | \nvhdl work \"uart/uart.vhd\" \
160 | \nvhdl work \"system.vhd\"" > $@
161 |
162 | %.lso:
163 | @echo -e "work" > $@
164 |
165 | r-vex_v2p.ut:
166 | @echo -e "-w \
167 | \n-g DebugBitstream:No \
168 | \n-g Binary:no \
169 | \n-g CRC:Enable \
170 | \n-g ConfigRate:4 \
171 | \n-g CclkPin:PullUp \
172 | \n-g M0Pin:PullUp \
173 | \n-g M1Pin:PullUp \
174 | \n-g M2Pin:PullUp \
175 | \n-g ProgPin:PullUp \
176 | \n-g DonePin:PullUp \
177 | \n-g PowerdownPin:PullUp \
178 | \n-g TckPin:PullUp \
179 | \n-g TdiPin:PullUp \
180 | \n-g TdoPin:PullNone \
181 | \n-g TmsPin:PullUp \
182 | \n-g UnusedPin:PullDown \
183 | \n-g UserID:0xFFFFFFFF \
184 | \n-g DCMShutdown:Disable \
185 | \n-g DisableBandgap:No \
186 | \n-g DCIUpdateMode:AsRequired \
187 | \n-g StartUpClk:CClk \
188 | \n-g DONE_cycle:4 \
189 | \n-g GTS_cycle:5 \
190 | \n-g GWE_cycle:6 \
191 | \n-g LCK_cycle:NoWait \
192 | \n-g Match_cycle:Auto \
193 | \n-g Security:None \
194 | \n-g DonePipe:No \
195 | \n-g DriveDone:No \
196 | \n-g Encrypt:No " > $@
197 |
198 | r-vex_v2p.xst:
199 | @echo -e "set -xsthdpdir __xst \
200 | \nrun \
201 | \n-ifn r-vex_v2p.prj \
202 | \n-ifmt mixed \
203 | \n-ofn r-vex_v2p \
204 | \n-ofmt NGC \
205 | \n-p xc2vp30-7-ff896 \
206 | \n-top system \
207 | \n-opt_mode Speed \
208 | \n-opt_level 1 \
209 | \n-iuc NO \
210 | \n-lso r-vex_v2p.lso \
211 | \n-keep_hierarchy NO \
212 | \n-rtlview Yes \
213 | \n-glob_opt AllClockNets \
214 | \n-read_cores YES \
215 | \n-write_timing_constraints NO \
216 | \n-cross_clock_analysis NO \
217 | \n-hierarchy_separator / \
218 | \n-bus_delimiter <> \
219 | \n-case maintain \
220 | \n-slice_utilization_ratio 100 \
221 | \n-verilog2001 YES \
222 | \n-fsm_extract YES -fsm_encoding Auto \
223 | \n-safe_implementation No \
224 | \n-fsm_style lut \
225 | \n-ram_extract Yes \
226 | \n-ram_style Auto \
227 | \n-rom_extract Yes \
228 | \n-mux_style Auto \
229 | \n-decoder_extract YES \
230 | \n-priority_extract YES \
231 | \n-shreg_extract YES \
232 | \n-shift_extract YES" > r-vex_v2p.xst
233 |
234 | r-vex_v2p.ucf:
235 | @echo -e "net \"clk\" period = 10.0ns high 50%; \
236 | \nnet \"clk\" loc = \"aj15\" | iostandard = lvcmos25; \
237 | \nnet \"reset\" loc = \"ag5\" | iostandard = lvttl; \
238 | \nnet \"tx\" loc = \"ae7\" | iostandard = lvcmos25 | slew = slow | drive = 8;" > r-vex_v2p.ucf
239 |
240 | r-vex_v2p.cmd:
241 | @echo -e "setMode -bs \
242 | \nsetMode -bs \
243 | \nsetCable -port auto \
244 | \nIdentify \
245 | \nidentifyMPM \
246 | \nsetMode -bs \
247 | \naddDevice -p 3 -file r-vex_v2p.bit \
248 | \ndeleteDevice -position 4 \
249 | \nProgram -p 3 -defaultVersion 0 \
250 | \nquit" > r-vex_fpga.cmd
251 |
252 | unlock_cable.cmd:
253 | @echo -e "setMode -bscan \
254 | \ncleancablelock \
255 | \nquit" > unlock_cable.cmd
256 |
257 | vsimdo:
258 | @echo -e "quit -sim \
259 | \nvsim work.tb_system \
260 | \nadd wave -r /* \
261 | \nrun 20000ns" > r-vex.do
262 |
263 | vcom:
264 | vlib work
265 | vcom ${OBJS}
266 | vcom ../testbenches/tb_system.vhd
267 |
268 | modelsim: vcom vsimdo
269 | vsim -do r-vex.do
270 |
271 |
--------------------------------------------------------------------------------
/r-VEX/src/alu.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Arithmetic Logic Unit
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- alu.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.numeric_std.all;
34 |
35 | library work;
36 | use work.rVEX_pkg.all;
37 | use work.alu_operations.all;
38 |
39 | entity alu is
40 | port ( clk : in std_logic; -- system clock
41 | reset : in std_logic; -- system reset
42 | aluop : in std_logic_vector(6 downto 0); -- opcode
43 | src1 : in std_logic_vector(31 downto 0); -- operand 1
44 | src2 : in std_logic_vector(31 downto 0); -- operand 2
45 | cin : in std_logic; -- carry input
46 |
47 | result : out std_logic_vector(31 downto 0); -- result of operation
48 | cout : out std_logic; -- carry output
49 | out_valid : out std_logic); -- '1' when output is valid
50 | end entity alu;
51 |
52 |
53 | architecture behavioural of alu is
54 | signal result_i : std_logic_vector(31 downto 0) := (others => '0');
55 | signal cout_i : std_logic := '0';
56 | begin
57 | result <= result_i;
58 | cout <= cout_i;
59 |
60 | -- Controls ALU operations
61 | alu_control : process(clk, reset)
62 | begin
63 | if (reset = '1') then
64 | out_valid <= '0';
65 | result_i <= (others => '0');
66 | cout_i <= '0';
67 | elsif (clk = '1' and clk'event) then
68 | out_valid <= '1'; -- this will be overriden when a non-existent opcode is issued
69 |
70 | if std_match(aluop, ALU_ADD) then
71 | result_i <= f_ADD (src1, src2);
72 | elsif std_match(aluop, ALU_ADDCG) then
73 | f_ADDCG (src1, src2, cin, result_i, cout_i);
74 | elsif std_match(aluop, ALU_AND) then
75 | result_i <= f_AND (src1, src2);
76 | elsif std_match(aluop, ALU_ANDC) then
77 | result_i <= f_ANDC (src1, src2);
78 | elsif std_match(aluop, ALU_DIVS) then
79 | f_DIVS (src1, src2, cin, result_i, cout_i);
80 | elsif std_match(aluop, ALU_MAX) then
81 | result_i <= f_MAX (src1, src2);
82 | elsif std_match(aluop, ALU_MAXU) then
83 | result_i <= f_MAXU (src1, src2);
84 | elsif std_match(aluop, ALU_MIN) then
85 | result_i <= f_MIN (src1, src2);
86 | elsif std_match(aluop, ALU_MINU) then
87 | result_i <= f_MINU (src1, src2);
88 | elsif std_match(aluop, ALU_OR) then
89 | result_i <= f_OR (src1, src2);
90 | elsif std_match(aluop, ALU_ORC) then
91 | result_i <= f_ORC (src1, src2);
92 | elsif std_match(aluop, ALU_SH1ADD) then
93 | result_i <= f_SH1ADD (src1, src2);
94 | elsif std_match(aluop, ALU_SH2ADD) then
95 | result_i <= f_SH2ADD (src1, src2);
96 | elsif std_match(aluop, ALU_SH3ADD) then
97 | result_i <= f_SH3ADD (src1, src2);
98 | elsif std_match(aluop, ALU_SH4ADD) then
99 | result_i <= f_SH4ADD (src1, src2);
100 | elsif std_match(aluop, ALU_SHL) then
101 | result_i <= f_SHL (src1, src2);
102 | elsif std_match(aluop, ALU_SHR) then
103 | result_i <= f_SHR (src1, src2);
104 | elsif std_match(aluop, ALU_SHRU) then
105 | result_i <= f_SHRU (src1, src2);
106 | elsif std_match(aluop, ALU_SUB) then
107 | result_i <= f_SUB (src1, src2);
108 | elsif std_match(aluop, ALU_SXTB) then
109 | result_i <= f_SXTB (src1);
110 | elsif std_match(aluop, ALU_SXTH) then
111 | result_i <= f_SXTH (src1);
112 | elsif std_match(aluop, ALU_ZXTB) then
113 | result_i <= f_ZXTB (src1);
114 | elsif std_match(aluop, ALU_ZXTH) then
115 | result_i <= f_ZXTH (src1);
116 | elsif std_match(aluop, ALU_XOR) then
117 | result_i <= f_XOR (src1, src2);
118 | elsif std_match(aluop, ALU_CMPEQ) then
119 | result_i <= f_CMPEQ (src1, src2);
120 | elsif std_match(aluop, ALU_CMPGE) then
121 | result_i <= f_CMPGE (src1, src2);
122 | elsif std_match(aluop, ALU_CMPGEU) then
123 | result_i <= f_CMPGEU (src1, src2);
124 | elsif std_match(aluop, ALU_CMPGT) then
125 | result_i <= f_CMPGT (src1, src2);
126 | elsif std_match(aluop, ALU_CMPGTU) then
127 | result_i <= f_CMPGTU (src1, src2);
128 | elsif std_match(aluop, ALU_CMPLE) then
129 | result_i <= f_CMPLE (src1, src2);
130 | elsif std_match(aluop, ALU_CMPLEU) then
131 | result_i <= f_CMPLEU (src1, src2);
132 | elsif std_match(aluop, ALU_CMPLT) then
133 | result_i <= f_CMPLT (src1, src2);
134 | elsif std_match(aluop, ALU_CMPLTU) then
135 | result_i <= f_CMPLTU (src1, src2);
136 | elsif std_match(aluop, ALU_CMPNE) then
137 | result_i <= f_CMPNE (src1, src2);
138 | elsif std_match(aluop, ALU_NANDL) then
139 | result_i <= f_NANDL (src1, src2);
140 | elsif std_match(aluop, ALU_NORL) then
141 | result_i <= f_NORL (src1, src2);
142 | elsif std_match(aluop, ALU_ORL) then
143 | result_i <= f_ORL (src1, src2);
144 | elsif std_match(aluop, ALU_SLCT) then
145 | result_i <= f_SLCT (src1, src2, cin);
146 | elsif std_match(aluop, ALU_SLCTF) then
147 | result_i <= f_SLCTF (src1, src2, cin);
148 | elsif std_match(aluop, ALU_MOV) then
149 | result_i <= src1;
150 | elsif std_match(aluop, ALU_ANDL) then
151 | result_i <= f_ANDL (src1, src2);
152 | elsif std_match(aluop, ALU_MTB) then
153 | cout_i <= src1(0);
154 | else
155 | out_valid <= '0';
156 | end if;
157 | end if;
158 | end process alu_control;
159 | end architecture behavioural;
160 |
--------------------------------------------------------------------------------
/r-VEX/src/clk_div.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Clock divider
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- Used because to meet timing constraints
29 | --------------------------------------------------------------------------------
30 | -- clk_div.vhd
31 | --------------------------------------------------------------------------------
32 |
33 | library ieee;
34 | use ieee.std_logic_1164.all;
35 |
36 | entity clk_div is
37 | port ( clk : in std_logic; -- system clock
38 |
39 | clk_out : out std_logic); -- output clock (0.5 * clk freq)
40 | end clk_div;
41 |
42 |
43 | architecture behavioral of clk_div is
44 | signal clk_s : std_logic := '0';
45 | begin
46 | clk_out <= clk_s;
47 |
48 | clock_divider : process(clk)
49 | begin
50 | if (clk = '1' and clk'event) then
51 | clk_s <= not clk_s;
52 | end if;
53 | end process;
54 | end behavioral;
55 |
56 |
--------------------------------------------------------------------------------
/r-VEX/src/ctrl.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Control unit
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- ctrl.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 |
34 | library work;
35 | use work.rVEX_pkg.all;
36 | use work.ctrl_operations.all;
37 |
38 | entity ctrl is
39 | port ( clk : in std_logic; -- system clock
40 | reset : in std_logic; -- system reset
41 | opcode : in std_logic_vector(6 downto 0); -- CTRL opcode
42 | pc : in std_logic_vector((ADDR_WIDTH - 1) downto 0); -- current program counter
43 | lr : in std_logic_vector(31 downto 0); -- current link register ($r0.63) contents
44 | sp : in std_logic_vector(31 downto 0); -- current stack pointer ($r0.1) contents
45 | offset : in std_logic_vector((BROFF_WIDTH - 1) downto 0); -- branch offset (imm or lr) value
46 | br : in std_logic; -- branch register contents
47 | in_valid : in std_logic; -- '1' when input is valud
48 |
49 | pc_goto : out std_logic_vector((ADDR_WIDTH - 1) downto 0); -- address to jump to
50 | result : out std_logic_vector(31 downto 0); -- new lr or sp value
51 | out_valid : out std_logic); -- '1' when output is valid
52 | end entity ctrl;
53 |
54 |
55 | architecture behavioural of ctrl is
56 | signal result_i : std_logic_vector(31 downto 0) := (others => '0');
57 | signal pc_goto_i : std_logic_vector((ADDR_WIDTH - 1) downto 0) := (others => '0');
58 | begin
59 | result <= result_i;
60 | pc_goto <= pc_goto_i;
61 |
62 | -- Controls CTRL operations
63 | ctrl_control : process(clk, reset)
64 | begin
65 | if (reset = '1') then
66 | out_valid <= '0';
67 | result_i <= (others => '0');
68 | pc_goto_i <= (others => '0');
69 | elsif (clk = '1' and clk'event) then
70 | if (in_valid = '1') then
71 | out_valid <= '1'; -- this will be overriden when a non-existent opcode is issued
72 | case opcode is
73 | when CTRL_GOTO =>
74 | pc_goto_i <= f_GOTO (offset);
75 | when CTRL_IGOTO =>
76 | pc_goto_i <= f_IGOTO (lr);
77 | when CTRL_CALL =>
78 | f_CALL (offset, pc, pc_goto_i, result_i);
79 | when CTRL_ICALL =>
80 | f_ICALL (lr, pc, pc_goto_i, result_i);
81 | when CTRL_BR =>
82 | pc_goto_i <= f_BR (offset, pc, br);
83 | when CTRL_BRF =>
84 | pc_goto_i <= f_BRF (offset, pc, br);
85 | when CTRL_RETURN =>
86 | f_RETURN (offset, lr, sp, pc_goto_i, result_i);
87 | when CTRL_RFI =>
88 | f_RETURN (offset, lr, sp, pc_goto_i, result_i);
89 | when CTRL_XNOP =>
90 | pc_goto_i <= (others => '0');
91 | when NOP =>
92 | pc_goto_i <= (others => '0');
93 | when others =>
94 | out_valid <= '0';
95 | end case;
96 | else
97 | out_valid <= '0';
98 | end if;
99 | end if;
100 | end process ctrl_control;
101 | end architecture behavioural;
102 |
103 |
--------------------------------------------------------------------------------
/r-VEX/src/ctrl_operations.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Package with control functions and procedures
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- All operations that can be performed by the control unit
29 | --------------------------------------------------------------------------------
30 | -- ctrl_operations.vhd
31 | --------------------------------------------------------------------------------
32 |
33 | library ieee;
34 | use ieee.std_logic_1164.all;
35 | use ieee.std_logic_signed.all;
36 | use ieee.numeric_std.all;
37 |
38 | library work;
39 | use work.rVEX_pkg.all;
40 |
41 | package ctrl_operations is
42 | function f_GOTO ( offset : std_logic_vector((BROFF_WIDTH - 1) downto 0))
43 | return std_logic_vector;
44 |
45 | function f_IGOTO ( lr : std_logic_vector(31 downto 0))
46 | return std_logic_vector;
47 |
48 | procedure f_CALL ( offset : in std_logic_vector((BROFF_WIDTH - 1) downto 0);
49 | pc : in std_logic_vector((ADDR_WIDTH - 1) downto 0);
50 | signal pc_goto : out std_logic_vector((ADDR_WIDTH - 1) downto 0);
51 | signal result : out std_logic_vector(31 downto 0));
52 |
53 | procedure f_ICALL ( lr : in std_logic_vector(31 downto 0);
54 | pc : in std_logic_vector((ADDR_WIDTH - 1) downto 0);
55 | signal pc_goto : out std_logic_vector((ADDR_WIDTH - 1) downto 0);
56 | signal result : out std_logic_vector(31 downto 0));
57 |
58 | function f_BR ( offset : std_logic_vector((BROFF_WIDTH - 1) downto 0);
59 | pc : std_logic_vector((ADDR_WIDTH - 1) downto 0);
60 | br : std_logic)
61 | return std_logic_vector;
62 |
63 | function f_BRF ( offset : std_logic_vector((BROFF_WIDTH - 1) downto 0);
64 | pc : std_logic_vector((ADDR_WIDTH - 1) downto 0);
65 | br : std_logic)
66 | return std_logic_vector;
67 |
68 | procedure f_RETURN ( offset : in std_logic_vector((BROFF_WIDTH - 1) downto 0);
69 | lr : in std_logic_vector(31 downto 0);
70 | sp : in std_logic_vector(31 downto 0);
71 | signal pc_goto : out std_logic_vector((ADDR_WIDTH - 1) downto 0);
72 | signal result : out std_logic_vector(31 downto 0));
73 | end package ctrl_operations;
74 |
75 |
76 | package body ctrl_operations is
77 | function f_GOTO ( offset : std_logic_vector((BROFF_WIDTH - 1) downto 0))
78 | return std_logic_vector is
79 | begin
80 | return offset((ADDR_WIDTH - 1) downto 0);
81 | end function f_GOTO;
82 |
83 | function f_IGOTO ( lr : std_logic_vector(31 downto 0))
84 | return std_logic_vector is
85 | begin
86 | return lr((ADDR_WIDTH - 1) downto 0);
87 | end function f_IGOTO;
88 |
89 | procedure f_CALL ( offset : in std_logic_vector((BROFF_WIDTH - 1) downto 0);
90 | pc : in std_logic_vector((ADDR_WIDTH - 1) downto 0);
91 | signal pc_goto : out std_logic_vector((ADDR_WIDTH - 1) downto 0);
92 | signal result : out std_logic_vector(31 downto 0)) is
93 | variable pc_tmp : std_logic_vector(31 downto 0) := (others => '0');
94 | begin
95 | pc_tmp((ADDR_WIDTH - 1) downto 0) := pc;
96 |
97 | pc_goto <= offset((ADDR_WIDTH - 1) downto 0);
98 | result <= pc_tmp + 1;
99 | end procedure f_CALL;
100 |
101 |
102 | procedure f_ICALL ( lr : in std_logic_vector(31 downto 0);
103 | pc : in std_logic_vector((ADDR_WIDTH - 1) downto 0);
104 | signal pc_goto : out std_logic_vector((ADDR_WIDTH - 1) downto 0);
105 | signal result : out std_logic_vector(31 downto 0)) is
106 | variable pc_tmp : std_logic_vector(31 downto 0) := (others => '0');
107 | begin
108 | pc_tmp((ADDR_WIDTH - 1) downto 0) := pc;
109 |
110 | pc_goto <= lr((ADDR_WIDTH - 1) downto 0);
111 | result <= pc_tmp + 1;
112 | end procedure f_ICALL;
113 |
114 | function f_BR ( offset : std_logic_vector((BROFF_WIDTH - 1) downto 0);
115 | pc : std_logic_vector((ADDR_WIDTH - 1) downto 0);
116 | br : std_logic)
117 | return std_logic_vector is
118 | begin
119 | if (br = '1') then
120 | return offset((ADDR_WIDTH - 1) downto 0);
121 | else
122 | return (pc + 1);
123 | end if;
124 | end function f_BR;
125 |
126 | function f_BRF ( offset : std_logic_vector((BROFF_WIDTH - 1) downto 0);
127 | pc : std_logic_vector((ADDR_WIDTH - 1) downto 0);
128 | br : std_logic)
129 | return std_logic_vector is
130 | begin
131 | if (br = '0') then
132 | return offset((ADDR_WIDTH - 1) downto 0);
133 | else
134 | return (pc + 1);
135 | end if;
136 | end function f_BRF;
137 |
138 | procedure f_RETURN ( offset : in std_logic_vector((BROFF_WIDTH - 1) downto 0);
139 | lr : in std_logic_vector(31 downto 0);
140 | sp : in std_logic_vector(31 downto 0);
141 | signal pc_goto : out std_logic_vector((ADDR_WIDTH - 1) downto 0);
142 | signal result : out std_logic_vector(31 downto 0)) is
143 | begin
144 | pc_goto <= lr((ADDR_WIDTH - 1) downto 0);
145 | result <= sp + offset;
146 | end procedure f_RETURN;
147 | end package body ctrl_operations;
148 |
149 |
--------------------------------------------------------------------------------
/r-VEX/src/d_mem.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Data memory
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- Implementation uses BRAM
29 | --------------------------------------------------------------------------------
30 | -- d_mem.vhd
31 | --------------------------------------------------------------------------------
32 |
33 | library ieee;
34 | use ieee.std_logic_1164.all;
35 | use ieee.std_logic_unsigned.all;
36 | use ieee.numeric_std.all;
37 |
38 | library work;
39 | use work.rVEX_pkg.all;
40 |
41 | entity d_mem is
42 | port ( clk : in std_logic; -- system clock
43 | write_en : in std_logic; -- write enable
44 | address_r1 : in std_logic_vector((DMEM_LOGDEP - 1) downto 0); -- address to read from (r-VEX)
45 | address_r2 : in std_logic_vector((DMEM_LOGDEP - 1) downto 0); -- address to read from (UART)
46 | address_w : in std_logic_vector((DMEM_LOGDEP - 1) downto 0); -- address to write to
47 | data_in : in std_logic_vector((DMEM_WIDTH - 1) downto 0); -- data to write
48 |
49 | data_out1 : out std_logic_vector((DMEM_WIDTH - 1) downto 0); -- data to be read (r-VEX)
50 | data_out2 : out std_logic_vector((DMEM_WIDTH - 1) downto 0)); -- data to be read (UART)
51 | end entity d_mem;
52 |
53 |
54 | architecture behavioural of d_mem is
55 | type mem_t is array (0 to (DMEM_DEPTH - 1)) of std_logic_vector((DMEM_WIDTH - 1) downto 0);
56 | signal d_memory : mem_t := (others => (others => '0'));
57 | begin
58 | mem_handler : process(clk)
59 | begin
60 | if (clk = '1' and clk'event) then
61 | if (write_en = '1') then
62 | d_memory(conv_integer(address_w)) <= data_in;
63 | end if;
64 |
65 | data_out1 <= d_memory(conv_integer(address_r1));
66 | data_out2 <= d_memory(conv_integer(address_r2));
67 | end if;
68 | end process mem_handler;
69 | end architecture behavioural;
70 |
71 |
--------------------------------------------------------------------------------
/r-VEX/src/fetch.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Instruction fetch unit
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- fetch.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_unsigned.all;
34 |
35 | entity fetch is
36 | port ( clk : in std_logic; -- system clock
37 | reset : in std_logic; -- system reset
38 | instr : in std_logic_vector(127 downto 0); -- instruction (4 syllables)
39 | next_instr : in std_logic; -- '1' when syllable is decoded
40 | start : in std_logic; -- '1' when to start execution of r-VEX
41 | stop : in std_logic; -- '1' when STOP syllable is decoded
42 | pc : in std_logic_vector(7 downto 0); -- current program counter
43 |
44 | syllable_0 : out std_logic_vector(31 downto 0); -- syllable 0
45 | syllable_1 : out std_logic_vector(31 downto 0); -- syllable 1
46 | syllable_2 : out std_logic_vector(31 downto 0); -- syllable 2
47 | syllable_3 : out std_logic_vector(31 downto 0); -- syllabel 3
48 | stop_out : out std_logic; -- '1' when execution has stopped
49 | cycles : out std_logic_vector(31 downto 0); -- number of clock cycles the execution took
50 | address : out std_logic_vector(7 downto 0); -- address in instruction memory to be read
51 | out_valid : out std_logic); -- '1' when syllables are valid
52 | end entity fetch;
53 |
54 | architecture behavioural of fetch is
55 | type fetch_states is (reset_state, waiting, send_syllables);
56 | signal current_state, next_state: fetch_states;
57 |
58 | signal running_s : std_logic := '0';
59 | signal cycles_i : std_logic_vector(31 downto 0) := x"00000000";
60 | signal stop_i : std_logic := '0';
61 | signal out_valid_i : std_logic := '0';
62 | begin
63 | out_valid <= out_valid_i;
64 | stop_out <= stop_i;
65 | cycles <= cycles_i;
66 |
67 | -- Counts running cycles
68 | cycle_counter : process(clk, reset)
69 | begin
70 | if (reset = '1') then
71 | cycles_i <= (others => '0');
72 | elsif (clk = '1' and clk'event) then
73 | if (running_s = '1' and stop_i = '0') then
74 | cycles_i <= cycles_i + 1;
75 | else
76 | cycles_i <= cycles_i;
77 | end if;
78 | end if;
79 | end process cycle_counter;
80 |
81 | -- Checks for stop signal
82 | -- TODO: move this to writeback stage
83 | stop_check : process(stop, reset) is
84 | begin
85 | if (reset = '1') then
86 | stop_i <= '0';
87 | elsif (stop = '1' and stop'event) then
88 | stop_i <= '1';
89 | end if;
90 | end process stop_check;
91 |
92 | -- Synchronizes fetch states
93 | synchronize : process (clk, reset)
94 | begin
95 | if (reset = '1') then
96 | current_state <= reset_state;
97 | elsif (clk = '1' and clk'event) then
98 | current_state <= next_state;
99 | end if;
100 | end process synchronize;
101 |
102 | -- Output
103 | fetch_out : process(current_state, pc, instr) is
104 | begin
105 | syllable_0 <= (others => 'X');
106 | syllable_1 <= (others => 'X');
107 | address <= (others => 'X');
108 |
109 | case current_state is
110 | when reset_state =>
111 | syllable_0 <= (others => '0');
112 | syllable_1 <= (others => '0');
113 | syllable_2 <= (others => '0');
114 | syllable_3 <= (others => '0');
115 | address <= (others => '0');
116 | out_valid_i <= '0';
117 | running_s <= '0';
118 | when waiting =>
119 | syllable_0 <= instr(31 downto 0);
120 | syllable_1 <= instr(63 downto 32);
121 | syllable_2 <= instr(95 downto 64);
122 | syllable_3 <= instr(127 downto 96);
123 | address <= pc;
124 | out_valid_i <= '0';
125 | running_s <= '1';
126 | when send_syllables =>
127 | syllable_0 <= instr(31 downto 0);
128 | syllable_1 <= instr(63 downto 32);
129 | syllable_2 <= instr(95 downto 64);
130 | syllable_3 <= instr(127 downto 96);
131 | address <= pc;
132 | out_valid_i <= '1';
133 | running_s <= '1';
134 | end case;
135 | end process fetch_out;
136 |
137 | -- Controls syllable fetch stage
138 | fetch_control: process(clk, current_state, start, stop_i, next_instr)
139 | begin
140 | case current_state is
141 | when reset_state =>
142 | if (start = '1' and stop_i = '0') then
143 | next_state <= waiting;
144 | else
145 | next_state <= reset_state;
146 | end if;
147 | when waiting =>
148 | if (next_instr = '1' and stop_i = '0') then
149 | next_state <= send_syllables;
150 | else
151 | next_state <= waiting;
152 | end if;
153 | when send_syllables =>
154 | if (next_instr = '0' and stop_i = '0') then
155 | next_state <= waiting;
156 | else
157 | next_state <= send_syllables;
158 | end if;
159 | end case;
160 | end process fetch_control;
161 | end architecture behavioural;
162 |
163 |
--------------------------------------------------------------------------------
/r-VEX/src/i_mem.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Instruction ROM
3 | --------------------------------------------------------------------------------
4 | --
5 | -- This file was assembled by r-ASM, the r-VEX assembler/
6 | -- instruction ROM generator.
7 | --
8 | -- source file: ../../demos/fibonacci.s
9 | -- r-ASM flags: ./rasm ../../demos/fibonacci.s
10 | -- date & time: Aug 19, 2008 @ 22:34:28
11 | --
12 | -- r-VEX & r-ASM are
13 | -- Copyright (c) 2008, Thijs van As
14 | --
15 | -- Computer Engineering Laboratory
16 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
17 | -- Delft University of Technology
18 | -- Delft, The Netherlands
19 | --
20 | -- http://r-vex.googlecode.com
21 | --
22 | -- r-VEX is free hardware: you can redistribute it and/or modify
23 | -- it under the terms of the GNU General Public License as published by
24 | -- the Free Software Foundation, either version 3 of the License, or
25 | -- (at your option) any later version.
26 | --
27 | -- This program is distributed in the hope that it will be useful,
28 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
29 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 | -- GNU General Public License for more details.
31 | --
32 | -- You should have received a copy of the GNU General Public License
33 | -- along with this program. If not, see .
34 | --
35 | --------------------------------------------------------------------------------
36 | -- i_mem.vhd (generated by r-ASM)
37 | --------------------------------------------------------------------------------
38 |
39 | library ieee;
40 | use ieee.std_logic_1164.all;
41 |
42 | entity i_mem is
43 | port ( reset : in std_logic; -- system reset
44 | address : in std_logic_vector(7 downto 0); -- address of instruction to be read
45 |
46 | instr : out std_logic_vector(127 downto 0)); -- instruction (4 syllables)
47 | end entity i_mem;
48 |
49 |
50 | architecture behavioural of i_mem is
51 | begin
52 | memory : process(address, reset)
53 | begin
54 | if (reset = '1') then
55 | instr <= x"00000000000000000000000000000000";
56 | else
57 | case address is
58 | when x"00" => instr <= "10000010100111100000000000000110"& -- add $r0.15 = $r0.0, 1
59 | "10110000000000100000000000000000"& -- mov $r0.1 = $r0.0
60 | "10000010100101000000000010110000"& -- add $r0.10 = $r0.0, 44
61 | "10000010100001000000000000000101"; -- add $r0.2 = $r0.0, 1
62 | -- LABEL_BEGIN:
63 | when x"01" => instr <= "10000010000001000000100001000010"& -- add $r0.2 = $r0.1, $r0.2
64 | "10000010000001100000000001000000"& -- add $r0.3 = $r0.0, $r0.2
65 | "10110010000000000100100101000000"& -- cmpeq $b0.0 = $r0.9, $r0.10
66 | "01001011000000000000000001100001"; -- br $b0.0, LABEL_END
67 | when x"02" => instr <= "10000010100100100100100000000110"& -- add $r0.9 = $r0.9, 1
68 | "10000010000000100000000001100000"& -- add $r0.1 = $r0.0, $r0.3
69 | "00000000000000000000000000000000"& -- nop
70 | "01000011000000000000000000100001"; -- goto LABEL_BEGIN
71 | -- LABEL_END:
72 | when x"03" => instr <= "00101100000000100111100000000010"& -- stw 0x0[$r0.15] = $r0.1
73 | "10110000000100100000000000000000"& -- mov $r0.9 = $r0.0
74 | "00000000000000000000000000000000"& -- nop
75 | "00000000000000000000000000000001"; -- nop
76 | when others => instr <= "00000000000000000000000000000010"& -- nop
77 | "00000000000000000000000000000000"& -- nop
78 | "00000000000000000000000000000000"& -- nop
79 | "00111110000000000000000000000001"; -- stop
80 | end case;
81 | end if;
82 | end process memory;
83 | end architecture behavioural;
84 |
85 |
--------------------------------------------------------------------------------
/r-VEX/src/mem.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Memory unit
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- mem.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_unsigned.all;
34 | use ieee.numeric_std.all;
35 |
36 | library work;
37 | use work.rVEX_pkg.all;
38 | use work.mem_operations.all;
39 |
40 | entity mem is
41 | port ( clk : in std_logic; -- system clock
42 | reset : in std_logic; -- system reset
43 | opcode : in std_logic_vector(6 downto 0); -- opcode
44 | data_reg : in std_logic_vector(31 downto 0); -- register contents to store
45 | pos_off : in std_logic_vector(1 downto 0); -- offset in data memory
46 | data_ld : in std_logic_vector((DMEM_WIDTH - 1) downto 0); -- data loaded from memory
47 | in_valid : in std_logic; -- '1' when input is valid
48 |
49 | data_st : out std_logic_vector((DMEM_WIDTH - 1) downto 0); -- data to be stored in memory
50 | data_2reg : out std_logic_vector(31 downto 0); -- data from memory to be stored in register
51 | out_valid : out std_logic); -- '1' when output is valid
52 | end entity mem;
53 |
54 |
55 | architecture behavioural of mem is
56 | signal result_s : std_logic_vector((DMEM_WIDTH - 1) downto 0) := (others => '0');
57 |
58 | type mem_states is (reset_state, waiting, load, store, output_load,
59 | output_store, output_store1);
60 | signal current_state, next_state : mem_states;
61 | begin
62 | -- Calculates load/store values
63 | mem_cal : process(clk, reset)
64 | begin
65 | if (reset = '1') then
66 | result_s <= (others => '0');
67 | elsif (clk = '1' and clk'event) then
68 | case opcode is
69 | when MEM_LDW =>
70 | result_s <= f_LDW (data_ld);
71 | when MEM_LDH =>
72 | result_s <= f_LDH (data_ld, pos_off);
73 | when MEM_LDHU =>
74 | result_s <= f_LDHU (data_ld, pos_off);
75 | when MEM_LDB =>
76 | result_s <= f_LDB (data_ld, pos_off);
77 | when MEM_LDBU =>
78 | result_s <= f_LDBU (data_ld, pos_off);
79 | when MEM_STW =>
80 | result_s <= f_STW (data_reg);
81 | when MEM_STH =>
82 | result_s <= f_STH (data_ld, data_reg, pos_off);
83 | when MEM_STB =>
84 | result_s <= f_STB (data_ld, data_reg, pos_off);
85 | when others =>
86 | result_s <= (others => '0');
87 | end case;
88 | end if;
89 | end process mem_cal;
90 |
91 | -- Synchronizes MEM states
92 | mem_sync : process(clk, reset)
93 | begin
94 | if (reset = '1') then
95 | current_state <= reset_state;
96 | elsif (clk = '1' and clk'event) then
97 | current_state <= next_state;
98 | end if;
99 | end process mem_sync;
100 |
101 | -- Controls outputs of memory unit
102 | mem_output : process(current_state, result_s)
103 | begin
104 | case current_state is
105 | when reset_state =>
106 | data_st <= (others => '0');
107 | data_2reg <= (others => '0');
108 | out_valid <= '0';
109 | when waiting =>
110 | data_st <= (others => '0');
111 | data_2reg <= (others => '0');
112 | out_valid <= '0';
113 | when load =>
114 | data_st <= (others => '0');
115 | data_2reg <= result_s;
116 | out_valid <= '0';
117 | when store =>
118 | data_st <= result_s;
119 | data_2reg <= (others => '0');
120 | out_valid <= '0';
121 | when output_load =>
122 | data_st <= (others => '0');
123 | data_2reg <= result_s;
124 | out_valid <= '1';
125 | when output_store =>
126 | data_st <= result_s;
127 | data_2reg <= (others => '0');
128 | out_valid <= '1';
129 | when output_store1 =>
130 | data_st <= result_s;
131 | data_2reg <= (others => '0');
132 | out_valid <= '1';
133 | end case;
134 | end process mem_output;
135 |
136 | -- Controls MEM operations
137 | mem_control : process(clk, current_state, in_valid, opcode)
138 | begin
139 | case current_state is
140 | when reset_state =>
141 | next_state <= waiting;
142 | when waiting =>
143 | if (in_valid = '1' and std_match(opcode, MEM_OP)) then
144 | if (std_match(opcode, MEM_STW) or std_match(opcode, MEM_STH)
145 | or std_match(opcode, MEM_STB)) then
146 | -- store operation
147 | next_state <= store;
148 | else
149 | -- load operation
150 | next_state <= load;
151 | end if;
152 | else
153 | next_state <= waiting;
154 | end if;
155 | when load =>
156 | next_state <= output_load;
157 | when store =>
158 | next_state <= output_store;
159 | when output_load =>
160 | next_state <= waiting;
161 | when output_store =>
162 | next_state <= output_store1;
163 | when output_store1 =>
164 | next_state <= waiting;
165 | end case;
166 | end process mem_control;
167 | end architecture behavioural;
168 |
169 |
--------------------------------------------------------------------------------
/r-VEX/src/mem_operations.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Package with memory functions and procedures
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- All operations that can be performed by the memory unit
29 | --------------------------------------------------------------------------------
30 | -- mem_operations.vhd
31 | --------------------------------------------------------------------------------
32 |
33 | library ieee;
34 | use ieee.std_logic_1164.all;
35 | use ieee.std_logic_signed.all;
36 | use ieee.numeric_std.all;
37 |
38 | library work;
39 | use work.rVEX_pkg.all;
40 |
41 | package mem_operations is
42 | function f_LDW ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0))
43 | return std_logic_vector;
44 |
45 | function f_LDH ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
46 | pos : std_logic_vector(1 downto 0))
47 | return std_logic_vector;
48 |
49 | function f_LDHU ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
50 | pos : std_logic_vector(1 downto 0))
51 | return std_logic_vector;
52 |
53 | function f_LDB ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
54 | pos : std_logic_vector(1 downto 0))
55 | return std_logic_vector;
56 |
57 | function f_LDBU ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
58 | pos : std_logic_vector(1 downto 0))
59 | return std_logic_vector;
60 |
61 | function f_STW ( reg_val : std_logic_vector(31 downto 0))
62 | return std_logic_vector;
63 |
64 | function f_STH ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
65 | reg_val : std_logic_vector(31 downto 0);
66 | pos : std_logic_vector(1 downto 0))
67 | return std_logic_vector;
68 |
69 | function f_STB ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
70 | reg_val : std_logic_vector(31 downto 0);
71 | pos : std_logic_vector(1 downto 0))
72 | return std_logic_vector;
73 | end package mem_operations;
74 |
75 |
76 | package body mem_operations is
77 | function f_LDW ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0))
78 | return std_logic_vector is
79 | begin
80 | return mem_val;
81 | end function f_LDW;
82 |
83 | function f_LDH ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
84 | pos : std_logic_vector(1 downto 0))
85 | return std_logic_vector is
86 | begin
87 | case pos is
88 | when "00" =>
89 | return (x"0000" & mem_val(31 downto 16));
90 | when "01" =>
91 | return (x"0000" & mem_val(23 downto 8));
92 | when "10" =>
93 | return (x"0000" & mem_val(15 downto 0));
94 | when others => -- not allowed
95 | return x"FFFFFFFF";
96 | end case;
97 | end function f_LDH;
98 |
99 | -- currently the same as LDHU, FIX this when data memory is more important
100 | function f_LDHU ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
101 | pos : std_logic_vector(1 downto 0))
102 | return std_logic_vector is
103 | begin
104 | case pos is
105 | when "00" =>
106 | return (x"0000" & mem_val(31 downto 16));
107 | when "01" =>
108 | return (x"0000" & mem_val(23 downto 8));
109 | when "10" =>
110 | return (x"0000" & mem_val(15 downto 0));
111 | when others => -- not allowed
112 | return x"FFFFFFFF";
113 | end case;
114 | end function f_LDHU;
115 |
116 | function f_LDB ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
117 | pos : std_logic_vector(1 downto 0))
118 | return std_logic_vector is
119 | begin
120 | case pos is
121 | when "00" =>
122 | return (x"000000" & mem_val(31 downto 24));
123 | when "01" =>
124 | return (x"000000" & mem_val(23 downto 16));
125 | when "10" =>
126 | return (x"000000" & mem_val(15 downto 8));
127 | when others =>
128 | return (x"000000" & mem_val(7 downto 0));
129 | end case;
130 | end function f_LDB;
131 |
132 | -- currently the same as LDB, FIX this more important
133 | function f_LDBU ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
134 | pos : std_logic_vector(1 downto 0))
135 | return std_logic_vector is
136 | begin
137 | case pos is
138 | when "00" =>
139 | return (x"000000" & mem_val(31 downto 24));
140 | when "01" =>
141 | return (x"000000" & mem_val(23 downto 16));
142 | when "10" =>
143 | return (x"000000" & mem_val(15 downto 8));
144 | when others =>
145 | return (x"000000" & mem_val(7 downto 0));
146 | end case;
147 | end function f_LDBU;
148 |
149 | function f_STW ( reg_val : std_logic_vector(31 downto 0))
150 | return std_logic_vector is
151 | begin
152 | return reg_val;
153 | end function f_STW;
154 |
155 | function f_STH ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
156 | reg_val : std_logic_vector(31 downto 0);
157 | pos : std_logic_vector(1 downto 0))
158 | return std_logic_vector is
159 | begin
160 | case pos is
161 | when "00" =>
162 | return (reg_val(15 downto 0) & mem_val(15 downto 0));
163 | when "01" =>
164 | return (mem_val(31 downto 24) & reg_val(15 downto 0) & mem_val(7 downto 0));
165 | when "10" =>
166 | return (mem_val(31 downto 16) & reg_val(15 downto 0));
167 | when others => -- not allowed
168 | return x"FFFFFFFF";
169 | end case;
170 | end function f_STH;
171 |
172 | function f_STB ( mem_val : std_logic_vector((DMEM_WIDTH - 1) downto 0);
173 | reg_val : std_logic_vector(31 downto 0);
174 | pos : std_logic_vector(1 downto 0))
175 | return std_logic_vector is
176 | begin
177 | case pos is
178 | when "00" =>
179 | return (reg_val(7 downto 0) & mem_val(23 downto 0));
180 | when "01" =>
181 | return (mem_val(31 downto 24) & reg_val(7 downto 0) & mem_val(15 downto 0));
182 | when "10" =>
183 | return (mem_val(31 downto 16) & reg_val(7 downto 0) & mem_val(7 downto 0));
184 | when others =>
185 | return (mem_val(31 downto 8) & reg_val(7 downto 0));
186 | end case;
187 | end function f_STB;
188 | end package body mem_operations;
189 |
190 |
--------------------------------------------------------------------------------
/r-VEX/src/mul.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Multiplier
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- mul.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 |
34 | library work;
35 | use work.rVEX_pkg.all;
36 | use work.mul_operations.all;
37 |
38 | entity mul is
39 | port ( clk : in std_logic; -- system clock
40 | reset : in std_logic; -- system reset
41 | mulop : in std_logic_vector(6 downto 0); -- operation
42 | src1 : in std_logic_vector(31 downto 0); -- operand 1
43 | src2 : in std_logic_vector(31 downto 0); -- operand 2
44 |
45 | result : out std_logic_vector(31 downto 0); -- result of operation
46 | overflow : out std_logic; -- '1' when overflow
47 | out_valid : out std_logic); -- '1' when output is valid
48 | end entity mul;
49 |
50 |
51 | architecture behavioural of mul is
52 | signal result_i : std_logic_vector(31 downto 0) := (others => '0');
53 | signal overflow_i : std_logic := '0';
54 | begin
55 | result <= result_i;
56 | overflow <= overflow_i;
57 |
58 | -- Controls MUL operations
59 | mul_control : process(clk, reset)
60 | begin
61 | if (reset = '1') then
62 | out_valid <= '0';
63 | result_i <= (others => '0');
64 | overflow_i <= '0';
65 | elsif (clk = '1' and clk'event) then
66 | out_valid <= '1'; -- this will be overriden when a non-existent opcode is issued
67 |
68 | case mulop is
69 | when MUL_MPYLL =>
70 | f_MPYLL (src1, src2, overflow_i, result_i);
71 | when MUL_MPYLLU =>
72 | f_MPYLLU (src1, src2, overflow_i, result_i);
73 | when MUL_MPYLH =>
74 | f_MPYLH (src1, src2, overflow_i, result_i);
75 | when MUL_MPYLHU =>
76 | f_MPYLHU (src1, src2, overflow_i, result_i);
77 | when MUL_MPYHH =>
78 | f_MPYHH (src1, src2, overflow_i, result_i);
79 | when MUL_MPYHHU =>
80 | f_MPYHHU (src1, src2, overflow_i, result_i);
81 | when MUL_MPYL =>
82 | f_MPYL (src1, src2, overflow_i, result_i);
83 | when MUL_MPYLU =>
84 | f_MPYLU (src1, src2, overflow_i, result_i);
85 | when MUL_MPYH =>
86 | f_MPYH (src1, src2, overflow_i, result_i);
87 | when MUL_MPYHU =>
88 | f_MPYH (src1, src2, overflow_i, result_i);
89 | when MUL_MPYHS =>
90 | f_MPYH (src1, src2, overflow_i, result_i);
91 | when NOP =>
92 | overflow_i <= '0';
93 | result_i <= (others => '0');
94 | when others =>
95 | out_valid <= '0';
96 | end case;
97 | end if;
98 | end process mul_control;
99 | end architecture behavioural;
100 |
101 |
--------------------------------------------------------------------------------
/r-VEX/src/mul_operations.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Package with multiplier procedures
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- All operations that can be performed by the multiplier
29 | --------------------------------------------------------------------------------
30 | -- mul_operations.vhd
31 | --------------------------------------------------------------------------------
32 |
33 | library ieee;
34 | use ieee.std_logic_1164.all;
35 | use ieee.std_logic_signed.all;
36 | use ieee.numeric_std.all;
37 |
38 | package mul_operations is
39 | procedure f_MPYLL ( s1, s2 : in std_logic_vector(31 downto 0);
40 | signal overflow : out std_logic;
41 | signal result : out std_logic_vector(31 downto 0));
42 |
43 | procedure f_MPYLLU ( s1, s2 : in std_logic_vector(31 downto 0);
44 | signal overflow : out std_logic;
45 | signal result : out std_logic_vector(31 downto 0));
46 |
47 | procedure f_MPYLH ( s1, s2 : in std_logic_vector(31 downto 0);
48 | signal overflow : out std_logic;
49 | signal result : out std_logic_vector(31 downto 0));
50 |
51 | procedure f_MPYLHU ( s1, s2 : in std_logic_vector(31 downto 0);
52 | signal overflow : out std_logic;
53 | signal result : out std_logic_vector(31 downto 0));
54 |
55 | procedure f_MPYHH ( s1, s2 : in std_logic_vector(31 downto 0);
56 | signal overflow : out std_logic;
57 | signal result : out std_logic_vector(31 downto 0));
58 |
59 | procedure f_MPYHHU ( s1, s2 : in std_logic_vector(31 downto 0);
60 | signal overflow : out std_logic;
61 | signal result : out std_logic_vector(31 downto 0));
62 |
63 | procedure f_MPYL ( s1, s2 : in std_logic_vector(31 downto 0);
64 | signal overflow : out std_logic;
65 | signal result : out std_logic_vector(31 downto 0));
66 |
67 | procedure f_MPYLU ( s1, s2 : in std_logic_vector(31 downto 0);
68 | signal overflow : out std_logic;
69 | signal result : out std_logic_vector(31 downto 0));
70 |
71 | procedure f_MPYH ( s1, s2 : in std_logic_vector(31 downto 0);
72 | signal overflow : out std_logic;
73 | signal result : out std_logic_vector(31 downto 0));
74 |
75 | procedure f_MPYHU ( s1, s2 : in std_logic_vector(31 downto 0);
76 | signal overflow : out std_logic;
77 | signal result : out std_logic_vector(31 downto 0));
78 |
79 | procedure f_MPYHS ( s1, s2 : in std_logic_vector(31 downto 0);
80 | signal overflow : out std_logic;
81 | signal result : out std_logic_vector(31 downto 0));
82 | end package mul_operations;
83 |
84 |
85 | package body mul_operations is
86 | procedure f_MPYLL ( s1, s2 : in std_logic_vector(31 downto 0);
87 | signal overflow : out std_logic;
88 | signal result : out std_logic_vector(31 downto 0)) is
89 | begin
90 | overflow <= '0';
91 | result <= std_logic_vector((signed(s1(15 downto 0)) * signed(s2(15 downto 0))));
92 | end procedure f_MPYLL;
93 |
94 | procedure f_MPYLLU ( s1, s2 : in std_logic_vector(31 downto 0);
95 | signal overflow : out std_logic;
96 | signal result : out std_logic_vector(31 downto 0)) is
97 | begin
98 | overflow <= '0';
99 | result <= std_logic_vector((unsigned(s1(15 downto 0)) * unsigned(s2(15 downto 0))));
100 | end procedure f_MPYLLU;
101 |
102 | procedure f_MPYLH ( s1, s2 : in std_logic_vector(31 downto 0);
103 | signal overflow : out std_logic;
104 | signal result : out std_logic_vector(31 downto 0)) is
105 | begin
106 | overflow <= '0';
107 | result <= std_logic_vector((signed(s1(15 downto 0)) * signed(s2(31 downto 16))));
108 | end procedure f_MPYLH;
109 |
110 | procedure f_MPYLHU ( s1, s2 : in std_logic_vector(31 downto 0);
111 | signal overflow : out std_logic;
112 | signal result : out std_logic_vector(31 downto 0)) is
113 | begin
114 | overflow <= '0';
115 | result <= std_logic_vector((unsigned(s1(15 downto 0)) * unsigned(s2(31 downto 16))));
116 | end procedure f_MPYLHU;
117 |
118 | procedure f_MPYHH ( s1, s2 : in std_logic_vector(31 downto 0);
119 | signal overflow : out std_logic;
120 | signal result : out std_logic_vector(31 downto 0)) is
121 | begin
122 | overflow <= '0';
123 | result <= std_logic_vector((signed(s1(31 downto 16)) * signed(s2(31 downto 16))));
124 | end procedure f_MPYHH;
125 |
126 | procedure f_MPYHHU ( s1, s2 : in std_logic_vector(31 downto 0);
127 | signal overflow : out std_logic;
128 | signal result : out std_logic_vector(31 downto 0)) is
129 | begin
130 | overflow <= '0';
131 | result <= std_logic_vector((signed(s1(31 downto 16)) * signed(s2(31 downto 16))));
132 | end procedure f_MPYHHU;
133 |
134 | procedure f_MPYL ( s1, s2 : in std_logic_vector(31 downto 0);
135 | signal overflow : out std_logic;
136 | signal result : out std_logic_vector(31 downto 0)) is
137 | variable tmp : std_logic_vector(47 downto 0) := (others => '0');
138 | begin
139 | tmp := std_logic_vector((signed(s1(31 downto 0)) * signed(s2(15 downto 0))));
140 |
141 | if (tmp(47 downto 32) > 0) then
142 | overflow <= '1';
143 | if (tmp(47) = '1') then -- negative result
144 | result <= x"80000000";
145 | else -- positive result
146 | result <= x"7FFFFFFF";
147 | end if;
148 | else
149 | overflow <= '0';
150 | result <= tmp(31 downto 0);
151 | end if;
152 | end procedure f_MPYL;
153 |
154 | procedure f_MPYLU ( s1, s2 : in std_logic_vector(31 downto 0);
155 | signal overflow : out std_logic;
156 | signal result : out std_logic_vector(31 downto 0)) is
157 | variable tmp : std_logic_vector(47 downto 0) := (others => '0');
158 | begin
159 | tmp := std_logic_vector((unsigned(s1(31 downto 0)) * unsigned(s2(15 downto 0))));
160 |
161 | if (tmp(47 downto 32) > 0) then
162 | overflow <= '1';
163 | result <= x"FFFFFFFF";
164 | else
165 | overflow <= '0';
166 | result <= tmp(31 downto 0);
167 | end if;
168 | end procedure f_MPYLU;
169 |
170 | procedure f_MPYH ( s1, s2 : in std_logic_vector(31 downto 0);
171 | signal overflow : out std_logic;
172 | signal result : out std_logic_vector(31 downto 0)) is
173 | variable tmp : std_logic_vector(47 downto 0) := (others => '0');
174 | begin
175 | tmp := std_logic_vector((signed(s1(31 downto 0)) * signed(s2(31 downto 16))));
176 |
177 | if (tmp(47 downto 32) > 0) then
178 | overflow <= '1';
179 | if (tmp(47) = '1') then -- negative result
180 | result <= x"80000000";
181 | else -- positive result
182 | result <= x"7FFFFFFF";
183 | end if;
184 | else
185 | overflow <= '0';
186 | result <= tmp(31 downto 0);
187 | end if;
188 | end procedure f_MPYH;
189 |
190 | procedure f_MPYHU ( s1, s2 : in std_logic_vector(31 downto 0);
191 | signal overflow : out std_logic;
192 | signal result : out std_logic_vector(31 downto 0)) is
193 | variable tmp : std_logic_vector(47 downto 0) := (others => '0');
194 | begin
195 | tmp := std_logic_vector((unsigned(s1(31 downto 0)) * unsigned(s2(31 downto 16))));
196 |
197 | if (tmp(47 downto 32) > 0) then
198 | overflow <= '1';
199 | result <= x"FFFFFFFF";
200 | else
201 | overflow <= '0';
202 | result <= tmp(31 downto 0);
203 | end if;
204 | end procedure f_MPYHU;
205 |
206 | procedure f_MPYHS ( s1, s2 : in std_logic_vector(31 downto 0);
207 | signal overflow : out std_logic;
208 | signal result : out std_logic_vector(31 downto 0)) is
209 | variable tmp : std_logic_vector(47 downto 0) := (others => '0');
210 | variable tmp2 : std_logic_vector(47 downto 0) := (others => '0');
211 | begin
212 | tmp := (std_logic_vector((signed(s1(31 downto 0)) * signed(s2(31 downto 16)))));
213 |
214 | if (tmp(47 downto 32) > 0) then
215 | overflow <= '1';
216 | result <= x"FFFFFFFF";
217 | else
218 | overflow <= '0';
219 | tmp2 := (SHL (tmp, "10000"));
220 | result <= tmp2(31 downto 0);
221 | end if;
222 | end procedure f_MPYHS;
223 | end package body mul_operations;
224 |
225 |
--------------------------------------------------------------------------------
/r-VEX/src/pc.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Program Counter
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- pc.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_unsigned.all;
34 |
35 | library work;
36 | use work.rVEX_pkg.all;
37 |
38 | entity program_counter is
39 | port ( reset : in std_logic; -- system reset
40 | update_pc : in std_logic; -- update program counter on positive edge of update_pc
41 | pc_goto : in std_logic_vector((ADDR_WIDTH - 1) downto 0); -- branch-updated program counter value
42 |
43 | pc : out std_logic_vector((ADDR_WIDTH - 1) downto 0)); -- current program counter
44 | end entity program_counter;
45 |
46 |
47 | architecture behavioural of program_counter is
48 | signal pc_current_i : std_logic_vector((ADDR_WIDTH - 1) downto 0) := x"FF";
49 | begin
50 | pc <= pc_current_i;
51 |
52 | update_counter : process (update_pc, pc_current_i, pc_goto, reset)
53 | begin
54 | if (reset = '1') then
55 | pc_current_i <= x"FF";
56 | elsif (update_pc = '1' and update_pc'event) then
57 | pc_current_i <= pc_goto;
58 | end if;
59 | end process update_counter;
60 | end architecture behavioural;
61 |
62 |
--------------------------------------------------------------------------------
/r-VEX/src/r-vex_pkg.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Package with common definitions and opcodes
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- r-vex_pkg.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_signed.all;
34 | use ieee.numeric_std.all;
35 |
36 | package rVEX_pkg is
37 | --------------------------------------------------------------------------------
38 | -- Common definitions
39 | --------------------------------------------------------------------------------
40 | -- Active low/high logic on FPGA board
41 | constant ACTIVE_LOW : std_logic := '1'; -- '1' for Virtex-II Pro board, '0' for Spartan-3E board
42 |
43 | -- Register file definitions
44 | constant GR_DEPTH : integer := 32; -- Depth of general purpose register file
45 | constant BR_DEPTH : integer := 8; -- Depth of branch register file
46 |
47 | -- Memory address definitions
48 | constant ADDR_WIDTH : integer := 8; -- Width of the instruction memory address vector
49 | constant BROFF_WIDTH : integer := 12; -- Width of branch offset immediate values
50 | constant DMEM_WIDTH : integer := 32; -- Width of the data memory registers
51 | constant DMEM_DEPTH : integer := 256; -- Depth of the data memory regissters
52 | constant DMEM_LOGDEP : integer := 8; -- 2log of DMEM_DEPTH
53 |
54 | -- Immediate types
55 | constant NO_IMM : std_logic_vector(1 downto 0) := "00"; -- No immediate
56 | constant SHORT_IMM : std_logic_vector(1 downto 0) := "01"; -- Short immediate
57 | constant BRANCH_IMM : std_logic_vector(1 downto 0) := "10"; -- Branch offset immediate
58 | constant LONG_IMM : std_logic_vector(1 downto 0) := "11"; -- Long immediate
59 |
60 | -- Writeback targets
61 | constant WRITE_G : std_logic_vector(2 downto 0) := "001"; -- Write to GR register file
62 | constant WRITE_B : std_logic_vector(2 downto 0) := "010"; -- Write to BR register file
63 | constant WRITE_G_B : std_logic_vector(2 downto 0) := "011"; -- Write to GR and BR register files
64 | constant WRITE_P : std_logic_vector(2 downto 0) := "100"; -- Write to program counter
65 | constant WRITE_P_G : std_logic_vector(2 downto 0) := "101"; -- Write to program counter and GR register file
66 | constant WRITE_M : std_logic_vector(2 downto 0) := "110"; -- Write to data memory
67 | constant WRITE_MG : std_logic_vector(2 downto 0) := "111"; -- Write to GR register file, with memory unit input
68 | constant WRITE_NOP : std_logic_vector(2 downto 0) := "000"; -- Don't write back
69 |
70 | constant SEL_EXE : std_logic := '0'; -- Select execute unit as source for GR writeback
71 | constant SEL_MEM : std_logic := '1'; -- Select memory unit as source for GR writeback
72 |
73 | --------------------------------------------------------------------------------
74 | -- Opcodes
75 | --------------------------------------------------------------------------------
76 | constant ALU_OP : std_logic_vector(6 downto 0) := "1------"; -- ALU operation
77 | constant MUL_OP : std_logic_vector(6 downto 0) := "000----"; -- MUL operation
78 | constant CTRL_OP : std_logic_vector(6 downto 0) := "010----"; -- CTRL operation
79 | constant MEM_OP : std_logic_vector(6 downto 0) := "001----"; -- MEM operation
80 |
81 | constant STOP : std_logic_vector(6 downto 0) := "0011111"; -- STOP operation
82 | constant NOP : std_logic_vector(6 downto 0) := "0000000"; -- No operation
83 |
84 | -- ALU opcodes (integer arithmetic operations)
85 | constant ALU_ADD : std_logic_vector(6 downto 0) := "1000001"; -- Add
86 | constant ALU_AND : std_logic_vector(6 downto 0) := "1000011"; -- Bitwise AND
87 | constant ALU_ANDC : std_logic_vector(6 downto 0) := "1000100"; -- Bitwise complement and AND
88 | constant ALU_MAX : std_logic_vector(6 downto 0) := "1000101"; -- Maximum signed
89 | constant ALU_MAXU : std_logic_vector(6 downto 0) := "1000110"; -- Maximum unsigned
90 | constant ALU_MIN : std_logic_vector(6 downto 0) := "1000111"; -- Minimum signed
91 | constant ALU_MINU : std_logic_vector(6 downto 0) := "1001000"; -- Minimum unsigned
92 | constant ALU_OR : std_logic_vector(6 downto 0) := "1001001"; -- Bitwise OR
93 | constant ALU_ORC : std_logic_vector(6 downto 0) := "1001010"; -- Bitwise complement and OR
94 | constant ALU_SH1ADD : std_logic_vector(6 downto 0) := "1001011"; -- Shift left 1 and add
95 | constant ALU_SH2ADD : std_logic_vector(6 downto 0) := "1001100"; -- Shift left 2 and add
96 | constant ALU_SH3ADD : std_logic_vector(6 downto 0) := "1001101"; -- Shift left 3 and add
97 | constant ALU_SH4ADD : std_logic_vector(6 downto 0) := "1001110"; -- Shift left 4 and add
98 | constant ALU_SHL : std_logic_vector(6 downto 0) := "1001111"; -- Shift left
99 | constant ALU_SHR : std_logic_vector(6 downto 0) := "1010000"; -- Shift right signed
100 | constant ALU_SHRU : std_logic_vector(6 downto 0) := "1010001"; -- Shift right unsigned
101 | constant ALU_SUB : std_logic_vector(6 downto 0) := "1010010"; -- Subtract
102 | constant ALU_SXTB : std_logic_vector(6 downto 0) := "1010011"; -- Sign extend byte
103 | constant ALU_SXTH : std_logic_vector(6 downto 0) := "1010100"; -- Sign extend half word
104 | constant ALU_ZXTB : std_logic_vector(6 downto 0) := "1010101"; -- Zero extend byte
105 | constant ALU_ZXTH : std_logic_vector(6 downto 0) := "1010110"; -- Zero extend half word
106 | constant ALU_XOR : std_logic_vector(6 downto 0) := "1010111"; -- Bitwise XOR
107 | constant ALU_MOV : std_logic_vector(6 downto 0) := "1011000"; -- Copy s1 to other location
108 |
109 | -- ALU opcodes (logical and select operations)
110 | --
111 | -- This block of operation can operate on a GR register or a BR registers as target.
112 | -- See syllable_layout.txt for more information
113 | constant ALU_CMPEQ : std_logic_vector(6 downto 0) := "1011001"; -- Compare: equal
114 | constant ALU_CMPGE : std_logic_vector(6 downto 0) := "1011010"; -- Compare: greater equal signed
115 | constant ALU_CMPGEU : std_logic_vector(6 downto 0) := "1011011"; -- Compare: greater equal unsigned
116 | constant ALU_CMPGT : std_logic_vector(6 downto 0) := "1011100"; -- Compare: greater signed
117 | constant ALU_CMPGTU : std_logic_vector(6 downto 0) := "1011101"; -- Compare: greater unsigned
118 | constant ALU_CMPLE : std_logic_vector(6 downto 0) := "1011110"; -- Compare: less than equal signed
119 | constant ALU_CMPLEU : std_logic_vector(6 downto 0) := "1011111"; -- Compare: less than equal unsigned
120 | constant ALU_CMPLT : std_logic_vector(6 downto 0) := "1100000"; -- Compare: less than signed
121 | constant ALU_CMPLTU : std_logic_vector(6 downto 0) := "1100001"; -- Compare: less than unsigned
122 | constant ALU_CMPNE : std_logic_vector(6 downto 0) := "1100010"; -- Compare: not equal
123 | constant ALU_NANDL : std_logic_vector(6 downto 0) := "1100011"; -- Logical NAND
124 | constant ALU_NORL : std_logic_vector(6 downto 0) := "1100100"; -- Logical NOR
125 | constant ALU_ORL : std_logic_vector(6 downto 0) := "1100110"; -- Logical OR
126 | constant ALU_MTB : std_logic_vector(6 downto 0) := "1100111"; -- Move GR to BR
127 | constant ALU_ANDL : std_logic_vector(6 downto 0) := "1101000"; -- Logical AND
128 |
129 | -- ALU opcodes (BR usage, see doc/syllable_layout.txt)
130 | constant ALU_ADDCG : std_logic_vector(6 downto 0) := "1111---"; -- Add with carry and generate carry.
131 | constant ALU_DIVS : std_logic_vector(6 downto 0) := "1110---"; -- Division step with carry and generate carry
132 | constant ALU_SLCT : std_logic_vector(6 downto 0) := "0111---"; -- Select s1 on true condition. (exception: opcode starts with 0)
133 | constant ALU_SLCTF : std_logic_vector(6 downto 0) := "0110---"; -- Select s1 on false condition. (exception: opcode starts with 0)
134 |
135 | -- Multiplier opcodes
136 | constant MUL_MPYLL : std_logic_vector(6 downto 0) := "0000001"; -- Multiply signed low 16 x low 16 bits
137 | constant MUL_MPYLLU : std_logic_vector(6 downto 0) := "0000010"; -- Multiply unsigned low 16 x low 16 bits
138 | constant MUL_MPYLH : std_logic_vector(6 downto 0) := "0000011"; -- Multiply signed low 16 (s1) x high 16 (s2) bits
139 | constant MUL_MPYLHU : std_logic_vector(6 downto 0) := "0000100"; -- Multiply unsigned low 16 (s1) x high 16 (s2) bits
140 | constant MUL_MPYHH : std_logic_vector(6 downto 0) := "0000101"; -- Multiply signed high 16 x high 16 bits
141 | constant MUL_MPYHHU : std_logic_vector(6 downto 0) := "0000110"; -- Multiply unsigned high 16 x high 16 bits
142 | constant MUL_MPYL : std_logic_vector(6 downto 0) := "0000111"; -- Multiply signed low 16 (s2) x 32 (s1) bits
143 | constant MUL_MPYLU : std_logic_vector(6 downto 0) := "0001000"; -- Multiply unsigned low 16 (s2) x 32 (s1) bits
144 | constant MUL_MPYH : std_logic_vector(6 downto 0) := "0001001"; -- Multiply signed high 16 (s2) x 32 (s1) bits
145 | constant MUL_MPYHU : std_logic_vector(6 downto 0) := "0001010"; -- Multiply unsigned high 16 (s2) x 32 (s1) bits
146 | constant MUL_MPYHS : std_logic_vector(6 downto 0) := "0001011"; -- Multiply signed high 16 (s2) x 32 (s1) bits, shift left 16
147 |
148 | -- Control opcodes
149 | --
150 | -- NOTE: igoto and icall are overloaded by goto and call, as mentioned on the VEX forum at
151 | -- http://www.vliw.org/vex/viewtopic.php?t=52
152 | constant CTRL_GOTO : std_logic_vector(6 downto 0) := "0100001"; -- Unconditional relative jump
153 | constant CTRL_IGOTO : std_logic_vector(6 downto 0) := "0100010"; -- Unconditional absolute indirect jump to link register
154 | constant CTRL_CALL : std_logic_vector(6 downto 0) := "0100011"; -- Unconditional relative call
155 | constant CTRL_ICALL : std_logic_vector(6 downto 0) := "0100100"; -- Unconditional absolute indirect call to link register
156 | constant CTRL_BR : std_logic_vector(6 downto 0) := "0100101"; -- Conditional relative branch on true condition
157 | constant CTRL_BRF : std_logic_vector(6 downto 0) := "0100110"; -- Conditional relative branch on false condition
158 | constant CTRL_RETURN : std_logic_vector(6 downto 0) := "0100111"; -- Pop stack frame and goto link register
159 | constant CTRL_RFI : std_logic_vector(6 downto 0) := "0101000"; -- Return from interrupt
160 | constant CTRL_XNOP : std_logic_vector(6 downto 0) := "0101001"; -- Multicycle NOP
161 |
162 | -- Inter-cluster opcodes
163 | --
164 | -- NOTE: These opcodes aren't used in the current r-VEX implementation,
165 | -- because it has only one cluster. The opcode definitions are
166 | -- here for possible future use.
167 | --
168 | constant INTR_SEND : std_logic_vector(6 downto 0) := "0101010"; -- Send s1 to the path identified by im
169 | constant INTR_RECV : std_logic_vector(6 downto 0) := "0101011"; -- Assigns the value from the path identified by im to t
170 |
171 | -- Memory opcodes
172 | constant MEM_LDW : std_logic_vector(6 downto 0) := "0010001"; -- Load word
173 | constant MEM_LDH : std_logic_vector(6 downto 0) := "0010010"; -- Load halfword signed
174 | constant MEM_LDHU : std_logic_vector(6 downto 0) := "0010011"; -- Load halfword unsigned
175 | constant MEM_LDB : std_logic_vector(6 downto 0) := "0010100"; -- Load byte signed
176 | constant MEM_LDBU : std_logic_vector(6 downto 0) := "0010101"; -- Load byte unsigned
177 | constant MEM_STW : std_logic_vector(6 downto 0) := "0010110"; -- Store word
178 | constant MEM_STH : std_logic_vector(6 downto 0) := "0010111"; -- Store halfword
179 | constant MEM_STB : std_logic_vector(6 downto 0) := "0011000"; -- Store byte
180 | constant MEM_PFT : std_logic_vector(6 downto 0) := "0011001"; -- Prefetch
181 |
182 | -- Syllable is a follow-up to previous syllable with other part of long immediate
183 | constant SYL_FOLLOW : std_logic_vector(6 downto 0) := "0011100";
184 | end package rVEX_pkg;
185 |
186 | package body rVEX_pkg is
187 | end package body rVEX_pkg;
188 |
189 |
--------------------------------------------------------------------------------
/r-VEX/src/registers_br.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | BR Register file
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- registers_br.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_unsigned.all;
34 | use ieee.numeric_std.all;
35 |
36 | library work;
37 | use work.rVEX_pkg.all;
38 |
39 | entity registers_br is
40 | port ( clk : in std_logic;
41 | write_en_0 : in std_logic; -- syllable 0 write enable
42 | write_en_1 : in std_logic; -- syllable 1 write enable
43 | write_en_2 : in std_logic; -- syllable 2 write enable
44 | write_en_3 : in std_logic; -- syllable 3 write enable
45 | address_r_0 : in std_logic_vector(2 downto 0); -- syllable 0 address to be read from
46 | address_r_1 : in std_logic_vector(2 downto 0); -- syllable 1 address to be read from
47 | address_r_2 : in std_logic_vector(2 downto 0); -- syllable 2 address to be read from
48 | address_r_3 : in std_logic_vector(2 downto 0); -- syllable 3 address to be read from
49 | address_w_0 : in std_logic_vector(2 downto 0); -- syllable 0 address to be written to
50 | address_w_1 : in std_logic_vector(2 downto 0); -- syllable 1 address to be written to
51 | address_w_2 : in std_logic_vector(2 downto 0); -- syllable 2 address to be written to
52 | address_w_3 : in std_logic_vector(2 downto 0); -- syllable 3 address to be written to
53 | data_in_0 : in std_logic; -- syllable 0 input data
54 | data_in_1 : in std_logic; -- syllable 1 input data
55 | data_in_2 : in std_logic; -- syllable 2 input data
56 | data_in_3 : in std_logic; -- syllable 3 input data
57 |
58 | data_out_0 : out std_logic; -- syllable 0 output data
59 | data_out_1 : out std_logic; -- syllable 1 output data
60 | data_out_2 : out std_logic; -- syllable 2 output data
61 | data_out_3 : out std_logic); -- syllable 3 output data
62 | end entity registers_br;
63 |
64 |
65 | architecture behavioural of registers_br is
66 | type regs_t is array (0 to (BR_DEPTH - 1)) of std_logic;
67 | signal registers : regs_t := (others => '0');
68 | begin
69 | reg_handler : process(clk)
70 | begin
71 | if (clk = '1' and clk'event) then
72 | if (write_en_0 = '1') then
73 | registers(conv_integer(address_w_0)) <= data_in_0;
74 | end if;
75 |
76 | if (write_en_1 = '1') then
77 | registers(conv_integer(address_w_1)) <= data_in_1;
78 | end if;
79 |
80 | if (write_en_2 = '1') then
81 | registers(conv_integer(address_w_2)) <= data_in_2;
82 | end if;
83 |
84 | if (write_en_3 = '1') then
85 | registers(conv_integer(address_w_3)) <= data_in_3;
86 | end if;
87 |
88 | data_out_0 <= registers(conv_integer(address_r_0));
89 | data_out_1 <= registers(conv_integer(address_r_1));
90 | data_out_2 <= registers(conv_integer(address_r_2));
91 | data_out_3 <= registers(conv_integer(address_r_3));
92 | end if;
93 | end process reg_handler;
94 | end architecture behavioural;
95 |
96 |
--------------------------------------------------------------------------------
/r-VEX/src/registers_gr.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | GR Register file
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- registers_gr.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_unsigned.all;
34 | use ieee.numeric_std.all;
35 |
36 | library work;
37 | use work.rVEX_pkg.all;
38 |
39 | entity registers_gr is
40 | port ( clk : in std_logic;
41 | write_en_0 : in std_logic; -- syllable 0 write enable
42 | write_en_1 : in std_logic; -- syllable 1 write enable
43 | write_en_2 : in std_logic; -- syllable 2 write enable
44 | write_en_3 : in std_logic; -- syllable 3 write enable
45 | address_r1_0 : in std_logic_vector(5 downto 0); -- syllable 0 address 1 to be read from
46 | address_r2_0 : in std_logic_vector(5 downto 0); -- syllable 0 address 2 to be read from
47 | address_r1_1 : in std_logic_vector(5 downto 0); -- syllable 1 address 1 to be read from
48 | address_r2_1 : in std_logic_vector(5 downto 0); -- syllable 1 address 2 to be read from
49 | address_r1_2 : in std_logic_vector(5 downto 0); -- syllable 2 address 1 to be read from
50 | address_r2_2 : in std_logic_vector(5 downto 0); -- syllable 2 address 2 to be read from
51 | address_r1_3 : in std_logic_vector(5 downto 0); -- syllable 3 address 1 to be read from
52 | address_r2_3 : in std_logic_vector(5 downto 0); -- syllable 3 address 2 to be read from
53 | address_w_0 : in std_logic_vector(5 downto 0); -- syllable 0 address to be written to
54 | address_w_1 : in std_logic_vector(5 downto 0); -- syllable 1 address to be written to
55 | address_w_2 : in std_logic_vector(5 downto 0); -- syllable 2 address to be written to
56 | address_w_3 : in std_logic_vector(5 downto 0); -- syllable 3 address to be written to
57 | data_in_0 : in std_logic_vector(31 downto 0); -- syllable 0 input data
58 | data_in_1 : in std_logic_vector(31 downto 0); -- syllable 1 input data
59 | data_in_2 : in std_logic_vector(31 downto 0); -- syllable 2 input data
60 | data_in_3 : in std_logic_vector(31 downto 0); -- syllable 3 input data
61 |
62 | data_out1_0 : out std_logic_vector(31 downto 0); -- syllable 0 output data 1
63 | data_out1_1 : out std_logic_vector(31 downto 0); -- syllable 1 output data 1
64 | data_out1_2 : out std_logic_vector(31 downto 0); -- syllable 2 output data 1
65 | data_out1_3 : out std_logic_vector(31 downto 0); -- syllable 3 output data 1
66 | data_out2_0 : out std_logic_vector(31 downto 0); -- syllable 0 output data 2
67 | data_out2_1 : out std_logic_vector(31 downto 0); -- syllable 1 output data 2
68 | data_out2_2 : out std_logic_vector(31 downto 0); -- syllable 2 output data 2
69 | data_out2_3 : out std_logic_vector(31 downto 0)); -- syllable 3 output data 2
70 | end entity registers_gr;
71 |
72 |
73 | architecture behavioural of registers_gr is
74 | type regs_t is array (0 to (GR_DEPTH - 1)) of std_logic_vector(31 downto 0);
75 | signal registers : regs_t := (others => x"00000000");
76 | begin
77 | reg_handler : process(clk)
78 | begin
79 | if (clk = '1' and clk'event) then
80 | if (write_en_0 = '1' and not(address_w_0 = "000000")) then
81 | registers(conv_integer(address_w_0)) <= data_in_0;
82 | end if;
83 |
84 | if (write_en_1 = '1' and not(address_w_1 = "000000")) then
85 | registers(conv_integer(address_w_1)) <= data_in_1;
86 | end if;
87 |
88 | if (write_en_2 = '1' and not(address_w_2 = "000000")) then
89 | registers(conv_integer(address_w_2)) <= data_in_2;
90 | end if;
91 |
92 | if (write_en_3 = '1' and not(address_w_3 = "000000")) then
93 | registers(conv_integer(address_w_3)) <= data_in_3;
94 | end if;
95 |
96 | data_out1_0 <= registers(conv_integer(address_r1_0));
97 | data_out2_0 <= registers(conv_integer(address_r2_0));
98 | data_out1_1 <= registers(conv_integer(address_r1_1));
99 | data_out2_1 <= registers(conv_integer(address_r2_1));
100 | data_out1_2 <= registers(conv_integer(address_r1_2));
101 | data_out2_2 <= registers(conv_integer(address_r2_2));
102 | data_out1_3 <= registers(conv_integer(address_r1_3));
103 | data_out2_3 <= registers(conv_integer(address_r2_3));
104 | end if;
105 | end process reg_handler;
106 | end architecture behavioural;
107 |
108 |
--------------------------------------------------------------------------------
/r-VEX/src/system.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- r-VEX | Stand-alone system
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- system.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_unsigned.all;
34 | use ieee.numeric_std.all;
35 |
36 | library work;
37 | use work.rVEX_pkg.all;
38 |
39 | entity system is
40 | port ( clk : in std_logic; -- system clock
41 | reset : in std_logic; -- system reset
42 |
43 | tx : out std_logic); -- tx signal for UART
44 | end entity system;
45 |
46 |
47 | architecture behavioural of system is
48 | -- r-VEX processor core
49 | component rVEX is
50 | port ( clk : in std_logic;
51 | reset : in std_logic;
52 | instr : in std_logic_vector(127 downto 0);
53 | data_in : in std_logic_vector((DMEM_WIDTH - 1) downto 0);
54 | run : in std_logic;
55 |
56 | done : out std_logic;
57 | cycles : out std_logic_vector(31 downto 0);
58 | address_i : out std_logic_vector(7 downto 0);
59 | address_dr : out std_logic_vector((DMEM_LOGDEP - 1) downto 0);
60 | address_dw : out std_logic_vector((DMEM_LOGDEP - 1) downto 0);
61 | write_en_d : out std_logic;
62 | data_out : out std_logic_vector((DMEM_WIDTH - 1) downto 0));
63 | end component rVEX;
64 |
65 | -- Instruction memory
66 | component i_mem is
67 | port ( reset : in std_logic;
68 | address : in std_logic_vector(7 downto 0);
69 |
70 | instr : out std_logic_vector(127 downto 0));
71 | end component i_mem;
72 |
73 | -- Data memory
74 | component d_mem is
75 | port ( clk : in std_logic;
76 | write_en : in std_logic;
77 | address_r1 : in std_logic_vector((DMEM_LOGDEP - 1) downto 0);
78 | address_r2 : in std_logic_vector((DMEM_LOGDEP - 1) downto 0);
79 | address_w : in std_logic_vector((DMEM_LOGDEP - 1) downto 0);
80 | data_in : in std_logic_vector((DMEM_WIDTH - 1) downto 0);
81 |
82 | data_out1 : out std_logic_vector((DMEM_WIDTH - 1) downto 0);
83 | data_out2 : out std_logic_vector((DMEM_WIDTH - 1) downto 0));
84 | end component d_mem;
85 |
86 | -- Debug UART
87 | component uart is
88 | port ( clk : in std_logic;
89 | reset : in std_logic;
90 | ready : in std_logic;
91 | cycles : in std_logic_vector(31 downto 0);
92 | data_in : in std_logic_vector(31 downto 0);
93 |
94 | address : out std_logic_vector(7 downto 0);
95 | tx : out std_logic);
96 | end component uart;
97 |
98 | -- clock divider to generate clock of 0.5 * clk frequency
99 | -- to meet timing constraints
100 | component clk_div is
101 | port ( clk : in std_logic;
102 | clk_out : out std_logic);
103 | end component clk_div;
104 |
105 | signal clk_half : std_logic := '0';
106 | signal clk_uart_s : std_logic := '0';
107 | signal run_s : std_logic := '0';
108 | signal reset_s : std_logic := '0';
109 | signal address_i_s : std_logic_vector(7 downto 0) := (others => '0');
110 | signal address_dr_s : std_logic_vector((DMEM_LOGDEP - 1) downto 0) := (others => '0');
111 | signal address_dw_s : std_logic_vector((DMEM_LOGDEP - 1) downto 0) := (others => '0');
112 | signal write_en_d_s : std_logic := '0';
113 | signal m2rvex_data_s : std_logic_vector((DMEM_WIDTH - 1) downto 0) := (others => '0');
114 | signal rvex2m_data_s : std_logic_vector((DMEM_WIDTH - 1) downto 0) := (others => '0');
115 | signal instr_s : std_logic_vector(127 downto 0) := (others => '0');
116 | signal done_s : std_logic := '0';
117 | signal cycles_s : std_logic_vector(31 downto 0) := (others => '0');
118 | signal address_uart_s : std_logic_vector((DMEM_LOGDEP - 1) downto 0) := (others => '0');
119 | signal data_uart_s : std_logic_vector(31 downto 0);
120 | signal start_counter_s : std_logic_vector(1 downto 0) := (others => '0');
121 | begin
122 | clk05 : clk_div port map (clk => clk,
123 | clk_out => clk_half);
124 |
125 | rVEX0 : rVEX port map (clk => clk_half,
126 | reset => reset_s,
127 | instr => instr_s,
128 | data_in => m2rvex_data_s,
129 | run => run_s,
130 |
131 | done => done_s,
132 | cycles => cycles_s,
133 | address_i => address_i_s,
134 | address_dr => address_dr_s,
135 | address_dw => address_dw_s,
136 | write_en_d => write_en_d_s,
137 | data_out => rvex2m_data_s);
138 |
139 | i_mem0 : i_mem port map (reset => reset_s,
140 | address => address_i_s,
141 |
142 | instr => instr_s);
143 |
144 | d_mem0 : d_mem port map (clk => clk_half,
145 | write_en => write_en_d_s,
146 | address_r1 => address_dr_s,
147 | address_r2 => address_uart_s,
148 | address_w => address_dw_s,
149 | data_in => rvex2m_data_s,
150 |
151 | data_out1 => m2rvex_data_s,
152 | data_out2 => data_uart_s);
153 |
154 | uart0 : uart port map (clk => clk_uart_s,
155 | reset => reset_s,
156 | ready => done_s,
157 | cycles => cycles_s,
158 | data_in => data_uart_s,
159 |
160 | address => address_uart_s,
161 | tx => tx);
162 |
163 |
164 | update_counter : process (clk, reset_s)
165 | begin
166 | if (reset_s = '1') then
167 | start_counter_s <= (others => '0');
168 | elsif (clk = '1' and clk'event) then
169 | start_counter_s <= start_counter_s + 1;
170 | end if;
171 | end process update_counter;
172 |
173 | igniter : process (clk, reset_s)
174 | begin
175 | if (reset_s = '1') then
176 | run_s <= '0';
177 | elsif (clk = '1' and clk'event) then
178 | if (start_counter_s > "10") then
179 | run_s <= '1';
180 | end if;
181 | end if;
182 | end process igniter;
183 |
184 | -- buttons on Virtex-II Pro board are active high, on Spartan-3E board active low
185 | reset_s <= reset xor ACTIVE_LOW;
186 |
187 | -- clk is 100 MHz on Virtex-II Pro board, 50 MHz on Spartan-3E board.
188 | -- UART needs a 50 MHz clock, so clk_half is fed on Virtex-II Pro board,
189 | -- whilst clk is fed on Spartan-3E board.
190 | clk_uart_s <= clk_half when (ACTIVE_LOW = '1') else clk;
191 | end architecture behavioural;
192 |
193 |
--------------------------------------------------------------------------------
/r-VEX/src/uart/clk_18432.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- UART | 1.8432 MHz Clock Generator
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- Input: clk | System clock
29 | -- reset | System reset
30 | --
31 | -- Output: clk_18432 | 1.8432 MHz clock
32 | --------------------------------------------------------------------------------
33 | -- Generates a 1.8432 MHz clock signal from a 50 MHz input
34 | -- clock signal. From this signal, 115200 bps baud ticks
35 | -- can be easily generated (divide by 16)
36 | --
37 | -- 50 MHz * 1152/15625 = 3.6864 MHz (high/low switching
38 | -- frequency)
39 | --------------------------------------------------------------------------------
40 | -- clk_18432.vhd
41 | --------------------------------------------------------------------------------
42 |
43 | library ieee;
44 | use ieee.std_logic_1164.all;
45 | use ieee.std_logic_unsigned.all;
46 | use ieee.numeric_std.all;
47 |
48 | entity clk_18432 is
49 | port ( clk : in std_logic;
50 | reset : in std_logic;
51 |
52 | clk_18432 : out std_logic );
53 | end clk_18432;
54 |
55 | architecture behavioural of clk_18432 is
56 | constant NUMERATOR : std_logic_vector(14 downto 0) := "000010010000000"; -- 1152;
57 | constant DENOMINATOR : std_logic_vector(14 downto 0) := "011110100001001"; -- 15625;
58 |
59 | signal clk_out : std_logic := '0';
60 | signal counter : std_logic_vector(14 downto 0) := (others => '0');
61 | begin
62 |
63 | clk_18432 <= clk_out;
64 |
65 | process (clk, reset)
66 | begin
67 | if (reset = '1') then
68 | clk_out <= '1';
69 | counter <= DENOMINATOR - NUMERATOR - 1;
70 | elsif (clk = '1' and clk'event) then
71 | if counter(14) = '1' then
72 | clk_out <= not clk_out;
73 | counter <= counter + DENOMINATOR - NUMERATOR;
74 | else
75 | counter <= counter - NUMERATOR;
76 | end if;
77 | end if;
78 | end process;
79 |
80 | end architecture behavioural;
81 |
82 |
--------------------------------------------------------------------------------
/r-VEX/src/uart/uart.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- UART | Transmitter
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- Input: clk | System clock
29 | -- reset | System reset
30 | -- ready | r-VEX is done
31 | -- cycles | Number of cycles execution took
32 | -- data_in | Data to be transmitted from memory
33 | --
34 | -- Output: address | Address to read from data memory
35 | -- tx | TX signal
36 | --------------------------------------------------------------------------------
37 | -- uart.vhd
38 | --------------------------------------------------------------------------------
39 |
40 | library ieee;
41 | use ieee.std_logic_1164.all;
42 | use ieee.std_logic_unsigned.all;
43 | use ieee.numeric_std.all;
44 |
45 | library work;
46 | use work.uart_pkg.all;
47 |
48 | entity uart is
49 | port ( clk : in std_logic;
50 | reset : in std_logic;
51 | ready : in std_logic;
52 | cycles : in std_logic_vector(31 downto 0);
53 | data_in : in std_logic_vector(31 downto 0);
54 |
55 | address : out std_logic_vector(7 downto 0);
56 | tx : out std_logic);
57 | end entity uart;
58 |
59 | architecture behavioural of uart is
60 | component clk_18432 is
61 | port ( clk : in std_logic;
62 | reset : in std_logic;
63 |
64 | clk_18432 : out std_logic);
65 | end component clk_18432;
66 |
67 | component uart_tx is
68 | port ( clk : in std_logic;
69 | reset : in std_logic;
70 | data_in : in std_logic_vector(7 downto 0);
71 | in_valid : in std_logic;
72 |
73 | tx : out std_logic;
74 | accept_in : out std_logic);
75 | end component uart_tx;
76 |
77 | signal clk_18432_s : std_logic := '0';
78 | signal data_s : std_logic_vector(7 downto 0) := x"00";
79 | signal in_valid_s : std_logic := '0';
80 | signal accept_s : std_logic := '0';
81 | signal counter_s : std_logic_vector(8 downto 0) := (others => '0');
82 | signal ready_s : std_logic := '0';
83 | signal in_valid_welcome_s : std_logic := '0';
84 | signal in_valid_data_s : std_logic := '0';
85 | signal counter_welcome_s : std_logic_vector(7 downto 0) := (others => '0');
86 | signal switch_s : std_logic := '1';
87 | signal cnt_s : std_logic_vector(7 downto 0) := x"00";
88 | signal hex8_s : std_logic_vector(7 downto 0) := x"00";
89 | signal hex7_s : std_logic_vector(7 downto 0) := x"00";
90 | signal hex6_s : std_logic_vector(7 downto 0) := x"00";
91 | signal hex5_s : std_logic_vector(7 downto 0) := x"00";
92 | signal hex4_s : std_logic_vector(7 downto 0) := x"00";
93 | signal hex3_s : std_logic_vector(7 downto 0) := x"00";
94 | signal hex2_s : std_logic_vector(7 downto 0) := x"00";
95 | signal hex1_s : std_logic_vector(7 downto 0) := x"00";
96 |
97 | -- Xilinx specific clock buffer attributes
98 | attribute buffer_type : string;
99 | attribute buffer_type of clk_18432_s : signal is "BUFG";
100 | attribute buffer_type of accept_s : signal is "BUFG";
101 | begin
102 | clk_gen : clk_18432 port map ( clk => clk,
103 | reset => reset,
104 |
105 | clk_18432 => clk_18432_s);
106 |
107 | tx_0 : uart_tx port map ( clk => clk_18432_s,
108 | reset => reset,
109 | data_in => data_s,
110 | in_valid => in_valid_s,
111 |
112 | tx => tx,
113 | accept_in => accept_s);
114 |
115 | update_welcome_counter : process (accept_s, ready)
116 | begin
117 | if (ready = '0') then
118 | counter_welcome_s <= (others => '0');
119 | elsif (accept_s = '1' and accept_s'event) then
120 | counter_welcome_s <= counter_welcome_s + 1;
121 | end if;
122 | end process update_welcome_counter;
123 |
124 | update_counter : process (accept_s, ready_s)
125 | begin
126 | if (ready_s = '0') then
127 | counter_s <= (others => '0');
128 | elsif (accept_s = '1' and accept_s'event) then
129 | counter_s <= counter_s + 1;
130 | end if;
131 | end process update_counter;
132 |
133 | update_dmem : process(clk, reset)
134 | begin
135 | if (reset = '1') then
136 | address <= (others => '0');
137 | elsif (clk = '1' and clk'event) then
138 | address <= "0000" & counter_s(8 downto 5);
139 | end if;
140 | end process update_dmem;
141 |
142 | input_adapt : process(clk, reset)
143 | begin
144 | if (reset = '1') then
145 | cnt_s <= x"00";
146 | hex1_s <= x"00";
147 | hex2_s <= x"00";
148 | hex3_s <= x"00";
149 | hex4_s <= x"00";
150 | hex5_s <= x"00";
151 | hex6_s <= x"00";
152 | hex7_s <= x"00";
153 | hex8_s <= x"00";
154 | elsif (clk = '1' and clk'event) then
155 | cnt_s <= to_hex_ascii(counter_s(8 downto 5));
156 | hex8_s <= to_hex_ascii(data_in(31 downto 28));
157 | hex7_s <= to_hex_ascii(data_in(27 downto 24));
158 | hex6_s <= to_hex_ascii(data_in(23 downto 20));
159 | hex5_s <= to_hex_ascii(data_in(19 downto 16));
160 | hex4_s <= to_hex_ascii(data_in(15 downto 12));
161 | hex3_s <= to_hex_ascii(data_in(11 downto 8));
162 | hex2_s <= to_hex_ascii(data_in(7 downto 4));
163 | hex1_s <= to_hex_ascii(data_in(3 downto 0));
164 | end if;
165 | end process input_adapt;
166 |
167 | update_data : process (clk, reset)
168 | begin
169 | if (reset = '1') then
170 | data_s <= (others => '0');
171 | elsif (clk = '1' and clk'event) then
172 | if (ready_s = '0') then
173 | data_s <= init_message(counter_welcome_s, cycles);
174 | else
175 | case counter_s(4 downto 0) is
176 | when "00000" =>
177 | data_s <= "00001101"; -- CR Carriage Return
178 | when "00001" =>
179 | data_s <= "00001010"; -- LF Line Feed
180 | when "00010" =>
181 | data_s <= "00110000"; -- 0
182 | when "00011" =>
183 | data_s <= "01111000"; -- x
184 | when "00100" =>
185 | data_s <= "00110000"; -- 0
186 | when "00101" =>
187 | data_s <= cnt_s; -- Hexadecimal address value
188 | when "00110" =>
189 | data_s <= "00100000"; -- SP Space
190 | when "00111" =>
191 | data_s <= "01111100"; -- |
192 | when "01000" =>
193 | data_s <= "00100000"; -- SP Space
194 | when "01001" =>
195 | data_s <= "00110000"; -- 0
196 | when "01010" =>
197 | data_s <= "01111000"; -- x
198 | when "01011" =>
199 | data_s <= hex8_s; -- Most significant hex digit of value
200 | when "01100" =>
201 | data_s <= hex7_s;
202 | when "01101" =>
203 | data_s <= hex6_s;
204 | when "01110" =>
205 | data_s <= hex5_s;
206 | when "01111" =>
207 | data_s <= hex4_s;
208 | when "10000" =>
209 | data_s <= hex3_s;
210 | when "10001" =>
211 | data_s <= hex2_s;
212 | when "10010" =>
213 | data_s <= hex1_s; -- Least siginificant hex digit of value
214 | when others =>
215 | data_s <= "00000000"; -- null
216 | end case;
217 | end if;
218 | end if;
219 | end process update_data;
220 |
221 | update_ready : process (clk, reset)
222 | begin
223 | if (reset = '1') then
224 | ready_s <= '0';
225 | elsif (clk = '1' and clk'event) then
226 | if (counter_welcome_s > x"5E") then
227 | ready_s <= '1';
228 | end if;
229 | end if;
230 | end process update_ready;
231 |
232 | welcome_message : process (clk, ready)
233 | begin
234 | if (ready = '0') then
235 | in_valid_welcome_s <= '0';
236 | elsif (clk = '1' and clk'event) then
237 | if (counter_welcome_s < "11111111") then
238 | in_valid_welcome_s <= '1';
239 | else
240 | in_valid_welcome_s <= '0';
241 | end if;
242 | end if;
243 | end process welcome_message;
244 |
245 | send_data : process (clk, ready_s)
246 | begin
247 | if (ready_s = '0') then
248 | in_valid_data_s <= '0';
249 | elsif (clk = '1' and clk'event) then
250 | if (counter_s < "111111111") then
251 | in_valid_data_s <= '1';
252 | else
253 | in_valid_data_s <= '0';
254 | end if;
255 | end if;
256 | end process send_data;
257 |
258 | uart_switch : process (clk, reset)
259 | begin
260 | if (reset = '1') then
261 | switch_s <= '1';
262 | elsif (clk = '1' and clk'event) then
263 | if (counter_s > "111110011" ) then
264 | switch_s <= '0';
265 | end if;
266 | end if;
267 | end process uart_switch;
268 |
269 | in_valid_s <= (in_valid_welcome_s or in_valid_data_s) and switch_s;
270 | end architecture behavioural;
271 |
272 |
--------------------------------------------------------------------------------
/r-VEX/src/uart/uart_pkg.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- UART | Package
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- uart_pkg.vhd
29 | --------------------------------------------------------------------------------
30 |
31 | library ieee;
32 | use ieee.std_logic_1164.all;
33 | use ieee.std_logic_unsigned.all;
34 | use ieee.numeric_std.all;
35 |
36 | package uart_pkg is
37 | function init_message(index : std_logic_vector(7 downto 0);
38 | cycles : std_logic_vector(31 downto 0)) return std_logic_vector;
39 |
40 | function to_hex_ascii(hex : std_logic_vector(3 downto 0)) return std_logic_vector;
41 | end package;
42 |
43 |
44 | package body uart_pkg is
45 | function init_message(index : std_logic_vector(7 downto 0);
46 | cycles : std_logic_vector(31 downto 0)) return std_logic_vector is
47 | begin
48 | case index is
49 | when x"00" =>
50 | return "00001101"; -- CR Carriage Return
51 | when x"01" =>
52 | return "00001010"; -- LF Line Feed
53 | when x"03" =>
54 | return "00001101"; -- CR Carriage Return
55 | when x"04" =>
56 | return "00001010"; -- LF Line Feed
57 | when x"05" =>
58 | return "01110010"; -- r
59 | when x"06" =>
60 | return "00101101"; -- -
61 | when x"07" =>
62 | return "01010110"; -- V
63 | when x"08" =>
64 | return "01000101"; -- E
65 | when x"09" =>
66 | return "01011000"; -- X
67 | when x"0A" =>
68 | return "00001101"; -- CR Carriage Return
69 | when x"0B" =>
70 | return "00001010"; -- LF Line Feed
71 | when x"0C" =>
72 | return "00101101"; -- -
73 | when x"0D" =>
74 | return "00101101"; -- -
75 | when x"0E" =>
76 | return "00101101"; -- -
77 | when x"0F" =>
78 | return "00101101"; -- -
79 | when x"10" =>
80 | return "00101101"; -- -
81 | when x"11" =>
82 | return "00001101"; -- CR Carriage Return
83 | when x"12" =>
84 | return "00001010"; -- LF Line Feed
85 | when x"13" =>
86 | return "01000011"; -- C
87 | when x"14" =>
88 | return "01111001"; -- y
89 | when x"15" =>
90 | return "01100011"; -- c
91 | when x"16" =>
92 | return "01101100"; -- l
93 | when x"17" =>
94 | return "01100101"; -- e
95 | when x"18" =>
96 | return "01110011"; -- s
97 | when x"19" =>
98 | return "00111010"; -- :
99 | when x"1A" =>
100 | return "00100000"; -- SP Space
101 | when x"1B" =>
102 | return "00110000"; -- 0
103 | when x"1C" =>
104 | return "01111000"; -- x
105 | when x"1D" =>
106 | return to_hex_ascii(cycles(31 downto 28));
107 | when x"1E" =>
108 | return to_hex_ascii(cycles(27 downto 24));
109 | when x"1F" =>
110 | return to_hex_ascii(cycles(23 downto 20));
111 | when x"20" =>
112 | return to_hex_ascii(cycles(19 downto 16));
113 | when x"21" =>
114 | return to_hex_ascii(cycles(15 downto 12));
115 | when x"22" =>
116 | return to_hex_ascii(cycles(11 downto 8));
117 | when x"23" =>
118 | return to_hex_ascii(cycles(7 downto 4));
119 | when x"24" =>
120 | return to_hex_ascii(cycles(3 downto 0));
121 | when x"25" =>
122 | return "00001101"; -- CR Carriage Return
123 | when x"26" =>
124 | return "00001010"; -- LF Line Feed
125 | when x"27" =>
126 | return "00001101"; -- CR Carriage Return
127 | when x"28" =>
128 | return "00001010"; -- LF Line Feed
129 | when x"29" =>
130 | return "01000100"; -- D
131 | when x"2A" =>
132 | return "01100001"; -- a
133 | when x"2B" =>
134 | return "01110100"; -- t
135 | when x"2C" =>
136 | return "01100001"; -- a
137 | when x"2D" =>
138 | return "00100000"; -- SP Space
139 | when x"2E" =>
140 | return "01101101"; -- m
141 | when x"2F" =>
142 | return "01100101"; -- e
143 | when x"30" =>
144 | return "01101101"; -- m
145 | when x"31" =>
146 | return "01101111"; -- o
147 | when x"32" =>
148 | return "01110010"; -- r
149 | when x"33" =>
150 | return "01111001"; -- y
151 | when x"34" =>
152 | return "00100000"; -- SP Space
153 | when x"35" =>
154 | return "01100100"; -- d
155 | when x"36" =>
156 | return "01110101"; -- u
157 | when x"37" =>
158 | return "01101101"; -- m
159 | when x"38" =>
160 | return "01110000"; -- p
161 | when x"39" =>
162 | return "00001101"; -- CR Carriage Return
163 | when x"3A" =>
164 | return "00001010"; -- LF Line Feed
165 | when x"3B" =>
166 | return "00001101"; -- CR Carriage Return
167 | when x"3C" =>
168 | return "00001010"; -- LF Line Feed
169 | when x"3D" =>
170 | return "01100001"; -- a
171 | when x"3E" =>
172 | return "01100100"; -- d
173 | when x"3F" =>
174 | return "01100100"; -- d
175 | when x"40" =>
176 | return "01110010"; -- r
177 | when x"41" =>
178 | return "00100000"; -- SP Space
179 | when x"42" =>
180 | return "01111100"; -- |
181 | when x"43" =>
182 | return "00100000"; -- SP Space
183 | when x"44" =>
184 | return "01100011"; -- c
185 | when x"45" =>
186 | return "01101111"; -- o
187 | when x"46" =>
188 | return "01101110"; -- n
189 | when x"47" =>
190 | return "01110100"; -- t
191 | when x"48" =>
192 | return "01100101"; -- e
193 | when x"49" =>
194 | return "01101110"; -- n
195 | when x"4A" =>
196 | return "01110100"; -- t
197 | when x"4B" =>
198 | return "01110011"; -- s
199 | when x"4C" =>
200 | return "00001101"; -- CR Carriage Return
201 | when x"4D" =>
202 | return "00001010"; -- LF Line Feed
203 | when x"4E" =>
204 | return "00101101"; -- -
205 | when x"4F" =>
206 | return "00101101"; -- -
207 | when x"50" =>
208 | return "00101101"; -- -
209 | when x"51" =>
210 | return "00101101"; -- -
211 | when x"52" =>
212 | return "00101101"; -- -
213 | when x"53" =>
214 | return "00101011"; -- +
215 | when x"54" =>
216 | return "00101101"; -- -
217 | when x"55" =>
218 | return "00101101"; -- -
219 | when x"56" =>
220 | return "00101101"; -- -
221 | when x"57" =>
222 | return "00101101"; -- -
223 | when x"58" =>
224 | return "00101101"; -- -
225 | when x"59" =>
226 | return "00101101"; -- -
227 | when x"5A" =>
228 | return "00101101"; -- -
229 | when x"5B" =>
230 | return "00101101"; -- -
231 | when x"5C" =>
232 | return "00101101"; -- -
233 | when x"5D" =>
234 | return "00101101"; -- -
235 | when x"5E" =>
236 | return "00101101"; -- -
237 | when others =>
238 | return "00000000"; -- null
239 | end case;
240 | end function init_message;
241 |
242 | function to_hex_ascii(hex : std_logic_vector(3 downto 0)) return std_logic_vector is
243 | begin
244 | case hex is
245 | when x"0" =>
246 | return "00110000";
247 | when x"1" =>
248 | return "00110001";
249 | when x"2" =>
250 | return "00110010";
251 | when x"3" =>
252 | return "00110011";
253 | when x"4" =>
254 | return "00110100";
255 | when x"5" =>
256 | return "00110101";
257 | when x"6" =>
258 | return "00110110";
259 | when x"7" =>
260 | return "00110111";
261 | when x"8" =>
262 | return "00111000";
263 | when x"9" =>
264 | return "00111001";
265 | when x"A" =>
266 | return "01000001";
267 | when x"B" =>
268 | return "01000010";
269 | when x"C" =>
270 | return "01000011";
271 | when x"D" =>
272 | return "01000100";
273 | when x"E" =>
274 | return "01000101";
275 | when x"F" =>
276 | return "01000110";
277 | when others =>
278 | return "00000000";
279 | end case;
280 | end function to_hex_ascii;
281 | end package body uart_pkg;
282 |
283 |
--------------------------------------------------------------------------------
/r-VEX/src/uart/uart_tx.vhd:
--------------------------------------------------------------------------------
1 | --------------------------------------------------------------------------------
2 | -- UART | Transmitter unit
3 | --------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Faculty of Electrical Engineering, Mathematics and Computer Science
9 | -- Delft University of Technology
10 | -- Delft, The Netherlands
11 | --
12 | -- http://r-vex.googlecode.com
13 | --
14 | -- r-VEX is free hardware: you can redistribute it and/or modify
15 | -- it under the terms of the GNU General Public License as published by
16 | -- the Free Software Foundation, either version 3 of the License, or
17 | -- (at your option) any later version.
18 | --
19 | -- This program is distributed in the hope that it will be useful,
20 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
21 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 | -- GNU General Public License for more details.
23 | --
24 | -- You should have received a copy of the GNU General Public License
25 | -- along with this program. If not, see .
26 | --
27 | --------------------------------------------------------------------------------
28 | -- Input: clk | System clock at 1.8432 MHz
29 | -- reset | System reset
30 | -- data_in | Input data
31 | -- in_valid | Input data valid
32 | --
33 | -- Output: tx | TX line
34 | -- accept_in | '1' when transmitter accepts
35 | --------------------------------------------------------------------------------
36 | -- uart_tx.vhd
37 | --------------------------------------------------------------------------------
38 |
39 | library ieee;
40 | use ieee.std_logic_1164.all;
41 | use ieee.std_logic_unsigned.all;
42 | use ieee.numeric_std.all;
43 |
44 | entity uart_tx is
45 | port ( clk : in std_logic;
46 | reset : in std_logic;
47 | data_in : in std_logic_vector(7 downto 0);
48 | in_valid : in std_logic;
49 |
50 | tx : out std_logic;
51 | accept_in : out std_logic);
52 | end entity uart_tx;
53 |
54 |
55 | architecture behavioural of uart_tx is
56 | type tx_state is (reset_state, idle, start_bit, send_data, stop_bit);
57 | signal current_state, next_state : tx_state;
58 | signal data_counter : std_logic_vector(2 downto 0) := (others => '0');
59 | signal ticker : std_logic_vector(3 downto 0) := (others => '0');
60 | begin
61 | -- Updates the states in the statemachine at a 115200 bps rate
62 | clkgen_115k2 : process(clk, reset)
63 | begin
64 | if (reset = '1') then
65 | ticker <= (others => '0');
66 | current_state <= reset_state;
67 | data_counter <= "000";
68 | elsif (clk = '1' and clk'event) then
69 | if (ticker = 15 or (current_state = idle and next_state = idle)) then
70 | ticker <= (others => '0');
71 | current_state <= next_state;
72 | if (current_state = send_data) then
73 | data_counter <= data_counter + 1;
74 | else
75 | data_counter <= "000";
76 | end if;
77 | else
78 | current_state <= current_state;
79 | ticker <= ticker + 1;
80 | end if;
81 | end if;
82 | end process clkgen_115k2;
83 |
84 | tx_control : process (current_state, in_valid, data_counter)
85 | begin
86 | case current_state is
87 | when reset_state =>
88 | accept_in <= '0';
89 | tx <= '1';
90 |
91 | next_state <= idle;
92 | when idle =>
93 | accept_in <= '1';
94 | tx <= '1';
95 |
96 | if (in_valid = '1') then
97 | next_state <= start_bit;
98 | else
99 | next_state <= idle;
100 | end if;
101 | when start_bit =>
102 | accept_in <= '0';
103 | tx <= '0';
104 |
105 | next_state <= send_data;
106 | when send_data =>
107 | accept_in <= '0';
108 | tx <= data_in(conv_integer(data_counter));
109 |
110 | if (data_counter = 7) then
111 | next_state <= stop_bit;
112 | else
113 | next_state <= send_data;
114 | end if;
115 | when stop_bit =>
116 | accept_in <= '0';
117 | tx <= '1';
118 |
119 | next_state <= idle;
120 | when others =>
121 | accept_in <= '0';
122 | tx <= '1';
123 |
124 | next_state <= reset_state;
125 | end case;
126 | end process tx_control;
127 | end architecture behavioural;
128 |
--------------------------------------------------------------------------------
/r-VEX/testbenches/old/tb_alu.vhd:
--------------------------------------------------------------------------------
1 | -----------------------------------------------------------
2 | -- rho-VEX | Testbench ALU
3 | -----------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -----------------------------------------------------------
8 | -- testbenches/tb_alu.vhd
9 | -----------------------------------------------------------
10 |
11 | library ieee;
12 | use ieee.std_logic_1164.all;
13 | use ieee.std_logic_signed.all;
14 | use ieee.numeric_std.all;
15 |
16 | library work;
17 | use work.opcodes.all;
18 |
19 | entity tb_alu is
20 | end tb_alu;
21 |
22 | architecture test of tb_alu is
23 | component alu is
24 | port ( clk : in std_logic;
25 | reset : in std_logic;
26 | aluop : in std_logic_vector(6 downto 0);
27 | src1 : in std_logic_vector(31 downto 0);
28 | src2 : in std_logic_vector(31 downto 0);
29 | cin : in std_logic;
30 | in_valid : in std_logic;
31 |
32 | result : out std_logic_vector(31 downto 0);
33 | cout : out std_logic;
34 | out_valid : out std_logic);
35 | end component alu;
36 |
37 | signal clk_s : std_logic := '0';
38 | signal reset_s : std_logic := '0';
39 | signal aluop_s : std_logic_vector(6 downto 0) := (others => '0');
40 | signal src1_s : std_logic_vector(31 downto 0) := (others => '0');
41 | signal src2_s : std_logic_vector(31 downto 0) := (others => '0');
42 | signal cin_s : std_logic := '0';
43 | signal in_valid_s : std_logic := '0';
44 | signal result_s : std_logic_vector(31 downto 0) := (others => '0');
45 | signal cout_s : std_logic := '0';
46 | signal out_valid_s : std_logic := '0';
47 |
48 | constant testval_1 : std_logic_vector(31 downto 0) := x"FFFFFFFF";
49 | constant testval_2 : std_logic_vector(31 downto 0) := x"00000000";
50 | constant testval_3 : std_logic_vector(31 downto 0) := x"00000001";
51 | constant testval_4 : std_logic_vector(31 downto 0) := x"80000000";
52 | constant testval_5 : std_logic_vector(31 downto 0) := x"11111111";
53 | begin
54 | alu0 : alu port map (clk_s, reset_s, aluop_s, src1_s, src2_s, cin_s, in_valid_s,
55 | result_s, cout_s, out_valid_s);
56 |
57 | clk_s <= not clk_s after 10 ns;
58 |
59 | reset_s <= '1' after 10 ns,
60 | '0' after 40 ns;
61 |
62 | testbench : process
63 | begin
64 | wait for 60 ns;
65 |
66 | for i in 1 to 50 loop
67 | aluop_s <= ("1000000" + std_logic_vector(to_unsigned(i, 7)));
68 | src1_s <= testval_1;
69 | src2_s <= testval_1;
70 | cin_s <= '0';
71 | in_valid_s <= '1';
72 | wait for 20 ns;
73 | in_valid_s <= '0';
74 | wait for 20 ns;
75 | src1_s <= testval_1;
76 | src2_s <= testval_2;
77 | cin_s <= '0';
78 | in_valid_s <= '1';
79 | wait for 20 ns;
80 | in_valid_s <= '0';
81 | wait for 20 ns;
82 | src1_s <= testval_1;
83 | src2_s <= testval_3;
84 | cin_s <= '0';
85 | in_valid_s <= '1';
86 | wait for 20 ns;
87 | in_valid_s <= '0';
88 | wait for 20 ns;
89 | src1_s <= testval_2;
90 | src2_s <= testval_1;
91 | cin_s <= '0';
92 | in_valid_s <= '1';
93 | wait for 20 ns;
94 | in_valid_s <= '0';
95 | wait for 20 ns;
96 | src1_s <= testval_3;
97 | src2_s <= testval_4;
98 | cin_s <= '1';
99 | in_valid_s <= '1';
100 | wait for 20 ns;
101 | in_valid_s <= '0';
102 | wait for 20 ns;
103 | src1_s <= testval_4;
104 | src2_s <= testval_4;
105 | cin_s <= '1';
106 | in_valid_s <= '1';
107 | wait for 20 ns;
108 | in_valid_s <= '0';
109 | wait for 20 ns;
110 | src1_s <= testval_5;
111 | src2_s <= testval_5;
112 | cin_s <= '1';
113 | in_valid_s <= '1';
114 | wait for 20 ns;
115 | in_valid_s <= '0';
116 | wait for 20 ns;
117 | src1_s <= testval_1;
118 | src2_s <= testval_5;
119 | cin_s <= '1';
120 | in_valid_s <= '1';
121 | wait for 20 ns;
122 | in_valid_s <= '0';
123 | wait for 20 ns;
124 | end loop;
125 | end process testbench;
126 | end architecture test;
127 |
128 |
--------------------------------------------------------------------------------
/r-VEX/testbenches/old/tb_decode.vhd:
--------------------------------------------------------------------------------
1 | -----------------------------------------------------------
2 | -- rho-VEX | Testbench Syllable Decode Stage
3 | -----------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -----------------------------------------------------------
8 | -- testbenches/tb_decode.vhd
9 | -----------------------------------------------------------
10 | -- Testsbench for decode + execute + GR + BR (read/write)
11 | -----------------------------------------------------------
12 |
13 | library ieee;
14 | use ieee.std_logic_1164.all;
15 | use ieee.std_logic_signed.all;
16 | use ieee.numeric_std.all;
17 |
18 | entity tb_decode is
19 | end tb_decode;
20 |
21 | architecture test of tb_decode is
22 | component syl_decode is
23 | port ( clk : in std_logic;
24 | reset : in std_logic;
25 | syllable : in std_logic_vector(31 downto 0);
26 | src1 : in std_logic_vector(31 downto 0);
27 | src2 : in std_logic_vector(31 downto 0);
28 | srcb : in std_logic_vector(31 downto 0);
29 | src1_ok : in std_logic;
30 | src2_ok : in std_logic;
31 | srcb_ok : in std_logic;
32 | exe_in : in std_logic;
33 | exe_ok : in std_logic;
34 | start : in std_logic;
35 |
36 | opcode : out std_logic_vector(6 downto 0);
37 | src1_reg : out std_logic_vector(5 downto 0);
38 | src2_reg : out std_logic_vector(5 downto 0);
39 | srcb_reg : out std_logic_vector(2 downto 0);
40 | write_g : out std_logic;
41 | write_b : out std_logic;
42 | src1_en : out std_logic;
43 | src2_en : out std_logic;
44 | srcb_en : out std_logic;
45 | operand1 : out std_logic_vector(31 downto 0);
46 | operand2 : out std_logic_vector(31 downto 0);
47 | operandb : out std_logic_vector(31 downto 0);
48 | dest_reg : out std_logic_vector(5 downto 0);
49 | destb_reg : out std_logic_vector(2 downto 0);
50 | ops_ready : out std_logic;
51 | accept_in : out std_logic);
52 | end component syl_decode;
53 |
54 | component execute is
55 | port ( clk : in std_logic;
56 | reset : in std_logic;
57 | opcode : in std_logic_vector(6 downto 0);
58 | operand1 : in std_logic_vector(31 downto 0);
59 | operand2 : in std_logic_vector(31 downto 0);
60 | operandb : in std_logic_vector(31 downto 0);
61 | start : in std_logic;
62 |
63 | result : out std_logic_vector(31 downto 0);
64 | resultb : out std_logic_vector(31 downto 0);
65 | accept_in : out std_logic;
66 | out_valid : out std_logic);
67 | end component execute;
68 |
69 | component registers_gr is
70 | port ( clk : in std_logic;
71 | reset : in std_logic;
72 | read_en1 : in std_logic;
73 | read_en2 : in std_logic;
74 | write_en : in std_logic;
75 | address_r1 : in std_logic_vector(5 downto 0);
76 | address_r2 : in std_logic_vector(5 downto 0);
77 | address_w : in std_logic_vector(5 downto 0);
78 | data_in : in std_logic_vector(31 downto 0);
79 |
80 | out_valid1 : out std_logic;
81 | out_valid2 : out std_logic;
82 | data_out1 : out std_logic_vector(31 downto 0);
83 | data_out2 : out std_logic_vector(31 downto 0));
84 | end component registers_gr;
85 |
86 | component registers_br is
87 | port ( clk : in std_logic;
88 | reset : in std_logic;
89 | read_en : in std_logic;
90 | write_en : in std_logic;
91 | address_r : in std_logic_vector(2 downto 0);
92 | address_w : in std_logic_vector(2 downto 0);
93 | data_in : in std_logic_vector(31 downto 0);
94 |
95 | out_valid : out std_logic;
96 | data_out : out std_logic_vector(31 downto 0));
97 | end component registers_br;
98 |
99 | component writeback is
100 | port ( clk : in std_logic;
101 | reset : in std_logic;
102 | write_en : in std_logic;
103 | address_gi : in std_logic_vector(5 downto 0);
104 | address_bi : in std_logic_vector(2 downto 0);
105 | data_gi : in std_logic_vector(31 downto 0);
106 | data_bi : in std_logic_vector(31 downto 0);
107 | write_g : in std_logic;
108 | write_b : in std_logic;
109 |
110 | written : out std_logic;
111 | write_g_en : out std_logic;
112 | write_b_en : out std_logic;
113 | address_go : out std_logic_vector(5 downto 0);
114 | address_bo : out std_logic_vector(2 downto 0);
115 | data_go : out std_logic_vector(31 downto 0);
116 | data_bo : out std_logic_vector(31 downto 0);
117 | accept_in : out std_logic);
118 | end component writeback;
119 |
120 | signal clk_s : std_logic := '0';
121 | signal reset_s : std_logic := '0';
122 | signal opcode_s : std_logic_vector(6 downto 0) := (others => '0');
123 | signal operand1_s : std_logic_vector(31 downto 0) := (others => '0');
124 | signal operand2_s : std_logic_vector(31 downto 0) := (others => '0');
125 | signal operandb_s : std_logic_vector(31 downto 0) := (others => '0');
126 | signal result_s : std_logic_vector(31 downto 0) := (others => '0');
127 | signal resultb_s : std_logic_vector(31 downto 0) := (others => '0');
128 | signal start_dec_s : std_logic := '0';
129 | signal accept_in_dec_s : std_logic := '0';
130 | signal ops_ready_s : std_logic := '0';
131 |
132 | signal write_en_s : std_logic := '0';
133 | signal address_w_s : std_logic_vector(5 downto 0) := (others => '0');
134 | signal data_in_s : std_logic_vector(31 downto 0) := (others => '0');
135 | signal write_enb_s : std_logic := '0';
136 | signal address_wb_s : std_logic_vector(2 downto 0) := (others => '0');
137 | signal data_inb_s : std_logic_vector(31 downto 0) := (others => '0');
138 |
139 | signal syllable_s : std_logic_vector(31 downto 0) := (others => '0');
140 | signal src1_s : std_logic_vector(31 downto 0) := (others => '0');
141 | signal src2_s : std_logic_vector(31 downto 0) := (others => '0');
142 | signal srcb_s : std_logic_vector(31 downto 0) := (others => '0');
143 | signal src1_ok_s : std_logic := '0';
144 | signal src2_ok_s : std_logic := '0';
145 | signal srcb_ok_s : std_logic := '0';
146 | signal src1_en_s : std_logic := '0';
147 | signal src2_en_s : std_logic := '0';
148 | signal srcb_en_s : std_logic := '0';
149 |
150 | signal write_g_s : std_logic := '0';
151 | signal write_b_s : std_logic := '0';
152 | signal destb_reg_s : std_logic_vector(2 downto 0) := (others => '0');
153 | signal dest_reg_s : std_logic_vector(5 downto 0) := (others => '0');
154 | signal src1_reg_s : std_logic_vector(5 downto 0) := (others => '0');
155 | signal src2_reg_s : std_logic_vector(5 downto 0) := (others => '0');
156 | signal srcb_reg_s : std_logic_vector(2 downto 0) := (others => '0');
157 |
158 | signal accept_in_ex_s : std_logic := '0';
159 | signal out_valid_s : std_logic := '0';
160 | signal wbwritten_s : std_logic := '0';
161 | signal wbaccept_s : std_logic := '0';
162 | begin
163 | syl_decode0 : syl_decode port map (clk_s, reset_s, syllable_s, src1_s, src2_s, srcb_s, src1_ok_s, src2_ok_s, srcb_ok_s, accept_in_ex_s, out_valid_s, start_dec_s,
164 | opcode_s, src1_reg_s, src2_reg_s, srcb_reg_s, write_g_s, write_b_s, src1_en_s, src2_en_s, srcb_en_s, operand1_s, operand2_s,
165 | operandb_s, dest_reg_s, destb_reg_s, ops_ready_s, accept_in_dec_s);
166 |
167 | execute0 : execute port map (clk_s, reset_s, opcode_s, operand1_s, operand2_s, operandb_s, ops_ready_s,
168 | result_s, resultb_s, accept_in_ex_s, out_valid_s);
169 |
170 | registers_gr0 : registers_gr port map (clk_s, reset_s, src1_en_s, src2_en_s, write_en_s, src1_reg_s, src2_reg_s, address_w_s, data_in_s,
171 | src1_ok_s, src2_ok_s, src1_s, src2_s);
172 |
173 | registers_br0 : registers_br port map (clk_s, reset_s, srcb_en_s, write_enb_s, srcb_reg_s, address_wb_s, data_inb_s,
174 | srcb_ok_s, srcb_s);
175 |
176 | writeback0 : writeback port map (clk_s, reset_s, out_valid_s, dest_reg_s, destb_reg_s, result_s, resultb_s, write_g_s, write_b_s,
177 | wbwritten_s, write_en_s, write_enb_s, address_w_s, address_wb_s, data_in_s, data_inb_s, wbaccept_s);
178 |
179 | clk_s <= not clk_s after 10 ns;
180 |
181 | reset_s <= '1' after 10 ns,
182 | '0' after 40 ns;
183 |
184 | testbench : process
185 | begin
186 | wait for 60 ns;
187 | syllable_s <= "10000010011111100000100001000011"; -- ALU operation ADD, store in GR 63
188 | wait for 20 ns;
189 | start_dec_s <= '1';
190 | wait for 20 ns;
191 | start_dec_s <= '0';
192 | wait for 200 ns;
193 | syllable_s <= "00000010011111000000100001000011"; -- MUL operation low x low, store in GR 62
194 | start_dec_s <= '1';
195 | wait for 20 ns;
196 | start_dec_s <= '0';
197 | wait for 1000 ns;
198 | end process testbench;
199 | end architecture test;
200 |
201 |
--------------------------------------------------------------------------------
/r-VEX/testbenches/old/tb_execute.vhd:
--------------------------------------------------------------------------------
1 | -----------------------------------------------------------
2 | -- rho-VEX | Testbench Execute Stage
3 | -----------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -----------------------------------------------------------
8 | -- testbenches/tb_execute.vhd
9 | -----------------------------------------------------------
10 |
11 | library ieee;
12 | use ieee.std_logic_1164.all;
13 | use ieee.std_logic_signed.all;
14 | use ieee.numeric_std.all;
15 |
16 | entity tb_execute is
17 | end tb_execute;
18 |
19 | architecture test of tb_execute is
20 | component execute is
21 | port ( clk : in std_logic;
22 | reset : in std_logic;
23 | opcode : in std_logic_vector(6 downto 0);
24 | operand1 : in std_logic_vector(31 downto 0);
25 | operand2 : in std_logic_vector(31 downto 0);
26 | operandb : in std_logic_vector(31 downto 0);
27 | start : in std_logic;
28 |
29 | result : out std_logic_vector(31 downto 0);
30 | resultb : out std_logic_vector(31 downto 0);
31 | accept_in : out std_logic;
32 | out_valid : out std_logic);
33 | end component execute;
34 |
35 | signal clk_s : std_logic := '0';
36 | signal reset_s : std_logic := '0';
37 | signal opcode_s : std_logic_vector(6 downto 0) := (others => '0');
38 | signal operand1_s : std_logic_vector(31 downto 0) := (others => '0');
39 | signal operand2_s : std_logic_vector(31 downto 0) := (others => '0');
40 | signal operandb_s : std_logic_vector(31 downto 0) := (others => '0');
41 | signal result_s : std_logic_vector(31 downto 0) := (others => '0');
42 | signal resultb_s : std_logic_vector(31 downto 0) := (others => '0');
43 | signal start_s : std_logic := '0';
44 | signal accept_in_s : std_logic := '0';
45 | signal out_valid_s : std_logic := '0';
46 |
47 | begin
48 | execute0 : execute port map (clk_s, reset_s, opcode_s, operand1_s, operand2_s, operandb_s, start_s,
49 | result_s, resultb_s, accept_in_s, out_valid_s);
50 |
51 | clk_s <= not clk_s after 10 ns;
52 |
53 | reset_s <= '1' after 10 ns,
54 | '0' after 40 ns;
55 |
56 | testbench : process
57 | begin
58 | wait for 60 ns;
59 | opcode_s <= "1000001"; -- ALU operation ADD
60 | operand1_s <= x"00000004";
61 | operand2_s <= x"00000005";
62 | wait for 20 ns;
63 | start_s <= '1';
64 | wait for 80 ns;
65 | start_s <= '0';
66 | wait for 60 ns;
67 | opcode_s <= "0000001"; -- MUL operation low x low
68 | operand1_s <= x"00000004";
69 | operand2_s <= x"00000005";
70 | wait for 20 ns;
71 | start_s <= '1';
72 | end process testbench;
73 | end architecture test;
74 |
75 |
--------------------------------------------------------------------------------
/r-VEX/testbenches/old/tb_mul.vhd:
--------------------------------------------------------------------------------
1 | -----------------------------------------------------------
2 | -- rho-VEX | Testbench MUL
3 | -----------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -----------------------------------------------------------
8 | -- testbenches/tb_mul.vhd
9 | -----------------------------------------------------------
10 |
11 | library ieee;
12 | use ieee.std_logic_1164.all;
13 | use ieee.std_logic_signed.all;
14 | use ieee.numeric_std.all;
15 |
16 | library work;
17 | use work.opcodes.all;
18 |
19 | entity tb_mul is
20 | end tb_mul;
21 |
22 | architecture test of tb_mul is
23 | component mul is
24 | port ( clk : in std_logic;
25 | reset : in std_logic;
26 | mulop : in std_logic_vector(6 downto 0);
27 | src1 : in std_logic_vector(31 downto 0);
28 | src2 : in std_logic_vector(31 downto 0);
29 | in_valid : in std_logic;
30 |
31 | result : out std_logic_vector(31 downto 0);
32 | overflow : out std_logic;
33 | out_valid : out std_logic);
34 | end component mul;
35 |
36 | signal clk_s : std_logic := '0';
37 | signal reset_s : std_logic := '0';
38 | signal mulop_s : std_logic_vector(6 downto 0) := (others => '0');
39 | signal src1_s : std_logic_vector(31 downto 0) := (others => '0');
40 | signal src2_s : std_logic_vector(31 downto 0) := (others => '0');
41 | signal in_valid_s : std_logic := '0';
42 | signal result_s : std_logic_vector(31 downto 0) := (others => '0');
43 | signal overflow_s : std_logic := '0';
44 | signal out_valid_s : std_logic := '0';
45 |
46 | constant testval_1 : std_logic_vector(31 downto 0) := x"00000003";
47 | constant testval_2 : std_logic_vector(31 downto 0) := x"00000002";
48 | constant testval_3 : std_logic_vector(31 downto 0) := x"000000FF";
49 | constant testval_4 : std_logic_vector(31 downto 0) := x"8432FFFF";
50 | constant testval_5 : std_logic_vector(31 downto 0) := x"11111111";
51 | begin
52 | mul0 : mul port map (clk_s, reset_s, mulop_s, src1_s, src2_s, in_valid_s,
53 | result_s, overflow_s, out_valid_s);
54 |
55 | clk_s <= not clk_s after 10 ns;
56 |
57 | reset_s <= '1' after 10 ns,
58 | '0' after 40 ns;
59 |
60 | testbench : process
61 | begin
62 | wait for 60 ns;
63 |
64 | for i in 1 to 15 loop
65 | mulop_s <= std_logic_vector(to_unsigned(i, 7));
66 | src1_s <= testval_1;
67 | src2_s <= testval_1;
68 | in_valid_s <= '1';
69 | wait for 20 ns;
70 | in_valid_s <= '0';
71 | wait for 20 ns;
72 | src1_s <= testval_1;
73 | src2_s <= testval_2;
74 | in_valid_s <= '1';
75 | wait for 20 ns;
76 | in_valid_s <= '0';
77 | wait for 20 ns;
78 | src1_s <= testval_1;
79 | src2_s <= testval_3;
80 | in_valid_s <= '1';
81 | wait for 20 ns;
82 | in_valid_s <= '0';
83 | wait for 20 ns;
84 | src1_s <= testval_2;
85 | src2_s <= testval_1;
86 | in_valid_s <= '1';
87 | wait for 20 ns;
88 | in_valid_s <= '0';
89 | wait for 20 ns;
90 | src1_s <= testval_3;
91 | src2_s <= testval_4;
92 | in_valid_s <= '1';
93 | wait for 20 ns;
94 | in_valid_s <= '0';
95 | wait for 20 ns;
96 | src1_s <= testval_4;
97 | src2_s <= testval_4;
98 | in_valid_s <= '1';
99 | wait for 20 ns;
100 | in_valid_s <= '0';
101 | wait for 20 ns;
102 | src1_s <= testval_5;
103 | src2_s <= testval_5;
104 | in_valid_s <= '1';
105 | wait for 20 ns;
106 | in_valid_s <= '0';
107 | wait for 20 ns;
108 | src1_s <= testval_1;
109 | src2_s <= testval_5;
110 | in_valid_s <= '1';
111 | wait for 20 ns;
112 | in_valid_s <= '0';
113 | wait for 20 ns;
114 | end loop;
115 | end process testbench;
116 | end architecture test;
117 |
118 |
--------------------------------------------------------------------------------
/r-VEX/testbenches/old/tb_registers_gr.vhd:
--------------------------------------------------------------------------------
1 | -----------------------------------------------------------
2 | -- rho-VEX | GR register file
3 | -----------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -----------------------------------------------------------
8 | -- testbenches/tb_registers_gr.vhd
9 | -----------------------------------------------------------
10 |
11 | library ieee;
12 | use ieee.std_logic_1164.all;
13 | use ieee.std_logic_signed.all;
14 | use ieee.numeric_std.all;
15 |
16 | entity tb_registers_gr is
17 | end tb_registers_gr;
18 |
19 | architecture test of tb_registers_gr is
20 | component registers_gr is
21 | port ( clk : in std_logic;
22 | reset : in std_logic;
23 | read_en1 : in std_logic;
24 | read_en2 : in std_logic;
25 | write_en : in std_logic;
26 | address_r1 : in std_logic_vector(5 downto 0);
27 | address_r2 : in std_logic_vector(5 downto 0);
28 | address_w : in std_logic_vector(5 downto 0);
29 | data_in : in std_logic_vector(31 downto 0);
30 |
31 | out_valid1 : out std_logic;
32 | out_valid2 : out std_logic;
33 | data_out1 : out std_logic_vector(31 downto 0);
34 | data_out2 : out std_logic_vector(31 downto 0));
35 | end component registers_gr;
36 |
37 | signal clk_s : std_logic := '0';
38 | signal reset_s : std_logic := '0';
39 | signal read_en1_s : std_logic := '0';
40 | signal read_en2_s : std_logic := '0';
41 | signal write_en_s : std_logic := '0';
42 | signal address_r1_s : std_logic_vector(5 downto 0) := (others => '0');
43 | signal address_r2_s : std_logic_vector(5 downto 0) := (others => '0');
44 | signal address_w_s : std_logic_vector(5 downto 0) := (others => '0');
45 | signal data_in_s : std_logic_vector(31 downto 0) := (others => '0');
46 | signal out_valid1_s : std_logic := '0';
47 | signal out_valid2_s : std_logic := '0';
48 | signal data_out1_s : std_logic_vector(31 downto 0) := (others => '0');
49 | signal data_out2_s : std_logic_vector(31 downto 0) := (others => '0');
50 | begin
51 | regs0 : registers_gr port map (clk_s, reset_s, read_en1_s, read_en2_s, write_en_s, address_r1_s, address_r2_s, address_w_s, data_in_s,
52 | out_valid1_s, out_valid2_s, data_out1_s, data_out2_s);
53 |
54 | clk_s <= not clk_s after 10 ns;
55 |
56 | reset_s <= '1' after 10 ns,
57 | '0' after 40 ns;
58 |
59 | testbench : process
60 | begin
61 | wait for 60 ns;
62 |
63 | for i in 0 to 63 loop
64 | address_w_s <= std_logic_vector(to_unsigned(i, 6));
65 | data_in_s <= std_logic_vector(to_unsigned(i, 32));
66 | write_en_s <= '1';
67 | wait for 20 ns;
68 | write_en_s <= '0';
69 | wait for 20 ns;
70 | end loop;
71 |
72 | for i in 0 to 63 loop
73 | address_r1_s <= std_logic_vector(to_unsigned(i, 6));
74 | read_en1_s <= '1';
75 | wait for 20 ns;
76 | read_en1_s <= '0';
77 | wait for 20 ns;
78 | end loop;
79 |
80 | -- simultaneous read and write test
81 | address_w_s <= std_logic_vector(to_unsigned(1, 6));
82 | address_r1_s <= std_logic_vector(to_unsigned(2, 6));
83 | data_in_s <= std_logic_vector(to_unsigned(123, 32));
84 | write_en_s <= '1';
85 | read_en1_s <= '1';
86 | end process testbench;
87 | end architecture test;
88 |
89 |
--------------------------------------------------------------------------------
/r-VEX/testbenches/old/tb_system.vhd:
--------------------------------------------------------------------------------
1 | -----------------------------------------------------------
2 | -- rho-VEX | Testbench system
3 | -----------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -----------------------------------------------------------
8 | -- testbenches/tb_system.vhd
9 | -----------------------------------------------------------
10 |
11 | library ieee;
12 | use ieee.std_logic_1164.all;
13 | use ieee.numeric_std.all;
14 |
15 | library work;
16 |
17 | entity tb_system is
18 | end tb_system;
19 |
20 | architecture test of tb_system is
21 | component system is
22 | port ( clk : in std_logic;
23 | reset : in std_logic;
24 | run : in std_logic);
25 | end component system;
26 |
27 | signal clk_s : std_logic := '0';
28 | signal reset_s : std_logic := '0';
29 | signal run_s : std_logic := '0';
30 | begin
31 | system_0 : system port map (clk_s, reset_s, run_s);
32 |
33 | clk_s <= not clk_s after 10 ns;
34 |
35 | reset_s <= '1' after 10 ns,
36 | '0' after 40 ns;
37 |
38 | run_s <= '1' after 100 ns,
39 | '0' after 120 ns;
40 | end architecture test;
41 |
42 |
--------------------------------------------------------------------------------
/r-VEX/testbenches/tb_system.vhd:
--------------------------------------------------------------------------------
1 | -------------------------------------------------------------------------------
2 | -- r-VEX | Testbench system
3 | -------------------------------------------------------------------------------
4 | --
5 | -- Copyright (c) 2008, Thijs van As
6 | --
7 | -- Computer Engineering Laboratory
8 | -- Delft University of Technology
9 | -- Delft, The Netherlands
10 | --
11 | -- http://r-vex.googlecode.com
12 | --
13 | -- r-VEX is free hardware: you can redistribute it and/or modify
14 | -- it under the terms of the GNU General Public License as published by
15 | -- the Free Software Foundation, either version 3 of the License, or
16 | -- (at your option) any later version.
17 | --
18 | -- This program is distributed in the hope that it will be useful,
19 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of
20 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 | -- GNU General Public License for more details.
22 | --
23 | -- You should have received a copy of the GNU General Public License
24 | -- along with this program. If not, see .
25 | --
26 | -------------------------------------------------------------------------------
27 | -- tb_system.vhd
28 | -------------------------------------------------------------------------------
29 |
30 | library ieee;
31 | use ieee.std_logic_1164.all;
32 | use ieee.numeric_std.all;
33 |
34 | library work;
35 | use work.rVEX_pkg.all;
36 |
37 | entity tb_system is
38 | end tb_system;
39 |
40 | architecture test of tb_system is
41 | component system is
42 | port ( clk : in std_logic;
43 | reset : in std_logic;
44 |
45 | tx : out std_logic);
46 | end component system;
47 |
48 | signal tx_s : std_logic := '0';
49 | signal clk_s : std_logic := '0';
50 | signal reset_s : std_logic := '0';
51 | begin
52 | system_0 : system port map (clk => clk_s,
53 | reset => reset_s,
54 |
55 | tx => tx_s);
56 |
57 | clk_s <= not clk_s after 10 ns;
58 |
59 | reset_s <= not ACTIVE_LOW after 10 ns,
60 | ACTIVE_LOW after 50 ns;
61 | end architecture test;
62 |
63 |
--------------------------------------------------------------------------------