├── AXI_modbus ├── README.md ├── image │ └── README │ │ ├── 1656471924071.png │ │ ├── 1656472212220.png │ │ ├── 1656473035122.png │ │ ├── 1656473443314.png │ │ ├── 1656473470206.png │ │ ├── 1656480162933.png │ │ ├── 1656480462814.png │ │ ├── 1656480553603.png │ │ ├── 1656482893005.png │ │ └── 1656483013594.png ├── tb │ ├── hdl │ │ ├── DPRAM.v │ │ ├── clk_div.v │ │ ├── crc_16.v │ │ ├── ct_15t_gen.v │ │ ├── ct_35t_gen.v │ │ ├── exceptions.v │ │ ├── frame_rx.v │ │ ├── func_handler.v │ │ ├── modbus_crc_16.v │ │ ├── modbus_rtu_slave_top.v │ │ ├── reset_module.v │ │ ├── top.v │ │ ├── tx_response.v │ │ ├── uart_byte_rx.v │ │ └── uart_byte_tx.v │ ├── modbus_rtu_slave_top_tb.do │ ├── modbus_rtu_slave_top_tb.v │ ├── rtl_work │ │ ├── @_opt │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_0.qdb │ │ │ ├── _lib1_0.qpg │ │ │ ├── _lib1_0.qtl │ │ │ ├── _lib2_0.qdb │ │ │ ├── _lib2_0.qpg │ │ │ ├── _lib2_0.qtl │ │ │ ├── _lib3_0.qdb │ │ │ ├── _lib3_0.qpg │ │ │ ├── _lib3_0.qtl │ │ │ ├── _lib4_0.qdb │ │ │ ├── _lib4_0.qpg │ │ │ └── _lib4_0.qtl │ │ ├── @_opt1 │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_0.qdb │ │ │ ├── _lib1_0.qpg │ │ │ ├── _lib1_0.qtl │ │ │ ├── _lib2_0.qdb │ │ │ ├── _lib2_0.qpg │ │ │ ├── _lib2_0.qtl │ │ │ ├── _lib3_0.qdb │ │ │ ├── _lib3_0.qpg │ │ │ ├── _lib3_0.qtl │ │ │ ├── _lib4_0.qdb │ │ │ ├── _lib4_0.qpg │ │ │ └── _lib4_0.qtl │ │ ├── @_opt2 │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_0.qdb │ │ │ ├── _lib1_0.qpg │ │ │ ├── _lib1_0.qtl │ │ │ ├── _lib2_0.qdb │ │ │ ├── _lib2_0.qpg │ │ │ ├── _lib2_0.qtl │ │ │ ├── _lib3_0.qdb │ │ │ ├── _lib3_0.qpg │ │ │ ├── _lib3_0.qtl │ │ │ ├── _lib4_0.qdb │ │ │ ├── _lib4_0.qpg │ │ │ ├── _lib4_0.qtl │ │ │ ├── _lib5_0.qdb │ │ │ ├── _lib5_0.qpg │ │ │ └── _lib5_0.qtl │ │ ├── _info │ │ ├── _lib.qdb │ │ ├── _lib1_0.qdb │ │ ├── _lib1_0.qpg │ │ ├── _lib1_0.qtl │ │ ├── _opt1__lock │ │ ├── _opt__lock │ │ └── _vmake │ └── vsim.wlf └── vivado │ ├── hdl │ ├── DPRAM.v │ ├── clk_div.v │ ├── crc_16.v │ ├── ct_15t_gen.v │ ├── ct_35t_gen.v │ ├── exceptions.v │ ├── frame_rx.v │ ├── func_handler.v │ ├── modbus_crc_16.v │ ├── modbus_rtu_slave_top.v │ ├── reset_module.v │ ├── top.v │ ├── tx_response.v │ ├── uart_byte_rx.v │ └── uart_byte_tx.v │ ├── ip_repo │ └── axi_modbus_1.0 │ │ ├── bd │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── drivers │ │ └── axi_modbus_v1_0 │ │ │ ├── data │ │ │ ├── axi_modbus.mdd │ │ │ └── axi_modbus.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── axi_modbus.c │ │ │ ├── axi_modbus.h │ │ │ └── axi_modbus_selftest.c │ │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── axi_modbus_v1_0_tb.sv │ │ │ └── design.tcl │ │ └── debug_hw_design │ │ │ ├── axi_modbus_v1_0_hw_test.tcl │ │ │ └── design.tcl │ │ ├── hdl │ │ ├── DPRAM.v │ │ ├── axi_modbus_v1_0.v │ │ ├── axi_modbus_v1_0_S0_AXI.v │ │ ├── clk_div.v │ │ ├── crc_16.v │ │ ├── ct_15t_gen.v │ │ ├── ct_35t_gen.v │ │ ├── exceptions.v │ │ ├── frame_rx.v │ │ ├── func_handler.v │ │ ├── modbus_crc_16.v │ │ ├── modbus_rtu_slave_top.v │ │ ├── tx_response.v │ │ ├── uart_byte_rx.v │ │ └── uart_byte_tx.v │ │ ├── src │ │ ├── DPRAM.v │ │ ├── axi_modbus_v1_0.v │ │ ├── axi_modbus_v1_0_S0_AXI.v │ │ ├── clk_div.v │ │ ├── crc_16.v │ │ ├── ct_15t_gen.v │ │ ├── ct_35t_gen.v │ │ ├── exceptions.v │ │ ├── frame_rx.v │ │ ├── func_handler.v │ │ ├── modbus_crc_16.v │ │ ├── modbus_rtu_slave_top.v │ │ ├── tx_response.v │ │ ├── uart_byte_rx.v │ │ └── uart_byte_tx.v │ │ └── xgui │ │ └── axi_modbus_v1_0.tcl │ └── managed_ip_project │ ├── managed_ip_project.cache │ └── wt │ │ └── project.wpc │ ├── managed_ip_project.hw │ └── managed_ip_project.lpr │ └── managed_ip_project.xpr ├── README.md ├── crc_python └── main.py ├── image └── README │ ├── 1656466808318.png │ ├── 1656467688993.png │ ├── 1656468054291.png │ ├── 1656468347844.png │ ├── 1656469426588.png │ ├── 1656470139988.png │ ├── 1656470319207.png │ ├── 1656470388435.png │ ├── 1656470469951.png │ └── 1656470599405.png └── modbus_rtu_slave_rtl ├── tb ├── modbus_rtu_slave_top_tb.do ├── modbus_rtu_slave_top_tb.v ├── modelsim.ini ├── rtl_work │ ├── @_opt │ │ ├── _lib.qdb │ │ ├── _lib1_0.qdb │ │ ├── _lib1_0.qpg │ │ ├── _lib1_0.qtl │ │ ├── _lib2_0.qdb │ │ ├── _lib2_0.qpg │ │ ├── _lib2_0.qtl │ │ ├── _lib3_0.qdb │ │ ├── _lib3_0.qpg │ │ ├── _lib3_0.qtl │ │ ├── _lib4_0.qdb │ │ ├── _lib4_0.qpg │ │ └── _lib4_0.qtl │ ├── _info │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ └── _vmake └── vsim.wlf └── vivado ├── Makefile ├── clean.sh ├── create_and_build_proj.tcl ├── create_proj.tcl ├── hdl ├── DPRAM.v ├── clk_div.v ├── crc_16.v ├── ct_15t_gen.v ├── ct_35t_gen.v ├── exceptions.v ├── frame_rx.v ├── func_handler.v ├── modbus_crc_16.v ├── modbus_rtu_slave_top.v ├── reset_module.v ├── top.v ├── tx_response.v ├── uart_byte_rx.v └── uart_byte_tx.v ├── ip_cache └── .gitkeep ├── proj_build.sh ├── proj_gen.sh ├── scripts ├── create_proj.tcl ├── gen_xsa.tcl ├── implement.tcl ├── ip_cache.tcl └── synthesis.tcl ├── setenv.sh ├── vivado_proj ├── vivado.jou ├── vivado.log ├── vivado_proj.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ └── webtalk_pa.xml ├── vivado_proj.hw │ ├── hw_1 │ │ └── hw.xml │ └── vivado_proj.lpr ├── vivado_proj.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ └── vrs_config_4.xml │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .phys_opt_design.begin.rst │ │ ├── .phys_opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── phys_opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── top.bit │ │ ├── top.tcl │ │ ├── top.vdi │ │ ├── top_bus_skew_routed.pb │ │ ├── top_bus_skew_routed.rpt │ │ ├── top_bus_skew_routed.rpx │ │ ├── top_clock_utilization_routed.rpt │ │ ├── top_control_sets_placed.rpt │ │ ├── top_drc_opted.pb │ │ ├── top_drc_opted.rpt │ │ ├── top_drc_opted.rpx │ │ ├── top_drc_routed.pb │ │ ├── top_drc_routed.rpt │ │ ├── top_drc_routed.rpx │ │ ├── top_io_placed.rpt │ │ ├── top_methodology_drc_routed.pb │ │ ├── top_methodology_drc_routed.rpt │ │ ├── top_methodology_drc_routed.rpx │ │ ├── top_opt.dcp │ │ ├── top_physopt.dcp │ │ ├── top_placed.dcp │ │ ├── top_power_routed.rpt │ │ ├── top_power_routed.rpx │ │ ├── top_power_summary_routed.pb │ │ ├── top_route_status.pb │ │ ├── top_route_status.rpt │ │ ├── top_routed.dcp │ │ ├── top_timing_summary_routed.pb │ │ ├── top_timing_summary_routed.rpt │ │ ├── top_timing_summary_routed.rpx │ │ ├── top_utilization_placed.pb │ │ ├── top_utilization_placed.rpt │ │ ├── usage_statistics_webtalk.html │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── top_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── top.dcp │ │ ├── top.tcl │ │ ├── top.vds │ │ ├── top_utilization_synth.pb │ │ ├── top_utilization_synth.rpt │ │ ├── vivado.jou │ │ └── vivado.pb ├── vivado_proj.srcs │ └── constrs_1 │ │ └── imports │ │ └── xdc │ │ └── top.xdc └── vivado_proj.xpr └── xdc └── top.xdc /AXI_modbus/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/README.md -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656471924071.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656471924071.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656472212220.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656472212220.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656473035122.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656473035122.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656473443314.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656473443314.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656473470206.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656473470206.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656480162933.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656480162933.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656480462814.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656480462814.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656480553603.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656480553603.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656482893005.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656482893005.png -------------------------------------------------------------------------------- /AXI_modbus/image/README/1656483013594.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/image/README/1656483013594.png -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/DPRAM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/DPRAM.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/clk_div.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/ct_15t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/ct_15t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/ct_35t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/ct_35t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/exceptions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/exceptions.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/frame_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/frame_rx.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/func_handler.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/func_handler.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/modbus_crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/modbus_crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/modbus_rtu_slave_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/modbus_rtu_slave_top.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/reset_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/reset_module.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/top.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/tx_response.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/tx_response.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/uart_byte_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/uart_byte_rx.v -------------------------------------------------------------------------------- /AXI_modbus/tb/hdl/uart_byte_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/hdl/uart_byte_tx.v -------------------------------------------------------------------------------- /AXI_modbus/tb/modbus_rtu_slave_top_tb.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/modbus_rtu_slave_top_tb.do -------------------------------------------------------------------------------- /AXI_modbus/tb/modbus_rtu_slave_top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/modbus_rtu_slave_top_tb.v -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib1_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib1_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib1_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib1_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib2_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib2_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib2_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib2_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib2_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib2_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib3_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib3_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib3_0.qpg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib3_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib3_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib4_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib4_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib4_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib4_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt/_lib4_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt/_lib4_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib1_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib1_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib1_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib1_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib2_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib2_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib2_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib2_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib2_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib2_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib3_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib3_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib3_0.qpg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib3_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib3_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib4_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib4_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib4_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib4_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt1/_lib4_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt1/_lib4_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib1_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib1_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib1_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib1_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib2_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib2_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib2_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib2_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib2_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib2_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib3_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib3_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib3_0.qpg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib3_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib3_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib4_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib4_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib4_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib4_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib4_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib4_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib5_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib5_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib5_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib5_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/@_opt2/_lib5_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/@_opt2/_lib5_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/_info -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/_lib.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_lib1_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/_lib1_0.qdb -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/_lib1_0.qpg -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/rtl_work/_lib1_0.qtl -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_opt1__lock: -------------------------------------------------------------------------------- 1 | txzing@TX, pid = 8536 2 | -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_opt__lock: -------------------------------------------------------------------------------- 1 | txzing@TX, pid = 10236 2 | -------------------------------------------------------------------------------- /AXI_modbus/tb/rtl_work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /AXI_modbus/tb/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/tb/vsim.wlf -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/DPRAM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/DPRAM.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/clk_div.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/ct_15t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/ct_15t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/ct_35t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/ct_35t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/exceptions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/exceptions.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/frame_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/frame_rx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/func_handler.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/func_handler.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/modbus_crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/modbus_crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/modbus_rtu_slave_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/modbus_rtu_slave_top.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/reset_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/reset_module.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/top.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/tx_response.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/tx_response.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/uart_byte_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/uart_byte_rx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/hdl/uart_byte_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/hdl/uart_byte_tx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/bd/bd.tcl -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/component.xml -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/data/axi_modbus.mdd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/data/axi_modbus.mdd -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/data/axi_modbus.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/data/axi_modbus.tcl -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/Makefile -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/axi_modbus.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/axi_modbus.c -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/axi_modbus.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/axi_modbus.h -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/axi_modbus_selftest.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/drivers/axi_modbus_v1_0/src/axi_modbus_selftest.c -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/bfm_design/axi_modbus_v1_0_tb.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/bfm_design/axi_modbus_v1_0_tb.sv -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/bfm_design/design.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/bfm_design/design.tcl -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/debug_hw_design/axi_modbus_v1_0_hw_test.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/debug_hw_design/axi_modbus_v1_0_hw_test.tcl -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/debug_hw_design/design.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/example_designs/debug_hw_design/design.tcl -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/DPRAM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/DPRAM.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/axi_modbus_v1_0.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/axi_modbus_v1_0.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/axi_modbus_v1_0_S0_AXI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/axi_modbus_v1_0_S0_AXI.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/clk_div.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/ct_15t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/ct_15t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/ct_35t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/ct_35t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/exceptions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/exceptions.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/frame_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/frame_rx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/func_handler.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/func_handler.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/modbus_crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/modbus_crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/modbus_rtu_slave_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/modbus_rtu_slave_top.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/tx_response.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/tx_response.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/uart_byte_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/uart_byte_rx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/uart_byte_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/hdl/uart_byte_tx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/DPRAM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/DPRAM.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/axi_modbus_v1_0.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/axi_modbus_v1_0.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/axi_modbus_v1_0_S0_AXI.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/axi_modbus_v1_0_S0_AXI.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/clk_div.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/ct_15t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/ct_15t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/ct_35t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/ct_35t_gen.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/exceptions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/exceptions.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/frame_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/frame_rx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/func_handler.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/func_handler.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/modbus_crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/modbus_crc_16.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/modbus_rtu_slave_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/modbus_rtu_slave_top.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/tx_response.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/tx_response.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/uart_byte_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/uart_byte_rx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/uart_byte_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/src/uart_byte_tx.v -------------------------------------------------------------------------------- /AXI_modbus/vivado/ip_repo/axi_modbus_1.0/xgui/axi_modbus_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/ip_repo/axi_modbus_1.0/xgui/axi_modbus_v1_0.tcl -------------------------------------------------------------------------------- /AXI_modbus/vivado/managed_ip_project/managed_ip_project.cache/wt/project.wpc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/managed_ip_project/managed_ip_project.cache/wt/project.wpc -------------------------------------------------------------------------------- /AXI_modbus/vivado/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr -------------------------------------------------------------------------------- /AXI_modbus/vivado/managed_ip_project/managed_ip_project.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/AXI_modbus/vivado/managed_ip_project/managed_ip_project.xpr -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/README.md -------------------------------------------------------------------------------- /crc_python/main.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/crc_python/main.py -------------------------------------------------------------------------------- /image/README/1656466808318.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656466808318.png -------------------------------------------------------------------------------- /image/README/1656467688993.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656467688993.png -------------------------------------------------------------------------------- /image/README/1656468054291.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656468054291.png -------------------------------------------------------------------------------- /image/README/1656468347844.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656468347844.png -------------------------------------------------------------------------------- /image/README/1656469426588.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656469426588.png -------------------------------------------------------------------------------- /image/README/1656470139988.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656470139988.png -------------------------------------------------------------------------------- /image/README/1656470319207.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656470319207.png -------------------------------------------------------------------------------- /image/README/1656470388435.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656470388435.png -------------------------------------------------------------------------------- /image/README/1656470469951.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656470469951.png -------------------------------------------------------------------------------- /image/README/1656470599405.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/image/README/1656470599405.png -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/modbus_rtu_slave_top_tb.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/modbus_rtu_slave_top_tb.do -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/modbus_rtu_slave_top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/modbus_rtu_slave_top_tb.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/modelsim.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/modelsim.ini -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib.qdb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib1_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib1_0.qdb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib1_0.qpg -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib1_0.qtl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib2_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib2_0.qdb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib2_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib2_0.qpg -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib2_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib2_0.qtl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib3_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib3_0.qdb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib3_0.qpg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib3_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib3_0.qtl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib4_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib4_0.qdb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib4_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib4_0.qpg -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib4_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/@_opt/_lib4_0.qtl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/_info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/_info -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/_lib.qdb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/_lib1_0.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/_lib1_0.qdb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/_lib1_0.qpg -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/rtl_work/_lib1_0.qtl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/rtl_work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/tb/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/tb/vsim.wlf -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/Makefile -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/clean.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/clean.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/create_and_build_proj.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/create_and_build_proj.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/create_proj.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/create_proj.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/DPRAM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/DPRAM.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/clk_div.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/crc_16.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/ct_15t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/ct_15t_gen.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/ct_35t_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/ct_35t_gen.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/exceptions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/exceptions.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/frame_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/frame_rx.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/func_handler.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/func_handler.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/modbus_crc_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/modbus_crc_16.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/modbus_rtu_slave_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/modbus_rtu_slave_top.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/reset_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/reset_module.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/top.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/tx_response.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/tx_response.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/uart_byte_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/uart_byte_rx.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/hdl/uart_byte_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/hdl/uart_byte_tx.v -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/ip_cache/.gitkeep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/proj_build.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/proj_build.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/proj_gen.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/proj_gen.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/scripts/create_proj.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/scripts/create_proj.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/scripts/gen_xsa.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/scripts/gen_xsa.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/scripts/implement.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/scripts/implement.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/scripts/ip_cache.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/scripts/ip_cache.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/scripts/synthesis.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/scripts/synthesis.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/setenv.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/setenv.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado.jou -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado.log -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/gui_handlers.wdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/gui_handlers.wdf -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/java_command_handlers.wdf -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/project.wpc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/project.wpc -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/synthesis.wdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/synthesis.wdf -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/synthesis_details.wdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/synthesis_details.wdf -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.cache/wt/webtalk_pa.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.hw/hw_1/hw.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.hw/hw_1/hw.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.hw/vivado_proj.lpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.hw/vivado_proj.lpr -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_1.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_2.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_2.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_3.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_3.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_4.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/.jobs/vrs_config_4.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.Vivado_Implementation.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.init_design.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.init_design.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.opt_design.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.opt_design.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.phys_opt_design.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.phys_opt_design.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.phys_opt_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.place_design.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.place_design.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.place_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.route_design.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.route_design.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.route_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.vivado.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.vivado.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.write_bitstream.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.write_bitstream.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/.write_bitstream.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/ISEWrap.js: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/ISEWrap.js -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/ISEWrap.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/ISEWrap.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/gen_run.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/gen_run.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/htr.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/htr.txt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/init_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/init_design.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/opt_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/opt_design.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/phys_opt_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/phys_opt_design.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/place_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/place_design.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/project.wdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/project.wdf -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/route_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/route_design.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/rundef.js: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/rundef.js -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/runme.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/runme.bat -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/runme.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/runme.log -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/runme.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/runme.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top.bit -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top.vdi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top.vdi -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_bus_skew_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_bus_skew_routed.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_bus_skew_routed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_bus_skew_routed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_bus_skew_routed.rpx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_bus_skew_routed.rpx -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_clock_utilization_routed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_clock_utilization_routed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_control_sets_placed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_control_sets_placed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_opted.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_opted.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_opted.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_opted.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_opted.rpx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_opted.rpx -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_routed.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_routed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_routed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_routed.rpx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_drc_routed.rpx -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_io_placed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_io_placed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_methodology_drc_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_methodology_drc_routed.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_methodology_drc_routed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_methodology_drc_routed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_methodology_drc_routed.rpx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_methodology_drc_routed.rpx -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_opt.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_opt.dcp -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_physopt.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_physopt.dcp -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_placed.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_placed.dcp -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_power_routed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_power_routed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_power_routed.rpx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_power_routed.rpx -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_power_summary_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_power_summary_routed.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_route_status.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_route_status.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_route_status.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_route_status.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_routed.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_routed.dcp -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_timing_summary_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_timing_summary_routed.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_timing_summary_routed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_timing_summary_routed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_timing_summary_routed.rpx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_timing_summary_routed.rpx -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_utilization_placed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_utilization_placed.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_utilization_placed.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/top_utilization_placed.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/usage_statistics_webtalk.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/usage_statistics_webtalk.html -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/usage_statistics_webtalk.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/usage_statistics_webtalk.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/vivado.jou -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/vivado.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/write_bitstream.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/impl_1/write_bitstream.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/.Xil/top_propImpl.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/.Xil/top_propImpl.xdc -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/.vivado.begin.rst -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/ISEWrap.js: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/ISEWrap.js -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/ISEWrap.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/ISEWrap.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/gen_run.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/gen_run.xml -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/htr.txt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/rundef.js: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/rundef.js -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/runme.bat -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/runme.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/runme.log -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/runme.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/runme.sh -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top.dcp -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top.tcl -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top.vds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top.vds -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top_utilization_synth.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top_utilization_synth.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/top_utilization_synth.rpt -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/vivado.jou -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.srcs/constrs_1/imports/xdc/top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.srcs/constrs_1/imports/xdc/top.xdc -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.xpr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/vivado_proj/vivado_proj.xpr -------------------------------------------------------------------------------- /modbus_rtu_slave_rtl/vivado/xdc/top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/txzing/modbus_crc_verilog/HEAD/modbus_rtu_slave_rtl/vivado/xdc/top.xdc --------------------------------------------------------------------------------