├── src ├── CMakeLists.txt └── logic │ ├── axi4 │ ├── CMakeLists.txt │ └── stream │ │ ├── sequencer.cpp │ │ ├── rx_sequencer.cpp │ │ ├── tx_sequencer.cpp │ │ ├── reset_sequencer.cpp │ │ ├── reset_if.cpp │ │ ├── rx_sequence.cpp │ │ ├── tx_sequence.cpp │ │ ├── reset_sequence.cpp │ │ └── CMakeLists.txt │ ├── trace_base.cpp │ ├── printer │ └── CMakeLists.txt │ ├── gtest │ ├── main.cpp │ └── factory.cpp │ ├── bitstream_const_reference.cpp │ ├── command_line_argument.hpp │ ├── trace_verilated.cpp │ ├── bitstream_reference.cpp │ └── command_line_argument.cpp ├── rtl ├── logic │ ├── pll │ │ ├── CMakeLists.txt │ │ └── lock_service │ │ │ └── CMakeLists.txt │ ├── reset │ │ ├── CMakeLists.txt │ │ └── synchronizer │ │ │ ├── CMakeLists.txt │ │ │ └── logic_reset_synchronizer_unit.sv │ ├── clock │ │ ├── CMakeLists.txt │ │ └── domain_crossing │ │ │ ├── logic_clock_domain_crossing.sdc │ │ │ ├── logic_clock_domain_crossing_generic_write_sync.sv │ │ │ ├── logic_clock_domain_crossing_generic_memory.sv │ │ │ └── CMakeLists.txt │ ├── axi4 │ │ ├── CMakeLists.txt │ │ ├── lite │ │ │ ├── bus │ │ │ │ ├── logic_axi4_lite_bus_pkg.sv │ │ │ │ └── CMakeLists.txt │ │ │ ├── CMakeLists.txt │ │ │ ├── queue │ │ │ │ └── CMakeLists.txt │ │ │ ├── buffer │ │ │ │ └── CMakeLists.txt │ │ │ ├── clock_crossing │ │ │ │ └── CMakeLists.txt │ │ │ ├── write_aligned │ │ │ │ └── CMakeLists.txt │ │ │ ├── to_avalon_mm │ │ │ │ └── CMakeLists.txt │ │ │ └── from_avalon_mm │ │ │ │ └── CMakeLists.txt │ │ └── stream │ │ │ ├── timer │ │ │ └── CMakeLists.txt │ │ │ ├── assign │ │ │ └── CMakeLists.txt │ │ │ ├── delay │ │ │ └── CMakeLists.txt │ │ │ ├── buffer │ │ │ └── CMakeLists.txt │ │ │ ├── transfer_counter │ │ │ └── CMakeLists.txt │ │ │ ├── to_avalon_st │ │ │ └── CMakeLists.txt │ │ │ ├── from_avalon_st │ │ │ └── CMakeLists.txt │ │ │ ├── queue │ │ │ └── CMakeLists.txt │ │ │ ├── resizer │ │ │ └── CMakeLists.txt │ │ │ ├── clock_crossing │ │ │ └── CMakeLists.txt │ │ │ ├── upsizer │ │ │ └── CMakeLists.txt │ │ │ ├── CMakeLists.txt │ │ │ ├── downsizer │ │ │ └── CMakeLists.txt │ │ │ ├── split │ │ │ └── CMakeLists.txt │ │ │ ├── extract │ │ │ └── CMakeLists.txt │ │ │ ├── packet_buffer │ │ │ └── CMakeLists.txt │ │ │ ├── mux │ │ │ └── CMakeLists.txt │ │ │ └── demux │ │ │ └── CMakeLists.txt │ ├── basic │ │ ├── buffer │ │ │ └── CMakeLists.txt │ │ ├── binary2gray │ │ │ ├── CMakeLists.txt │ │ │ └── logic_basic_binary2gray.sv │ │ ├── gray2binary │ │ │ ├── CMakeLists.txt │ │ │ └── logic_basic_gray2binary.sv │ │ ├── delay │ │ │ └── CMakeLists.txt │ │ ├── CMakeLists.txt │ │ ├── synchronizer │ │ │ ├── CMakeLists.txt │ │ │ ├── logic_basic_synchronizer_intel.sv │ │ │ ├── logic_basic_synchronizer_generic.sv │ │ │ └── logic_basic_synchronizer.sv │ │ └── queue │ │ │ ├── CMakeLists.txt │ │ │ ├── logic_basic_queue_generic_memory.sv │ │ │ └── logic_basic_queue_generic_write.sv │ ├── dummy │ │ └── logic_dummy.sv │ ├── include │ │ ├── logic_axi4.svh │ │ ├── logic_avalon.svh │ │ ├── logic.svh │ │ └── logic_modport.svh │ ├── packages │ │ ├── CMakeLists.txt │ │ └── logic_avalon_mm_pkg.sv │ ├── CMakeLists.txt │ └── interfaces │ │ └── CMakeLists.txt └── CMakeLists.txt ├── tests ├── logic │ ├── pll │ │ ├── CMakeLists.txt │ │ └── lock_service │ │ │ └── CMakeLists.txt │ ├── reset │ │ ├── CMakeLists.txt │ │ └── synchronizer │ │ │ ├── CMakeLists.txt │ │ │ └── logic_reset_synchronizer_unit_test.sv │ ├── axi4 │ │ ├── CMakeLists.txt │ │ ├── lite │ │ │ ├── CMakeLists.txt │ │ │ ├── bus │ │ │ │ └── CMakeLists.txt │ │ │ ├── buffer │ │ │ │ └── CMakeLists.txt │ │ │ ├── write_aligned │ │ │ │ └── CMakeLists.txt │ │ │ └── clock_crossing │ │ │ │ └── CMakeLists.txt │ │ └── stream │ │ │ ├── mux │ │ │ └── CMakeLists.txt │ │ │ ├── delay │ │ │ └── CMakeLists.txt │ │ │ ├── demux │ │ │ └── CMakeLists.txt │ │ │ ├── split │ │ │ └── CMakeLists.txt │ │ │ ├── timer │ │ │ └── CMakeLists.txt │ │ │ ├── assign │ │ │ └── CMakeLists.txt │ │ │ ├── extract │ │ │ └── CMakeLists.txt │ │ │ ├── upsizer │ │ │ └── CMakeLists.txt │ │ │ ├── downsizer │ │ │ └── CMakeLists.txt │ │ │ ├── to_avalon_st │ │ │ └── CMakeLists.txt │ │ │ ├── from_avalon_st │ │ │ └── CMakeLists.txt │ │ │ ├── CMakeLists.txt │ │ │ ├── transfer_counter │ │ │ └── CMakeLists.txt │ │ │ ├── packet_buffer │ │ │ └── CMakeLists.txt │ │ │ ├── clock_crossing │ │ │ └── CMakeLists.txt │ │ │ └── resizer │ │ │ └── CMakeLists.txt │ ├── basic │ │ ├── CMakeLists.txt │ │ ├── binary2gray │ │ │ └── CMakeLists.txt │ │ ├── gray2binary │ │ │ └── CMakeLists.txt │ │ └── synchronizer │ │ │ └── CMakeLists.txt │ ├── CMakeLists.txt │ └── packages │ │ ├── CMakeLists.txt │ │ └── logic_unit_test_pkg.sv └── CMakeLists.txt ├── cmake ├── AddQuartusProject.qpf.cmake.in ├── VerilatorConfig.cmake.in ├── AddHDL.cmake ├── ModelSim.tcl.in ├── verilator_coverage.cpp.in ├── AddHDLVivado.cmake ├── AddMsvcCompiler.cmake ├── AddQuartusProject.qsf.cmake.in ├── AddThreads.cmake ├── AddHDLQuartus.cmake ├── AddVivadoProject.tcl.cmake.in ├── verilator_callbacks.cpp ├── GetHDLDepends.cmake ├── AddHDLSystemC.cmake ├── FindStdOVL.cmake ├── AddLogic.cmake ├── FindVivado.cmake ├── SVUnitTestRunner.sv.in ├── AddHDLQsysInputs.cmake └── FindSVUnit.cmake ├── .gitlab-ci.yml ├── include └── logic │ ├── command_line.hpp │ ├── trace_base.hpp │ ├── printer │ └── json.hpp │ ├── axi4 │ └── stream │ │ ├── tx_sequencer.hpp │ │ ├── rx_sequencer.hpp │ │ ├── reset_sequencer.hpp │ │ ├── reset_if.hpp │ │ ├── sequencer.hpp │ │ ├── monitor.hpp │ │ ├── tx_sequence.hpp │ │ ├── reset_agent.hpp │ │ ├── rx_sequence.hpp │ │ ├── rx_agent.hpp │ │ ├── tx_agent.hpp │ │ ├── reset_sequence.hpp │ │ ├── reset_driver.hpp │ │ ├── test.hpp │ │ ├── tx_driver.hpp │ │ ├── testbench.hpp │ │ ├── rx_driver.hpp │ │ ├── sequence.hpp │ │ ├── reset_sequence_item.hpp │ │ └── packet.hpp │ ├── trace_systemc.hpp │ ├── bitstream_reference.hpp │ └── bitstream_const_reference.hpp ├── CMakeLists.txt └── scripts └── modelsim_run.tcl /src/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(logic) 16 | -------------------------------------------------------------------------------- /src/logic/axi4/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(stream) 16 | -------------------------------------------------------------------------------- /rtl/logic/pll/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(lock_service) 16 | -------------------------------------------------------------------------------- /rtl/logic/reset/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(synchronizer) 16 | -------------------------------------------------------------------------------- /tests/logic/pll/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(lock_service) 16 | -------------------------------------------------------------------------------- /rtl/logic/clock/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(domain_crossing) 16 | -------------------------------------------------------------------------------- /tests/logic/reset/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(synchronizer) 16 | -------------------------------------------------------------------------------- /rtl/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set(HDL_SYNTHESIZABLE TRUE) 16 | 17 | add_subdirectory(logic) 18 | -------------------------------------------------------------------------------- /rtl/logic/axi4/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(stream) 16 | add_subdirectory(lite) 17 | -------------------------------------------------------------------------------- /tests/logic/axi4/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(lite) 16 | add_subdirectory(stream) 17 | -------------------------------------------------------------------------------- /cmake/AddQuartusProject.qpf.cmake.in: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # Revisions 16 | 17 | PROJECT_REVISION = "@ARG_REVISION@" 18 | -------------------------------------------------------------------------------- /cmake/VerilatorConfig.cmake.in: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `verilator_config 17 | @verilator_config@ 18 | -------------------------------------------------------------------------------- /rtl/logic/basic/buffer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_basic_buffer.sv 16 | ANALYSIS 17 | TRUE 18 | ) 19 | -------------------------------------------------------------------------------- /rtl/logic/basic/binary2gray/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_basic_binary2gray.sv 16 | ANALYSIS 17 | TRUE 18 | ) 19 | -------------------------------------------------------------------------------- /rtl/logic/basic/gray2binary/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_basic_gray2binary.sv 16 | ANALYSIS 17 | TRUE 18 | ) 19 | -------------------------------------------------------------------------------- /tests/logic/basic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(binary2gray) 16 | add_subdirectory(gray2binary) 17 | add_subdirectory(synchronizer) 18 | -------------------------------------------------------------------------------- /rtl/logic/dummy/logic_dummy.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | /* Used only for Vim syntastic plugin */ 17 | module logic_dummy; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /rtl/logic/basic/delay/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_basic_delay.sv 16 | MODELSIM_SUPPRESS 17 | 2583 18 | ANALYSIS 19 | TRUE 20 | ) 21 | -------------------------------------------------------------------------------- /src/logic/trace_base.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/trace_base.hpp" 17 | 18 | using logic::trace_base; 19 | 20 | trace_base::~trace_base() = default; 21 | -------------------------------------------------------------------------------- /tests/logic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(packages) 16 | add_subdirectory(axi4) 17 | add_subdirectory(reset) 18 | add_subdirectory(basic) 19 | add_subdirectory(pll) 20 | -------------------------------------------------------------------------------- /tests/logic/axi4/lite/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(buffer) 16 | add_subdirectory(clock_crossing) 17 | add_subdirectory(write_aligned) 18 | add_subdirectory(bus) 19 | -------------------------------------------------------------------------------- /rtl/logic/basic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(synchronizer) 16 | add_subdirectory(binary2gray) 17 | add_subdirectory(gray2binary) 18 | add_subdirectory(buffer) 19 | add_subdirectory(delay) 20 | add_subdirectory(queue) 21 | -------------------------------------------------------------------------------- /rtl/logic/include/logic_axi4.svh: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `ifndef LOGIC_AXI4_SVH 17 | `define LOGIC_AXI4_SVH 18 | 19 | `include "logic_axi4_lite.svh" 20 | `include "logic_axi4_stream.svh" 21 | 22 | `endif /* LOGIC_AXI4_SVH */ 23 | -------------------------------------------------------------------------------- /rtl/logic/include/logic_avalon.svh: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `ifndef LOGIC_AVALON_SVH 17 | `define LOGIC_AVALON_SVH 18 | 19 | `include "logic_avalon_st.svh" 20 | `include "logic_avalon_mm.svh" 21 | 22 | `endif /* LOGIC_AVALON_SVH */ 23 | -------------------------------------------------------------------------------- /tests/logic/pll/lock_service/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_pll_lock_service_unit_test.sv 18 | DEPENDS 19 | logic_pll_lock_service 20 | MODELSIM_SUPPRESS 21 | 3009 22 | ) 23 | -------------------------------------------------------------------------------- /rtl/logic/reset/synchronizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_reset_synchronizer.sv 16 | SOURCES 17 | logic_reset_synchronizer_unit.sv 18 | ANALYSIS 19 | TRUE 20 | MODELSIM_SUPPRESS 21 | 2583 22 | ) 23 | -------------------------------------------------------------------------------- /cmake/AddHDL.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | include(GetHDLDepends) 16 | include(AddHDLSource) 17 | include(AddHDLModelSim) 18 | include(AddHDLQuartus) 19 | include(AddHDLVivado) 20 | include(AddHDLSystemC) 21 | include(AddHDLVerilator) 22 | include(AddHDLUnitTest) 23 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/bus/logic_axi4_lite_bus_pkg.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | package logic_axi4_lite_bus_pkg; 17 | typedef struct packed { 18 | bit [63:0] address_high; 19 | bit [63:0] address_low; 20 | } slave_t; 21 | endpackage 22 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(buffer) 16 | add_subdirectory(queue) 17 | add_subdirectory(write_aligned) 18 | add_subdirectory(to_avalon_mm) 19 | add_subdirectory(from_avalon_mm) 20 | add_subdirectory(clock_crossing) 21 | add_subdirectory(bus) 22 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_mux_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_mux 23 | ) 24 | -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | job1: 16 | only: 17 | - master 18 | script: 19 | - source /home/fpga/.bashrc 20 | - mkdir build && cd build 21 | - cmake -G Ninja .. 22 | - cmake --build . --target all 23 | - ctest 24 | - cmake --build . --target quartus-analysis-all 25 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/delay/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_delay_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_delay 23 | ) 24 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/demux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_demux_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_demux 23 | ) 24 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/split/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_split_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_split 23 | ) 24 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/timer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_timer_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_timer 23 | ) 24 | -------------------------------------------------------------------------------- /rtl/logic/packages/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_pkg.sv 16 | PACKAGE 17 | TRUE 18 | ) 19 | 20 | add_hdl_source(logic_axi4_lite_pkg.sv 21 | PACKAGE 22 | TRUE 23 | ) 24 | 25 | add_hdl_source(logic_avalon_mm_pkg.sv 26 | PACKAGE 27 | TRUE 28 | ) 29 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/assign/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_assign_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_assign 23 | ) 24 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/extract/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_extract_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_extract 23 | ) 24 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/upsizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_upsizer_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_upsizer 23 | ) 24 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/downsizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_downsizer_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_downsizer 23 | ) 24 | -------------------------------------------------------------------------------- /cmake/ModelSim.tcl.in: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env tclsh 2 | # Copyright 2018 Tymoteusz Blazejczyk 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | set mode -c 17 | 18 | foreach arg $argv { 19 | if {$arg eq "-c" || $arg eq "-gui" || $arg eq "-i"} { 20 | set mode "" 21 | } 22 | } 23 | 24 | exec @modelsim_simulator@ $mode @modelsim_flags@ {*}$argv @modelsim_target@ >&@stdout 25 | -------------------------------------------------------------------------------- /tests/logic/packages/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_source(logic_unit_test_pkg.sv 18 | DEPENDS 19 | logic_axi4_lite_pkg 20 | logic_axi4_lite_if 21 | logic_axi4_stream_if 22 | PACKAGE 23 | TRUE 24 | INCLUDES 25 | . 26 | ) 27 | -------------------------------------------------------------------------------- /tests/logic/axi4/lite/bus/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_lite_bus_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_lite_pkg 22 | logic_axi4_lite_if 23 | logic_axi4_lite_bus 24 | ) 25 | -------------------------------------------------------------------------------- /tests/logic/axi4/lite/buffer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_lite_buffer_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_lite_pkg 22 | logic_axi4_lite_if 23 | logic_axi4_lite_buffer 24 | ) 25 | -------------------------------------------------------------------------------- /include/logic/command_line.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_COMMAND_LINE_HPP 17 | #define LOGIC_COMMAND_LINE_HPP 18 | 19 | namespace logic { 20 | 21 | class command_line { 22 | public: 23 | command_line(int argc, char* argv[]); 24 | }; 25 | 26 | } /* namespace logic */ 27 | 28 | #endif /* LOGIC_COMMAND_LINE_HPP */ 29 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/timer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_timer.sv 16 | DEPENDS 17 | logic_axi4_stream_if 18 | ) 19 | 20 | add_hdl_source(logic_axi4_stream_timer_top.sv 21 | DEPENDS 22 | logic_axi4_stream_if 23 | logic_axi4_stream_timer 24 | ANALYSIS 25 | TRUE 26 | ) 27 | -------------------------------------------------------------------------------- /tests/logic/axi4/lite/write_aligned/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_lite_write_aligned_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_lite_pkg 22 | logic_axi4_lite_if 23 | logic_axi4_lite_write_aligned 24 | ) 25 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/to_avalon_st/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_to_avalon_st_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_avalon_st_if 23 | logic_axi4_stream_to_avalon_st 24 | ) 25 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/from_avalon_st/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_from_avalon_st_unit_test.sv 18 | DEPENDS 19 | logic_pkg 20 | logic_unit_test_pkg 21 | logic_axi4_stream_if 22 | logic_avalon_st_if 23 | logic_axi4_stream_from_avalon_st 24 | ) 25 | -------------------------------------------------------------------------------- /tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (NOT VERILATOR_FOUND) 16 | message(WARNING "Tests enabled but cannot find Verilator") 17 | return() 18 | endif() 19 | 20 | if (NOT GTEST_FOUND) 21 | message(WARNING "Tests enabled but cannot find Google Test") 22 | return() 23 | endif() 24 | 25 | set(HDL_SYNTHESIZABLE FALSE) 26 | 27 | add_subdirectory(logic) 28 | -------------------------------------------------------------------------------- /rtl/logic/pll/lock_service/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_pll_lock_service.sv 16 | SOURCES 17 | logic_pll_lock_service_unit.sv 18 | logic_pll_lock_service_main.sv 19 | DEPENDS 20 | logic_axi4_stream_if 21 | logic_axi4_stream_timer 22 | logic_reset_synchronizer 23 | ANALYSIS 24 | TRUE 25 | ) 26 | -------------------------------------------------------------------------------- /src/logic/printer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_library(logic-core-printer OBJECT 16 | json.cpp 17 | ) 18 | 19 | target_include_directories(logic-core-printer PRIVATE 20 | ${LOGIC_INCLUDE_DIR} 21 | ) 22 | 23 | target_include_directories(logic-core-printer SYSTEM PRIVATE 24 | ${SYSTEMC_INCLUDE_DIRS} 25 | ) 26 | 27 | logic_target_compile_options(logic-core-printer) 28 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/assign/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_assign.sv 16 | DEPENDS 17 | logic_axi4_stream_if 18 | MODELSIM_SUPPRESS 19 | 2583 20 | ) 21 | 22 | add_hdl_source(logic_axi4_stream_assign_top.sv 23 | DEPENDS 24 | logic_axi4_stream_if 25 | logic_axi4_stream_assign 26 | ANALYSIS 27 | TRUE 28 | ) 29 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/queue/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_lite_queue.sv 16 | DEPENDS 17 | logic_axi4_lite_if 18 | logic_basic_queue 19 | MODELSIM_SUPPRESS 20 | 2583 21 | ) 22 | 23 | add_hdl_source(logic_axi4_lite_queue_top.sv 24 | DEPENDS 25 | logic_axi4_lite_if 26 | logic_axi4_lite_queue 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/buffer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_lite_buffer.sv 16 | DEPENDS 17 | logic_axi4_lite_if 18 | logic_basic_buffer 19 | MODELSIM_SUPPRESS 20 | 2583 21 | ) 22 | 23 | add_hdl_source(logic_axi4_lite_buffer_top.sv 24 | DEPENDS 25 | logic_axi4_lite_if 26 | logic_axi4_lite_buffer 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/delay/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_delay.sv 16 | DEPENDS 17 | logic_axi4_stream_if 18 | logic_basic_delay 19 | MODELSIM_SUPPRESS 20 | 2583 21 | ) 22 | 23 | add_hdl_source(logic_axi4_stream_delay_top.sv 24 | DEPENDS 25 | logic_axi4_stream_if 26 | logic_axi4_stream_delay 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/buffer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_buffer.sv 16 | DEPENDS 17 | logic_axi4_stream_if 18 | logic_basic_buffer 19 | MODELSIM_SUPPRESS 20 | 2583 21 | ) 22 | 23 | add_hdl_source(logic_axi4_stream_buffer_top.sv 24 | DEPENDS 25 | logic_axi4_stream_if 26 | logic_axi4_stream_buffer 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/transfer_counter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_transfer_counter.sv 16 | DEPENDS 17 | logic_axi4_stream_if 18 | MODELSIM_SUPPRESS 19 | 2583 20 | ) 21 | 22 | add_hdl_source(logic_axi4_stream_transfer_counter_top.sv 23 | DEPENDS 24 | logic_axi4_stream_if 25 | logic_axi4_stream_transfer_counter 26 | ANALYSIS 27 | TRUE 28 | ) 29 | -------------------------------------------------------------------------------- /cmake/verilator_coverage.cpp.in: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "@ARG_TARGET@.h" 17 | 18 | #include "verilated.h" 19 | #include "verilated_cov.h" 20 | 21 | #include 22 | 23 | double sc_time_stamp() { 24 | return 0; 25 | } 26 | 27 | int main() { 28 | @ARG_TARGET@ top; 29 | top.eval(); 30 | top.final(); 31 | 32 | VerilatedCov::write("@ARG_TARGET@.coverage"); 33 | 34 | return EXIT_SUCCESS; 35 | } 36 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/to_avalon_st/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_to_avalon_st.sv 16 | DEPENDS 17 | logic_axi4_stream_if 18 | logic_avalon_st_if 19 | MODELSIM_SUPPRESS 20 | 2583 21 | ) 22 | 23 | add_hdl_source(logic_axi4_stream_to_avalon_st_top.sv 24 | DEPENDS 25 | logic_axi4_stream_if 26 | logic_axi4_stream_to_avalon_st 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /rtl/logic/basic/synchronizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set(vendor_depends "") 16 | 17 | if (QUARTUS_FOUND) 18 | list(APPEND vendor_depends altera_mf) 19 | endif() 20 | 21 | add_hdl_source(logic_basic_synchronizer.sv 22 | SOURCES 23 | logic_basic_synchronizer_generic.sv 24 | logic_basic_synchronizer_intel.sv 25 | DEPENDS 26 | logic_pkg 27 | ${vendor_depends} 28 | ANALYSIS 29 | TRUE 30 | ) 31 | -------------------------------------------------------------------------------- /cmake/AddHDLVivado.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (COMMAND add_hdl_vivado) 16 | return() 17 | endif() 18 | 19 | include(AddVivadoProject) 20 | 21 | function(add_hdl_vivado) 22 | get_target_property(analysis ${ARG_NAME} HDL_ANALYSIS) 23 | 24 | if (analysis MATCHES ALL OR analysis MATCHES Vivado) 25 | add_vivado_project(${ARG_NAME} 26 | DEFINES 27 | SYNTHESIS 28 | ) 29 | endif() 30 | endfunction() 31 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/clock_crossing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_lite_clock_crossing.sv 16 | DEPENDS 17 | logic_pkg 18 | logic_axi4_lite_if 19 | logic_clock_domain_crossing 20 | ) 21 | 22 | add_hdl_source(logic_axi4_lite_clock_crossing_top.sv 23 | DEPENDS 24 | logic_pkg 25 | logic_axi4_lite_if 26 | logic_axi4_lite_clock_crossing 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/from_avalon_st/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_from_avalon_st.sv 16 | DEPENDS 17 | logic_avalon_st_if 18 | logic_axi4_stream_if 19 | MODELSIM_SUPPRESS 20 | 2583 21 | ) 22 | 23 | add_hdl_source(logic_axi4_stream_from_avalon_st_top.sv 24 | DEPENDS 25 | logic_axi4_stream_if 26 | logic_axi4_stream_from_avalon_st 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /src/logic/gtest/main.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/gtest/factory.hpp" 17 | 18 | #include 19 | #include 20 | 21 | int sc_main(int argc, char* argv[]) { 22 | 23 | logic::gtest::factory::get_instance().create(); 24 | 25 | testing::InitGoogleTest(&argc, argv); 26 | int status = RUN_ALL_TESTS(); 27 | 28 | logic::gtest::factory::get_instance().destroy(); 29 | 30 | return status; 31 | } 32 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/queue/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_queue.sv 16 | DEPENDS 17 | logic_pkg 18 | logic_axi4_stream_if 19 | logic_basic_queue 20 | MODELSIM_SUPPRESS 21 | 2583 22 | ) 23 | 24 | add_hdl_source(logic_axi4_stream_queue_top.sv 25 | DEPENDS 26 | logic_pkg 27 | logic_axi4_stream_if 28 | logic_axi4_stream_queue 29 | ANALYSIS 30 | TRUE 31 | ) 32 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/resizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_resizer.sv 16 | DEPENDS 17 | logic_axi4_stream_if 18 | logic_axi4_stream_upsizer 19 | logic_axi4_stream_downsizer 20 | logic_axi4_stream_assign 21 | ) 22 | 23 | add_hdl_source(logic_axi4_stream_resizer_top.sv 24 | DEPENDS 25 | logic_axi4_stream_if 26 | logic_axi4_stream_resizer 27 | ANALYSIS 28 | TRUE 29 | ) 30 | -------------------------------------------------------------------------------- /tests/logic/packages/logic_unit_test_pkg.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | /* Package: logic_unit_test_pkg 17 | * 18 | * Logic unit test package. 19 | */ 20 | package logic_unit_test_pkg; 21 | `include "logic_avalon_st_driver_rx.svh" 22 | `include "logic_avalon_st_driver_tx.svh" 23 | `include "logic_axi4_stream_driver_rx.svh" 24 | `include "logic_axi4_stream_driver_tx.svh" 25 | `include "logic_axi4_lite_driver_slave.svh" 26 | `include "logic_axi4_lite_driver_master.svh" 27 | endpackage 28 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/write_aligned/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_lite_write_aligned.sv 16 | SOURCES 17 | logic_axi4_lite_write_aligned_main.sv 18 | DEPENDS 19 | logic_axi4_lite_if 20 | logic_reset_synchronizer 21 | logic_axi4_lite_buffer 22 | ) 23 | 24 | add_hdl_source(logic_axi4_lite_write_aligned_top.sv 25 | DEPENDS 26 | logic_axi4_lite_if 27 | logic_axi4_lite_write_aligned 28 | ANALYSIS 29 | TRUE 30 | ) 31 | -------------------------------------------------------------------------------- /cmake/AddMsvcCompiler.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (ADD_MSVC_COMPILER) 16 | return() 17 | endif() 18 | 19 | if (NOT CMAKE_CXX_COMPILER_ID MATCHES MSVC) 20 | return() 21 | endif () 22 | 23 | set(ADD_MSVC_COMPILER TRUE) 24 | 25 | set(CMAKE_CXX_FLAGS ${CMAKE_CXX_FLAGS} /std:c++latest) 26 | set(CMAKE_CXX_FLAGS ${CMAKE_CXX_FLAGS} /W4) 27 | 28 | if (WARNINGS_INTO_ERRORS) 29 | set(CMAKE_CXX_FLAGS ${CMAKE_CXX_FLAGS} /WX) 30 | endif() 31 | 32 | string(REPLACE ";" " " CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}") 33 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/clock_crossing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_clock_crossing.sv 16 | DEPENDS 17 | logic_pkg 18 | logic_axi4_stream_if 19 | logic_clock_domain_crossing 20 | MODELSIM_SUPPRESS 21 | 2583 22 | ) 23 | 24 | add_hdl_source(logic_axi4_stream_clock_crossing_top.sv 25 | DEPENDS 26 | logic_pkg 27 | logic_axi4_stream_if 28 | logic_axi4_stream_clock_crossing 29 | ANALYSIS 30 | TRUE 31 | ) 32 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/sequencer.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/sequencer.hpp" 17 | 18 | using logic::axi4::stream::sequencer; 19 | 20 | sequencer::sequencer() : 21 | sequencer("sequencer") 22 | { } 23 | 24 | sequencer::sequencer(const uvm::uvm_component_name& component_name) : 25 | uvm::uvm_sequencer<>(component_name), 26 | rx_sequencer{nullptr}, 27 | tx_sequencer{nullptr}, 28 | reset_sequencer{nullptr} 29 | { } 30 | 31 | sequencer::~sequencer() = default; 32 | -------------------------------------------------------------------------------- /cmake/AddQuartusProject.qsf.cmake.in: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set_global_assignment -name TOP_LEVEL_ENTITY @ARG_TOP_LEVEL_ENTITY@ 16 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 17 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 18 | set_global_assignment -name NUM_PARALLEL_PROCESSORS @ARG_NUM_PARALLEL_PROCESSORS@ 19 | set_global_assignment -name LAST_QUARTUS_VERSION "@QUARTUS_VERSION@ @QUARTUS_EDITION@ Edition" 20 | 21 | @quartus_assignments@ 22 | @quartus_ip_search_paths_assignment@ 23 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/rx_sequencer.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/rx_sequencer.hpp" 17 | #include "logic/axi4/stream/rx_sequence_item.hpp" 18 | 19 | using logic::axi4::stream::rx_sequencer; 20 | 21 | rx_sequencer::rx_sequencer() : 22 | rx_sequencer("rx_sequencer") 23 | { } 24 | 25 | rx_sequencer::rx_sequencer(const uvm::uvm_component_name& component_name) : 26 | uvm::uvm_sequencer(component_name) 27 | { } 28 | 29 | rx_sequencer::~rx_sequencer() = default; 30 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/tx_sequencer.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/tx_sequencer.hpp" 17 | #include "logic/axi4/stream/tx_sequence_item.hpp" 18 | 19 | using logic::axi4::stream::tx_sequencer; 20 | 21 | tx_sequencer::tx_sequencer() : 22 | tx_sequencer("tx_sequencer") 23 | { } 24 | 25 | tx_sequencer::tx_sequencer(const uvm::uvm_component_name& component_name) : 26 | uvm::uvm_sequencer(component_name) 27 | { } 28 | 29 | tx_sequencer::~tx_sequencer() = default; 30 | -------------------------------------------------------------------------------- /rtl/logic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set(HDL_DEPENDS) 16 | set(HDL_DEFINES) 17 | set(HDL_INCLUDES ${CMAKE_CURRENT_SOURCE_DIR}/include) 18 | 19 | if (STD_OVL_FOUND) 20 | set(HDL_INCLUDES ${HDL_INCLUDES} 21 | ${STD_OVL_DIR} 22 | ) 23 | 24 | set(HDL_DEFINES ${HDL_DEFINES} 25 | OVL_ASSERT_ON 26 | ) 27 | endif() 28 | 29 | add_subdirectory(packages) 30 | add_subdirectory(interfaces) 31 | add_subdirectory(reset) 32 | add_subdirectory(basic) 33 | add_subdirectory(clock) 34 | add_subdirectory(axi4) 35 | add_subdirectory(pll) 36 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/to_avalon_mm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_lite_to_avalon_mm.sv 16 | SOURCES 17 | logic_axi4_lite_to_avalon_mm_main.sv 18 | DEPENDS 19 | logic_axi4_lite_if 20 | logic_avalon_mm_if 21 | logic_reset_synchronizer 22 | logic_axi4_lite_buffer 23 | ) 24 | 25 | add_hdl_source(logic_axi4_lite_to_avalon_mm_top.sv 26 | DEPENDS 27 | logic_axi4_lite_if 28 | logic_avalon_mm_if 29 | logic_axi4_lite_to_avalon_mm 30 | ANALYSIS 31 | TRUE 32 | ) 33 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/reset_sequencer.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/reset_sequencer.hpp" 17 | #include "logic/axi4/stream/reset_sequence_item.hpp" 18 | 19 | using logic::axi4::stream::reset_sequencer; 20 | 21 | reset_sequencer::reset_sequencer() : 22 | reset_sequencer("reset_sequencer") 23 | { } 24 | 25 | reset_sequencer::reset_sequencer( 26 | const uvm::uvm_component_name& component_name) : 27 | uvm::uvm_sequencer(component_name) 28 | { } 29 | 30 | reset_sequencer::~reset_sequencer() = default; 31 | -------------------------------------------------------------------------------- /tests/logic/basic/binary2gray/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # Create SystemVerilog with SVUnit 16 | 17 | set(depends) 18 | set(defines) 19 | set(includes) 20 | 21 | if (STD_OVL_FOUND) 22 | list(APPEND depends ovl_never_unknown_async) 23 | list(APPEND defines OVL_ASSERT_ON) 24 | list(APPEND includes "${STD_OVL_DIR}") 25 | endif() 26 | 27 | add_hdl_unit_test(logic_basic_binary2gray_unit_test.sv 28 | DEPENDS 29 | ${depends} 30 | logic_basic_binary2gray 31 | INCLUDES 32 | ${includes} 33 | DEFINES 34 | ${defines} 35 | ) 36 | -------------------------------------------------------------------------------- /tests/logic/basic/gray2binary/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # Create SystemVerilog with SVUnit 16 | 17 | set(depends) 18 | set(defines) 19 | set(includes) 20 | 21 | if (STD_OVL_FOUND) 22 | list(APPEND depends ovl_never_unknown_async) 23 | list(APPEND defines OVL_ASSERT_ON) 24 | list(APPEND includes "${STD_OVL_DIR}") 25 | endif() 26 | 27 | add_hdl_unit_test(logic_basic_gray2binary_unit_test.sv 28 | DEPENDS 29 | ${depends} 30 | logic_basic_gray2binary 31 | INCLUDES 32 | ${includes} 33 | DEFINES 34 | ${defines} 35 | ) 36 | -------------------------------------------------------------------------------- /tests/logic/basic/synchronizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # Create SystemVerilog with SVUnit 16 | 17 | set(depends) 18 | set(defines) 19 | set(includes) 20 | 21 | if (STD_OVL_FOUND) 22 | list(APPEND depends ovl_never_unknown_async) 23 | list(APPEND defines OVL_ASSERT_ON) 24 | list(APPEND includes "${STD_OVL_DIR}") 25 | endif() 26 | 27 | add_hdl_unit_test(logic_basic_synchronizer_unit_test.sv 28 | DEPENDS 29 | ${depends} 30 | logic_basic_synchronizer 31 | INCLUDES 32 | ${includes} 33 | DEFINES 34 | ${defines} 35 | ) 36 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/upsizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_upsizer.sv 16 | SOURCES 17 | logic_axi4_stream_upsizer_unit.sv 18 | logic_axi4_stream_upsizer_main.sv 19 | DEPENDS 20 | logic_axi4_stream_if 21 | logic_axi4_stream_buffer 22 | logic_reset_synchronizer 23 | MODELSIM_SUPPRESS 24 | 2583 25 | ) 26 | 27 | add_hdl_source(logic_axi4_stream_upsizer_top.sv 28 | DEPENDS 29 | logic_axi4_stream_if 30 | logic_axi4_stream_upsizer 31 | ANALYSIS 32 | TRUE 33 | ) 34 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(assign) 16 | add_subdirectory(timer) 17 | add_subdirectory(buffer) 18 | add_subdirectory(delay) 19 | add_subdirectory(mux) 20 | add_subdirectory(demux) 21 | add_subdirectory(queue) 22 | add_subdirectory(to_avalon_st) 23 | add_subdirectory(from_avalon_st) 24 | add_subdirectory(clock_crossing) 25 | add_subdirectory(transfer_counter) 26 | add_subdirectory(packet_buffer) 27 | add_subdirectory(upsizer) 28 | add_subdirectory(downsizer) 29 | add_subdirectory(resizer) 30 | add_subdirectory(extract) 31 | add_subdirectory(split) 32 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/downsizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_downsizer.sv 16 | SOURCES 17 | logic_axi4_stream_downsizer_unit.sv 18 | logic_axi4_stream_downsizer_main.sv 19 | DEPENDS 20 | logic_axi4_stream_if 21 | logic_axi4_stream_buffer 22 | logic_reset_synchronizer 23 | MODELSIM_SUPPRESS 24 | 2583 25 | ) 26 | 27 | add_hdl_source(logic_axi4_stream_downsizer_top.sv 28 | DEPENDS 29 | logic_axi4_stream_if 30 | logic_axi4_stream_downsizer 31 | ANALYSIS 32 | TRUE 33 | ) 34 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_subdirectory(assign) 16 | add_subdirectory(buffer) 17 | add_subdirectory(delay) 18 | add_subdirectory(queue) 19 | add_subdirectory(clock_crossing) 20 | add_subdirectory(packet_buffer) 21 | add_subdirectory(timer) 22 | add_subdirectory(from_avalon_st) 23 | add_subdirectory(to_avalon_st) 24 | add_subdirectory(mux) 25 | add_subdirectory(demux) 26 | add_subdirectory(upsizer) 27 | add_subdirectory(downsizer) 28 | add_subdirectory(resizer) 29 | add_subdirectory(extract) 30 | add_subdirectory(split) 31 | add_subdirectory(transfer_counter) 32 | -------------------------------------------------------------------------------- /include/logic/trace_base.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_TRACE_BASE_HPP 17 | #define LOGIC_TRACE_BASE_HPP 18 | 19 | namespace logic { 20 | 21 | class trace_base { 22 | public: 23 | trace_base(trace_base&&) = delete; 24 | 25 | trace_base(const trace_base&) = delete; 26 | 27 | trace_base& operator=(trace_base&&) = delete; 28 | 29 | trace_base& operator=(const trace_base&) = delete; 30 | protected: 31 | trace_base() = default; 32 | 33 | virtual ~trace_base(); 34 | }; 35 | 36 | } /* namespace logic */ 37 | 38 | #endif /* LOGIC_TRACE_BASE_HPP */ 39 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/split/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_split.sv 16 | SOURCES 17 | logic_axi4_stream_split_unit.sv 18 | logic_axi4_stream_split_main.sv 19 | DEPENDS 20 | logic_axi4_stream_if 21 | logic_axi4_stream_buffer 22 | logic_reset_synchronizer 23 | MODELSIM_SUPPRESS 24 | 2583 25 | ) 26 | 27 | add_hdl_source(logic_axi4_stream_split_top.sv 28 | DEPENDS 29 | logic_axi4_stream_if 30 | logic_axi4_stream_split 31 | ANALYSIS 32 | TRUE 33 | MODELSIM_SUPPRESS 34 | 2583 35 | ) 36 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/from_avalon_mm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_lite_from_avalon_mm.sv 16 | SOURCES 17 | logic_axi4_lite_from_avalon_mm_main.sv 18 | logic_axi4_lite_from_avalon_mm_buffer.sv 19 | DEPENDS 20 | logic_axi4_lite_if 21 | logic_avalon_mm_if 22 | logic_basic_buffer 23 | logic_reset_synchronizer 24 | ) 25 | 26 | add_hdl_source(logic_axi4_lite_from_avalon_mm_top.sv 27 | DEPENDS 28 | logic_axi4_lite_if 29 | logic_avalon_mm_if 30 | logic_axi4_lite_from_avalon_mm 31 | ANALYSIS 32 | TRUE 33 | ) 34 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/extract/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_extract.sv 16 | SOURCES 17 | logic_axi4_stream_extract_unit.sv 18 | logic_axi4_stream_extract_main.sv 19 | DEPENDS 20 | logic_axi4_stream_if 21 | logic_axi4_stream_buffer 22 | logic_reset_synchronizer 23 | MODELSIM_SUPPRESS 24 | 2583 25 | ) 26 | 27 | add_hdl_source(logic_axi4_stream_extract_top.sv 28 | DEPENDS 29 | logic_axi4_stream_if 30 | logic_axi4_stream_extract 31 | ANALYSIS 32 | TRUE 33 | MODELSIM_SUPPRESS 34 | 2583 35 | ) 36 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/packet_buffer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_packet_buffer.sv 16 | SOURCES 17 | logic_axi4_stream_packet_buffer_main.sv 18 | logic_axi4_stream_packet_buffer_unit.sv 19 | DEPENDS 20 | logic_pkg 21 | logic_axi4_stream_if 22 | logic_axi4_stream_queue 23 | logic_axi4_stream_transfer_counter 24 | ) 25 | 26 | add_hdl_source(logic_axi4_stream_packet_buffer_top.sv 27 | DEPENDS 28 | logic_pkg 29 | logic_axi4_stream_if 30 | logic_axi4_stream_packet_buffer 31 | ANALYSIS 32 | TRUE 33 | ) 34 | -------------------------------------------------------------------------------- /cmake/AddThreads.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (THREADS_FOUND) 16 | return() 17 | endif() 18 | 19 | set(CMAKE_THREAD_PREFER_PTHREAD TRUE) 20 | set(THREADS_PREFER_PTHREAD_FLAG TRUE) 21 | find_package(Threads) 22 | 23 | if (CMAKE_USE_PTHREADS_INIT) 24 | set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -pthread") 25 | message(STATUS "Threads enabled") 26 | elseif (CMAKE_THREAD_LIBS_INIT) 27 | set(CMAKE_EXE_LINKER_FLAGS 28 | "${CMAKE_EXE_LINKER_FLAGS} ${CMAKE_THREAD_LIBS_INIT}") 29 | message(STATUS "Threads enabled") 30 | else() 31 | message(WARNING "Threads not found") 32 | set(THREADS OFF) 33 | endif() 34 | -------------------------------------------------------------------------------- /rtl/logic/clock/domain_crossing/logic_clock_domain_crossing.sdc: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # From write to read clock domain: 16 | 17 | set_false_path \ 18 | -from [get_registers {*logic_clock_domain_crossing_generic_read_sync:read_sync*gray_write_synced*}] \ 19 | -to [get_registers {*logic_clock_domain_crossing_generic_read_sync:read_sync*gray_read_synced*}] 20 | 21 | # From read to write clock domain: 22 | 23 | set_false_path \ 24 | -from [get_registers {*logic_clock_domain_crossing_generic_write_sync:write_sync*gray_write_synced*}] \ 25 | -to [get_registers {*logic_clock_domain_crossing_generic_write_sync:write_sync*gray_read_synced*}] 26 | -------------------------------------------------------------------------------- /src/logic/bitstream_const_reference.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/bitstream_const_reference.hpp" 17 | 18 | using logic::bitstream_const_reference; 19 | 20 | bitstream_const_reference::bitstream_const_reference( 21 | const bitstream_reference& other) noexcept : 22 | m_reference{other} 23 | { } 24 | 25 | bitstream_const_reference::bitstream_const_reference(const_pointer bits, 26 | size_type index) noexcept : 27 | m_reference{const_cast(bits), index} 28 | { } 29 | 30 | bitstream_const_reference::operator bool() const noexcept { 31 | return m_reference.operator bool(); 32 | } 33 | -------------------------------------------------------------------------------- /rtl/logic/include/logic.svh: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `ifndef LOGIC_SVH 17 | `define LOGIC_SVH 18 | 19 | `ifdef SYNTHESIS 20 | `ifdef OVL_ASSERT_ON 21 | `undef OVL_ASSERT_ON 22 | `endif 23 | `elsif VERILATOR 24 | /* Define: SYNTHESIS 25 | * 26 | * Enable only synthesizable parts of HDL. 27 | */ 28 | `define SYNTHESIS 29 | `endif 30 | 31 | `include "logic_drc.svh" 32 | `include "logic_axi4.svh" 33 | `include "logic_avalon.svh" 34 | `include "logic_modport.svh" 35 | 36 | `ifdef OVL_ASSERT_ON 37 | `define OVL_VERILOG 38 | `define OVL_SVA_INTERFACE 39 | `include "std_ovl_defines.h" 40 | `endif 41 | 42 | `endif /* LOGIC_SVH */ 43 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | cmake_minimum_required(VERSION 3.1) 16 | project(Logic C CXX) 17 | 18 | set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH}" "${CMAKE_CURRENT_LIST_DIR}/cmake") 19 | 20 | option(LOGIC_TESTS "Enable/disable tests" ON) 21 | option(LOGIC_RTL "Enable/disable RTL build" ON) 22 | option(LOGIC_WARNINGS_INTO_ERRORS "Enable/disable warnings as errors" OFF) 23 | 24 | include(AddLogic) 25 | 26 | set(LOGIC_INCLUDE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/include") 27 | 28 | add_subdirectory(src) 29 | 30 | if (LOGIC_RTL) 31 | add_subdirectory(rtl) 32 | 33 | if (LOGIC_TESTS) 34 | include(CTest) 35 | add_subdirectory(tests) 36 | endif() 37 | endif() 38 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_mux.sv 16 | SOURCES 17 | logic_axi4_stream_mux_unit.sv 18 | logic_axi4_stream_mux_stage.sv 19 | logic_axi4_stream_mux_main.sv 20 | DEPENDS 21 | logic_axi4_stream_if 22 | logic_axi4_stream_assign 23 | logic_axi4_stream_buffer 24 | logic_reset_synchronizer 25 | MODELSIM_SUPPRESS 26 | 2583 27 | ) 28 | 29 | add_hdl_source(logic_axi4_stream_mux_top.sv 30 | DEPENDS 31 | logic_axi4_stream_if 32 | logic_axi4_stream_mux 33 | ANALYSIS 34 | TRUE 35 | MODELSIM_SUPPRESS 36 | 2583 37 | ) 38 | -------------------------------------------------------------------------------- /rtl/logic/axi4/stream/demux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_stream_demux.sv 16 | SOURCES 17 | logic_axi4_stream_demux_unit.sv 18 | logic_axi4_stream_demux_stage.sv 19 | logic_axi4_stream_demux_main.sv 20 | DEPENDS 21 | logic_axi4_stream_if 22 | logic_axi4_stream_assign 23 | logic_axi4_stream_buffer 24 | logic_reset_synchronizer 25 | MODELSIM_SUPPRESS 26 | 2583 27 | ) 28 | 29 | add_hdl_source(logic_axi4_stream_demux_top.sv 30 | DEPENDS 31 | logic_axi4_stream_if 32 | logic_axi4_stream_demux 33 | ANALYSIS 34 | TRUE 35 | MODELSIM_SUPPRESS 36 | 2583 37 | ) 38 | -------------------------------------------------------------------------------- /cmake/AddHDLQuartus.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (COMMAND add_hdl_quartus) 16 | return() 17 | endif() 18 | 19 | include(AddQuartusProject) 20 | 21 | function(add_hdl_quartus) 22 | get_target_property(analysis ${ARG_NAME} HDL_ANALYSIS) 23 | 24 | if (analysis MATCHES ALL OR analysis MATCHES Quartus) 25 | set(quartus_defines "") 26 | 27 | list(APPEND quartus_defines SYNTHESIS) 28 | 29 | if (QUARTUS_EDITION MATCHES Pro) 30 | list(APPEND quartus_defines LOGIC_MODPORT_DISABLED) 31 | endif() 32 | 33 | add_quartus_project(${ARG_NAME} 34 | DEFINES 35 | ${quartus_defines} 36 | ) 37 | endif() 38 | endfunction() 39 | -------------------------------------------------------------------------------- /include/logic/printer/json.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_PRINTER_JSON_HPP 17 | #define LOGIC_PRINTER_JSON_HPP 18 | 19 | #include 20 | 21 | #include 22 | 23 | namespace logic { 24 | namespace printer { 25 | 26 | class json : public uvm::uvm_printer { 27 | public: 28 | json() = default; 29 | 30 | json(json&&) = default; 31 | 32 | json(const json&) = default; 33 | 34 | json& operator=(json&&) = default; 35 | 36 | json& operator=(const json&) = default; 37 | 38 | std::string emit() override; 39 | 40 | ~json() override; 41 | }; 42 | 43 | } /* namespace printer */ 44 | } /* namespace logic */ 45 | 46 | #endif /* LOGIC_PRINTER_JSON_HPP */ 47 | -------------------------------------------------------------------------------- /cmake/AddVivadoProject.tcl.cmake.in: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | create_project @ARG_TOP_LEVEL_ENTITY@ -in_memory 16 | 17 | set includes {} 18 | set defines {} 19 | set sources {} 20 | 21 | @vivado_defines_list@ 22 | 23 | @vivado_includes_list@ 24 | 25 | @vivado_sources_list@ 26 | 27 | add_files $sources 28 | 29 | set synth_arguments {} 30 | 31 | lappend synth_arguments -name @ARG_TOP_LEVEL_ENTITY@ 32 | lappend synth_arguments -top @ARG_TOP_LEVEL_ENTITY@ 33 | lappend synth_arguments -rtl 34 | 35 | foreach def $defines { 36 | lappend synth_arguments -verilog_define $def 37 | } 38 | 39 | if [llength includes] { 40 | lappend synth_arguments -include_dirs $includes 41 | } 42 | 43 | synth_design {*}$synth_arguments 44 | -------------------------------------------------------------------------------- /rtl/logic/include/logic_modport.svh: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `ifndef LOGIC_MODPORT_SVH 17 | `define LOGIC_MODPORT_SVH 18 | 19 | `ifndef LOGIC_MODPORT_DISABLED 20 | /* Define: LOGIC_MODPORT 21 | * 22 | * Define that helps to enable or disable modport feature. Useful only for Intel 23 | * Quartus Pro Prime that doesn't support modports properly. 24 | * 25 | * Parameters: 26 | * _interface - Interface name. 27 | * _modport - Modport name. 28 | */ 29 | `define LOGIC_MODPORT(_interface, _modport) \ 30 | _interface.``_modport 31 | `else 32 | `define LOGIC_MODPORT(_interface, _modport) \ 33 | _interface 34 | `endif 35 | 36 | `endif /* LOGIC_MODPORT_SVH */ 37 | -------------------------------------------------------------------------------- /cmake/verilator_callbacks.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include 17 | #include 18 | 19 | static void simulation_stop() { 20 | if (!Verilated::gotFinish()) { 21 | Verilated::flushCall(); 22 | sc_core::sc_stop(); 23 | } 24 | Verilated::gotFinish(true); 25 | } 26 | 27 | void vl_finish(const char* filename, int linenum, 28 | const char* /* hier */) VL_MT_UNSAFE { 29 | VL_PRINTF("- %s:%d: Verilog $finish\n", filename, linenum); 30 | simulation_stop(); 31 | } 32 | 33 | void vl_stop(const char* filename, int linenum, 34 | const char* /* hier */) VL_MT_UNSAFE { 35 | VL_PRINTF("- %s:%d: Verilog $stop\n", filename, linenum); 36 | simulation_stop(); 37 | } 38 | -------------------------------------------------------------------------------- /cmake/GetHDLDepends.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (COMMAND get_hdl_depends) 16 | return() 17 | endif() 18 | 19 | function(get_hdl_depends hdl_target hdl_depends_var) 20 | set(hdl_depends "") 21 | 22 | get_target_property(target_depends ${hdl_target} HDL_DEPENDS) 23 | 24 | foreach (name ${target_depends}) 25 | if (NOT TARGET ${name}) 26 | message(FATAL_ERROR "HDL target doesn't exist: ${name}") 27 | endif() 28 | 29 | get_hdl_depends(${name} depends) 30 | 31 | list(APPEND hdl_depends ${depends}) 32 | list(APPEND hdl_depends ${name}) 33 | endforeach() 34 | 35 | list(REMOVE_DUPLICATES hdl_depends) 36 | 37 | set(${hdl_depends_var} ${hdl_depends} PARENT_SCOPE) 38 | endfunction() 39 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/tx_sequencer.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_TX_SEQUENCER_HPP 17 | #define LOGIC_AXI4_STREAM_TX_SEQUENCER_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class tx_sequence_item; 26 | 27 | class tx_sequencer : public uvm::uvm_sequencer { 28 | public: 29 | UVM_COMPONENT_UTILS(logic::axi4::stream::tx_sequencer) 30 | 31 | tx_sequencer(); 32 | 33 | explicit tx_sequencer(const uvm::uvm_component_name& component_name); 34 | 35 | ~tx_sequencer() override; 36 | }; 37 | 38 | } /* namespace stream */ 39 | } /* namespace axi4 */ 40 | } /* namespace logic */ 41 | 42 | #endif /* LOGIC_AXI4_STREAM_TX_SEQUENCER_HPP */ 43 | -------------------------------------------------------------------------------- /rtl/logic/basic/gray2binary/logic_basic_gray2binary.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | /* Module: logic_basic_gray2binary 19 | * 20 | * Converts input data coded in gray codes to binary data. 21 | * 22 | * Parameters: 23 | * WIDTH - Number of bits for input and output signals. 24 | * 25 | * Ports: 26 | * i - Input gray data. 27 | * o - Output binary data. 28 | */ 29 | module logic_basic_gray2binary #( 30 | int WIDTH = 1 31 | ) ( 32 | input [WIDTH-1:0] i, 33 | output logic [WIDTH-1:0] o 34 | ); 35 | always_comb begin 36 | o[WIDTH-1] = i[WIDTH-1]; 37 | 38 | for (int k = (WIDTH - 1); k > 0; --k) begin 39 | o[k - 1] = i[k - 1] ^ o[k]; 40 | end 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /rtl/logic/basic/binary2gray/logic_basic_binary2gray.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | /* Module: logic_basic_binary2gray 19 | * 20 | * Converts input binary data to data coded in gray codes. 21 | * 22 | * Parameters: 23 | * WIDTH - Number of bits for input and output signals. 24 | * 25 | * Ports: 26 | * i - Input binary data. 27 | * o - Output gray data. 28 | */ 29 | module logic_basic_binary2gray #( 30 | int WIDTH = 1 31 | ) ( 32 | input [WIDTH-1:0] i, 33 | output logic [WIDTH-1:0] o 34 | ); 35 | always_comb begin 36 | o[WIDTH-1] = i[WIDTH-1]; 37 | 38 | for (int k = 0; k < (WIDTH - 1); ++k) begin 39 | o[k] = i[k] ^ i[k + 1]; 40 | end 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /rtl/logic/basic/queue/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set(vendor_depends "") 16 | 17 | if (QUARTUS_FOUND) 18 | list(APPEND vendor_depends altera_mf) 19 | endif() 20 | 21 | if (STD_OVL_FOUND) 22 | list(APPEND vendor_depends ovl_no_transition) 23 | endif() 24 | 25 | add_hdl_source(logic_basic_queue.sv 26 | SOURCES 27 | logic_basic_queue_generic_capacity.sv 28 | logic_basic_queue_generic_memory.sv 29 | logic_basic_queue_generic_read.sv 30 | logic_basic_queue_generic_write.sv 31 | logic_basic_queue_generic.sv 32 | logic_basic_queue_intel.sv 33 | logic_basic_queue_main.sv 34 | DEPENDS 35 | logic_pkg 36 | logic_axi4_stream_if 37 | logic_reset_synchronizer 38 | ${vendor_depends} 39 | ANALYSIS 40 | TRUE 41 | ) 42 | -------------------------------------------------------------------------------- /src/logic/command_line_argument.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef COMMAND_LINE_ARGUMENT_HPP 17 | #define COMMAND_LINE_ARGUMENT_HPP 18 | 19 | #include 20 | #include 21 | 22 | namespace logic { 23 | 24 | class command_line_argument { 25 | public: 26 | using callback = void(*)(const std::string& arg); 27 | 28 | command_line_argument(const char* argument_name, 29 | callback argument_callback) noexcept; 30 | 31 | const char* name() const noexcept; 32 | 33 | std::size_t length() const noexcept; 34 | 35 | bool match(const char* argument_name) const noexcept; 36 | 37 | void operator()(const std::string& arg) const; 38 | private: 39 | const char* m_name; 40 | callback m_callback; 41 | }; 42 | 43 | } /* namespace logic */ 44 | 45 | #endif /* COMMAND_LINE_ARGUMENT_HPP */ 46 | -------------------------------------------------------------------------------- /cmake/AddHDLSystemC.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (COMMAND add_hdl_systemc) 16 | return() 17 | endif() 18 | 19 | function(add_hdl_systemc target_name) 20 | set(one_value_arguments 21 | NAME 22 | TARGET 23 | ) 24 | 25 | set(multi_value_arguments 26 | DEFINES 27 | INCLUDES 28 | PARAMETERS 29 | VERILATOR_CONFIGURATIONS 30 | ) 31 | 32 | cmake_parse_arguments(ARG "" "${one_value_arguments}" 33 | "${multi_value_arguments}" ${ARGN}) 34 | 35 | set(ARG_COMPILE Verilator) 36 | set(ARG_ANALYSIS Verilator) 37 | set(ARG_SYNTHESIZABLE TRUE) 38 | 39 | if (NOT ARG_NAME) 40 | set(ARG_NAME ${target_name}) 41 | endif() 42 | 43 | if (NOT ARG_TARGET) 44 | set(ARG_TARGET ${target_name}) 45 | endif() 46 | 47 | add_hdl_verilator() 48 | endfunction() 49 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/transfer_counter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_transfer_counter_unit_test.sv 18 | NAME 19 | logic_axi4_stream_transfer_counter_normal_unit_test 20 | DEPENDS 21 | logic_pkg 22 | logic_unit_test_pkg 23 | logic_axi4_stream_if 24 | logic_axi4_stream_queue 25 | logic_axi4_stream_transfer_counter 26 | PARAMETERS 27 | PACKETS=0 28 | ) 29 | 30 | add_hdl_unit_test(logic_axi4_stream_transfer_counter_unit_test.sv 31 | NAME 32 | logic_axi4_stream_transfer_counter_packets_unit_test 33 | DEPENDS 34 | logic_pkg 35 | logic_unit_test_pkg 36 | logic_axi4_stream_if 37 | logic_axi4_stream_queue 38 | logic_axi4_stream_transfer_counter 39 | PARAMETERS 40 | PACKETS=1 41 | ) 42 | -------------------------------------------------------------------------------- /cmake/FindStdOVL.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | #.rst: 16 | # FindStdOVL 17 | # ---------- 18 | # 19 | # Find Open Verification Library 20 | # 21 | # :: 22 | # 23 | # STD_OVL_DIR - Open Verification Library directory 24 | 25 | if (COMMAND _find_accellera_std_ovl) 26 | return() 27 | endif() 28 | 29 | function(_find_accellera_std_ovl) 30 | find_package(PackageHandleStandardArgs REQUIRED) 31 | 32 | find_path(STD_OVL_DIR std_ovl_defines.h 33 | HINTS $ENV{STD_OVL_DIR} $ENV{STD_OVL} 34 | DOC "Path to the Open Verification Library directory" 35 | ) 36 | 37 | mark_as_advanced(STD_OVL_DIR) 38 | 39 | find_package_handle_standard_args(STD_OVL REQUIRED_VARS STD_OVL_DIR) 40 | 41 | set(STD_OVL_FOUND ${STD_OVL_FOUND} PARENT_SCOPE) 42 | set(STD_OVL_DIR "${STD_OVL_DIR}" PARENT_SCOPE) 43 | endfunction() 44 | 45 | _find_accellera_std_ovl() 46 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/reset_if.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/reset_if.hpp" 17 | 18 | using logic::axi4::stream::reset_if; 19 | 20 | reset_if::reset_if() : 21 | reset_if{""} 22 | { } 23 | 24 | reset_if::reset_if(const sc_core::sc_module_name& module_name) : 25 | sc_core::sc_module{module_name}, 26 | aclk{"aclk"}, 27 | areset_n{"areset_n"} 28 | { } 29 | 30 | void reset_if::trace(sc_core::sc_trace_file* trace_file) const { 31 | if (trace_file != nullptr) { 32 | sc_core::sc_trace(trace_file, aclk, aclk.name()); 33 | sc_core::sc_trace(trace_file, areset_n, areset_n.name()); 34 | } 35 | } 36 | 37 | void reset_if::set_areset_n(bool value) { 38 | areset_n.write(value); 39 | } 40 | 41 | void reset_if::aclk_posedge() { 42 | sc_core::wait(aclk.posedge_event()); 43 | } 44 | 45 | reset_if::~reset_if() = default; 46 | -------------------------------------------------------------------------------- /cmake/AddLogic.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | if (ADD_LOGIC_INCLUDED) 16 | return() 17 | endif() 18 | 19 | set(ADD_LOGIC_INCLUDED TRUE) 20 | 21 | include(AddThreads) 22 | include(AddGnuCompiler) 23 | include(AddMsvcCompiler) 24 | include(AddClangCompiler) 25 | include(AddVivadoProject) 26 | include(AddQuartusProject) 27 | include(AddQuartusFile) 28 | include(AddHDL) 29 | include(AddStdOVL) 30 | 31 | find_package(SVUnit) 32 | find_package(ModelSim) 33 | find_package(NaturalDocs) 34 | find_package(SystemC REQUIRED COMPONENTS SCV UVM) 35 | find_package(Verilator) 36 | find_package(Vivado) 37 | find_package(Quartus) 38 | find_package(GTest) 39 | find_package(StdOVL) 40 | 41 | include(AddQuartusSimulation) 42 | 43 | if (SVUNIT_FOUND) 44 | add_hdl_source(${SVUNIT_HDL_PACKAGE} 45 | PACKAGE TRUE 46 | SYNTHESIZABLE FALSE 47 | INCLUDES "${SVUNIT_INCLUDE_DIR}" 48 | ) 49 | endif() 50 | -------------------------------------------------------------------------------- /rtl/logic/interfaces/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set(std_ovl_depends) 16 | 17 | if (STD_OVL_FOUND) 18 | set(std_ovl_depends 19 | ovl_never_unknown 20 | ovl_win_unchange 21 | ovl_always 22 | ) 23 | endif() 24 | 25 | add_hdl_source(logic_axi4_stream_if.sv 26 | DEPENDS 27 | ${std_ovl_depends} 28 | MODELSIM_SUPPRESS 29 | 2583 30 | ) 31 | 32 | add_hdl_source(logic_axi4_lite_if.sv 33 | DEPENDS 34 | logic_axi4_lite_pkg 35 | ${std_ovl_depends} 36 | ) 37 | 38 | if (STD_OVL_FOUND) 39 | set(std_ovl_depends 40 | ovl_win_unchange 41 | ovl_always 42 | ) 43 | endif() 44 | 45 | add_hdl_source(logic_avalon_st_if.sv 46 | DEPENDS 47 | ${std_ovl_depends} 48 | MODELSIM_SUPPRESS 49 | 2583 50 | ) 51 | 52 | add_hdl_source(logic_avalon_mm_if.sv 53 | DEPENDS 54 | logic_avalon_mm_pkg 55 | ) 56 | -------------------------------------------------------------------------------- /rtl/logic/packages/logic_avalon_mm_pkg.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | /* Package: logic_avalon_mm_pkg 17 | * 18 | * Logic package. 19 | */ 20 | package logic_avalon_mm_pkg; 21 | /* Enum: response_t 22 | * 23 | * Response. 24 | * 25 | * RESPONSE_OKAY - Successful response for a transaction. 26 | * RESPONSE_RESERVED - Encoding is reserved. 27 | * RESPONSE_SLAVEERROR - Error from an endpoint slave. Indicates an 28 | * unsuccessful transaction. 29 | * RESPONSE_DECODEERROR - Indicates attempted access to an undefined 30 | * location. 31 | */ 32 | typedef enum logic [1:0] { 33 | RESPONSE_OKAY = 2'b00, 34 | RESPONSE_RESERVED = 2'b01, 35 | RESPONSE_SLAVEERROR = 2'b10, 36 | RESPONSE_DECODEERROR = 2'b11 37 | } response_t; 38 | endpackage 39 | -------------------------------------------------------------------------------- /scripts/modelsim_run.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set broken 0 16 | 17 | onfinish stop 18 | 19 | onbreak { 20 | lassign [runStatus -full] status fullstat 21 | 22 | if {$status eq "error"} { 23 | # Unexpected error, report info and force an error exit. 24 | echo "Error: $fullstat" 25 | set broken 1 26 | resume 27 | } elseif {$status eq "break"} { 28 | if {[string match "user_*" $fullstat]} { 29 | pause 30 | } else { 31 | resume 32 | } 33 | } else { 34 | resume 35 | } 36 | } 37 | 38 | log -r /* 39 | run -all 40 | 41 | if {$broken} { 42 | # Unexpected condition. Exit with bad status. 43 | quit -force -code 3 44 | } 45 | 46 | if {[find signals test_passed] != ""} { 47 | if ![exa test_passed] { 48 | quit -force -code 1 49 | } 50 | } else { 51 | quit -force -code 1 52 | } 53 | 54 | quit -force 55 | -------------------------------------------------------------------------------- /include/logic/trace_systemc.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_TRACE_SYSTEMC_HPP 17 | #define LOGIC_TRACE_SYSTEMC_HPP 18 | 19 | #include "trace_base.hpp" 20 | 21 | #include 22 | 23 | #include 24 | #include 25 | 26 | namespace logic { 27 | 28 | class trace_systemc : public trace_base { 29 | public: 30 | trace_systemc(trace_systemc&&) = delete; 31 | 32 | trace_systemc(const trace_systemc&) = delete; 33 | 34 | trace_systemc& operator=(trace_systemc&&) = delete; 35 | 36 | trace_systemc& operator=(const trace_systemc&) = delete; 37 | protected: 38 | trace_systemc(const sc_core::sc_object& object, 39 | const std::string& filename, std::size_t level); 40 | 41 | ~trace_systemc() override; 42 | private: 43 | sc_core::sc_trace_file* m_trace_file{nullptr}; 44 | }; 45 | 46 | } /* namespace logic */ 47 | 48 | #endif /* LOGIC_TRACE_SYSTEMC_HPP */ 49 | -------------------------------------------------------------------------------- /tests/logic/axi4/lite/clock_crossing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_lite_clock_crossing_unit_test.sv 18 | NAME 19 | logic_axi4_lite_clock_crossing_generic_unit_test 20 | DEPENDS 21 | logic_pkg 22 | logic_unit_test_pkg 23 | logic_axi4_lite_pkg 24 | logic_axi4_lite_if 25 | logic_axi4_lite_clock_crossing 26 | PARAMETERS 27 | TARGET=logic_pkg::TARGET_GENERIC 28 | ) 29 | 30 | if (QUARTUS_FOUND) 31 | add_hdl_unit_test(logic_axi4_lite_clock_crossing_unit_test.sv 32 | NAME 33 | logic_axi4_lite_clock_crossing_intel_unit_test 34 | DEPENDS 35 | logic_pkg 36 | logic_unit_test_pkg 37 | logic_axi4_lite_pkg 38 | logic_axi4_lite_if 39 | logic_axi4_lite_clock_crossing 40 | PARAMETERS 41 | TARGET=logic_pkg::TARGET_INTEL 42 | ) 43 | endif() 44 | -------------------------------------------------------------------------------- /rtl/logic/axi4/lite/bus/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_hdl_source(logic_axi4_lite_bus_pkg.sv 16 | PACKAGE 17 | TRUE 18 | ) 19 | 20 | add_hdl_source(logic_axi4_lite_bus.sv 21 | SOURCES 22 | logic_axi4_lite_bus_multi_slave.sv 23 | logic_axi4_lite_bus_multi_slave_decoder.sv 24 | logic_axi4_lite_bus_multi_slave_mux.sv 25 | logic_axi4_lite_bus_main.sv 26 | DEPENDS 27 | logic_axi4_stream_if 28 | logic_axi4_stream_queue 29 | logic_axi4_lite_if 30 | logic_axi4_lite_queue 31 | logic_axi4_lite_buffer 32 | logic_axi4_lite_bus_pkg 33 | logic_reset_synchronizer 34 | MODELSIM_SUPPRESS 35 | 2583 36 | ) 37 | 38 | add_hdl_source(logic_axi4_lite_bus_top.sv 39 | DEPENDS 40 | logic_axi4_lite_if 41 | logic_axi4_lite_bus_pkg 42 | logic_axi4_lite_bus 43 | ANALYSIS 44 | TRUE 45 | MODELSIM_SUPPRESS 46 | 2583 47 | ) 48 | -------------------------------------------------------------------------------- /rtl/logic/basic/queue/logic_basic_queue_generic_memory.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | module logic_basic_queue_generic_memory #( 19 | int DATA_WIDTH = 1, 20 | int ADDRESS_WIDTH = 1 21 | ) ( 22 | input aclk, 23 | input write_enable, 24 | input [DATA_WIDTH-1:0] write_data, 25 | input [ADDRESS_WIDTH-1:0] write_pointer, 26 | input read_enable, 27 | input [ADDRESS_WIDTH-1:0] read_pointer, 28 | output logic [DATA_WIDTH-1:0] read_data 29 | ); 30 | localparam MEMORY_DEPTH = 2**ADDRESS_WIDTH; 31 | 32 | logic [DATA_WIDTH-1:0] memory[0:MEMORY_DEPTH-1]; 33 | 34 | always_ff @(posedge aclk) begin 35 | if (write_enable) begin 36 | memory[write_pointer] <= write_data; 37 | end 38 | end 39 | 40 | always_ff @(posedge aclk) begin 41 | if (read_enable) begin 42 | read_data <= memory[read_pointer]; 43 | end 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/logic/clock/domain_crossing/logic_clock_domain_crossing_generic_write_sync.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | module logic_clock_domain_crossing_generic_write_sync #( 19 | int ADDRESS_WIDTH = 1, 20 | logic_pkg::target_t TARGET = logic_pkg::TARGET_GENERIC 21 | ) ( 22 | input read_aclk, 23 | input read_areset_n, 24 | input [ADDRESS_WIDTH-1:0] read_pointer, 25 | input write_aclk, 26 | input write_areset_n, 27 | output logic [ADDRESS_WIDTH-1:0] read_pointer_synced 28 | ); 29 | logic_clock_domain_crossing_generic_read_sync #( 30 | .TARGET(TARGET), 31 | .ADDRESS_WIDTH(ADDRESS_WIDTH) 32 | ) 33 | synced ( 34 | .write_aclk(read_aclk), 35 | .write_areset_n(read_areset_n), 36 | .write_pointer(read_pointer), 37 | .read_aclk(write_aclk), 38 | .read_areset_n(write_areset_n), 39 | .write_pointer_synced(read_pointer_synced) 40 | ); 41 | endmodule 42 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/packet_buffer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_packet_buffer_unit_test.sv 18 | NAME 19 | logic_axi4_stream_packet_buffer_generic_unit_test 20 | DEPENDS 21 | logic_pkg 22 | logic_unit_test_pkg 23 | logic_axi4_stream_if 24 | logic_axi4_stream_packet_buffer 25 | PARAMETERS 26 | TARGET=logic_pkg::TARGET_GENERIC 27 | ) 28 | 29 | if (QUARTUS_FOUND) 30 | add_hdl_unit_test(logic_axi4_stream_packet_buffer_unit_test.sv 31 | NAME 32 | logic_axi4_stream_packet_buffer_intel_unit_test 33 | DEPENDS 34 | logic_pkg 35 | logic_unit_test_pkg 36 | logic_axi4_stream_if 37 | logic_axi4_stream_packet_buffer 38 | PARAMETERS 39 | TARGET=logic_pkg::TARGET_INTEL 40 | MODELSIM_SUPPRESS 41 | 3009 42 | 3017 43 | 3722 44 | ) 45 | endif() 46 | -------------------------------------------------------------------------------- /tests/logic/reset/synchronizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # Create SystemVerilog with SVUnit 16 | 17 | add_hdl_unit_test(logic_reset_synchronizer_unit_test.sv 18 | DEPENDS 19 | logic_reset_synchronizer 20 | ) 21 | 22 | # Create SystemC with GTest 23 | 24 | set(hdl_name logic_reset_synchronizer) 25 | 26 | add_hdl_systemc(${hdl_name}) 27 | 28 | add_executable(${hdl_name}_test 29 | logic_reset_synchronizer_test.cpp 30 | ) 31 | 32 | set_target_properties(${hdl_name}_test PROPERTIES 33 | RUNTIME_OUTPUT_DIRECTORY 34 | "${CMAKE_BINARY_DIR}/systemc/unit_tests/${hdl_name}" 35 | ) 36 | 37 | logic_target_compile_options(${hdl_name}_test) 38 | 39 | logic_target_link_libraries(${hdl_name}_test 40 | systemc-module-${hdl_name} 41 | logic-gtest-main 42 | ) 43 | 44 | add_test( 45 | NAME 46 | ${hdl_name}_test 47 | COMMAND 48 | ${hdl_name}_test 49 | WORKING_DIRECTORY 50 | "${CMAKE_BINARY_DIR}/systemc/unit_tests/${hdl_name}" 51 | ) 52 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/clock_crossing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_clock_crossing_unit_test.sv 18 | NAME 19 | logic_axi4_stream_clock_crossing_generic_unit_test 20 | DEPENDS 21 | logic_pkg 22 | logic_unit_test_pkg 23 | logic_axi4_stream_if 24 | logic_axi4_stream_clock_crossing 25 | PARAMETERS 26 | TARGET=logic_pkg::TARGET_GENERIC 27 | ) 28 | 29 | if (QUARTUS_FOUND) 30 | add_hdl_unit_test(logic_axi4_stream_clock_crossing_unit_test.sv 31 | NAME 32 | logic_axi4_stream_clock_crossing_intel_unit_test 33 | DEPENDS 34 | logic_pkg 35 | logic_unit_test_pkg 36 | logic_axi4_stream_if 37 | logic_axi4_stream_clock_crossing 38 | PARAMETERS 39 | TARGET=logic_pkg::TARGET_INTEL 40 | MODELSIM_SUPPRESS 41 | 3009 42 | 3017 43 | 3722 44 | ) 45 | endif() 46 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/rx_sequencer.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RX_SEQUENCER_HPP 17 | #define LOGIC_AXI4_STREAM_RX_SEQUENCER_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class rx_sequence_item; 26 | 27 | class rx_sequencer : public uvm::uvm_sequencer { 28 | public: 29 | UVM_COMPONENT_UTILS(logic::axi4::stream::rx_sequencer) 30 | 31 | rx_sequencer(); 32 | 33 | explicit rx_sequencer(const uvm::uvm_component_name& component_name); 34 | 35 | rx_sequencer(rx_sequencer&&) = delete; 36 | 37 | rx_sequencer(const rx_sequencer&) = delete; 38 | 39 | rx_sequencer& operator=(rx_sequencer&&) = delete; 40 | 41 | rx_sequencer& operator=(const rx_sequencer&) = delete; 42 | 43 | ~rx_sequencer() override; 44 | }; 45 | 46 | } /* namespace stream */ 47 | } /* namespace axi4 */ 48 | } /* namespace logic */ 49 | 50 | #endif /* LOGIC_AXI4_STREAM_RX_SEQUENCER_HPP */ 51 | -------------------------------------------------------------------------------- /rtl/logic/clock/domain_crossing/logic_clock_domain_crossing_generic_memory.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | module logic_clock_domain_crossing_generic_memory #( 19 | int DATA_WIDTH = 1, 20 | int ADDRESS_WIDTH = 1 21 | ) ( 22 | input write_aclk, 23 | input write_enable, 24 | input [DATA_WIDTH-1:0] write_data, 25 | input [ADDRESS_WIDTH-1:0] write_pointer, 26 | input read_aclk, 27 | input read_enable, 28 | input [ADDRESS_WIDTH-1:0] read_pointer, 29 | output logic [DATA_WIDTH-1:0] read_data 30 | ); 31 | localparam CAPACITY = 2**ADDRESS_WIDTH; 32 | 33 | logic [DATA_WIDTH-1:0] memory[0:CAPACITY-1]; 34 | 35 | always_ff @(posedge write_aclk) begin 36 | if (write_enable) begin 37 | memory[write_pointer] <= write_data; 38 | end 39 | end 40 | 41 | always_ff @(posedge read_aclk) begin 42 | if (read_enable) begin 43 | read_data <= memory[read_pointer]; 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /src/logic/trace_verilated.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/trace_verilated.hpp" 17 | 18 | #include 19 | #include 20 | #include 21 | #include 22 | 23 | using logic::trace_verilated; 24 | 25 | trace_verilated::trace_verilated(const std::string& name, 26 | const std::string& filename) : 27 | m_trace_file{new VerilatedVcdSc}, 28 | m_filename{filename.empty() ? name : filename} 29 | { 30 | Verilated::traceEverOn(true); 31 | } 32 | 33 | trace_verilated::~trace_verilated() { 34 | m_trace_file->close(); 35 | Verilated::traceEverOn(false); 36 | delete m_trace_file; 37 | VerilatedCov::write((m_filename + ".coverage").c_str()); 38 | } 39 | 40 | auto trace_verilated::get( 41 | VerilatedVcdSc* verilated_vcd) const noexcept -> VerilatedVcdC* { 42 | return verilated_vcd; 43 | } 44 | 45 | void trace_verilated::open() { 46 | m_trace_file->open((m_filename + ".vcd").c_str()); 47 | } 48 | -------------------------------------------------------------------------------- /cmake/FindVivado.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | #.rst: 16 | # FindVivado 17 | # -------- 18 | # 19 | # Find Vivado 20 | # 21 | # :: 22 | # 23 | # VIVADO_EXECUTABLE - Vivado executable 24 | 25 | if (COMMAND _find_xilinx_vivado) 26 | return() 27 | endif() 28 | 29 | function(_find_xilinx_vivado) 30 | find_package(PackageHandleStandardArgs REQUIRED) 31 | 32 | set(VIVADO_HINTS 33 | $ENV{VIVADO_ROOTDIR} 34 | $ENV{VIVADO_HOME} 35 | $ENV{VIVADO_ROOT} 36 | $ENV{VIVADO_DIR} 37 | $ENV{VIVADO} 38 | ) 39 | 40 | find_program(VIVADO_EXECUTABLE vivado 41 | HINTS ${VIVADO_HINTS} 42 | PATH_SUFFIXES bin bin64 43 | DOC "Path to the Vivado executable" 44 | ) 45 | 46 | mark_as_advanced(VIVADO_EXECUTABLE) 47 | 48 | find_package_handle_standard_args(Vivado REQUIRED_VARS VIVADO_EXECUTABLE) 49 | 50 | set(VIVADO_EXECUTABLE "${VIVADO_EXECUTABLE}" PARENT_SCOPE) 51 | set(VIVADO_FOUND ${VIVADO_FOUND} PARENT_SCOPE) 52 | endfunction() 53 | 54 | _find_xilinx_vivado() 55 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/rx_sequence.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/rx_sequence.hpp" 17 | 18 | using logic::axi4::stream::rx_sequence; 19 | 20 | rx_sequence::rx_sequence() : 21 | rx_sequence{"rx_sequence"} 22 | { } 23 | 24 | rx_sequence::rx_sequence(const std::string& name) : 25 | uvm::uvm_sequence{name}, 26 | items{} 27 | { } 28 | 29 | rx_sequence::~rx_sequence() = default; 30 | 31 | void rx_sequence::pre_body() { 32 | if (starting_phase != nullptr) { 33 | starting_phase->raise_objection(this); 34 | } 35 | } 36 | 37 | void rx_sequence::body() { 38 | UVM_INFO(get_name(), "Starting sequence", uvm::UVM_FULL); 39 | 40 | for (auto& item : items) { 41 | start_item(&item); 42 | finish_item(&item); 43 | } 44 | 45 | UVM_INFO(get_name(), "Finishing sequence", uvm::UVM_FULL); 46 | } 47 | 48 | void rx_sequence::post_body() { 49 | if (starting_phase != nullptr) { 50 | starting_phase->drop_objection(this); 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/tx_sequence.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/tx_sequence.hpp" 17 | 18 | using logic::axi4::stream::tx_sequence; 19 | 20 | tx_sequence::tx_sequence() : 21 | tx_sequence{"tx_sequence"} 22 | { } 23 | 24 | tx_sequence::tx_sequence(const std::string& name) : 25 | uvm::uvm_sequence{name}, 26 | items{} 27 | { } 28 | 29 | tx_sequence::~tx_sequence() = default; 30 | 31 | void tx_sequence::pre_body() { 32 | if (starting_phase != nullptr) { 33 | starting_phase->raise_objection(this); 34 | } 35 | } 36 | 37 | void tx_sequence::body() { 38 | UVM_INFO(get_name(), "Starting sequence", uvm::UVM_FULL); 39 | 40 | for (auto& item : items) { 41 | start_item(&item); 42 | finish_item(&item); 43 | } 44 | 45 | UVM_INFO(get_name(), "Finishing sequence", uvm::UVM_FULL); 46 | } 47 | 48 | void tx_sequence::post_body() { 49 | if (starting_phase != nullptr) { 50 | starting_phase->drop_objection(this); 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/reset_sequencer.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RESET_SEQUENCER_HPP 17 | #define LOGIC_AXI4_STREAM_RESET_SEQUENCER_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class reset_sequence_item; 26 | 27 | class reset_sequencer : public uvm::uvm_sequencer { 28 | public: 29 | UVM_COMPONENT_UTILS(logic::axi4::stream::reset_sequencer) 30 | 31 | reset_sequencer(); 32 | 33 | explicit reset_sequencer(const uvm::uvm_component_name& component_name); 34 | 35 | reset_sequencer(reset_sequencer&&) = delete; 36 | 37 | reset_sequencer(const reset_sequencer&) = delete; 38 | 39 | reset_sequencer& operator=(reset_sequencer&&) = delete; 40 | 41 | reset_sequencer& operator=(const reset_sequencer&) = delete; 42 | 43 | ~reset_sequencer() override; 44 | }; 45 | 46 | } /* namespace stream */ 47 | } /* namespace axi4 */ 48 | } /* namespace logic */ 49 | 50 | #endif /* LOGIC_AXI4_STREAM_RESET_SEQUENCER_HPP */ 51 | -------------------------------------------------------------------------------- /src/logic/bitstream_reference.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/bitstream_reference.hpp" 17 | 18 | #include 19 | 20 | using logic::bitstream_reference; 21 | 22 | static constexpr bitstream_reference::size_type BITS{8}; 23 | 24 | bitstream_reference::bitstream_reference(pointer bits, 25 | size_type index) noexcept : 26 | m_bits{bits}, 27 | m_index{index} 28 | { } 29 | 30 | auto bitstream_reference::operator=( 31 | bool value) noexcept -> bitstream_reference& { 32 | auto mask = std::uint8_t(1 << (m_index % BITS)); 33 | auto data = static_cast(m_bits) + (m_index / BITS); 34 | 35 | if (value) { 36 | *data |= mask; 37 | } 38 | else { 39 | *data &= std::uint8_t(~mask); 40 | } 41 | 42 | return *this; 43 | } 44 | 45 | bitstream_reference::operator bool() const noexcept { 46 | auto mask = std::uint8_t(1 << (m_index % BITS)); 47 | auto data = static_cast(m_bits) + (m_index / BITS); 48 | 49 | return (*data & mask) == mask; 50 | } 51 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/reset_if.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RESET_IF_HPP 17 | #define LOGIC_AXI4_STREAM_RESET_IF_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class reset_if : public sc_core::sc_module { 26 | public: 27 | sc_core::sc_in aclk; 28 | sc_core::sc_out areset_n; 29 | 30 | reset_if(); 31 | 32 | explicit reset_if(const sc_core::sc_module_name& module_name); 33 | 34 | void trace(sc_core::sc_trace_file* trace_file) const override; 35 | 36 | void set_areset_n(bool value); 37 | 38 | void aclk_posedge(); 39 | 40 | reset_if(reset_if&&) = delete; 41 | 42 | reset_if(const reset_if& other) = delete; 43 | 44 | reset_if& operator=(reset_if&&) = delete; 45 | 46 | reset_if& operator=(const reset_if& other) = delete; 47 | 48 | ~reset_if() override; 49 | }; 50 | 51 | } /* namespace stream */ 52 | } /* namespace axi4 */ 53 | } /* namespace logic */ 54 | 55 | #endif /* LOGIC_AXI4_STREAM_RESET_IF_HPP */ 56 | -------------------------------------------------------------------------------- /rtl/logic/clock/domain_crossing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set(vendor_depends "") 16 | 17 | if (QUARTUS_FOUND) 18 | list(APPEND vendor_depends altera_mf) 19 | endif() 20 | 21 | if (STD_OVL_FOUND) 22 | list(APPEND vendor_depends ovl_no_transition) 23 | endif() 24 | 25 | add_hdl_source(logic_clock_domain_crossing.sv 26 | SOURCES 27 | logic_clock_domain_crossing_intel.sv 28 | logic_clock_domain_crossing_generic_memory.sv 29 | logic_clock_domain_crossing_generic_write_sync.sv 30 | logic_clock_domain_crossing_generic_write.sv 31 | logic_clock_domain_crossing_generic_read.sv 32 | logic_clock_domain_crossing_generic_read_sync.sv 33 | logic_clock_domain_crossing_generic.sv 34 | DEPENDS 35 | logic_pkg 36 | logic_axi4_stream_if 37 | logic_reset_synchronizer 38 | logic_basic_synchronizer 39 | logic_basic_gray2binary 40 | logic_basic_binary2gray 41 | ${vendor_depends} 42 | ANALYSIS 43 | TRUE 44 | QUARTUS_SDC_FILES 45 | logic_clock_domain_crossing.sdc 46 | ) 47 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/reset_sequence.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/axi4/stream/reset_sequence.hpp" 17 | 18 | using logic::axi4::stream::reset_sequence; 19 | 20 | reset_sequence::reset_sequence() : 21 | reset_sequence{"reset_sequence"} 22 | { } 23 | 24 | reset_sequence::reset_sequence(const std::string& name) : 25 | uvm::uvm_sequence{name}, 26 | items{} 27 | { } 28 | 29 | reset_sequence::~reset_sequence() = default; 30 | 31 | void reset_sequence::pre_body() { 32 | if (starting_phase != nullptr) { 33 | starting_phase->raise_objection(this); 34 | } 35 | } 36 | 37 | void reset_sequence::body() { 38 | UVM_INFO(get_name(), "Starting reset sequence", uvm::UVM_FULL); 39 | 40 | for (auto& item : items) { 41 | start_item(&item); 42 | finish_item(&item); 43 | } 44 | 45 | UVM_INFO(get_name(), "Finishing reset sequence", uvm::UVM_FULL); 46 | } 47 | 48 | void reset_sequence::post_body() { 49 | if (starting_phase != nullptr) { 50 | starting_phase->drop_objection(this); 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /include/logic/bitstream_reference.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_BITSTREAM_REFERENCE_HPP 17 | #define LOGIC_BITSTREAM_REFERENCE_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | 23 | class bitstream_reference { 24 | public: 25 | using size_type = std::size_t; 26 | using pointer = void*; 27 | 28 | bitstream_reference(pointer bits, size_type index) noexcept; 29 | 30 | bitstream_reference(bitstream_reference&& other) noexcept = default; 31 | 32 | bitstream_reference(const bitstream_reference& other) noexcept = default; 33 | 34 | bitstream_reference& operator=( 35 | bitstream_reference&& other) noexcept = default; 36 | 37 | bitstream_reference& operator=( 38 | const bitstream_reference& other) noexcept = default; 39 | 40 | bitstream_reference& operator=(bool value) noexcept; 41 | 42 | explicit operator bool() const noexcept; 43 | 44 | ~bitstream_reference() = default; 45 | private: 46 | pointer m_bits; 47 | size_type m_index; 48 | }; 49 | 50 | } /* namespace logic */ 51 | 52 | #endif /* LOGIC_BITSTREAM_REFERENCE_HPP */ 53 | -------------------------------------------------------------------------------- /rtl/logic/basic/synchronizer/logic_basic_synchronizer_intel.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | /* Module: logic_basic_synchronizer_intel 19 | * 20 | * Synchronize input signal to clock. 21 | * 22 | * Parameters: 23 | * WIDTH - Number of bits for input and output signals. 24 | * STAGES - Number of pipeline stages from input to output. 25 | */ 26 | module logic_basic_synchronizer_intel #( 27 | int WIDTH = 1, 28 | int STAGES = 2 29 | ) ( 30 | input aclk, 31 | input areset_n, 32 | input [WIDTH-1:0] i, 33 | output logic [WIDTH-1:0] o 34 | ); 35 | genvar k; 36 | 37 | generate 38 | for (k = 0; k < WIDTH; ++k) begin: width 39 | /* verilator lint_off DECLFILENAME */ 40 | altera_std_synchronizer #( 41 | .depth(STAGES) 42 | ) 43 | synchronizer ( 44 | .clk(aclk), 45 | .reset_n(areset_n), 46 | .din(i[k]), 47 | .dout(o[k]) 48 | ); 49 | /* verilator lint_on DECLFILENAME */ 50 | end 51 | endgenerate 52 | endmodule 53 | -------------------------------------------------------------------------------- /tests/logic/axi4/stream/resizer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # SVUnit unit test 16 | 17 | add_hdl_unit_test(logic_axi4_stream_resizer_unit_test.sv 18 | NAME 19 | logic_axi4_stream_resizer_equal_unit_test 20 | DEPENDS 21 | logic_pkg 22 | logic_unit_test_pkg 23 | logic_axi4_stream_if 24 | logic_axi4_stream_resizer 25 | PARAMETERS 26 | RX_TDATA_BYTES=4 27 | TX_TDATA_BYTES=4 28 | ) 29 | 30 | add_hdl_unit_test(logic_axi4_stream_resizer_unit_test.sv 31 | NAME 32 | logic_axi4_stream_resizer_up_unit_test 33 | DEPENDS 34 | logic_pkg 35 | logic_unit_test_pkg 36 | logic_axi4_stream_if 37 | logic_axi4_stream_resizer 38 | PARAMETERS 39 | RX_TDATA_BYTES=4 40 | TX_TDATA_BYTES=12 41 | ) 42 | 43 | add_hdl_unit_test(logic_axi4_stream_resizer_unit_test.sv 44 | NAME 45 | logic_axi4_stream_resizer_down_unit_test 46 | DEPENDS 47 | logic_pkg 48 | logic_unit_test_pkg 49 | logic_axi4_stream_if 50 | logic_axi4_stream_resizer 51 | PARAMETERS 52 | RX_TDATA_BYTES=12 53 | TX_TDATA_BYTES=4 54 | ) 55 | -------------------------------------------------------------------------------- /cmake/SVUnitTestRunner.sv.in: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | module @ARG_NAME@_runner; 17 | logic test_passed = 0; 18 | 19 | import svunit_pkg::svunit_testrunner; 20 | import svunit_pkg::svunit_testsuite; 21 | 22 | svunit_testrunner svunit_tr; 23 | svunit_testsuite svunit_ts; 24 | 25 | @ARG_UNIT_TEST_NAME@ ut(); 26 | 27 | initial begin 28 | build(); 29 | run(); 30 | 31 | unique case (svunit_tr.get_results()) 32 | svunit_pkg::PASS: begin 33 | test_passed = 1; 34 | $finish; 35 | end 36 | svunit_pkg::FAIL: begin 37 | test_passed = 0; 38 | $fatal(1); 39 | end 40 | endcase 41 | end 42 | 43 | function void build(); 44 | svunit_tr = new ("testrunner"); 45 | svunit_ts = new ("testsuite"); 46 | 47 | ut.build(); 48 | svunit_ts.add_testcase(ut.svunit_ut); 49 | svunit_tr.add_testsuite(svunit_ts); 50 | endfunction 51 | 52 | task run(); 53 | svunit_ts.run(); 54 | ut.run(); 55 | svunit_ts.report(); 56 | svunit_tr.report(); 57 | endtask 58 | endmodule 59 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/sequencer.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_SEQUENCER_HPP 17 | #define LOGIC_AXI4_STREAM_SEQUENCER_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class rx_sequencer; 26 | class tx_sequencer; 27 | class reset_sequencer; 28 | 29 | class sequencer : public uvm::uvm_sequencer<> { 30 | public: 31 | UVM_COMPONENT_UTILS(logic::axi4::stream::sequencer) 32 | 33 | logic::axi4::stream::rx_sequencer* rx_sequencer; 34 | logic::axi4::stream::tx_sequencer* tx_sequencer; 35 | logic::axi4::stream::reset_sequencer* reset_sequencer; 36 | 37 | sequencer(); 38 | 39 | explicit sequencer(const uvm::uvm_component_name& component_name); 40 | 41 | sequencer(sequencer&&) = delete; 42 | 43 | sequencer(const sequencer&) = delete; 44 | 45 | sequencer& operator=(sequencer&&) = delete; 46 | 47 | sequencer& operator=(const sequencer&) = delete; 48 | 49 | ~sequencer() override; 50 | }; 51 | 52 | } /* namespace stream */ 53 | } /* namespace axi4 */ 54 | } /* namespace logic */ 55 | 56 | #endif /* LOGIC_AXI4_STREAM_SEQUENCER_HPP */ 57 | -------------------------------------------------------------------------------- /rtl/logic/reset/synchronizer/logic_reset_synchronizer_unit.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | /* Module: logic_reset_synchronizer_unit 19 | * 20 | * Synchronize asynchronous reset de-assertion to clock. 21 | * 22 | * Parameters: 23 | * STAGES - Number of registers used for reset synchronization. 24 | * 25 | * Ports: 26 | * aclk - Clock. 27 | * areset_n - Asynchronous active-low reset. 28 | * areset_n_synced - Asynchronous reset assertion. 29 | * Synchronous reset de-assertion. 30 | */ 31 | module logic_reset_synchronizer_unit #( 32 | int STAGES = 2 33 | ) ( 34 | input aclk, 35 | input areset_n, 36 | output logic areset_n_synced 37 | ); 38 | initial begin: design_rule_checks 39 | `LOGIC_DRC_EQUAL_OR_GREATER_THAN(STAGES, 2) 40 | end 41 | 42 | logic [STAGES-1:0] q; 43 | 44 | always_ff @(posedge aclk or negedge areset_n) begin 45 | if (!areset_n) begin 46 | q <= '0; 47 | end 48 | else begin 49 | q <= {1'b1, q[STAGES-1:1]}; 50 | end 51 | end 52 | 53 | always_comb areset_n_synced = q[0]; 54 | endmodule 55 | -------------------------------------------------------------------------------- /cmake/AddHDLQsysInputs.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | set(INPUT_FILES "" CACHE STRING "Input files") 16 | set(OUTPUT_DIRECTORY "." CACHE STRING "Output directory") 17 | 18 | get_filename_component(output_directory "${OUTPUT_DIRECTORY}" REALPATH) 19 | 20 | foreach (input_file ${INPUT_FILES}) 21 | get_filename_component(input_file "${input_file}" REALPATH) 22 | 23 | file(READ "${input_file}" input_context) 24 | string(REGEX REPLACE "\n" ";" input_list "${input_context}") 25 | 26 | foreach (input ${input_list}) 27 | get_filename_component(name "${input}" NAME) 28 | 29 | if (UNIX) 30 | execute_process( 31 | COMMAND 32 | ${CMAKE_COMMAND} -E create_symlink "${input}" "${name}" 33 | WORKING_DIRECTORY 34 | "${output_directory}" 35 | OUTPUT_QUIET 36 | ) 37 | else() 38 | execute_process( 39 | COMMAND 40 | ${CMAKE_COMMAND} -E copy "${input}" "${name}" 41 | WORKING_DIRECTORY 42 | "${output_directory}" 43 | OUTPUT_QUIET 44 | ) 45 | endif() 46 | endforeach() 47 | endforeach() 48 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/monitor.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_MONITOR_HPP 17 | #define LOGIC_AXI4_STREAM_MONITOR_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class packet; 26 | class bus_if_base; 27 | 28 | class monitor : public uvm::uvm_monitor { 29 | public: 30 | UVM_COMPONENT_UTILS(logic::axi4::stream::monitor) 31 | 32 | monitor(); 33 | 34 | explicit monitor(const uvm::uvm_component_name& component_name); 35 | 36 | monitor(monitor&&) = delete; 37 | 38 | monitor(const monitor&) = delete; 39 | 40 | monitor& operator=(monitor&&) = delete; 41 | 42 | monitor& operator=(const monitor&) = delete; 43 | 44 | ~monitor() override; 45 | 46 | uvm::uvm_analysis_port analysis_port; 47 | protected: 48 | void build_phase(uvm::uvm_phase& phase) override; 49 | 50 | [[noreturn]] void run_phase(uvm::uvm_phase& phase) override; 51 | 52 | bus_if_base* m_vif; 53 | bool m_checks_enable; 54 | bool m_coverage_enable; 55 | }; 56 | 57 | } /* namespace stream */ 58 | } /* namespace axi4 */ 59 | } /* namespace logic */ 60 | 61 | #endif /* LOGIC_AXI4_STREAM_MONITOR_HPP */ 62 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/tx_sequence.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_TX_SEQUENCE_HPP 17 | #define LOGIC_AXI4_STREAM_TX_SEQUENCE_HPP 18 | 19 | #include "logic/axi4/stream/tx_sequence_item.hpp" 20 | 21 | #include 22 | 23 | #include 24 | #include 25 | 26 | namespace logic { 27 | namespace axi4 { 28 | namespace stream { 29 | 30 | class tx_sequence : public uvm::uvm_sequence { 31 | public: 32 | UVM_OBJECT_UTILS(logic::axi4::stream::tx_sequence) 33 | 34 | std::vector items; 35 | 36 | tx_sequence(); 37 | 38 | explicit tx_sequence(const std::string& name); 39 | 40 | tx_sequence(tx_sequence&&) = delete; 41 | 42 | tx_sequence(const tx_sequence&) = delete; 43 | 44 | tx_sequence& operator=(tx_sequence&&) = delete; 45 | 46 | tx_sequence& operator=(const tx_sequence&) = delete; 47 | 48 | ~tx_sequence() override; 49 | protected: 50 | void pre_body() override; 51 | 52 | void body() override; 53 | 54 | void post_body() override; 55 | }; 56 | 57 | } /* namespace stream */ 58 | } /* namespace axi4 */ 59 | } /* namespace logic */ 60 | 61 | #endif /* LOGIC_AXI4_STREAM_TX_SEQUENCE_HPP */ 62 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/reset_agent.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RESET_AGENT_HPP 17 | #define LOGIC_AXI4_STREAM_RESET_AGENT_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class packet; 26 | class reset_driver; 27 | class reset_sequencer; 28 | 29 | class reset_agent : public uvm::uvm_agent { 30 | public: 31 | UVM_COMPONENT_UTILS(logic::axi4::stream::reset_agent) 32 | 33 | reset_sequencer* sequencer; 34 | 35 | reset_agent(); 36 | 37 | explicit reset_agent(const uvm::uvm_component_name& component_name); 38 | 39 | reset_agent(reset_agent&&) = delete; 40 | 41 | reset_agent(const reset_agent&) = delete; 42 | 43 | reset_agent& operator=(reset_agent&&) = delete; 44 | 45 | reset_agent& operator=(const reset_agent&) = delete; 46 | 47 | ~reset_agent() override; 48 | protected: 49 | void build_phase(uvm::uvm_phase& phase) override; 50 | 51 | void connect_phase(uvm::uvm_phase& phase) override; 52 | 53 | reset_driver* m_driver; 54 | }; 55 | 56 | } /* namespace stream */ 57 | } /* namespace axi4 */ 58 | } /* namespace logic */ 59 | 60 | #endif /* LOGIC_AXI4_STREAM_RESET_AGENT_HPP */ 61 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/rx_sequence.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RX_SEQUENCE_HPP 17 | #define LOGIC_AXI4_STREAM_RX_SEQUENCE_HPP 18 | 19 | #include "logic/range.hpp" 20 | #include "rx_sequence_item.hpp" 21 | 22 | #include 23 | 24 | #include 25 | #include 26 | 27 | namespace logic { 28 | namespace axi4 { 29 | namespace stream { 30 | 31 | class rx_sequence : public uvm::uvm_sequence { 32 | public: 33 | UVM_OBJECT_UTILS(logic::axi4::stream::rx_sequence) 34 | 35 | std::vector items; 36 | 37 | rx_sequence(); 38 | 39 | explicit rx_sequence(const std::string& name); 40 | 41 | rx_sequence(rx_sequence&&) = delete; 42 | 43 | rx_sequence(const rx_sequence& other) = delete; 44 | 45 | rx_sequence& operator=(rx_sequence&&) = delete; 46 | 47 | rx_sequence& operator=(const rx_sequence& other) = delete; 48 | 49 | ~rx_sequence() override; 50 | protected: 51 | void pre_body() override; 52 | 53 | void body() override; 54 | 55 | void post_body() override; 56 | }; 57 | 58 | } /* namespace stream */ 59 | } /* namespace axi4 */ 60 | } /* namespace logic */ 61 | 62 | #endif /* LOGIC_AXI4_STREAM_RX_SEQUENCE_HPP */ 63 | -------------------------------------------------------------------------------- /src/logic/axi4/stream/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | add_library(logic-axi4-stream OBJECT 16 | bus_if_base.cpp 17 | monitor.cpp 18 | packet.cpp 19 | reset_agent.cpp 20 | reset_driver.cpp 21 | reset_if.cpp 22 | reset_sequence.cpp 23 | reset_sequence_item.cpp 24 | reset_sequencer.cpp 25 | rx_agent.cpp 26 | rx_driver.cpp 27 | rx_sequence.cpp 28 | rx_sequence_item.cpp 29 | rx_sequencer.cpp 30 | scoreboard.cpp 31 | sequence.cpp 32 | sequencer.cpp 33 | tdata_byte.cpp 34 | test.cpp 35 | testbench.cpp 36 | tx_agent.cpp 37 | tx_driver.cpp 38 | tx_sequence.cpp 39 | tx_sequence_item.cpp 40 | tx_sequencer.cpp 41 | ) 42 | 43 | target_include_directories(logic-axi4-stream PRIVATE 44 | ${LOGIC_INCLUDE_DIR} 45 | ) 46 | 47 | target_include_directories(logic-axi4-stream SYSTEM PRIVATE 48 | ${SYSTEMC_INCLUDE_DIRS} 49 | ) 50 | 51 | set(compile_options "") 52 | 53 | if (CMAKE_CXX_COMPILER_ID MATCHES Clang) 54 | if (NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 3.9) 55 | list(APPEND compile_options 56 | -Wno-undefined-func-template 57 | ) 58 | endif() 59 | endif() 60 | 61 | logic_target_compile_options(logic-axi4-stream ${compile_options}) 62 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/rx_agent.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RX_AGENT_HPP 17 | #define LOGIC_AXI4_STREAM_RX_AGENT_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class packet; 26 | class monitor; 27 | class rx_driver; 28 | class rx_sequencer; 29 | 30 | class rx_agent : public uvm::uvm_agent { 31 | public: 32 | UVM_COMPONENT_UTILS(logic::axi4::stream::rx_agent) 33 | 34 | rx_agent(); 35 | 36 | explicit rx_agent(const uvm::uvm_component_name& component_name); 37 | 38 | rx_agent(rx_agent&&) = delete; 39 | 40 | rx_agent(const rx_agent&) = delete; 41 | 42 | rx_agent& operator=(rx_agent&&) = delete; 43 | 44 | rx_agent& operator=(const rx_agent&) = delete; 45 | 46 | ~rx_agent() override; 47 | 48 | uvm::uvm_analysis_port analysis_port; 49 | rx_sequencer* sequencer; 50 | protected: 51 | void build_phase(uvm::uvm_phase& phase) override; 52 | 53 | void connect_phase(uvm::uvm_phase& phase) override; 54 | 55 | monitor* m_monitor; 56 | rx_driver* m_driver; 57 | }; 58 | 59 | } /* namespace stream */ 60 | } /* namespace axi4 */ 61 | } /* namespace logic */ 62 | 63 | #endif /* LOGIC_AXI4_STREAM_RX_AGENT_HPP */ 64 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/tx_agent.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_TX_AGENT_HPP 17 | #define LOGIC_AXI4_STREAM_TX_AGENT_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class packet; 26 | class monitor; 27 | class tx_driver; 28 | class tx_sequencer; 29 | 30 | class tx_agent : public uvm::uvm_agent { 31 | public: 32 | UVM_COMPONENT_UTILS(logic::axi4::stream::tx_agent) 33 | 34 | tx_agent(); 35 | 36 | explicit tx_agent(const uvm::uvm_component_name& component_name); 37 | 38 | tx_agent(tx_agent&&) = delete; 39 | 40 | tx_agent(const tx_agent&) = delete; 41 | 42 | tx_agent& operator=(tx_agent&&) = delete; 43 | 44 | tx_agent& operator=(const tx_agent&) = delete; 45 | 46 | ~tx_agent() override; 47 | 48 | uvm::uvm_analysis_port analysis_port; 49 | tx_sequencer* sequencer; 50 | protected: 51 | void build_phase(uvm::uvm_phase& phase) override; 52 | 53 | void connect_phase(uvm::uvm_phase& phase) override; 54 | 55 | monitor* m_monitor; 56 | tx_driver* m_driver; 57 | }; 58 | 59 | } /* namespace stream */ 60 | } /* namespace axi4 */ 61 | } /* namespace logic */ 62 | 63 | #endif /* LOGIC_AXI4_STREAM_TX_AGENT_HPP */ 64 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/reset_sequence.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RESET_SEQUENCE_HPP 17 | #define LOGIC_AXI4_STREAM_RESET_SEQUENCE_HPP 18 | 19 | #include "reset_sequence_item.hpp" 20 | 21 | #include 22 | 23 | #include 24 | #include 25 | 26 | namespace logic { 27 | namespace axi4 { 28 | namespace stream { 29 | 30 | class reset_sequence : public uvm::uvm_sequence { 31 | public: 32 | UVM_OBJECT_UTILS(logic::axi4::stream::reset_sequence) 33 | 34 | std::vector items; 35 | 36 | reset_sequence(); 37 | 38 | explicit reset_sequence(const std::string& name); 39 | 40 | reset_sequence(reset_sequence&&) = delete; 41 | 42 | reset_sequence(const reset_sequence& other) = delete; 43 | 44 | reset_sequence& operator=(reset_sequence&&) = delete; 45 | 46 | reset_sequence& operator=(const reset_sequence& other) = delete; 47 | 48 | ~reset_sequence() override; 49 | protected: 50 | void pre_body() override; 51 | 52 | void body() override; 53 | 54 | void post_body() override; 55 | }; 56 | 57 | } /* namespace stream */ 58 | } /* namespace axi4 */ 59 | } /* namespace logic */ 60 | 61 | #endif /* LOGIC_AXI4_STREAM_RESET_SEQUENCE_HPP */ 62 | -------------------------------------------------------------------------------- /src/logic/command_line_argument.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "command_line_argument.hpp" 17 | 18 | using logic::command_line_argument; 19 | 20 | command_line_argument::command_line_argument(const char* argument_name, 21 | callback argument_callback) noexcept : 22 | m_name{argument_name}, 23 | m_callback{argument_callback} 24 | { } 25 | 26 | auto command_line_argument::name() const noexcept -> const char* { 27 | return m_name; 28 | } 29 | 30 | auto command_line_argument::length() const noexcept -> std::size_t { 31 | std::size_t count{0u}; 32 | 33 | if (m_name != nullptr) { 34 | auto it = m_name; 35 | 36 | while (*it++ != '\0') { 37 | ++count; 38 | } 39 | } 40 | 41 | return count; 42 | } 43 | 44 | bool command_line_argument::match(const char* argument_name) const noexcept { 45 | bool ok{false}; 46 | 47 | if ((m_name != nullptr) && (argument_name != nullptr)) { 48 | auto it = m_name; 49 | 50 | ok = true; 51 | while (ok && (*it != '\0')) { 52 | ok = ((*it++) == (*argument_name++)); 53 | } 54 | } 55 | 56 | return ok; 57 | } 58 | 59 | void command_line_argument::operator()(const std::string& arg) const { 60 | m_callback(arg); 61 | } 62 | -------------------------------------------------------------------------------- /cmake/FindSVUnit.cmake: -------------------------------------------------------------------------------- 1 | # Copyright 2018 Tymoteusz Blazejczyk 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | #.rst: 16 | # FindSVUnit 17 | # -------- 18 | # 19 | # Find SVUnit 20 | # 21 | # :: 22 | # 23 | # SVUNIT_HDL_PACKAGE - SVUnit SystemVerilog package 24 | # SVUNIT_INCLUDE_DIR - SVUnit include directory 25 | # SVUNIT_FOUND - true if SVUnit found 26 | 27 | if (COMMAND _find_svunit) 28 | return() 29 | endif() 30 | 31 | function(_find_svunit) 32 | find_package(PackageHandleStandardArgs REQUIRED) 33 | 34 | find_path(SVUNIT_HDL_SOURCES_DIR svunit_base.sv 35 | HINTS $ENV{SVUNIT_INSTALL} 36 | PATH_SUFFIXES svunit_base 37 | DOC "Path to the SVUnit include directory" 38 | ) 39 | 40 | if (SVUNIT_HDL_SOURCES_DIR) 41 | set(SVUNIT_HDL_PACKAGE ${SVUNIT_HDL_SOURCES_DIR}/svunit_pkg.sv) 42 | set(SVUNIT_INCLUDE_DIR ${SVUNIT_HDL_SOURCES_DIR}) 43 | endif() 44 | 45 | mark_as_advanced(SVUNIT_HDL_PACKAGE) 46 | mark_as_advanced(SVUNIT_INCLUDE_DIR) 47 | 48 | find_package_handle_standard_args(SVUnit REQUIRED_VARS 49 | SVUNIT_HDL_PACKAGE SVUNIT_INCLUDE_DIR) 50 | 51 | set(SVUNIT_FOUND ${SVUNIT_FOUND} PARENT_SCOPE) 52 | set(SVUNIT_INCLUDE_DIR "${SVUNIT_INCLUDE_DIR}" PARENT_SCOPE) 53 | set(SVUNIT_HDL_PACKAGE "${SVUNIT_HDL_PACKAGE}" PARENT_SCOPE) 54 | endfunction() 55 | 56 | _find_svunit() 57 | -------------------------------------------------------------------------------- /include/logic/bitstream_const_reference.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_BITSTREAM_CONST_REFERENCE_HPP 17 | #define LOGIC_BITSTREAM_CONST_REFERENCE_HPP 18 | 19 | #include "bitstream_reference.hpp" 20 | 21 | namespace logic { 22 | 23 | class bitstream_const_reference { 24 | public: 25 | using size_type = std::size_t; 26 | using const_pointer = const void*; 27 | 28 | explicit bitstream_const_reference( 29 | const bitstream_reference& other) noexcept; 30 | 31 | bitstream_const_reference(const_pointer bits, size_type index) noexcept; 32 | 33 | bitstream_const_reference( 34 | bitstream_const_reference&& other) noexcept = default; 35 | 36 | bitstream_const_reference( 37 | const bitstream_const_reference& other) noexcept = default; 38 | 39 | bitstream_const_reference& operator=( 40 | bitstream_const_reference&& other) noexcept = default; 41 | 42 | bitstream_const_reference& operator=( 43 | const bitstream_const_reference& other) noexcept = default; 44 | 45 | explicit operator bool() const noexcept; 46 | 47 | ~bitstream_const_reference() = default; 48 | private: 49 | bitstream_reference m_reference; 50 | }; 51 | 52 | } /* namespace logic */ 53 | 54 | #endif /* LOGIC_BITSTREAM_CONST_REFERENCE_HPP */ 55 | -------------------------------------------------------------------------------- /rtl/logic/basic/synchronizer/logic_basic_synchronizer_generic.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | /* Module: logic_basic_synchronizer_generic 19 | * 20 | * Synchronize input signal to clock. 21 | * 22 | * Parameters: 23 | * WIDTH - Number of bits for input and output signals. 24 | * STAGES - Number of pipeline stages from input to output. 25 | */ 26 | module logic_basic_synchronizer_generic #( 27 | int WIDTH = 1, 28 | int STAGES = 2 29 | ) ( 30 | input aclk, 31 | input areset_n, 32 | input [WIDTH-1:0] i, 33 | output logic [WIDTH-1:0] o 34 | ); 35 | genvar k; 36 | 37 | logic [WIDTH-1:0] q[STAGES-1:0]; 38 | 39 | always_ff @(posedge aclk or negedge areset_n) begin 40 | if (!areset_n) begin 41 | q[0] <= '0; 42 | end 43 | else begin 44 | q[0] <= i; 45 | end 46 | end 47 | 48 | generate 49 | for (k = 1; k < STAGES; ++k) begin: stages 50 | always_ff @(posedge aclk or negedge areset_n) begin 51 | if (!areset_n) begin 52 | q[k] <= '0; 53 | end 54 | else begin 55 | q[k] <= q[k - 1]; 56 | end 57 | end 58 | end 59 | endgenerate 60 | 61 | always_comb o = q[STAGES-1]; 62 | endmodule 63 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/reset_driver.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RESET_DRIVER_HPP 17 | #define LOGIC_AXI4_STREAM_RESET_DRIVER_HPP 18 | 19 | #include "logic/axi4/stream/reset_sequence_item.hpp" 20 | 21 | #include 22 | 23 | namespace logic { 24 | namespace axi4 { 25 | namespace stream { 26 | 27 | class reset_if; 28 | class reset_sequence_item; 29 | 30 | class reset_driver : public uvm::uvm_driver { 31 | public: 32 | UVM_COMPONENT_UTILS(logic::axi4::stream::reset_driver) 33 | 34 | reset_driver(); 35 | 36 | explicit reset_driver(const uvm::uvm_component_name& component_name); 37 | 38 | reset_driver(reset_driver&&) = delete; 39 | 40 | reset_driver(const reset_driver&) = delete; 41 | 42 | reset_driver& operator=(reset_driver&&) = delete; 43 | 44 | reset_driver& operator=(const reset_driver&) = delete; 45 | 46 | ~reset_driver() override; 47 | protected: 48 | void build_phase(uvm::uvm_phase& phase) override; 49 | 50 | [[noreturn]] void run_phase(uvm::uvm_phase& phase) override; 51 | 52 | void transfer(const reset_sequence_item& item); 53 | 54 | reset_if* m_vif; 55 | reset_sequence_item* m_item; 56 | }; 57 | 58 | } /* namespace stream */ 59 | } /* namespace axi4 */ 60 | } /* namespace logic */ 61 | 62 | #endif /* LOGIC_AXI4_STREAM_RESET_DRIVER_HPP */ 63 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/test.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_TEST_HPP 17 | #define LOGIC_AXI4_STREAM_TEST_HPP 18 | 19 | #include "logic/axi4/stream/sequence.hpp" 20 | #include "logic/axi4/stream/sequencer.hpp" 21 | #include "logic/axi4/stream/testbench.hpp" 22 | 23 | #include 24 | 25 | namespace logic{ 26 | namespace axi4 { 27 | namespace stream { 28 | 29 | class sequence; 30 | class testbench; 31 | 32 | class test : public uvm::uvm_test { 33 | public: 34 | UVM_COMPONENT_UTILS(logic::axi4::stream::test) 35 | 36 | test(); 37 | 38 | explicit test(const uvm::uvm_component_name& component_name); 39 | 40 | test(test&&) = delete; 41 | 42 | test(const test&) = delete; 43 | 44 | test& operator=(test&&) = delete; 45 | 46 | test& operator=(const test&) = delete; 47 | 48 | ~test() override; 49 | protected: 50 | void build_phase(uvm::uvm_phase& phase) override; 51 | 52 | void run_phase(uvm::uvm_phase& phase) override; 53 | 54 | void extract_phase(uvm::uvm_phase& phase) override; 55 | 56 | void report_phase(uvm::uvm_phase& phase) override; 57 | 58 | sequence* m_sequence; 59 | testbench* m_testbench; 60 | bool m_test_passed; 61 | }; 62 | 63 | } /* namespace stream */ 64 | } /* namespace axi4 */ 65 | } /* namespace logic */ 66 | 67 | #endif /* LOGIC_AXI4_STREAM_TEST_HPP */ 68 | -------------------------------------------------------------------------------- /src/logic/gtest/factory.cpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #include "logic/gtest/factory.hpp" 17 | 18 | #include 19 | 20 | using logic::gtest::factory; 21 | 22 | auto factory::get_instance() -> factory& { 23 | static factory instance{}; 24 | return instance; 25 | } 26 | 27 | factory::factory() = default; 28 | 29 | factory::~factory() = default; 30 | 31 | void factory::create() { 32 | for (const auto& item : m_constructors) { 33 | m_objects[item.first] = item.second(); 34 | } 35 | } 36 | 37 | void factory::destroy() { 38 | m_objects.clear(); 39 | } 40 | 41 | void factory::add_object(const std::string& name, 42 | const constructor& create_object) { 43 | auto it = m_constructors.find(name); 44 | 45 | if (it == m_constructors.cend()) { 46 | m_constructors[name] = create_object; 47 | } 48 | else { 49 | throw std::runtime_error("logic::gtest::factory::add(): " 50 | + name + " object already exist in factory"); 51 | } 52 | } 53 | 54 | auto factory::get_object(const std::string& name) -> void* { 55 | auto it = m_objects.find(name); 56 | 57 | if (it == m_objects.cend()) { 58 | throw std::runtime_error("logic::gtest::factory::get(): " 59 | + name + " object doesn't exist in factory"); 60 | } 61 | 62 | return it->second.get(); 63 | } 64 | -------------------------------------------------------------------------------- /rtl/logic/basic/queue/logic_basic_queue_generic_write.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | module logic_basic_queue_generic_write #( 19 | int DATA_WIDTH = 1, 20 | int ADDRESS_WIDTH = 1 21 | ) ( 22 | input aclk, 23 | input areset_n, 24 | input rx_tvalid, 25 | input [DATA_WIDTH-1:0] rx_tdata, 26 | output logic rx_tready, 27 | output logic write_enable, 28 | output logic [DATA_WIDTH-1:0] write_data, 29 | output logic [ADDRESS_WIDTH-1:0] write_pointer, 30 | input [ADDRESS_WIDTH:0] capacity 31 | ); 32 | localparam ALMOST_FULL = (2**ADDRESS_WIDTH) - 1; 33 | 34 | logic almost_full; 35 | 36 | always_comb write_data = rx_tdata; 37 | always_comb write_enable = rx_tvalid && rx_tready; 38 | always_comb almost_full = (capacity >= ALMOST_FULL[ADDRESS_WIDTH:0]); 39 | 40 | always_ff @(posedge aclk or negedge areset_n) begin 41 | if (!areset_n) begin 42 | rx_tready <= '0; 43 | end 44 | else begin 45 | rx_tready <= !almost_full; 46 | end 47 | end 48 | 49 | always_ff @(posedge aclk or negedge areset_n) begin 50 | if (!areset_n) begin 51 | write_pointer <= '0; 52 | end 53 | else if (write_enable) begin 54 | write_pointer <= write_pointer + 1'b1; 55 | end 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /rtl/logic/basic/synchronizer/logic_basic_synchronizer.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "logic.svh" 17 | 18 | /* Module: logic_basic_synchronizer 19 | * 20 | * Synchronize input signal to clock. 21 | * 22 | * Parameters: 23 | * WIDTH - Number of bits for input and output signals. 24 | * STAGES - Number of pipeline stages from input to output. 25 | */ 26 | module logic_basic_synchronizer #( 27 | logic_pkg::target_t TARGET = logic_pkg::TARGET_GENERIC, 28 | int WIDTH = 1, 29 | int STAGES = 2 30 | ) ( 31 | input aclk, 32 | input areset_n, 33 | input [WIDTH-1:0] i, 34 | output logic [WIDTH-1:0] o 35 | ); 36 | generate 37 | case (TARGET) 38 | logic_pkg::TARGET_INTEL, 39 | logic_pkg::TARGET_INTEL_ARRIA_10, 40 | logic_pkg::TARGET_INTEL_ARRIA_10_SOC: begin: target_intel 41 | logic_basic_synchronizer_intel #( 42 | .WIDTH(WIDTH), 43 | .STAGES(STAGES) 44 | ) 45 | unit ( 46 | .* 47 | ); 48 | end 49 | default: begin: target_generic 50 | logic_basic_synchronizer_generic #( 51 | .WIDTH(WIDTH), 52 | .STAGES(STAGES) 53 | ) 54 | unit ( 55 | .* 56 | ); 57 | end 58 | endcase 59 | endgenerate 60 | endmodule 61 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/tx_driver.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_TX_DRIVER_HPP 17 | #define LOGIC_AXI4_STREAM_TX_DRIVER_HPP 18 | 19 | #include "logic/axi4/stream/tx_sequence_item.hpp" 20 | 21 | #include 22 | 23 | #include 24 | #include 25 | 26 | namespace logic { 27 | namespace axi4 { 28 | namespace stream { 29 | 30 | class bus_if_base; 31 | class tx_sequence_item; 32 | 33 | class tx_driver : public uvm::uvm_driver { 34 | public: 35 | UVM_COMPONENT_UTILS(logic::axi4::stream::tx_driver) 36 | 37 | tx_driver(); 38 | 39 | explicit tx_driver(const uvm::uvm_component_name& component_name); 40 | 41 | tx_driver(tx_driver&&) = delete; 42 | 43 | tx_driver(const tx_driver&) = delete; 44 | 45 | tx_driver& operator=(tx_driver&&) = delete; 46 | 47 | tx_driver& operator=(const tx_driver&) = delete; 48 | 49 | ~tx_driver() override; 50 | protected: 51 | void build_phase(uvm::uvm_phase& phase) override; 52 | 53 | [[noreturn]] void run_phase(uvm::uvm_phase& phase) override; 54 | 55 | void transfer(const tx_sequence_item& item); 56 | 57 | bus_if_base* m_vif; 58 | tx_sequence_item* m_item; 59 | std::mt19937 m_random_generator; 60 | }; 61 | 62 | } /* namespace stream */ 63 | } /* namespace axi4 */ 64 | } /* namespace logic */ 65 | 66 | #endif /* LOGIC_AXI4_STREAM_TX_DRIVER_HPP */ 67 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/testbench.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_TESTBENCH_HPP 17 | #define LOGIC_AXI4_STREAM_TESTBENCH_HPP 18 | 19 | #include 20 | 21 | namespace logic { 22 | namespace axi4 { 23 | namespace stream { 24 | 25 | class rx_agent; 26 | class tx_agent; 27 | class sequencer; 28 | class scoreboard; 29 | class reset_agent; 30 | 31 | class testbench : public uvm::uvm_env { 32 | public: 33 | UVM_COMPONENT_UTILS(logic::axi4::stream::testbench) 34 | 35 | logic::axi4::stream::sequencer* sequencer; 36 | 37 | testbench(); 38 | 39 | explicit testbench(const uvm::uvm_component_name& component_name); 40 | 41 | bool passed() const noexcept; 42 | 43 | bool failed() const noexcept; 44 | 45 | testbench(testbench&&) = delete; 46 | 47 | testbench(const testbench&) = delete; 48 | 49 | testbench& operator=(testbench&&) = delete; 50 | 51 | testbench& operator=(const testbench&) = delete; 52 | 53 | ~testbench() override; 54 | protected: 55 | void build_phase(uvm::uvm_phase& phase) override; 56 | 57 | void connect_phase(uvm::uvm_phase& phase) override; 58 | 59 | rx_agent* m_rx_agent; 60 | tx_agent* m_tx_agent; 61 | scoreboard* m_scoreboard; 62 | reset_agent* m_reset_agent; 63 | }; 64 | 65 | } /* namespace stream */ 66 | } /* namespace axi4 */ 67 | } /* namespace logic */ 68 | 69 | #endif /* LOGIC_AXI4_STREAM_TESTBENCH_HPP */ 70 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/rx_driver.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RX_DRIVER_HPP 17 | #define LOGIC_AXI4_STREAM_RX_DRIVER_HPP 18 | 19 | #include "logic/axi4/stream/rx_sequence_item.hpp" 20 | 21 | #include 22 | 23 | #include 24 | #include 25 | 26 | namespace logic { 27 | namespace axi4 { 28 | namespace stream { 29 | 30 | class bus_if_base; 31 | class rx_sequence_item; 32 | 33 | class rx_driver : public uvm::uvm_driver { 34 | public: 35 | UVM_COMPONENT_UTILS(logic::axi4::stream::rx_driver) 36 | 37 | rx_driver(); 38 | 39 | explicit rx_driver(const uvm::uvm_component_name& component_name); 40 | 41 | rx_driver(rx_driver&&) = delete; 42 | 43 | rx_driver(const rx_driver&) = delete; 44 | 45 | rx_driver& operator=(rx_driver&&) = delete; 46 | 47 | rx_driver& operator=(const rx_driver&) = delete; 48 | 49 | ~rx_driver() override; 50 | protected: 51 | void build_phase(uvm::uvm_phase& phase) override; 52 | 53 | [[noreturn]] void run_phase(uvm::uvm_phase& phase) override; 54 | 55 | void data_transfer(const rx_sequence_item& item); 56 | 57 | void idle_transfer(const rx_sequence_item& item); 58 | 59 | bus_if_base* m_vif; 60 | rx_sequence_item* m_item; 61 | std::mt19937 m_random_generator; 62 | }; 63 | 64 | } /* namespace stream */ 65 | } /* namespace axi4 */ 66 | } /* namespace logic */ 67 | 68 | #endif /* LOGIC_AXI4_STREAM_RX_DRIVER_HPP */ 69 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/sequence.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_SEQUENCE_HPP 17 | #define LOGIC_AXI4_STREAM_SEQUENCE_HPP 18 | 19 | #include "logic/axi4/stream/reset_sequence.hpp" 20 | #include "logic/axi4/stream/rx_sequence.hpp" 21 | #include "logic/axi4/stream/tx_sequence.hpp" 22 | #include "logic/range.hpp" 23 | 24 | #include 25 | 26 | namespace logic { 27 | namespace axi4 { 28 | namespace stream { 29 | 30 | class rx_sequencer; 31 | class tx_sequencer; 32 | class reset_sequencer; 33 | 34 | class sequence : public uvm::uvm_sequence<> { 35 | public: 36 | UVM_OBJECT_UTILS(logic::axi4::stream::sequence) 37 | 38 | reset_sequence* reset; 39 | rx_sequence* rx; 40 | tx_sequence* tx; 41 | 42 | sequence(); 43 | 44 | explicit sequence(const std::string& name); 45 | 46 | sequence(sequence&&) = delete; 47 | 48 | sequence(const sequence&) = delete; 49 | 50 | sequence& operator=(sequence&&) = delete; 51 | 52 | sequence& operator=(const sequence&) = delete; 53 | 54 | ~sequence() override; 55 | protected: 56 | void pre_body() override; 57 | 58 | void body() override; 59 | 60 | void post_body() override; 61 | 62 | rx_sequencer* m_rx_sequencer; 63 | tx_sequencer* m_tx_sequencer; 64 | reset_sequencer* m_reset_sequencer; 65 | }; 66 | 67 | } /* namespace stream */ 68 | } /* namespace axi4 */ 69 | } /* namespace logic */ 70 | 71 | #endif /* LOGIC_AXI4_STREAM_SEQUENCE_HPP */ 72 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/reset_sequence_item.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_RESET_SEQUENCE_ITEM_HPP 17 | #define LOGIC_AXI4_STREAM_RESET_SEQUENCE_ITEM_HPP 18 | 19 | #include 20 | 21 | #include 22 | 23 | namespace logic { 24 | namespace axi4 { 25 | namespace stream { 26 | 27 | class reset_sequence_item : public uvm::uvm_sequence_item { 28 | public: 29 | UVM_OBJECT_UTILS(logic::axi4::stream::reset_sequence_item) 30 | 31 | std::size_t duration; 32 | std::size_t idle; 33 | 34 | reset_sequence_item(); 35 | 36 | explicit reset_sequence_item(const std::string& name); 37 | 38 | reset_sequence_item(reset_sequence_item&&) = default; 39 | 40 | reset_sequence_item(const reset_sequence_item&) = default; 41 | 42 | reset_sequence_item& operator=(reset_sequence_item&&) = default; 43 | 44 | reset_sequence_item& operator=(const reset_sequence_item&) = default; 45 | 46 | std::string convert2string() const override; 47 | 48 | ~reset_sequence_item() override; 49 | protected: 50 | void do_print(const uvm::uvm_printer& printer) const override; 51 | 52 | void do_copy(const uvm::uvm_object& rhs) override; 53 | 54 | bool do_compare(const uvm::uvm_object& rhs, 55 | const uvm::uvm_comparer* comparer = nullptr) const override; 56 | }; 57 | 58 | } /* namespace stream */ 59 | } /* namespace axi4 */ 60 | } /* namespace logic */ 61 | 62 | #endif /* LOGIC_AXI4_STREAM_RESET_SEQUENCE_ITEM_HPP */ 63 | -------------------------------------------------------------------------------- /tests/logic/reset/synchronizer/logic_reset_synchronizer_unit_test.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | `include "svunit_defines.svh" 17 | 18 | module logic_reset_synchronizer_unit_test; 19 | import svunit_pkg::svunit_testcase; 20 | 21 | string name = "logic_reset_synchronizer_unit_test"; 22 | svunit_testcase svunit_ut; 23 | 24 | logic aclk = 0; 25 | logic areset_n = 0; 26 | logic areset_n_synced; 27 | 28 | initial forever #1 aclk = ~aclk; 29 | 30 | logic_reset_synchronizer dut ( 31 | .* 32 | ); 33 | 34 | function void build(); 35 | svunit_ut = new (name); 36 | endfunction 37 | 38 | task setup(); 39 | svunit_ut.setup(); 40 | 41 | areset_n = 0; 42 | @(posedge aclk); 43 | endtask 44 | 45 | task teardown(); 46 | svunit_ut.teardown(); 47 | 48 | areset_n = 0; 49 | endtask 50 | 51 | `SVUNIT_TESTS_BEGIN 52 | 53 | `SVTEST(simple) 54 | areset_n = 0; 55 | repeat (3) @(posedge aclk); 56 | 57 | `FAIL_UNLESS_EQUAL(areset_n_synced, 0) 58 | 59 | areset_n = 1; 60 | repeat (3) @(posedge aclk); 61 | 62 | `FAIL_UNLESS_EQUAL(areset_n_synced, 1) 63 | `SVTEST_END 64 | 65 | `SVTEST(deassertion) 66 | areset_n = 1; 67 | repeat (3) @(posedge aclk); 68 | 69 | `FAIL_UNLESS_EQUAL(areset_n_synced, 1) 70 | 71 | areset_n = 0; 72 | #1; 73 | 74 | `FAIL_UNLESS_EQUAL(areset_n_synced, 0) 75 | `SVTEST_END 76 | 77 | `SVUNIT_TESTS_END 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /include/logic/axi4/stream/packet.hpp: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 Tymoteusz Blazejczyk 2 | * 3 | * Licensed under the Apache License, Version 2.0 (the "License"); 4 | * you may not use this file except in compliance with the License. 5 | * You may obtain a copy of the License at 6 | * 7 | * http://www.apache.org/licenses/LICENSE-2.0 8 | * 9 | * Unless required by applicable law or agreed to in writing, software 10 | * distributed under the License is distributed on an "AS IS" BASIS, 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | * See the License for the specific language governing permissions and 13 | * limitations under the License. 14 | */ 15 | 16 | #ifndef LOGIC_AXI4_STREAM_PACKET_HPP 17 | #define LOGIC_AXI4_STREAM_PACKET_HPP 18 | 19 | #include "logic/bitstream.hpp" 20 | #include "tdata_byte.hpp" 21 | 22 | #include 23 | 24 | #include 25 | #include 26 | 27 | namespace logic { 28 | namespace axi4 { 29 | namespace stream { 30 | 31 | class packet : public uvm::uvm_object { 32 | public: 33 | UVM_OBJECT_UTILS(logic::axi4::stream::packet) 34 | 35 | bitstream tid; 36 | bitstream tdest; 37 | std::vector tuser; 38 | std::vector tdata; 39 | std::vector timestamps; 40 | std::size_t bus_size; 41 | 42 | packet(); 43 | 44 | explicit packet(const std::string& name); 45 | 46 | packet(packet&&) = default; 47 | 48 | packet(const packet&) = default; 49 | 50 | packet& operator=(packet&&) = default; 51 | 52 | packet& operator=(const packet&) = default; 53 | 54 | std::string convert2string() const override; 55 | 56 | ~packet() override; 57 | protected: 58 | void do_print(const uvm::uvm_printer& printer) const override; 59 | 60 | void do_copy(const uvm::uvm_object& rhs) override; 61 | 62 | bool do_compare(const uvm::uvm_object& rhs, 63 | const uvm::uvm_comparer* comparer = nullptr) const override; 64 | }; 65 | 66 | } /* namespace stream */ 67 | } /* namespace axi4 */ 68 | } /* namespace logic */ 69 | 70 | #endif /* LOGIC_AXI4_STREAM_PACKET_HPP */ 71 | --------------------------------------------------------------------------------