├── .gitignore ├── ChangeLog ├── Makefile ├── README.md ├── ReleaseNotes ├── bin ├── bootaws.py ├── build_graphs.py ├── jinja2html.py ├── sbt ├── sbt-launch-0.12.2.jar └── tex2html.py ├── build.sbt ├── chisel.mtt ├── configure ├── csrc ├── emulator.h ├── makefile └── tests.cpp ├── doc └── README ├── man.mk ├── project ├── build.properties └── plugins.sbt ├── scalastyle-config.xml └── src ├── LICENSE.TXT ├── main ├── resources │ ├── Makefile │ ├── emul_api.h │ ├── emulator.h │ ├── sim_api.h │ ├── template.txt │ ├── vpi.cpp │ ├── vpi.h │ └── vpi.tab └── scala │ ├── AdvTester.scala │ ├── Aggregate.scala │ ├── Assert.scala │ ├── Backend.scala │ ├── Binding.scala │ ├── BitPat.scala │ ├── Bits.scala │ ├── BlackBox.scala │ ├── Bool.scala │ ├── Bundle.scala │ ├── CSE.scala │ ├── Cat.scala │ ├── ChiselError.scala │ ├── ChiselUtil.scala │ ├── Clock.scala │ ├── Complex.scala │ ├── Cpp.scala │ ├── Data.scala │ ├── Dot.scala │ ├── Driver.scala │ ├── Enum.scala │ ├── Extract.scala │ ├── FP.scala │ ├── FPGA.scala │ ├── FameBackend.scala │ ├── Fill.scala │ ├── Fixed.scala │ ├── Flo.scala │ ├── IO.scala │ ├── ImplicitConversions.scala │ ├── Insert.scala │ ├── JHFormat.scala │ ├── Lit.scala │ ├── Log2.scala │ ├── Lookup.scala │ ├── Mem.scala │ ├── Module.scala │ ├── Mux.scala │ ├── Node.scala │ ├── Op.scala │ ├── Parameters.scala │ ├── Params.scala │ ├── PartitionIslands.scala │ ├── ROM.scala │ ├── Reg.scala │ ├── SCWrapper.scala │ ├── SInt.scala │ ├── SysC.scala │ ├── Tester.scala │ ├── UInt.scala │ ├── Vcd.scala │ ├── Vec.scala │ ├── Verilog.scala │ ├── Version.scala │ ├── Width.scala │ ├── fixpt.scala │ ├── hcl.scala │ ├── iotesters │ ├── ChiselSpec.scala │ ├── Driver.scala │ ├── HWIOTester.scala │ ├── IOAccessor.scala │ ├── OrderedDecoupledHWIOTester.scala │ ├── PeekPokeTester.scala │ └── SteppedHWIOTester.scala │ ├── package.scala │ ├── testers │ ├── BasicTester.scala │ └── TesterDriver.scala │ └── when.scala └── test ├── resources ├── AddFilterSysCdriver.cpp ├── ConnectSuite_A_4.v ├── ConnectSuite_BindingTest_1.v ├── ConnectSuite_InstanceSuperclass_1.v ├── ConnectSuite_LogicBtwInstances_1.v ├── ConnectSuite_NoClassRelation_1.v ├── ConnectSuite_SubmoduleInputUse_1.v ├── ConnectSuite_SuppliesResetsParent_1.v ├── ConnectSuite_UnconnectedIOs_1.h ├── ConnectSuite_UnconnectedResets_1.v ├── ConnectSuite_UnspecifiedBundleValues_1.v ├── ConnectSuite_UsesShimParent_1.v ├── ConnectWireSuite_BindingTest_1.v ├── DataSuite_BypassDataComp_1.h ├── DelaySuite_MemReadModule_1.v ├── DelaySuite_ROMModule_1.cpp ├── DelaySuite_ROMModule_1.h ├── DelaySuite_ROMModule_1.v ├── DelaySuite_ReadCondMaskedWrite_1.v ├── DelaySuite_ReadCondWriteModule_1.v ├── DelaySuite_ReadWriteModule_1.v ├── DelaySuite_RegInitCondUpdate_1.v ├── DelaySuite_RegInitUpdate_1.v ├── DelaySuite_RegNoInitUpdate_1.v ├── DelaySuite_SeqReadBundle_1.cpp ├── DelaySuite_SeqReadBundle_1.h ├── DotBackendSuite_DAGComp_1.dot ├── FullAdderSysCdriver.cpp ├── Makefile.sysc ├── MultiClockSuite_ClockDec_1.v ├── MultiClockSuite_Comp_1.v ├── MultiClockSuite_TestMultiClock2_1.v ├── NameSuite_BindFifthComp_1.v ├── NameSuite_BindFirstComp_1.v ├── NameSuite_BindFourthComp_1.v ├── NameSuite_BindSecondComp_1.v ├── NameSuite_BindThirdComp_1.v ├── NameSuite_DebugComp_1.cpp ├── NameSuite_DebugComp_1.h ├── NameSuite_InputPortNameComp_1.v ├── NameSuite_ListLookupsComp_1.v ├── NameSuite_MemComp_1.v ├── NameSuite_VariationComp_1.v ├── NameSuite_VecComp_1.v ├── NameSuite_VecSecondComp_1.v ├── RegVcdSuite_RegVcdTest_1.vcd ├── StdlibSuite_ArbiterTest_1.v ├── StdlibSuite_AssignBundleComp_1.v ├── StdlibSuite_CatComp_1.v ├── StdlibSuite_DivSU_1.v ├── StdlibSuite_DivUS_1.v ├── StdlibSuite_MulSU_1.v ├── StdlibSuite_MulUS_1.v ├── StdlibSuite_OHToUIntComp_1.v ├── StdlibSuite_PipeComp_1.v ├── StdlibSuite_QueueComp_1.v ├── StdlibSuite_RRArbiterTest_1.v ├── StdlibSuite_RemSU_1.v ├── StdlibSuite_RemUS_1.v ├── VCDVerifySuite_Top_1.vcd ├── VerifSuite_CppAssertComp_1.cpp ├── VerifSuite_CppPrintfComp_1.cpp ├── VerifSuite_CppPrintfComp_1.h ├── VerifSuite_VerilogAssertComp_1.v ├── VerifSuite_VerilogPrintfComp_1.v ├── VerifSuite_VerilogPrintfNULComp_1.v ├── VerilogMultiModule_MultiMultiFIR_2.v ├── WhenSuite_EmbedWhenComp_1.v ├── WhenSuite_SwitchClassComp_1.cpp ├── WhenSuite_SwitchClassComp_1.v ├── WhenSuite_UnlessClassComp_1.v ├── WhenSuite_WhenClassComp_1.v ├── WhenSuite_WhenComp_1.v ├── ZeroWidthTest_ArbiterTest_1.dot ├── ZeroWidthTest_AssignBundleComp_1.dot ├── ZeroWidthTest_CatCompW0W_1.dot ├── ZeroWidthTest_CatComp_1.dot ├── ZeroWidthTest_CounterComp_1.dot ├── ZeroWidthTest_DivSU_1.dot ├── ZeroWidthTest_DivUS_1.dot ├── ZeroWidthTest_DivUUZ_1.dot ├── ZeroWidthTest_DivUZ_1.dot ├── ZeroWidthTest_DivZU_1.dot ├── ZeroWidthTest_FillComp_1.dot ├── ZeroWidthTest_FillInterleavedComp_1.dot ├── ZeroWidthTest_Log2Comp_1.dot ├── ZeroWidthTest_LookupComp_1.dot ├── ZeroWidthTest_MulSU_1.dot ├── ZeroWidthTest_MulUS_1.dot ├── ZeroWidthTest_MulUUZ_1.dot ├── ZeroWidthTest_MulUZ_1.dot ├── ZeroWidthTest_MulZS_1.dot ├── ZeroWidthTest_MulZU_1.dot ├── ZeroWidthTest_MuxCaseComp_1.dot ├── ZeroWidthTest_MuxComp_1.dot ├── ZeroWidthTest_MuxLookupComp_1.dot ├── ZeroWidthTest_OHToUIntComp_1.dot ├── ZeroWidthTest_OperatorComp_1.dot ├── ZeroWidthTest_PipeComp_1.dot ├── ZeroWidthTest_PopCountComp_1.dot ├── ZeroWidthTest_PriorityEncoderComp_1.dot ├── ZeroWidthTest_PriorityEncoderOHComp_1.dot ├── ZeroWidthTest_PriorityMuxComp_1.dot ├── ZeroWidthTest_QueueComp_1.dot ├── ZeroWidthTest_RRArbiterTest_1.dot ├── ZeroWidthTest_RemSU_1.dot ├── ZeroWidthTest_RemUS_1.dot ├── ZeroWidthTest_RemUZ_1.dot ├── ZeroWidthTest_RemZU_1.dot ├── ZeroWidthTest_ReverseComp_1.dot ├── ZeroWidthTest_ShiftRegisterComp_1.dot ├── ZeroWidthTest_UIntToOHComp_1.dot ├── ZeroWidthTest_ZeroWidthForceMatching_1.v └── ZeroWidthTest_foldRComp_1.dot └── scala ├── ArbiterTest.scala ├── AssertSuite.scala ├── BitPatSuite.scala ├── BitsTest.scala ├── BundleWire.scala ├── Chisel3Compatibility.scala ├── CombLoopTests.scala ├── ComplexSuite.scala ├── ConnectTest.scala ├── ConnectTestWire.scala ├── DataTest.scala ├── DecoupledGCD.scala ├── DelayBetween.scala ├── DelayTest.scala ├── DotBackendTest.scala ├── DoubleSuite.scala ├── ExtractSuite.scala ├── FillApp.scala ├── FixedTest.scala ├── FlushPrintfOutput.scala ├── FunTestSuite.scala ├── GCDUnitTest.scala ├── LargeNumber.scala ├── ManyEnums.scala ├── ModuleTests.scala ├── MultiClockTest.scala ├── NameTest.scala ├── Outer.scala ├── ROM.scala ├── ReadMeCode.scala ├── RegVcdTest.scala ├── RegWithAgregateDefaultSuite.scala ├── Risc.scala ├── SeqMemSuite.scala ├── StdlibTest.scala ├── SubwordTests.scala ├── SysCTest ├── AddFilter.scala └── FullAdder.scala ├── SystemCSuite.scala ├── TestHelpers.scala ├── TestSuite.scala ├── TesterTest.scala ├── TextComparator.scala ├── VCDComparator.scala ├── VCDVerifySuite.scala ├── VecApp.scala ├── VerifTest.scala ├── VerilogMultiModule.scala ├── VersionSuite.scala ├── WhenTest.scala └── ZeroWidthTest.scala /.gitignore: -------------------------------------------------------------------------------- 1 | target/ 2 | test-outputs/ 3 | test-reports/ 4 | .DS_Store 5 | .history 6 | .ensime 7 | .ensime_lucene/ 8 | *.nav 9 | *.out 10 | *.snm 11 | *.vrb 12 | *.toc 13 | *.bak 14 | *.new 15 | *~ 16 | /eclipse.bin 17 | /ucli.key 18 | /cpp 19 | -------------------------------------------------------------------------------- /ChangeLog: -------------------------------------------------------------------------------- 1 | ChangeLog for Chisel v2.2.38 2 | 3 | Move {as,to}{U,S}Int definitions to Node.scala, and add them as Bundle key words. 4 | Update deprecated Fill() usage in FillApp.scala. 5 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # Retain all intermediate files. 2 | .SECONDARY: 3 | 4 | SBT ?= sbt 5 | SBT_FLAGS ?= -Dsbt.log.noformat=true 6 | RM_DIRS := test-outputs test-reports 7 | CLEAN_DIRS := 8 | 9 | SRC_DIR ?= . 10 | #SYSTEMC ?= $(SRC_DIR)/../../systemc/systemc-2.3.1 11 | SYSCTESTS ?= $(addsuffix .sysctest,$(notdir $(basename $(wildcard $(SRC_DIR)/src/test/scala/SysCTest/*.scala)))) 12 | CHISEL_JAR ?= $(SRC_DIR)/target/scala-2.10/chisel_2.10-2.3-SNAPSHOT.jar 13 | TEST_OUTPUT_DIR ?= ./test-outputs 14 | 15 | .PHONY: smoke publish-local check clean jenkins-build sysctest coverage scaladoc test compile style 16 | 17 | SMOKE_TESTS ?= StdlibSuite 18 | 19 | default: publish-local 20 | 21 | compile: 22 | $(SBT) $(SBT_FLAGS) compile 23 | 24 | publish-local: 25 | $(SBT) $(SBT_FLAGS) +publish-local 26 | 27 | smoke: 28 | $(SBT) $(SBT_FLAGS) "test-only $(SMOKE_TESTS) -- -l org.scalatest.tags.Slow" 29 | 30 | style: 31 | $(SBT) $(SBT_FLAGS) scalastyle test:scalastyle 32 | 33 | check test: 34 | $(SBT) $(SBT_FLAGS) test 35 | 36 | coverage: 37 | $(SBT) $(SBT_FLAGS) coverage test 38 | $(SBT) $(SBT_FLAGS) coverageReport 39 | 40 | clean: 41 | $(SBT) $(SBT_FLAGS) +clean 42 | for dir in $(CLEAN_DIRS); do $(MAKE) -C $$dir clean; done 43 | $(RM) -r $(RM_DIRS) 44 | 45 | scaladoc: 46 | $(SBT) $(SBT_FLAGS) doc test:doc 47 | 48 | # Start off clean, then run tests for all supported configurations, and publish those versions of the code. 49 | # Then run coverage and style tests (for developer's use). 50 | # Don't publish the coverage test code since it contains hooks/references to the coverage test package 51 | # and we don't want code with those dependencies published. 52 | # We need to run the coverage tests last, since Jenkins will fail the build if it can't find their results. 53 | jenkins-build: clean 54 | $(SBT) $(SBT_FLAGS) +test 55 | $(SBT) $(SBT_FLAGS) +clean +publish-local 56 | $(SBT) $(SBT_FLAGS) scalastyle coverage test 57 | $(SBT) $(SBT_FLAGS) coverageReport 58 | 59 | .PHONY: SYSCDIR 60 | 61 | SYSCDIR: 62 | @if [ -z "$(SYSTEMC)" ]; then echo "Please define SYSTEMC (the root of the systemc distribution) in your environment"; exit 1; fi 63 | @if [ ! -d "$(SYSTEMC)" ]; then echo "SYSTEMC isn't a valid directory - $(SYSTEMC)"; exit 1; fi 64 | 65 | sysctests: $(SYSCTESTS) SYSCDIR 66 | 67 | sysctest: $(firstword $(SYSCTESTS)) SYSCDIR 68 | 69 | %.sysctest: 70 | mkdir -p $(TEST_OUTPUT_DIR) 71 | $(MAKE) -C $(TEST_OUTPUT_DIR) -f ../Makefile SRC_DIR=.. $(basename $@).sysc 72 | cd $(TEST_OUTPUT_DIR) && ./$(basename $@).sysc 73 | 74 | %.sysc: %.h %.cpp $(SRC_DIR)/src/test/resources/%SysCdriver.cpp 75 | $(CXX) -g $(filter-out %.h,$^) \ 76 | -I. -I$(SYSTEMC)/include -L$(SYSTEMC)/lib-macosx64 -lsystemc -o $@ 77 | 78 | %.h %.cpp: %.class 79 | scala -cp $(CHISEL_JAR):. SysCTest.$(basename $@) --targetDir . --genHarness --backend sysc 80 | 81 | %.class: ../src/test/scala/SysCTest/%.scala $(CHISEL_JAR) 82 | scalac -cp $(CHISEL_JAR) $< 83 | 84 | -------------------------------------------------------------------------------- /ReleaseNotes: -------------------------------------------------------------------------------- 1 | ReleaseNotes for Chisel v2.2.38 2 | 3 | This release of Chisel is a maintenance release, incorporating support for Chisel3's {as,to}{U,S}Int methods in all Chisel Data types. 4 | 5 | We will be removing support for Scala 2.10 in future Chisel 6 | releases. Please verify your code compiles and runs correctly under 7 | Scala 2.11. 8 | 9 | -------------------------------------------------------------------------------- /bin/jinja2html.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import fnmatch, json, os, re, sys, xml.dom.minidom 4 | 5 | from jinja2 import Environment, FileSystemLoader 6 | 7 | def main(args): 8 | env = Environment(loader=FileSystemLoader( 9 | os.path.join(os.path.dirname(os.path.dirname(sys.argv[0])), 10 | 'doc', 'templates'))) 11 | template = env.get_template(args[1]) 12 | with open(args[2], 'w') as outfile: 13 | outfile.write(template.render()) 14 | 15 | if __name__ == '__main__': 16 | main(sys.argv) 17 | -------------------------------------------------------------------------------- /bin/sbt-launch-0.12.2.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/chisel2-deprecated/9d9672bb69e9d6168ab3779f0ed543d5ad190dee/bin/sbt-launch-0.12.2.jar -------------------------------------------------------------------------------- /bin/tex2html.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import fnmatch, json, os, re, subprocess, sys, tempfile 4 | 5 | from bs4 import BeautifulSoup, Comment, Tag, NavigableString 6 | from jinja2 import Environment, ChoiceLoader, FileSystemLoader 7 | 8 | def main(args): 9 | # Extract from the html generated by htlatex 10 | with open(args[1]) as texhtmlfile: 11 | soup = BeautifulSoup(texhtmlfile.read()) 12 | tmpfile = args[2] + '.1' 13 | with open(tmpfile, 'w') as htmlfile: 14 | htmlfile.write(""" 15 | {% extends "base.html" %} 16 | 17 | {% block content %} 18 | {{text}} 19 | """) 20 | text = '' 21 | for img in soup.find_all('img'): 22 | img['src'] = os.path.join( 23 | 'figs', os.path.basename(img['src'])) 24 | for node in soup.body.contents: 25 | if isinstance(node, Tag) and node.name == 'pre': 26 | codefile = tempfile.NamedTemporaryFile(delete=False) 27 | codepath = codefile.name 28 | with codefile: 29 | for code in node.contents: 30 | if isinstance(code, Tag) and code.name == 'br': 31 | codefile.write('\n') 32 | elif not isinstance(code, Comment): 33 | if isinstance(code, NavigableString): 34 | codefile.write(code.string) 35 | else: 36 | codefile.write(code.get_text().encode('utf-8')) 37 | codetext = subprocess.check_output( 38 | ["source-highlight", "-s", "scala", "-i", codepath]) 39 | os.remove(codepath) 40 | text = text + codetext.decode('utf-8') 41 | elif not isinstance(node, Comment): 42 | text = text + str(node).decode('utf-8') 43 | htmlfile.write(""" 44 | {% endblock %} 45 | """) 46 | 47 | # Dress up with base layout 48 | env = Environment(loader=ChoiceLoader([ 49 | FileSystemLoader('.'), 50 | FileSystemLoader( 51 | os.path.join(os.path.dirname(os.path.dirname(sys.argv[0])), 52 | 'doc', 'templates'))])) 53 | template = env.get_template(tmpfile) 54 | with open(args[2], 'w') as outfile: 55 | outfile.write(template.render(text=text).encode('utf-8')) 56 | 57 | 58 | if __name__ == '__main__': 59 | main(sys.argv) 60 | -------------------------------------------------------------------------------- /configure: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # This script will copy the appropriate project/ directories from the source 4 | # tree and modify build.sbt such that we build the chisel jar in a build tree 5 | # independent of the filesystem on which sources reside. 6 | 7 | srcTop=`dirname $0` 8 | buildTop=`pwd` 9 | 10 | if [ $(uname) == "Linux" ] ; then 11 | statFormat="--format='%d:%i'" 12 | else 13 | statFormat="-f '%d:%i'" 14 | fi 15 | 16 | if [ "$(stat -L $statFormat $srcTop)" == "$(stat -L $statFormat $buildTop)" ] 17 | then 18 | echo "You are running 'configure' in the directory it resides." 19 | echo "Nothing to be done, just run sbt directory." 20 | exit 1 21 | fi 22 | 23 | sed -e "s,//sourceDirectory := new File(\"@srcTop@\"),sourceDirectory := new File(\"${srcTop}\")," $srcTop/build.sbt > build.sbt 24 | cp -rf $srcTop/project . 25 | echo "Done." 26 | echo "Ready to run sbt commands from the build directory." 27 | -------------------------------------------------------------------------------- /csrc/emulator.h: -------------------------------------------------------------------------------- 1 | ../src/main/resources/emulator.h -------------------------------------------------------------------------------- /csrc/makefile: -------------------------------------------------------------------------------- 1 | # CPPFLAGS = -O2 # -S -g 2 | CPPFLAGS = -g -O2 -std=c++11 3 | 4 | all: tests 5 | 6 | tests.o: tests.cpp emulator.h 7 | g++-4.8 $(CPPFLAGS) -c -g tests.cpp 8 | tests: tests.o 9 | g++-4.8 $(CPPFLAGS) -o tests -g tests.o 10 | clean: 11 | rm -f *.o emulator test 12 | -------------------------------------------------------------------------------- /doc/README: -------------------------------------------------------------------------------- 1 | Chisel documentation (non-tutorial) has been moved to the chisel-doc repo: 2 | 3 | https://github.com/ucb-bar/chisel-doc 4 | 5 | Tutorial documentation has been moved to the chisel-tutorial repo: 6 | 7 | https://github.com/ucb-bar/chisel-tutorial/doc/tutorial 8 | 9 | -------------------------------------------------------------------------------- /man.mk: -------------------------------------------------------------------------------- 1 | # make fragment to build man pages. 2 | 3 | LATEX2MAN := latex2man 4 | MAN_PAGES := chisel.man 5 | 6 | # Set the current release info 7 | # RELEASE_TAGTEXT is something like: v2.2.18 125 g3501d7f 8 | # i.e., the output of git describe with dashes replaced by spaces 9 | RELEASE_TAGTEXT=$(subst -, ,$(shell git describe --tags release)) 10 | RELEASE_TAG=$(firstword $(RELEASE_TAGTEXT)) 11 | RELEASE_DATETEXT=$(shell git log -1 --format="%ai" $(RELEASE_TAG)) 12 | RELEASE_DATE=$(firstword $(RELEASE_DATETEXT)) 13 | 14 | all: $(MAN_PAGES) 15 | 16 | %.man: %.mtt 17 | sed -e "s/@VERSION@/$(RELEASE_TAG)/" -e "s/@DATE@/$(RELEASE_DATE)/" $(notdir $<) > $(basename $@).ttex ;\ 18 | latex2man $(basename $@).ttex $@ 19 | 20 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=0.13.16 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) 2 | 3 | resolvers += Classpaths.sbtPluginReleases 4 | 5 | addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "0.8.0") 6 | 7 | addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.3.5") 8 | 9 | addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.6.1") 10 | -------------------------------------------------------------------------------- /src/LICENSE.TXT: -------------------------------------------------------------------------------- 1 | Chisel licence terms 2 | 3 | Copyright (c); 2011, 2012, 2013 The Regents of the University of 4 | California (Regents). All Rights Reserved. Redistribution and use in 5 | source and binary forms, with or without modification, are permitted 6 | provided that the following conditions are met: 7 | 8 | o Redistributions of source code must retain the above 9 | copyright notice, this list of conditions and the following 10 | two paragraphs of disclaimer. 11 | 12 | o Redistributions in binary form must reproduce the above 13 | copyright notice, this list of conditions and the following 14 | two paragraphs of disclaimer in the documentation and/or 15 | other materials provided with the distribution. 16 | 17 | o Neither the name of the Regents nor the names of its contributors 18 | may be used to endorse or promote products derived from this 19 | software without specific prior written permission. 20 | 21 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 22 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 23 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 24 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 | 26 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 27 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 29 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 30 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 31 | MODIFICATIONS. 32 | -------------------------------------------------------------------------------- /src/main/resources/Makefile: -------------------------------------------------------------------------------- 1 | # Chisel parallel make template. 2 | 3 | HFILES = @HFILES@ 4 | ONCEONLY = @ONCEONLY@ 5 | UNOPTIMIZED = @UNOPTIMIZED@ 6 | OPTIMIZED = @OPTIMIZED@ 7 | 8 | EXEC = @EXEC@ 9 | OPTIM0 = @OPTIM0@ 10 | OPTIM1 = @OPTIM1@ 11 | OPTIM2 = @OPTIM2@ 12 | CPPFLAGS = @CPPFLAGS@ 13 | CXXFLAGS = @CXXFLAGS@ 14 | LDFLAGS = @LDFLAGS@ 15 | CXX = @CXX@ 16 | 17 | default: $(EXEC) 18 | 19 | clean: 20 | $(RM) $(EXEC) $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) 21 | 22 | $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED): $(HFILES) 23 | 24 | $(EXEC): $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) Makefile 25 | $(CXX) -o $@ $(filter-out Makefile,$^) 26 | 27 | ifneq (,$(ONCEONLY)) 28 | $(ONCEONLY): %.o: %.cpp 29 | $(CXX) -c -o $@ $(OPTIM0) $(CPPFLAGS) $(CXXFLAGS) $< 30 | endif 31 | 32 | ifneq (,$(UNOPTIMIZED)) 33 | $(UNOPTIMIZED): %.o: %.cpp 34 | $(CXX) -c -o $@ $(OPTIM1) $(CPPFLAGS) $(CXXFLAGS) $< 35 | endif 36 | 37 | ifneq (,$(OPTIMIZED)) 38 | $(OPTIMIZED): %.o: %.cpp 39 | $(CXX) -c -o $@ $(OPTIM2) $(CPPFLAGS) $(CXXFLAGS) $< 40 | endif 41 | -------------------------------------------------------------------------------- /src/main/resources/template.txt: -------------------------------------------------------------------------------- 1 | #include "{!header_file!}" 2 | 3 | // ======================================== 4 | // dat_t needs to have this operator defined, so that 5 | // I'm allowed to use it with System C. 6 | // But be warned: I don't quite know what I 7 | // am doing. 8 | // ======================================== 9 | template 10 | inline ostream& operator << (ostream& os, const dat_t& arg){ 11 | return os; 12 | } 13 | 14 | {!ostream_lsh!} 15 | 16 | SC_MODULE({!name!}){ 17 | {!component_type!}* c; 18 | 19 | // sc_fifo >* in; 20 | {!input_fifos!} 21 | 22 | // sc_fifo >* out; 23 | {!output_fifos!} 24 | 25 | SC_HAS_PROCESS({!name!}); 26 | {!name!}(sc_module_name a_name) : sc_module(a_name) { 27 | // Initialize Component, Clock in RESET 28 | c = new {!component_type!}(); 29 | c->init(); 30 | 31 | // Initialize Output Fifos 32 | // out = new sc_fifo >(1); 33 | {!init_output_fifos!} 34 | 35 | // Clock Initialization? 36 | // Don't understand what this is for. Copied from emulator. 37 | for(int i = 0; i < 5; i++) { 38 | dat_t<1> reset = LIT<1>(1); 39 | c->clock_lo(reset); 40 | c->clock_hi(reset); 41 | } 42 | 43 | //Register Thread 44 | SC_THREAD(component_thread); 45 | } 46 | 47 | void component_thread(void){ 48 | //Buffer for input data 49 | // dat_t<1> in_data; 50 | // int has_in = 0; 51 | {!input_buffers!} 52 | 53 | while(true){ 54 | //Is there input waiting? 55 | // if(!has_in){has_in = in->nb_read(in_data);} 56 | // c->GCD__io_a = in_data; 57 | // c->GCD__io_v1 = LIT<1>(has_in); 58 | {!fill_input!} 59 | 60 | //Are output queues ready? 61 | // c->GCD__io_r2 = LIT<1>(out->num_free() > 0); 62 | {!check_output!} 63 | 64 | //Clock Lo 65 | dat_t<1> reset = LIT<1>(0); 66 | c->clock_lo(reset); 67 | 68 | //Has input been accepted? 69 | // if(c->GCD__io_r1.values[0]) has_in = 0; 70 | {!check_input!} 71 | 72 | //Is output ready? 73 | // if(c->GCD__io_v2.values[0]) out->nb_write(c->GCD__io_z); 74 | {!valid_output!} 75 | 76 | //Clock Hi 77 | wait(1.0, SC_SEC); 78 | c->clock_hi(reset); 79 | } 80 | } 81 | }; 82 | -------------------------------------------------------------------------------- /src/main/resources/vpi.cpp: -------------------------------------------------------------------------------- 1 | #include "vpi.h" 2 | 3 | vpi_api_t* vpi_api = NULL; 4 | 5 | extern "C" { 6 | 7 | PLI_INT32 init_clks_calltf(PLI_BYTE8 *user_data) { 8 | vpi_api->init_clks(); 9 | return 0; 10 | } 11 | 12 | PLI_INT32 init_rsts_calltf(PLI_BYTE8 *user_data) { 13 | vpi_api->init_rsts(); 14 | return 0; 15 | } 16 | 17 | PLI_INT32 init_ins_calltf(PLI_BYTE8 *user_data) { 18 | vpi_api->init_ins(); 19 | return 0; 20 | } 21 | 22 | PLI_INT32 init_outs_calltf(PLI_BYTE8 *user_data) { 23 | vpi_api->init_outs(); 24 | return 0; 25 | } 26 | 27 | PLI_INT32 init_sigs_calltf(PLI_BYTE8 *user_data) { 28 | vpi_api->init_sigs(); 29 | vpi_api->init_channels(); 30 | return 0; 31 | } 32 | 33 | PLI_INT32 tick_calltf(PLI_BYTE8 *user_data) { 34 | vpi_api->tick(); 35 | return 0; 36 | } 37 | 38 | PLI_INT32 tick_compiletf(PLI_BYTE8 *user_data) { 39 | s_cb_data data_s; 40 | data_s.reason = cbStartOfSimulation; 41 | data_s.cb_rtn = sim_start_cb; 42 | data_s.obj = NULL; 43 | data_s.time = NULL; 44 | data_s.value = NULL; 45 | data_s.user_data = NULL; 46 | vpi_free_object(vpi_register_cb(&data_s)); 47 | 48 | data_s.reason = cbEndOfSimulation; 49 | data_s.cb_rtn = sim_end_cb; 50 | data_s.obj = NULL; 51 | data_s.time = NULL; 52 | data_s.value = NULL; 53 | data_s.user_data = NULL; 54 | vpi_free_object(vpi_register_cb(&data_s)); 55 | return 0; 56 | } 57 | 58 | PLI_INT32 sim_start_cb(p_cb_data cb_data) { 59 | vpi_api = new vpi_api_t; 60 | return 0; 61 | } 62 | 63 | PLI_INT32 sim_end_cb(p_cb_data cb_data) { 64 | delete vpi_api; 65 | vpi_control(vpiFinish, 0); 66 | return 0; 67 | } 68 | 69 | PLI_INT32 tick_cb(p_cb_data cb_data) { 70 | vpi_api->tick(); 71 | return 0; 72 | } 73 | 74 | } 75 | -------------------------------------------------------------------------------- /src/main/resources/vpi.tab: -------------------------------------------------------------------------------- 1 | $init_clks call=init_clks_calltf 2 | $init_rsts call=init_rsts_calltf 3 | $init_ins call=init_ins_calltf 4 | $init_outs call=init_outs_calltf 5 | $init_sigs call=init_sigs_calltf 6 | $tick call=tick_calltf check=tick_compiletf acc+=rw,frc:* 7 | -------------------------------------------------------------------------------- /src/main/scala/Aggregate.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | abstract class Aggregate extends Data { 34 | override def getWidth: Int = this.flatten.map(_._2.getWidth).fold(0)(_ + _) 35 | // Aggregate classes do not generally 'live' in the graph so width inference 36 | // will not touch these nodes and thus must get their width by looking 37 | // into the container 38 | override def isWired: Boolean = this.flatten.forall(_._2.isWired) 39 | override def setIsWired(value: Boolean): Unit = this.flatten.map(_._2.setIsWired(value)) 40 | } 41 | -------------------------------------------------------------------------------- /src/main/scala/Binding.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | // used for component to component connections 34 | object Binding { 35 | 36 | def apply(m: Node, c: Module, ioComp: Module): Node = { 37 | c.findBinding(m) match { 38 | case Some(res) => res 39 | case None => { 40 | val res = new Binding(m, ioComp) 41 | res.compOpt = Some(c) 42 | res.init("", Node.widthOf(0), m) 43 | res.infer 44 | c.nodes += res 45 | c.bindings += res 46 | res 47 | } 48 | } 49 | } 50 | } 51 | 52 | class Binding(val targetNode: Node, val targetComponent: Module) extends Node { 53 | 54 | override def toString: String = "BINDING(" + inputs(0) + ", of " + component + ", called " + name + ")"; 55 | } 56 | -------------------------------------------------------------------------------- /src/main/scala/BitPat.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | import Literal._ 33 | 34 | /** A bit pattern object to enable representation of dont cares */ 35 | object BitPat { 36 | /** Get a bit pattern from a string 37 | * @param n a string with format b---- eg) b1?01 38 | * @note legal characters are 0, 1, ? and must be base 2*/ 39 | def apply(n: String): BitPat = { 40 | require(n(0) == 'b', "BINARY BitPats ONLY") 41 | val (bits, mask, swidth) = parseLit(n.substring(1)) 42 | new BitPat(toLitVal(bits, 2), toLitVal(mask, 2), swidth) 43 | } 44 | 45 | /** Get a bit pattern of don't cares with a specified width */ 46 | def DC(width: Int): BitPat = BitPat("b" + ("?" * width)) 47 | 48 | // BitPat <-> UInt 49 | /** enable conversion of a bit pattern to a UInt */ 50 | implicit def BitPatToUInt(x: BitPat): UInt = { 51 | require(x.mask == (BigInt(1) << x.getWidth)-1) 52 | UInt(x.value, x.getWidth) 53 | } 54 | /** create a bit pattern from a UInt */ 55 | implicit def apply(x: UInt): BitPat = { 56 | require(x.isLit) 57 | BitPat("b" + x.litValue().toString(2)) 58 | } 59 | } 60 | 61 | /** A class to create bit patterns 62 | * Use the [[Chisel.BitPat$ BitPat]] object instead of this class directly */ 63 | class BitPat(val value: BigInt, val mask: BigInt, width: Int) { 64 | def getWidth: Int = width 65 | def === (other: Bits): Bool = UInt(value) === (other & UInt(mask)) 66 | @deprecated("Use =/= rather than != for chisel comparison", "3") 67 | def != (other: Bits): Bool = { 68 | ChiselError.check("Chisel3 compatibility: != is deprecated, use =/= instead", Version("3.0")) 69 | !(this === other) 70 | } 71 | def =/= (other: Bits): Bool = !(this === other) 72 | } 73 | -------------------------------------------------------------------------------- /src/main/scala/CSE.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | class CSENode(val node: Node) { 34 | override def hashCode: Int = node.hashCodeForCSE 35 | override def equals(x: Any): Boolean = x match { 36 | case x: CSENode => node.equalsForCSE(x.node) 37 | case _ => false 38 | } 39 | } 40 | 41 | object CSE { 42 | def transform(mod: Module): Unit = { 43 | Driver.components foreach doCSE 44 | } 45 | 46 | private def doCSE(mod: Module): Unit = while (doCSEOnce(mod)) {} 47 | 48 | private def doCSEOnce(mod: Module): Boolean = { 49 | def dontTouch(x: Node, replaceWith: Node) = 50 | !x.name.isEmpty || x.isInObject && !replaceWith.isInObject 51 | val cseNodes = new collection.mutable.LinkedHashMap[CSENode, Node] 52 | val removedNodes = new collection.mutable.LinkedHashMap[Node, Node] 53 | for (n <- mod.nodes) { 54 | if (n.canCSE) { 55 | val cseNode = new CSENode(n) 56 | val cseTo = cseNodes.get(cseNode) 57 | if (cseTo.isEmpty) 58 | cseNodes += cseNode -> n 59 | else if (!dontTouch(n, cseTo.get)) 60 | removedNodes += n -> cseTo.get 61 | else if (!dontTouch(cseTo.get, n)) { 62 | cseNodes += cseNode -> n 63 | removedNodes += cseTo.get -> n 64 | } 65 | } 66 | } 67 | 68 | var removed = false 69 | for (n <- mod.nodes) { 70 | for (i <- 0 until n.inputs.length) { 71 | val in = n.inputs(i) 72 | if (in.component == mod) { 73 | val cseTo = removedNodes.get(in) 74 | if (!cseTo.isEmpty) { 75 | n.inputs(i) = cseTo.get 76 | removed = true 77 | } 78 | } 79 | } 80 | } 81 | removed 82 | } 83 | 84 | def inputsEqual(x: Node, y: Node): Boolean = { 85 | if (x.widthW != y.widthW || x.inputs.length != y.inputs.length) false 86 | else (x.inputs zip y.inputs) forall {case (a, b) => a == b} 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /src/main/scala/Cat.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | object Cat { 34 | /** Combine data elements together 35 | * @param mod Data to combine with 36 | * @param mods any number of other Data elements to be combined in order 37 | * @return A UInt which is all of the bits combined together 38 | */ 39 | def apply[T <: Data](mod: T, mods: T*): UInt = apply(mod :: mods.toList) 40 | /** Combine data elements together 41 | * @param mods any number of other Data elements to be combined in order 42 | * @return A UInt which is all of the bits combined together 43 | */ 44 | def apply[T <: Data](mods: Seq[T]): UInt = 45 | UInt(OUTPUT).fromNode(Concatenate(mods)) 46 | } 47 | 48 | object Concatenate { 49 | /** Combine nodes together 50 | * @param mod Data to combine with 51 | * @param mods any number of other Data elements to be combined in order 52 | * @return A Node which is all of the bits combined together 53 | */ 54 | def apply(mod: Node, mods: Node*): Node = apply(mod :: mods.toList) 55 | /** Combine nodes together 56 | * @param mods any number of other Data elements to be combined in order 57 | * @return A Node which is all of the bits combined together 58 | */ 59 | def apply(mods: Seq[Node]): Node = doCat(mods) 60 | private def doCat(mods: Seq[Node]): Node = 61 | if (mods.tail.isEmpty) mods.head 62 | else BinaryOp(doCat(mods.slice(0, mods.length/2)), doCat(mods.slice(mods.length/2, mods.length)), "##") 63 | } 64 | -------------------------------------------------------------------------------- /src/main/scala/Clock.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | /** Create a new Clock */ 34 | object Clock { 35 | // TODO: make src and period private like Clock Class? 36 | /** @param reset the reset for this clock 37 | * @param src the source clock for this clock 38 | * @param period the period in ps for this clock, implicitClock has period of 1ps 39 | */ 40 | def apply(reset: Bool = Driver.implicitReset, src: Option[Clock] = None, period: Double = 1.0) = { 41 | new Clock(reset, src, period) 42 | } 43 | 44 | // For Chisel3 compatibility. 45 | def apply(dir: IODirection): Clock = { 46 | apply() 47 | } 48 | 49 | implicit def toOption(c: Clock) = Option(c) 50 | } 51 | 52 | /** Create a new clock 53 | * @param reset The reset for this clock 54 | */ 55 | class Clock(reset: Bool = Driver.implicitReset, 56 | private[Chisel] val srcClock: Option[Clock] = None, 57 | private[Chisel] val period: Double = 1.0 /* in ps */) extends Node { 58 | 59 | init("", 1) 60 | Driver.clocks += this 61 | 62 | /** @return a reset pin connected to reset for the component in scope */ 63 | def getReset: Bool = { 64 | if (!Driver.compStack.isEmpty) { 65 | Driver.compStack.top.addResetPin(reset) 66 | } else { 67 | reset 68 | } 69 | } 70 | 71 | override lazy val isInObject: Boolean = true 72 | override lazy val isInVCD: Boolean = Driver.isVCD 73 | 74 | /** multiply the period of the clock 75 | * Will create another clock with the respective period */ 76 | def * (x: Int) = Clock(reset, Some(this), period * x.toDouble) 77 | /** divide the clock period 78 | * Will create another clock with the respective period */ 79 | def / (x: Int) = Clock(reset, Some(this), period / x.toDouble) 80 | 81 | def := (that: Clock): Unit = { 82 | this.getReset := that.getReset 83 | } 84 | } 85 | -------------------------------------------------------------------------------- /src/main/scala/Enum.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | /** An object for creating C style Enums */ 34 | object Enum { 35 | import Literal.sizeof 36 | /** create n enum values of given type for n <= 22 37 | * @param nodeType the type of node to create 38 | * @param n the number of nodes to create 39 | * @example {{{ val s1 :: s2 :: s3 :: Nil = Enum(UInt(), 3) }}} 40 | * @note When declaring vals the first character must be lower case, ie S1 is illegal 41 | * @note The 22 state size limitation is due to the maximum Scala tuple size of 22 (other methods avoid this limitation)*/ 42 | def apply[T <: UInt](nodeType: T, n: Int): List[T] = (Range(0, n, 1).map(x => (Lit(x, sizeof(n-1))(nodeType)))).toList; 43 | 44 | /** create enum values of given type and names 45 | * @param nodeType the type of node to create 46 | * @param l any number of Symbols to create as an Enum 47 | * @return a map from Symbol to the node created*/ 48 | def apply[T <: UInt](nodeType: T, l: Symbol *): Map[Symbol, T] = (l.toList zip (Range(0, l.length, 1).map(x => Lit(x, sizeof(l.length-1))(nodeType)))).toMap; 49 | 50 | /** create enum values of given type and names 51 | * @param nodeType the type of node to create 52 | * @param l a list of symbols 53 | * @return a map of symbols to a node created 54 | * @example {{{ 55 | * val states = Enum(UInt(), List('s1, 's2, 's3)) 56 | * val state = Reg(UInt(), init = states('s1)) 57 | * }}}*/ 58 | def apply[T <: UInt](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip (Range(0, l.length, 1).map(x => Lit(x, sizeof(l.length-1))(nodeType)))).toMap; 59 | 60 | } 61 | -------------------------------------------------------------------------------- /src/main/scala/FPGA.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | /** class with no inline mem */ 34 | class FPGABackend extends VerilogBackend 35 | { 36 | Driver.isInlineMem = false 37 | } 38 | -------------------------------------------------------------------------------- /src/main/scala/IO.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | abstract class IODirection { 34 | def toString: String 35 | } 36 | 37 | /** Define the IODirection INPUT */ 38 | object INPUT extends IODirection { 39 | override def toString = "INPUT" 40 | } 41 | 42 | /** Define the IODirection OUTPUT */ 43 | object OUTPUT extends IODirection { 44 | override def toString = "OUTPUT" 45 | } 46 | 47 | /** Define the IODirection NODIR */ 48 | object NODIR extends IODirection { 49 | override def toString = "NODIR" 50 | } 51 | -------------------------------------------------------------------------------- /src/main/scala/ImplicitConversions.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | object ImplicitConversions { 34 | 35 | implicit def intToUInt(x: Int): UInt = UInt(x) 36 | @deprecated("It is not advisable to use implicit conversion between Boolean and Bool", "3") 37 | implicit def booleanToBool(x: Boolean): Bool = Bool(x) 38 | 39 | // These ones for the lazy programmer. 40 | implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false 41 | implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 42 | 43 | } 44 | -------------------------------------------------------------------------------- /src/main/scala/Insert.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | class Insert(tgt: Bits, bit: UInt, length: Int) extends proc { 34 | override def procAssign(src: Node): Unit = { 35 | tgt.nextOpt match { 36 | case None => ChiselError.error("Subword assignment requires a default value to have been assigned") 37 | case Some(next) => 38 | val mask = UInt((BigInt(1) << length) - 1, length) 39 | val shiftedMask = (mask << bit).zext // zero-extend to tgt.width 40 | val fill = 41 | if (length == 1) src.asInstanceOf[Bits].toBool.toSInt & shiftedMask 42 | else (src.asInstanceOf[Bits] & mask) << bit 43 | tgt := UInt(next) & ~shiftedMask | fill 44 | } 45 | } 46 | 47 | // Chisel3 - this node contains data - used for verifying Wire() wrapping 48 | override def isTypeOnly = false 49 | } 50 | -------------------------------------------------------------------------------- /src/main/scala/Lookup.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel 32 | 33 | object ListLookup { 34 | def apply[U, T <: Data](addr: UInt, default: List[T], mapping: Array[(U, List[T])]): List[T] = { 35 | val map = mapping.map { 36 | case (x: BitPat, y) => (addr === x, y) 37 | case (x: UInt, y) => (addr === x, y) 38 | case _ => throwException("Not allowed type for mapping") 39 | } 40 | default.zipWithIndex map { case (d, i) => 41 | map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n)) 42 | } 43 | } 44 | } 45 | 46 | object Lookup { 47 | def apply[U, T <: Bits](addr: UInt, default: T, mapping: Seq[(U, T)]): T = 48 | ListLookup(addr, List(default), mapping.map(m => (m._1, List(m._2))).toArray).head 49 | } 50 | -------------------------------------------------------------------------------- /src/main/scala/iotesters/ChiselSpec.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package Chisel.iotesters 4 | 5 | //import Chisel._ 6 | import Chisel.testers.{BasicTester, TesterDriver} 7 | //import java.io.File 8 | 9 | import org.scalatest._ 10 | import org.scalatest.prop._ 11 | import org.scalacheck._ 12 | 13 | /** Common utility functions for Chisel unit tests. */ 14 | trait ChiselRunners extends Assertions { 15 | val backends = TesterDriver.backends 16 | implicit val testArgs = Driver.testArgs 17 | def runTester(t: => BasicTester): Boolean = { 18 | TesterDriver.execute(() => t) 19 | } 20 | def assertTesterPasses(t: => BasicTester): Unit = { 21 | assert(runTester(t)) 22 | } 23 | def assertTesterFails(t: => BasicTester): Unit = { 24 | assert(!runTester(t)) 25 | } 26 | // def elaborate(t: => Module): Unit = Driver.elaborate(() => t) 27 | 28 | } 29 | 30 | /** Spec base class for BDD-style testers. */ 31 | class ChiselFlatSpec extends FlatSpec with ChiselRunners with Matchers 32 | 33 | /** Spec base class for property-based testers. */ 34 | class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks { 35 | 36 | // Constrain the default number of instances generated for every use of forAll. 37 | implicit override val generatorDrivenConfig = 38 | PropertyCheckConfig(minSuccessful = 8, minSize = 1, maxSize = 4) 39 | 40 | // Generator for small positive integers. 41 | val smallPosInts = Gen.choose(1, 4) 42 | 43 | // Generator for widths considered "safe". 44 | val safeUIntWidth = Gen.choose(1, 30) 45 | 46 | // Generators for integers that fit within "safe" widths. 47 | val safeUInts = Gen.choose(0, (1 << 30)) 48 | 49 | // Generators for vector sizes. 50 | val vecSizes = Gen.choose(0, 4) 51 | 52 | // Generator for string representing an arbitrary integer. 53 | val binaryString = for (i <- Arbitrary.arbitrary[Int]) yield "b" + i.toBinaryString 54 | 55 | // Generator for a sequence of Booleans of size n. 56 | def enSequence(n: Int): Gen[List[Boolean]] = Gen.containerOfN[List, Boolean](n, Gen.oneOf(true, false)) 57 | 58 | // Generator which gives a width w and a list (of size n) of numbers up to w bits. 59 | def safeUIntN(n: Int): Gen[(Int, List[Int])] = for { 60 | w <- smallPosInts 61 | i <- Gen.containerOfN[List, Int](n, Gen.choose(0, (1 << w) - 1)) 62 | } yield (w, i) 63 | 64 | // Generator which gives a width w and a numbers up to w bits. 65 | val safeUInt = for { 66 | w <- smallPosInts 67 | i <- Gen.choose(0, (1 << w) - 1) 68 | } yield (w, i) 69 | 70 | // Generator which gives a width w and a list (of size n) of a pair of numbers up to w bits. 71 | def safeUIntPairN(n: Int): Gen[(Int, List[(Int, Int)])] = for { 72 | w <- smallPosInts 73 | i <- Gen.containerOfN[List, Int](n, Gen.choose(0, (1 << w) - 1)) 74 | j <- Gen.containerOfN[List, Int](n, Gen.choose(0, (1 << w) - 1)) 75 | } yield (w, i zip j) 76 | 77 | // Generator which gives a width w and a pair of numbers up to w bits. 78 | val safeUIntPair = for { 79 | w <- smallPosInts 80 | i <- Gen.choose(0, (1 << w) - 1) 81 | j <- Gen.choose(0, (1 << w) - 1) 82 | } yield (w, i, j) 83 | } 84 | -------------------------------------------------------------------------------- /src/main/scala/iotesters/Driver.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel.iotesters 32 | 33 | import Chisel.{Backend => ChiselBackend} 34 | import Chisel._ 35 | 36 | object Driver { 37 | val basicTestArgs = Array[String]("--compile", "--genHarness", "--test") ++ chiselEnvironmentArguments() 38 | var backendName: Option[String] = None 39 | def testArgs: Array[String] = basicTestArgs ++ (if (backendName != None) { 40 | Array("--backend", backendName.get) 41 | } else { 42 | Array[String]() 43 | }) 44 | 45 | def apply[T <: Module](dutGen: () => T, backendType: String = "")(testerGen: T => PeekPokeTester[T]): Boolean = { 46 | // Save the current backend name. 47 | if (backendType != "") { 48 | backendName = Some(backendType) 49 | } 50 | val res: Boolean = { 51 | try { 52 | // val oldTesterGen = testerGen(_: T, None) 53 | chiselMain.run(testArgs, dutGen, testerGen) 54 | true 55 | } 56 | catch { 57 | case e: Throwable => false 58 | } 59 | } 60 | res 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /src/main/scala/iotesters/HWIOTester.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel.iotesters 32 | 33 | import Chisel._ 34 | import Chisel.testers.BasicTester 35 | 36 | // scalastyle:off regex 37 | // scalastyle:off method.name 38 | /** 39 | * provide common facilities for step based testing and decoupled interface testing 40 | */ 41 | abstract class HWIOTester extends BasicTester { 42 | val device_under_test: Module 43 | var io_info: IOAccessor = null 44 | def finish(): Unit 45 | 46 | def int(x: Bits): BigInt = x.litValue() 47 | 48 | override val io = new Bundle { 49 | val running = Bool(INPUT) 50 | val error = Bool(OUTPUT) 51 | val pc = UInt(OUTPUT, 32) 52 | val done = Bool(OUTPUT) 53 | } 54 | io.done := setDone 55 | io.error := setError 56 | 57 | val rnd = new scala.util.Random(Chisel.Driver.testerSeed) 58 | 59 | var enable_scala_debug = false 60 | var enable_printf_debug = false 61 | var enable_all_debug = false 62 | 63 | def logScalaDebug(msg: => String): Unit = { 64 | //noinspection ScalaStyle 65 | if(enable_all_debug || enable_scala_debug) println(msg) 66 | } 67 | 68 | def logPrintfDebug(fmt: String, args: Bits*): Unit = { 69 | if(enable_all_debug || enable_scala_debug) printf(fmt, args :_*) 70 | } 71 | } 72 | -------------------------------------------------------------------------------- /src/main/scala/iotesters/PeekPokeTester.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel.iotesters 32 | 33 | import Chisel.{ Backend => ChiselBackend } 34 | import Chisel._ 35 | 36 | class Backend 37 | 38 | class PeekPokeTester[+T <: Module]( 39 | val dut: T, 40 | verbose: Boolean = true, 41 | _base: Int = 16, 42 | logFile: Option[String] = None, 43 | waveform: Option[String] = None, 44 | _backend: Option[Backend] = None, 45 | _seed: Long = System.currentTimeMillis 46 | ) extends Tester[T](dut, verbose, _base) 47 | 48 | object runPeekPokeTester { 49 | def apply[T <: Module](dutGen: () => T, backendType: String = "")(testerGen: (T, Option[Backend]) => PeekPokeTester[T]): Boolean = { 50 | val testArgs = Array[String]("--backend", "c", "--compile", "--genHarness", "--test") ++ chiselEnvironmentArguments() 51 | val res: Boolean = { 52 | try { 53 | val oldTesterGen = testerGen(_: T, None) 54 | chiselMainTest(testArgs, dutGen)(oldTesterGen) 55 | true 56 | } 57 | catch { 58 | case e: Throwable => false 59 | } 60 | } 61 | res 62 | } 63 | } 64 | -------------------------------------------------------------------------------- /src/main/scala/package.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package object Chisel { 32 | import Chisel.Width 33 | implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { 34 | def U: UInt = UInt(x) 35 | def S: SInt = SInt(x) 36 | } 37 | implicit class fromIntToLiteral(val x: Int) extends AnyVal { 38 | def U: UInt = UInt(BigInt(x)) 39 | def S: SInt = SInt(BigInt(x)) 40 | } 41 | implicit class fromStringToLiteral(val x: String) extends AnyVal { 42 | def U: UInt = UInt(x) 43 | } 44 | implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { 45 | def B: Bool = Bool(x) 46 | } 47 | // Chisel3 compatibility. 48 | object Input { 49 | def apply[T<:Data](source: T): T = source.asInput() 50 | } 51 | object Output { 52 | def apply[T<:Data](source: T): T = source.asOutput() 53 | } 54 | object Flipped { 55 | def apply[T<:Data](source: T): T = source.flip() 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /src/main/scala/testers/BasicTester.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel.testers 32 | import Chisel._ 33 | 34 | // In Chisel2, the BasicTester has an IO interface which it uses to communicate with the Chisel2 Tester Scala code. 35 | class BasicTester extends Module { 36 | 37 | val io = new Bundle { 38 | val running = Bool(INPUT) 39 | val error = Bool(OUTPUT) 40 | val pc = UInt(OUTPUT, 32) 41 | val done = Bool(OUTPUT) 42 | } 43 | 44 | val setDone = Reg(init = Bool(false)) 45 | val setError = Reg(init = Bool(false)) 46 | 47 | def popCount(n: Long): Int = n.toBinaryString.count(_=='1') 48 | 49 | /** Ends the test reporting success. 50 | * 51 | * Does not fire when in reset (defined as the encapsulating Module's 52 | * reset). If your definition of reset is not the encapsulating Module's 53 | * reset, you will need to gate this externally. 54 | */ 55 | def stop() { 56 | when (!reset) { 57 | setDone := Bool(true) 58 | printf("STOP %d\n", io.done) 59 | } 60 | } 61 | 62 | def error(message: String = "") { 63 | setError := Bool(true) 64 | printf("ERROR: %s\n".format(message)) 65 | stop() 66 | } 67 | 68 | def finish(): Unit = {} 69 | } 70 | -------------------------------------------------------------------------------- /src/main/scala/testers/TesterDriver.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | package Chisel.testers 32 | 33 | import Chisel._ 34 | import scala.io.Source 35 | import scala.sys.process._ 36 | import java.io._ 37 | 38 | // Wrapper to run Chisel3-style testers in Chisel2. 39 | 40 | object TesterDriver { 41 | def execute(t: () => BasicTester)(implicit testArgs: Array[String]): Boolean = { 42 | try { 43 | // Construct the combined circuit, containing all the required 44 | // poke()'s and expect()'s as arrays of data. 45 | val mod = Driver(testArgs, finishWrapper(t), false) 46 | if (Driver.isTesting) { 47 | // Initialize a tester with tracing turned on. 48 | val c = new Tester(mod, true) 49 | // Run the testing circuit until we see io.done. 50 | while(c.peek(mod.io.done) == 0) { 51 | c.step(1) 52 | } 53 | val error = c.peek(mod.io.error) 54 | val pc = c.peek(mod.io.pc) 55 | if (error != 0) { 56 | c.fail 57 | } 58 | 59 | // Do an additional step to get any printf output. 60 | c.step(1) 61 | c.finish 62 | } 63 | Driver.done 64 | true 65 | } catch { 66 | case e: Throwable => 67 | println(e) 68 | false 69 | } 70 | } 71 | 72 | def elaborate(t: () => BasicTester)(implicit testArgs: Array[String]): Module = { 73 | val mod = Driver(testArgs, finishWrapper(t), false) 74 | mod 75 | } 76 | 77 | def finishWrapper(test: () => BasicTester): () => BasicTester = { 78 | () => { 79 | val tester = test() 80 | tester.finish() 81 | tester 82 | } 83 | } 84 | 85 | val backends = List("c") ++ {if (Driver.isVCSAvailable) "v" :: Nil else Nil} 86 | } 87 | -------------------------------------------------------------------------------- /src/test/resources/AddFilterSysCdriver.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | using namespace std; 3 | using namespace sc_core; 4 | using namespace sc_dt; 5 | #include "SCWrappedAddFilter.cpp" 6 | 7 | SC_MODULE(Counter){ 8 | sc_fifo > out; 9 | 10 | SC_HAS_PROCESS(Counter); 11 | Counter(sc_module_name a_name) : sc_module(a_name), out(1){ 12 | SC_THREAD(counter_thread); 13 | } 14 | 15 | void counter_thread(void){ 16 | for(int i=1; i<100; i++){ 17 | out.write(i); 18 | wait(20.0, SC_SEC); 19 | } 20 | } 21 | }; 22 | 23 | SC_MODULE(Eater){ 24 | sc_fifo >* in; 25 | 26 | SC_HAS_PROCESS(Eater); 27 | Eater(sc_module_name a_name) : sc_module(a_name){ 28 | SC_THREAD(eater_thread); 29 | } 30 | 31 | void eater_thread(void){ 32 | while(true){ 33 | dat_t<4> data = in->read(); 34 | printf("Output = %llu\n", data.values[0]); 35 | } 36 | } 37 | }; 38 | 39 | int sc_main(int sc_argc, char* sc_argv[1]){ 40 | 41 | //Create components 42 | Counter counter("mycounter"); 43 | Eater eater("muncher"); 44 | SCWrappedAddFilter filter("myfilter"); 45 | 46 | //Connect components 47 | filter.a = &counter.out; 48 | eater.in = filter.b; 49 | 50 | 51 | //Simulate 52 | sc_start(1000.0, SC_SEC); 53 | return 0; 54 | } 55 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_A_4.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_A_4(input clk, 2 | output[7:0] io_status_im, 3 | output[6:0] io_status_zero, 4 | output io_status_vm, 5 | output io_status_s64, 6 | output io_status_u64, 7 | output io_status_s, 8 | output io_status_ps, 9 | output io_status_ec, 10 | output io_status_ev, 11 | output io_status_ef, 12 | output io_status_et, 13 | input io_wen, 14 | input [31:0] io_wdata 15 | ); 16 | 17 | reg[0:0] reg_status_et; 18 | wire T0; 19 | reg[0:0] reg_status_ef; 20 | wire T1; 21 | reg[0:0] reg_status_ev; 22 | wire T2; 23 | reg[0:0] reg_status_ec; 24 | wire T3; 25 | reg[0:0] reg_status_ps; 26 | wire T4; 27 | reg[0:0] reg_status_s; 28 | wire T5; 29 | reg[0:0] reg_status_u64; 30 | wire T6; 31 | reg[0:0] reg_status_s64; 32 | wire T7; 33 | reg[0:0] reg_status_vm; 34 | wire T8; 35 | reg[6:0] reg_status_zero; 36 | wire[6:0] T9; 37 | reg[7:0] reg_status_im; 38 | wire[7:0] T10; 39 | 40 | assign io_status_et = reg_status_et; 41 | assign T0 = io_wdata[1'h0:1'h0]; 42 | assign io_status_ef = reg_status_ef; 43 | assign T1 = io_wdata[1'h1:1'h1]; 44 | assign io_status_ev = reg_status_ev; 45 | assign T2 = io_wdata[2'h2:2'h2]; 46 | assign io_status_ec = reg_status_ec; 47 | assign T3 = io_wdata[2'h3:2'h3]; 48 | assign io_status_ps = reg_status_ps; 49 | assign T4 = io_wdata[3'h4:3'h4]; 50 | assign io_status_s = reg_status_s; 51 | assign T5 = io_wdata[3'h5:3'h5]; 52 | assign io_status_u64 = reg_status_u64; 53 | assign T6 = io_wdata[3'h6:3'h6]; 54 | assign io_status_s64 = reg_status_s64; 55 | assign T7 = io_wdata[3'h7:3'h7]; 56 | assign io_status_vm = reg_status_vm; 57 | assign T8 = io_wdata[4'h8:4'h8]; 58 | assign io_status_zero = reg_status_zero; 59 | assign T9 = io_wdata[4'hf:4'h9]; 60 | assign io_status_im = reg_status_im; 61 | assign T10 = io_wdata[5'h17:5'h10]; 62 | 63 | always @(posedge clk) begin 64 | if(io_wen) begin 65 | reg_status_et <= T0; 66 | end 67 | if(io_wen) begin 68 | reg_status_ef <= T1; 69 | end 70 | if(io_wen) begin 71 | reg_status_ev <= T2; 72 | end 73 | if(io_wen) begin 74 | reg_status_ec <= T3; 75 | end 76 | if(io_wen) begin 77 | reg_status_ps <= T4; 78 | end 79 | if(io_wen) begin 80 | reg_status_s <= T5; 81 | end 82 | if(io_wen) begin 83 | reg_status_u64 <= T6; 84 | end 85 | if(io_wen) begin 86 | reg_status_s64 <= T7; 87 | end 88 | if(io_wen) begin 89 | reg_status_vm <= T8; 90 | end 91 | if(io_wen) begin 92 | reg_status_zero <= T9; 93 | end 94 | if(io_wen) begin 95 | reg_status_im <= T10; 96 | end 97 | end 98 | endmodule 99 | 100 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_InstanceSuperclass_1.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_A_3( 2 | input io_a_in, 3 | output io_a_out 4 | ); 5 | 6 | 7 | assign io_a_out = io_a_in; 8 | endmodule 9 | 10 | module ConnectSuite_InstanceSuperclass_1( 11 | input io_a_in, 12 | output io_a_out 13 | ); 14 | 15 | 16 | assign io_a_out = io_a_in; 17 | ConnectSuite_A_3 aInBComp( 18 | .io_a_in( io_a_in ) 19 | //.io_a_out( ) 20 | ); 21 | endmodule 22 | 23 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_LogicBtwInstances_1.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_A_2( 2 | input io_a_in, 3 | output io_a_out 4 | ); 5 | 6 | 7 | assign io_a_out = io_a_in; 8 | endmodule 9 | 10 | module ConnectSuite_LogicBtwInstances_1(input clk, 11 | input io_b_in, 12 | output io_b_out 13 | ); 14 | 15 | wire T0; 16 | reg[0:0] x; 17 | wire T1; 18 | wire a2_io_a_out; 19 | wire a1_io_a_out; 20 | 21 | assign io_b_out = T0; 22 | assign T0 = T1 | x; 23 | assign T1 = a1_io_a_out | a2_io_a_out; 24 | ConnectSuite_A_2 a1( 25 | .io_a_in( io_b_in ), 26 | .io_a_out( a1_io_a_out ) 27 | ); 28 | ConnectSuite_A_2 a2( 29 | .io_a_in( io_b_in ), 30 | .io_a_out( a2_io_a_out ) 31 | ); 32 | 33 | always @(posedge clk) begin 34 | x <= io_b_in; 35 | end 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_NoClassRelation_1.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_A_1( 2 | input io_a_in, 3 | output io_a_out 4 | ); 5 | 6 | 7 | assign io_a_out = io_a_in; 8 | endmodule 9 | 10 | module ConnectSuite_B_1( 11 | input io_b_in, 12 | output io_b_out 13 | ); 14 | 15 | wire aComp_io_a_out; 16 | 17 | assign io_b_out = aComp_io_a_out; 18 | ConnectSuite_A_1 aComp( 19 | .io_a_in( io_b_in ), 20 | .io_a_out( aComp_io_a_out ) 21 | ); 22 | endmodule 23 | 24 | module ConnectSuite_NoClassRelation_1( 25 | input io_c_in, 26 | output io_c_out 27 | ); 28 | 29 | wire aComp_io_b_out; 30 | 31 | assign io_c_out = aComp_io_b_out; 32 | ConnectSuite_B_1 aComp( 33 | .io_b_in( io_c_in ), 34 | .io_b_out( aComp_io_b_out ) 35 | ); 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_SubmoduleInputUse_1.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_PassThrough_1( 2 | input [7:0] io_ptin, 3 | output[7:0] io_ptout 4 | ); 5 | 6 | 7 | 8 | assign io_ptout = io_ptin; 9 | endmodule 10 | 11 | module ConnectSuite_SubmoduleInputUse_1( 12 | input [7:0] io_in, 13 | output[7:0] io_out1, 14 | output[7:0] io_out2a, 15 | output[7:0] io_out2b, 16 | output[7:0] io_out3 17 | ); 18 | 19 | wire[7:0] pt3_io_ptout; 20 | wire[7:0] pt2b_io_ptout; 21 | wire[7:0] pt2a_io_ptout; 22 | wire[7:0] pt1_io_ptout; 23 | 24 | 25 | assign io_out3 = pt3_io_ptout; 26 | assign io_out2b = pt2b_io_ptout; 27 | assign io_out2a = pt2a_io_ptout; 28 | assign io_out1 = pt1_io_ptout; 29 | ConnectSuite_PassThrough_1 pt3( 30 | .io_ptin( io_out2b ), 31 | .io_ptout( pt3_io_ptout ) 32 | ); 33 | ConnectSuite_PassThrough_1 pt2b( 34 | .io_ptin( pt1_io_ptout ), 35 | .io_ptout( pt2b_io_ptout ) 36 | ); 37 | ConnectSuite_PassThrough_1 pt2a( 38 | .io_ptin( pt1_io_ptout ), 39 | .io_ptout( pt2a_io_ptout ) 40 | ); 41 | ConnectSuite_PassThrough_1 pt1( 42 | .io_ptin( io_in ), 43 | .io_ptout( pt1_io_ptout ) 44 | ); 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_SuppliesResetsParent_1.v: -------------------------------------------------------------------------------- 1 | module Queue(input clk, input reset, 2 | output io_enq_ready, 3 | input io_enq_valid, 4 | input io_enq_bits, 5 | input io_deq_ready, 6 | output io_deq_valid, 7 | output io_deq_bits, 8 | output io_count 9 | ); 10 | 11 | wire T0; 12 | wire[2:0] T1; 13 | reg[0:0] maybe_full; 14 | wire T2; 15 | wire do_deq; 16 | wire T3; 17 | wire do_flow; 18 | wire T4; 19 | wire do_enq; 20 | wire T5; 21 | wire T6; 22 | wire T7; 23 | reg [0:0] ram [0:0]; 24 | wire T8; 25 | wire T9; 26 | wire T10; 27 | wire empty; 28 | wire T11; 29 | 30 | assign io_count = T0; 31 | assign T0 = T1[1'h0/* 0*/:1'h0/* 0*/]; 32 | assign T1 = {maybe_full, 2'h0/* 0*/}; 33 | assign T2 = do_enq != do_deq; 34 | assign do_deq = T4 && T3; 35 | assign T3 = ! do_flow; 36 | assign do_flow = 1'h0/* 0*/; 37 | assign T4 = io_deq_ready && io_deq_valid; 38 | assign do_enq = T6 && T5; 39 | assign T5 = ! do_flow; 40 | assign T6 = io_enq_ready && io_enq_valid; 41 | assign io_deq_bits = T7; 42 | assign T7 = ram[1'h0/* 0*/]; 43 | assign T9 = io_enq_bits; 44 | assign io_deq_valid = T10; 45 | assign T10 = ! empty; 46 | assign empty = ! maybe_full; 47 | assign io_enq_ready = T11; 48 | assign T11 = ! maybe_full; 49 | 50 | always @(posedge clk) begin 51 | if(reset) begin 52 | maybe_full <= 1'h0/* 0*/; 53 | end else if(T2) begin 54 | maybe_full <= do_enq; 55 | end 56 | if (do_enq) 57 | ram[1'h0/* 0*/] <= T9; 58 | end 59 | endmodule 60 | 61 | module ConnectSuite_UsesReset_2(input clk, input reset, 62 | input io_in, 63 | output io_out 64 | ); 65 | 66 | wire T0; 67 | wire q_io_deq_bits; 68 | 69 | assign io_out = T0; 70 | assign T0 = q_io_deq_bits || reset; 71 | Queue q(.clk(clk), .reset(reset), 72 | //.io_enq_ready( ) 73 | .io_enq_valid( 1'h1/* 1*/ ), 74 | .io_enq_bits( io_in ), 75 | .io_deq_ready( 1'h1/* 1*/ ), 76 | //.io_deq_valid( ) 77 | .io_deq_bits( q_io_deq_bits ) 78 | //.io_count( ) 79 | ); 80 | endmodule 81 | 82 | module ConnectSuite_SuppliesResets_1(input clk, input reset, 83 | input io_in, 84 | output io_out 85 | ); 86 | 87 | reg[0:0] R0; 88 | reg[0:0] delayed; 89 | wire T1; 90 | wire T2; 91 | wire a2_io_out; 92 | wire T3; 93 | wire a1_io_out; 94 | wire a0_io_out; 95 | 96 | assign io_out = T1; 97 | assign T1 = T2 || delayed; 98 | assign T2 = T3 || a2_io_out; 99 | assign T3 = a0_io_out || a1_io_out; 100 | ConnectSuite_UsesReset_2 a0(.clk(clk), .reset(reset), 101 | .io_in( io_in ), 102 | .io_out( a0_io_out ) 103 | ); 104 | ConnectSuite_UsesReset_2 a1(.clk(clk), .reset(delayed), 105 | .io_in( io_in ), 106 | .io_out( a1_io_out ) 107 | ); 108 | ConnectSuite_UsesReset_2 a2(.clk(clk), .reset(R0), 109 | .io_in( io_in ), 110 | .io_out( a2_io_out ) 111 | ); 112 | 113 | always @(posedge clk) begin 114 | R0 <= reset; 115 | delayed <= reset; 116 | end 117 | endmodule 118 | 119 | module ConnectSuite_SuppliesResetsParent_1(input clk, input reset, 120 | input io_in, 121 | output io_out 122 | ); 123 | 124 | wire srs_io_out; 125 | 126 | assign io_out = srs_io_out; 127 | ConnectSuite_SuppliesResets_1 srs(.clk(clk), .reset(reset), 128 | .io_in( io_in ), 129 | .io_out( srs_io_out ) 130 | ); 131 | endmodule 132 | 133 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_UnconnectedIOs_1.h: -------------------------------------------------------------------------------- 1 | #ifndef __ConnectSuite_UnconnectedIOs_1__ 2 | #define __ConnectSuite_UnconnectedIOs_1__ 3 | 4 | #include "emulator.h" 5 | 6 | class ConnectSuite_UnconnectedIOs_1_t : public mod_t { 7 | private: 8 | val_t __rand_seed; 9 | void __srand(val_t seed) { __rand_seed = seed; } 10 | val_t __rand_val() { return ::__rand_val(&__rand_seed); } 11 | public: 12 | dat_t<1> ConnectSuite_UnconnectedIOs_1__io_in; 13 | dat_t<1> ConnectSuite_UnconnectedIOs_1_sub__io_in; 14 | dat_t<1> ConnectSuite_UnconnectedIOs_1_sub__reset; 15 | dat_t<1> T0; 16 | dat_t<1> ConnectSuite_UnconnectedIOs_1_sub__r; 17 | dat_t<1> ConnectSuite_UnconnectedIOs_1_sub__io_ncOut; 18 | dat_t<1> ConnectSuite_UnconnectedIOs_1_sub__io_out; 19 | dat_t<1> ConnectSuite_UnconnectedIOs_1__io_out; 20 | dat_t<1> ConnectSuite_UnconnectedIOs_1__io_ncOut; 21 | dat_t<1> reset; 22 | dat_t<1> ConnectSuite_UnconnectedIOs_1__regs_0; 23 | dat_t<1> ConnectSuite_UnconnectedIOs_1__regs_1; 24 | dat_t<1> ConnectSuite_UnconnectedIOs_1__regs_2; 25 | dat_t<1> ConnectSuite_UnconnectedIOs_1__io_ncIn; 26 | clk_t clk; 27 | 28 | void init ( val_t rand_init = 0 ); 29 | void clock_lo ( dat_t<1> reset, bool assert_fire=true ); 30 | void clock_hi ( dat_t<1> reset ); 31 | int clock ( dat_t<1> reset ); 32 | void print ( FILE* f ); 33 | void print ( std::ostream& s ); 34 | void dump ( FILE* f, val_t t, dat_t<1> reset=LIT<1>(0) ); 35 | void dump_init ( FILE* f ); 36 | 37 | }; 38 | 39 | 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_UnconnectedResets_1.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_SubModule_1(input clk, input reset, 2 | input io_in, 3 | output io_out 4 | ); 5 | 6 | reg r; 7 | wire T0; 8 | 9 | `ifndef SYNTHESIS 10 | // synthesis translate_off 11 | integer initvar; 12 | initial begin 13 | #0.002; 14 | r = {1{$random}}; 15 | end 16 | // synthesis translate_on 17 | `endif 18 | 19 | assign io_out = r; 20 | assign T0 = reset ? 1'h1 : io_in; 21 | 22 | always @(posedge clk) begin 23 | if(reset) begin 24 | r <= 1'h1; 25 | end else begin 26 | r <= io_in; 27 | end 28 | end 29 | endmodule 30 | 31 | module ConnectSuite_UnconnectedResets_1(input clk, input reset, 32 | input io_in, 33 | output io_out 34 | ); 35 | 36 | reg regs_2; 37 | reg regs_1; 38 | reg regs_0; 39 | wire sub_io_out; 40 | 41 | `ifndef SYNTHESIS 42 | // synthesis translate_off 43 | integer initvar; 44 | initial begin 45 | #0.002; 46 | regs_2 = {1{$random}}; 47 | regs_1 = {1{$random}}; 48 | regs_0 = {1{$random}}; 49 | end 50 | // synthesis translate_on 51 | `endif 52 | 53 | assign io_out = sub_io_out; 54 | ConnectSuite_SubModule_1 sub(.clk(clk), .reset(regs_2), 55 | .io_in( io_in ), 56 | .io_out( sub_io_out ) 57 | ); 58 | 59 | always @(posedge clk) begin 60 | regs_2 <= regs_1; 61 | regs_1 <= regs_0; 62 | regs_0 <= reset; 63 | end 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_UnspecifiedBundleValues_1.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_UnspecifiedBundleValues_1(input clk, input reset, 2 | input io_in_a, 3 | input io_in_b, 4 | input io_something, 5 | output io_out 6 | ); 7 | 8 | wire T0; 9 | wire[103:0] T1; 10 | wire T2; 11 | reg my_reg_b; 12 | wire T3; 13 | wire T7; 14 | wire T4; 15 | reg my_reg_a; 16 | wire T5; 17 | wire T8; 18 | wire T6; 19 | 20 | `ifndef SYNTHESIS 21 | // synthesis translate_off 22 | integer initvar; 23 | initial begin 24 | #0.002; 25 | my_reg_b = {1{$random}}; 26 | my_reg_a = {1{$random}}; 27 | end 28 | // synthesis translate_on 29 | `endif 30 | 31 | `ifndef SYNTHESIS 32 | // synthesis translate_off 33 | assign T3 = {1{$random}}; 34 | // synthesis translate_on 35 | `endif 36 | assign T0 = reset ^ 1'h1; 37 | assign io_out = T2; 38 | assign T2 = my_reg_a | my_reg_b; 39 | assign T7 = reset ? T3 : T4; 40 | assign T4 = io_something ? io_in_b : my_reg_b; 41 | assign T5 = 1'h0; 42 | assign T8 = reset ? T5 : T6; 43 | assign T6 = io_something ? io_in_a : my_reg_a; 44 | 45 | always @(posedge clk) begin 46 | if(reset) begin 47 | my_reg_b <= T3; 48 | end else if(io_something) begin 49 | my_reg_b <= io_in_b; 50 | end 51 | if(reset) begin 52 | my_reg_a <= T5; 53 | end else if(io_something) begin 54 | my_reg_a <= io_in_a; 55 | end 56 | `ifndef SYNTHESIS 57 | // synthesis translate_off 58 | `ifdef PRINTF_COND 59 | if (`PRINTF_COND) 60 | `endif 61 | if (T0) 62 | $fwrite(32'h80000002, "Hello World!\n"); 63 | // synthesis translate_on 64 | `endif 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /src/test/resources/ConnectSuite_UsesShimParent_1.v: -------------------------------------------------------------------------------- 1 | module ConnectSuite_UsesShim_1( 2 | output io_in_ready, 3 | input io_in_valid, 4 | input io_in_bits, 5 | input io_out_ready, 6 | output io_out_valid, 7 | output io_out_bits 8 | ); 9 | 10 | wire s_bits; 11 | wire T0; 12 | wire s_valid; 13 | wire s_ready; 14 | 15 | assign io_out_bits = s_bits; 16 | assign s_bits = T0; 17 | assign T0 = io_in_bits + 1'h1; 18 | assign io_out_valid = s_valid; 19 | assign s_valid = io_in_valid; 20 | assign io_in_ready = s_ready; 21 | assign s_ready = io_out_ready; 22 | endmodule 23 | 24 | module ConnectSuite_UsesShimParent_1( 25 | output io_in_ready, 26 | input io_in_valid, 27 | input io_in_bits, 28 | input io_out_ready, 29 | output io_out_valid, 30 | output io_out_bits 31 | ); 32 | 33 | wire us_io_out_bits; 34 | wire us_io_out_valid; 35 | wire us_io_in_ready; 36 | 37 | assign io_out_bits = us_io_out_bits; 38 | assign io_out_valid = us_io_out_valid; 39 | assign io_in_ready = us_io_in_ready; 40 | ConnectSuite_UsesShim_1 us( 41 | .io_in_ready( us_io_in_ready ), 42 | .io_in_valid( io_in_valid ), 43 | .io_in_bits( io_in_bits ), 44 | .io_out_ready( io_out_ready ), 45 | .io_out_valid( us_io_out_valid ), 46 | .io_out_bits( us_io_out_bits ) 47 | ); 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /src/test/resources/DataSuite_BypassDataComp_1.h: -------------------------------------------------------------------------------- 1 | #ifndef __DataSuite_BypassDataComp_1__ 2 | #define __DataSuite_BypassDataComp_1__ 3 | 4 | #include "emulator.h" 5 | 6 | class DataSuite_BypassDataComp_1_t : public mod_t { 7 | private: 8 | val_t __rand_seed; 9 | void __srand(val_t seed) { __rand_seed = seed; } 10 | val_t __rand_val() { return ::__rand_val(&__rand_seed); } 11 | public: 12 | dat_t<1> DataSuite_BypassDataComp_1__io_valid_0; 13 | dat_t<1> DataSuite_BypassDataComp_1__io_valid_1; 14 | dat_t<1> DataSuite_BypassDataComp_1__io_valid_2; 15 | dat_t<3> DataSuite_BypassDataComp_1__io_data; 16 | int clk; 17 | int clk_cnt; 18 | 19 | void init ( val_t rand_init = 0 ); 20 | void clock_lo ( dat_t<1> reset ); 21 | void clock_hi ( dat_t<1> reset ); 22 | int clock ( dat_t<1> reset ); 23 | mod_t* clone(); 24 | bool set_circuit_from(mod_t* src); 25 | void print ( FILE* f ); 26 | void print ( std::ostream& s ); 27 | void dump ( FILE* f, int t ); 28 | void dump_init ( FILE* f ); 29 | 30 | }; 31 | 32 | class DataSuite_BypassDataComp_1_api_t : public mod_api_t { 33 | void init_mapping_table(); 34 | }; 35 | 36 | 37 | 38 | #endif 39 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_MemReadModule_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_MemReadModule_1(input clk, 2 | input [31:0] io_addr, 3 | output[31:0] io_out 4 | ); 5 | 6 | wire[31:0] T0; 7 | reg [31:0] mem [7:0]; 8 | wire[2:0] T1; 9 | 10 | `ifndef SYNTHESIS 11 | // synthesis translate_off 12 | integer initvar; 13 | initial begin 14 | #0.002; 15 | for (initvar = 0; initvar < 8; initvar = initvar+1) 16 | mem[initvar] = {1{$random}}; 17 | end 18 | // synthesis translate_on 19 | `endif 20 | 21 | assign io_out = T0; 22 | assign T0 = mem[T1]; 23 | assign T1 = io_addr[2:0]; 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_ROMModule_1.cpp: -------------------------------------------------------------------------------- 1 | #include "DelaySuite_ROMModule_1.h" 2 | 3 | void DelaySuite_ROMModule_1_t::init ( val_t rand_init ) { 4 | this->__srand(rand_init); 5 | T1.randomize(&__rand_seed); 6 | { T1.put(0, 0, 0x1L);} 7 | { T1.put(1, 0, 0x2L);} 8 | { T1.put(2, 0, 0x3L);} 9 | clk.len = 1; 10 | clk.cnt = 0; 11 | clk.values[0] = 0; 12 | } 13 | int DelaySuite_ROMModule_1_t::clock ( dat_t<1> reset ) { 14 | uint32_t min = ((uint32_t)1<<31)-1; 15 | if (clk.cnt < min) min = clk.cnt; 16 | clk.cnt-=min; 17 | if (clk.cnt == 0) clock_lo( reset ); 18 | if (!reset.to_bool()) print( std::cerr ); 19 | if (clk.cnt == 0) clock_hi( reset ); 20 | if (clk.cnt == 0) clk.cnt = clk.len; 21 | return min; 22 | } 23 | void DelaySuite_ROMModule_1_t::print ( FILE* f ) { 24 | } 25 | void DelaySuite_ROMModule_1_t::print ( std::ostream& s ) { 26 | } 27 | void DelaySuite_ROMModule_1_t::dump_init ( FILE* f ) { 28 | } 29 | void DelaySuite_ROMModule_1_t::dump ( FILE* f, val_t t, dat_t<1> reset ) { 30 | } 31 | void DelaySuite_ROMModule_1_t::clock_lo ( dat_t<1> reset, bool assert_fire ) { 32 | val_t T0; 33 | { T0 = T1.get(DelaySuite_ROMModule_1__io_addr.values[0], 0);} 34 | { DelaySuite_ROMModule_1__io_out.values[0] = T0;} 35 | } 36 | void DelaySuite_ROMModule_1_t::clock_hi ( dat_t<1> reset ) { 37 | } 38 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_ROMModule_1.h: -------------------------------------------------------------------------------- 1 | #ifndef __DelaySuite_ROMModule_1__ 2 | #define __DelaySuite_ROMModule_1__ 3 | 4 | #include "emulator.h" 5 | 6 | class DelaySuite_ROMModule_1_t : public mod_t { 7 | private: 8 | val_t __rand_seed; 9 | void __srand(val_t seed) { __rand_seed = seed; } 10 | val_t __rand_val() { return ::__rand_val(&__rand_seed); } 11 | public: 12 | dat_t<2> DelaySuite_ROMModule_1__io_addr; 13 | dat_t<4> DelaySuite_ROMModule_1__io_out; 14 | mem_t<4,3> T1; 15 | clk_t clk; 16 | 17 | void init ( val_t rand_init = 0 ); 18 | void clock_lo ( dat_t<1> reset, bool assert_fire=true ); 19 | void clock_hi ( dat_t<1> reset ); 20 | int clock ( dat_t<1> reset ); 21 | void print ( FILE* f ); 22 | void print ( std::ostream& s ); 23 | void dump ( FILE* f, val_t t, dat_t<1> reset=LIT<1>(0) ); 24 | void dump_init ( FILE* f ); 25 | 26 | }; 27 | 28 | 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_ROMModule_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_ROMModule_1( 2 | input [1:0] io_addr, 3 | output[3:0] io_out 4 | ); 5 | 6 | reg [3:0] T0; 7 | 8 | 9 | assign io_out = T0; 10 | always @(*) case (io_addr) 11 | 0: T0 = 4'h1; 12 | 1: T0 = 4'h2; 13 | 2: T0 = 4'h3; 14 | default: begin 15 | T0 = 4'bx; 16 | `ifndef SYNTHESIS 17 | // synthesis translate_off 18 | T0 = {1{$random}}; 19 | // synthesis translate_on 20 | `endif 21 | end 22 | endcase 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_ReadCondMaskedWrite_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_ReadCondMaskedWrite_1(input clk, 2 | input io_enable, 3 | input [31:0] io_addr, 4 | output[31:0] io_out 5 | ); 6 | 7 | wire[31:0] T0; 8 | reg [31:0] mem [7:0]; 9 | wire[31:0] T1; 10 | wire[31:0] T2; 11 | wire[31:0] T3; 12 | wire[31:0] T4; 13 | wire[2:0] T5; 14 | wire[2:0] T6; 15 | 16 | `ifndef SYNTHESIS 17 | // synthesis translate_off 18 | integer initvar; 19 | initial begin 20 | #0.002; 21 | for (initvar = 0; initvar < 8; initvar = initvar+1) 22 | mem[initvar] = {1{$random}}; 23 | end 24 | // synthesis translate_on 25 | `endif 26 | 27 | assign io_out = T0; 28 | assign T0 = mem[T6]; 29 | assign T2 = T4 | T3; 30 | assign T3 = T0 & 32'hff; 31 | assign T4 = T0 & 32'hff00; 32 | assign T5 = io_addr[2:0]; 33 | assign T6 = io_addr[2:0]; 34 | 35 | always @(posedge clk) begin 36 | if (io_enable) 37 | mem[T5] <= T2; 38 | end 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_ReadCondWriteModule_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_ReadCondWriteModule_1(input clk, 2 | input io_enable, 3 | input [31:0] io_addr, 4 | output[31:0] io_out 5 | ); 6 | 7 | wire[31:0] T0; 8 | reg [31:0] mem [7:0]; 9 | wire[31:0] T1; 10 | wire[31:0] T2; 11 | wire[2:0] T7; 12 | wire[31:0] T3; 13 | wire T4; 14 | wire[2:0] T8; 15 | wire[31:0] T5; 16 | wire[31:0] T6; 17 | wire[2:0] T9; 18 | wire[2:0] T10; 19 | 20 | `ifndef SYNTHESIS 21 | // synthesis translate_off 22 | integer initvar; 23 | initial begin 24 | #0.002; 25 | for (initvar = 0; initvar < 8; initvar = initvar+1) 26 | mem[initvar] = {1{$random}}; 27 | end 28 | // synthesis translate_on 29 | `endif 30 | 31 | assign io_out = T0; 32 | assign T0 = mem[T10]; 33 | assign T2 = mem[T7]; 34 | assign T7 = T3[2:0]; 35 | assign T3 = io_addr + 32'h4; 36 | assign T4 = io_enable ^ 1'h1; 37 | assign T8 = io_addr[2:0]; 38 | assign T6 = T0 + 32'h1; 39 | assign T9 = io_addr[2:0]; 40 | assign T10 = io_addr[2:0]; 41 | 42 | always @(posedge clk) begin 43 | if (T4) 44 | mem[T8] <= T2; 45 | if (io_enable) 46 | mem[T9] <= T6; 47 | end 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_ReadWriteModule_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_ReadWriteModule_1(input clk, 2 | input [31:0] io_addr, 3 | output[31:0] io_out 4 | ); 5 | 6 | wire[31:0] T0; 7 | reg [31:0] mem [7:0]; 8 | wire[31:0] T1; 9 | wire[31:0] T2; 10 | wire[2:0] T3; 11 | wire[2:0] T4; 12 | 13 | `ifndef SYNTHESIS 14 | // synthesis translate_off 15 | integer initvar; 16 | initial begin 17 | #0.002; 18 | for (initvar = 0; initvar < 8; initvar = initvar+1) 19 | mem[initvar] = {1{$random}}; 20 | end 21 | // synthesis translate_on 22 | `endif 23 | 24 | assign io_out = T0; 25 | assign T0 = mem[T4]; 26 | assign T2 = T0 + 32'h1; 27 | assign T3 = io_addr[2:0]; 28 | assign T4 = io_addr[2:0]; 29 | 30 | always @(posedge clk) begin 31 | if (1'h1) 32 | mem[T3] <= T2; 33 | end 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_RegInitCondUpdate_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_RegInitCondUpdate_1(input clk, input reset, 2 | input io_in, 3 | output[31:0] io_out 4 | ); 5 | 6 | wire[31:0] T2; 7 | reg res; 8 | wire T3; 9 | wire T0; 10 | wire T1; 11 | 12 | `ifndef SYNTHESIS 13 | // synthesis translate_off 14 | integer initvar; 15 | initial begin 16 | #0.002; 17 | res = {1{$random}}; 18 | end 19 | // synthesis translate_on 20 | `endif 21 | 22 | assign io_out = T2; 23 | assign T2 = {31'h0, res}; 24 | assign T3 = reset ? 1'h0 : T0; 25 | assign T0 = io_in ? T1 : res; 26 | assign T1 = res + 1'h1; 27 | 28 | always @(posedge clk) begin 29 | if(reset) begin 30 | res <= 1'h0; 31 | end else if(io_in) begin 32 | res <= T1; 33 | end 34 | end 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_RegInitUpdate_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_RegInitUpdate_1(input clk, input reset, 2 | output[31:0] io_out 3 | ); 4 | 5 | wire[31:0] T1; 6 | reg res; 7 | wire T2; 8 | wire T0; 9 | 10 | `ifndef SYNTHESIS 11 | // synthesis translate_off 12 | integer initvar; 13 | initial begin 14 | #0.002; 15 | res = {1{$random}}; 16 | end 17 | // synthesis translate_on 18 | `endif 19 | 20 | assign io_out = T1; 21 | assign T1 = {31'h0, res}; 22 | assign T2 = reset ? 1'h0 : T0; 23 | assign T0 = res + 1'h1; 24 | 25 | always @(posedge clk) begin 26 | if(reset) begin 27 | res <= 1'h0; 28 | end else begin 29 | res <= T0; 30 | end 31 | end 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_RegNoInitUpdate_1.v: -------------------------------------------------------------------------------- 1 | module DelaySuite_RegNoInitUpdate_1(input clk, 2 | output[31:0] io_out 3 | ); 4 | 5 | reg [31:0] res; 6 | wire[31:0] T0; 7 | 8 | `ifndef SYNTHESIS 9 | // synthesis translate_off 10 | integer initvar; 11 | initial begin 12 | #0.002; 13 | res = {1{$random}}; 14 | end 15 | // synthesis translate_on 16 | `endif 17 | 18 | assign io_out = res; 19 | assign T0 = res + 32'h1; 20 | 21 | always @(posedge clk) begin 22 | res <= T0; 23 | end 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_SeqReadBundle_1.cpp: -------------------------------------------------------------------------------- 1 | #include "DelaySuite_SeqReadBundle_1.h" 2 | 3 | void DelaySuite_SeqReadBundle_1_t::init ( val_t rand_init ) { 4 | this->__srand(rand_init); 5 | DelaySuite_SeqReadBundle_1__R9.randomize(&__rand_seed); 6 | DelaySuite_SeqReadBundle_1__mem.randomize(&__rand_seed); 7 | clk.len = 1; 8 | clk.cnt = 0; 9 | clk.values[0] = 0; 10 | } 11 | int DelaySuite_SeqReadBundle_1_t::clock ( dat_t<1> reset ) { 12 | uint32_t min = ((uint32_t)1<<31)-1; 13 | if (clk.cnt < min) min = clk.cnt; 14 | clk.cnt-=min; 15 | if (clk.cnt == 0) clock_lo( reset ); 16 | if (!reset.to_bool()) print( std::cerr ); 17 | if (clk.cnt == 0) clock_hi( reset ); 18 | if (clk.cnt == 0) clk.cnt = clk.len; 19 | return min; 20 | } 21 | void DelaySuite_SeqReadBundle_1_t::print ( FILE* f ) { 22 | } 23 | void DelaySuite_SeqReadBundle_1_t::print ( std::ostream& s ) { 24 | } 25 | void DelaySuite_SeqReadBundle_1_t::dump_init ( FILE* f ) { 26 | } 27 | void DelaySuite_SeqReadBundle_1_t::dump ( FILE* f, val_t t, dat_t<1> reset ) { 28 | } 29 | void DelaySuite_SeqReadBundle_1_t::clock_lo ( dat_t<1> reset, bool assert_fire ) { 30 | val_t T0[2]; 31 | { T0[0] = DelaySuite_SeqReadBundle_1__mem.get(DelaySuite_SeqReadBundle_1__R9.values[0], 0); T0[1] = DelaySuite_SeqReadBundle_1__mem.get(DelaySuite_SeqReadBundle_1__R9.values[0], 1);} 32 | val_t T1; 33 | { T1 = T0[1] >> 40;} 34 | T1 = T1 & 0xffL; 35 | { DelaySuite_SeqReadBundle_1__io_out_1_a_a.values[0] = T1;} 36 | val_t T2; 37 | { T2 = T0[1] >> 24;} 38 | T2 = T2 & 0xffffL; 39 | { DelaySuite_SeqReadBundle_1__io_out_1_a_b.values[0] = T2;} 40 | val_t T3; 41 | { T3 = T0[0] >> 56 | T0[1] << 8;} 42 | T3 = T3 & 0xffffffffL; 43 | { DelaySuite_SeqReadBundle_1__io_out_1_a_b_.values[0] = T3;} 44 | val_t T4; 45 | { T4 = T0[0] >> 48 | T0[1] << 16;} 46 | T4 = T4 & 0xffL; 47 | { DelaySuite_SeqReadBundle_1__io_out_0_a_a.values[0] = T4;} 48 | val_t T5; 49 | { T5 = T0[0] >> 32 | T0[1] << 32;} 50 | T5 = T5 & 0xffffL; 51 | { DelaySuite_SeqReadBundle_1__io_out_0_a_b.values[0] = T5;} 52 | { T6.values[0] = TERNARY_1(DelaySuite_SeqReadBundle_1__io_ren.values[0], DelaySuite_SeqReadBundle_1__io_raddr.values[0], DelaySuite_SeqReadBundle_1__R9.values[0]);} 53 | val_t T7; 54 | { T7 = DelaySuite_SeqReadBundle_1__io_in_0_a_b_.values[0] | DelaySuite_SeqReadBundle_1__io_in_0_a_b.values[0] << 32;} 55 | val_t T8; 56 | { T8 = T7 | DelaySuite_SeqReadBundle_1__io_in_0_a_a.values[0] << 48;} 57 | val_t T9; 58 | { T9 = DelaySuite_SeqReadBundle_1__io_in_1_a_b_.values[0] | DelaySuite_SeqReadBundle_1__io_in_1_a_b.values[0] << 32;} 59 | val_t T10; 60 | { T10 = T9 | DelaySuite_SeqReadBundle_1__io_in_1_a_a.values[0] << 48;} 61 | val_t T11[2]; 62 | { T11[0] = T8 | T10 << 56; T11[1] = T10 >> 8;} 63 | { T12.values[0] = T11[0]; T12.values[1] = T11[1];} 64 | val_t T13; 65 | { T13 = T0[0];} 66 | T13 = T13 & 0xffffffffL; 67 | { DelaySuite_SeqReadBundle_1__io_out_0_a_b_.values[0] = T13;} 68 | } 69 | void DelaySuite_SeqReadBundle_1_t::clock_hi ( dat_t<1> reset ) { 70 | dat_t<4> DelaySuite_SeqReadBundle_1__R9__shadow = T6; 71 | { if (DelaySuite_SeqReadBundle_1__io_wen.values[0]) DelaySuite_SeqReadBundle_1__mem.put(DelaySuite_SeqReadBundle_1__io_waddr.values[0], 0, T12.values[0]); if (DelaySuite_SeqReadBundle_1__io_wen.values[0]) DelaySuite_SeqReadBundle_1__mem.put(DelaySuite_SeqReadBundle_1__io_waddr.values[0], 1, T12.values[1]);} 72 | DelaySuite_SeqReadBundle_1__R9 = T6; 73 | } 74 | -------------------------------------------------------------------------------- /src/test/resources/DelaySuite_SeqReadBundle_1.h: -------------------------------------------------------------------------------- 1 | #ifndef __DelaySuite_SeqReadBundle_1__ 2 | #define __DelaySuite_SeqReadBundle_1__ 3 | 4 | #include "emulator.h" 5 | 6 | class DelaySuite_SeqReadBundle_1_t : public mod_t { 7 | private: 8 | val_t __rand_seed; 9 | void __srand(val_t seed) { __rand_seed = seed; } 10 | val_t __rand_val() { return ::__rand_val(&__rand_seed); } 11 | public: 12 | dat_t<1> DelaySuite_SeqReadBundle_1__io_ren; 13 | dat_t<1> DelaySuite_SeqReadBundle_1__io_wen; 14 | dat_t<4> DelaySuite_SeqReadBundle_1__io_raddr; 15 | dat_t<4> T6; 16 | dat_t<4> DelaySuite_SeqReadBundle_1__R9; 17 | dat_t<4> DelaySuite_SeqReadBundle_1__io_waddr; 18 | dat_t<8> DelaySuite_SeqReadBundle_1__io_out_1_a_a; 19 | dat_t<8> DelaySuite_SeqReadBundle_1__io_out_0_a_a; 20 | dat_t<8> DelaySuite_SeqReadBundle_1__io_in_0_a_a; 21 | dat_t<8> DelaySuite_SeqReadBundle_1__io_in_1_a_a; 22 | dat_t<16> DelaySuite_SeqReadBundle_1__io_out_1_a_b; 23 | dat_t<16> DelaySuite_SeqReadBundle_1__io_out_0_a_b; 24 | dat_t<16> DelaySuite_SeqReadBundle_1__io_in_0_a_b; 25 | dat_t<16> DelaySuite_SeqReadBundle_1__io_in_1_a_b; 26 | dat_t<32> DelaySuite_SeqReadBundle_1__io_out_1_a_b_; 27 | dat_t<32> DelaySuite_SeqReadBundle_1__io_in_0_a_b_; 28 | dat_t<32> DelaySuite_SeqReadBundle_1__io_in_1_a_b_; 29 | dat_t<32> DelaySuite_SeqReadBundle_1__io_out_0_a_b_; 30 | dat_t<112> T12; 31 | mem_t<112,16> DelaySuite_SeqReadBundle_1__mem; 32 | clk_t clk; 33 | 34 | void init ( val_t rand_init = 0 ); 35 | void clock_lo ( dat_t<1> reset, bool assert_fire=true ); 36 | void clock_hi ( dat_t<1> reset ); 37 | int clock ( dat_t<1> reset ); 38 | void print ( FILE* f ); 39 | void print ( std::ostream& s ); 40 | void dump ( FILE* f, val_t t, dat_t<1> reset=LIT<1>(0) ); 41 | void dump_init ( FILE* f ); 42 | 43 | }; 44 | 45 | 46 | 47 | #endif 48 | -------------------------------------------------------------------------------- /src/test/resources/DotBackendSuite_DAGComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph DotBackendSuite_DAGComp_1{ 2 | rankdir = LR; 3 | subgraph clustersub{ 4 | label = "sub" 5 | DotBackendSuite_DAGComp_1_sub__io_valid[label="io_valid:Bool"]; 6 | DotBackendSuite_DAGComp_1_sub__stored[shape=square,label="stored:Reg"]; 7 | DotBackendSuite_DAGComp_1_sub__io_ready[label="io_ready:Bool"]; 8 | DotBackendSuite_DAGComp_1_sub__stored -> DotBackendSuite_DAGComp_1_sub__io_valid[label="1"]; 9 | DotBackendSuite_DAGComp_1_sub__io_ready -> DotBackendSuite_DAGComp_1_sub__stored[label="1"]; 10 | } 11 | T0 -> DotBackendSuite_DAGComp_1_sub__io_ready[label="1"]; 12 | T0[label="&"]; 13 | io_result[label="io_result:Bool"]; 14 | io_data1[label="io_data1:Bool"]; 15 | io_data0[label="io_data0:Bool"]; 16 | io_data0 -> T0[label="1"]; 17 | io_data1 -> T0[label="1"]; 18 | DotBackendSuite_DAGComp_1_sub__io_valid -> io_result[label="1"]; 19 | } -------------------------------------------------------------------------------- /src/test/resources/FullAdderSysCdriver.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | using namespace std; 3 | using namespace sc_core; 4 | using namespace sc_dt; 5 | #include "SCWrappedFullAdder.cpp" 6 | #include 7 | 8 | SC_MODULE(Generator){ 9 | sc_fifo out; 10 | sc_fifo src; 11 | 12 | SC_HAS_PROCESS(Generator); 13 | Generator(sc_module_name a_name) : sc_module(a_name), out(1){ 14 | SC_THREAD(generator_thread); 15 | } 16 | 17 | void generator_thread(void){ 18 | cs_io_in_bits_i dat; 19 | 20 | for(int i=1; i<100; i++){ 21 | dat.FullAdder__io_in_bits_a = rand() & 0x01; 22 | dat.FullAdder__io_in_bits_b = rand() & 0x01; 23 | dat.FullAdder__io_in_bits_cin = rand() & 0x01; 24 | out.write(dat); 25 | src.write(dat); 26 | wait(20.0, SC_SEC); 27 | } 28 | } 29 | }; 30 | 31 | SC_MODULE(Eater){ 32 | sc_fifo *src; 33 | sc_fifo* in; 34 | 35 | SC_HAS_PROCESS(Eater); 36 | Eater(sc_module_name a_name) : sc_module(a_name){ 37 | SC_THREAD(eater_thread); 38 | } 39 | 40 | void eater_thread(void){ 41 | while(true){ 42 | cs_io_in_bits_i test = src->read(); 43 | printf("Input a = %llu\n", test.FullAdder__io_in_bits_a.values[0]); 44 | printf("Input b = %llu\n", test.FullAdder__io_in_bits_b.values[0]); 45 | printf("Input cin = %llu\n", test.FullAdder__io_in_bits_cin.values[0]); 46 | cs_io_out_bits_o data = in->read(); 47 | printf("Output sum = %llu\n", data.FullAdder__io_out_bits_sum.values[0]); 48 | printf("Output cout = %llu\n", data.FullAdder__io_out_bits_cout.values[0]); 49 | } 50 | } 51 | }; 52 | 53 | int sc_main(int sc_argc, char* sc_argv[1]) 54 | { 55 | // See if we've been provided with a SEED. 56 | for (int i = 0; i < sc_argc; i += 1) { 57 | if (strcmp(sc_argv[i], "--SEED") == 0) { 58 | srand(atoi(sc_argv[i + 1])); 59 | } 60 | } 61 | //Create components 62 | Generator generator("mygenerator"); 63 | Eater eater("muncher"); 64 | SCWrappedFullAdder filter("myfilter"); 65 | 66 | //Connect components 67 | filter.in = &generator.out; 68 | eater.in = filter.out; 69 | eater.src = &generator.src; 70 | 71 | //Simulate 72 | sc_start(1000.0, SC_SEC); 73 | return 0; 74 | } 75 | -------------------------------------------------------------------------------- /src/test/resources/Makefile.sysc: -------------------------------------------------------------------------------- 1 | test: 2 | # mkdir -p generated/ 3 | # sbt "run --targetDir generated --compile --test --genHarness --backend sysc" 4 | sbt "run --targetDir generated --compile --test --genHarness --backend sysc --design AddFilter" 5 | sbt "run --targetDir generated --compile --test --genHarness --backend sysc --design MyCounter" 6 | 7 | SYSTEMC := /Users/jrl/noArc/clients/ucb/systemc/systemc-2.3.1 8 | sysc: 9 | g++ AddFilter.cpp ../src/test/resources/AddFilterSysCdriver.cpp \ 10 | -I. -I$(SYSTEMC)/include -L$(SYSTEMC)/lib-macosx64 -lsystemc -o addfilter 11 | 12 | .PHONY: test 13 | -------------------------------------------------------------------------------- /src/test/resources/MultiClockSuite_ClockDec_1.v: -------------------------------------------------------------------------------- 1 | module MultiClockSuite_ClockDec_1(input myClock, input myNewReset, 2 | input io_in, 3 | output io_out 4 | ); 5 | 6 | reg reg_; 7 | wire T1; 8 | 9 | `ifndef SYNTHESIS 10 | // synthesis translate_off 11 | integer initvar; 12 | initial begin 13 | #0.002; 14 | reg_ = {1{$random}}; 15 | end 16 | // synthesis translate_on 17 | `endif 18 | 19 | assign io_out = reg_; 20 | assign T1 = myNewReset ? 1'h0 : io_in; 21 | 22 | always @(posedge myClock) begin 23 | if(myNewReset) begin 24 | reg_ <= 1'h0; 25 | end else begin 26 | reg_ <= io_in; 27 | end 28 | end 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /src/test/resources/MultiClockSuite_Comp_1.v: -------------------------------------------------------------------------------- 1 | module MultiClockSuite_ClockedSubComp_1(input T0, 2 | input io_ready, 3 | output io_valid 4 | ); 5 | 6 | reg stored; 7 | 8 | `ifndef SYNTHESIS 9 | // synthesis translate_off 10 | integer initvar; 11 | initial begin 12 | #0.002; 13 | stored = {1{$random}}; 14 | end 15 | // synthesis translate_on 16 | `endif 17 | 18 | assign io_valid = stored; 19 | 20 | always @(posedge T0) begin 21 | stored <= io_ready; 22 | end 23 | endmodule 24 | 25 | module MultiClockSuite_Comp_1(input T0, 26 | input io_data0, 27 | input io_data1, 28 | output io_result 29 | ); 30 | 31 | wire T0; 32 | wire sub_io_valid; 33 | 34 | 35 | assign T0 = io_data0 & io_data1; 36 | assign io_result = sub_io_valid; 37 | MultiClockSuite_ClockedSubComp_1 sub(.T0(T0), 38 | .io_ready( T0 ), 39 | .io_valid( sub_io_valid ) 40 | ); 41 | endmodule 42 | 43 | -------------------------------------------------------------------------------- /src/test/resources/MultiClockSuite_TestMultiClock2_1.v: -------------------------------------------------------------------------------- 1 | module MultiClockSuite_TestMultiClock2_1_TestMultiClock2_subsub(input clkB, 2 | input io_in, 3 | output io_out 4 | ); 5 | 6 | reg r1_onSignal; 7 | 8 | `ifndef SYNTHESIS 9 | // synthesis translate_off 10 | integer initvar; 11 | initial begin 12 | #0.002; 13 | r1_onSignal = {1{$random}}; 14 | end 15 | // synthesis translate_on 16 | `endif 17 | 18 | assign io_out = r1_onSignal; 19 | 20 | always @(posedge clkB) begin 21 | r1_onSignal <= io_in; 22 | end 23 | endmodule 24 | 25 | module MultiClockSuite_TestMultiClock2_1_TestMultiClock2_sub(input clkB, 26 | input io_in, 27 | output io_out 28 | ); 29 | 30 | wire sub_io_out; 31 | 32 | 33 | assign io_out = sub_io_out; 34 | MultiClockSuite_TestMultiClock2_1_TestMultiClock2_subsub sub(.clkB(clkB), 35 | .io_in( io_in ), 36 | .io_out( sub_io_out ) 37 | ); 38 | endmodule 39 | 40 | module MultiClockSuite_TestMultiClock2_1(input clkB, 41 | input io_in, 42 | output io_out 43 | ); 44 | 45 | wire sub_io_out; 46 | 47 | 48 | assign io_out = sub_io_out; 49 | MultiClockSuite_TestMultiClock2_1_TestMultiClock2_sub sub(.clkB(clkB), 50 | .io_in( io_in ), 51 | .io_out( sub_io_out ) 52 | ); 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_BindFifthComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_Block_2(input clk, 2 | input io_in_resp_valid, 3 | input io_in_resp_bits_error, 4 | input [31:0] io_in_resp_bits_ppn, 5 | output io_out_resp_valid, 6 | output io_out_resp_bits_error, 7 | output[31:0] io_out_resp_bits_ppn 8 | ); 9 | 10 | wire[31:0] T0; 11 | wire[31:0] T1; 12 | reg [31:0] tag_ram_1; 13 | wire[31:0] T2; 14 | wire T3; 15 | wire T4; 16 | wire[1:0] T5; 17 | wire T6; 18 | wire T7; 19 | reg [31:0] tag_ram_0; 20 | wire[31:0] T8; 21 | wire T9; 22 | wire T10; 23 | wire[31:0] T11; 24 | wire T12; 25 | 26 | `ifndef SYNTHESIS 27 | // synthesis translate_off 28 | integer initvar; 29 | initial begin 30 | #0.002; 31 | tag_ram_1 = {1{$random}}; 32 | tag_ram_0 = {1{$random}}; 33 | end 34 | // synthesis translate_on 35 | `endif 36 | 37 | `ifndef SYNTHESIS 38 | // synthesis translate_off 39 | assign io_out_resp_bits_error = {1{$random}}; 40 | assign io_out_resp_valid = {1{$random}}; 41 | // synthesis translate_on 42 | `endif 43 | assign io_out_resp_bits_ppn = T0; 44 | assign T0 = T11 | T1; 45 | assign T1 = T7 ? tag_ram_1 : 32'h0; 46 | assign T2 = T3 ? io_in_resp_bits_ppn : tag_ram_1; 47 | assign T3 = io_in_resp_valid & T4; 48 | assign T4 = T5[1]; 49 | assign T5 = 1'h1 << T6; 50 | assign T6 = 1'h0; 51 | assign T7 = tag_ram_0[1]; 52 | assign T8 = T9 ? io_in_resp_bits_ppn : tag_ram_0; 53 | assign T9 = io_in_resp_valid & T10; 54 | assign T10 = T5[0]; 55 | assign T11 = T12 ? tag_ram_0 : 32'h0; 56 | assign T12 = tag_ram_0[0]; 57 | 58 | always @(posedge clk) begin 59 | if(T3) begin 60 | tag_ram_1 <= io_in_resp_bits_ppn; 61 | end 62 | if(T9) begin 63 | tag_ram_0 <= io_in_resp_bits_ppn; 64 | end 65 | end 66 | endmodule 67 | 68 | module NameSuite_BindFifthComp_1(input clk, 69 | input io_imem_ptw_resp_valid, 70 | input io_imem_ptw_resp_bits_error, 71 | input [31:0] io_imem_ptw_resp_bits_ppn, 72 | input io_dmem_ptw_resp_valid, 73 | input io_dmem_ptw_resp_bits_error, 74 | input [31:0] io_dmem_ptw_resp_bits_ppn, 75 | output io_resp_resp_valid, 76 | output io_resp_resp_bits_error, 77 | output[31:0] io_resp_resp_bits_ppn 78 | ); 79 | 80 | wire vdtlb_io_out_resp_valid; 81 | wire vdtlb_io_out_resp_bits_error; 82 | wire[31:0] vdtlb_io_out_resp_bits_ppn; 83 | 84 | 85 | assign io_resp_resp_bits_ppn = vdtlb_io_out_resp_bits_ppn; 86 | assign io_resp_resp_bits_error = vdtlb_io_out_resp_bits_error; 87 | assign io_resp_resp_valid = vdtlb_io_out_resp_valid; 88 | NameSuite_Block_2 vdtlb(.clk(clk), 89 | .io_in_resp_valid( io_imem_ptw_resp_valid ), 90 | .io_in_resp_bits_error( io_imem_ptw_resp_bits_error ), 91 | .io_in_resp_bits_ppn( io_imem_ptw_resp_bits_ppn ), 92 | .io_out_resp_valid( vdtlb_io_out_resp_valid ), 93 | .io_out_resp_bits_error( vdtlb_io_out_resp_bits_error ), 94 | .io_out_resp_bits_ppn( vdtlb_io_out_resp_bits_ppn ) 95 | ); 96 | `ifndef SYNTHESIS 97 | // synthesis translate_off 98 | assign vdtlb.io_out_resp_valid = {1{$random}}; 99 | assign vdtlb.io_out_resp_bits_error = {1{$random}}; 100 | // synthesis translate_on 101 | `endif 102 | endmodule 103 | 104 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_BindFirstComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_BlockDecoder_1( 2 | input io_valid, 3 | output io_replay, 4 | output io_sigs_enq_cmdq, 5 | output io_sigs_enq_ximm1q 6 | ); 7 | 8 | 9 | 10 | `ifndef SYNTHESIS 11 | // synthesis translate_off 12 | assign io_sigs_enq_ximm1q = {1{$random}}; 13 | assign io_sigs_enq_cmdq = {1{$random}}; 14 | // synthesis translate_on 15 | `endif 16 | assign io_replay = io_valid; 17 | endmodule 18 | 19 | module NameSuite_BindFirstComp_1( 20 | input io_valid, 21 | output io_replay 22 | ); 23 | 24 | wire T0; 25 | wire T1; 26 | wire T2; 27 | wire mask_ximm1q_ready; 28 | wire T3; 29 | wire mask_cmdq_ready; 30 | wire dec_io_sigs_enq_cmdq; 31 | wire dec_io_sigs_enq_ximm1q; 32 | 33 | 34 | assign io_replay = T0; 35 | assign T0 = io_valid & T1; 36 | assign T1 = T3 | T2; 37 | assign T2 = mask_ximm1q_ready ^ 1'h1; 38 | assign mask_ximm1q_ready = dec_io_sigs_enq_ximm1q ^ 1'h1; 39 | assign T3 = mask_cmdq_ready ^ 1'h1; 40 | assign mask_cmdq_ready = dec_io_sigs_enq_cmdq ^ 1'h1; 41 | NameSuite_BlockDecoder_1 dec( 42 | //.io_valid( ) 43 | //.io_replay( ) 44 | .io_sigs_enq_cmdq( dec_io_sigs_enq_cmdq ), 45 | .io_sigs_enq_ximm1q( dec_io_sigs_enq_ximm1q ) 46 | ); 47 | `ifndef SYNTHESIS 48 | // synthesis translate_off 49 | assign dec.io_valid = {1{$random}}; 50 | assign dec.io_sigs_enq_cmdq = {1{$random}}; 51 | assign dec.io_sigs_enq_ximm1q = {1{$random}}; 52 | // synthesis translate_on 53 | `endif 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_BindFourthComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_BindFourthComp_1( 2 | input [4:0] io_in, 3 | output[4:0] io_out 4 | ); 5 | 6 | 7 | 8 | assign io_out = io_in; 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_BindSecondComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_Block_1( 2 | input io_irq, 3 | output[4:0] io_irq_cause 4 | ); 5 | 6 | 7 | 8 | assign io_irq_cause = 5'h2; 9 | endmodule 10 | 11 | module NameSuite_BindSecondComp_1( 12 | input io_irq, 13 | output[5:0] io_irq_cause 14 | ); 15 | 16 | wire[5:0] T0; 17 | wire[4:0] NameSuite_Block_1_io_irq_cause; 18 | 19 | 20 | assign io_irq_cause = T0; 21 | assign T0 = {1'h1, NameSuite_Block_1_io_irq_cause}; 22 | NameSuite_Block_1 NameSuite_Block_1( 23 | .io_irq( io_irq ), 24 | .io_irq_cause( NameSuite_Block_1_io_irq_cause ) 25 | ); 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_BindThirdComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_Comp_1( 2 | input io_in_ren, 3 | output io_out_ren 4 | ); 5 | 6 | 7 | 8 | assign io_out_ren = io_in_ren; 9 | endmodule 10 | 11 | module NameSuite_BindThirdComp_1( 12 | input io_in_ren, 13 | output io_result 14 | ); 15 | 16 | wire T0; 17 | wire T1; 18 | wire T2; 19 | wire NameSuite_Comp_1_io_out_ren; 20 | wire NameSuite_Comp_1_1_io_out_ren; 21 | wire NameSuite_Comp_1_2_io_out_ren; 22 | wire NameSuite_Comp_1_3_io_out_ren; 23 | 24 | 25 | assign io_result = T0; 26 | assign T0 = T1 | NameSuite_Comp_1_3_io_out_ren; 27 | assign T1 = T2 | NameSuite_Comp_1_2_io_out_ren; 28 | assign T2 = NameSuite_Comp_1_io_out_ren | NameSuite_Comp_1_1_io_out_ren; 29 | NameSuite_Comp_1 NameSuite_Comp_1( 30 | .io_in_ren( io_in_ren ), 31 | .io_out_ren( NameSuite_Comp_1_io_out_ren ) 32 | ); 33 | NameSuite_Comp_1 NameSuite_Comp_1_1( 34 | .io_in_ren( NameSuite_Comp_1_io_out_ren ), 35 | .io_out_ren( NameSuite_Comp_1_1_io_out_ren ) 36 | ); 37 | NameSuite_Comp_1 NameSuite_Comp_1_2( 38 | .io_in_ren( NameSuite_Comp_1_1_io_out_ren ), 39 | .io_out_ren( NameSuite_Comp_1_2_io_out_ren ) 40 | ); 41 | NameSuite_Comp_1 NameSuite_Comp_1_3( 42 | .io_in_ren( NameSuite_Comp_1_2_io_out_ren ), 43 | .io_out_ren( NameSuite_Comp_1_3_io_out_ren ) 44 | ); 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_DebugComp_1.h: -------------------------------------------------------------------------------- 1 | #ifndef __NameSuite_DebugComp_1__ 2 | #define __NameSuite_DebugComp_1__ 3 | 4 | #include "emulator.h" 5 | 6 | class NameSuite_DebugComp_1_t : public mod_t { 7 | private: 8 | val_t __rand_seed; 9 | void __srand(val_t seed) { __rand_seed = seed; } 10 | val_t __rand_val() { return ::__rand_val(&__rand_seed); } 11 | public: 12 | dat_t<1> NameSuite_DebugComp_1__io_ctrl_wb_wen; 13 | dat_t<1> NameSuite_DebugComp_1_dpath__io_ctrl_wb_wen; 14 | dat_t<1> NameSuite_DebugComp_1_dpath__wb_wen; 15 | dat_t<1> reset; 16 | dat_t<1> NameSuite_DebugComp_1_dpath__reset; 17 | dat_t<1> T1; 18 | dat_t<1> NameSuite_DebugComp_1_dpath__wb_reg_ll_wb; 19 | dat_t<1> NameSuite_DebugComp_1_dpath__io_ctrl_out; 20 | dat_t<1> NameSuite_DebugComp_1__io_ctrl_out; 21 | dat_t<1> NameSuite_DebugComp_1__io_ctrl_wb_wen__prev; 22 | dat_t<1> NameSuite_DebugComp_1_dpath__io_ctrl_wb_wen__prev; 23 | dat_t<1> NameSuite_DebugComp_1_dpath__reset__prev; 24 | dat_t<1> NameSuite_DebugComp_1_dpath__wb_reg_ll_wb__prev; 25 | dat_t<1> NameSuite_DebugComp_1_dpath__io_ctrl_out__prev; 26 | dat_t<1> NameSuite_DebugComp_1__io_ctrl_out__prev; 27 | clk_t clk; 28 | dat_t<1> reset__prev; 29 | 30 | void init ( val_t rand_init = 0 ); 31 | void clock_lo ( dat_t<1> reset, bool assert_fire=true ); 32 | void clock_hi ( dat_t<1> reset ); 33 | int clock ( dat_t<1> reset ); 34 | void print ( FILE* f ); 35 | void print ( std::ostream& s ); 36 | void dump ( FILE* f, val_t t, dat_t<1> reset=LIT<1>(0) ); 37 | void dump_init ( FILE* f ); 38 | 39 | }; 40 | 41 | 42 | 43 | #endif 44 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_InputPortNameComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_InputPortNameComp_1( 2 | input [19:0] io_in, 3 | output[19:0] io_out 4 | ); 5 | 6 | 7 | 8 | assign io_out = io_in; 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_ListLookupsComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_ListLookupsComp_1( 2 | input [31:0] io_inst, 3 | output io_sigs_valid 4 | ); 5 | 6 | wire T0; 7 | wire T1; 8 | wire T2; 9 | wire[2:0] T3; 10 | wire[2:0] T4; 11 | wire T5; 12 | wire T6; 13 | wire T7; 14 | wire T8; 15 | 16 | 17 | assign io_sigs_valid = T0; 18 | assign T0 = T1; 19 | assign T1 = T7 ^ T2; 20 | assign T2 = T3[2]; 21 | assign T3 = T6 ? 3'h4 : T4; 22 | assign T4 = T5 ? 3'h1 : 3'h0; 23 | assign T5 = io_inst == 32'h257b; 24 | assign T6 = io_inst == 32'h277b; 25 | assign T7 = T6 ? 1'h1 : T8; 26 | assign T8 = T5 == 1'h0; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_MemComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_MemComp_1(input clk, 2 | input io_ren, 3 | input [7:0] io_raddr, 4 | output[64:0] io_rdata 5 | ); 6 | 7 | wire[64:0] T0; 8 | reg [7:0] raddr; 9 | wire[7:0] T1; 10 | 11 | `ifndef SYNTHESIS 12 | // synthesis translate_off 13 | integer initvar; 14 | initial begin 15 | #0.002; 16 | raddr = {1{$random}}; 17 | end 18 | // synthesis translate_on 19 | `endif 20 | 21 | assign io_rdata = T0; 22 | NameSuite_MemComp_1_rfile rfile ( 23 | .CLK(clk), 24 | .R0A(io_raddr), 25 | .R0E(io_ren), 26 | .R0O(T0) 27 | ); 28 | assign T1 = io_ren ? io_raddr : raddr; 29 | 30 | always @(posedge clk) begin 31 | if(io_ren) begin 32 | raddr <= io_raddr; 33 | end 34 | end 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_VariationComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_CompBlock_1_0( 2 | input io_valid, 3 | output io_replay 4 | ); 5 | 6 | 7 | 8 | assign io_replay = 1'h0; 9 | endmodule 10 | 11 | module NameSuite_CompBlock_1_1( 12 | input io_valid, 13 | output io_replay 14 | ); 15 | 16 | 17 | 18 | assign io_replay = io_valid; 19 | endmodule 20 | 21 | module NameSuite_VariationComp_1( 22 | input io_valid, 23 | output io_replay 24 | ); 25 | 26 | wire T0; 27 | wire T1; 28 | wire block_0_io_replay; 29 | wire block_1_io_replay; 30 | wire block_2_io_replay; 31 | 32 | 33 | assign io_replay = T0; 34 | assign T0 = T1 & block_2_io_replay; 35 | assign T1 = block_0_io_replay & block_1_io_replay; 36 | NameSuite_CompBlock_1_0 block_0( 37 | .io_valid( io_valid ), 38 | .io_replay( block_0_io_replay ) 39 | ); 40 | NameSuite_CompBlock_1_0 block_1( 41 | .io_valid( io_valid ), 42 | .io_replay( block_1_io_replay ) 43 | ); 44 | NameSuite_CompBlock_1_1 block_2( 45 | .io_valid( io_valid ), 46 | .io_replay( block_2_io_replay ) 47 | ); 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_VecComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_VecComp_1(input clk, 2 | input [63:0] io_pcr_req_data, 3 | input io_r_en, 4 | input [4:0] io_r_addr, 5 | input [63:0] io_w_data, 6 | output[7:0] io_status_im 7 | ); 8 | 9 | reg [7:0] reg_status_im; 10 | wire[7:0] T0; 11 | wire[63:0] wdata; 12 | reg [63:0] host_pcr_bits_data; 13 | wire[63:0] T1; 14 | wire[63:0] T2; 15 | wire[7:0] rdata; 16 | wire[7:0] elts_0; 17 | 18 | `ifndef SYNTHESIS 19 | // synthesis translate_off 20 | integer initvar; 21 | initial begin 22 | #0.002; 23 | reg_status_im = {1{$random}}; 24 | host_pcr_bits_data = {2{$random}}; 25 | end 26 | // synthesis translate_on 27 | `endif 28 | 29 | assign io_status_im = reg_status_im; 30 | assign T0 = wdata[7:0]; 31 | assign wdata = io_r_en ? io_w_data : host_pcr_bits_data; 32 | assign T1 = io_r_en ? T2 : host_pcr_bits_data; 33 | assign T2 = {56'h0, rdata}; 34 | assign rdata = elts_0; 35 | assign elts_0 = reg_status_im; 36 | 37 | always @(posedge clk) begin 38 | reg_status_im <= T0; 39 | if(io_r_en) begin 40 | host_pcr_bits_data <= T2; 41 | end 42 | end 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /src/test/resources/NameSuite_VecSecondComp_1.v: -------------------------------------------------------------------------------- 1 | module NameSuite_VecSecondComp_1(input clk, 2 | output io_requestor_3_req_ready, 3 | input io_requestor_3_req_valid, 4 | input io_requestor_3_req_bits_ready, 5 | output io_requestor_2_req_ready, 6 | input io_requestor_2_req_valid, 7 | input io_requestor_2_req_bits_ready, 8 | output io_requestor_1_req_ready, 9 | input io_requestor_1_req_valid, 10 | input io_requestor_1_req_bits_ready, 11 | output io_requestor_0_req_ready, 12 | input io_requestor_0_req_valid, 13 | input io_requestor_0_req_bits_ready, 14 | output io_mem 15 | ); 16 | 17 | wire T0; 18 | wire T1; 19 | wire T2; 20 | wire T3; 21 | reg r_valid_0; 22 | reg r_valid_1; 23 | reg r_valid_2; 24 | reg r_valid_3; 25 | 26 | `ifndef SYNTHESIS 27 | // synthesis translate_off 28 | integer initvar; 29 | initial begin 30 | #0.002; 31 | r_valid_0 = {1{$random}}; 32 | r_valid_1 = {1{$random}}; 33 | r_valid_2 = {1{$random}}; 34 | r_valid_3 = {1{$random}}; 35 | end 36 | // synthesis translate_on 37 | `endif 38 | 39 | `ifndef SYNTHESIS 40 | // synthesis translate_off 41 | assign io_requestor_0_req_ready = {1{$random}}; 42 | assign io_requestor_1_req_ready = {1{$random}}; 43 | assign io_requestor_2_req_ready = {1{$random}}; 44 | assign io_requestor_3_req_ready = {1{$random}}; 45 | // synthesis translate_on 46 | `endif 47 | assign io_mem = T0; 48 | assign T0 = r_valid_3 ? io_requestor_3_req_ready : T1; 49 | assign T1 = r_valid_2 ? io_requestor_2_req_ready : T2; 50 | assign T2 = r_valid_1 ? io_requestor_1_req_ready : T3; 51 | assign T3 = r_valid_0 ? io_requestor_0_req_ready : io_requestor_0_req_ready; 52 | 53 | always @(posedge clk) begin 54 | r_valid_0 <= io_requestor_0_req_ready; 55 | r_valid_1 <= io_requestor_1_req_ready; 56 | r_valid_2 <= io_requestor_2_req_ready; 57 | r_valid_3 <= io_requestor_3_req_ready; 58 | end 59 | endmodule 60 | 61 | -------------------------------------------------------------------------------- /src/test/resources/RegVcdSuite_RegVcdTest_1.vcd: -------------------------------------------------------------------------------- 1 | $timescale 1ps $end 2 | $scope module RegVcdSuite_RegVcdTest_1 $end 3 | $var wire 1 ! clk $end 4 | $var wire 1 " reset $end 5 | $var wire 1 # io_ready $end 6 | $var wire 1 $ io_full $end 7 | $var wire 1 % io_write $end 8 | $var wire 1 & io_read $end 9 | $var wire 1 ' stateReg $end 10 | $var wire 1 ( io_stateReg $end 11 | $var wire 8 ) io_din $end 12 | $var wire 8 * dataReg $end 13 | $var wire 8 + io_dout $end 14 | $upscope $end 15 | $enddefinitions $end 16 | $dumpvars 17 | $end 18 | #0 19 | b1 ! 20 | b1 " 21 | b1 # 22 | b0 $ 23 | b0 % 24 | b0 & 25 | b0 ' 26 | b0 ( 27 | b00000001 ) 28 | b00000000 * 29 | b00000000 + 30 | #1 31 | b0 ! 32 | #2 33 | b1 ! 34 | b1 " 35 | #3 36 | b0 ! 37 | #4 38 | b1 ! 39 | #5 40 | b0 ! 41 | #6 42 | b1 ! 43 | #7 44 | b0 ! 45 | #8 46 | b1 ! 47 | #9 48 | b0 ! 49 | #10 50 | b1 ! 51 | b0 " 52 | b10101011 ) 53 | #11 54 | b0 ! 55 | #12 56 | b1 ! 57 | b1 % 58 | b00010010 ) 59 | #13 60 | b0 ! 61 | #14 62 | b1 ! 63 | b0 # 64 | b1 $ 65 | b0 % 66 | b1 ' 67 | b1 ( 68 | b00110100 ) 69 | b00010010 * 70 | b00010010 + 71 | #15 72 | b0 ! 73 | #16 74 | b1 ! 75 | b1 & 76 | #17 77 | b0 ! 78 | #18 79 | b1 ! 80 | b1 # 81 | b0 $ 82 | b0 & 83 | b0 ' 84 | b0 ( 85 | #19 86 | b0 ! 87 | #20 88 | b1 ! 89 | b1 % 90 | b01010110 ) 91 | #21 92 | b0 ! 93 | #22 94 | b1 ! 95 | b0 # 96 | b1 $ 97 | b1 ' 98 | b1 ( 99 | b01010110 * 100 | b01010110 + 101 | #23 102 | b0 ! 103 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_AssignBundleComp_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_AssignBundleComp_1( 2 | input [1:0] io_in_v_1, 3 | input [1:0] io_in_v_0, 4 | output[1:0] io_out_v_1, 5 | output[1:0] io_out_v_0 6 | ); 7 | 8 | 9 | 10 | assign io_out_v_0 = io_in_v_0; 11 | assign io_out_v_1 = io_in_v_1; 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_CatComp_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_CatComp_1( 2 | input [7:0] io_x, 3 | input [7:0] io_y, 4 | output[15:0] io_z 5 | ); 6 | 7 | wire[15:0] T0; 8 | 9 | 10 | assign io_z = T0; 11 | assign T0 = {io_x, io_y}; 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_DivSU_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_DivSU_1( 2 | input [31:0] io_x, 3 | input [31:0] io_y, 4 | output[31:0] io_z 5 | ); 6 | 7 | wire[31:0] T0; 8 | wire[32:0] T1; 9 | wire[32:0] T2; 10 | 11 | 12 | assign io_z = T0; 13 | assign T0 = $signed(io_x) / $signed(T1); 14 | assign T1 = T2; 15 | assign T2 = {1'h0, io_y}; 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_DivUS_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_DivUS_1( 2 | input [31:0] io_x, 3 | input [31:0] io_y, 4 | output[32:0] io_z 5 | ); 6 | 7 | wire[32:0] T0; 8 | wire[32:0] T1; 9 | wire[32:0] T2; 10 | 11 | 12 | assign io_z = T0; 13 | assign T0 = $signed(T1) / $signed(io_y); 14 | assign T1 = T2; 15 | assign T2 = {1'h0, io_x}; 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_MulSU_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_MulSU_1( 2 | input [31:0] io_x, 3 | input [31:0] io_y, 4 | output[63:0] io_z 5 | ); 6 | 7 | wire[63:0] T0; 8 | wire[32:0] T1; 9 | wire[32:0] T2; 10 | 11 | 12 | assign io_z = T0; 13 | assign T0 = $signed(io_x) * $signed(T1); 14 | assign T1 = T2; 15 | assign T2 = {1'h0, io_y}; 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_MulUS_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_MulUS_1( 2 | input [31:0] io_x, 3 | input [31:0] io_y, 4 | output[63:0] io_z 5 | ); 6 | 7 | wire[63:0] T0; 8 | wire[32:0] T1; 9 | wire[32:0] T2; 10 | 11 | 12 | assign io_z = T0; 13 | assign T0 = $signed(io_y) * $signed(T1); 14 | assign T1 = T2; 15 | assign T2 = {1'h0, io_x}; 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_OHToUIntComp_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_OHToUIntComp_1( 2 | input io_in, 3 | output[1:0] io_out 4 | ); 5 | 6 | wire[1:0] T5; 7 | wire T6; 8 | wire[1:0] T7; 9 | wire[1:0] T8; 10 | wire[3:0] T1; 11 | wire[3:0] T2; 12 | wire[1:0] T3; 13 | wire[1:0] T4; 14 | wire[1:0] T9; 15 | wire T10; 16 | 17 | 18 | assign io_out = T5; 19 | assign T5 = {T10, T6}; 20 | assign T6 = T7[1]; 21 | assign T7 = T9 | T8; 22 | assign T8 = T1[1:0]; 23 | assign T1 = T2; 24 | assign T2 = {T4, T3}; 25 | assign T3 = {io_in, 1'h1}; 26 | assign T4 = {io_in, 1'h0}; 27 | assign T9 = T1[3:2]; 28 | assign T10 = T9 != 2'h0; 29 | endmodule 30 | 31 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_PipeComp_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_PipeComp_1(input clk, input reset, 2 | input io_enq_valid, 3 | input [7:0] io_enq_bits, 4 | output io_deq_valid, 5 | output[7:0] io_deq_bits 6 | ); 7 | 8 | reg [7:0] R0; 9 | wire[7:0] T1; 10 | reg [7:0] R2; 11 | wire[7:0] T3; 12 | reg R4; 13 | wire T6; 14 | reg R5; 15 | wire T7; 16 | 17 | `ifndef SYNTHESIS 18 | // synthesis translate_off 19 | integer initvar; 20 | initial begin 21 | #0.002; 22 | R0 = {1{$random}}; 23 | R2 = {1{$random}}; 24 | R4 = {1{$random}}; 25 | R5 = {1{$random}}; 26 | end 27 | // synthesis translate_on 28 | `endif 29 | 30 | assign io_deq_bits = R0; 31 | assign T1 = R4 ? R2 : R0; 32 | assign T3 = io_enq_valid ? io_enq_bits : R2; 33 | assign T6 = reset ? 1'h0 : io_enq_valid; 34 | assign io_deq_valid = R5; 35 | assign T7 = reset ? 1'h0 : R4; 36 | 37 | always @(posedge clk) begin 38 | if(R4) begin 39 | R0 <= R2; 40 | end 41 | if(io_enq_valid) begin 42 | R2 <= io_enq_bits; 43 | end 44 | if(reset) begin 45 | R4 <= 1'h0; 46 | end else begin 47 | R4 <= io_enq_valid; 48 | end 49 | if(reset) begin 50 | R5 <= 1'h0; 51 | end else begin 52 | R5 <= R4; 53 | end 54 | end 55 | endmodule 56 | 57 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_QueueComp_1.v: -------------------------------------------------------------------------------- 1 | module Queue(input clk, input reset, 2 | output io_enq_ready, 3 | input io_enq_valid, 4 | input [7:0] io_enq_bits, 5 | input io_deq_ready, 6 | output io_deq_valid, 7 | output[7:0] io_deq_bits, 8 | output[1:0] io_count 9 | ); 10 | 11 | wire[1:0] T0; 12 | wire ptr_diff; 13 | reg R1; 14 | wire T15; 15 | wire T2; 16 | wire T3; 17 | wire do_deq; 18 | reg R4; 19 | wire T16; 20 | wire T5; 21 | wire T6; 22 | wire do_enq; 23 | wire T7; 24 | wire ptr_match; 25 | reg maybe_full; 26 | wire T17; 27 | wire T8; 28 | wire T9; 29 | wire[7:0] T10; 30 | reg [7:0] ram [1:0]; 31 | wire[7:0] T11; 32 | wire T12; 33 | wire empty; 34 | wire T13; 35 | wire T14; 36 | wire full; 37 | 38 | `ifndef SYNTHESIS 39 | // synthesis translate_off 40 | integer initvar; 41 | initial begin 42 | #0.002; 43 | R1 = {1{$random}}; 44 | R4 = {1{$random}}; 45 | maybe_full = {1{$random}}; 46 | for (initvar = 0; initvar < 2; initvar = initvar+1) 47 | ram[initvar] = {1{$random}}; 48 | end 49 | // synthesis translate_on 50 | `endif 51 | 52 | assign io_count = T0; 53 | assign T0 = {T7, ptr_diff}; 54 | assign ptr_diff = R4 - R1; 55 | assign T15 = reset ? 1'h0 : T2; 56 | assign T2 = do_deq ? T3 : R1; 57 | assign T3 = R1 + 1'h1; 58 | assign do_deq = io_deq_ready & io_deq_valid; 59 | assign T16 = reset ? 1'h0 : T5; 60 | assign T5 = do_enq ? T6 : R4; 61 | assign T6 = R4 + 1'h1; 62 | assign do_enq = io_enq_ready & io_enq_valid; 63 | assign T7 = maybe_full & ptr_match; 64 | assign ptr_match = R4 == R1; 65 | assign T17 = reset ? 1'h0 : T8; 66 | assign T8 = T9 ? do_enq : maybe_full; 67 | assign T9 = do_enq != do_deq; 68 | assign io_deq_bits = T10; 69 | assign T10 = ram[R1]; 70 | assign io_deq_valid = T12; 71 | assign T12 = empty ^ 1'h1; 72 | assign empty = ptr_match & T13; 73 | assign T13 = maybe_full ^ 1'h1; 74 | assign io_enq_ready = T14; 75 | assign T14 = full ^ 1'h1; 76 | assign full = ptr_match & maybe_full; 77 | 78 | always @(posedge clk) begin 79 | if(reset) begin 80 | R1 <= 1'h0; 81 | end else if(do_deq) begin 82 | R1 <= T3; 83 | end 84 | if(reset) begin 85 | R4 <= 1'h0; 86 | end else if(do_enq) begin 87 | R4 <= T6; 88 | end 89 | if(reset) begin 90 | maybe_full <= 1'h0; 91 | end else if(T9) begin 92 | maybe_full <= do_enq; 93 | end 94 | if (do_enq) 95 | ram[R4] <= io_enq_bits; 96 | end 97 | endmodule 98 | 99 | module StdlibSuite_QueueComp_1(input clk, input reset, 100 | output io_req_ready, 101 | input io_req_valid, 102 | input [7:0] io_req_bits, 103 | input io_resp_ready, 104 | output io_resp_valid, 105 | output[7:0] io_resp_bits 106 | ); 107 | 108 | wire Queue_io_enq_ready; 109 | wire Queue_io_deq_valid; 110 | wire[7:0] Queue_io_deq_bits; 111 | 112 | 113 | assign io_resp_bits = Queue_io_deq_bits; 114 | assign io_resp_valid = Queue_io_deq_valid; 115 | assign io_req_ready = Queue_io_enq_ready; 116 | Queue Queue(.clk(clk), .reset(reset), 117 | .io_enq_ready( Queue_io_enq_ready ), 118 | .io_enq_valid( io_req_valid ), 119 | .io_enq_bits( io_req_bits ), 120 | .io_deq_ready( io_resp_ready ), 121 | .io_deq_valid( Queue_io_deq_valid ), 122 | .io_deq_bits( Queue_io_deq_bits ) 123 | //.io_count( ) 124 | ); 125 | endmodule 126 | 127 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_RemSU_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_RemSU_1( 2 | input [31:0] io_x, 3 | input [31:0] io_y, 4 | output[31:0] io_z 5 | ); 6 | 7 | wire[31:0] T0; 8 | wire[32:0] T1; 9 | wire[32:0] T2; 10 | 11 | 12 | assign io_z = T0; 13 | assign T0 = $signed(io_x) % $signed(T1); 14 | assign T1 = T2; 15 | assign T2 = {1'h0, io_y}; 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/StdlibSuite_RemUS_1.v: -------------------------------------------------------------------------------- 1 | module StdlibSuite_RemUS_1( 2 | input [31:0] io_x, 3 | input [31:0] io_y, 4 | output[31:0] io_z 5 | ); 6 | 7 | wire[31:0] T0; 8 | wire[32:0] T1; 9 | wire[32:0] T2; 10 | 11 | 12 | assign io_z = T0; 13 | assign T0 = $signed(T1) % $signed(io_y); 14 | assign T1 = T2; 15 | assign T2 = {1'h0, io_x}; 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/VCDVerifySuite_Top_1.vcd: -------------------------------------------------------------------------------- 1 | $timescale 1ps $end 2 | $scope module VCDVerifySuite_Top_1 $end 3 | $var wire 1 ! clk $end 4 | $var wire 1 " reset $end 5 | $var wire 1 # io_input $end 6 | $var wire 1 ( io_output $end 7 | $scope module hz $end 8 | $var wire 1 $ io_input $end 9 | $var wire 1 % reset $end 10 | $var wire 1 & reg_ $end 11 | $var wire 1 ' io_output $end 12 | $upscope $end 13 | $upscope $end 14 | $enddefinitions $end 15 | $dumpvars 16 | $end 17 | #0 18 | b1 ! 19 | b1 " 20 | b0 # 21 | b0 $ 22 | b1 % 23 | b0 & 24 | b0 ' 25 | b0 ( 26 | #1 27 | b0 ! 28 | #2 29 | b1 ! 30 | b1 " 31 | #3 32 | b0 ! 33 | #4 34 | b1 ! 35 | #5 36 | b0 ! 37 | #6 38 | b1 ! 39 | #7 40 | b0 ! 41 | #8 42 | b1 ! 43 | #9 44 | b0 ! 45 | #10 46 | b1 ! 47 | b0 " 48 | b0 # 49 | b0 $ 50 | b0 % 51 | #11 52 | b0 ! 53 | #12 54 | b1 ! 55 | b1 # 56 | b1 $ 57 | #13 58 | b0 ! 59 | #14 60 | b1 ! 61 | b1 & 62 | b1 ' 63 | b1 ( 64 | #15 65 | b0 ! 66 | #16 67 | b1 ! 68 | #17 69 | b0 ! 70 | #18 71 | b1 ! 72 | #19 73 | b0 ! 74 | #20 75 | b1 ! 76 | #21 77 | b0 ! 78 | #22 79 | b1 ! 80 | #23 81 | b0 ! 82 | -------------------------------------------------------------------------------- /src/test/resources/VerifSuite_CppAssertComp_1.cpp: -------------------------------------------------------------------------------- 1 | #include "VerifSuite_CppAssertComp_1.h" 2 | 3 | void VerifSuite_CppAssertComp_1_t::init ( val_t rand_init ) { 4 | this->__srand(rand_init); 5 | clk.len = 1; 6 | clk.cnt = 0; 7 | clk.values[0] = 0; 8 | } 9 | int VerifSuite_CppAssertComp_1_t::clock ( dat_t<1> reset ) { 10 | uint32_t min = ((uint32_t)1<<31)-1; 11 | if (clk.cnt < min) min = clk.cnt; 12 | clk.cnt-=min; 13 | if (clk.cnt == 0) clock_lo( reset ); 14 | if (!reset.to_bool()) print( std::cerr ); 15 | if (clk.cnt == 0) clock_hi( reset ); 16 | if (clk.cnt == 0) clk.cnt = clk.len; 17 | return min; 18 | } 19 | void VerifSuite_CppAssertComp_1_t::print ( FILE* f ) { 20 | } 21 | void VerifSuite_CppAssertComp_1_t::print ( std::ostream& s ) { 22 | } 23 | void VerifSuite_CppAssertComp_1_t::dump_init ( FILE* f ) { 24 | } 25 | void VerifSuite_CppAssertComp_1_t::dump ( FILE* f, val_t t, dat_t<1> reset ) { 26 | } 27 | void VerifSuite_CppAssertComp_1_t::clock_lo ( dat_t<1> reset, bool assert_fire ) { 28 | val_t T0; 29 | { T0 = VerifSuite_CppAssertComp_1__io_y.values[0] | VerifSuite_CppAssertComp_1__io_x.values[0] << 8;} 30 | { VerifSuite_CppAssertComp_1__io_z.values[0] = T0;} 31 | ASSERT(reset.values[0], "failure"); 32 | } 33 | void VerifSuite_CppAssertComp_1_t::clock_hi ( dat_t<1> reset ) { 34 | } 35 | -------------------------------------------------------------------------------- /src/test/resources/VerifSuite_CppPrintfComp_1.cpp: -------------------------------------------------------------------------------- 1 | #include "VerifSuite_CppPrintfComp_1.h" 2 | 3 | void VerifSuite_CppPrintfComp_1_t::init ( val_t rand_init ) { 4 | this->__srand(rand_init); 5 | clk.len = 1; 6 | clk.cnt = 0; 7 | clk.values[0] = 0; 8 | } 9 | int VerifSuite_CppPrintfComp_1_t::clock ( dat_t<1> reset ) { 10 | uint32_t min = ((uint32_t)1<<31)-1; 11 | if (clk.cnt < min) min = clk.cnt; 12 | clk.cnt-=min; 13 | if (clk.cnt == 0) clock_lo( reset ); 14 | if (!reset.to_bool()) print( std::cerr ); 15 | if (clk.cnt == 0) clock_hi( reset ); 16 | if (clk.cnt == 0) clk.cnt = clk.len; 17 | return min; 18 | } 19 | void VerifSuite_CppPrintfComp_1_t::print ( FILE* f ) { 20 | #if __cplusplus >= 201103L 21 | if (T1.values[0]) dat_fprintf<104>(f, "display %h %h", T3, T2); 22 | #endif 23 | fflush(f); 24 | } 25 | void VerifSuite_CppPrintfComp_1_t::print ( std::ostream& s ) { 26 | #if __cplusplus >= 201103L 27 | if (T1.values[0]) dat_prints<104>(s, "display %h %h", T3, T2); 28 | #endif 29 | s.flush(); 30 | } 31 | void VerifSuite_CppPrintfComp_1_t::dump_init ( FILE* f ) { 32 | } 33 | void VerifSuite_CppPrintfComp_1_t::dump ( FILE* f, val_t t, dat_t<1> reset ) { 34 | } 35 | void VerifSuite_CppPrintfComp_1_t::clock_lo ( dat_t<1> reset, bool assert_fire ) { 36 | val_t T0; 37 | { T0 = VerifSuite_CppPrintfComp_1__io_y.values[0] | VerifSuite_CppPrintfComp_1__io_x.values[0] << 8;} 38 | { VerifSuite_CppPrintfComp_1__io_z.values[0] = T0;} 39 | { T1.values[0] = reset.values[0] ^ 0x1L;} 40 | { T2.values[0] = VerifSuite_CppPrintfComp_1__io_y.values[0];} 41 | { T3.values[0] = VerifSuite_CppPrintfComp_1__io_x.values[0];} 42 | } 43 | void VerifSuite_CppPrintfComp_1_t::clock_hi ( dat_t<1> reset ) { 44 | } 45 | -------------------------------------------------------------------------------- /src/test/resources/VerifSuite_CppPrintfComp_1.h: -------------------------------------------------------------------------------- 1 | #ifndef __VerifSuite_CppPrintfComp_1__ 2 | #define __VerifSuite_CppPrintfComp_1__ 3 | 4 | #include "emulator.h" 5 | 6 | class VerifSuite_CppPrintfComp_1_t : public mod_t { 7 | private: 8 | val_t __rand_seed; 9 | void __srand(val_t seed) { __rand_seed = seed; } 10 | val_t __rand_val() { return ::__rand_val(&__rand_seed); } 11 | public: 12 | dat_t<1> reset; 13 | dat_t<1> T1; 14 | dat_t<8> VerifSuite_CppPrintfComp_1__io_y; 15 | dat_t<8> VerifSuite_CppPrintfComp_1__io_x; 16 | dat_t<8> T2; 17 | dat_t<8> T3; 18 | dat_t<16> VerifSuite_CppPrintfComp_1__io_z; 19 | dat_t<104> T4; 20 | clk_t clk; 21 | 22 | void init ( val_t rand_init = 0 ); 23 | void clock_lo ( dat_t<1> reset, bool assert_fire=true ); 24 | void clock_hi ( dat_t<1> reset ); 25 | int clock ( dat_t<1> reset ); 26 | void print ( FILE* f ); 27 | void print ( std::ostream& s ); 28 | void dump ( FILE* f, val_t t, dat_t<1> reset=LIT<1>(0) ); 29 | void dump_init ( FILE* f ); 30 | 31 | }; 32 | 33 | 34 | 35 | #endif 36 | -------------------------------------------------------------------------------- /src/test/resources/VerifSuite_VerilogAssertComp_1.v: -------------------------------------------------------------------------------- 1 | module VerifSuite_VerilogAssertComp_1(input clk, input reset, 2 | input [7:0] io_x, 3 | input [7:0] io_y, 4 | output[15:0] io_z 5 | ); 6 | 7 | reg T0; 8 | wire[15:0] T1; 9 | 10 | `ifndef SYNTHESIS 11 | // synthesis translate_off 12 | integer initvar; 13 | initial begin 14 | #0.002; 15 | T0 = 1'b0; 16 | end 17 | // synthesis translate_on 18 | `endif 19 | 20 | assign io_z = T1; 21 | assign T1 = {io_x, io_y}; 22 | 23 | always @(posedge clk) begin 24 | `ifndef SYNTHESIS 25 | // synthesis translate_off 26 | if(reset) T0 <= 1'b1; 27 | if(!reset && T0 && !reset) begin 28 | $fwrite(32'h80000002, "ASSERTION FAILED: %s\n", "failure"); 29 | $finish; 30 | end 31 | // synthesis translate_on 32 | `endif 33 | end 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /src/test/resources/VerifSuite_VerilogPrintfComp_1.v: -------------------------------------------------------------------------------- 1 | module VerifSuite_VerilogPrintfComp_1(input clk, input reset, 2 | input [7:0] io_x, 3 | input [7:0] io_y, 4 | output[15:0] io_z 5 | ); 6 | 7 | wire T0; 8 | wire[7:0] T1; 9 | wire[7:0] T2; 10 | wire[31:0] T3; 11 | wire[31:0] T4; 12 | reg [31:0] tsc_reg; 13 | wire[31:0] T8; 14 | wire[31:0] T5; 15 | wire[199:0] T6; 16 | wire[15:0] T7; 17 | 18 | `ifndef SYNTHESIS 19 | // synthesis translate_off 20 | integer initvar; 21 | initial begin 22 | #0.002; 23 | tsc_reg = {1{$random}}; 24 | end 25 | // synthesis translate_on 26 | `endif 27 | 28 | assign T0 = reset ^ 1'h1; 29 | assign T1 = io_y; 30 | assign T2 = io_x; 31 | assign T3 = T4; 32 | assign T4 = tsc_reg; 33 | assign T8 = reset ? 32'h0 : T5; 34 | assign T5 = tsc_reg + 32'h1; 35 | assign io_z = T7; 36 | assign T7 = {io_x, io_y}; 37 | 38 | always @(posedge clk) begin 39 | if(reset) begin 40 | tsc_reg <= 32'h0; 41 | end else begin 42 | tsc_reg <= T5; 43 | end 44 | `ifndef SYNTHESIS 45 | // synthesis translate_off 46 | `ifdef PRINTF_COND 47 | if (`PRINTF_COND) 48 | `endif 49 | if (T0) 50 | $fwrite(32'h80000002, "Cyc= %d io: %h %h", T3, T2, T1); 51 | // synthesis translate_on 52 | `endif 53 | end 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /src/test/resources/VerifSuite_VerilogPrintfNULComp_1.v: -------------------------------------------------------------------------------- 1 | module VerifSuite_VerilogPrintfNULComp_1(input clk, input reset, 2 | input io_in 3 | ); 4 | 5 | wire T0; 6 | wire T1; 7 | wire[15:0] T2; 8 | 9 | 10 | assign T0 = reset ^ 1'h1; 11 | assign T1 = io_in; 12 | 13 | always @(posedge clk) begin 14 | `ifndef SYNTHESIS 15 | // synthesis translate_off 16 | `ifdef PRINTF_COND 17 | if (`PRINTF_COND) 18 | `endif 19 | if (T0) 20 | $fwrite(32'h80000002, "%b\n", T1); 21 | // synthesis translate_on 22 | `endif 23 | end 24 | endmodule 25 | 26 | -------------------------------------------------------------------------------- /src/test/resources/WhenSuite_EmbedWhenComp_1.v: -------------------------------------------------------------------------------- 1 | module WhenSuite_EmbedWhenComp_1( 2 | input io_in0, 3 | input io_in1, 4 | output io_out 5 | ); 6 | 7 | wire T0; 8 | wire T1; 9 | wire T2; 10 | 11 | assign io_out = T0; 12 | assign T0 = T2 ? io_in1 : T1; 13 | assign T1 = io_in0 ? io_in0 : 1'h0; 14 | assign T2 = io_in0 && io_in1; 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /src/test/resources/WhenSuite_SwitchClassComp_1.cpp: -------------------------------------------------------------------------------- 1 | #include "WhenSuite_SwitchClassComp_1.h" 2 | 3 | void WhenSuite_SwitchClassComp_1_t::init ( val_t rand_init ) { 4 | nodes.clear(); 5 | mems.clear(); 6 | nodes.push_back(debug_node_t("WhenSuite_SwitchClassComp_1.io_in0", &WhenSuite_SwitchClassComp_1__io_in0)); 7 | nodes.push_back(debug_node_t("WhenSuite_SwitchClassComp_1.io_in1", &WhenSuite_SwitchClassComp_1__io_in1)); 8 | nodes.push_back(debug_node_t("WhenSuite_SwitchClassComp_1.io_out", &WhenSuite_SwitchClassComp_1__io_out)); 9 | } 10 | int WhenSuite_SwitchClassComp_1_t::clock ( dat_t<1> reset ) { 11 | uint32_t min = ((uint32_t)1<<31)-1; 12 | if (clk_cnt < min) min = clk_cnt; 13 | clk_cnt-=min; 14 | if (clk_cnt == 0) clock_lo( reset ); 15 | if (clk_cnt == 0) clock_hi( reset ); 16 | if (clk_cnt == 0) clk_cnt = clk; 17 | return min; 18 | } 19 | void WhenSuite_SwitchClassComp_1_t::print ( FILE* f, FILE* e ) { 20 | } 21 | bool WhenSuite_SwitchClassComp_1_t::scan ( FILE* f ) { 22 | return(!feof(f)); 23 | } 24 | void WhenSuite_SwitchClassComp_1_t::dump(FILE *f, int t) { 25 | } 26 | void WhenSuite_SwitchClassComp_1_t::clock_lo ( dat_t<1> reset ) { 27 | val_t T0__w0; 28 | { T0__w0 = WhenSuite_SwitchClassComp_1__io_in0.values[0]&0xf3L; } 29 | val_t T1__w0; 30 | T1__w0 = T0__w0 == 0x51L; 31 | val_t T2__w0; 32 | { T2__w0 = TERNARY(T1__w0, WhenSuite_SwitchClassComp_1__io_in1.values[0], WhenSuite_SwitchClassComp_1__io_in0.values[0]); } 33 | { WhenSuite_SwitchClassComp_1__io_out.values[0] = T2__w0; } 34 | } 35 | void WhenSuite_SwitchClassComp_1_t::clock_hi ( dat_t<1> reset ) { 36 | } 37 | -------------------------------------------------------------------------------- /src/test/resources/WhenSuite_SwitchClassComp_1.v: -------------------------------------------------------------------------------- 1 | module WhenSuite_SwitchClassComp_1( 2 | input [7:0] io_in0, 3 | input [7:0] io_in1, 4 | output[7:0] io_out 5 | ); 6 | 7 | wire[7:0] T0; 8 | wire T1; 9 | wire T2; 10 | wire[7:0] T3; 11 | 12 | assign io_out = T0; 13 | assign T0 = T1 ? io_in1 : io_in0; 14 | assign T1 = T2; 15 | assign T2 = T3 == 8'h51; 16 | assign T3 = io_in0 & 8'hf3; 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /src/test/resources/WhenSuite_UnlessClassComp_1.v: -------------------------------------------------------------------------------- 1 | module WhenSuite_UnlessClassComp_1( 2 | input io_in0, 3 | input io_in1, 4 | output io_out 5 | ); 6 | 7 | wire T0; 8 | wire T1; 9 | 10 | assign io_out = T0; 11 | assign T0 = T1 ? io_in1 : io_in0; 12 | assign T1 = ! io_in0; 13 | endmodule 14 | 15 | -------------------------------------------------------------------------------- /src/test/resources/WhenSuite_WhenClassComp_1.v: -------------------------------------------------------------------------------- 1 | module WhenSuite_WhenClassComp_1( 2 | input io_in0, 3 | input io_in1, 4 | output io_out 5 | ); 6 | 7 | wire T0; 8 | wire T1; 9 | wire T2; 10 | wire T3; 11 | wire T4; 12 | wire T5; 13 | wire T6; 14 | 15 | assign io_out = T0; 16 | assign T0 = T5 ? 1'h0 : T1; 17 | assign T1 = T3 ? io_in1 : T2; 18 | assign T2 = io_in0 ? io_in0 : 1'h0; 19 | assign T3 = T4 && io_in1; 20 | assign T4 = ! io_in0; 21 | assign T5 = ! T6; 22 | assign T6 = io_in0 || io_in1; 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /src/test/resources/WhenSuite_WhenComp_1.v: -------------------------------------------------------------------------------- 1 | module WhenSuite_WhenComp_1( 2 | input io_in, 3 | output io_out 4 | ); 5 | 6 | wire T0; 7 | 8 | assign io_out = T0; 9 | assign T0 = io_in ? io_in : 1'h0; 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_AssignBundleComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_AssignBundleComp_1{ 2 | rankdir = LR; 3 | io_out_v_0[label="io_out_v_0:UInt"]; 4 | io_in_v_0[label="io_in_v_0:UInt"]; 5 | io_out_v_1[label="io_out_v_1:UInt"]; 6 | io_in_v_1[label="io_in_v_1:UInt"]; 7 | io_in_v_0 -> io_out_v_0[label="2"]; 8 | io_in_v_1 -> io_out_v_1[label="2"]; 9 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_CatCompW0W_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_CatCompW0W_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:UInt"]; 4 | io_y[label="io_y:UInt"]; 5 | io_x[label="io_x:UInt"]; 6 | io_x -> io_z[label="8"]; 7 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_CatComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_CatComp_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:UInt"]; 4 | T0[label="##"]; 5 | io_y[label="io_y:UInt"]; 6 | io_x[label="io_x:UInt"]; 7 | T0 -> io_z[label="16"]; 8 | io_x -> T0[label="8"]; 9 | io_y -> T0[label="8"]; 10 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_CounterComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_CounterComp_1{ 2 | rankdir = LR; 3 | io_wrap[label="io_wrap:Bool"]; 4 | wrap[label="&"]; 5 | T0[label="==(_, 0x4)"]; 6 | count[shape=square,label="count:RegReset(_, 0x0)"]; 7 | T1[label="Mux(_, 0x0, _)"]; 8 | T2[label="Mux"]; 9 | T3[label="Mux(_, 0x0, _)"]; 10 | T4[label="+(_, 0x1)"]; 11 | io_in[label="io_in:Bool"]; 12 | io_out[label="io_out:UInt"]; 13 | wrap -> io_wrap[label="1"]; 14 | io_in -> wrap[label="1"]; 15 | T0 -> wrap[label="1"]; 16 | count -> T0[label="3"]; 17 | T1 -> count[label="3"]; 18 | T2 -> T1[label="3"]; 19 | io_in -> T2[label="1"]; 20 | T3 -> T2[label="3"]; 21 | count -> T2[label="3"]; 22 | T0 -> T3[label="1"]; 23 | T4 -> T3[label="3"]; 24 | count -> T4[label="3"]; 25 | count -> io_out[label="3"]; 26 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_DivSU_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_DivSU_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="s/s"]; 5 | T1[label="T1:SInt"]; 6 | T2[label="##(0x0, _)"]; 7 | io_y[label="io_y:UInt"]; 8 | io_x[label="io_x:SInt"]; 9 | T0 -> io_z[label="32"]; 10 | io_x -> T0[label="32"]; 11 | T1 -> T0[label="33"]; 12 | T2 -> T1[label="33"]; 13 | io_y -> T2[label="32"]; 14 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_DivUS_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_DivUS_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="s/s"]; 5 | io_y[label="io_y:SInt"]; 6 | T1[label="T1:SInt"]; 7 | T2[label="##(0x0, _)"]; 8 | io_x[label="io_x:UInt"]; 9 | T0 -> io_z[label="33"]; 10 | T1 -> T0[label="33"]; 11 | io_y -> T0[label="32"]; 12 | T2 -> T1[label="33"]; 13 | io_x -> T2[label="32"]; 14 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_DivUUZ_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_DivUUZ_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="T0:SInt"]; 5 | T1[label="##(0x0, _)"]; 6 | io_y[label="io_y:UInt"]; 7 | io_x[label="io_x:UInt"]; 8 | T0 -> io_z[label="33"]; 9 | T1 -> T0[label="33"]; 10 | io_x -> T1[label="32"]; 11 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_DivUZ_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_DivUZ_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:UInt(0x0)"]; 4 | io_y[label="io_y:UInt"]; 5 | io_x[label="io_x:UInt"]; 6 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_DivZU_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_DivZU_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt(0x0)"]; 4 | io_y[label="io_y:UInt"]; 5 | io_x[label="io_x:SInt"]; 6 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_FillComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_FillComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="##"]; 5 | T1[label="##"]; 6 | io_in[label="io_in:UInt"]; 7 | T0 -> io_out[label="32"]; 8 | T1 -> T0[label="16"]; 9 | T1 -> T0[label="16"]; 10 | io_in -> T1[label="8"]; 11 | io_in -> T1[label="8"]; 12 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_FillInterleavedComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_FillInterleavedComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="T0:UInt"]; 5 | T1[label="##"]; 6 | T2[label="##"]; 7 | T3[label="##"]; 8 | T4[label="-(0x0, _)"]; 9 | T5[label="##(0x0, _)"]; 10 | T6[label="T6:Extract(_, 0x0, 0x0)"]; 11 | io_in[label="io_in:UInt"]; 12 | T7[label="-(0x0, _)"]; 13 | T8[label="##(0x0, _)"]; 14 | T9[label="T9:Extract(_, 0x1, 0x1)"]; 15 | T10[label="##"]; 16 | T11[label="-(0x0, _)"]; 17 | T12[label="##(0x0, _)"]; 18 | T13[label="T13:Extract(_, 0x2, 0x2)"]; 19 | T14[label="-(0x0, _)"]; 20 | T15[label="##(0x0, _)"]; 21 | T16[label="T16:Extract(_, 0x3, 0x3)"]; 22 | T17[label="##"]; 23 | T18[label="##"]; 24 | T19[label="-(0x0, _)"]; 25 | T20[label="##(0x0, _)"]; 26 | T21[label="T21:Extract(_, 0x4, 0x4)"]; 27 | T22[label="-(0x0, _)"]; 28 | T23[label="##(0x0, _)"]; 29 | T24[label="T24:Extract(_, 0x5, 0x5)"]; 30 | T25[label="##"]; 31 | T26[label="-(0x0, _)"]; 32 | T27[label="##(0x0, _)"]; 33 | T28[label="T28:Extract(_, 0x6, 0x6)"]; 34 | T29[label="-(0x0, _)"]; 35 | T30[label="##(0x0, _)"]; 36 | T31[label="T31:Extract(_, 0x7, 0x7)"]; 37 | T0 -> io_out[label="32"]; 38 | T1 -> T0[label="32"]; 39 | T17 -> T1[label="16"]; 40 | T2 -> T1[label="16"]; 41 | T10 -> T2[label="8"]; 42 | T3 -> T2[label="8"]; 43 | T7 -> T3[label="4"]; 44 | T4 -> T3[label="4"]; 45 | T5 -> T4[label="4"]; 46 | T6 -> T5[label="1"]; 47 | io_in -> T6[label="8"]; 48 | T8 -> T7[label="4"]; 49 | T9 -> T8[label="1"]; 50 | io_in -> T9[label="8"]; 51 | T14 -> T10[label="4"]; 52 | T11 -> T10[label="4"]; 53 | T12 -> T11[label="4"]; 54 | T13 -> T12[label="1"]; 55 | io_in -> T13[label="8"]; 56 | T15 -> T14[label="4"]; 57 | T16 -> T15[label="1"]; 58 | io_in -> T16[label="8"]; 59 | T25 -> T17[label="8"]; 60 | T18 -> T17[label="8"]; 61 | T22 -> T18[label="4"]; 62 | T19 -> T18[label="4"]; 63 | T20 -> T19[label="4"]; 64 | T21 -> T20[label="1"]; 65 | io_in -> T21[label="8"]; 66 | T23 -> T22[label="4"]; 67 | T24 -> T23[label="1"]; 68 | io_in -> T24[label="8"]; 69 | T29 -> T25[label="4"]; 70 | T26 -> T25[label="4"]; 71 | T27 -> T26[label="4"]; 72 | T28 -> T27[label="1"]; 73 | io_in -> T28[label="8"]; 74 | T30 -> T29[label="4"]; 75 | T31 -> T30[label="1"]; 76 | io_in -> T31[label="8"]; 77 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_Log2Comp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_Log2Comp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="Log2"]; 5 | T1[label="T1:Extract(_, 0x1, 0x0)"]; 6 | io_in[label="io_in:UInt"]; 7 | T0 -> io_out[label="1"]; 8 | T1 -> T0[label="2"]; 9 | io_in -> T1[label="8"]; 10 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_LookupComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_LookupComp_1{ 2 | rankdir = LR; 3 | io_data[label="io_data:UInt(0x0)"]; 4 | io_addr[label="io_addr:UInt"]; 5 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MulSU_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MulSU_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="s*u"]; 5 | T1[label="T1:SInt"]; 6 | T2[label="##(0x0, _)"]; 7 | io_y[label="io_y:UInt"]; 8 | io_x[label="io_x:SInt"]; 9 | T0 -> io_z[label="64"]; 10 | io_x -> T0[label="32"]; 11 | T1 -> T0[label="33"]; 12 | T2 -> T1[label="33"]; 13 | io_y -> T2[label="32"]; 14 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MulUS_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MulUS_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="s*u"]; 5 | T1[label="T1:SInt"]; 6 | T2[label="##(0x0, _)"]; 7 | io_x[label="io_x:UInt"]; 8 | io_y[label="io_y:SInt"]; 9 | T0 -> io_z[label="64"]; 10 | io_y -> T0[label="32"]; 11 | T1 -> T0[label="33"]; 12 | T2 -> T1[label="33"]; 13 | io_x -> T2[label="32"]; 14 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MulUUZ_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MulUUZ_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:UInt"]; 4 | io_y[label="io_y:UInt"]; 5 | io_x[label="io_x:UInt"]; 6 | io_x -> io_z[label="32"]; 7 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MulUZ_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MulUZ_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T3[label="T3:Extract(_, 0x1f, 0x0)"]; 5 | T1[label="T1:SInt"]; 6 | T2[label="##(0x0, _)"]; 7 | io_y[label="io_y:SInt"]; 8 | io_x[label="io_x:UInt"]; 9 | T3 -> io_z[label="32"]; 10 | T1 -> T3[label="33"]; 11 | T2 -> T1[label="33"]; 12 | io_x -> T2[label="32"]; 13 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MulZS_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MulZS_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | io_y[label="io_y:SInt"]; 5 | io_x[label="io_x:UInt"]; 6 | io_y -> io_z[label="32"]; 7 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MulZU_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MulZU_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="T0:Extract(_, 0x1f, 0x0)"]; 5 | T1[label="T1:SInt"]; 6 | T2[label="##(0x0, _)"]; 7 | io_y[label="io_y:UInt"]; 8 | io_x[label="io_x:SInt"]; 9 | T0 -> io_z[label="32"]; 10 | T1 -> T0[label="33"]; 11 | T2 -> T1[label="33"]; 12 | io_y -> T2[label="32"]; 13 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MuxCaseComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MuxCaseComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | io_in0[label="io_in0:UInt"]; 5 | io_in1[label="io_in1:UInt"]; 6 | io_default[label="io_default:UInt"]; 7 | io_in0 -> io_out[label="8"]; 8 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MuxComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MuxComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="Mux"]; 5 | io_a[label="io_a:UInt"]; 6 | io_c[label="io_c:UInt"]; 7 | io_t[label="io_t:Bool"]; 8 | T0 -> io_out[label="8"]; 9 | io_t -> T0[label="1"]; 10 | io_c -> T0[label="8"]; 11 | io_a -> T0[label="8"]; 12 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_MuxLookupComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_MuxLookupComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="Mux"]; 5 | T1[label="Mux"]; 6 | io_default[label="io_default:UInt"]; 7 | io_data1[label="io_data1:UInt"]; 8 | T2[label="=="]; 9 | io_in1[label="io_in1:UInt"]; 10 | io_key[label="io_key:UInt"]; 11 | io_data0[label="io_data0:UInt"]; 12 | T3[label="=="]; 13 | io_in0[label="io_in0:UInt"]; 14 | T0 -> io_out[label="16"]; 15 | T3 -> T0[label="1"]; 16 | io_data0 -> T0[label="16"]; 17 | T1 -> T0[label="16"]; 18 | T2 -> T1[label="1"]; 19 | io_data1 -> T1[label="16"]; 20 | io_default -> T1[label="16"]; 21 | io_key -> T2[label="8"]; 22 | io_in1 -> T2[label="8"]; 23 | io_key -> T3[label="8"]; 24 | io_in0 -> T3[label="8"]; 25 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_OHToUIntComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_OHToUIntComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="OHToUInt"]; 5 | T1[label="T1:UInt"]; 6 | T2[label="##"]; 7 | T3[label="##(_, 0x1)"]; 8 | io_in[label="io_in:Bool"]; 9 | T4[label="##(_, 0x0)"]; 10 | T0 -> io_out[label="2"]; 11 | T1 -> T0[label="4"]; 12 | T2 -> T1[label="4"]; 13 | T4 -> T2[label="2"]; 14 | T3 -> T2[label="2"]; 15 | io_in -> T3[label="1"]; 16 | io_in -> T4[label="1"]; 17 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_OperatorComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_OperatorComp_1{ 2 | rankdir = LR; 3 | io_zb[label="io_zb:Bool"]; 4 | T1[label="|"]; 5 | T2[label="<=(_, 0x0)"]; 6 | io_y[label="io_y:UInt"]; 7 | T3[label="|"]; 8 | T4[label="<=(0x0, _)"]; 9 | T5[label="|"]; 10 | T6[label="<(0x0, _)"]; 11 | T7[label="|"]; 12 | T8[label="<(_, 0x0)"]; 13 | T9[label="|"]; 14 | T10[label="!=(0x0, _)"]; 15 | v[label="==(0x0, _)"]; 16 | io_z[label="io_z:UInt"]; 17 | T0[label="|"]; 18 | t[label="-(0x0, _)"]; 19 | T11[label="|(_, 0x0)"]; 20 | T12[label="|(_, 0x0)"]; 21 | T13[label="|"]; 22 | ac[label="|(0x0, _)"]; 23 | T14[label="|"]; 24 | ab[label="&(0x1, _)"]; 25 | T15[label="|"]; 26 | u[label="##(0x0, _)"]; 27 | T16[label="|"]; 28 | r[label="^(0x0, _)"]; 29 | T17[label="|"]; 30 | o[label="*(0x1, _)"]; 31 | T18[label="|"]; 32 | n[label="+(0x0, _)"]; 33 | T19[label="##(0x0, _)"]; 34 | T20[label="|(_, 0x0)"]; 35 | T21[label="|(_, 0x0)"]; 36 | T22[label="|(_, 0x0)"]; 37 | T23[label="|"]; 38 | T24[label="!=(0x0, 0x0)"]; 39 | T25[label="|"]; 40 | T26[label="==(0x0, 0x1)"]; 41 | T27[label="|(_, 0x0)"]; 42 | T28[label="|(0x0, _)"]; 43 | g[label="-(0x0, 0x0)"]; 44 | io_ys[label="io_ys:SInt"]; 45 | io_x[label="io_x:UInt"]; 46 | T1 -> io_zb[label="1"]; 47 | T3 -> T1[label="1"]; 48 | T2 -> T1[label="1"]; 49 | io_y -> T2[label="8"]; 50 | T5 -> T3[label="1"]; 51 | T4 -> T3[label="1"]; 52 | io_y -> T4[label="8"]; 53 | T7 -> T5[label="1"]; 54 | T6 -> T5[label="1"]; 55 | io_y -> T6[label="8"]; 56 | T9 -> T7[label="1"]; 57 | T8 -> T7[label="1"]; 58 | io_y -> T8[label="8"]; 59 | v -> T9[label="1"]; 60 | T10 -> T9[label="1"]; 61 | io_y -> T10[label="8"]; 62 | io_y -> v[label="8"]; 63 | T0 -> io_z[label="8"]; 64 | T11 -> T0[label="8"]; 65 | t -> T0[label="8"]; 66 | io_y -> t[label="8"]; 67 | T12 -> T11[label="8"]; 68 | T13 -> T12[label="8"]; 69 | T14 -> T13[label="8"]; 70 | ac -> T13[label="8"]; 71 | io_y -> ac[label="8"]; 72 | T15 -> T14[label="8"]; 73 | ab -> T14[label="8"]; 74 | io_y -> ab[label="8"]; 75 | T16 -> T15[label="8"]; 76 | u -> T15[label="8"]; 77 | io_y -> u[label="8"]; 78 | T17 -> T16[label="8"]; 79 | r -> T16[label="8"]; 80 | io_y -> r[label="8"]; 81 | T18 -> T17[label="8"]; 82 | o -> T17[label="8"]; 83 | io_y -> o[label="8"]; 84 | T19 -> T18[label="8"]; 85 | n -> T18[label="8"]; 86 | io_y -> n[label="8"]; 87 | T20 -> T19[label="1"]; 88 | T21 -> T20[label="1"]; 89 | T22 -> T21[label="1"]; 90 | T23 -> T22[label="1"]; 91 | T25 -> T23[label="1"]; 92 | T24 -> T23[label="1"]; 93 | T27 -> T25[label="1"]; 94 | T26 -> T25[label="1"]; 95 | T28 -> T27[label="1"]; 96 | g -> T28[label="1"]; 97 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_PipeComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_PipeComp_1{ 2 | rankdir = LR; 3 | io_deq_bits[label="io_deq_bits:UInt"]; 4 | R0[shape=square,label="R0:Reg"]; 5 | T2[label="Mux"]; 6 | R3[shape=square,label="R3:Reg"]; 7 | T4[label="Mux"]; 8 | io_enq_bits[label="io_enq_bits:UInt"]; 9 | io_enq_valid[label="io_enq_valid:Bool"]; 10 | R5[shape=square,label="R5:RegReset(_, 0x0)"]; 11 | T6[label="Mux(_, 0x0, _)"]; 12 | io_deq_valid[label="io_deq_valid:Bool"]; 13 | R1[shape=square,label="R1:RegReset(_, 0x0)"]; 14 | T7[label="Mux(_, 0x0, _)"]; 15 | R0 -> io_deq_bits[label="8"]; 16 | T2 -> R0[label="8"]; 17 | R5 -> T2[label="1"]; 18 | R3 -> T2[label="8"]; 19 | R0 -> T2[label="8"]; 20 | T4 -> R3[label="8"]; 21 | io_enq_valid -> T4[label="1"]; 22 | io_enq_bits -> T4[label="8"]; 23 | R3 -> T4[label="8"]; 24 | T6 -> R5[label="1"]; 25 | io_enq_valid -> T6[label="1"]; 26 | R1 -> io_deq_valid[label="1"]; 27 | T7 -> R1[label="1"]; 28 | R5 -> T7[label="1"]; 29 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_PopCountComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_PopCountComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt(0x1)"]; 4 | io_in[label="io_in:UInt"]; 5 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_PriorityEncoderComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_PriorityEncoderComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="PriEnc"]; 5 | io_in[label="io_in:UInt"]; 6 | T0 -> io_out[label="3"]; 7 | io_in -> T0[label="8"]; 8 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_PriorityEncoderOHComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_PriorityEncoderOHComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="Mux(_, 0x1, _)"]; 5 | T1[label="Mux(_, 0x2, _)"]; 6 | T2[label="Mux(_, 0x4, _)"]; 7 | T3[label="Mux(_, 0x8, _)"]; 8 | T4[label="Mux(_, 0x10, _)"]; 9 | T5[label="Mux(_, 0x20, _)"]; 10 | T6[label="Mux(_, 0x40, _)"]; 11 | T7[label="Mux(_, 0x80, 0x0)"]; 12 | T8[label="T8:Extract(_, 0x7, 0x7)"]; 13 | io_in[label="io_in:UInt"]; 14 | T9[label="T9:Extract(_, 0x6, 0x6)"]; 15 | T10[label="T10:Extract(_, 0x5, 0x5)"]; 16 | T11[label="T11:Extract(_, 0x4, 0x4)"]; 17 | T12[label="T12:Extract(_, 0x3, 0x3)"]; 18 | T13[label="T13:Extract(_, 0x2, 0x2)"]; 19 | T14[label="T14:Extract(_, 0x1, 0x1)"]; 20 | T15[label="T15:Extract(_, 0x0, 0x0)"]; 21 | T0 -> io_out[label="8"]; 22 | T15 -> T0[label="1"]; 23 | T1 -> T0[label="8"]; 24 | T14 -> T1[label="1"]; 25 | T2 -> T1[label="8"]; 26 | T13 -> T2[label="1"]; 27 | T3 -> T2[label="8"]; 28 | T12 -> T3[label="1"]; 29 | T4 -> T3[label="8"]; 30 | T11 -> T4[label="1"]; 31 | T5 -> T4[label="8"]; 32 | T10 -> T5[label="1"]; 33 | T6 -> T5[label="8"]; 34 | T9 -> T6[label="1"]; 35 | T7 -> T6[label="8"]; 36 | T8 -> T7[label="1"]; 37 | io_in -> T8[label="8"]; 38 | io_in -> T9[label="8"]; 39 | io_in -> T10[label="8"]; 40 | io_in -> T11[label="8"]; 41 | io_in -> T12[label="8"]; 42 | io_in -> T13[label="8"]; 43 | io_in -> T14[label="8"]; 44 | io_in -> T15[label="8"]; 45 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_PriorityMuxComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_PriorityMuxComp_1{ 2 | rankdir = LR; 3 | io_out2[label="io_out2:UInt"]; 4 | T2[label="Mux"]; 5 | io_data1[label="io_data1:UInt"]; 6 | io_data0[label="io_data0:UInt"]; 7 | io_in0[label="io_in0:Bool"]; 8 | io_out1[label="io_out1:UInt"]; 9 | T1[label="Mux"]; 10 | io_out0[label="io_out0:UInt"]; 11 | T0[label="Mux"]; 12 | io_in1[label="io_in1:Bool"]; 13 | T2 -> io_out2[label="16"]; 14 | io_in0 -> T2[label="1"]; 15 | io_data0 -> T2[label="16"]; 16 | io_data1 -> T2[label="16"]; 17 | T1 -> io_out1[label="16"]; 18 | io_in0 -> T1[label="1"]; 19 | io_data0 -> T1[label="16"]; 20 | io_data1 -> T1[label="16"]; 21 | T0 -> io_out0[label="16"]; 22 | io_in0 -> T0[label="1"]; 23 | io_data0 -> T0[label="16"]; 24 | io_data1 -> T0[label="16"]; 25 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_RemSU_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_RemSU_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="s%s"]; 5 | T1[label="T1:SInt"]; 6 | T2[label="##(0x0, _)"]; 7 | io_y[label="io_y:UInt"]; 8 | io_x[label="io_x:SInt"]; 9 | T0 -> io_z[label="32"]; 10 | io_x -> T0[label="32"]; 11 | T1 -> T0[label="33"]; 12 | T2 -> T1[label="33"]; 13 | io_y -> T2[label="32"]; 14 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_RemUS_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_RemUS_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt"]; 4 | T0[label="s%s"]; 5 | io_y[label="io_y:SInt"]; 6 | T1[label="T1:SInt"]; 7 | T2[label="##(0x0, _)"]; 8 | io_x[label="io_x:UInt"]; 9 | T0 -> io_z[label="32"]; 10 | T1 -> T0[label="33"]; 11 | io_y -> T0[label="32"]; 12 | T2 -> T1[label="33"]; 13 | io_x -> T2[label="32"]; 14 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_RemUZ_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_RemUZ_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt(0x0)"]; 4 | io_y[label="io_y:SInt"]; 5 | io_x[label="io_x:UInt"]; 6 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_RemZU_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_RemZU_1{ 2 | rankdir = LR; 3 | io_z[label="io_z:SInt(0x0)"]; 4 | io_y[label="io_y:UInt"]; 5 | io_x[label="io_x:SInt"]; 6 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_ReverseComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_ReverseComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="|"]; 5 | T1[label="&(_, 0xaa)"]; 6 | T2[label="<<(_, 0x1)"]; 7 | T3[label="T3:Extract(_, 0x6, 0x0)"]; 8 | T4[label="|"]; 9 | T5[label="&(_, 0xcc)"]; 10 | T6[label="<<(_, 0x2)"]; 11 | T7[label="T7:Extract(_, 0x5, 0x0)"]; 12 | T8[label="|"]; 13 | T9[label="&(_, 0xf0)"]; 14 | T10[label="<<(_, 0x4)"]; 15 | T11[label="T11:Extract(_, 0x3, 0x0)"]; 16 | io_in[label="io_in:UInt"]; 17 | T12[label="&(_, 0xf)"]; 18 | T13[label="##(0x0, _)"]; 19 | T14[label=">>(_, 0x4)"]; 20 | T15[label="&(_, 0x33)"]; 21 | T16[label="##(0x0, _)"]; 22 | T17[label=">>(_, 0x2)"]; 23 | T18[label="&(_, 0x55)"]; 24 | T19[label="##(0x0, _)"]; 25 | T20[label=">>(_, 0x1)"]; 26 | T0 -> io_out[label="8"]; 27 | T18 -> T0[label="8"]; 28 | T1 -> T0[label="8"]; 29 | T2 -> T1[label="8"]; 30 | T3 -> T2[label="7"]; 31 | T4 -> T3[label="8"]; 32 | T15 -> T4[label="8"]; 33 | T5 -> T4[label="8"]; 34 | T6 -> T5[label="8"]; 35 | T7 -> T6[label="6"]; 36 | T8 -> T7[label="8"]; 37 | T12 -> T8[label="8"]; 38 | T9 -> T8[label="8"]; 39 | T10 -> T9[label="8"]; 40 | T11 -> T10[label="4"]; 41 | io_in -> T11[label="8"]; 42 | T13 -> T12[label="8"]; 43 | T14 -> T13[label="4"]; 44 | io_in -> T14[label="8"]; 45 | T16 -> T15[label="8"]; 46 | T17 -> T16[label="6"]; 47 | T8 -> T17[label="8"]; 48 | T19 -> T18[label="8"]; 49 | T20 -> T19[label="7"]; 50 | T4 -> T20[label="8"]; 51 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_ShiftRegisterComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_ShiftRegisterComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | R0[shape=square,label="R0:Reg"]; 5 | R1[shape=square,label="R1:Reg"]; 6 | io_in[label="io_in:UInt"]; 7 | R0 -> io_out[label="8"]; 8 | R1 -> R0[label="8"]; 9 | io_in -> R1[label="8"]; 10 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_UIntToOHComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_UIntToOHComp_1{ 2 | rankdir = LR; 3 | io_out1[label="io_out1:UInt"]; 4 | T1[label="T1:Extract(_, 0x3, 0x0)"]; 5 | T2[label="<<(0x1, _)"]; 6 | T3[label="T3:Extract(_, 0x1, 0x0)"]; 7 | io_in[label="io_in:UInt"]; 8 | io_out0[label="io_out0:UInt"]; 9 | T0[label="<<(0x1, _)"]; 10 | T1 -> io_out1[label="4"]; 11 | T2 -> T1[label="4"]; 12 | T3 -> T2[label="2"]; 13 | io_in -> T3[label="8"]; 14 | T0 -> io_out0[label="256"]; 15 | io_in -> T0[label="8"]; 16 | } -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_ZeroWidthForceMatching_1.v: -------------------------------------------------------------------------------- 1 | module ZeroWidthTest_ZeroWidthForceMatching_1( 2 | output io 3 | ); 4 | 5 | 6 | 7 | assign io = 1'h0; 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /src/test/resources/ZeroWidthTest_foldRComp_1.dot: -------------------------------------------------------------------------------- 1 | digraph ZeroWidthTest_foldRComp_1{ 2 | rankdir = LR; 3 | io_out[label="io_out:UInt"]; 4 | T0[label="+"]; 5 | io_in2[label="io_in2:UInt"]; 6 | io_in0[label="io_in0:UInt"]; 7 | io_in1[label="io_in1:UInt"]; 8 | T0 -> io_out[label="8"]; 9 | io_in0 -> T0[label="8"]; 10 | io_in2 -> T0[label="8"]; 11 | } -------------------------------------------------------------------------------- /src/test/scala/BitPatSuite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import org.junit.Assert._ 32 | import org.junit.Test 33 | import org.junit.Ignore 34 | 35 | import Chisel._ 36 | 37 | class BitPatSuite extends TestSuite { 38 | // BitPat ? literals 39 | @Test def testBitPat() { 40 | println("\ntestBitPat...") 41 | class BitPatModule extends Module { 42 | val io = new Bundle { 43 | val in = UInt(INPUT,4) 44 | val out = Bool(OUTPUT) 45 | } 46 | io.out := Bool(false) 47 | switch(io.in) { 48 | is(0.U) { io.out := Bool(true) } 49 | is(BitPat("b???1")) { io.out := Bool(true) } 50 | } 51 | } 52 | 53 | class BitPatModuleTests(m: BitPatModule) extends Tester(m) { 54 | (0 until 8).map { i => 55 | poke(m.io.in, i) 56 | step(1) 57 | expect(m.io.out, if(i == 0) (1) else (i % 2)) 58 | } 59 | } 60 | 61 | launchCppTester((m: BitPatModule) => new BitPatModuleTests(m)) 62 | } 63 | 64 | @Test def testBitPatBool() { 65 | println("\ntestBitPatBool...") 66 | class BitPatBoolModule extends Module { 67 | val io = new Bundle { 68 | val in = Bool(INPUT) 69 | val out = Bool(OUTPUT) 70 | } 71 | io.out := Bool(false) 72 | val testDC = Bool.DC 73 | val testTrue = Bool(true) 74 | switch(io.in) { 75 | is(testDC) { io.out := Bool(true) } 76 | } 77 | } 78 | 79 | class BitPatBoolModuleTests(m: BitPatBoolModule) extends Tester(m) { 80 | (0 until 8).map { i => 81 | poke(m.io.in, i) 82 | step(1) 83 | expect(m.io.out, 1) 84 | } 85 | } 86 | 87 | launchCppTester((m: BitPatBoolModule) => new BitPatBoolModuleTests(m)) 88 | } 89 | } 90 | -------------------------------------------------------------------------------- /src/test/scala/BundleWire.scala: -------------------------------------------------------------------------------- 1 | //package ChiselTests 2 | import Chisel._ 3 | import org.junit.Assert._ 4 | import org.junit.Test 5 | import org.junit.Ignore 6 | 7 | class Coord extends Bundle { 8 | val x = UInt(width = 32) 9 | val y = UInt(width = 32) 10 | // We leave this as "clone" (we support the more correct "cloneType") 11 | // to ensure that the "old" usage is still supported. 12 | override def clone: this.type = { 13 | val res = new Coord() 14 | res.x.dir = this.x.dir 15 | res.y.dir = this.y.dir 16 | res.asInstanceOf[this.type] 17 | } 18 | } 19 | 20 | class BundleWireSuite extends TestSuite { 21 | 22 | @Test def testBundleWire() { 23 | println("\ntestBundleWire ...") 24 | 25 | class BundleWire extends Module { 26 | val io = new Bundle { 27 | val in = (new Coord).asInput 28 | val outs = Vec(4, (new Coord).asOutput) 29 | } 30 | val coords = Wire(Vec(4, new Coord)) 31 | for (i <- 0 until 4) { 32 | coords(i) := io.in 33 | io.outs(i) := coords(i) 34 | } 35 | } 36 | 37 | trait BundleWireTests extends Tests { 38 | def tests(c: BundleWire) { 39 | for (t <- 0 until 4) { 40 | val test_in_x = rnd.nextInt(256) 41 | val test_in_y = rnd.nextInt(256) 42 | poke(c.io.in.x, test_in_x) 43 | poke(c.io.in.y, test_in_y) 44 | step(1) 45 | for (i <- 0 until 4) { 46 | expect(c.io.outs(i).x, test_in_x) 47 | expect(c.io.outs(i).y, test_in_y) 48 | } 49 | } 50 | } 51 | } 52 | 53 | class BundleWireTester(c: BundleWire) extends Tester(c) with BundleWireTests { 54 | tests(c) 55 | } 56 | val args = chiselEnvironmentArguments() ++ Array[String]("--backend", "c", 57 | "--targetDir", dir.getPath.toString(), "--genHarness", "--compile", "--test") 58 | chiselMainTest(args, () => Module(new BundleWire())) {m => new BundleWireTester(m)} 59 | } 60 | 61 | @Test def testBundleWire2() { 62 | println("\ntestBundleWire2 ...") 63 | 64 | class BundleWire extends Module { 65 | val io = new Bundle { 66 | val in = (new Coord).asInput 67 | val outs = Vec(4, (new Coord).asOutput) 68 | } 69 | val coords = Wire(new Bundle { 70 | val a0 = new Coord 71 | val a1 = new Coord 72 | val a2 = new Coord 73 | val a3 = new Coord 74 | def apply(i: Int) = i match { 75 | case 0 => a0 76 | case 1 => a1 77 | case 2 => a2 78 | case 3 => a3 79 | } 80 | }) 81 | for (i <- 0 until 4) { 82 | coords(i) := io.in 83 | io.outs(i) := coords(i) 84 | } 85 | } 86 | 87 | class BundleWireTester(c: BundleWire) extends Tester(c) { 88 | for (t <- 0 until 4) { 89 | val test_in_x = rnd.nextInt(256) 90 | val test_in_y = rnd.nextInt(256) 91 | poke(c.io.in.x, test_in_x) 92 | poke(c.io.in.y, test_in_y) 93 | step(1) 94 | for (i <- 0 until 4) { 95 | expect(c.io.outs(i).x, test_in_x) 96 | expect(c.io.outs(i).y, test_in_y) 97 | } 98 | } 99 | } 100 | 101 | val args = chiselEnvironmentArguments() ++ Array[String]("--backend", "c", 102 | "--targetDir", dir.getPath.toString(), "--genHarness", "--compile", "--test") 103 | chiselMainTest(args, () => Module(new BundleWire())) {m => new BundleWireTester(m)} 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /src/test/scala/CombLoopTests.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import Chisel._ 32 | import org.junit.Assert._ 33 | import org.junit.Test 34 | import org.junit.Ignore 35 | 36 | class CombLoopSuite extends TestSuite { 37 | @Test def testCombLoop() { 38 | println("\ntestCombLoop ...") 39 | 40 | class CombLoopModule extends Module { 41 | val io = new Bundle { 42 | val in = Decoupled(UInt(width=16)).flip 43 | val out = Decoupled(UInt(width=16)) 44 | } 45 | io.in <> io.out 46 | } 47 | 48 | class CombLoopWrapper extends Module { 49 | val io = new Bundle { 50 | val out = Decoupled(UInt(width=16)) 51 | } 52 | val mod1 = Module(new CombLoopModule) 53 | val mod2 = Module(new CombLoopModule) 54 | val mod3 = Module(new CombLoopModule) 55 | mod1.io.out <> mod2.io.in 56 | mod2.io.out <> mod3.io.in 57 | mod3.io.out <> mod1.io.in 58 | io.out.bits := mod3.io.out.bits 59 | io.out.valid := mod3.io.out.valid 60 | mod3.io.out.ready := io.out.ready 61 | } 62 | 63 | val testArgs = chiselEnvironmentArguments() ++ Array("--targetDir", dir.getPath.toString(), 64 | "--minimumCompatibility", "3.0.0", "--wError", "--backend", "c") 65 | intercept[IllegalStateException] { 66 | // This should fail since we don't use a Wire wrapper 67 | chiselMain(testArgs, () => Module(new CombLoopWrapper)) 68 | } 69 | assertTrue(ChiselError.hasErrors) 70 | } 71 | } 72 | -------------------------------------------------------------------------------- /src/test/scala/DotBackendTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import scala.collection.mutable.ArrayBuffer 32 | import scala.collection.mutable.ListBuffer 33 | import org.junit.Assert._ 34 | import org.junit.Test 35 | import org.junit.Before 36 | import org.junit.After 37 | import org.junit.rules.TemporaryFolder; 38 | 39 | import Chisel._ 40 | 41 | 42 | /** This testsuite checks the generation of dot graphs. 43 | */ 44 | class DotBackendSuite extends TestSuite { 45 | 46 | /** Checks generation of simple dataflow graph */ 47 | @Test def testSimple() { 48 | 49 | class DAGSubComp extends Module { 50 | val io = new Bundle { 51 | val ready = Bool(INPUT) 52 | val valid = Bool(OUTPUT) 53 | } 54 | val stored = Reg(next=io.ready) 55 | io.valid := stored 56 | } 57 | 58 | class DAGComp extends Module { 59 | val io = new Bundle { 60 | val data0 = Bool(INPUT) 61 | val data1 = Bool(INPUT) 62 | val result = Bool(OUTPUT) // XXX If we don't explicitely specify 63 | // OUTPUT here, dot and verilog is generated correctly but 64 | // not c++. This is an interaction between Module.findRoots 65 | // and class Bool { def apply(): Bool = Bool(null); } 66 | } 67 | val sub = Module(new DAGSubComp()) 68 | sub.io.ready := io.data0 & io.data1 69 | io.result := sub.io.valid 70 | } 71 | 72 | chiselMain(Array[String]( 73 | "--backend", "Chisel.DotBackend", 74 | "--targetDir", dir.getPath.toString()), 75 | () => Module(new DAGComp())) 76 | assertFile("DotBackendSuite_DAGComp_1.dot") 77 | } 78 | } 79 | -------------------------------------------------------------------------------- /src/test/scala/DoubleSuite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import org.junit.Test 32 | 33 | import Chisel._ 34 | 35 | class DoubleSuite extends TestSuite { 36 | @Test def testCompareDbl() { 37 | println("\ntestCompareDbl...") 38 | class CompareDblModule extends Module { 39 | class IO extends Bundle { 40 | val in1 = Dbl(INPUT) 41 | val in2 = Dbl(INPUT) 42 | val outLT = Bool(OUTPUT) 43 | val outLE = Bool(OUTPUT) 44 | val outGT = Bool(OUTPUT) 45 | val outGE = Bool(OUTPUT) 46 | } 47 | val io = new IO() 48 | val dbl1 = io.in1 49 | val dbl2 = io.in2 50 | io.outLT := dbl1 < dbl2 51 | io.outLE := dbl1 <= dbl2 52 | io.outGT := dbl1 > dbl2 53 | io.outGE := dbl1 >= dbl2 54 | } 55 | 56 | trait CompareDblModuleTests extends Tests { 57 | def tests(m: CompareDblModule) { 58 | for (i <- 0 to 100) { 59 | val dbl1 = rnd.nextDouble 60 | val dbl2 = rnd.nextDouble 61 | 62 | poke(m.io.in1, dbl1) 63 | poke(m.io.in2, dbl2) 64 | expect(m.io.outLT, if (dbl1 < dbl2) 1 else 0) 65 | expect(m.io.outLE, if (dbl1 <= dbl2) 1 else 0) 66 | expect(m.io.outGT, if (dbl1 > dbl2) 1 else 0) 67 | expect(m.io.outGE, if (dbl1 >= dbl2) 1 else 0) 68 | } 69 | } 70 | } 71 | 72 | class CompareDblModuleTester(m: CompareDblModule) extends Tester(m) with CompareDblModuleTests { 73 | tests(m) 74 | } 75 | 76 | launchCppTester((m: CompareDblModule) => new CompareDblModuleTester(m)) 77 | } 78 | } 79 | -------------------------------------------------------------------------------- /src/test/scala/FillApp.scala: -------------------------------------------------------------------------------- 1 | //package ChiselTests 2 | import Chisel._ 3 | import org.junit.Test 4 | import org.junit.Assert._ 5 | 6 | class FillSuite extends TestSuite { 7 | 8 | // Issue #Chisel3/233 - Fill(Chisel.UInt, Int) 9 | @Test def testFillArgOrder() { 10 | println("\ntestFillArgOrder ...") 11 | 12 | class FillApp() extends Module { 13 | val io = new Bundle { 14 | val a = UInt(INPUT, 4) 15 | } 16 | val f = Fill(3, UInt(1,1)) 17 | } 18 | 19 | val testArgs = chiselEnvironmentArguments() ++ Array("--targetDir", dir.getPath.toString(), 20 | "--minimumCompatibility", "3.0.0", "--wError", "--backend", "null") 21 | intercept[IllegalStateException] { 22 | chiselMain(testArgs, () => Module(new FillApp())) 23 | } 24 | assertTrue(ChiselError.hasErrors) 25 | } 26 | } 27 | -------------------------------------------------------------------------------- /src/test/scala/FunTestSuite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import org.scalatest.FunSuite 32 | 33 | // The launchers included in TestSuite do not work with ScalaTest tests, due to issues trying to 34 | // instantiate instances of the device under test - the newInstance() method fails with an "invalid argument" 35 | // exception apparently because the "this" argument is the enclosing Suite, 36 | // whereas the module is defined in an anonymous function having its own class, and wants to be created with 37 | // an instance of that class as the argument to the constructor. 38 | // This could be resolved by moving all the DUT definitions up into the enclosing Suite, or by getting a handle 39 | // on the particular ScalaTest test that is executing. 40 | abstract class FunTestSuite extends FunSuite with TestHelpers {} 41 | -------------------------------------------------------------------------------- /src/test/scala/ManyEnums.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | //package ChiselTests 32 | import org.junit.Assert._ 33 | import org.junit.Test 34 | import org.junit.Ignore 35 | 36 | import Chisel._ 37 | 38 | class ManyEnumsSuite extends TestSuite { 39 | @Test def testManyEnums() { 40 | println("\ntestManyEnums...") 41 | class ManyEnums extends Module { 42 | val io = UInt(OUTPUT, 16) 43 | val states = Enum(UInt(), 44 | List('e_00, 'e_01, 'e_02, 'e_03, 'e_04, 'e_05, 'e_06, 'e_07, 45 | 'e_08, 'e_09, 'e_10, 'e_11, 'e_12, 'e_13, 'e_14, 'e_15, 'e_16, 'e_17, 46 | 'e_18, 'e_19, 'e_20, 'e_21, 'e_22)) 47 | val state = Reg(UInt(), init = states('e_22)) 48 | io := state 49 | } 50 | 51 | class ManyEnumsTester(m: ManyEnums) extends Tester(m) { 52 | expect(m.io, 22) 53 | } 54 | 55 | launchCppTester((c: ManyEnums) => new ManyEnumsTester(c)) 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /src/test/scala/ModuleTests.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import scala.collection.mutable.ArrayBuffer 32 | import org.junit.Assert._ 33 | import org.junit.Test 34 | 35 | import Chisel._ 36 | 37 | /** This testsuite various issues with dealing with Module. 38 | */ 39 | class ModuleTests extends TestSuite { 40 | val testArgs = Array("--targetDir", dir.getPath.toString()) 41 | 42 | /** Catch attempts to wrap a Module with a Module (directly). */ 43 | @Test def testModuleWrap() { 44 | println("\ntestModuleWrap ...") 45 | try { 46 | class ModuleOne extends Module { 47 | val io = new Bundle { 48 | val x = UInt(INPUT, 32) 49 | val y = SInt(INPUT, 32) 50 | val z = SInt(OUTPUT) 51 | } 52 | io.z := io.x * io.y 53 | } 54 | chiselMain(testArgs, 55 | () => Module( 56 | Module( 57 | new ModuleOne() 58 | ) 59 | ) 60 | ) 61 | } catch { 62 | case e : java.lang.IllegalStateException => {} 63 | } 64 | assertTrue(ChiselError.hasErrors); 65 | } 66 | 67 | } -------------------------------------------------------------------------------- /src/test/scala/Outer.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | //package ChiselTests 32 | import org.junit.Assert._ 33 | import org.junit.Test 34 | import org.junit.Ignore 35 | 36 | import Chisel._ 37 | 38 | 39 | class OuterSuite extends TestSuite { 40 | @Test def testOuterSuite() { 41 | println("\ntestOuterSuite...") 42 | 43 | class Inner extends Module { 44 | val io = new Bundle { 45 | val in = Bits(INPUT, 8) 46 | val out = Bits(OUTPUT, 8) 47 | } 48 | io.out := io.in + Bits(1) 49 | } 50 | 51 | class Outer extends Module { 52 | val io = new Bundle { 53 | val in = Bits(INPUT, 8) 54 | val out = Bits(OUTPUT, 8) 55 | } 56 | // val c = Module(new Inner) 57 | val c = Array(Module(new Inner)) 58 | // val w = Wire(Bits(NO_DIR, 8)) 59 | // w := io.in 60 | c(0).io.in := io.in 61 | io.out := (c(0).io.out * Bits(2))(7,0) 62 | } 63 | 64 | class OuterTester(c: Outer) extends Tester(c) { 65 | for (t <- 0 until 16) { 66 | val test_in = rnd.nextInt(256) 67 | poke(c.io.in, test_in) 68 | step(1) 69 | expect(c.io.out, ((test_in + 1) * 2)&255) 70 | } 71 | } 72 | 73 | launchCppTester((c: Outer) => new OuterTester(c)) 74 | } 75 | } 76 | 77 | -------------------------------------------------------------------------------- /src/test/scala/ROM.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | //package ChiselTests 32 | import org.junit.Test 33 | 34 | import Chisel._ 35 | 36 | class ROMSuite extends TestSuite { 37 | // Verify we can initialize a ROM wider then 64 bits. 38 | @Test def testWideROMInit() { 39 | println("\ntestWideROMInit...") 40 | class DUT extends Module { 41 | 42 | val DATAWIDTH = 133 43 | 44 | val wideROM = { 45 | val inits = (1 to 2).map(i => UInt(i, width = DATAWIDTH)) 46 | ROM(inits) 47 | } 48 | 49 | val io = new Bundle { 50 | val m = UInt(INPUT, width = log2Up(DATAWIDTH)) 51 | val fState = Bits(OUTPUT, width = DATAWIDTH) 52 | } 53 | 54 | val inpBitStrReg = RegInit(Bits(0, width = DATAWIDTH)) 55 | 56 | inpBitStrReg := wideROM.read(io.m) 57 | io.fState := inpBitStrReg 58 | } 59 | 60 | class DUTTester(c: DUT) extends Tester(c) { 61 | poke(c.io.m, 0) 62 | // We expect a one-cycle delay in memory response. 63 | expect(c.io.fState, 0) 64 | step(1) 65 | expect(c.io.fState, 1) 66 | step(1) 67 | poke(c.io.m, 1) 68 | expect(c.io.fState, 1) 69 | step(1) 70 | // We expect a one-cycle delay in memory response. 71 | expect(c.io.fState, 2) 72 | } 73 | val testArgs = chiselEnvironmentArguments() ++ Array("--targetDir", dir.getPath.toString(), 74 | "--backend", "c", "--genHarness", "--compile", "--test", "--debug") 75 | chiselMainTest(testArgs, () => Module(new DUT())){ c => new DUTTester(c) } 76 | } 77 | } 78 | -------------------------------------------------------------------------------- /src/test/scala/ReadMeCode.scala: -------------------------------------------------------------------------------- 1 | import Chisel._ 2 | 3 | class HelloModule extends Module { 4 | val io = new Bundle {} 5 | printf("Hello World!\n") 6 | } 7 | 8 | class HelloModuleTests(c: HelloModule) extends Tester(c) { 9 | step(1) 10 | } 11 | 12 | object hello { 13 | def main(args: Array[String]): Unit = { 14 | chiselMainTest(Array[String]("--backend", "c", "--compile", "--test", "--genHarness"), 15 | () => Module(new HelloModule())){c => new HelloModuleTests(c)} 16 | } 17 | } 18 | 19 | -------------------------------------------------------------------------------- /src/test/scala/SeqMemSuite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import Chisel._ 32 | import org.junit.Assert._ 33 | import org.junit.Test 34 | import org.junit.Ignore 35 | 36 | class SeqMemSuite extends TestSuite { 37 | // Test out creating a Sequential Memory 38 | @Test def testSeqMemCreate() { 39 | println("\ntestSeqMemCreate ...") 40 | class CreateSeqMem(size: Integer) extends Module { 41 | val io = new Bundle { 42 | val wEnable = Bool(INPUT) 43 | val rEnable = Bool(INPUT) 44 | val addr = UInt(INPUT, log2Ceil(size)) 45 | val value = UInt(INPUT, 32) 46 | val out = UInt(OUTPUT, 32) 47 | } 48 | val mem = SeqMem(size, UInt(width = 32)) 49 | when(io.wEnable) { 50 | mem.write(io.addr, io.value) 51 | } 52 | val rdata = mem.read(io.addr, io.rEnable) 53 | io.out := rdata 54 | } 55 | 56 | class CreateSeqMemTester(c: CreateSeqMem, size: Int) extends Tester(c) { 57 | for (t <- 0 until 4) { 58 | val test_addr = rnd.nextInt(size) 59 | val test_value = rnd.nextInt(log2Ceil(size)) 60 | poke(c.io.addr, test_addr) 61 | poke(c.io.value, test_value) 62 | poke(c.io.wEnable, 1) 63 | poke(c.io.rEnable, 1) 64 | step(2) 65 | expect(c.io.out, test_value) 66 | } 67 | } 68 | val size = 1024 69 | val testArgs = chiselEnvironmentArguments() ++ Array("--compile", "--genHarness", "--test", "--targetDir", dir.getPath) 70 | chiselMainTest(testArgs, () => Module(new CreateSeqMem(size))){ 71 | c => new CreateSeqMemTester(c, size)} 72 | } 73 | } 74 | -------------------------------------------------------------------------------- /src/test/scala/SysCTest/FullAdder.scala: -------------------------------------------------------------------------------- 1 | package SysCTest 2 | 3 | import Chisel._ 4 | 5 | class FullAdderInput extends Bundle { 6 | val a = Bits(width = 1) 7 | val b = Bits(width = 1) 8 | val cin = Bits(width = 1) 9 | } 10 | 11 | class FullAdderOutput extends Bundle { 12 | val sum = Bits(width = 1) 13 | val cout = Bits(width = 1) 14 | } 15 | 16 | class FullAdder extends Module { 17 | val io = new Bundle { 18 | val in = Decoupled(new FullAdderInput()).flip() 19 | val out = Decoupled(new FullAdderOutput()) 20 | } 21 | 22 | val in_a = Reg(UInt(1)) 23 | val in_b = Reg(UInt(1)) 24 | val in_cin = Reg(UInt(1)) 25 | val out_sum = Reg(init=UInt(0, 1)) 26 | val out_cout = Reg(init=UInt(0, 1)) 27 | 28 | val p = Reg(init=Bool(false)) 29 | val q = Reg(init=Bool(true)) 30 | io.in.ready := !p 31 | io.out.valid := !q 32 | 33 | when (io.in.valid && !p) { 34 | in_a := io.in.bits.a 35 | in_b := io.in.bits.b 36 | in_cin := io.in.bits.cin 37 | io.in.ready := Bool(false) 38 | io.out.valid := Bool(false) 39 | p := Bool(true) 40 | q := Bool(true) 41 | } 42 | 43 | when (io.out.ready && p) { 44 | // Calculate the sum 45 | val a_xor_b = in_a ^ in_b 46 | out_sum := a_xor_b ^ in_cin 47 | // Generate the carry 48 | val a_and_b = io.in.bits.a & io.in.bits.b 49 | val a_and_cin = io.in.bits.a & io.in.bits.cin 50 | val b_and_cin = io.in.bits.b & io.in.bits.cin 51 | out_cout := a_and_b | b_and_cin | a_and_cin 52 | p := Bool(false) 53 | q := Bool(false) 54 | io.out.valid := p 55 | } 56 | io.out.bits.sum := out_sum 57 | io.out.bits.cout := out_cout 58 | } 59 | 60 | class FullAdderTests(c: FullAdder) extends Tester(c) { 61 | var i = 0 62 | do { 63 | val a = rnd.nextInt(2) 64 | val b = rnd.nextInt(2) 65 | val cin = rnd.nextInt(2) 66 | val res = a + b + cin 67 | val sum = res & 1 68 | val cout = (res >> 1) & 1 69 | var transfer = false 70 | poke(c.io.in.valid, 0) 71 | poke(c.io.out.ready, 0) 72 | 73 | do { 74 | transfer = (peek(c.io.in.ready) == 1) 75 | step(1) 76 | } while (t < 50 && !transfer) 77 | 78 | poke(c.io.in.bits.a, a) 79 | poke(c.io.in.bits.b, b) 80 | poke(c.io.in.bits.cin, cin) 81 | poke(c.io.in.valid, 1) 82 | poke(c.io.out.ready, 1) 83 | 84 | do { 85 | transfer = (peek(c.io.out.valid) == 1) 86 | step(1) 87 | } while (t < 50 && !transfer) 88 | 89 | expect(c.io.out.bits.sum, sum) 90 | expect(c.io.out.bits.cout, cout) 91 | i += 1 92 | printf("* INPUT -> a: %d b: %d cin: %d",a, b, cin) 93 | printf(" - OUTPUT -> sum: %d cout: %d\n", sum, cout) 94 | } while (t < 50 && i < 4) 95 | if (t >= 50) fail 96 | } 97 | 98 | object FullAdder { 99 | def main(mainArgs: scala.Array[String]): Unit = { 100 | val sysCArgs = Array[String]("--backend", "sysc", "--genHarness", "--compile", "--test") 101 | val args = sysCArgs ++ mainArgs 102 | chiselMainTest(args, 103 | () => Module(new FullAdder())){c => new FullAdderTests(c)} 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /src/test/scala/SystemCSuite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | import org.junit.Assert._ 31 | import org.junit.Test 32 | import org.junit.Ignore 33 | 34 | //package ChiselTests 35 | import Chisel._ 36 | 37 | 38 | /** This testsuite checks the SystemC backend implementation. 39 | */ 40 | class SystemCSuite extends TestSuite { 41 | // Test top-level IOs are decoupled. 42 | @Test def testTopLevelIO() { 43 | 44 | class SystemCModuleGood extends Module { 45 | val io = new Bundle { 46 | val a = Decoupled( UInt(width = 16) ).flip() 47 | val b = Decoupled( UInt(width = 16) ) 48 | } 49 | 50 | io.b.bits := io.a.bits + UInt(10) 51 | io.a.ready := io.b.ready 52 | io.b.valid := io.a.valid 53 | } 54 | 55 | class SystemCModuleBad extends Module { 56 | val io = new Bundle { 57 | val a = UInt(INPUT, width = 16) 58 | val b = UInt(OUTPUT, width = 16) 59 | } 60 | 61 | io.b := io.a + UInt(10) 62 | } 63 | 64 | val testArgs = chiselEnvironmentArguments() ++ Array("--targetDir", dir.getPath, "--backend", "sysc") 65 | 66 | chiselMain(testArgs.toArray, () => Module(new SystemCModuleGood())) 67 | assertFalse(ChiselError.hasErrors) 68 | 69 | chiselMain(testArgs.toArray, () => Module(new SystemCModuleBad())) 70 | assertTrue(ChiselError.hasErrors) 71 | } 72 | } 73 | -------------------------------------------------------------------------------- /src/test/scala/VCDVerifySuite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import org.junit.Assert._ 32 | import org.junit.Test 33 | import org.junit.Ignore 34 | import scala.collection.mutable.HashMap 35 | import scala.sys.process._ 36 | 37 | import Chisel._ 38 | 39 | object VCDVerifySuite { 40 | val backends = List("c") /* ++ 41 | (if (Driver.isVCSAvailable) { 42 | "v" :: Nil 43 | } else { 44 | Nil 45 | } 46 | ) */ 47 | } 48 | 49 | class VCDVerifySuite extends TestSuite { 50 | 51 | // We currently ignore this test until assertVCDFile is updated to deal with redundant signal values. 52 | @Test def verifyVCD1() { 53 | class Hz extends Module { 54 | val io = new Bundle { 55 | val input = Bool(INPUT) 56 | val output = Bool(OUTPUT) 57 | } 58 | val reg = Reg(init = Bool(false)) 59 | when (io.input) { 60 | reg := Bool(true) 61 | } 62 | io.output := reg 63 | } 64 | 65 | class Top extends Module { 66 | val io = new Bundle { 67 | val input = Bool(INPUT) 68 | val output = Bool(OUTPUT) 69 | } 70 | val hz = Module(new Hz) 71 | hz.io <> io 72 | } 73 | 74 | class VCDTester(c: Top) extends Tester(c) { 75 | step(1) 76 | poke(c.io.input, true) 77 | step(5) 78 | } 79 | 80 | for (backend <- VCDVerifySuite.backends) { 81 | chiselMain(Array[String]("--backend", backend, "--compile", "--genHarness", "--test", "--vcd", 82 | "--targetDir", dir.getPath.toString()), 83 | () => Module(new Top()), (c: Top) => new VCDTester(c)) 84 | assertVCDFile("VCDVerifySuite_Top_1.vcd") 85 | } 86 | } 87 | } 88 | 89 | -------------------------------------------------------------------------------- /src/test/scala/VecApp.scala: -------------------------------------------------------------------------------- 1 | //package ChiselTests 2 | import Chisel._ 3 | import org.junit.Test 4 | import org.junit.Assert._ 5 | 6 | class VecSuite extends TestSuite { 7 | @Test def testMiscVec() { 8 | println("\ntestMiscVec ...") 9 | 10 | class VecApp(n: Int, W: Int) extends Module { 11 | class MyBundle(aWidth: Int) extends Bundle { 12 | val aUInt = UInt(width = aWidth) 13 | } 14 | val io = IO(new Bundle { 15 | val a = UInt(INPUT, n) 16 | val i = Vec(n, Bits(INPUT, W)) 17 | val d = Bits(OUTPUT, W) 18 | }) 19 | io.d := io.i(io.a) 20 | } 21 | 22 | val testArgs = chiselEnvironmentArguments() ++ Array("--targetDir", dir.getPath.toString(), 23 | "--minimumCompatibility", "3.0.0", "--wError", "--backend", "null") 24 | chiselMain(testArgs, () => Module(new VecApp(8, 9))) 25 | assertFalse(ChiselError.hasErrors) 26 | } 27 | 28 | @Test def testEmptyVec() { 29 | println("\ntestEmptyVec ...") 30 | 31 | class EmptyVec(n: Int) extends Module { 32 | class MyBundle(aWidth: Int) extends Bundle { 33 | val aUInt = UInt(width = aWidth) 34 | } 35 | val io = IO(new Bundle { 36 | val empty = Vec(0, new MyBundle(n).asOutput) 37 | }) 38 | } 39 | 40 | val testArgs = chiselEnvironmentArguments() ++ Array("--targetDir", dir.getPath.toString(), 41 | "--minimumCompatibility", "3.0.0", "--wError", "--backend", "null") 42 | intercept[IllegalStateException] { 43 | chiselMain(testArgs, () => Module(new EmptyVec(8))) 44 | } 45 | assertTrue(ChiselError.hasErrors) 46 | } 47 | // Issue #718 - Vec.fill with vec initializer 48 | @Test def testVecFillFromVec() { 49 | println("\ntestVecFillFromVec ...") 50 | 51 | class VecApp(n: Int) extends Module { 52 | val io = IO(new Bundle { 53 | val a = UInt(INPUT, n) 54 | }) 55 | val z = Vec(32, UInt(32, width=16)) 56 | var i = 0 57 | val x = Vec.fill( 32 ) 58 | { 59 | val y = z(i) 60 | i = i + 1 61 | y 62 | } 63 | } 64 | 65 | val testArgs = chiselEnvironmentArguments() ++ Array("--targetDir", dir.getPath.toString(), 66 | /* "--minimumCompatibility", "3.0.0", "--wError",*/ "--backend", "null") 67 | chiselMain(testArgs, () => Module(new VecApp(32))) 68 | assertFalse(ChiselError.hasErrors) 69 | 70 | } 71 | } 72 | -------------------------------------------------------------------------------- /src/test/scala/VersionSuite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2011 - 2016 The Regents of the University of 3 | California (Regents). All Rights Reserved. Redistribution and use in 4 | source and binary forms, with or without modification, are permitted 5 | provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above 8 | copyright notice, this list of conditions and the following 9 | two paragraphs of disclaimer. 10 | * Redistributions in binary form must reproduce the above 11 | copyright notice, this list of conditions and the following 12 | two paragraphs of disclaimer in the documentation and/or other materials 13 | provided with the distribution. 14 | * Neither the name of the Regents nor the names of its contributors 15 | may be used to endorse or promote products derived from this 16 | software without specific prior written permission. 17 | 18 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 19 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, 20 | ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF 21 | REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 | 23 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF 26 | ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION 27 | TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 28 | MODIFICATIONS. 29 | */ 30 | 31 | import scala.collection.mutable.ArrayBuffer 32 | import org.scalatest._ 33 | //import org.junit.Assert._ 34 | import org.junit.Test 35 | 36 | import Chisel._ 37 | class VersionSuite extends TestSuite { 38 | @Test def testValidVersions() { 39 | val versions = Array[(Version, Version, String)]( 40 | ("", "99.99.99", "!="), 41 | ("", "", "=="), 42 | ("3", "2.99.99", "!="), 43 | ("4", "3", "!="), 44 | ("3", "3.99.99", "!="), 45 | ("3.99.99", "3", "!="), 46 | ("3.0", "2.9", "!="), 47 | ("3.9", "3", "!="), 48 | ("3.9", "3.0", "!="), 49 | ("3.9", "3.9.99", "!="), 50 | ("3.2.1", "3.2.1", "==") 51 | 52 | ) 53 | for((v1, v2, eq) <- versions) { 54 | assert(v1 >= v2) 55 | if (eq == "==") { 56 | assert(v1 == v2) 57 | } else { 58 | assert(v1 != v2) 59 | } 60 | } 61 | } 62 | 63 | @Test def testInvalidVersions() { 64 | val versions = Array[String]( 65 | ("foo"), 66 | ("3..5"), 67 | ("3.4.5.6") 68 | ) 69 | for(s <- versions) { 70 | intercept[IllegalArgumentException] { 71 | val v = Version(s) 72 | } 73 | } 74 | } 75 | } --------------------------------------------------------------------------------