├── .github └── workflows │ ├── apt-packages.txt │ └── continuous-integration.yml ├── .gitignore ├── ChangeLog.md ├── LICENSE ├── Makefile.in ├── README.md ├── VERSION ├── aclocal.m4 ├── arch_test_target └── spike │ ├── Makefile.include │ ├── README.md │ ├── device │ ├── rv32i_m │ │ ├── C │ │ │ └── Makefile.include │ │ ├── I │ │ │ └── Makefile.include │ │ ├── M │ │ │ └── Makefile.include │ │ ├── Zifencei │ │ │ └── Makefile.include │ │ └── privilege │ │ │ └── Makefile.include │ └── rv64i_m │ │ ├── C │ │ └── Makefile.include │ │ ├── I │ │ └── Makefile.include │ │ ├── M │ │ └── Makefile.include │ │ ├── Zifencei │ │ └── Makefile.include │ │ └── privilege │ │ └── Makefile.include │ ├── link.ld │ └── model_test.h ├── ax_append_flag.m4 ├── ax_append_link_flags.m4 ├── ax_boost_asio.m4 ├── ax_boost_base.m4 ├── ax_boost_regex.m4 ├── ax_check_compile_flag.m4 ├── ax_check_link_flag.m4 ├── ax_require_defined.m4 ├── ci-tests └── test-spike ├── config.h.in ├── configure ├── configure.ac ├── customext ├── cflush.cc ├── customext.ac ├── customext.mk.in ├── dummy_rocc.cc └── dummy_rocc_test.c ├── debug_rom ├── .gitignore ├── Makefile ├── debug_rom.S ├── debug_rom.h └── link.ld ├── disasm ├── disasm.ac ├── disasm.cc ├── disasm.mk.in └── regnames.cc ├── fdt ├── fdt.ac ├── fdt.c ├── fdt.h ├── fdt.mk.in ├── fdt_addresses.c ├── fdt_empty_tree.c ├── fdt_overlay.c ├── fdt_ro.c ├── fdt_rw.c ├── fdt_strerror.c ├── fdt_sw.c ├── fdt_wip.c ├── libfdt.h ├── libfdt_env.h └── libfdt_internal.h ├── fesvr ├── byteorder.h ├── context.cc ├── context.h ├── debug_defines.h ├── device.cc ├── device.h ├── dtm.cc ├── dtm.h ├── dummy.cc ├── elf.h ├── elf2hex.cc ├── elfloader.cc ├── elfloader.h ├── fesvr.ac ├── fesvr.mk.in ├── fesvr.pc.in ├── htif.cc ├── htif.h ├── htif_hexwriter.cc ├── htif_hexwriter.h ├── htif_pthread.cc ├── htif_pthread.h ├── memif.cc ├── memif.h ├── option_parser.cc ├── option_parser.h ├── rfb.cc ├── rfb.h ├── syscall.cc ├── syscall.h ├── term.cc ├── term.h ├── tsi.cc └── tsi.h ├── gemmini ├── gemmini.ac ├── gemmini.cc ├── gemmini.h ├── gemmini.mk.in └── gemmini_params.h ├── hwacha ├── .gitignore ├── README ├── cvt16.cc ├── cvt16.h ├── decode_hwacha.h ├── decode_hwacha_ut.h ├── encodings_hwacha.h ├── hwacha.ac ├── hwacha.cc ├── hwacha.h ├── hwacha.mk.in ├── hwacha_disasm.cc ├── hwacha_xcpt.h ├── insn_template_hwacha.cc ├── insn_template_hwacha.h ├── insn_template_hwacha_ut.cc ├── insn_template_hwacha_ut.h ├── insns │ ├── venqcmd.h │ ├── venqcnt.h │ ├── venqimm1.h │ ├── venqimm2.h │ ├── vf.h │ ├── vft.h │ ├── vgetcfg.h │ ├── vgetvl.h │ ├── vmca.h │ ├── vmcs.h │ ├── vsetcfg.h │ ├── vsetucfg.h │ ├── vsetvlh.h │ ├── vuncfg.h │ ├── vxcptaux.h │ ├── vxcptcause.h │ ├── vxcptevac.h │ ├── vxcpthold.h │ ├── vxcptkill.h │ ├── vxcptrestore.h │ └── vxcptsave.h ├── insns_ut │ ├── vadd.h │ ├── vaddi.h │ ├── vaddiw.h │ ├── vaddu.h │ ├── vaddw.h │ ├── vamoadd_d.h │ ├── vamoadd_w.h │ ├── vamoand_d.h │ ├── vamoand_w.h │ ├── vamomax_d.h │ ├── vamomax_w.h │ ├── vamomaxu_d.h │ ├── vamomaxu_w.h │ ├── vamomin_d.h │ ├── vamomin_w.h │ ├── vamominu_d.h │ ├── vamominu_w.h │ ├── vamoor_d.h │ ├── vamoor_w.h │ ├── vamoswap_d.h │ ├── vamoswap_w.h │ ├── vamoxor_d.h │ ├── vamoxor_w.h │ ├── vand.h │ ├── vandi.h │ ├── vauipc.h │ ├── vcjal.h │ ├── vcjalr.h │ ├── vcmpeq.h │ ├── vcmpfeq_d.h │ ├── vcmpfeq_h.h │ ├── vcmpfeq_s.h │ ├── vcmpfle_d.h │ ├── vcmpfle_h.h │ ├── vcmpfle_s.h │ ├── vcmpflt_d.h │ ├── vcmpflt_h.h │ ├── vcmpflt_s.h │ ├── vcmplt.h │ ├── vcmpltu.h │ ├── vdiv.h │ ├── vdivu.h │ ├── vdivuw.h │ ├── vdivw.h │ ├── veidx.h │ ├── vfadd_d.h │ ├── vfadd_d_h.h │ ├── vfadd_d_s.h │ ├── vfadd_h.h │ ├── vfadd_s.h │ ├── vfadd_s_h.h │ ├── vfclass_d.h │ ├── vfclass_h.h │ ├── vfclass_s.h │ ├── vfcvt_d_h.h │ ├── vfcvt_d_l.h │ ├── vfcvt_d_lu.h │ ├── vfcvt_d_s.h │ ├── vfcvt_d_w.h │ ├── vfcvt_d_wu.h │ ├── vfcvt_h_d.h │ ├── vfcvt_h_l.h │ ├── vfcvt_h_lu.h │ ├── vfcvt_h_s.h │ ├── vfcvt_h_w.h │ ├── vfcvt_h_wu.h │ ├── vfcvt_l_d.h │ ├── vfcvt_l_h.h │ ├── vfcvt_l_s.h │ ├── vfcvt_lu_d.h │ ├── vfcvt_lu_h.h │ ├── vfcvt_lu_s.h │ ├── vfcvt_s_d.h │ ├── vfcvt_s_h.h │ ├── vfcvt_s_l.h │ ├── vfcvt_s_lu.h │ ├── vfcvt_s_w.h │ ├── vfcvt_s_wu.h │ ├── vfcvt_w_d.h │ ├── vfcvt_w_h.h │ ├── vfcvt_w_s.h │ ├── vfcvt_wu_d.h │ ├── vfcvt_wu_h.h │ ├── vfcvt_wu_s.h │ ├── vfdiv_d.h │ ├── vfdiv_h.h │ ├── vfdiv_s.h │ ├── vfence.h │ ├── vfirst.h │ ├── vfmadd_d.h │ ├── vfmadd_d_h.h │ ├── vfmadd_d_s.h │ ├── vfmadd_h.h │ ├── vfmadd_s.h │ ├── vfmadd_s_h.h │ ├── vfmax_d.h │ ├── vfmax_h.h │ ├── vfmax_s.h │ ├── vfmin_d.h │ ├── vfmin_h.h │ ├── vfmin_s.h │ ├── vfmsub_d.h │ ├── vfmsub_d_h.h │ ├── vfmsub_d_s.h │ ├── vfmsub_h.h │ ├── vfmsub_s.h │ ├── vfmsub_s_h.h │ ├── vfmul_d.h │ ├── vfmul_d_h.h │ ├── vfmul_d_s.h │ ├── vfmul_h.h │ ├── vfmul_s.h │ ├── vfmul_s_h.h │ ├── vfnmadd_d.h │ ├── vfnmadd_d_h.h │ ├── vfnmadd_d_s.h │ ├── vfnmadd_h.h │ ├── vfnmadd_s.h │ ├── vfnmadd_s_h.h │ ├── vfnmsub_d.h │ ├── vfnmsub_d_h.h │ ├── vfnmsub_d_s.h │ ├── vfnmsub_h.h │ ├── vfnmsub_s.h │ ├── vfnmsub_s_h.h │ ├── vfsgnj_d.h │ ├── vfsgnj_h.h │ ├── vfsgnj_s.h │ ├── vfsgnjn_d.h │ ├── vfsgnjn_h.h │ ├── vfsgnjn_s.h │ ├── vfsgnjx_d.h │ ├── vfsgnjx_h.h │ ├── vfsgnjx_s.h │ ├── vfsqrt_d.h │ ├── vfsqrt_h.h │ ├── vfsqrt_s.h │ ├── vfsub_d.h │ ├── vfsub_d_h.h │ ├── vfsub_d_s.h │ ├── vfsub_h.h │ ├── vfsub_s.h │ ├── vfsub_s_h.h │ ├── vlasegb.h │ ├── vlasegbu.h │ ├── vlasegd.h │ ├── vlasegh.h │ ├── vlaseghu.h │ ├── vlasegw.h │ ├── vlasegwu.h │ ├── vlsegb.h │ ├── vlsegbu.h │ ├── vlsegd.h │ ├── vlsegh.h │ ├── vlseghu.h │ ├── vlsegstb.h │ ├── vlsegstbu.h │ ├── vlsegstd.h │ ├── vlsegsth.h │ ├── vlsegsthu.h │ ├── vlsegstw.h │ ├── vlsegstwu.h │ ├── vlsegw.h │ ├── vlsegwu.h │ ├── vlsegxb.h │ ├── vlsegxbu.h │ ├── vlsegxd.h │ ├── vlsegxh.h │ ├── vlsegxhu.h │ ├── vlsegxw.h │ ├── vlsegxwu.h │ ├── vlssegb.h │ ├── vlssegbu.h │ ├── vlssegd.h │ ├── vlssegh.h │ ├── vlsseghu.h │ ├── vlssegw.h │ ├── vlssegwu.h │ ├── vlui.h │ ├── vmul.h │ ├── vmulh.h │ ├── vmulhsu.h │ ├── vmulhu.h │ ├── vmulw.h │ ├── vor.h │ ├── vori.h │ ├── vpl.h │ ├── vpop.h │ ├── vps.h │ ├── vrem.h │ ├── vremu.h │ ├── vremuw.h │ ├── vremw.h │ ├── vsasegb.h │ ├── vsasegd.h │ ├── vsasegh.h │ ├── vsasegw.h │ ├── vsll.h │ ├── vslli.h │ ├── vslliw.h │ ├── vsllw.h │ ├── vslt.h │ ├── vslti.h │ ├── vsltiu.h │ ├── vsltu.h │ ├── vsra.h │ ├── vsrai.h │ ├── vsraiw.h │ ├── vsraw.h │ ├── vsrl.h │ ├── vsrli.h │ ├── vsrliw.h │ ├── vsrlw.h │ ├── vssegb.h │ ├── vssegd.h │ ├── vssegh.h │ ├── vssegstb.h │ ├── vssegstd.h │ ├── vssegsth.h │ ├── vssegstw.h │ ├── vssegw.h │ ├── vssegxb.h │ ├── vssegxd.h │ ├── vssegxh.h │ ├── vssegxw.h │ ├── vsssegb.h │ ├── vsssegd.h │ ├── vsssegh.h │ ├── vsssegw.h │ ├── vstop.h │ ├── vsub.h │ ├── vsubw.h │ ├── vxor.h │ └── vxori.h ├── opcodes_hwacha.h └── opcodes_hwacha_ut.h ├── riscv-disasm.pc.in ├── riscv-fesvr.pc.in ├── riscv-gemmini.pc.in ├── riscv-hwacha.pc.in ├── riscv-sha3.pc.in ├── riscv ├── abstract_device.h ├── arith.h ├── cachesim.cc ├── cachesim.h ├── clint.cc ├── common.h ├── csrs.cc ├── csrs.h ├── debug_defines.h ├── debug_module.cc ├── debug_module.h ├── debug_rom_defines.h ├── decode.h ├── devices.cc ├── devices.h ├── disasm.h ├── dts.cc ├── dts.h ├── encoding.h ├── entropy_source.h ├── execute.cc ├── extension.cc ├── extension.h ├── extensions.cc ├── insn_template.cc ├── insn_template.h ├── insns │ ├── add.h │ ├── add16.h │ ├── add32.h │ ├── add64.h │ ├── add8.h │ ├── add_uw.h │ ├── addi.h │ ├── addiw.h │ ├── addw.h │ ├── aes32dsi.h │ ├── aes32dsmi.h │ ├── aes32esi.h │ ├── aes32esmi.h │ ├── aes64ds.h │ ├── aes64dsm.h │ ├── aes64es.h │ ├── aes64esm.h │ ├── aes64im.h │ ├── aes64ks1i.h │ ├── aes64ks2.h │ ├── aes_common.h │ ├── amoadd_d.h │ ├── amoadd_w.h │ ├── amoand_d.h │ ├── amoand_w.h │ ├── amomax_d.h │ ├── amomax_w.h │ ├── amomaxu_d.h │ ├── amomaxu_w.h │ ├── amomin_d.h │ ├── amomin_w.h │ ├── amominu_d.h │ ├── amominu_w.h │ ├── amoor_d.h │ ├── amoor_w.h │ ├── amoswap_d.h │ ├── amoswap_w.h │ ├── amoxor_d.h │ ├── amoxor_w.h │ ├── and.h │ ├── andi.h │ ├── andn.h │ ├── auipc.h │ ├── ave.h │ ├── bclr.h │ ├── bclri.h │ ├── bcompress.h │ ├── bcompressw.h │ ├── bdecompress.h │ ├── bdecompressw.h │ ├── beq.h │ ├── bext.h │ ├── bexti.h │ ├── bfp.h │ ├── bfpw.h │ ├── bge.h │ ├── bgeu.h │ ├── binv.h │ ├── binvi.h │ ├── bitrev.h │ ├── bitrevi.h │ ├── blt.h │ ├── bltu.h │ ├── bmatflip.h │ ├── bmator.h │ ├── bmatxor.h │ ├── bne.h │ ├── bpick.h │ ├── bset.h │ ├── bseti.h │ ├── c_add.h │ ├── c_addi.h │ ├── c_addi4spn.h │ ├── c_addw.h │ ├── c_and.h │ ├── c_andi.h │ ├── c_beqz.h │ ├── c_bnez.h │ ├── c_ebreak.h │ ├── c_fld.h │ ├── c_fldsp.h │ ├── c_flw.h │ ├── c_flwsp.h │ ├── c_fsd.h │ ├── c_fsdsp.h │ ├── c_fsw.h │ ├── c_fswsp.h │ ├── c_j.h │ ├── c_jal.h │ ├── c_jalr.h │ ├── c_jr.h │ ├── c_li.h │ ├── c_lui.h │ ├── c_lw.h │ ├── c_lwsp.h │ ├── c_mv.h │ ├── c_or.h │ ├── c_slli.h │ ├── c_srai.h │ ├── c_srli.h │ ├── c_sub.h │ ├── c_subw.h │ ├── c_sw.h │ ├── c_swsp.h │ ├── c_xor.h │ ├── clmul.h │ ├── clmulh.h │ ├── clmulhw.h │ ├── clmulr.h │ ├── clmulrw.h │ ├── clmulw.h │ ├── clo16.h │ ├── clo32.h │ ├── clo8.h │ ├── clrs16.h │ ├── clrs32.h │ ├── clrs8.h │ ├── clz.h │ ├── clz16.h │ ├── clz32.h │ ├── clz8.h │ ├── clzw.h │ ├── cmix.h │ ├── cmov.h │ ├── cmpeq16.h │ ├── cmpeq8.h │ ├── cpop.h │ ├── cpopw.h │ ├── cras16.h │ ├── cras32.h │ ├── crc32_b.h │ ├── crc32_d.h │ ├── crc32_h.h │ ├── crc32_w.h │ ├── crc32c_b.h │ ├── crc32c_d.h │ ├── crc32c_h.h │ ├── crc32c_w.h │ ├── crsa16.h │ ├── crsa32.h │ ├── csrrc.h │ ├── csrrci.h │ ├── csrrs.h │ ├── csrrsi.h │ ├── csrrw.h │ ├── csrrwi.h │ ├── ctz.h │ ├── ctzw.h │ ├── div.h │ ├── divu.h │ ├── divuw.h │ ├── divw.h │ ├── dret.h │ ├── ebreak.h │ ├── ecall.h │ ├── fadd_d.h │ ├── fadd_h.h │ ├── fadd_q.h │ ├── fadd_s.h │ ├── fclass_d.h │ ├── fclass_h.h │ ├── fclass_q.h │ ├── fclass_s.h │ ├── fcvt_d_h.h │ ├── fcvt_d_l.h │ ├── fcvt_d_lu.h │ ├── fcvt_d_q.h │ ├── fcvt_d_s.h │ ├── fcvt_d_w.h │ ├── fcvt_d_wu.h │ ├── fcvt_h_d.h │ ├── fcvt_h_l.h │ ├── fcvt_h_lu.h │ ├── fcvt_h_q.h │ ├── fcvt_h_s.h │ ├── fcvt_h_w.h │ ├── fcvt_h_wu.h │ ├── fcvt_l_d.h │ ├── fcvt_l_h.h │ ├── fcvt_l_q.h │ ├── fcvt_l_s.h │ ├── fcvt_lu_d.h │ ├── fcvt_lu_h.h │ ├── fcvt_lu_q.h │ ├── fcvt_lu_s.h │ ├── fcvt_q_d.h │ ├── fcvt_q_h.h │ ├── fcvt_q_l.h │ ├── fcvt_q_lu.h │ ├── fcvt_q_s.h │ ├── fcvt_q_w.h │ ├── fcvt_q_wu.h │ ├── fcvt_s_d.h │ ├── fcvt_s_h.h │ ├── fcvt_s_l.h │ ├── fcvt_s_lu.h │ ├── fcvt_s_q.h │ ├── fcvt_s_w.h │ ├── fcvt_s_wu.h │ ├── fcvt_w_d.h │ ├── fcvt_w_h.h │ ├── fcvt_w_q.h │ ├── fcvt_w_s.h │ ├── fcvt_wu_d.h │ ├── fcvt_wu_h.h │ ├── fcvt_wu_q.h │ ├── fcvt_wu_s.h │ ├── fdiv_d.h │ ├── fdiv_h.h │ ├── fdiv_q.h │ ├── fdiv_s.h │ ├── fence.h │ ├── fence_i.h │ ├── feq_d.h │ ├── feq_h.h │ ├── feq_q.h │ ├── feq_s.h │ ├── fld.h │ ├── fle_d.h │ ├── fle_h.h │ ├── fle_q.h │ ├── fle_s.h │ ├── flh.h │ ├── flq.h │ ├── flt_d.h │ ├── flt_h.h │ ├── flt_q.h │ ├── flt_s.h │ ├── flw.h │ ├── fmadd_d.h │ ├── fmadd_h.h │ ├── fmadd_q.h │ ├── fmadd_s.h │ ├── fmax_d.h │ ├── fmax_h.h │ ├── fmax_q.h │ ├── fmax_s.h │ ├── fmin_d.h │ ├── fmin_h.h │ ├── fmin_q.h │ ├── fmin_s.h │ ├── fmsub_d.h │ ├── fmsub_h.h │ ├── fmsub_q.h │ ├── fmsub_s.h │ ├── fmul_d.h │ ├── fmul_h.h │ ├── fmul_q.h │ ├── fmul_s.h │ ├── fmv_d_x.h │ ├── fmv_h_x.h │ ├── fmv_w_x.h │ ├── fmv_x_d.h │ ├── fmv_x_h.h │ ├── fmv_x_w.h │ ├── fnmadd_d.h │ ├── fnmadd_h.h │ ├── fnmadd_q.h │ ├── fnmadd_s.h │ ├── fnmsub_d.h │ ├── fnmsub_h.h │ ├── fnmsub_q.h │ ├── fnmsub_s.h │ ├── fsd.h │ ├── fsgnj_d.h │ ├── fsgnj_h.h │ ├── fsgnj_q.h │ ├── fsgnj_s.h │ ├── fsgnjn_d.h │ ├── fsgnjn_h.h │ ├── fsgnjn_q.h │ ├── fsgnjn_s.h │ ├── fsgnjx_d.h │ ├── fsgnjx_h.h │ ├── fsgnjx_q.h │ ├── fsgnjx_s.h │ ├── fsh.h │ ├── fsl.h │ ├── fslw.h │ ├── fsq.h │ ├── fsqrt_d.h │ ├── fsqrt_h.h │ ├── fsqrt_q.h │ ├── fsqrt_s.h │ ├── fsr.h │ ├── fsri.h │ ├── fsriw.h │ ├── fsrw.h │ ├── fsub_d.h │ ├── fsub_h.h │ ├── fsub_q.h │ ├── fsub_s.h │ ├── fsw.h │ ├── gorc.h │ ├── gorci.h │ ├── gorciw.h │ ├── gorcw.h │ ├── grev.h │ ├── grevi.h │ ├── greviw.h │ ├── grevw.h │ ├── hfence_gvma.h │ ├── hfence_vvma.h │ ├── hinval_gvma.h │ ├── hinval_vvma.h │ ├── hlv_b.h │ ├── hlv_bu.h │ ├── hlv_d.h │ ├── hlv_h.h │ ├── hlv_hu.h │ ├── hlv_w.h │ ├── hlv_wu.h │ ├── hlvx_hu.h │ ├── hlvx_wu.h │ ├── hsv_b.h │ ├── hsv_d.h │ ├── hsv_h.h │ ├── hsv_w.h │ ├── insb.h │ ├── jal.h │ ├── jalr.h │ ├── kabs16.h │ ├── kabs32.h │ ├── kabs8.h │ ├── kabsw.h │ ├── kadd16.h │ ├── kadd32.h │ ├── kadd64.h │ ├── kadd8.h │ ├── kaddh.h │ ├── kaddw.h │ ├── kcras16.h │ ├── kcras32.h │ ├── kcrsa16.h │ ├── kcrsa32.h │ ├── kdmabb.h │ ├── kdmabb16.h │ ├── kdmabt.h │ ├── kdmabt16.h │ ├── kdmatt.h │ ├── kdmatt16.h │ ├── kdmbb.h │ ├── kdmbb16.h │ ├── kdmbt.h │ ├── kdmbt16.h │ ├── kdmtt.h │ ├── kdmtt16.h │ ├── khm16.h │ ├── khm8.h │ ├── khmbb.h │ ├── khmbb16.h │ ├── khmbt.h │ ├── khmbt16.h │ ├── khmtt.h │ ├── khmtt16.h │ ├── khmx16.h │ ├── khmx8.h │ ├── kmabb.h │ ├── kmabb32.h │ ├── kmabt.h │ ├── kmabt32.h │ ├── kmada.h │ ├── kmadrs.h │ ├── kmadrs32.h │ ├── kmads.h │ ├── kmads32.h │ ├── kmar64.h │ ├── kmatt.h │ ├── kmatt32.h │ ├── kmaxda.h │ ├── kmaxda32.h │ ├── kmaxds.h │ ├── kmaxds32.h │ ├── kmda.h │ ├── kmda32.h │ ├── kmmac.h │ ├── kmmac_u.h │ ├── kmmawb.h │ ├── kmmawb2.h │ ├── kmmawb2_u.h │ ├── kmmawb_u.h │ ├── kmmawt.h │ ├── kmmawt2.h │ ├── kmmawt2_u.h │ ├── kmmawt_u.h │ ├── kmmsb.h │ ├── kmmsb_u.h │ ├── kmmwb2.h │ ├── kmmwb2_u.h │ ├── kmmwt2.h │ ├── kmmwt2_u.h │ ├── kmsda.h │ ├── kmsda32.h │ ├── kmsr64.h │ ├── kmsxda.h │ ├── kmsxda32.h │ ├── kmxda.h │ ├── kmxda32.h │ ├── ksll16.h │ ├── ksll32.h │ ├── ksll8.h │ ├── kslli16.h │ ├── kslli32.h │ ├── kslli8.h │ ├── kslliw.h │ ├── ksllw.h │ ├── kslra16.h │ ├── kslra16_u.h │ ├── kslra32.h │ ├── kslra32_u.h │ ├── kslra8.h │ ├── kslra8_u.h │ ├── kslraw.h │ ├── kslraw_u.h │ ├── kstas16.h │ ├── kstas32.h │ ├── kstsa16.h │ ├── kstsa32.h │ ├── ksub16.h │ ├── ksub32.h │ ├── ksub64.h │ ├── ksub8.h │ ├── ksubh.h │ ├── ksubw.h │ ├── kwmmul.h │ ├── kwmmul_u.h │ ├── lb.h │ ├── lbu.h │ ├── ld.h │ ├── lh.h │ ├── lhu.h │ ├── lr_d.h │ ├── lr_w.h │ ├── lui.h │ ├── lw.h │ ├── lwu.h │ ├── maddr32.h │ ├── max.h │ ├── maxu.h │ ├── maxw.h │ ├── min.h │ ├── minu.h │ ├── minw.h │ ├── mret.h │ ├── msubr32.h │ ├── mul.h │ ├── mulh.h │ ├── mulhsu.h │ ├── mulhu.h │ ├── mulr64.h │ ├── mulsr64.h │ ├── mulw.h │ ├── or.h │ ├── ori.h │ ├── orn.h │ ├── pack.h │ ├── packh.h │ ├── packu.h │ ├── packuw.h │ ├── packw.h │ ├── pbsad.h │ ├── pbsada.h │ ├── pkbb16.h │ ├── pkbb32.h │ ├── pkbt16.h │ ├── pkbt32.h │ ├── pktb16.h │ ├── pktb32.h │ ├── pktt16.h │ ├── pktt32.h │ ├── radd16.h │ ├── radd32.h │ ├── radd64.h │ ├── radd8.h │ ├── raddw.h │ ├── rcras16.h │ ├── rcras32.h │ ├── rcrsa16.h │ ├── rcrsa32.h │ ├── rem.h │ ├── remu.h │ ├── remuw.h │ ├── remw.h │ ├── rol.h │ ├── rolw.h │ ├── ror.h │ ├── rori.h │ ├── roriw.h │ ├── rorw.h │ ├── rstas16.h │ ├── rstas32.h │ ├── rstsa16.h │ ├── rstsa32.h │ ├── rsub16.h │ ├── rsub32.h │ ├── rsub64.h │ ├── rsub8.h │ ├── rsubw.h │ ├── sb.h │ ├── sc_d.h │ ├── sc_w.h │ ├── sclip16.h │ ├── sclip32.h │ ├── sclip8.h │ ├── scmple16.h │ ├── scmple8.h │ ├── scmplt16.h │ ├── scmplt8.h │ ├── sd.h │ ├── sext_b.h │ ├── sext_h.h │ ├── sfence_inval_ir.h │ ├── sfence_vma.h │ ├── sfence_w_inval.h │ ├── sh.h │ ├── sh1add.h │ ├── sh1add_uw.h │ ├── sh2add.h │ ├── sh2add_uw.h │ ├── sh3add.h │ ├── sh3add_uw.h │ ├── sha256sig0.h │ ├── sha256sig1.h │ ├── sha256sum0.h │ ├── sha256sum1.h │ ├── sha512sig0.h │ ├── sha512sig0h.h │ ├── sha512sig0l.h │ ├── sha512sig1.h │ ├── sha512sig1h.h │ ├── sha512sig1l.h │ ├── sha512sum0.h │ ├── sha512sum0r.h │ ├── sha512sum1.h │ ├── sha512sum1r.h │ ├── shfl.h │ ├── shfli.h │ ├── shflw.h │ ├── sinval_vma.h │ ├── sll.h │ ├── sll16.h │ ├── sll32.h │ ├── sll8.h │ ├── slli.h │ ├── slli16.h │ ├── slli32.h │ ├── slli8.h │ ├── slli_uw.h │ ├── slliw.h │ ├── sllw.h │ ├── slo.h │ ├── sloi.h │ ├── sloiw.h │ ├── slow.h │ ├── slt.h │ ├── slti.h │ ├── sltiu.h │ ├── sltu.h │ ├── sm3p0.h │ ├── sm3p1.h │ ├── sm4_common.h │ ├── sm4ed.h │ ├── sm4ks.h │ ├── smal.h │ ├── smalbb.h │ ├── smalbt.h │ ├── smalda.h │ ├── smaldrs.h │ ├── smalds.h │ ├── smaltt.h │ ├── smalxda.h │ ├── smalxds.h │ ├── smaqa.h │ ├── smaqa_su.h │ ├── smar64.h │ ├── smax16.h │ ├── smax32.h │ ├── smax8.h │ ├── smbb16.h │ ├── smbt16.h │ ├── smbt32.h │ ├── smdrs.h │ ├── smdrs32.h │ ├── smds.h │ ├── smds32.h │ ├── smin16.h │ ├── smin32.h │ ├── smin8.h │ ├── smmul.h │ ├── smmul_u.h │ ├── smmwb.h │ ├── smmwb_u.h │ ├── smmwt.h │ ├── smmwt_u.h │ ├── smslda.h │ ├── smslxda.h │ ├── smsr64.h │ ├── smtt16.h │ ├── smtt32.h │ ├── smul16.h │ ├── smul8.h │ ├── smulx16.h │ ├── smulx8.h │ ├── smxds.h │ ├── smxds32.h │ ├── sra.h │ ├── sra16.h │ ├── sra16_u.h │ ├── sra32.h │ ├── sra32_u.h │ ├── sra8.h │ ├── sra8_u.h │ ├── sra_u.h │ ├── srai.h │ ├── srai16.h │ ├── srai16_u.h │ ├── srai32.h │ ├── srai32_u.h │ ├── srai8.h │ ├── srai8_u.h │ ├── srai_u.h │ ├── sraiw.h │ ├── sraiw_u.h │ ├── sraw.h │ ├── sret.h │ ├── srl.h │ ├── srl16.h │ ├── srl16_u.h │ ├── srl32.h │ ├── srl32_u.h │ ├── srl8.h │ ├── srl8_u.h │ ├── srli.h │ ├── srli16.h │ ├── srli16_u.h │ ├── srli32.h │ ├── srli32_u.h │ ├── srli8.h │ ├── srli8_u.h │ ├── srliw.h │ ├── srlw.h │ ├── sro.h │ ├── sroi.h │ ├── sroiw.h │ ├── srow.h │ ├── stas16.h │ ├── stas32.h │ ├── stsa16.h │ ├── stsa32.h │ ├── sub.h │ ├── sub16.h │ ├── sub32.h │ ├── sub64.h │ ├── sub8.h │ ├── subw.h │ ├── sunpkd810.h │ ├── sunpkd820.h │ ├── sunpkd830.h │ ├── sunpkd831.h │ ├── sunpkd832.h │ ├── sw.h │ ├── swap8.h │ ├── uclip16.h │ ├── uclip32.h │ ├── uclip8.h │ ├── ucmple16.h │ ├── ucmple8.h │ ├── ucmplt16.h │ ├── ucmplt8.h │ ├── ukadd16.h │ ├── ukadd32.h │ ├── ukadd64.h │ ├── ukadd8.h │ ├── ukaddh.h │ ├── ukaddw.h │ ├── ukcras16.h │ ├── ukcras32.h │ ├── ukcrsa16.h │ ├── ukcrsa32.h │ ├── ukmar64.h │ ├── ukmsr64.h │ ├── ukstas16.h │ ├── ukstas32.h │ ├── ukstsa16.h │ ├── ukstsa32.h │ ├── uksub16.h │ ├── uksub32.h │ ├── uksub64.h │ ├── uksub8.h │ ├── uksubh.h │ ├── uksubw.h │ ├── umaqa.h │ ├── umar64.h │ ├── umax16.h │ ├── umax32.h │ ├── umax8.h │ ├── umin16.h │ ├── umin32.h │ ├── umin8.h │ ├── umsr64.h │ ├── umul16.h │ ├── umul8.h │ ├── umulx16.h │ ├── umulx8.h │ ├── unshfl.h │ ├── unshfli.h │ ├── unshflw.h │ ├── uradd16.h │ ├── uradd32.h │ ├── uradd64.h │ ├── uradd8.h │ ├── uraddw.h │ ├── urcras16.h │ ├── urcras32.h │ ├── urcrsa16.h │ ├── urcrsa32.h │ ├── urstas16.h │ ├── urstas32.h │ ├── urstsa16.h │ ├── urstsa32.h │ ├── ursub16.h │ ├── ursub32.h │ ├── ursub64.h │ ├── ursub8.h │ ├── ursubw.h │ ├── vaadd_vv.h │ ├── vaadd_vx.h │ ├── vaaddu_vv.h │ ├── vaaddu_vx.h │ ├── vadc_vim.h │ ├── vadc_vvm.h │ ├── vadc_vxm.h │ ├── vadd_vi.h │ ├── vadd_vv.h │ ├── vadd_vx.h │ ├── vamoaddei16_v.h │ ├── vamoaddei32_v.h │ ├── vamoaddei64_v.h │ ├── vamoaddei8_v.h │ ├── vamoandei16_v.h │ ├── vamoandei32_v.h │ ├── vamoandei64_v.h │ ├── vamoandei8_v.h │ ├── vamomaxei16_v.h │ ├── vamomaxei32_v.h │ ├── vamomaxei64_v.h │ ├── vamomaxei8_v.h │ ├── vamomaxuei16_v.h │ ├── vamomaxuei32_v.h │ ├── vamomaxuei64_v.h │ ├── vamomaxuei8_v.h │ ├── vamominei16_v.h │ ├── vamominei32_v.h │ ├── vamominei64_v.h │ ├── vamominei8_v.h │ ├── vamominuei16_v.h │ ├── vamominuei32_v.h │ ├── vamominuei64_v.h │ ├── vamominuei8_v.h │ ├── vamoorei16_v.h │ ├── vamoorei32_v.h │ ├── vamoorei64_v.h │ ├── vamoorei8_v.h │ ├── vamoswapei16_v.h │ ├── vamoswapei32_v.h │ ├── vamoswapei64_v.h │ ├── vamoswapei8_v.h │ ├── vamoxorei16_v.h │ ├── vamoxorei32_v.h │ ├── vamoxorei64_v.h │ ├── vamoxorei8_v.h │ ├── vand_vi.h │ ├── vand_vv.h │ ├── vand_vx.h │ ├── vasub_vv.h │ ├── vasub_vx.h │ ├── vasubu_vv.h │ ├── vasubu_vx.h │ ├── vcompress_vm.h │ ├── vcpop_m.h │ ├── vdiv_vv.h │ ├── vdiv_vx.h │ ├── vdivu_vv.h │ ├── vdivu_vx.h │ ├── vfadd_vf.h │ ├── vfadd_vv.h │ ├── vfclass_v.h │ ├── vfcvt_f_x_v.h │ ├── vfcvt_f_xu_v.h │ ├── vfcvt_rtz_x_f_v.h │ ├── vfcvt_rtz_xu_f_v.h │ ├── vfcvt_x_f_v.h │ ├── vfcvt_xu_f_v.h │ ├── vfdiv_vf.h │ ├── vfdiv_vv.h │ ├── vfirst_m.h │ ├── vfmacc_vf.h │ ├── vfmacc_vv.h │ ├── vfmadd_vf.h │ ├── vfmadd_vv.h │ ├── vfmax_vf.h │ ├── vfmax_vv.h │ ├── vfmerge_vfm.h │ ├── vfmin_vf.h │ ├── vfmin_vv.h │ ├── vfmsac_vf.h │ ├── vfmsac_vv.h │ ├── vfmsub_vf.h │ ├── vfmsub_vv.h │ ├── vfmul_vf.h │ ├── vfmul_vv.h │ ├── vfmv_f_s.h │ ├── vfmv_s_f.h │ ├── vfmv_v_f.h │ ├── vfncvt_f_f_w.h │ ├── vfncvt_f_x_w.h │ ├── vfncvt_f_xu_w.h │ ├── vfncvt_rod_f_f_w.h │ ├── vfncvt_rtz_x_f_w.h │ ├── vfncvt_rtz_xu_f_w.h │ ├── vfncvt_x_f_w.h │ ├── vfncvt_xu_f_w.h │ ├── vfnmacc_vf.h │ ├── vfnmacc_vv.h │ ├── vfnmadd_vf.h │ ├── vfnmadd_vv.h │ ├── vfnmsac_vf.h │ ├── vfnmsac_vv.h │ ├── vfnmsub_vf.h │ ├── vfnmsub_vv.h │ ├── vfrdiv_vf.h │ ├── vfrec7_v.h │ ├── vfredmax_vs.h │ ├── vfredmin_vs.h │ ├── vfredosum_vs.h │ ├── vfredusum_vs.h │ ├── vfrsqrt7_v.h │ ├── vfrsub_vf.h │ ├── vfsgnj_vf.h │ ├── vfsgnj_vv.h │ ├── vfsgnjn_vf.h │ ├── vfsgnjn_vv.h │ ├── vfsgnjx_vf.h │ ├── vfsgnjx_vv.h │ ├── vfslide1down_vf.h │ ├── vfslide1up_vf.h │ ├── vfsqrt_v.h │ ├── vfsub_vf.h │ ├── vfsub_vv.h │ ├── vfwadd_vf.h │ ├── vfwadd_vv.h │ ├── vfwadd_wf.h │ ├── vfwadd_wv.h │ ├── vfwcvt_f_f_v.h │ ├── vfwcvt_f_x_v.h │ ├── vfwcvt_f_xu_v.h │ ├── vfwcvt_rtz_x_f_v.h │ ├── vfwcvt_rtz_xu_f_v.h │ ├── vfwcvt_x_f_v.h │ ├── vfwcvt_xu_f_v.h │ ├── vfwmacc_vf.h │ ├── vfwmacc_vv.h │ ├── vfwmsac_vf.h │ ├── vfwmsac_vv.h │ ├── vfwmul_vf.h │ ├── vfwmul_vv.h │ ├── vfwnmacc_vf.h │ ├── vfwnmacc_vv.h │ ├── vfwnmsac_vf.h │ ├── vfwnmsac_vv.h │ ├── vfwredosum_vs.h │ ├── vfwredusum_vs.h │ ├── vfwsub_vf.h │ ├── vfwsub_vv.h │ ├── vfwsub_wf.h │ ├── vfwsub_wv.h │ ├── vid_v.h │ ├── viota_m.h │ ├── vl1re16_v.h │ ├── vl1re32_v.h │ ├── vl1re64_v.h │ ├── vl1re8_v.h │ ├── vl2re16_v.h │ ├── vl2re32_v.h │ ├── vl2re64_v.h │ ├── vl2re8_v.h │ ├── vl4re16_v.h │ ├── vl4re32_v.h │ ├── vl4re64_v.h │ ├── vl4re8_v.h │ ├── vl8re16_v.h │ ├── vl8re32_v.h │ ├── vl8re64_v.h │ ├── vl8re8_v.h │ ├── vle16_v.h │ ├── vle16ff_v.h │ ├── vle32_v.h │ ├── vle32ff_v.h │ ├── vle64_v.h │ ├── vle64ff_v.h │ ├── vle8_v.h │ ├── vle8ff_v.h │ ├── vlm_v.h │ ├── vloxei16_v.h │ ├── vloxei32_v.h │ ├── vloxei64_v.h │ ├── vloxei8_v.h │ ├── vlse16_v.h │ ├── vlse32_v.h │ ├── vlse64_v.h │ ├── vlse8_v.h │ ├── vluxei16_v.h │ ├── vluxei32_v.h │ ├── vluxei64_v.h │ ├── vluxei8_v.h │ ├── vmacc_vv.h │ ├── vmacc_vx.h │ ├── vmadc_vi.h │ ├── vmadc_vim.h │ ├── vmadc_vv.h │ ├── vmadc_vvm.h │ ├── vmadc_vx.h │ ├── vmadc_vxm.h │ ├── vmadd_vv.h │ ├── vmadd_vx.h │ ├── vmand_mm.h │ ├── vmandnot_mm.h │ ├── vmax_vv.h │ ├── vmax_vx.h │ ├── vmaxu_vv.h │ ├── vmaxu_vx.h │ ├── vmerge_vim.h │ ├── vmerge_vvm.h │ ├── vmerge_vxm.h │ ├── vmfeq_vf.h │ ├── vmfeq_vv.h │ ├── vmfge_vf.h │ ├── vmfgt_vf.h │ ├── vmfle_vf.h │ ├── vmfle_vv.h │ ├── vmflt_vf.h │ ├── vmflt_vv.h │ ├── vmfne_vf.h │ ├── vmfne_vv.h │ ├── vmin_vv.h │ ├── vmin_vx.h │ ├── vminu_vv.h │ ├── vminu_vx.h │ ├── vmnand_mm.h │ ├── vmnor_mm.h │ ├── vmor_mm.h │ ├── vmornot_mm.h │ ├── vmsbc_vv.h │ ├── vmsbc_vvm.h │ ├── vmsbc_vx.h │ ├── vmsbc_vxm.h │ ├── vmsbf_m.h │ ├── vmseq_vi.h │ ├── vmseq_vv.h │ ├── vmseq_vx.h │ ├── vmsgt_vi.h │ ├── vmsgt_vx.h │ ├── vmsgtu_vi.h │ ├── vmsgtu_vx.h │ ├── vmsif_m.h │ ├── vmsle_vi.h │ ├── vmsle_vv.h │ ├── vmsle_vx.h │ ├── vmsleu_vi.h │ ├── vmsleu_vv.h │ ├── vmsleu_vx.h │ ├── vmslt_vv.h │ ├── vmslt_vx.h │ ├── vmsltu_vv.h │ ├── vmsltu_vx.h │ ├── vmsne_vi.h │ ├── vmsne_vv.h │ ├── vmsne_vx.h │ ├── vmsof_m.h │ ├── vmul_vv.h │ ├── vmul_vx.h │ ├── vmulh_vv.h │ ├── vmulh_vx.h │ ├── vmulhsu_vv.h │ ├── vmulhsu_vx.h │ ├── vmulhu_vv.h │ ├── vmulhu_vx.h │ ├── vmv1r_v.h │ ├── vmv2r_v.h │ ├── vmv4r_v.h │ ├── vmv8r_v.h │ ├── vmv_s_x.h │ ├── vmv_v_i.h │ ├── vmv_v_v.h │ ├── vmv_v_x.h │ ├── vmv_x_s.h │ ├── vmvnfr_v.h │ ├── vmxnor_mm.h │ ├── vmxor_mm.h │ ├── vnclip_wi.h │ ├── vnclip_wv.h │ ├── vnclip_wx.h │ ├── vnclipu_wi.h │ ├── vnclipu_wv.h │ ├── vnclipu_wx.h │ ├── vnmsac_vv.h │ ├── vnmsac_vx.h │ ├── vnmsub_vv.h │ ├── vnmsub_vx.h │ ├── vnsra_wi.h │ ├── vnsra_wv.h │ ├── vnsra_wx.h │ ├── vnsrl_wi.h │ ├── vnsrl_wv.h │ ├── vnsrl_wx.h │ ├── vor_vi.h │ ├── vor_vv.h │ ├── vor_vx.h │ ├── vredand_vs.h │ ├── vredmax_vs.h │ ├── vredmaxu_vs.h │ ├── vredmin_vs.h │ ├── vredminu_vs.h │ ├── vredor_vs.h │ ├── vredsum_vs.h │ ├── vredxor_vs.h │ ├── vrem_vv.h │ ├── vrem_vx.h │ ├── vremu_vv.h │ ├── vremu_vx.h │ ├── vrgather_vi.h │ ├── vrgather_vv.h │ ├── vrgather_vx.h │ ├── vrgatherei16_vv.h │ ├── vrsub_vi.h │ ├── vrsub_vx.h │ ├── vs1r_v.h │ ├── vs2r_v.h │ ├── vs4r_v.h │ ├── vs8r_v.h │ ├── vsadd_vi.h │ ├── vsadd_vv.h │ ├── vsadd_vx.h │ ├── vsaddu_vi.h │ ├── vsaddu_vv.h │ ├── vsaddu_vx.h │ ├── vsbc_vvm.h │ ├── vsbc_vxm.h │ ├── vse16_v.h │ ├── vse32_v.h │ ├── vse64_v.h │ ├── vse8_v.h │ ├── vsetivli.h │ ├── vsetvl.h │ ├── vsetvli.h │ ├── vsext_vf2.h │ ├── vsext_vf4.h │ ├── vsext_vf8.h │ ├── vslide1down_vx.h │ ├── vslide1up_vx.h │ ├── vslidedown_vi.h │ ├── vslidedown_vx.h │ ├── vslideup_vi.h │ ├── vslideup_vx.h │ ├── vsll_vi.h │ ├── vsll_vv.h │ ├── vsll_vx.h │ ├── vsm_v.h │ ├── vsmul_vv.h │ ├── vsmul_vx.h │ ├── vsoxei16_v.h │ ├── vsoxei32_v.h │ ├── vsoxei64_v.h │ ├── vsoxei8_v.h │ ├── vsra_vi.h │ ├── vsra_vv.h │ ├── vsra_vx.h │ ├── vsrl_vi.h │ ├── vsrl_vv.h │ ├── vsrl_vx.h │ ├── vsse16_v.h │ ├── vsse32_v.h │ ├── vsse64_v.h │ ├── vsse8_v.h │ ├── vssra_vi.h │ ├── vssra_vv.h │ ├── vssra_vx.h │ ├── vssrl_vi.h │ ├── vssrl_vv.h │ ├── vssrl_vx.h │ ├── vssub_vv.h │ ├── vssub_vx.h │ ├── vssubu_vv.h │ ├── vssubu_vx.h │ ├── vsub_vv.h │ ├── vsub_vx.h │ ├── vsuxei16_v.h │ ├── vsuxei32_v.h │ ├── vsuxei64_v.h │ ├── vsuxei8_v.h │ ├── vwadd_vv.h │ ├── vwadd_vx.h │ ├── vwadd_wv.h │ ├── vwadd_wx.h │ ├── vwaddu_vv.h │ ├── vwaddu_vx.h │ ├── vwaddu_wv.h │ ├── vwaddu_wx.h │ ├── vwmacc_vv.h │ ├── vwmacc_vx.h │ ├── vwmaccsu_vv.h │ ├── vwmaccsu_vx.h │ ├── vwmaccu_vv.h │ ├── vwmaccu_vx.h │ ├── vwmaccus_vx.h │ ├── vwmul_vv.h │ ├── vwmul_vx.h │ ├── vwmulsu_vv.h │ ├── vwmulsu_vx.h │ ├── vwmulu_vv.h │ ├── vwmulu_vx.h │ ├── vwredsum_vs.h │ ├── vwredsumu_vs.h │ ├── vwsub_vv.h │ ├── vwsub_vx.h │ ├── vwsub_wv.h │ ├── vwsub_wx.h │ ├── vwsubu_vv.h │ ├── vwsubu_vx.h │ ├── vwsubu_wv.h │ ├── vwsubu_wx.h │ ├── vxor_vi.h │ ├── vxor_vv.h │ ├── vxor_vx.h │ ├── vzext_vf2.h │ ├── vzext_vf4.h │ ├── vzext_vf8.h │ ├── wext.h │ ├── wexti.h │ ├── wfi.h │ ├── xnor.h │ ├── xor.h │ ├── xori.h │ ├── xperm_b.h │ ├── xperm_h.h │ ├── xperm_n.h │ ├── xperm_w.h │ ├── zunpkd810.h │ ├── zunpkd820.h │ ├── zunpkd830.h │ ├── zunpkd831.h │ └── zunpkd832.h ├── interactive.cc ├── jtag_dtm.cc ├── jtag_dtm.h ├── log_file.h ├── memtracer.h ├── mmio_plugin.h ├── mmu.cc ├── mmu.h ├── opcodes.h ├── platform.h ├── processor.cc ├── processor.h ├── remote_bitbang.cc ├── remote_bitbang.h ├── riscv.ac ├── riscv.mk.in ├── rocc.cc ├── rocc.h ├── rom.cc ├── sim.cc ├── sim.h ├── simif.h ├── tracer.h ├── trap.cc └── trap.h ├── scripts ├── config.guess ├── config.sub ├── install.sh ├── mk-install-dirs.sh └── vcs-version.sh ├── sha3 ├── sha3.ac ├── sha3.cc ├── sha3.h └── sha3.mk.in ├── softfloat ├── f128_add.c ├── f128_classify.c ├── f128_div.c ├── f128_eq.c ├── f128_eq_signaling.c ├── f128_isSignalingNaN.c ├── f128_le.c ├── f128_le_quiet.c ├── f128_lt.c ├── f128_lt_quiet.c ├── f128_mul.c ├── f128_mulAdd.c ├── f128_rem.c ├── f128_roundToInt.c ├── f128_sqrt.c ├── f128_sub.c ├── f128_to_f16.c ├── f128_to_f32.c ├── f128_to_f64.c ├── f128_to_i32.c ├── f128_to_i32_r_minMag.c ├── f128_to_i64.c ├── f128_to_i64_r_minMag.c ├── f128_to_ui32.c ├── f128_to_ui32_r_minMag.c ├── f128_to_ui64.c ├── f128_to_ui64_r_minMag.c ├── f16_add.c ├── f16_classify.c ├── f16_div.c ├── f16_eq.c ├── f16_eq_signaling.c ├── f16_isSignalingNaN.c ├── f16_le.c ├── f16_le_quiet.c ├── f16_lt.c ├── f16_lt_quiet.c ├── f16_mul.c ├── f16_mulAdd.c ├── f16_rem.c ├── f16_roundToInt.c ├── f16_sqrt.c ├── f16_sub.c ├── f16_to_f128.c ├── f16_to_f32.c ├── f16_to_f64.c ├── f16_to_i16.c ├── f16_to_i32.c ├── f16_to_i32_r_minMag.c ├── f16_to_i64.c ├── f16_to_i64_r_minMag.c ├── f16_to_i8.c ├── f16_to_ui16.c ├── f16_to_ui32.c ├── f16_to_ui32_r_minMag.c ├── f16_to_ui64.c ├── f16_to_ui64_r_minMag.c ├── f16_to_ui8.c ├── f32_add.c ├── f32_classify.c ├── f32_div.c ├── f32_eq.c ├── f32_eq_signaling.c ├── f32_isSignalingNaN.c ├── f32_le.c ├── f32_le_quiet.c ├── f32_lt.c ├── f32_lt_quiet.c ├── f32_mul.c ├── f32_mulAdd.c ├── f32_rem.c ├── f32_roundToInt.c ├── f32_sqrt.c ├── f32_sub.c ├── f32_to_f128.c ├── f32_to_f16.c ├── f32_to_f64.c ├── f32_to_i16.c ├── f32_to_i32.c ├── f32_to_i32_r_minMag.c ├── f32_to_i64.c ├── f32_to_i64_r_minMag.c ├── f32_to_ui16.c ├── f32_to_ui32.c ├── f32_to_ui32_r_minMag.c ├── f32_to_ui64.c ├── f32_to_ui64_r_minMag.c ├── f64_add.c ├── f64_classify.c ├── f64_div.c ├── f64_eq.c ├── f64_eq_signaling.c ├── f64_isSignalingNaN.c ├── f64_le.c ├── f64_le_quiet.c ├── f64_lt.c ├── f64_lt_quiet.c ├── f64_mul.c ├── f64_mulAdd.c ├── f64_rem.c ├── f64_roundToInt.c ├── f64_sqrt.c ├── f64_sub.c ├── f64_to_f128.c ├── f64_to_f16.c ├── f64_to_f32.c ├── f64_to_i32.c ├── f64_to_i32_r_minMag.c ├── f64_to_i64.c ├── f64_to_i64_r_minMag.c ├── f64_to_ui32.c ├── f64_to_ui32_r_minMag.c ├── f64_to_ui64.c ├── f64_to_ui64_r_minMag.c ├── fall_maxmin.c ├── fall_reciprocal.c ├── i32_to_f128.c ├── i32_to_f16.c ├── i32_to_f32.c ├── i32_to_f64.c ├── i64_to_f128.c ├── i64_to_f16.c ├── i64_to_f32.c ├── i64_to_f64.c ├── internals.h ├── platform.h ├── primitiveTypes.h ├── primitives.h ├── s_add128.c ├── s_add256M.c ├── s_addCarryM.c ├── s_addComplCarryM.c ├── s_addM.c ├── s_addMagsF128.c ├── s_addMagsF16.c ├── s_addMagsF32.c ├── s_addMagsF64.c ├── s_approxRecip32_1.c ├── s_approxRecipSqrt32_1.c ├── s_approxRecipSqrt_1Ks.c ├── s_approxRecip_1Ks.c ├── s_commonNaNToF128UI.c ├── s_commonNaNToF16UI.c ├── s_commonNaNToF32UI.c ├── s_commonNaNToF64UI.c ├── s_compare128M.c ├── s_compare96M.c ├── s_countLeadingZeros16.c ├── s_countLeadingZeros32.c ├── s_countLeadingZeros64.c ├── s_countLeadingZeros8.c ├── s_eq128.c ├── s_f128UIToCommonNaN.c ├── s_f16UIToCommonNaN.c ├── s_f32UIToCommonNaN.c ├── s_f64UIToCommonNaN.c ├── s_le128.c ├── s_lt128.c ├── s_mul128By32.c ├── s_mul128MTo256M.c ├── s_mul128To256M.c ├── s_mul64ByShifted32To128.c ├── s_mul64To128.c ├── s_mul64To128M.c ├── s_mulAddF128.c ├── s_mulAddF16.c ├── s_mulAddF32.c ├── s_mulAddF64.c ├── s_negXM.c ├── s_normRoundPackToF128.c ├── s_normRoundPackToF16.c ├── s_normRoundPackToF32.c ├── s_normRoundPackToF64.c ├── s_normSubnormalF128Sig.c ├── s_normSubnormalF16Sig.c ├── s_normSubnormalF32Sig.c ├── s_normSubnormalF64Sig.c ├── s_propagateNaNF128UI.c ├── s_propagateNaNF16UI.c ├── s_propagateNaNF32UI.c ├── s_propagateNaNF64UI.c ├── s_remStepMBy32.c ├── s_roundMToI64.c ├── s_roundMToUI64.c ├── s_roundPackMToI64.c ├── s_roundPackMToUI64.c ├── s_roundPackToF128.c ├── s_roundPackToF16.c ├── s_roundPackToF32.c ├── s_roundPackToF64.c ├── s_roundPackToI32.c ├── s_roundPackToI64.c ├── s_roundPackToUI32.c ├── s_roundPackToUI64.c ├── s_roundToI32.c ├── s_roundToI64.c ├── s_roundToUI32.c ├── s_roundToUI64.c ├── s_shiftRightJam128.c ├── s_shiftRightJam128Extra.c ├── s_shiftRightJam256M.c ├── s_shiftRightJam32.c ├── s_shiftRightJam64.c ├── s_shiftRightJam64Extra.c ├── s_shortShiftLeft128.c ├── s_shortShiftLeft64To96M.c ├── s_shortShiftRight128.c ├── s_shortShiftRightExtendM.c ├── s_shortShiftRightJam128.c ├── s_shortShiftRightJam128Extra.c ├── s_shortShiftRightJam64.c ├── s_shortShiftRightJam64Extra.c ├── s_shortShiftRightM.c ├── s_sub128.c ├── s_sub1XM.c ├── s_sub256M.c ├── s_subM.c ├── s_subMagsF128.c ├── s_subMagsF16.c ├── s_subMagsF32.c ├── s_subMagsF64.c ├── softfloat.ac ├── softfloat.h ├── softfloat.mk.in ├── softfloat_raiseFlags.c ├── softfloat_state.c ├── softfloat_types.h ├── specialize.h ├── ui32_to_f128.c ├── ui32_to_f16.c ├── ui32_to_f32.c ├── ui32_to_f64.c ├── ui64_to_f128.c ├── ui64_to_f16.c ├── ui64_to_f32.c └── ui64_to_f64.c ├── spike_dasm ├── spike-dasm.cc ├── spike_dasm.ac ├── spike_dasm.mk.in └── spike_dasm_option_parser.cc ├── spike_main ├── spike-log-parser.cc ├── spike.cc ├── spike_main.ac ├── spike_main.mk.in ├── termios-xspike.cc └── xspike.cc └── tests ├── ebreak.py ├── ebreak.s └── testlib.py /.github/workflows/apt-packages.txt: -------------------------------------------------------------------------------- 1 | build-essential 2 | device-tree-compiler 3 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | *.gch 3 | autom4te.cache/ 4 | .*.swp 5 | *.swo 6 | *.o 7 | *.d 8 | .gdb_history 9 | -------------------------------------------------------------------------------- /VERSION: -------------------------------------------------------------------------------- 1 | #define SPIKE_VERSION "1.0.1-dev" 2 | -------------------------------------------------------------------------------- /customext/customext.ac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/customext/customext.ac -------------------------------------------------------------------------------- /debug_rom/.gitignore: -------------------------------------------------------------------------------- 1 | /debug_rom 2 | /debug_rom32 3 | /debug_rom64 4 | /debug_rom32.h 5 | /debug_rom64.h 6 | -------------------------------------------------------------------------------- /disasm/disasm.ac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/disasm/disasm.ac -------------------------------------------------------------------------------- /disasm/disasm.mk.in: -------------------------------------------------------------------------------- 1 | disasm_srcs = \ 2 | disasm.cc \ 3 | regnames.cc \ 4 | 5 | disasm_install_lib = yes 6 | -------------------------------------------------------------------------------- /fdt/fdt.ac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/fdt/fdt.ac -------------------------------------------------------------------------------- /fesvr/dummy.cc: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | // help out poor, C-centric autoconf 4 | extern "C" void libfesvr_is_present() {} 5 | -------------------------------------------------------------------------------- /hwacha/.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | -------------------------------------------------------------------------------- /hwacha/README: -------------------------------------------------------------------------------- 1 | This directory contains work in progress on Hwacha, a data-parallel 2 | accelerator. 3 | -------------------------------------------------------------------------------- /hwacha/insn_template_hwacha.h: -------------------------------------------------------------------------------- 1 | #include "hwacha.h" 2 | #include "decode_hwacha.h" 3 | //#include "encodings_hwacha.h" 4 | #include "rocc.h" 5 | #include 6 | -------------------------------------------------------------------------------- /hwacha/insns/venqcmd.h: -------------------------------------------------------------------------------- 1 | //Empty 2 | -------------------------------------------------------------------------------- /hwacha/insns/venqcnt.h: -------------------------------------------------------------------------------- 1 | //Empty 2 | -------------------------------------------------------------------------------- /hwacha/insns/venqimm1.h: -------------------------------------------------------------------------------- 1 | //Empty 2 | -------------------------------------------------------------------------------- /hwacha/insns/venqimm2.h: -------------------------------------------------------------------------------- 1 | //Empty 2 | -------------------------------------------------------------------------------- /hwacha/insns/vft.h: -------------------------------------------------------------------------------- 1 | vf.h -------------------------------------------------------------------------------- /hwacha/insns/vgetcfg.h: -------------------------------------------------------------------------------- 1 | //f(!ENABLED) 2 | //h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, VF_PC); 3 | 4 | WRITE_XRD((NXPR & 0x3f) | ((NPPR & 0x3f) << 6)); 5 | -------------------------------------------------------------------------------- /hwacha/insns/vgetvl.h: -------------------------------------------------------------------------------- 1 | //if(!ENABLED) 2 | //h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, VF_PC); 3 | 4 | WRITE_XRD(VL); 5 | -------------------------------------------------------------------------------- /hwacha/insns/vmca.h: -------------------------------------------------------------------------------- 1 | if(!ENABLED) 2 | h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, VF_PC); 3 | 4 | WRITE_SVARD(XS1); 5 | -------------------------------------------------------------------------------- /hwacha/insns/vmcs.h: -------------------------------------------------------------------------------- 1 | if(!ENABLED) 2 | h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, VF_PC); 3 | 4 | WRITE_SVSRD(XS1); 5 | -------------------------------------------------------------------------------- /hwacha/insns/vsetucfg.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.u_imm()); 2 | -------------------------------------------------------------------------------- /hwacha/insns/vuncfg.h: -------------------------------------------------------------------------------- 1 | WRITE_ENABLE(false); 2 | -------------------------------------------------------------------------------- /hwacha/insns/vxcptaux.h: -------------------------------------------------------------------------------- 1 | require_supervisor_hwacha; 2 | xd = h->get_aux(); 3 | -------------------------------------------------------------------------------- /hwacha/insns/vxcptcause.h: -------------------------------------------------------------------------------- 1 | require_supervisor_hwacha; 2 | h->clear_exception(); 3 | xd = h->get_cause(); 4 | -------------------------------------------------------------------------------- /hwacha/insns/vxcptkill.h: -------------------------------------------------------------------------------- 1 | require_supervisor_hwacha; 2 | h->get_ct_state()->reset(); 3 | for (uint32_t i=0; imax_uts; i++) 4 | h->get_ut_state(i)->reset(); 5 | -------------------------------------------------------------------------------- /hwacha/insns/vxcptrestore.h: -------------------------------------------------------------------------------- 1 | vxcpthold.h -------------------------------------------------------------------------------- /hwacha/insns/vxcptsave.h: -------------------------------------------------------------------------------- 1 | vxcptevac.h -------------------------------------------------------------------------------- /hwacha/insns_ut/vadd.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 + RS2)); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vaddi.h: -------------------------------------------------------------------------------- 1 | WRITE_SRD(sext_xlen(SRS1 + insn.v_imm())); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vaddiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_SRD(sext32(insn.v_imm() + SRS1)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vaddu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(zext_xlen(RS1 + RS2)); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vaddw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 + RS2)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoadd_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | reg_t v = MMU.load_uint64(RS1); 4 | MMU.store_uint64(RS1, RS2 + v); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoadd_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | reg_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, RS2 + v); 4 | WRITE_RD(v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoand_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | reg_t v = MMU.load_uint64(RS1); 4 | MMU.store_uint64(RS1, RS2 & v); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoand_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | reg_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, RS2 & v); 4 | WRITE_RD(v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamomax_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | sreg_t v = MMU.load_int64(RS1); 4 | MMU.store_uint64(RS1, std::max(sreg_t(RS2),v)); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamomax_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | int32_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, std::max(int32_t(RS2),v)); 4 | WRITE_RD(v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamomaxu_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | reg_t v = MMU.load_uint64(RS1); 4 | MMU.store_uint64(RS1, std::max(RS2,v)); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamomaxu_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | uint32_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, std::max(uint32_t(RS2),v)); 4 | WRITE_RD((int32_t)v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamomin_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | sreg_t v = MMU.load_int64(RS1); 4 | MMU.store_uint64(RS1, std::min(sreg_t(RS2),v)); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamomin_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | int32_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, std::min(int32_t(RS2),v)); 4 | WRITE_RD(v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamominu_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | reg_t v = MMU.load_uint64(RS1); 4 | MMU.store_uint64(RS1, std::min(RS2,v)); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamominu_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | uint32_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, std::min(uint32_t(RS2),v)); 4 | WRITE_RD((int32_t)v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoor_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | reg_t v = MMU.load_uint64(RS1); 4 | MMU.store_uint64(RS1, RS2 | v); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoor_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | reg_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, RS2 | v); 4 | WRITE_RD(v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoswap_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | reg_t v = MMU.load_uint64(RS1); 4 | MMU.store_uint64(RS1, RS2); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoswap_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | reg_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, RS2); 4 | WRITE_RD(v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoxor_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | if(VPRED){ 3 | reg_t v = MMU.load_uint64(RS1); 4 | MMU.store_uint64(RS1, RS2 ^ v); 5 | WRITE_RD(v); 6 | } 7 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vamoxor_w.h: -------------------------------------------------------------------------------- 1 | if(VPRED){ 2 | reg_t v = MMU.load_int32(RS1); 3 | MMU.store_uint32(RS1, RS2 ^ v); 4 | WRITE_RD(v); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vand.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 & RS2); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vandi.h: -------------------------------------------------------------------------------- 1 | WRITE_SRD(insn.v_imm() & SRS1); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vauipc.h: -------------------------------------------------------------------------------- 1 | WRITE_SRD(sext_xlen(insn.v_imm() + VF_PC)); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcjal.h: -------------------------------------------------------------------------------- 1 | if(COND){ 2 | reg_t temp = VF_PC; 3 | WRITE_SRD(npc); 4 | npc = ((temp + insn.vc_imm()) & ~7); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcjalr.h: -------------------------------------------------------------------------------- 1 | if(COND){ 2 | reg_t temp = SRS1; 3 | WRITE_SRD(npc); 4 | npc = ((temp + insn.vc_imm()) & ~7); 5 | } 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpeq.h: -------------------------------------------------------------------------------- 1 | WRITE_PRD(RS1 == RS2); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpfeq_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f64_eq(f64(FRS1), f64(FRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpfeq_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f32_eq(f32(HFRS1), f32(HFRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpfeq_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f32_eq(f32(FRS1), f32(FRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpfle_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f64_le(f64(FRS1), f64(FRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpfle_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f32_le(f32(HFRS1), f32(HFRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpfle_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f32_le(f32(FRS1), f32(FRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpflt_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f64_lt(f64(FRS1), f64(FRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpflt_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f32_lt(f32(HFRS1), f32(HFRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpflt_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_PRD(f32_lt(f32(FRS1), f32(FRS2))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmplt.h: -------------------------------------------------------------------------------- 1 | WRITE_PRD(sreg_t(RS1) < sreg_t(RS2)); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vcmpltu.h: -------------------------------------------------------------------------------- 1 | WRITE_PRD(RS1 < RS2); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/veidx.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(UTIDX); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfadd_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f64_add(f64(FRS1), f64(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfadd_d_h.h: -------------------------------------------------------------------------------- 1 | softfloat_roundingMode = VFRM; 2 | WRITE_FRD(f64_add(f32_to_f64(f32(HFRS1)), f32_to_f64(f32(HFRS2)))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfadd_d_s.h: -------------------------------------------------------------------------------- 1 | softfloat_roundingMode = VFRM; 2 | WRITE_FRD(f64_add(f32_to_f64(f32(FRS1)), f32_to_f64(f32(FRS2)))); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfadd_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(f32_add(f32(HFRS1), f32(HFRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfadd_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f32_add(f32(FRS1), f32(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfadd_s_h.h: -------------------------------------------------------------------------------- 1 | softfloat_roundingMode = VFRM; 2 | WRITE_SFRD(f32_add(f32(HFRS1), f32(HFRS2)).v); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfclass_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_RD(f64_classify(f64(FRS1))); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfclass_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_RD(f32_classify(f32(HFRS1))); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfclass_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_RD(f32_classify(f32(FRS1))); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_d_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f32_to_f64(f32(HFRS1))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_d_l.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_FRD(i64_to_f64(RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_d_lu.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_FRD(ui64_to_f64(RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_d_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f32_to_f64(f32(FRS1))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_d_w.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(i32_to_f64((int32_t)RS1)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_d_wu.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(ui32_to_f64((uint32_t)RS1)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_h_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(f64_to_f32(f64(FRS1))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_h_l.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_HFRD(i64_to_f32(RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_h_lu.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_HFRD(ui64_to_f32(RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_h_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_HFRD(f32(FRS1)); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_h_w.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(i32_to_f32((int32_t)RS1)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_h_wu.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(ui32_to_f32((uint32_t)RS1)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_l_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_RD(f64_to_i64(f64(FRS1), VFRM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_l_h.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_RD(f32_to_i64(f32(HFRS1), VFRM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_l_s.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_RD(f32_to_i64(f32(FRS1), VFRM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_lu_d.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_RD(f64_to_ui64(f64(FRS1), VFRM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_lu_h.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_RD(f32_to_ui64(f32(HFRS1), VFRM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_s_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(f64_to_f32(f64(FRS1)).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_s_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_SFRD(f32(HFRS1).v); 3 | set_fp_exceptions; 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_s_l.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_SFRD(i64_to_f32(RS1).v); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_s_lu.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_fp; 3 | softfloat_roundingMode = VFRM; 4 | WRITE_SFRD(ui64_to_f32(RS1).v); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_s_w.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(i32_to_f32((int32_t)RS1).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_s_wu.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(ui32_to_f32((uint32_t)RS1).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_w_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_RD(sext32(f64_to_i32(f64(FRS1), VFRM, true))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_w_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_RD(sext32(f32_to_i32(f32(HFRS1), VFRM, true))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_w_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_RD(sext32(f32_to_i32(f32(FRS1), VFRM, true))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_wu_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_RD(sext32(f64_to_ui32(f64(FRS1), VFRM, true))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_wu_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_RD(sext32(f32_to_ui32(f32(HFRS1), VFRM, true))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfcvt_wu_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_RD(sext32(f32_to_ui32(f32(FRS1), VFRM, true))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfdiv_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f64_div(f64(FRS1), f64(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfdiv_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(f32_div(f32(HFRS1), f32(HFRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfdiv_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(f32_div(f32(FRS1), f32(FRS2)).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfence.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/hwacha/insns_ut/vfence.h -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmadd_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmadd_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(f32_mulAdd(f32(HFRS1), f32(HFRS2), f32(HFRS3))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmadd_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmadd_s_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(f32_mulAdd(f32(HFRS1), f32(HFRS2), f32(HFRS3)).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmul_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmul_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(f32_mul(f32(HFRS1), f32(HFRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmul_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(f32_mul(f32(FRS1), f32(FRS2)).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfmul_s_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_SFRD(f32_mul(f32(HFRS1), f32(HFRS2)).v); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnj_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_FRD(fsgnj64(FRS1, FRS2, false, false)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnj_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_HFRD(fsgnj32(HFRS1, HFRS2, false, false)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnj_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_FRD(fsgnj32(FRS1, FRS2, false, false)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnjn_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_FRD(fsgnj64(FRS1, FRS2, true, false)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnjn_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_HFRD(fsgnj32(HFRS1, HFRS2, true, false)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnjn_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_FRD(fsgnj32(FRS1, FRS2, true, false)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnjx_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_FRD(fsgnj64(FRS1, FRS2, false, true)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnjx_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_HFRD(fsgnj32(HFRS1, HFRS2, false, true)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsgnjx_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | WRITE_FRD(fsgnj32(FRS1, FRS2, false, true)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsqrt_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f64_sqrt(f64(FRS1))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsqrt_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(f32_sqrt(f32(HFRS1))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsqrt_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f32_sqrt(f32(FRS1))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsub_d.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsub_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_HFRD(f32_sub(f32(HFRS1), f32(HFRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsub_s.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vfsub_s_h.h: -------------------------------------------------------------------------------- 1 | require_fp; 2 | softfloat_roundingMode = VFRM; 3 | WRITE_FRD(f32_sub(f32(HFRS1), f32(HFRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vlasegb.h: -------------------------------------------------------------------------------- 1 | for (uint32_t j=0; j> 32)); 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vmulhsu.h: -------------------------------------------------------------------------------- 1 | if (xlen == 64) 2 | WRITE_RD(mulhsu(RS1, RS2)); 3 | else 4 | WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32)); 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vmulw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 * RS2)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vor.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 | RS2); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vori.h: -------------------------------------------------------------------------------- 1 | WRITE_SRD(insn.v_imm() | SRS1); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vpl.h: -------------------------------------------------------------------------------- 1 | reg_t addr = ARS1+(UTIDX/8); 2 | uint8_t temp = MMU.load_uint8(addr); 3 | WRITE_PPR_NO_PRED(UTIDX, INSN_VRD, temp & (0x1 << (UTIDX%8))); 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vpop.h: -------------------------------------------------------------------------------- 1 | reg_t index = (PRS1) | (PRS2 << 1) | (PRS3 << 2); 2 | WRITE_PPR_NO_PRED(UTIDX, INSN_VRD, !!(POP_TABLE & (0x1 << index))); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsasegb.h: -------------------------------------------------------------------------------- 1 | for (uint32_t j=0; j> (RS2 & (xlen-1)))); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsraiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_SRD(sext32(int32_t(SRS1) >> VSHAMT)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsraw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(int32_t(RS1) >> (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsrl.h: -------------------------------------------------------------------------------- 1 | if(xlen == 64) 2 | WRITE_RD(RS1 >> (RS2 & 0x3F)); 3 | else 4 | WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); 5 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsrliw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_SRD(sext32((uint32_t)SRS1 >> VSHAMT)); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsrlw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegb.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_STORE(XPR, store_uint8, 1); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegd.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_STORE(XPR, store_uint64, 8); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegh.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_STORE(XPR, store_uint16, 2); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegstb.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_ST_STORE(XPR, store_uint8, ARS2, 1); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegstd.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_ST_STORE(XPR, store_uint64, ARS2, 8); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegsth.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_ST_STORE(XPR, store_uint16, ARS2, 2); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegstw.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_ST_STORE(XPR, store_uint32, ARS2, 4); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegw.h: -------------------------------------------------------------------------------- 1 | VEC_SEG_STORE(XPR, store_uint32, 4); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vssegxb.h: -------------------------------------------------------------------------------- 1 | if(VPRED) { 2 | for (uint32_t j=0; jget_ut_state(j)->run = false; 3 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsub.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 - RS2)); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vsubw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 - RS2)); 3 | 4 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vxor.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 ^ RS2); 2 | -------------------------------------------------------------------------------- /hwacha/insns_ut/vxori.h: -------------------------------------------------------------------------------- 1 | WRITE_SRD(insn.v_imm() ^ SRS1); 2 | -------------------------------------------------------------------------------- /riscv/insns/add.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 + RS2)); 2 | -------------------------------------------------------------------------------- /riscv/insns/add16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = ps1 + ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/add32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_LOOP(32, { 3 | pd = ps1 + ps2; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/add64.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE({ 2 | rd = rs1 + rs2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/add8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = ps1 + ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen(zext32(RS1) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/addi.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/addiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(insn.i_imm() + RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/addw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoadd_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs + RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoadd_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs + RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoand_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs & RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoand_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs & RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomax_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amomax_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomaxu_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amomaxu_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomin_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amomin_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amominu_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amominu_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoor_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs | RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoor_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs | RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoswap_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoswap_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoxor_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs ^ RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoxor_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs ^ RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/and.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 & RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/andi.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.i_imm() & RS1); 2 | -------------------------------------------------------------------------------- /riscv/insns/andn.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | WRITE_RD(RS1 & ~RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/auipc.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(insn.u_imm() + pc)); 2 | -------------------------------------------------------------------------------- /riscv/insns/bclr.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 & ~(1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/bclri.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = SHAMT & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 & ~(1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/beq.h: -------------------------------------------------------------------------------- 1 | if(RS1 == RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bext.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(1 & (RS1 >> shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/bexti.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = SHAMT & (xlen-1); 3 | WRITE_RD(sext_xlen(1 & (RS1 >> shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/bge.h: -------------------------------------------------------------------------------- 1 | if(sreg_t(RS1) >= sreg_t(RS2)) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bgeu.h: -------------------------------------------------------------------------------- 1 | if(RS1 >= RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/binv.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 ^ (1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/binvi.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = SHAMT & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 ^ (1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/blt.h: -------------------------------------------------------------------------------- 1 | if(sreg_t(RS1) < sreg_t(RS2)) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bltu.h: -------------------------------------------------------------------------------- 1 | if(RS1 < RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bne.h: -------------------------------------------------------------------------------- 1 | if(RS1 != RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bpick.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | reg_t rc = RS3; 3 | reg_t rs1 = RS1; 4 | reg_t rs2 = RS2; 5 | 6 | WRITE_RD(sext_xlen((rs1 & rc) | (rs2 & ~rc))); -------------------------------------------------------------------------------- /riscv/insns/bset.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 | (1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/bseti.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = SHAMT & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 | (1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_add.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_rs2() != 0); 3 | WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_addi.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_addi4spn.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_addi4spn_imm() != 0); 3 | WRITE_RVC_RS2S(sext_xlen(RVC_SP + insn.rvc_addi4spn_imm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_addw.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require_rv64; 3 | WRITE_RVC_RS1S(sext32(RVC_RS1S + RVC_RS2S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_and.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RVC_RS1S(RVC_RS1S & RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_andi.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RVC_RS1S(RVC_RS1S & insn.rvc_imm()); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_beqz.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | if (RVC_RS1S == 0) 3 | set_pc(pc + insn.rvc_b_imm()); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_bnez.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | if (RVC_RS1S != 0) 3 | set_pc(pc + insn.rvc_b_imm()); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_ebreak.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | throw trap_breakpoint(pc); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_fld.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require_extension('D'); 3 | require_fp; 4 | WRITE_RVC_FRS2S(f64(MMU.load_uint64(RVC_RS1S + insn.rvc_ld_imm()))); 5 | -------------------------------------------------------------------------------- /riscv/insns/c_fldsp.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require_extension('D'); 3 | require_fp; 4 | WRITE_FRD(f64(MMU.load_uint64(RVC_SP + insn.rvc_ldsp_imm()))); 5 | -------------------------------------------------------------------------------- /riscv/insns/c_fsd.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require_extension('D'); 3 | require_fp; 4 | MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v[0]); 5 | -------------------------------------------------------------------------------- /riscv/insns/c_fsdsp.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require_extension('D'); 3 | require_fp; 4 | MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v[0]); 5 | -------------------------------------------------------------------------------- /riscv/insns/c_j.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | set_pc(pc + insn.rvc_j_imm()); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_jalr.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_rs1() != 0); 3 | reg_t tmp = npc; 4 | set_pc(RVC_RS1 & ~reg_t(1)); 5 | WRITE_REG(X_RA, tmp); 6 | -------------------------------------------------------------------------------- /riscv/insns/c_jr.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_rs1() != 0); 3 | set_pc(RVC_RS1 & ~reg_t(1)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_li.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RD(insn.rvc_imm()); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_lw.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RVC_RS2S(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_lwsp.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_rd() != 0); 3 | WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_mv.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_rs2() != 0); 3 | WRITE_RD(RVC_RS2); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_or.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RVC_RS1S(RVC_RS1S | RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_slli.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_zimm() < xlen); 3 | WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_srai.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_zimm() < xlen); 3 | WRITE_RVC_RS1S(sext_xlen(sext_xlen(RVC_RS1S) >> insn.rvc_zimm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_srli.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require(insn.rvc_zimm() < xlen); 3 | WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_sub.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RVC_RS1S(sext_xlen(RVC_RS1S - RVC_RS2S)); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_subw.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | require_rv64; 3 | WRITE_RVC_RS1S(sext32(RVC_RS1S - RVC_RS2S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_sw.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_swsp.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_xor.h: -------------------------------------------------------------------------------- 1 | require_extension('C'); 2 | WRITE_RVC_RS1S(RVC_RS1S ^ RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/cmix.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_XBITMANIP); 2 | WRITE_RD((RS1 & RS2) | (RS3 & ~RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/cmov.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_XBITMANIP); 2 | WRITE_RD(RS2 ? RS1 : RS3); 3 | -------------------------------------------------------------------------------- /riscv/insns/cmpeq16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = (ps1 == ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/cmpeq8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = (ps1 == ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/cpop.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | reg_t x = 0; 3 | for (int i = 0; i < xlen; i++) 4 | if (1 & (RS1 >> i)) x++; 5 | WRITE_RD(sext_xlen(x)); 6 | -------------------------------------------------------------------------------- /riscv/insns/cras16.h: -------------------------------------------------------------------------------- 1 | P_CROSS_LOOP(16, { 2 | pd = ps1 + ps2; 3 | }, { 4 | pd = ps1 - ps2; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/cras32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_CROSS_LOOP(32, { 3 | pd = ps1 + ps2; 4 | }, { 5 | pd = ps1 - ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/crsa16.h: -------------------------------------------------------------------------------- 1 | P_CROSS_LOOP(16, { 2 | pd = ps1 - ps2; 3 | }, { 4 | pd = ps1 + ps2; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/crsa32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_CROSS_LOOP(32, { 3 | pd = (int64_t)ps1 - ps2; 4 | }, { 5 | pd = (int64_t)ps1 + ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/ebreak.h: -------------------------------------------------------------------------------- 1 | throw trap_breakpoint(pc); 2 | -------------------------------------------------------------------------------- /riscv/insns/fadd_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_add(f64(FRS1), f64(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fadd_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_add(f32(FRS1), f32(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fclass_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_RD(f64_classify(f64(FRS1))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fclass_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_RD(f16_classify(f16(FRS1))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fclass_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_classify(f128(FRS1))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fclass_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_RD(f32_classify(f32(FRS1))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_to_f64(f128(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_s.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_to_f64(f32(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_w.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(i32_to_f64((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_wu.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(ui32_to_f64((uint32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_s.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_to_f16(f32(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(i32_to_f16((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_d.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_to_f128(f64(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_s.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_to_f128(f32(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_w.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(i32_to_f128((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_wu.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(ui32_to_f128((uint32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_to_f32(f64(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f16_to_f32(f16(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_to_f32(f128(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_w.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(i32_to_f32((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_wu.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(ui32_to_f32((uint32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fdiv_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_div(f64(FRS1), f64(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fdiv_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_div(f32(FRS1), f32(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fence.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/riscv/insns/fence.h -------------------------------------------------------------------------------- /riscv/insns/fence_i.h: -------------------------------------------------------------------------------- 1 | MMU.flush_icache(); 2 | -------------------------------------------------------------------------------- /riscv/insns/feq_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_RD(f64_eq(f64(FRS1), f64(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/feq_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_RD(f16_eq(f16(FRS1), f16(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/feq_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_eq(f128(FRS1), f128(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/feq_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_RD(f32_eq(f32(FRS1), f32(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fld.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_FRD(f64(MMU.load_uint64(RS1 + insn.i_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fle_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_RD(f64_le(f64(FRS1), f64(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fle_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_RD(f16_le(f16(FRS1), f16(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fle_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_le(f128(FRS1), f128(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fle_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_RD(f32_le(f32(FRS1), f32(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flh.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_FRD(f16(MMU.load_uint16(RS1 + insn.i_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/flq.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_FRD(MMU.load_float128(RS1 + insn.i_imm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/flt_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_RD(f64_lt(f64(FRS1), f64(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flt_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_RD(f16_lt(f16(FRS1), f16(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flt_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_lt(f128(FRS1), f128(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flt_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_RD(f32_lt(f32(FRS1), f32(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flw.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_FRD(f32(MMU.load_uint32(RS1 + insn.i_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fmax_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_FRD(f16_max(f16(FRS1), f16(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fmin_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_FRD(f16_min(f16(FRS1), f16(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fmul_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmul_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmv_d_x.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_rv64; 3 | require_fp; 4 | WRITE_FRD(f64(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/fmv_h_x.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_FRD(f16(RS1)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fmv_w_x.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_FRD(f32(RS1)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fmv_x_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_rv64; 3 | require_fp; 4 | WRITE_RD(FRS1.v[0]); 5 | -------------------------------------------------------------------------------- /riscv/insns/fmv_x_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_RD(sext32((int16_t)(FRS1.v[0]))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fmv_x_w.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_RD(sext32(FRS1.v[0])); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsd.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_FRD(fsgnj64(FRS1, FRS2, false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_FRD(fsgnj16(FRS1, FRS2, false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_FRD(fsgnj128(FRS1, FRS2, false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_FRD(fsgnj32(FRS1, FRS2, false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_FRD(fsgnj64(FRS1, FRS2, true, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_FRD(fsgnj16(FRS1, FRS2, true, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_FRD(fsgnj128(FRS1, FRS2, true, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_FRD(fsgnj32(FRS1, FRS2, true, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_FRD(fsgnj64(FRS1, FRS2, false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | WRITE_FRD(fsgnj16(FRS1, FRS2, false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_FRD(fsgnj128(FRS1, FRS2, false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_FRD(fsgnj32(FRS1, FRS2, false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsh.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | MMU.store_uint16(RS1 + insn.s_imm(), FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsq.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | MMU.store_float128(RS1 + insn.s_imm(), FRS2); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_sqrt(f64(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f16_sqrt(f16(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_sqrt(f128(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_sqrt(f32(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsub_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsub_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsw.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/hfence_vvma.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(PRV_S); 4 | MMU.flush_tlb(); 5 | -------------------------------------------------------------------------------- /riscv/insns/hinval_gvma.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_SVINVAL); 2 | #include "hfence_gvma.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/hinval_vvma.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_SVINVAL); 2 | #include "hfence_vvma.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/jal.h: -------------------------------------------------------------------------------- 1 | reg_t tmp = npc; 2 | set_pc(JUMP_TARGET); 3 | WRITE_RD(tmp); 4 | -------------------------------------------------------------------------------- /riscv/insns/jalr.h: -------------------------------------------------------------------------------- 1 | reg_t tmp = npc; 2 | set_pc((RS1 + insn.i_imm()) & ~reg_t(1)); 3 | WRITE_RD(tmp); 4 | -------------------------------------------------------------------------------- /riscv/insns/kadd16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | bool sat = false; 3 | pd = (sat_add(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/kadd32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_LOOP(32, { 3 | bool sat = false; 4 | pd = (sat_add(ps1, ps2, sat)); 5 | P_SET_OV(sat); 6 | }) -------------------------------------------------------------------------------- /riscv/insns/kadd64.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE({ 2 | bool sat = false; 3 | rd = (sat_add(rs1, rs2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/kadd8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | bool sat = false; 3 | pd = (sat_add(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/kaddh.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_SW(RS1, 0) + (sreg_t)P_SW(RS2, 0); 3 | P_SAT(res, 16); 4 | WRITE_RD(sext_xlen((int16_t)res)); -------------------------------------------------------------------------------- /riscv/insns/kaddw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_SW(RS1, 0) + (sreg_t)P_SW(RS2, 0); 3 | P_SAT(res, 32); 4 | WRITE_RD(sext32(res)); -------------------------------------------------------------------------------- /riscv/insns/kmada.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 16, true, true, { 2 | pd_res += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/kmadrs.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 16, true, true, { 2 | if (j & 1) 3 | pd_res -= ps1 * ps2; 4 | else 5 | pd_res += ps1 * ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/kmads.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 16, true, true, { 2 | if (j & 1) 3 | pd_res += ps1 * ps2; 4 | else 5 | pd_res -= ps1 * ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/kmaxda.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_CROSS_LOOP(32, 16, true, true, { 2 | pd_res += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/kmaxds.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_CROSS_LOOP(32, 16, true, true, { 2 | if (j & 1) 3 | pd_res += ps1 * ps2; 4 | else 5 | pd_res -= ps1 * ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/kmda.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 16, false, true, { 2 | pd_res += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/kmsda.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 16, true, true, { 2 | pd_res -= ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/kmsxda.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_CROSS_LOOP(32, 16, true, true, { 2 | pd_res -= ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/kmxda.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_CROSS_LOOP(32, 16, false, true, { 2 | pd_res += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/ksll16.h: -------------------------------------------------------------------------------- 1 | P_X_LOOP(16, 4, { 2 | auto res = (sreg_t)ps1 << sa; 3 | P_SAT(res, 16); 4 | pd = res; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ksll32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_X_LOOP(32, 5, { 3 | auto res = (sreg_t)ps1 << sa; 4 | P_SAT(res, 32); 5 | pd = res; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/ksll8.h: -------------------------------------------------------------------------------- 1 | P_X_LOOP(8, 3, { 2 | auto res = (sreg_t)ps1 << sa; 3 | P_SAT(res, 8); 4 | pd = res; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/kslli16.h: -------------------------------------------------------------------------------- 1 | P_I_LOOP(16, 4, { 2 | auto res = (sreg_t)ps1 << imm4u; 3 | P_SAT(res, 16); 4 | pd = res; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/kslli32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_I_LOOP(32, 5, { 3 | auto res = (sreg_t)ps1 << imm5u; 4 | P_SAT(res, 32); 5 | pd = res; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/kslli8.h: -------------------------------------------------------------------------------- 1 | P_I_LOOP(8, 3, { 2 | auto res = (sreg_t)ps1 << imm3u; 3 | P_SAT(res, 8); 4 | pd = res; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ksub16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | bool sat = false; 3 | pd = (sat_sub(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ksub32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_LOOP(32, { 3 | bool sat = false; 4 | pd = (sat_sub(ps1, ps2, sat)); 5 | P_SET_OV(sat); 6 | }) -------------------------------------------------------------------------------- /riscv/insns/ksub64.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE({ 2 | bool sat = false; 3 | rd = (sat_sub(rs1, rs2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ksub8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | bool sat = false; 3 | pd = (sat_sub(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ksubh.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_SW(RS1, 0) - (sreg_t)P_SW(RS2, 0); 3 | P_SAT(res, 16); 4 | WRITE_RD(sext_xlen((int16_t)res)); -------------------------------------------------------------------------------- /riscv/insns/ksubw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_SW(RS1, 0) - (sreg_t)P_SW(RS2, 0); 3 | P_SAT(res, 32); 4 | WRITE_RD(sext32(res)); -------------------------------------------------------------------------------- /riscv/insns/lb.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load_int8(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lbu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load_uint8(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/ld.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(MMU.load_int64(RS1 + insn.i_imm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/lh.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load_int16(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lhu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lr_d.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | require_rv64; 3 | auto res = MMU.load_int64(RS1, true); 4 | MMU.acquire_load_reservation(RS1); 5 | WRITE_RD(res); 6 | -------------------------------------------------------------------------------- /riscv/insns/lr_w.h: -------------------------------------------------------------------------------- 1 | require_extension('A'); 2 | auto res = MMU.load_int32(RS1, true); 3 | MMU.acquire_load_reservation(RS1); 4 | WRITE_RD(res); 5 | -------------------------------------------------------------------------------- /riscv/insns/lui.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.u_imm()); 2 | -------------------------------------------------------------------------------- /riscv/insns/lw.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load_int32(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lwu.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/max.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(sreg_t(RS1) > sreg_t(RS2) ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/maxu.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(RS1 > RS2 ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/maxw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | int32_t rs1w = P_W(RS1, 0); 3 | int32_t rs2w = P_W(RS2, 0); 4 | WRITE_RD(sext_xlen(rs1w >= rs2w ? rs1w : rs2w)); -------------------------------------------------------------------------------- /riscv/insns/min.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(sreg_t(RS1) < sreg_t(RS2) ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/minu.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(RS1 < RS2 ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/minw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | int32_t rs1w = P_W(RS1, 0); 3 | int32_t rs2w = P_W(RS2, 0); 4 | WRITE_RD(sext_xlen(rs1w >= rs2w ? rs2w : rs1w)); -------------------------------------------------------------------------------- /riscv/insns/mul.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | WRITE_RD(sext_xlen(RS1 * RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/mulh.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | if (xlen == 64) 3 | WRITE_RD(mulh(RS1, RS2)); 4 | else 5 | WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32)); 6 | -------------------------------------------------------------------------------- /riscv/insns/mulr64.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | reg_t rd = (reg_t)P_W(RS1, 0) * P_W(RS2, 0); 3 | P_64_PROFILE_END(); -------------------------------------------------------------------------------- /riscv/insns/mulsr64.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t rd = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); 3 | P_64_PROFILE_END(); -------------------------------------------------------------------------------- /riscv/insns/mulw.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | require_rv64; 3 | WRITE_RD(sext32(RS1 * RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/or.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 | RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/ori.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.i_imm() | RS1); 2 | -------------------------------------------------------------------------------- /riscv/insns/orn.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | WRITE_RD(RS1 | ~RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/pbsad.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_ULOOP(64, 8, false, false, { 2 | pd_res += (ps1 > ps2 ? ps1 - ps2 : ps2 - ps1); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/pbsada.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_ULOOP(64, 8, true, false, { 2 | pd_res += (ps1 > ps2 ? ps1 - ps2 : ps2 - ps1); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/pkbb16.h: -------------------------------------------------------------------------------- 1 | P_PK(16, 0, 0); -------------------------------------------------------------------------------- /riscv/insns/pkbb32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_PK(32, 0, 0); -------------------------------------------------------------------------------- /riscv/insns/pkbt16.h: -------------------------------------------------------------------------------- 1 | P_PK(16, 0, 1); -------------------------------------------------------------------------------- /riscv/insns/pkbt32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_PK(32, 0, 1); -------------------------------------------------------------------------------- /riscv/insns/pktb16.h: -------------------------------------------------------------------------------- 1 | P_PK(16, 1, 0); -------------------------------------------------------------------------------- /riscv/insns/pktb32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_PK(32, 1, 0); -------------------------------------------------------------------------------- /riscv/insns/pktt16.h: -------------------------------------------------------------------------------- 1 | P_PK(16, 1, 1); -------------------------------------------------------------------------------- /riscv/insns/pktt32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_PK(32, 1, 1); -------------------------------------------------------------------------------- /riscv/insns/radd16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = (ps1 + ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/radd32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_LOOP(32, { 3 | pd = ((int64_t)ps1 + ps2) >> 1; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/radd8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = (ps1 + ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/raddw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_SW(RS1, 0) + (sreg_t)P_SW(RS2, 0); 3 | res >>= 1; 4 | WRITE_RD(sext_xlen(res)); -------------------------------------------------------------------------------- /riscv/insns/rcras16.h: -------------------------------------------------------------------------------- 1 | P_CROSS_LOOP(16, { 2 | pd = (ps1 + ps2) >> 1; 3 | }, { 4 | pd = (ps1 - ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/rcras32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_CROSS_LOOP(32, { 3 | pd = ((int64_t)ps1 + ps2) >> 1; 4 | }, { 5 | pd = ((int64_t)ps1 - ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/rcrsa16.h: -------------------------------------------------------------------------------- 1 | P_CROSS_LOOP(16, { 2 | pd = (ps1 - ps2) >> 1; 3 | }, { 4 | pd = (ps1 + ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/rcrsa32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_CROSS_LOOP(32, { 3 | pd = ((uint64_t)ps1 - ps2) >> 1; 4 | }, { 5 | pd = ((uint64_t)ps1 + ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/rstas16.h: -------------------------------------------------------------------------------- 1 | P_STRAIGHT_LOOP(16, { 2 | pd = (ps1 + ps2) >> 1; 3 | }, { 4 | pd = (ps1 - ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/rstas32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_STRAIGHT_LOOP(32, { 3 | pd = ((int64_t)ps1 + ps2) >> 1; 4 | }, { 5 | pd = ((int64_t)ps1 - ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/rstsa16.h: -------------------------------------------------------------------------------- 1 | P_STRAIGHT_LOOP(16, { 2 | pd = (ps1 - ps2) >> 1; 3 | }, { 4 | pd = (ps1 + ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/rstsa32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_STRAIGHT_LOOP(32, { 3 | pd = ((int64_t)ps1 - ps2) >> 1; 4 | }, { 5 | pd = ((int64_t)ps1 + ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/rsub16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = (ps1 - ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/rsub32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_LOOP(32, { 3 | pd = ((int64_t)ps1 - ps2) >> 1; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/rsub8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = (ps1 - ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/rsubw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_SW(RS1, 0) - (sreg_t)P_SW(RS2, 0); 3 | res >>= 1; 4 | WRITE_RD(sext_xlen(res)); -------------------------------------------------------------------------------- /riscv/insns/sb.h: -------------------------------------------------------------------------------- 1 | MMU.store_uint8(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/scmple16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = (ps1 <= ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/scmple8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = (ps1 <= ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/scmplt16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = (ps1 < ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/scmplt8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = (ps1 < ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/sd.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | MMU.store_uint64(RS1 + insn.s_imm(), RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/sext_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD((sreg_t)(int8_t)(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sext_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD((sreg_t)(int16_t)(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sfence_inval_ir.h: -------------------------------------------------------------------------------- 1 | require_extension('S'); 2 | require_extension(EXT_SVINVAL); 3 | require_impl(IMPL_MMU); 4 | -------------------------------------------------------------------------------- /riscv/insns/sfence_w_inval.h: -------------------------------------------------------------------------------- 1 | require_extension('S'); 2 | require_extension(EXT_SVINVAL); 3 | require_impl(IMPL_MMU); 4 | -------------------------------------------------------------------------------- /riscv/insns/sh.h: -------------------------------------------------------------------------------- 1 | MMU.store_uint16(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/sh1add.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBA); 2 | WRITE_RD(sext_xlen((RS1 << 1) + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sh1add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen((zext32(RS1) << 1) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/sh2add.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBA); 2 | WRITE_RD(sext_xlen((RS1 << 2) + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sh2add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen((zext32(RS1) << 2) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/sh3add.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBA); 2 | WRITE_RD(sext_xlen((RS1 << 3) + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sh3add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen((zext32(RS1) << 3) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/sinval_vma.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_SVINVAL); 2 | #include "sfence_vma.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/sll.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 << (RS2 & (xlen-1)))); 2 | -------------------------------------------------------------------------------- /riscv/insns/sll16.h: -------------------------------------------------------------------------------- 1 | P_X_ULOOP(16, 4, { 2 | pd = ps1 << sa; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/sll32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_X_ULOOP(32, 5, { 3 | pd = ps1 << sa; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/sll8.h: -------------------------------------------------------------------------------- 1 | P_X_ULOOP(8, 3, { 2 | pd = ps1 << sa; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/slli.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | WRITE_RD(sext_xlen(RS1 << SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/slli16.h: -------------------------------------------------------------------------------- 1 | P_I_ULOOP(16, 4, { 2 | pd = ps1 << imm4u; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/slli32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_I_ULOOP(32, 5, { 3 | pd = ps1 << imm5u; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/slli8.h: -------------------------------------------------------------------------------- 1 | P_I_ULOOP(8, 3, { 2 | pd = ps1 << imm3u; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/slli_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen(zext32(RS1) << SHAMT)); 4 | -------------------------------------------------------------------------------- /riscv/insns/slliw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 << SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sllw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 << (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /riscv/insns/slo.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_XBITMANIP); 2 | WRITE_RD(sext_xlen(~((~RS1) << (RS2 & (xlen-1))))); 3 | -------------------------------------------------------------------------------- /riscv/insns/sloi.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | require_extension(EXT_XBITMANIP); 3 | WRITE_RD(sext_xlen(~((~RS1) << SHAMT))); 4 | -------------------------------------------------------------------------------- /riscv/insns/sloiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_XBITMANIP); 3 | WRITE_RD(sext32(~((~RS1) << SHAMT))); 4 | -------------------------------------------------------------------------------- /riscv/insns/slow.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_XBITMANIP); 3 | WRITE_RD(sext32(~((~RS1) << (RS2 & 0x1F)))); 4 | -------------------------------------------------------------------------------- /riscv/insns/slt.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sreg_t(RS1) < sreg_t(RS2)); 2 | -------------------------------------------------------------------------------- /riscv/insns/slti.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sreg_t(RS1) < sreg_t(insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/sltiu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 < reg_t(insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/sltu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 < RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/smalbb.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(32, { 2 | rd += (sreg_t)P_SH(ps1, 0) * (sreg_t)P_SH(ps2, 0); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smalbt.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(32, { 2 | rd += (sreg_t)P_SH(ps1, 0) * (sreg_t)P_SH(ps2, 1); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smalda.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(16, { 2 | rd += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smaldrs.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(16, { 2 | if (i & 1) { 3 | rd -= ps1 * ps2; 4 | } else { 5 | rd += ps1 * ps2; 6 | } 7 | }) -------------------------------------------------------------------------------- /riscv/insns/smalds.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(16, { 2 | if (i & 1) { 3 | rd += ps1 * ps2; 4 | } else { 5 | rd -= ps1 * ps2; 6 | } 7 | }) -------------------------------------------------------------------------------- /riscv/insns/smaltt.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(32, { 2 | rd += P_SH(ps1, 1) * P_SH(ps2, 1); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smaqa.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 8, true, false, { 2 | pd_res += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smaqa_su.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_SULOOP(32, 8, true, false, { 2 | pd_res += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smar64.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(32, { 2 | rd += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smax16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = (ps1 > ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smax32.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | pd = (ps1 > ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smax8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = (ps1 > ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smbb16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | pd = P_SH(ps1, 0) * P_SH(ps2, 0); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smbt16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | pd = P_SH(ps1, 0) * P_SH(ps2, 1); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smbt32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension('P'); 3 | WRITE_RD((sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1)); -------------------------------------------------------------------------------- /riscv/insns/smdrs.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 16, false, false, { 2 | if (j & 1) 3 | pd_res -= ps1 * ps2; 4 | else 5 | pd_res += ps1 * ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/smds.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_LOOP(32, 16, false, false, { 2 | if (j & 1) 3 | pd_res += ps1 * ps2; 4 | else 5 | pd_res -= ps1 * ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/smin16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = (ps1 < ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smin32.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | pd = (ps1 < ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smin8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = (ps1 < ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smmul.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | int64_t mres = (int64_t) ps1 * (int64_t) ps2; 3 | pd = mres >> 32; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/smmul_u.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | int64_t mres = (int64_t) ps1 * (int64_t) ps2; 3 | pd = ((mres >> 31) + 1) >> 1; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/smmwb.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 0); 3 | pd = mres >> 16; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/smmwb_u.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 0); 3 | pd = ((mres >> 15) + 1) >> 1; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/smmwt.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 1); 3 | pd = mres >> 16; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/smmwt_u.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 1); 3 | pd = ((mres >> 15) + 1) >> 1; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/smslda.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(16, { 2 | rd -= ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smsr64.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE_REDUCTION(32, { 2 | rd -= ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smtt16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(32, { 2 | pd = P_SH(ps1, 1) * P_SH(ps2, 1); 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smtt32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension('P'); 3 | WRITE_RD((sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1)); -------------------------------------------------------------------------------- /riscv/insns/smul16.h: -------------------------------------------------------------------------------- 1 | P_MUL_LOOP(16, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smul8.h: -------------------------------------------------------------------------------- 1 | P_MUL_LOOP(8, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smulx16.h: -------------------------------------------------------------------------------- 1 | P_MUL_CROSS_LOOP(16, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smulx8.h: -------------------------------------------------------------------------------- 1 | P_MUL_CROSS_LOOP(8, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/smxds.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_CROSS_LOOP(32, 16, false, false, { 2 | if (j & 1) 3 | pd_res += ps1 * ps2; 4 | else 5 | pd_res -= ps1 * ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/sra.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(sext_xlen(RS1) >> (RS2 & (xlen-1)))); 2 | -------------------------------------------------------------------------------- /riscv/insns/sra16.h: -------------------------------------------------------------------------------- 1 | P_X_LOOP(16, 4, { 2 | pd = ps1 >> sa; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/sra16_u.h: -------------------------------------------------------------------------------- 1 | P_X_LOOP(16, 4, { 2 | if(sa > 0) 3 | pd = ((ps1 >> (sa - 1)) + 1) >> 1; 4 | else 5 | pd = ps1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/sra32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_X_LOOP(32, 5, { 3 | pd = ps1 >> sa; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/sra32_u.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_X_LOOP(32, 5, { 3 | if(sa > 0) 4 | pd = (((uint64_t)(ps1 >> (sa - 1))) + 1) >> 1; 5 | else 6 | pd = ps1; 7 | }) -------------------------------------------------------------------------------- /riscv/insns/sra8.h: -------------------------------------------------------------------------------- 1 | P_X_LOOP(8, 3, { 2 | pd = ps1 >> sa; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/sra8_u.h: -------------------------------------------------------------------------------- 1 | P_X_LOOP(8, 3, { 2 | if(sa > 0) 3 | pd = ((ps1 >> (sa - 1)) + 1) >> 1; 4 | else 5 | pd = ps1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/srai.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | WRITE_RD(sext_xlen(sext_xlen(RS1) >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/srai16.h: -------------------------------------------------------------------------------- 1 | P_I_LOOP(16, 4, { 2 | pd = ps1 >> imm4u; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/srai16_u.h: -------------------------------------------------------------------------------- 1 | P_I_LOOP(16, 4, { 2 | if (imm4u > 0) 3 | pd = ((ps1 >> (imm4u - 1)) + 1) >> 1; 4 | else 5 | pd = ps1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/srai32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_I_LOOP(32, 5, { 3 | pd = ps1 >> imm5u; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/srai8.h: -------------------------------------------------------------------------------- 1 | P_I_LOOP(8, 3, { 2 | pd = ps1 >> imm3u; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/srai8_u.h: -------------------------------------------------------------------------------- 1 | P_I_LOOP(8, 3, { 2 | if (imm3u > 0) 3 | pd = ((ps1 >> (imm3u - 1)) + 1) >> 1; 4 | else 5 | pd = ps1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/sraiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(int32_t(RS1) >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sraw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(int32_t(RS1) >> (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /riscv/insns/srl.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(zext_xlen(RS1) >> (RS2 & (xlen-1)))); 2 | -------------------------------------------------------------------------------- /riscv/insns/srl16.h: -------------------------------------------------------------------------------- 1 | P_X_ULOOP(16, 4, { 2 | pd = ps1 >> sa; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/srl16_u.h: -------------------------------------------------------------------------------- 1 | P_X_ULOOP(16, 4, { 2 | if (sa > 0) { 3 | pd = ((ps1 >> (sa - 1)) + 1) >> 1; 4 | } else { 5 | pd = ps1; 6 | } 7 | }) -------------------------------------------------------------------------------- /riscv/insns/srl32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_X_ULOOP(32, 5, { 3 | pd = ps1 >> sa; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/srl8.h: -------------------------------------------------------------------------------- 1 | P_X_ULOOP(8, 3, { 2 | pd = ps1 >> sa; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/srl8_u.h: -------------------------------------------------------------------------------- 1 | P_X_ULOOP(8, 3, { 2 | if (sa > 0) { 3 | pd = ((ps1 >> (sa - 1)) + 1) >> 1; 4 | } else { 5 | pd = ps1; 6 | } 7 | }) -------------------------------------------------------------------------------- /riscv/insns/srli.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | WRITE_RD(sext_xlen(zext_xlen(RS1) >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/srli16.h: -------------------------------------------------------------------------------- 1 | P_I_ULOOP(16, 4, { 2 | pd = ps1 >> imm4u; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/srli16_u.h: -------------------------------------------------------------------------------- 1 | P_I_ULOOP(16, 4, { 2 | if (imm4u > 0) { 3 | pd = ((ps1 >> (imm4u - 1)) + 1) >> 1; 4 | } else { 5 | pd = ps1; 6 | } 7 | }) -------------------------------------------------------------------------------- /riscv/insns/srli32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_I_ULOOP(32, 5, { 3 | pd = ps1 >> imm5u; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/srli8.h: -------------------------------------------------------------------------------- 1 | P_I_ULOOP(8, 3, { 2 | pd = ps1 >> imm3u; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/srli8_u.h: -------------------------------------------------------------------------------- 1 | P_I_ULOOP(8, 3, { 2 | if (imm3u > 0) { 3 | pd = ((ps1 >> (imm3u - 1)) + 1) >> 1; 4 | } else { 5 | pd = ps1; 6 | } 7 | }) -------------------------------------------------------------------------------- /riscv/insns/srliw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32((uint32_t)RS1 >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/srlw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /riscv/insns/sro.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_XBITMANIP); 2 | WRITE_RD(sext_xlen(~((zext_xlen(~RS1)) >> (RS2 & (xlen-1))))); 3 | -------------------------------------------------------------------------------- /riscv/insns/sroi.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | require_extension(EXT_XBITMANIP); 3 | WRITE_RD(sext_xlen(~((zext_xlen(~RS1)) >> SHAMT))); 4 | -------------------------------------------------------------------------------- /riscv/insns/sroiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_XBITMANIP); 3 | WRITE_RD(sext32(~((~(uint32_t)RS1) >> SHAMT))); 4 | -------------------------------------------------------------------------------- /riscv/insns/srow.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_XBITMANIP); 3 | WRITE_RD(sext32(~((~(uint32_t)RS1) >> (RS2 & 0x1F)))); 4 | -------------------------------------------------------------------------------- /riscv/insns/stas16.h: -------------------------------------------------------------------------------- 1 | P_STRAIGHT_LOOP(16, { 2 | pd = ps1 + ps2; 3 | }, { 4 | pd = ps1 - ps2; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/stas32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_STRAIGHT_LOOP(32, { 3 | pd = ps1 + ps2; 4 | }, { 5 | pd = ps1 - ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/stsa16.h: -------------------------------------------------------------------------------- 1 | P_STRAIGHT_LOOP(16, { 2 | pd = ps1 - ps2; 3 | }, { 4 | pd = ps1 + ps2; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/stsa32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_STRAIGHT_LOOP(32, { 3 | pd = ps1 - ps2; 4 | }, { 5 | pd = ps1 + ps2; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/sub.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 - RS2)); 2 | -------------------------------------------------------------------------------- /riscv/insns/sub16.h: -------------------------------------------------------------------------------- 1 | P_LOOP(16, { 2 | pd = ps1 - ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/sub32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_LOOP(32, { 3 | pd = ps1 - ps2; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/sub64.h: -------------------------------------------------------------------------------- 1 | P_64_PROFILE({ 2 | rd = rs1 - rs2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/sub8.h: -------------------------------------------------------------------------------- 1 | P_LOOP(8, { 2 | pd = ps1 - ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/subw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 - RS2)); 3 | 4 | -------------------------------------------------------------------------------- /riscv/insns/sunpkd810.h: -------------------------------------------------------------------------------- 1 | P_SUNPKD8(1, 0) -------------------------------------------------------------------------------- /riscv/insns/sunpkd820.h: -------------------------------------------------------------------------------- 1 | P_SUNPKD8(2, 0) -------------------------------------------------------------------------------- /riscv/insns/sunpkd830.h: -------------------------------------------------------------------------------- 1 | P_SUNPKD8(3, 0) -------------------------------------------------------------------------------- /riscv/insns/sunpkd831.h: -------------------------------------------------------------------------------- 1 | P_SUNPKD8(3, 1) -------------------------------------------------------------------------------- /riscv/insns/sunpkd832.h: -------------------------------------------------------------------------------- 1 | P_SUNPKD8(3, 2) -------------------------------------------------------------------------------- /riscv/insns/sw.h: -------------------------------------------------------------------------------- 1 | MMU.store_uint32(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/swap8.h: -------------------------------------------------------------------------------- 1 | P_ONE_LOOP_BASE(8) 2 | auto pd = P_FIELD(rs1, (i ^ 1), 8); 3 | WRITE_PD(); 4 | P_LOOP_END() -------------------------------------------------------------------------------- /riscv/insns/ucmple16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | pd = (ps1 <= ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/ucmple8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | pd = (ps1 <= ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/ucmplt16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | pd = (ps1 < ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/ucmplt8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | pd = (ps1 < ps2) ? -1 : 0; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/ukadd16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | bool sat = false; 3 | pd = (sat_addu(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ukadd32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_ULOOP(32, { 3 | bool sat = false; 4 | pd = (sat_addu(ps1, ps2, sat)); 5 | P_SET_OV(sat); 6 | }) -------------------------------------------------------------------------------- /riscv/insns/ukadd64.h: -------------------------------------------------------------------------------- 1 | P_64_UPROFILE({ 2 | bool sat = false; 3 | rd = (sat_addu(rs1, rs2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ukadd8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | bool sat = false; 3 | pd = (sat_addu(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ukaddh.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_W(RS1, 0) + (sreg_t)P_W(RS2, 0); 3 | P_SATU(res, 16); 4 | WRITE_RD(sext_xlen((int16_t)res)); -------------------------------------------------------------------------------- /riscv/insns/ukaddw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_W(RS1, 0) + (sreg_t)P_W(RS2, 0); 3 | P_SATU(res, 32); 4 | WRITE_RD(sext32(res)); -------------------------------------------------------------------------------- /riscv/insns/ukmar64.h: -------------------------------------------------------------------------------- 1 | P_64_UPROFILE_REDUCTION(32, { 2 | bool sat = false; 3 | rd = (sat_addu(rd, ps1 * ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/ukmsr64.h: -------------------------------------------------------------------------------- 1 | P_64_UPROFILE_REDUCTION(32, { 2 | bool sat = false; 3 | rd = (sat_subu(rd, ps1 * ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/uksub16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | bool sat = false; 3 | pd = (sat_subu(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/uksub32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_ULOOP(32, { 3 | bool sat = false; 4 | pd = (sat_subu(ps1, ps2, sat)); 5 | P_SET_OV(sat); 6 | }) -------------------------------------------------------------------------------- /riscv/insns/uksub64.h: -------------------------------------------------------------------------------- 1 | P_64_UPROFILE({ 2 | bool sat = false; 3 | rd = (sat_subu(rs1, rs2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/uksub8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | bool sat = false; 3 | pd = (sat_subu(ps1, ps2, sat)); 4 | P_SET_OV(sat); 5 | }) -------------------------------------------------------------------------------- /riscv/insns/uksubh.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_W(RS1, 0) - (sreg_t)P_W(RS2, 0); 3 | P_SATU(res, 16); 4 | WRITE_RD(sext_xlen((int16_t)res)); -------------------------------------------------------------------------------- /riscv/insns/uksubw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | sreg_t res = (sreg_t)P_W(RS1, 0) - (sreg_t)P_W(RS2, 0); 3 | P_SATU(res, 32); 4 | WRITE_RD(sext32(res)); -------------------------------------------------------------------------------- /riscv/insns/umaqa.h: -------------------------------------------------------------------------------- 1 | P_REDUCTION_ULOOP(32, 8, true, false, { 2 | pd_res += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umar64.h: -------------------------------------------------------------------------------- 1 | P_64_UPROFILE_REDUCTION(32, { 2 | rd += ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umax16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | pd = (ps1 > ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umax32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_ULOOP(32, { 3 | pd = (ps1 > ps2) ? ps1 : ps2; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/umax8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | pd = (ps1 > ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umin16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | pd = (ps1 < ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umin32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_ULOOP(32, { 3 | pd = (ps1 < ps2) ? ps1 : ps2; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/umin8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | pd = (ps1 < ps2) ? ps1 : ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umsr64.h: -------------------------------------------------------------------------------- 1 | P_64_UPROFILE_REDUCTION(32, { 2 | rd -= ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umul16.h: -------------------------------------------------------------------------------- 1 | P_MUL_ULOOP(16, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umul8.h: -------------------------------------------------------------------------------- 1 | P_MUL_ULOOP(8, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umulx16.h: -------------------------------------------------------------------------------- 1 | P_MUL_CROSS_ULOOP(16, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/umulx8.h: -------------------------------------------------------------------------------- 1 | P_MUL_CROSS_ULOOP(8, { 2 | pd = ps1 * ps2; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/uradd16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | pd = (ps1 + ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/uradd32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_ULOOP(32, { 3 | pd = ((uint64_t)ps1 + ps2) >> 1; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/uradd8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | pd = (ps1 + ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/uraddw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | reg_t res = (reg_t)P_W(RS1, 0) + (reg_t)P_W(RS2, 0); 3 | res >>= 1; 4 | WRITE_RD(sext_xlen((int32_t)res)); -------------------------------------------------------------------------------- /riscv/insns/urcras16.h: -------------------------------------------------------------------------------- 1 | P_CROSS_ULOOP(16, { 2 | pd = (ps1 + ps2) >> 1; 3 | }, { 4 | pd = (ps1 - ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/urcras32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_CROSS_ULOOP(32, { 3 | pd = ((uint64_t)ps1 + ps2) >> 1; 4 | }, { 5 | pd = ((uint64_t)ps1 - ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/urcrsa16.h: -------------------------------------------------------------------------------- 1 | P_CROSS_ULOOP(16, { 2 | pd = (ps1 - ps2) >> 1; 3 | }, { 4 | pd = (ps1 + ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/urcrsa32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_CROSS_ULOOP(32, { 3 | pd = ((uint64_t)ps1 - ps2) >> 1; 4 | }, { 5 | pd = ((uint64_t)ps1 + ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/urstas16.h: -------------------------------------------------------------------------------- 1 | P_STRAIGHT_ULOOP(16, { 2 | pd = (ps1 + ps2) >> 1; 3 | }, { 4 | pd = (ps1 - ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/urstas32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_STRAIGHT_ULOOP(32, { 3 | pd = ((uint64_t)ps1 + ps2) >> 1; 4 | }, { 5 | pd = ((uint64_t)ps1 - ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/urstsa16.h: -------------------------------------------------------------------------------- 1 | P_STRAIGHT_ULOOP(16, { 2 | pd = (ps1 - ps2) >> 1; 3 | }, { 4 | pd = (ps1 + ps2) >> 1; 5 | }) -------------------------------------------------------------------------------- /riscv/insns/urstsa32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_STRAIGHT_ULOOP(32, { 3 | pd = ((uint64_t)ps1 - ps2) >> 1; 4 | }, { 5 | pd = ((uint64_t)ps1 + ps2) >> 1; 6 | }) -------------------------------------------------------------------------------- /riscv/insns/ursub16.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(16, { 2 | pd = (ps1 - ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/ursub32.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | P_ULOOP(32, { 3 | pd = ((uint64_t)ps1 - ps2) >> 1; 4 | }) -------------------------------------------------------------------------------- /riscv/insns/ursub8.h: -------------------------------------------------------------------------------- 1 | P_ULOOP(8, { 2 | pd = (ps1 - ps2) >> 1; 3 | }) -------------------------------------------------------------------------------- /riscv/insns/ursubw.h: -------------------------------------------------------------------------------- 1 | require_extension('P'); 2 | reg_t res = (reg_t)P_W(RS1, 0) - (reg_t)P_W(RS2, 0); 3 | res >>= 1; 4 | WRITE_RD(sext_xlen((int32_t)res)); -------------------------------------------------------------------------------- /riscv/insns/vaadd_vv.h: -------------------------------------------------------------------------------- 1 | // vaadd.vv vd, vs2, vs1 2 | VI_VVX_LOOP_AVG(vs1, +, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vaadd_vx.h: -------------------------------------------------------------------------------- 1 | // vaadd.vx vd, vs2, rs1 2 | VI_VVX_LOOP_AVG(rs1, +, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vaaddu_vv.h: -------------------------------------------------------------------------------- 1 | // vaaddu.vv vd, vs2, vs1 2 | VI_VVX_ULOOP_AVG(vs1, +, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vaaddu_vx.h: -------------------------------------------------------------------------------- 1 | // vaaddu.vx vd, vs2, rs1 2 | VI_VVX_ULOOP_AVG(rs1, +, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vadd_vi.h: -------------------------------------------------------------------------------- 1 | // vadd.vi vd, simm5, vs2, vm 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vadd_vv.h: -------------------------------------------------------------------------------- 1 | // vadd.vv vd, vs1, vs2, vm 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vadd_vx.h: -------------------------------------------------------------------------------- 1 | // vadd.vx vd, rs1, vs2, vm 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vamoaddei16_v.h: -------------------------------------------------------------------------------- 1 | //vamoadde.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs + vs3; }, uint, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoaddei32_v.h: -------------------------------------------------------------------------------- 1 | //vamoadde.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs + vs3; }, uint, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoaddei64_v.h: -------------------------------------------------------------------------------- 1 | //vamoadde.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs + vs3; }, uint, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoaddei8_v.h: -------------------------------------------------------------------------------- 1 | //vamoadde.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs + vs3; }, uint, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoandei16_v.h: -------------------------------------------------------------------------------- 1 | //vamoande.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs & vs3; }, uint, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoandei32_v.h: -------------------------------------------------------------------------------- 1 | //vamoande.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs & vs3; }, uint, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoandei64_v.h: -------------------------------------------------------------------------------- 1 | //vamoande.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs & vs3; }, uint, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoandei8_v.h: -------------------------------------------------------------------------------- 1 | //vamoande.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs & vs3; }, uint, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxei16_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxe.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxei32_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxe.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxei64_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxe.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxei8_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxe.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxuei16_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxuei32_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxuei64_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamomaxuei8_v.h: -------------------------------------------------------------------------------- 1 | //vamomaxue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominei16_v.h: -------------------------------------------------------------------------------- 1 | //vamomine.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominei32_v.h: -------------------------------------------------------------------------------- 1 | //vamomine.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominei64_v.h: -------------------------------------------------------------------------------- 1 | //vamomine.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominei8_v.h: -------------------------------------------------------------------------------- 1 | //vamomine.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominuei16_v.h: -------------------------------------------------------------------------------- 1 | //vamominue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominuei32_v.h: -------------------------------------------------------------------------------- 1 | //vamominue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominuei64_v.h: -------------------------------------------------------------------------------- 1 | //vamominue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamominuei8_v.h: -------------------------------------------------------------------------------- 1 | //vamominue.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoorei16_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs | vs3; }, uint, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoorei32_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs | vs3; }, uint, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoorei64_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs | vs3; }, uint, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoorei8_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs | vs3; }, uint, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoswapei16_v.h: -------------------------------------------------------------------------------- 1 | //vamoswape.v vd, (rs1), vs2, vd 2 | VI_AMO({ return vs3; }, uint, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoswapei32_v.h: -------------------------------------------------------------------------------- 1 | //vamoswape.v vd, (rs1), vs2, vd 2 | VI_AMO({ return vs3; }, uint, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoswapei64_v.h: -------------------------------------------------------------------------------- 1 | //vamoswape.v vd, (rs1), vs2, vd 2 | VI_AMO({ return vs3; }, uint, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoswapei8_v.h: -------------------------------------------------------------------------------- 1 | //vamoswape.v vd, (rs1), vs2, vd 2 | VI_AMO({ return vs3; }, uint, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoxorei16_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs ^ vs3; }, uint, e16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoxorei32_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs ^ vs3; }, uint, e32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoxorei64_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs ^ vs3; }, uint, e64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vamoxorei8_v.h: -------------------------------------------------------------------------------- 1 | //vamoore.v vd, (rs1), vs2, vd 2 | VI_AMO({ return lhs ^ vs3; }, uint, e8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vand_vi.h: -------------------------------------------------------------------------------- 1 | // vand.vi vd, simm5, vs2, vm 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 & vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vand_vv.h: -------------------------------------------------------------------------------- 1 | // vand.vv vd, vs1, vs2, vm 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 & vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vand_vx.h: -------------------------------------------------------------------------------- 1 | // vand.vx vd, rs1, vs2, vm 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 & vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vasub_vv.h: -------------------------------------------------------------------------------- 1 | // vasub.vv vd, vs2, vs1 2 | VI_VVX_LOOP_AVG(vs1, -, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vasub_vx.h: -------------------------------------------------------------------------------- 1 | // vasub.vx vd, vs2, rs1 2 | VI_VVX_LOOP_AVG(rs1, -, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vasubu_vv.h: -------------------------------------------------------------------------------- 1 | // vasubu.vv vd, vs2, vs1 2 | VI_VVX_ULOOP_AVG(vs1, -, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vasubu_vx.h: -------------------------------------------------------------------------------- 1 | // vasubu.vx vd, vs2, rs1 2 | VI_VVX_ULOOP_AVG(rs1, -, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vdivu_vv.h: -------------------------------------------------------------------------------- 1 | // vdivu.vv vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | if(vs1 == 0) 5 | vd = -1; 6 | else 7 | vd = vs2 / vs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vdivu_vx.h: -------------------------------------------------------------------------------- 1 | // vdivu.vx vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | if(rs1 == 0) 5 | vd = -1; 6 | else 7 | vd = vs2 / rs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_vf.h: -------------------------------------------------------------------------------- 1 | // vfwadd.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_add(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_add(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_vv.h: -------------------------------------------------------------------------------- 1 | // vfwadd.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_add(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_add(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_wf.h: -------------------------------------------------------------------------------- 1 | // vfwadd.wf vd, vs2, vs1 2 | VI_VFP_WF_LOOP_WIDE 3 | ({ 4 | vd = f32_add(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_add(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_wv.h: -------------------------------------------------------------------------------- 1 | // vfwadd.wv vd, vs2, vs1 2 | VI_VFP_WV_LOOP_WIDE 3 | ({ 4 | vd = f32_add(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_add(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwmul_vf.h: -------------------------------------------------------------------------------- 1 | // vfwmul.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_mul(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_mul(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwmul_vv.h: -------------------------------------------------------------------------------- 1 | // vfwmul.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_mul(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_mul(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_vf.h: -------------------------------------------------------------------------------- 1 | // vfwsub.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_vv.h: -------------------------------------------------------------------------------- 1 | // vfwsub.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_wf.h: -------------------------------------------------------------------------------- 1 | // vfwsub.wf vd, vs2, rs1 2 | VI_VFP_WF_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_wv.h: -------------------------------------------------------------------------------- 1 | // vfwsub.wv vd, vs2, vs1 2 | VI_VFP_WV_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vl1re16_v.h: -------------------------------------------------------------------------------- 1 | // vl1re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re32_v.h: -------------------------------------------------------------------------------- 1 | // vl1re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re64_v.h: -------------------------------------------------------------------------------- 1 | // vl1re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re8_v.h: -------------------------------------------------------------------------------- 1 | // vl1re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re16_v.h: -------------------------------------------------------------------------------- 1 | // vl2e16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re32_v.h: -------------------------------------------------------------------------------- 1 | // vl2re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re64_v.h: -------------------------------------------------------------------------------- 1 | // vl2re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re8_v.h: -------------------------------------------------------------------------------- 1 | // vl2re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re16_v.h: -------------------------------------------------------------------------------- 1 | // vl4re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re32_v.h: -------------------------------------------------------------------------------- 1 | // vl4re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re64_v.h: -------------------------------------------------------------------------------- 1 | // vl4re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re8_v.h: -------------------------------------------------------------------------------- 1 | // vl4re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re16_v.h: -------------------------------------------------------------------------------- 1 | // vl8re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re32_v.h: -------------------------------------------------------------------------------- 1 | // vl8re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re64_v.h: -------------------------------------------------------------------------------- 1 | // vl8re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re8_v.h: -------------------------------------------------------------------------------- 1 | // vl8re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle16_v.h: -------------------------------------------------------------------------------- 1 | // vle16.v and vlseg[2-8]e16.v 2 | VI_LD(0, (i * nf + fn), int16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle16ff_v.h: -------------------------------------------------------------------------------- 1 | // vle16ff.v and vlseg[2-8]e16ff.v 2 | VI_LDST_FF(int16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle32_v.h: -------------------------------------------------------------------------------- 1 | // vle32.v and vlseg[2-8]e32.v 2 | VI_LD(0, (i * nf + fn), int32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle32ff_v.h: -------------------------------------------------------------------------------- 1 | // vle32ff.v and vlseg[2-8]e32ff.v 2 | VI_LDST_FF(int32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle64_v.h: -------------------------------------------------------------------------------- 1 | // vle64.v and vlseg[2-8]e64.v 2 | VI_LD(0, (i * nf + fn), int64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle64ff_v.h: -------------------------------------------------------------------------------- 1 | // vle64ff.v and vlseg[2-8]e64ff.v 2 | VI_LDST_FF(int64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle8_v.h: -------------------------------------------------------------------------------- 1 | // vle8.v and vlseg[2-8]e8.v 2 | VI_LD(0, (i * nf + fn), int8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle8ff_v.h: -------------------------------------------------------------------------------- 1 | // vle8ff.v and vlseg[2-8]e8ff.v 2 | VI_LDST_FF(int8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlm_v.h: -------------------------------------------------------------------------------- 1 | // vle1.v and vlseg[2-8]e8.v 2 | VI_LD(0, (i * nf + fn), int8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vloxei16_v.h: -------------------------------------------------------------------------------- 1 | // vlxei16.v and vlxseg[2-8]e16.v 2 | VI_LD_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vloxei32_v.h: -------------------------------------------------------------------------------- 1 | // vlxe32.v and vlxseg[2-8]ei32.v 2 | VI_LD_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vloxei64_v.h: -------------------------------------------------------------------------------- 1 | // vlxei64.v and vlxseg[2-8]ei64.v 2 | VI_LD_INDEX(e64, true); 3 | 4 | -------------------------------------------------------------------------------- /riscv/insns/vloxei8_v.h: -------------------------------------------------------------------------------- 1 | // vlxei8.v and vlxseg[2-8]ei8.v 2 | VI_LD_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse16_v.h: -------------------------------------------------------------------------------- 1 | // vlse16.v and vlsseg[2-8]e16.v 2 | VI_LD(i * RS2, fn, int16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse32_v.h: -------------------------------------------------------------------------------- 1 | // vlse32.v and vlsseg[2-8]e32.v 2 | VI_LD(i * RS2, fn, int32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse64_v.h: -------------------------------------------------------------------------------- 1 | // vlse64.v and vlsseg[2-8]e64.v 2 | VI_LD(i * RS2, fn, int64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse8_v.h: -------------------------------------------------------------------------------- 1 | // vlse8.v and vlsseg[2-8]e8.v 2 | VI_LD(i * RS2, fn, int8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vluxei16_v.h: -------------------------------------------------------------------------------- 1 | // vlxei16.v and vlxseg[2-8]e16.v 2 | VI_LD_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vluxei32_v.h: -------------------------------------------------------------------------------- 1 | // vlxe32.v and vlxseg[2-8]ei32.v 2 | VI_LD_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vluxei64_v.h: -------------------------------------------------------------------------------- 1 | // vlxei64.v and vlxseg[2-8]ei64.v 2 | VI_LD_INDEX(e64, true); 3 | 4 | -------------------------------------------------------------------------------- /riscv/insns/vluxei8_v.h: -------------------------------------------------------------------------------- 1 | // vlxei8.v and vlxseg[2-8]ei8.v 2 | VI_LD_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmacc_vv.h: -------------------------------------------------------------------------------- 1 | // vmacc.vv: vd[i] = +(vs1[i] * vs2[i]) + vd[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 * vs2 + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmacc_vx.h: -------------------------------------------------------------------------------- 1 | // vmacc.vx: vd[i] = +(x[rs1] * vs2[i]) + vd[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 * vs2 + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vi.h: -------------------------------------------------------------------------------- 1 | // vmadc.vi vd, vs2, simm5 2 | #include "vmadc_vim.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vv.h: -------------------------------------------------------------------------------- 1 | // vmadc.vvm vd, vs2, rs1 2 | #include "vmadc_vvm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vx.h: -------------------------------------------------------------------------------- 1 | // vadc.vx vd, vs2, rs1 2 | #include "vmadc_vxm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmadd_vv.h: -------------------------------------------------------------------------------- 1 | // vmadd: vd[i] = (vd[i] * vs1[i]) + vs2[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = vd * vs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmadd_vx.h: -------------------------------------------------------------------------------- 1 | // vmadd: vd[i] = (vd[i] * x[rs1]) + vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = vd * rs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmand_mm.h: -------------------------------------------------------------------------------- 1 | // vmand.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 & vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmandnot_mm.h: -------------------------------------------------------------------------------- 1 | // vmandnot.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 & ~vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmnand_mm.h: -------------------------------------------------------------------------------- 1 | // vmnand.mm vd, vs2, vs1 2 | VI_LOOP_MASK(~(vs2 & vs1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmnor_mm.h: -------------------------------------------------------------------------------- 1 | // vmnor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(~(vs2 | vs1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmor_mm.h: -------------------------------------------------------------------------------- 1 | // vmor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 | vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmornot_mm.h: -------------------------------------------------------------------------------- 1 | // vmornot.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 | ~vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmsbc_vv.h: -------------------------------------------------------------------------------- 1 | // vmsbc.vv vd, vs2, rs1 2 | #include "vmsbc_vvm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmsbc_vx.h: -------------------------------------------------------------------------------- 1 | // vmsbc.vx vd, vs2, rs1 2 | #include "vmsbc_vxm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmseq_vi.h: -------------------------------------------------------------------------------- 1 | // vseq.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = simm5 == vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmseq_vv.h: -------------------------------------------------------------------------------- 1 | // vseq.vv vd, vs2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 == vs1; 5 | }) 6 | 7 | -------------------------------------------------------------------------------- /riscv/insns/vmseq_vx.h: -------------------------------------------------------------------------------- 1 | // vseq.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = rs1 == vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsgt_vi.h: -------------------------------------------------------------------------------- 1 | // vsgt.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = vs2 > simm5; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsgt_vx.h: -------------------------------------------------------------------------------- 1 | // vsgt.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 > rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsgtu_vi.h: -------------------------------------------------------------------------------- 1 | // vmsgtu.vi vd, vd2, simm5 2 | VI_VI_ULOOP_CMP 3 | ({ 4 | res = vs2 > (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsgtu_vx.h: -------------------------------------------------------------------------------- 1 | // vsgtu.vx vd, vs2, rs1 2 | VI_VX_ULOOP_CMP 3 | ({ 4 | res = vs2 > rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsle_vi.h: -------------------------------------------------------------------------------- 1 | // vsle.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = vs2 <= simm5; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsle_vv.h: -------------------------------------------------------------------------------- 1 | // vsle.vv vd, vs2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 <= vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsle_vx.h: -------------------------------------------------------------------------------- 1 | // vsle.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 <= rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsleu_vi.h: -------------------------------------------------------------------------------- 1 | // vmsleu.vi vd, vs2, simm5 2 | VI_VI_ULOOP_CMP 3 | ({ 4 | res = vs2 <= (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsleu_vv.h: -------------------------------------------------------------------------------- 1 | // vsleu.vv vd, vs2, vs1 2 | VI_VV_ULOOP_CMP 3 | ({ 4 | res = vs2 <= vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsleu_vx.h: -------------------------------------------------------------------------------- 1 | // vsleu.vx vd, vs2, rs1 2 | VI_VX_ULOOP_CMP 3 | ({ 4 | res = vs2 <= rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmslt_vv.h: -------------------------------------------------------------------------------- 1 | // vslt.vv vd, vd2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 < vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmslt_vx.h: -------------------------------------------------------------------------------- 1 | // vslt.vx vd, vs2, vs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 < rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsltu_vv.h: -------------------------------------------------------------------------------- 1 | // vsltu.vv vd, vs2, vs1 2 | VI_VV_ULOOP_CMP 3 | ({ 4 | res = vs2 < vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsltu_vx.h: -------------------------------------------------------------------------------- 1 | // vsltu.vx vd, vs2, vs1 2 | VI_VX_ULOOP_CMP 3 | ({ 4 | res = vs2 < rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsne_vi.h: -------------------------------------------------------------------------------- 1 | // vsne.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = vs2 != simm5; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsne_vv.h: -------------------------------------------------------------------------------- 1 | // vneq.vv vd, vs2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 != vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsne_vx.h: -------------------------------------------------------------------------------- 1 | // vsne.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 != rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmul_vv.h: -------------------------------------------------------------------------------- 1 | // vmul vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs2 * vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmul_vx.h: -------------------------------------------------------------------------------- 1 | // vmul vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | vd = vs2 * rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmulh_vv.h: -------------------------------------------------------------------------------- 1 | // vmulh vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | vd = ((int128_t)vs2 * vs1) >> sew; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmulh_vx.h: -------------------------------------------------------------------------------- 1 | // vmulh vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | vd = ((int128_t)vs2 * rs1) >> sew; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmulhu_vv.h: -------------------------------------------------------------------------------- 1 | // vmulhu vd ,vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | vd = ((uint128_t)vs2 * vs1) >> sew; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmulhu_vx.h: -------------------------------------------------------------------------------- 1 | // vmulhu vd ,vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | vd = ((uint128_t)vs2 * rs1) >> sew; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmv1r_v.h: -------------------------------------------------------------------------------- 1 | // vmv1r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv2r_v.h: -------------------------------------------------------------------------------- 1 | // vmv2r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv4r_v.h: -------------------------------------------------------------------------------- 1 | // vmv4r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv8r_v.h: -------------------------------------------------------------------------------- 1 | // vmv8r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv_v_i.h: -------------------------------------------------------------------------------- 1 | // vmv.v.i vd, simm5 2 | require_vector(true); 3 | VI_CHECK_SSS(false); 4 | VI_VVXI_MERGE_LOOP 5 | ({ 6 | vd = simm5; 7 | }) 8 | -------------------------------------------------------------------------------- /riscv/insns/vmv_v_v.h: -------------------------------------------------------------------------------- 1 | // vvmv.v.v vd, vs1 2 | require_vector(true); 3 | VI_CHECK_SSS(true); 4 | VI_VVXI_MERGE_LOOP 5 | ({ 6 | vd = vs1; 7 | }) 8 | -------------------------------------------------------------------------------- /riscv/insns/vmv_v_x.h: -------------------------------------------------------------------------------- 1 | // vmv.v.x vd, rs1 2 | require_vector(true); 3 | VI_CHECK_SSS(false); 4 | VI_VVXI_MERGE_LOOP 5 | ({ 6 | vd = rs1; 7 | }) 8 | -------------------------------------------------------------------------------- /riscv/insns/vmxnor_mm.h: -------------------------------------------------------------------------------- 1 | // vmnxor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(~(vs2 ^ vs1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmxor_mm.h: -------------------------------------------------------------------------------- 1 | // vmxor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 ^ vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vnmsac_vv.h: -------------------------------------------------------------------------------- 1 | // vmsac.vv: vd[i] = -(vs1[i] * vs2[i]) + vd[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = -(vs1 * vs2) + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnmsac_vx.h: -------------------------------------------------------------------------------- 1 | // vmsac: vd[i] = -(x[rs1] * vs2[i]) + vd[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = -(rs1 * vs2) + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnmsub_vv.h: -------------------------------------------------------------------------------- 1 | // vnmsub.vv: vd[i] = -(vd[i] * vs1[i]) + vs2[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = -(vd * vs1) + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnmsub_vx.h: -------------------------------------------------------------------------------- 1 | // vnmsub.vx: vd[i] = -(vd[i] * x[rs1]) + vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = -(vd * rs1) + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsra_wi.h: -------------------------------------------------------------------------------- 1 | // vnsra.vi vd, vs2, zimm5 2 | VI_VI_LOOP_NSHIFT 3 | ({ 4 | vd = vs2 >> (zimm5 & (sew * 2 - 1) & 0x1f); 5 | }, false) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsra_wv.h: -------------------------------------------------------------------------------- 1 | // vnsra.vv vd, vs2, vs1 2 | VI_VV_LOOP_NSHIFT 3 | ({ 4 | vd = vs2 >> (vs1 & (sew * 2 - 1)); 5 | }, true) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsra_wx.h: -------------------------------------------------------------------------------- 1 | // vnsra.vx vd, vs2, rs1 2 | VI_VX_LOOP_NSHIFT 3 | ({ 4 | vd = vs2 >> (rs1 & (sew * 2 - 1)); 5 | }, false) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsrl_wi.h: -------------------------------------------------------------------------------- 1 | // vnsrl.vi vd, vs2, zimm5 2 | VI_VI_LOOP_NSHIFT 3 | ({ 4 | vd = vs2_u >> (zimm5 & (sew * 2 - 1)); 5 | }, false) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsrl_wv.h: -------------------------------------------------------------------------------- 1 | // vnsrl.vv vd, vs2, vs1 2 | VI_VV_LOOP_NSHIFT 3 | ({ 4 | vd = vs2_u >> (vs1 & (sew * 2 - 1)); 5 | }, true) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsrl_wx.h: -------------------------------------------------------------------------------- 1 | // vnsrl.vx vd, vs2, rs1 2 | VI_VX_LOOP_NSHIFT 3 | ({ 4 | vd = vs2_u >> (rs1 & (sew * 2 - 1)); 5 | }, false) 6 | -------------------------------------------------------------------------------- /riscv/insns/vor_vi.h: -------------------------------------------------------------------------------- 1 | // vor 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 | vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vor_vv.h: -------------------------------------------------------------------------------- 1 | // vor 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 | vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vor_vx.h: -------------------------------------------------------------------------------- 1 | // vor 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 | vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredand_vs.h: -------------------------------------------------------------------------------- 1 | // vredand.vs vd, vs2 ,vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res &= vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredmax_vs.h: -------------------------------------------------------------------------------- 1 | // vredmax.vs vd, vs2 ,vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredmaxu_vs.h: -------------------------------------------------------------------------------- 1 | // vredmaxu.vs vd, vs2 ,vs1 2 | VI_VV_ULOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredmin_vs.h: -------------------------------------------------------------------------------- 1 | // vredmin.vs vd, vs2 ,vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredminu_vs.h: -------------------------------------------------------------------------------- 1 | // vredminu.vs vd, vs2 ,vs1 2 | VI_VV_ULOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredor_vs.h: -------------------------------------------------------------------------------- 1 | // vredor.vs vd, vs2 ,vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res |= vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredsum_vs.h: -------------------------------------------------------------------------------- 1 | // vredsum.vs vd, vs2 ,vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res += vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredxor_vs.h: -------------------------------------------------------------------------------- 1 | // vredxor.vs vd, vs2 ,vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res ^= vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vremu_vv.h: -------------------------------------------------------------------------------- 1 | // vremu.vv vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | if (vs1 == 0) 5 | vd = vs2; 6 | else 7 | vd = vs2 % vs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vremu_vx.h: -------------------------------------------------------------------------------- 1 | // vremu.vx vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | if (rs1 == 0) 5 | vd = vs2; 6 | else 7 | vd = vs2 % rs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vrsub_vi.h: -------------------------------------------------------------------------------- 1 | // vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i] 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 - vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vrsub_vx.h: -------------------------------------------------------------------------------- 1 | // vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1 - vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 - vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vs1r_v.h: -------------------------------------------------------------------------------- 1 | // vs1r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vs2r_v.h: -------------------------------------------------------------------------------- 1 | // vs2r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vs4r_v.h: -------------------------------------------------------------------------------- 1 | // vs4r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vs8r_v.h: -------------------------------------------------------------------------------- 1 | // vs8r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vse16_v.h: -------------------------------------------------------------------------------- 1 | // vse16.v and vsseg[2-8]e16.v 2 | VI_ST(0, (i * nf + fn), uint16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vse32_v.h: -------------------------------------------------------------------------------- 1 | // vse32.v and vsseg[2-8]e32.v 2 | VI_ST(0, (i * nf + fn), uint32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vse64_v.h: -------------------------------------------------------------------------------- 1 | // vse64.v and vsseg[2-8]e64.v 2 | VI_ST(0, (i * nf + fn), uint64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vse8_v.h: -------------------------------------------------------------------------------- 1 | // vse8.v and vsseg[2-8]e8.v 2 | VI_ST(0, (i * nf + fn), uint8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsetivli.h: -------------------------------------------------------------------------------- 1 | require_vector_novtype(false, false); 2 | WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10())); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsetvl.h: -------------------------------------------------------------------------------- 1 | require_vector_novtype(false, false); 2 | WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsetvli.h: -------------------------------------------------------------------------------- 1 | require_vector_novtype(false, false); 2 | WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11())); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf2.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(2, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf4.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(4, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf8.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(8, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vi.h: -------------------------------------------------------------------------------- 1 | // vsll.vi vd, vs2, zimm5 2 | VI_VI_LOOP 3 | ({ 4 | vd = vs2 << (simm5 & (sew - 1) & 0x1f); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vv.h: -------------------------------------------------------------------------------- 1 | // vsll 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs2 << (vs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vx.h: -------------------------------------------------------------------------------- 1 | // vsll 2 | VI_VX_LOOP 3 | ({ 4 | vd = vs2 << (rs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsm_v.h: -------------------------------------------------------------------------------- 1 | // vse1.v 2 | VI_ST(0, (i * nf + fn), uint8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei16_v.h: -------------------------------------------------------------------------------- 1 | // vsxei16.v and vsxseg[2-8]ei16.v 2 | VI_ST_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei32_v.h: -------------------------------------------------------------------------------- 1 | // vsxei32.v and vsxseg[2-8]ei32.v 2 | VI_ST_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei64_v.h: -------------------------------------------------------------------------------- 1 | // vsxei64.v and vsxseg[2-8]ei64.v 2 | VI_ST_INDEX(e64, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei8_v.h: -------------------------------------------------------------------------------- 1 | // vsxei8.v and vsxseg[2-8]ei8.v 2 | VI_ST_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsra_vi.h: -------------------------------------------------------------------------------- 1 | // vsra.vi vd, vs2, zimm5 2 | VI_VI_LOOP 3 | ({ 4 | vd = vs2 >> (simm5 & (sew - 1) & 0x1f); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsra_vv.h: -------------------------------------------------------------------------------- 1 | // vsra.vv vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs2 >> (vs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsra_vx.h: -------------------------------------------------------------------------------- 1 | // vsra.vx vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | vd = vs2 >> (rs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsrl_vi.h: -------------------------------------------------------------------------------- 1 | // vsrl.vi vd, vs2, zimm5 2 | VI_VI_ULOOP 3 | ({ 4 | vd = vs2 >> (zimm5 & (sew - 1) & 0x1f); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsrl_vv.h: -------------------------------------------------------------------------------- 1 | // vsrl.vv vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | vd = vs2 >> (vs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsrl_vx.h: -------------------------------------------------------------------------------- 1 | // vsrl.vx vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | vd = vs2 >> (rs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsse16_v.h: -------------------------------------------------------------------------------- 1 | // vsse16v and vssseg[2-8]e16.v 2 | VI_ST(i * RS2, fn, uint16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsse32_v.h: -------------------------------------------------------------------------------- 1 | // vsse32.v and vssseg[2-8]e32.v 2 | VI_ST(i * RS2, fn, uint32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsse64_v.h: -------------------------------------------------------------------------------- 1 | // vsse64.v and vssseg[2-8]e64.v 2 | VI_ST(i * RS2, fn, uint64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsse8_v.h: -------------------------------------------------------------------------------- 1 | // vsse8.v and vssseg[2-8]e8.v 2 | VI_ST(i * RS2, fn, uint8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsub_vv.h: -------------------------------------------------------------------------------- 1 | // vsub 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs2 - vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsub_vx.h: -------------------------------------------------------------------------------- 1 | // vsub: vd[i] = (vd[i] * x[rs1]) - vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = vs2 - rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei16_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe16.v 2 | VI_ST_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei32_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe32.v 2 | VI_ST_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei64_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe64.v 2 | VI_ST_INDEX(e64, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei8_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe8.v 2 | VI_ST_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_vv.h: -------------------------------------------------------------------------------- 1 | // vwadd.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_vx.h: -------------------------------------------------------------------------------- 1 | // vwadd.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_wv.h: -------------------------------------------------------------------------------- 1 | // vwadd.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_wx.h: -------------------------------------------------------------------------------- 1 | // vwaddu.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_vv.h: -------------------------------------------------------------------------------- 1 | // vwaddu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_vx.h: -------------------------------------------------------------------------------- 1 | // vwaddu.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_wv.h: -------------------------------------------------------------------------------- 1 | // vwaddu.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_wx.h: -------------------------------------------------------------------------------- 1 | // vwaddu.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmacc_vv.h: -------------------------------------------------------------------------------- 1 | // vwmacc.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmul_vv.h: -------------------------------------------------------------------------------- 1 | // vwmul.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmul_vx.h: -------------------------------------------------------------------------------- 1 | // vwmul.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmulu_vv.h: -------------------------------------------------------------------------------- 1 | // vwmulu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmulu_vx.h: -------------------------------------------------------------------------------- 1 | // vwmul.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwredsum_vs.h: -------------------------------------------------------------------------------- 1 | // vwredsum.vs vd, vs2, vs1 2 | VI_VV_LOOP_WIDE_REDUCTION 3 | ({ 4 | vd_0_res += vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwredsumu_vs.h: -------------------------------------------------------------------------------- 1 | // vwredsum.vs vd, vs2, vs1 2 | VI_VV_ULOOP_WIDE_REDUCTION 3 | ({ 4 | vd_0_res += vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_vv.h: -------------------------------------------------------------------------------- 1 | // vwsub.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_vx.h: -------------------------------------------------------------------------------- 1 | // vwsub.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_wv.h: -------------------------------------------------------------------------------- 1 | // vwsub.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, -, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_wx.h: -------------------------------------------------------------------------------- 1 | // vwsub.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, -, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_vv.h: -------------------------------------------------------------------------------- 1 | // vwsubu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_vx.h: -------------------------------------------------------------------------------- 1 | // vwsubu.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_wv.h: -------------------------------------------------------------------------------- 1 | // vwsubu.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, -, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_wx.h: -------------------------------------------------------------------------------- 1 | // vwsubu.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, -, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vi.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vv.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vx.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf2.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(2, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf4.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(4, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf8.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(8, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/xnor.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | WRITE_RD(RS1 ^ ~RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/xor.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 ^ RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/xori.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.i_imm() ^ RS1); 2 | -------------------------------------------------------------------------------- /riscv/insns/xperm_b.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBKX, EXT_XBITMANIP); 2 | WRITE_RD(sext_xlen(xperm(RS1, RS2, 3, xlen))); 3 | -------------------------------------------------------------------------------- /riscv/insns/xperm_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_XBITMANIP); 2 | WRITE_RD(sext_xlen(xperm(RS1, RS2, 4, xlen))); 3 | -------------------------------------------------------------------------------- /riscv/insns/xperm_n.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBKX, EXT_XBITMANIP); 2 | WRITE_RD(sext_xlen(xperm(RS1, RS2, 2, xlen))); 3 | -------------------------------------------------------------------------------- /riscv/insns/xperm_w.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_XBITMANIP); 3 | WRITE_RD(xperm(RS1, RS2, 5, xlen)); 4 | -------------------------------------------------------------------------------- /riscv/insns/zunpkd810.h: -------------------------------------------------------------------------------- 1 | P_ZUNPKD8(1, 0) -------------------------------------------------------------------------------- /riscv/insns/zunpkd820.h: -------------------------------------------------------------------------------- 1 | P_ZUNPKD8(2, 0) -------------------------------------------------------------------------------- /riscv/insns/zunpkd830.h: -------------------------------------------------------------------------------- 1 | P_ZUNPKD8(3, 0) -------------------------------------------------------------------------------- /riscv/insns/zunpkd831.h: -------------------------------------------------------------------------------- 1 | P_ZUNPKD8(3, 1) -------------------------------------------------------------------------------- /riscv/insns/zunpkd832.h: -------------------------------------------------------------------------------- 1 | P_ZUNPKD8(3, 2) -------------------------------------------------------------------------------- /softfloat/softfloat.ac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/softfloat/softfloat.ac -------------------------------------------------------------------------------- /spike_dasm/spike_dasm.ac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/spike_dasm/spike_dasm.ac -------------------------------------------------------------------------------- /spike_dasm/spike_dasm_option_parser.cc: -------------------------------------------------------------------------------- 1 | ../fesvr/option_parser.cc -------------------------------------------------------------------------------- /spike_main/spike_main.ac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/esp-isa-sim/051d820f08be84d069993de4375d29c91eb2f577/spike_main/spike_main.ac -------------------------------------------------------------------------------- /tests/ebreak.s: -------------------------------------------------------------------------------- 1 | .global main 2 | main: 3 | li a0, 0 4 | ebreak 5 | ret 6 | --------------------------------------------------------------------------------