├── .github └── workflows │ ├── ci.yml │ ├── install-circt │ └── action.yml │ └── setup-oss-cad-suite │ └── action.yml ├── .gitignore ├── .gitmodules ├── .install_verilator.sh ├── .scalafmt.conf ├── LICENSE ├── Makefile ├── README.md ├── build-riscv-tools.sh ├── build.sbt ├── custom-bmark ├── .gitignore ├── Makefile ├── add.S └── main.c ├── diagram.pdf ├── diagram.png ├── project ├── build.properties └── plugins.sbt ├── src ├── main │ ├── cc │ │ ├── mm.cc │ │ ├── mm.h │ │ └── top.cc │ └── scala │ │ ├── junctions │ │ └── nasti.scala │ │ └── mini │ │ ├── Alu.scala │ │ ├── BrCond.scala │ │ ├── CSR.scala │ │ ├── Cache.scala │ │ ├── Config.scala │ │ ├── Control.scala │ │ ├── Core.scala │ │ ├── Datapath.scala │ │ ├── ImmGen.scala │ │ ├── Instructions.scala │ │ ├── Main.scala │ │ ├── RegFile.scala │ │ └── Tile.scala └── test │ └── scala │ └── mini │ ├── ALUTests.scala │ ├── BrCondTests.scala │ ├── CSRTests.scala │ ├── CacheTests.scala │ ├── CoreTests.scala │ ├── DatapathTests.scala │ ├── ImmGenTests.scala │ ├── IntegrationTest.scala │ ├── Opcode.scala │ ├── TestConfig.scala │ ├── TestUtils.scala │ └── TileTester.scala └── tests ├── median.riscv-large.hex ├── median.riscv.hex ├── multiply.riscv-large.hex ├── multiply.riscv.hex ├── qsort.riscv-large.hex ├── qsort.riscv.hex ├── rv32mi-p-csr.hex ├── rv32mi-p-illegal.hex ├── rv32mi-p-ma_addr.hex ├── rv32mi-p-ma_fetch.hex ├── rv32mi-p-sbreak.hex ├── rv32mi-p-scall.hex ├── rv32ui-p-add.hex ├── rv32ui-p-addi.hex ├── rv32ui-p-and.hex ├── rv32ui-p-andi.hex ├── rv32ui-p-auipc.hex ├── rv32ui-p-beq.hex ├── rv32ui-p-bge.hex ├── rv32ui-p-bgeu.hex ├── rv32ui-p-blt.hex ├── rv32ui-p-bltu.hex ├── rv32ui-p-bne.hex ├── rv32ui-p-j.hex ├── rv32ui-p-jal.hex ├── rv32ui-p-jalr.hex ├── rv32ui-p-lb.hex ├── rv32ui-p-lbu.hex ├── rv32ui-p-lh.hex ├── rv32ui-p-lhu.hex ├── rv32ui-p-lui.hex ├── rv32ui-p-lw.hex ├── rv32ui-p-or.hex ├── rv32ui-p-ori.hex ├── rv32ui-p-sb.hex ├── rv32ui-p-sh.hex ├── rv32ui-p-simple.hex ├── rv32ui-p-sll.hex ├── rv32ui-p-slli.hex ├── rv32ui-p-slt.hex ├── rv32ui-p-slti.hex ├── rv32ui-p-sra.hex ├── rv32ui-p-srai.hex ├── rv32ui-p-sub.hex ├── rv32ui-p-sw.hex ├── rv32ui-p-xor.hex ├── rv32ui-p-xori.hex ├── towers.riscv-large.hex ├── towers.riscv.hex ├── vvadd.riscv-large.hex └── vvadd.riscv.hex /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | name: riscv-mini Tests 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | test: 7 | name: Scala Unit Tests 8 | runs-on: ubuntu-latest 9 | steps: 10 | - uses: actions/checkout@v3 11 | - name: Install Tabby OSS Cad Suite (from YosysHQ) 12 | uses: ./.github/workflows/setup-oss-cad-suite 13 | with: 14 | osscadsuite-version: '2022-02-02' 15 | - name: Scala Unit Tests 16 | run: sbt "testOnly -- -l IntegrationTest" 17 | 18 | integration-tests: 19 | name: Scala Integration Tests 20 | runs-on: ubuntu-latest 21 | steps: 22 | - uses: actions/checkout@v3 23 | - name: Install Tabby OSS Cad Suite (from YosysHQ) 24 | uses: ./.github/workflows/setup-oss-cad-suite 25 | with: 26 | osscadsuite-version: '2022-02-02' 27 | - name: Scala Integration Tests 28 | run: sbt "testOnly -- -n IntegrationTest" 29 | 30 | make-integration-tests: 31 | name: Makefile based Integration Tests 32 | runs-on: ubuntu-latest 33 | steps: 34 | - uses: actions/checkout@v3 35 | - name: Install Tabby OSS Cad Suite (from YosysHQ) 36 | uses: ./.github/workflows/setup-oss-cad-suite 37 | with: 38 | osscadsuite-version: '2022-02-02' 39 | - name: Install CIRCT 40 | uses: ./.github/workflows/install-circt 41 | with: 42 | version: 'firtool-1.37.0' 43 | - name: Makefile Integration Tests 44 | run: make run-tests 45 | 46 | doc: 47 | name: Documentation and Formatting 48 | runs-on: ubuntu-latest 49 | steps: 50 | - name: Checkout 51 | uses: actions/checkout@v3 52 | - name: Documentation 53 | id: doc 54 | run: sbt doc 55 | - name: Check Formatting 56 | run: sbt scalafmtCheckAll 57 | 58 | all_tests_passed: 59 | name: "all tests passed" 60 | needs: [test, doc, integration-tests, make-integration-tests] 61 | runs-on: ubuntu-latest 62 | steps: 63 | - run: echo Success! -------------------------------------------------------------------------------- /.github/workflows/install-circt/action.yml: -------------------------------------------------------------------------------- 1 | name: Install CIRCT 2 | 3 | inputs: 4 | version: 5 | description: 'version to install' 6 | required: false 7 | default: 'firtool-1.43.0' 8 | 9 | runs: 10 | using: composite 11 | steps: 12 | - id: cache-circt 13 | uses: actions/cache@v3 14 | with: 15 | path: circt 16 | key: circt-${{ runner.os }}-${{ inputs.version }} 17 | 18 | - shell: bash 19 | if: steps.cache-circt.outputs.cache-hit != 'true' 20 | run: | 21 | mkdir circt 22 | wget -q -O - https://github.com/llvm/circt/releases/download/${{ inputs.version }}/firrtl-bin-ubuntu-20.04.tar.gz | tar -zx -C circt/ --strip-components 1 23 | 24 | - shell: bash 25 | run: echo "$(pwd)/circt/bin" >> $GITHUB_PATH 26 | -------------------------------------------------------------------------------- /.github/workflows/setup-oss-cad-suite/action.yml: -------------------------------------------------------------------------------- 1 | name: Setup OSS CAD Suite 2 | 3 | inputs: 4 | osscadsuite-version: 5 | description: 'version to install' 6 | required: true 7 | 8 | runs: 9 | using: composite 10 | steps: 11 | - id: cache-oss-cad-suite 12 | uses: actions/cache@v3 13 | with: 14 | path: oss-cad-suite 15 | key: oss-cad-suite-${{ runner.os }}-${{ inputs.osscadsuite-version }} 16 | 17 | - shell: bash 18 | if: steps.cache-oss-cad-suite.outputs.cache-hit != 'true' 19 | run: | 20 | VERSION=${{ inputs.osscadsuite-version }} 21 | ARTIFACT=oss-cad-suite-linux-x64-$(echo $VERSION | tr -d '-') 22 | wget -q -O - https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${VERSION}/${ARTIFACT}.tgz | tar -zx 23 | 24 | # Add the CAD Suite to the PATH 25 | - shell: bash 26 | run: echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH 27 | 28 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | generated-src 2 | outputs 3 | test_run_dir 4 | target 5 | project/target 6 | *.key 7 | *.log 8 | *.swp 9 | .ivy2 10 | VTile 11 | dump.vcd* 12 | DVEfiles 13 | riscv-tools-priv1.7 14 | tests/32/* 15 | tests/64/* 16 | 17 | # Scala IDEs 18 | .project 19 | .classpath 20 | .settings 21 | .idea 22 | *.iml 23 | /*.bsp/ 24 | 25 | # Visual Studio Code 26 | .bloop/ 27 | .metals/ 28 | .vscode/ 29 | 30 | # Synopsys Verdi 31 | novas_dump.log 32 | ucli.key 33 | 34 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/riscv-mini/3eda724c437c73f3192fcbaaf76ae93b5eb870b0/.gitmodules -------------------------------------------------------------------------------- /.install_verilator.sh: -------------------------------------------------------------------------------- 1 | set -e 2 | # Install Verilator (http://www.veripool.org/projects/verilator/wiki/Installing) 3 | if [ ! -f $INSTALL_DIR/bin/verilator ]; then 4 | mkdir -p $INSTALL_DIR 5 | git clone https://git.veripool.org/git/verilator 6 | unset VERILATOR_ROOT 7 | cd verilator 8 | git config pull.ff only 9 | git pull 10 | git checkout v3.922 11 | autoconf 12 | ./configure --prefix=$INSTALL_DIR 13 | make 14 | make install 15 | export VERILATOR_ROOT=$INSTALL_DIR 16 | # Fix verilator for local install (http://www.lowrisc.org/docs/untether-v0.2/verilator/) 17 | ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include 18 | ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer 19 | fi 20 | -------------------------------------------------------------------------------- /.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 2.6.4 2 | 3 | maxColumn = 120 4 | align = most 5 | continuationIndent.defnSite = 2 6 | assumeStandardLibraryStripMargin = true 7 | docstrings = ScalaDoc 8 | lineEndings = preserve 9 | includeCurlyBraceInSelectChains = false 10 | danglingParentheses = true 11 | 12 | align.tokens.add = [ 13 | { 14 | code = ":" 15 | } 16 | ] 17 | 18 | newlines.alwaysBeforeCurlyBraceLambdaParams = false 19 | newlines.alwaysBeforeMultilineDef = false 20 | newlines.implicitParamListModifierForce = [before] 21 | 22 | verticalMultiline.atDefnSite = true 23 | 24 | optIn.annotationNewlines = true 25 | 26 | rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix] 27 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2017, The Regents of the University of California (Regents) 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | * Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | * Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | * Neither the name of the Regents nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | default: compile 2 | 3 | base_dir = $(abspath .) 4 | src_dir = $(base_dir)/src/main 5 | gen_dir = $(base_dir)/generated-src 6 | out_dir = $(base_dir)/outputs 7 | threads ?= 1 8 | 9 | SBT = sbt 10 | SBT_FLAGS = -ivy $(base_dir)/.ivy2 11 | 12 | sbt: 13 | $(SBT) $(SBT_FLAGS) 14 | 15 | compile: $(gen_dir)/Tile.sv 16 | 17 | $(gen_dir)/Tile.sv: $(wildcard $(src_dir)/scala/*.scala) 18 | $(SBT) $(SBT_FLAGS) "run --target-dir=$(gen_dir) --dump-fir" 19 | 20 | CXXFLAGS += -std=c++14 -Wall -Wno-unused-variable 21 | 22 | # compile verilator 23 | VERILATOR = verilator --cc --exe 24 | VERILATOR_FLAGS = --assert -Wno-STMTDLY -O3 --trace --threads $(threads)\ 25 | --top-module Tile -Mdir $(gen_dir)/VTile.csrc \ 26 | -CFLAGS "$(CXXFLAGS) -include $(gen_dir)/VTile.csrc/VTile.h" 27 | 28 | $(base_dir)/VTile: $(gen_dir)/Tile.sv $(src_dir)/cc/top.cc $(src_dir)/cc/mm.cc $(src_dir)/cc/mm.h 29 | $(VERILATOR) $(VERILATOR_FLAGS) -o $@ $< $(word 2, $^) $(word 3, $^) 30 | $(MAKE) -C $(gen_dir)/VTile.csrc -f VTile.mk 31 | 32 | verilator: $(base_dir)/VTile 33 | 34 | # isa tests + benchmarks with verilator 35 | test_hex_files = $(wildcard $(base_dir)/tests/*.hex) 36 | test_out_files = $(foreach f,$(test_hex_files),$(patsubst %.hex,%.out,$(out_dir)/$(notdir $f))) 37 | 38 | $(test_out_files): $(out_dir)/%.out: $(base_dir)/VTile $(base_dir)/tests/%.hex 39 | mkdir -p $(out_dir) 40 | $^ $(patsubst %.out,%.vcd,$@) 2> $@ 41 | 42 | run-tests: $(test_out_files) 43 | 44 | # run custom benchamrk 45 | custom_bmark_hex ?= $(base_dir)/custom-bmark/main.hex 46 | custom_bmark_out = $(patsubst %.hex,%.out,$(out_dir)/$(notdir $(custom_bmark_hex))) 47 | $(custom_bmark_hex): 48 | $(MAKE) -C custom-bmark 49 | 50 | $(custom_bmark_out): $(base_dir)/VTile $(custom_bmark_hex) 51 | mkdir -p $(out_dir) 52 | $^ $(patsubst %.out,%.vcd,$@) 2> $@ 53 | 54 | run-custom-bmark: $(custom_bmark_out) 55 | 56 | # unit tests + integration tests 57 | test: 58 | $(SBT) $(SBT_FLAGS) test 59 | 60 | # Only runs tests that failed in the previous run 61 | test-quick: 62 | $(SBT) $(SBT_FLAGS) testQuick 63 | 64 | clean: 65 | rm -rf $(gen_dir) $(out_dir) test_run_dir 66 | 67 | cleanall: clean 68 | rm -rf target project/target 69 | 70 | .PHONY: sbt compile verilator run-tests run-custom-bmark test test-quick clean cleanall 71 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # riscv-mini 2 | 3 | Author: Donggyu Kim (dgkim@eecs.berkeley.edu) 4 | 5 | `riscv-mini` is a simple RISC-V 3-stage pipeline written in Chisel. It has been a crucial example in various project developments, 6 | including [Chisel3](https://github.com/ucb-bar/chisel3.git), [FIRRTL](https://github.com/ucb-bar/firrtl.git), 7 | [Strober](https://bar.eecs.berkeley.edu/projects/strober.html), simulation and verification methodologies. 8 | It implements RV32I of the User-level ISA Version 2.0 and the Machine-level ISA of the Privileged Architecture Version 1.7. 9 | Unlike other simple pipelines, it also contains simple instruction and data caches. 10 | 11 | Note that a real-world processor is not the goal of `riscv-mini`. 12 | It is developed as an intermediate example before diving into [rocket-chip](https://github.com/freechipsproject/rocket-chip). 13 | 14 | ## Datapath Diagram 15 | ![pipeline](diagram.png) 16 | 17 | ## Getting Started 18 | 19 | $ git clone https://github.com/ucb-bar/riscv-mini.git 20 | $ cd riscv-mini 21 | $ make # generate firrtl & verilog files in generated-src 22 | 23 | The verilog output file can be used for verilator simulation or the ASIC tool flow. 24 | 25 | ## Running Verilator Simulation 26 | 27 | First, generate the verilator binary: 28 | 29 | $ make verilator 30 | 31 | This will generate `VTile` in the top-level directory. 32 | 33 | Now, you can run verilator simulation for a given hex file as follows: 34 | 35 | $ ./VTile [ 2> ] 36 | 37 | `` and the pipe to `` are optional. The waveform is dumped to `dump.vcd` and the execution trace is printed in the screen by default. 38 | 39 | The following command runs the whole test hex files in verilator and dumps the traces and the waveforms to the 'outputs' directory: 40 | 41 | $ make run-tests 42 | 43 | ## Unit and Integration Tests with `sbt` 44 | 45 | `riscv-mini` provides synthesizable unit & integration tests. 46 | Theres are six sets of unit tests(`ALUTests`, `BrCondTests`, `ImmGenTests`, `CSRTests`, `CacheTests`, `DatapathTests`), 47 | running user-defined test vectors. 48 | To execute them, first launch sbt with `make sbt` and run: 49 | 50 | > testOnly mini.[testname] 51 | 52 | There are also six sets of integration tests, running the hex files from [riscv-tests](https://github.com/riscv/riscv-tests). 53 | To execute them, also launch `sbt` and run: 54 | 55 | > testOnly mini.[Core|Tile][Simple|ISA|Bmark]Tests 56 | 57 | `Core` only contains the datapath and the control unit, while `Tile` also contains I$ and D$. `Simple` only runs `rv32ui-p-simple`, 58 | `ISA` runs the whole ISA tests, and `Bmark` runs five benchmarks(`median`, `multiply`, `qsort`, `towers`, `vvadd`). 59 | Note that all tests in a set run in parallel. 60 | 61 | Finally, to run all the tests, just in sbt: 62 | 63 | > test 64 | 65 | ## Running Your Own Program on `riscv-mini` 66 | 67 | At this point, you may want to implement and exeucte your custom application on `riscv-mini`. In this case, you need to install RISC-V tools for priv 1.7. This repo provides a script to install the correct version of tools. Run the script as follows: 68 | 69 | $ export RISCV= 70 | $ ./build-riscv-tools 71 | 72 | It takes a while to install the toolchain, so please be patient. 73 | 74 | This repo also provides a template for your own program in `custom-bmark`. Add your c or assembly code and edit `Makefile`. Next, to compile you program, run `make` in `custom-bmark` to generate the binary, dump, and the hex files. Finally, run the following command in the base directory: 75 | 76 | $ make run-custom-bmark 77 | -------------------------------------------------------------------------------- /build-riscv-tools.sh: -------------------------------------------------------------------------------- 1 | # Fetch tools for priv 1.7 2 | git clone -n https://github.com/riscv/riscv-tools.git riscv-tools-priv1.7 3 | cd riscv-tools-priv1.7 4 | git checkout 4635ab67966c763a84f7217bc2c20b65dcabc7ec 5 | git submodule update --init riscv-fesvr 6 | git submodule update --init --recursive riscv-gnu-toolchain 7 | git submodule update --init --recursive riscv-tests 8 | 9 | # Build priv 1.7 RISC-V tools 10 | source build.common 11 | 12 | echo "Starting RISC-V Toolchain build process" 13 | 14 | build_project riscv-fesvr --prefix=$RISCV 15 | build_project riscv-gnu-toolchain --prefix=$RISCV --with-xlen=32 16 | $MAKE -C riscv-tests/isa RISCV_PREFIX=riscv32-unknown-elf- XLEN=32 17 | $MAKE -C riscv-tests/benchmarks RISCV_PREFIX=riscv32-unknown-elf- XLEN=32 18 | -------------------------------------------------------------------------------- /build.sbt: -------------------------------------------------------------------------------- 1 | ThisBuild / scalaVersion := "2.13.7" 2 | ThisBuild / version := "2.5.0" 3 | ThisBuild / organization := "edu.berkeley.cs" 4 | 5 | val chiselVersion = "6.2.0" 6 | val chiseltestVersion = "6.0.0" 7 | 8 | lazy val root = (project in file(".")) 9 | .settings( 10 | name := "riscv-mini", 11 | libraryDependencies ++= Seq( 12 | "org.chipsalliance" %% "chisel" % chiselVersion, 13 | "edu.berkeley.cs" %% "chiseltest" % chiseltestVersion % "test" 14 | ), 15 | scalacOptions ++= Seq( 16 | "-language:reflectiveCalls", 17 | "-deprecation", 18 | "-feature", 19 | "-Xcheckinit", 20 | ), 21 | addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full), 22 | ) 23 | -------------------------------------------------------------------------------- /custom-bmark/.gitignore: -------------------------------------------------------------------------------- 1 | main 2 | *.o 3 | *.hex 4 | *.dump 5 | -------------------------------------------------------------------------------- /custom-bmark/Makefile: -------------------------------------------------------------------------------- 1 | base_dir = $(abspath ..) 2 | 3 | # For custom benchmarks 4 | RISCV_TEST_DIR ?= $(base_dir)/riscv-tools-priv1.7/riscv-tests 5 | CUSTOM_BMARK_BIN ?= main 6 | CUSTOM_BMARK_C_SRC ?= main.c syscalls.c 7 | CUSTOM_BMARK_S_SRC ?= add.S crt.S 8 | 9 | CUSTOM_BMARK_OBJS := \ 10 | $(foreach f,$(CUSTOM_BMARK_C_SRC),$(patsubst %.c,%.o,$f)) \ 11 | $(foreach f,$(CUSTOM_BMARK_S_SRC),$(patsubst %.S,%.o,$f)) 12 | 13 | riscv_bmark_dir = $(RISCV_TEST_DIR)/benchmarks 14 | 15 | RISCV_GCC = riscv32-unknown-elf-gcc 16 | RISCV_CFLAGS = -static -std=gnu99 -fno-common -fno-builtin-printf \ 17 | -I$(RISCV_TEST_DIR)/env -I$(RISCV_TEST_DIR)/benchmarks/common 18 | RISCV_LDFLAGS = -T $(RISCV_TEST_DIR)/benchmarks/common/test.ld \ 19 | -I$(RISCV_TEST_DIR)/env -I$(RISCV_TEST_DIR)/benchmarks/common 20 | 21 | VPATH += $(RISCV_TEST_DIR)/benchmarks/common 22 | 23 | all: $(CUSTOM_BMARK_BIN) $(CUSTOM_BMARK_BIN).hex $(CUSTOM_BMARK_BIN).dump 24 | 25 | %.o: %.c 26 | $(RISCV_GCC) $(RISCV_CFLAGS) -c -o $@ $< 27 | 28 | %.o: %.S 29 | $(RISCV_GCC) $(RISCV_CFLAGS) -D__ASSEMBLY__=1 -c -o $@ $< 30 | 31 | $(CUSTOM_BMARK_BIN): $(CUSTOM_BMARK_OBJS) 32 | $(RISCV_GCC) $(RISCV_LDFLAGS) -o $@ $^ -nostdlib -nostartfiles -lc -lgcc 33 | 34 | %.hex: % 35 | elf2hex 16 32768 $< > $@ 36 | 37 | %.dump: % 38 | riscv32-unknown-elf-objdump \ 39 | --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data \ 40 | $< > $@ 41 | 42 | clean: 43 | rm -rf *.o $(CUSTOM_BMARK_BIN) $(CUSTOM_BMARK_BIN).hex $(CUSTOM_BMARK_BIN).dump 44 | 45 | .PHONY: all clean 46 | -------------------------------------------------------------------------------- /custom-bmark/add.S: -------------------------------------------------------------------------------- 1 | .text 2 | .align 2 3 | 4 | .globl add 5 | .type add,@function 6 | 7 | add: 8 | add a0, a0, a1 9 | ret 10 | -------------------------------------------------------------------------------- /custom-bmark/main.c: -------------------------------------------------------------------------------- 1 | int add(int a, int b); 2 | 3 | int main(int argc, char** argv) { 4 | int res = add(3, 2); 5 | return res == 5 ? 0 : -1; 6 | } 7 | -------------------------------------------------------------------------------- /diagram.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/riscv-mini/3eda724c437c73f3192fcbaaf76ae93b5eb870b0/diagram.pdf -------------------------------------------------------------------------------- /diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ucb-bar/riscv-mini/3eda724c437c73f3192fcbaaf76ae93b5eb870b0/diagram.png -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.8.2 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.5") 2 | 3 | -------------------------------------------------------------------------------- /src/main/cc/mm.cc: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #include "mm.h" 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | mm_magic_t::mm_magic_t(size_t size, size_t word_size): 12 | data(new char[size]), 13 | size(size), 14 | word_size(word_size), 15 | store_inflight(false) 16 | { 17 | dummy_data.resize(word_size); 18 | } 19 | 20 | mm_magic_t::~mm_magic_t() 21 | { 22 | delete [] data; 23 | } 24 | 25 | void mm_magic_t::write(uint64_t addr, char *data) { 26 | addr %= this->size; 27 | 28 | char* base = this->data + addr; 29 | memcpy(base, data, word_size); 30 | } 31 | 32 | void mm_magic_t::write(uint64_t addr, char *data, uint64_t strb, uint64_t size) 33 | { 34 | strb &= ((1L << size) - 1) << (addr % word_size); 35 | addr %= this->size; 36 | 37 | char *base = this->data + addr; 38 | for (int i = 0; i < word_size; i++) { 39 | if (strb & 1) base[i] = data[i]; 40 | strb >>= 1; 41 | } 42 | } 43 | 44 | std::vector mm_magic_t::read(uint64_t addr) 45 | { 46 | addr %= this->size; 47 | 48 | char *base = this->data + addr; 49 | return std::vector(base, base + word_size); 50 | } 51 | 52 | void mm_magic_t::tick( 53 | bool reset, 54 | bool ar_valid, 55 | uint64_t ar_addr, 56 | uint64_t ar_id, 57 | uint64_t ar_size, 58 | uint64_t ar_len, 59 | 60 | bool aw_valid, 61 | uint64_t aw_addr, 62 | uint64_t aw_id, 63 | uint64_t aw_size, 64 | uint64_t aw_len, 65 | 66 | bool w_valid, 67 | uint64_t w_strb, 68 | void *w_data, 69 | bool w_last, 70 | 71 | bool r_ready, 72 | bool b_ready) 73 | { 74 | bool ar_fire = !reset && ar_valid && ar_ready(); 75 | bool aw_fire = !reset && aw_valid && aw_ready(); 76 | bool w_fire = !reset && w_valid && w_ready(); 77 | bool r_fire = !reset && r_valid() && r_ready; 78 | bool b_fire = !reset && b_valid() && b_ready; 79 | 80 | if (ar_fire) { 81 | uint64_t start_addr = (ar_addr / word_size) * word_size; 82 | for (size_t i = 0; i <= ar_len; i++) { 83 | auto dat = read(start_addr + i * word_size); 84 | rresp.push(mm_rresp_t(ar_id, dat, i == ar_len)); 85 | } 86 | } 87 | 88 | if (aw_fire) { 89 | store_addr = aw_addr; 90 | store_id = aw_id; 91 | store_count = aw_len + 1; 92 | store_size = 1 << aw_size; 93 | store_inflight = true; 94 | } 95 | 96 | if (w_fire) { 97 | write(store_addr, (char*)w_data, w_strb, store_size); 98 | store_addr += store_size; 99 | store_count--; 100 | 101 | if (store_count == 0) { 102 | store_inflight = false; 103 | bresp.push(store_id); 104 | assert(w_last); 105 | } 106 | } 107 | 108 | if (b_fire) 109 | bresp.pop(); 110 | 111 | if (r_fire) 112 | rresp.pop(); 113 | 114 | cycle++; 115 | 116 | if (reset) { 117 | while (!bresp.empty()) bresp.pop(); 118 | while (!rresp.empty()) rresp.pop(); 119 | cycle = 0; 120 | } 121 | } 122 | 123 | void load_mem(char* mem, const char* fn) 124 | { 125 | int start = 0; 126 | std::ifstream in(fn); 127 | if (!in) 128 | { 129 | std::cerr << "could not open " << fn << std::endl; 130 | exit(EXIT_FAILURE); 131 | } 132 | 133 | std::string line; 134 | while (std::getline(in, line)) 135 | { 136 | #define parse_nibble(c) ((c) >= 'a' ? (c)-'a'+10 : (c)-'0') 137 | for (int i = line.length()-2, j = 0; i >= 0; i -= 2, j++) { 138 | mem[start + j] = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]); 139 | } 140 | start += line.length()/2; 141 | } 142 | } 143 | -------------------------------------------------------------------------------- /src/main/cc/mm.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef MM_EMULATOR_H 4 | #define MM_EMULATOR_H 5 | 6 | #include 7 | #include 8 | #include 9 | 10 | struct mm_rresp_t 11 | { 12 | uint64_t id; 13 | std::vector data; 14 | bool last; 15 | 16 | mm_rresp_t(uint64_t id, std::vector data, bool last) 17 | { 18 | this->id = id; 19 | this->data = data; 20 | this->last = last; 21 | } 22 | 23 | mm_rresp_t() 24 | { 25 | this->id = 0; 26 | this->last = false; 27 | } 28 | }; 29 | 30 | class mm_magic_t 31 | { 32 | public: 33 | mm_magic_t(size_t size, size_t word_size); 34 | ~mm_magic_t(); 35 | void init(size_t sz, int word_size); 36 | char* get_data() { return data; } 37 | size_t get_size() { return size; } 38 | 39 | bool ar_ready() { return true; } 40 | bool aw_ready() { return !store_inflight; } 41 | bool w_ready() { return store_inflight; } 42 | bool b_valid() { return !bresp.empty(); } 43 | uint64_t b_resp() { return 0; } 44 | uint64_t b_id() { return b_valid() ? bresp.front() : 0; } 45 | bool r_valid() { return !rresp.empty(); } 46 | uint64_t r_resp() { return 0; } 47 | uint64_t r_id() { return r_valid() ? rresp.front().id: 0; } 48 | void *r_data() { return r_valid() ? &rresp.front().data[0] : &dummy_data[0]; } 49 | bool r_last() { return r_valid() ? rresp.front().last : false; } 50 | 51 | void tick 52 | ( 53 | bool reset, 54 | 55 | bool ar_valid, 56 | uint64_t ar_addr, 57 | uint64_t ar_id, 58 | uint64_t ar_size, 59 | uint64_t ar_len, 60 | 61 | bool aw_valid, 62 | uint64_t aw_addr, 63 | uint64_t aw_id, 64 | uint64_t aw_size, 65 | uint64_t aw_len, 66 | 67 | bool w_valid, 68 | uint64_t w_strb, 69 | void *w_data, 70 | bool w_last, 71 | 72 | bool r_ready, 73 | bool b_ready 74 | ); 75 | 76 | void write(uint64_t addr, char *data); 77 | void write(uint64_t addr, char *data, uint64_t strb, uint64_t size); 78 | std::vector read(uint64_t addr); 79 | 80 | private: 81 | char* data; 82 | size_t size; 83 | size_t word_size; 84 | 85 | bool store_inflight; 86 | uint64_t store_addr; 87 | uint64_t store_id; 88 | uint64_t store_size; 89 | uint64_t store_count; 90 | std::vector dummy_data; 91 | std::queue bresp; 92 | 93 | std::queue rresp; 94 | 95 | uint64_t cycle; 96 | }; 97 | 98 | void load_mem(char* mem, const char* fn); 99 | #endif 100 | -------------------------------------------------------------------------------- /src/main/cc/top.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #if VM_TRACE 5 | # include // Trace file format header 6 | #endif 7 | 8 | #include "mm.h" 9 | 10 | using namespace std; 11 | 12 | vluint64_t main_time = 0; // Current simulation time 13 | // This is a 64-bit integer to reduce wrap over issues and 14 | // allow modulus. You can also use a double, if you wish. 15 | 16 | double sc_time_stamp () { // Called by $time in Verilog 17 | return main_time; // converts to double, to match 18 | // what SystemC does 19 | } 20 | 21 | VTile* top; // target design 22 | #ifdef VM_TRACE 23 | VerilatedVcdC* tfp; 24 | #endif 25 | mm_magic_t* mem; // target memory 26 | 27 | // TODO Provide command-line options like vcd filename, timeout count, etc. 28 | const long timeout = 100000000L; 29 | 30 | void tick() { 31 | top->clock = 1; 32 | top->eval(); 33 | #if VM_TRACE 34 | if (tfp) tfp->dump((double) main_time); 35 | #endif // VM_TRACE 36 | main_time++; 37 | 38 | top->io_nasti_aw_ready = mem->aw_ready(); 39 | top->io_nasti_ar_ready = mem->ar_ready(); 40 | top->io_nasti_w_ready = mem->w_ready(); 41 | top->io_nasti_b_valid = mem->b_valid(); 42 | top->io_nasti_b_bits_id = mem->b_id(); 43 | top->io_nasti_b_bits_resp = mem->b_resp(); 44 | top->io_nasti_r_valid = mem->r_valid(); 45 | top->io_nasti_r_bits_id = mem->r_id(); 46 | top->io_nasti_r_bits_resp = mem->r_resp(); 47 | top->io_nasti_r_bits_last = mem->r_last(); 48 | memcpy(&top->io_nasti_r_bits_data, mem->r_data(), 8); 49 | 50 | mem->tick( 51 | top->reset, 52 | top->io_nasti_ar_valid, 53 | top->io_nasti_ar_bits_addr, 54 | top->io_nasti_ar_bits_id, 55 | top->io_nasti_ar_bits_size, 56 | top->io_nasti_ar_bits_len, 57 | 58 | top->io_nasti_aw_valid, 59 | top->io_nasti_aw_bits_addr, 60 | top->io_nasti_aw_bits_id, 61 | top->io_nasti_aw_bits_size, 62 | top->io_nasti_aw_bits_len, 63 | 64 | top->io_nasti_w_valid, 65 | top->io_nasti_w_bits_strb, 66 | &top->io_nasti_w_bits_data, 67 | top->io_nasti_w_bits_last, 68 | 69 | top->io_nasti_r_ready, 70 | top->io_nasti_b_ready 71 | ); 72 | 73 | top->clock = 0; 74 | top->eval(); 75 | #if VM_TRACE 76 | if (tfp) tfp->dump((double) main_time); 77 | #endif // VM_TRACE 78 | main_time++; 79 | } 80 | 81 | int main(int argc, char** argv) { 82 | Verilated::commandArgs(argc, argv); // Remember args 83 | top = new VTile; // target design 84 | mem = new mm_magic_t(1L << 32, 8); // target memory 85 | load_mem(mem->get_data(), (const char*)(argv[1])); // load hex 86 | 87 | #if VM_TRACE // If verilator was invoked with --trace 88 | Verilated::traceEverOn(true); // Verilator must compute traced signals 89 | VL_PRINTF("Enabling waves...\n"); 90 | tfp = new VerilatedVcdC; 91 | top->trace(tfp, 99); // Trace 99 levels of hierarchy 92 | tfp->open(argc > 2 ? argv[2] : "dump.vcd"); // Open the dump file 93 | #endif 94 | 95 | cout << "Starting simulation!\n"; 96 | 97 | // reset 98 | top->reset = 1; 99 | for (size_t i = 0; i < 5 ; i++) { 100 | tick(); 101 | } 102 | 103 | // start 104 | top->reset = 0; 105 | top->io_host_fromhost_bits = 0; 106 | top->io_host_fromhost_valid = 0; 107 | do { 108 | tick(); 109 | } while(!top->io_host_tohost && main_time < timeout); 110 | 111 | int retcode = top->io_host_tohost >> 1; 112 | 113 | // Run for 10 more clocks 114 | for (size_t i = 0 ; i < 10 ; i++) { 115 | tick(); 116 | } 117 | 118 | if (main_time >= timeout) { 119 | cerr << "Simulation terminated by timeout at time " << main_time 120 | << " (cycle " << main_time / 10 << ")"<< endl; 121 | return EXIT_FAILURE; 122 | } else { 123 | cerr << "Simulation completed at time " << main_time << 124 | " (cycle " << main_time / 10 << ")"<< endl; 125 | if (retcode) { 126 | cerr << "TOHOST = " << retcode << endl; 127 | } 128 | } 129 | 130 | #if VM_TRACE 131 | if (tfp) tfp->close(); 132 | delete tfp; 133 | #endif 134 | delete top; 135 | delete mem; 136 | 137 | cout << "Finishing simulation!\n"; 138 | 139 | return retcode == 0 ? EXIT_SUCCESS : EXIT_FAILURE; 140 | } 141 | 142 | -------------------------------------------------------------------------------- /src/main/scala/junctions/nasti.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE.Berkeley for license details. 2 | // See LICENSE.SiFive for license details. 3 | 4 | package junctions 5 | import chisel3._ 6 | import chisel3.util._ 7 | 8 | object NastiConstants { 9 | // These are all fixed by the standard: 10 | val LenBits = 8 11 | val SizeBits = 3 12 | val BurstBits = 2 13 | val LockBits = 1 14 | val CacheBits = 4 15 | val ProtBits = 3 16 | val QosBits = 4 17 | val RespBits = 2 18 | 19 | def CacheReadAllocate = 8.U(CacheBits.W) 20 | def CacheWriteAllocate = 4.U(CacheBits.W) 21 | def CacheModifiable = 2.U(CacheBits.W) 22 | def CacheBufferable = 1.U(CacheBits.W) 23 | 24 | def ProtPrivileged = 1.U(ProtBits.W) 25 | def ProtInsecure = 2.U(ProtBits.W) 26 | def ProtInstruction = 4.U(ProtBits.W) 27 | 28 | def BurstFixed = 0.U(BurstBits.W) 29 | def BurstIncr = 1.U(BurstBits.W) 30 | def BurstWrap = 2.U(BurstBits.W) 31 | 32 | def RespOkay = 0.U(RespBits.W) 33 | def RespExOkay = 1.U(RespBits.W) 34 | def RespSlvErr = 2.U(RespBits.W) 35 | def RespDevErr = 3.U(RespBits.W) 36 | } 37 | 38 | case class NastiBundleParameters( 39 | addrBits: Int, 40 | dataBits: Int, 41 | idBits: Int) { 42 | require(dataBits >= 8, s"AXI4 data bits must be >= 8 (got $dataBits)") 43 | require(addrBits >= 1, s"AXI4 addr bits must be >= 1 (got $addrBits)") 44 | require(idBits >= 1, s"AXI4 id bits must be >= 1 (got $idBits)") 45 | require(isPow2(dataBits), s"AXI4 data bits must be pow2 (got $dataBits)") 46 | } 47 | 48 | /** aka the AW/AR channel */ 49 | class NastiAddressBundle(params: NastiBundleParameters) extends Bundle { 50 | val id = UInt(params.idBits.W) 51 | val addr = UInt(params.addrBits.W) 52 | val len = UInt(NastiConstants.LenBits.W) // number of beats - 1 53 | val size = UInt(NastiConstants.SizeBits.W) // bytes in beat = 2^size 54 | val burst = UInt(NastiConstants.BurstBits.W) 55 | val lock = UInt(NastiConstants.LockBits.W) 56 | val cache = UInt(NastiConstants.CacheBits.W) 57 | val prot = UInt(NastiConstants.ProtBits.W) 58 | val qos = UInt(NastiConstants.QosBits.W) // 0=no QoS, bigger = higher priority 59 | } 60 | 61 | object NastiAddressBundle { 62 | def apply(params: NastiBundleParameters)(id: UInt, addr: UInt, size: UInt, len: UInt = 0.U): NastiAddressBundle = { 63 | val aw = Wire(new NastiAddressBundle(params)) 64 | aw.id := id 65 | aw.addr := addr 66 | aw.len := len 67 | aw.size := size 68 | aw.burst := NastiConstants.BurstIncr 69 | aw.lock := false.B 70 | aw.cache := 0.U 71 | aw.prot := 0.U 72 | aw.qos := 0.U 73 | aw 74 | } 75 | } 76 | 77 | /** aka the W-channel */ 78 | class NastiWriteDataBundle(params: NastiBundleParameters) extends Bundle { 79 | // id removed 80 | val data = UInt(params.dataBits.W) 81 | val strb = UInt((params.dataBits / 8).W) 82 | val last = Bool() 83 | } 84 | 85 | object NastiWriteDataBundle { 86 | def apply( 87 | params: NastiBundleParameters 88 | )(data: UInt, 89 | strb: Option[UInt] = None, 90 | last: Bool = true.B 91 | ): NastiWriteDataBundle = { 92 | val w = Wire(new NastiWriteDataBundle(params)) 93 | w.strb := strb.getOrElse(Fill(params.dataBits / 8, 1.U)) 94 | w.data := data 95 | w.last := last 96 | w 97 | } 98 | } 99 | 100 | /** aka the R-channel */ 101 | class NastiReadDataBundle(params: NastiBundleParameters) extends Bundle { 102 | val id = UInt(params.idBits.W) 103 | val data = UInt(params.dataBits.W) 104 | val resp = UInt(NastiConstants.RespBits.W) 105 | val last = Bool() 106 | } 107 | 108 | object NastiReadDataBundle { 109 | def apply( 110 | params: NastiBundleParameters 111 | )(id: UInt, 112 | data: UInt, 113 | last: Bool = true.B, 114 | resp: UInt = 0.U 115 | ): NastiReadDataBundle = { 116 | val r = Wire(new NastiReadDataBundle(params)) 117 | r.id := id 118 | r.data := data 119 | r.last := last 120 | r.resp := resp 121 | r 122 | } 123 | } 124 | 125 | /** aka the B-channel */ 126 | class NastiWriteResponseBundle(params: NastiBundleParameters) extends Bundle { 127 | val id = UInt(params.idBits.W) 128 | val resp = UInt(NastiConstants.RespBits.W) 129 | } 130 | 131 | object NastiWriteResponseBundle { 132 | def apply(params: NastiBundleParameters)(id: UInt, resp: UInt = 0.U): NastiWriteResponseBundle = { 133 | val b = Wire(new NastiWriteResponseBundle(params)) 134 | b.id := id 135 | b.resp := resp 136 | b 137 | } 138 | } 139 | 140 | class NastiBundle(params: NastiBundleParameters) extends Bundle { 141 | val aw = Decoupled(new NastiAddressBundle(params)) 142 | val w = Decoupled(new NastiWriteDataBundle(params)) 143 | val b = Flipped(Decoupled(new NastiWriteResponseBundle(params))) 144 | val ar = Decoupled(new NastiAddressBundle(params)) 145 | val r = Flipped(Decoupled(new NastiReadDataBundle(params))) 146 | } 147 | 148 | class NastiArbiterIO(params: NastiBundleParameters, arbN: Int) extends Bundle { 149 | val master = Flipped(Vec(arbN, new NastiBundle(params))) 150 | val slave = new NastiBundle(params) 151 | } 152 | 153 | /** Arbitrate among arbN masters requesting to a single slave */ 154 | class NastiArbiter(params: NastiBundleParameters, val arbN: Int) extends Module { 155 | val io = new NastiArbiterIO(params, arbN) 156 | 157 | if (arbN > 1) { 158 | val arbIdBits = log2Up(arbN) 159 | 160 | val ar_arb = Module(new RRArbiter(new NastiAddressBundle(params), arbN)) 161 | val aw_arb = Module(new RRArbiter(new NastiAddressBundle(params), arbN)) 162 | 163 | val slave_r_arb_id = io.slave.r.bits.id(arbIdBits - 1, 0) 164 | val slave_b_arb_id = io.slave.b.bits.id(arbIdBits - 1, 0) 165 | 166 | val w_chosen = Reg(UInt(arbIdBits.W)) 167 | val w_done = RegInit(true.B) 168 | 169 | when(aw_arb.io.out.fire) { 170 | w_chosen := aw_arb.io.chosen 171 | w_done := false.B 172 | } 173 | 174 | when(io.slave.w.fire && io.slave.w.bits.last) { 175 | w_done := true.B 176 | } 177 | 178 | for (i <- 0 until arbN) { 179 | val m_ar = io.master(i).ar 180 | val m_aw = io.master(i).aw 181 | val m_r = io.master(i).r 182 | val m_b = io.master(i).b 183 | val a_ar = ar_arb.io.in(i) 184 | val a_aw = aw_arb.io.in(i) 185 | val m_w = io.master(i).w 186 | 187 | a_ar <> m_ar 188 | a_aw <> m_aw 189 | 190 | m_r.valid := io.slave.r.valid && slave_r_arb_id === i.U 191 | m_r.bits := io.slave.r.bits 192 | m_r.bits.id := io.slave.r.bits.id >> arbIdBits.U 193 | 194 | m_b.valid := io.slave.b.valid && slave_b_arb_id === i.U 195 | m_b.bits := io.slave.b.bits 196 | m_b.bits.id := io.slave.b.bits.id >> arbIdBits.U 197 | 198 | m_w.ready := io.slave.w.ready && w_chosen === i.U && !w_done 199 | } 200 | 201 | io.slave.r.ready := io.master(slave_r_arb_id).r.ready 202 | io.slave.b.ready := io.master(slave_b_arb_id).b.ready 203 | 204 | io.slave.w.bits := io.master(w_chosen).w.bits 205 | io.slave.w.valid := io.master(w_chosen).w.valid && !w_done 206 | 207 | io.slave.ar <> ar_arb.io.out 208 | 209 | io.slave.aw.bits <> aw_arb.io.out.bits 210 | io.slave.aw.valid := aw_arb.io.out.valid && w_done 211 | aw_arb.io.out.ready := io.slave.aw.ready && w_done 212 | 213 | } else { io.slave <> io.master.head } 214 | } 215 | -------------------------------------------------------------------------------- /src/main/scala/mini/Alu.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | 8 | object Alu { 9 | val ALU_ADD = 0.U(4.W) 10 | val ALU_SUB = 1.U(4.W) 11 | val ALU_AND = 2.U(4.W) 12 | val ALU_OR = 3.U(4.W) 13 | val ALU_XOR = 4.U(4.W) 14 | val ALU_SLT = 5.U(4.W) 15 | val ALU_SLL = 6.U(4.W) 16 | val ALU_SLTU = 7.U(4.W) 17 | val ALU_SRL = 8.U(4.W) 18 | val ALU_SRA = 9.U(4.W) 19 | val ALU_COPY_A = 10.U(4.W) 20 | val ALU_COPY_B = 11.U(4.W) 21 | val ALU_XXX = 15.U(4.W) 22 | } 23 | 24 | class AluIO(width: Int) extends Bundle { 25 | val A = Input(UInt(width.W)) 26 | val B = Input(UInt(width.W)) 27 | val alu_op = Input(UInt(4.W)) 28 | val out = Output(UInt(width.W)) 29 | val sum = Output(UInt(width.W)) 30 | } 31 | 32 | import mini.Alu._ 33 | 34 | trait Alu extends Module { 35 | def width: Int 36 | val io: AluIO 37 | } 38 | 39 | class AluSimple(val width: Int) extends Alu { 40 | val io = IO(new AluIO(width)) 41 | 42 | val shamt = io.B(4, 0).asUInt 43 | 44 | io.out := MuxLookup(io.alu_op, io.B)( 45 | Seq( 46 | ALU_ADD -> (io.A + io.B), 47 | ALU_SUB -> (io.A - io.B), 48 | ALU_SRA -> (io.A.asSInt >> shamt).asUInt, 49 | ALU_SRL -> (io.A >> shamt), 50 | ALU_SLL -> (io.A << shamt), 51 | ALU_SLT -> (io.A.asSInt < io.B.asSInt), 52 | ALU_SLTU -> (io.A < io.B), 53 | ALU_AND -> (io.A & io.B), 54 | ALU_OR -> (io.A | io.B), 55 | ALU_XOR -> (io.A ^ io.B), 56 | ALU_COPY_A -> io.A 57 | ) 58 | ) 59 | 60 | io.sum := io.A + Mux(io.alu_op(0), -io.B, io.B) 61 | } 62 | 63 | class AluArea(val width: Int) extends Alu { 64 | val io = IO(new AluIO(width)) 65 | val sum = io.A + Mux(io.alu_op(0), -io.B, io.B) 66 | val cmp = 67 | Mux(io.A(width - 1) === io.B(width - 1), sum(width - 1), Mux(io.alu_op(1), io.B(width - 1), io.A(width - 1))) 68 | val shamt = io.B(4, 0).asUInt 69 | val shin = Mux(io.alu_op(3), io.A, Reverse(io.A)) 70 | val shiftr = (Cat(io.alu_op(0) && shin(width - 1), shin).asSInt >> shamt)(width - 1, 0) 71 | val shiftl = Reverse(shiftr) 72 | 73 | val out = 74 | Mux( 75 | io.alu_op === ALU_ADD || io.alu_op === ALU_SUB, 76 | sum, 77 | Mux( 78 | io.alu_op === ALU_SLT || io.alu_op === ALU_SLTU, 79 | cmp, 80 | Mux( 81 | io.alu_op === ALU_SRA || io.alu_op === ALU_SRL, 82 | shiftr, 83 | Mux( 84 | io.alu_op === ALU_SLL, 85 | shiftl, 86 | Mux( 87 | io.alu_op === ALU_AND, 88 | io.A & io.B, 89 | Mux( 90 | io.alu_op === ALU_OR, 91 | io.A | io.B, 92 | Mux(io.alu_op === ALU_XOR, io.A ^ io.B, Mux(io.alu_op === ALU_COPY_A, io.A, io.B)) 93 | ) 94 | ) 95 | ) 96 | ) 97 | ) 98 | ) 99 | 100 | io.out := out 101 | io.sum := sum 102 | } 103 | -------------------------------------------------------------------------------- /src/main/scala/mini/BrCond.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import mini.Control._ 7 | 8 | class BrCondIO(xlen: Int) extends Bundle { 9 | val rs1 = Input(UInt(xlen.W)) 10 | val rs2 = Input(UInt(xlen.W)) 11 | val br_type = Input(UInt(3.W)) 12 | val taken = Output(Bool()) 13 | } 14 | 15 | trait BrCond extends Module { 16 | def xlen: Int 17 | val io: BrCondIO 18 | } 19 | 20 | class BrCondSimple(val xlen: Int) extends BrCond { 21 | val io = IO(new BrCondIO(xlen)) 22 | val eq = io.rs1 === io.rs2 23 | val neq = !eq 24 | val lt = io.rs1.asSInt < io.rs2.asSInt 25 | val ge = !lt 26 | val ltu = io.rs1 < io.rs2 27 | val geu = !ltu 28 | io.taken := 29 | ((io.br_type === BR_EQ) && eq) || 30 | ((io.br_type === BR_NE) && neq) || 31 | ((io.br_type === BR_LT) && lt) || 32 | ((io.br_type === BR_GE) && ge) || 33 | ((io.br_type === BR_LTU) && ltu) || 34 | ((io.br_type === BR_GEU) && geu) 35 | } 36 | 37 | class BrCondArea(val xlen: Int) extends BrCond { 38 | val io = IO(new BrCondIO(xlen)) 39 | val diff = io.rs1 - io.rs2 40 | val neq = diff.orR 41 | val eq = !neq 42 | val isSameSign = io.rs1(xlen - 1) === io.rs2(xlen - 1) 43 | val lt = Mux(isSameSign, diff(xlen - 1), io.rs1(xlen - 1)) 44 | val ltu = Mux(isSameSign, diff(xlen - 1), io.rs2(xlen - 1)) 45 | val ge = !lt 46 | val geu = !ltu 47 | io.taken := 48 | ((io.br_type === BR_EQ) && eq) || 49 | ((io.br_type === BR_NE) && neq) || 50 | ((io.br_type === BR_LT) && lt) || 51 | ((io.br_type === BR_GE) && ge) || 52 | ((io.br_type === BR_LTU) && ltu) || 53 | ((io.br_type === BR_GEU) && geu) 54 | } 55 | -------------------------------------------------------------------------------- /src/main/scala/mini/Cache.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | import junctions._ 8 | 9 | class CacheReq(addrWidth: Int, dataWidth: Int) extends Bundle { 10 | val addr = UInt(addrWidth.W) 11 | val data = UInt(dataWidth.W) 12 | val mask = UInt((dataWidth / 8).W) 13 | } 14 | 15 | class CacheResp(dataWidth: Int) extends Bundle { 16 | val data = UInt(dataWidth.W) 17 | } 18 | 19 | class CacheIO(addrWidth: Int, dataWidth: Int) extends Bundle { 20 | val abort = Input(Bool()) 21 | val req = Flipped(Valid(new CacheReq(addrWidth, dataWidth))) 22 | val resp = Valid(new CacheResp(dataWidth)) 23 | } 24 | 25 | class CacheModuleIO(nastiParams: NastiBundleParameters, addrWidth: Int, dataWidth: Int) extends Bundle { 26 | val cpu = new CacheIO(addrWidth, dataWidth) 27 | val nasti = new NastiBundle(nastiParams) 28 | } 29 | 30 | case class CacheConfig(nWays: Int, nSets: Int, blockBytes: Int) 31 | 32 | class MetaData(tagLength: Int) extends Bundle { 33 | val tag = UInt(tagLength.W) 34 | } 35 | 36 | object CacheState extends ChiselEnum { 37 | val sIdle, sReadCache, sWriteCache, sWriteBack, sWriteAck, sRefillReady, sRefill = Value 38 | } 39 | 40 | class Cache(val p: CacheConfig, val nasti: NastiBundleParameters, val xlen: Int) extends Module { 41 | // local parameters 42 | val nSets = p.nSets 43 | val bBytes = p.blockBytes 44 | val bBits = bBytes << 3 45 | val blen = log2Ceil(bBytes) 46 | val slen = log2Ceil(nSets) 47 | val tlen = xlen - (slen + blen) 48 | val nWords = bBits / xlen 49 | val wBytes = xlen / 8 50 | val byteOffsetBits = log2Ceil(wBytes) 51 | val dataBeats = bBits / nasti.dataBits 52 | 53 | val io = IO(new CacheModuleIO(nasti, addrWidth = xlen, dataWidth = xlen)) 54 | 55 | // cache states 56 | import CacheState._ 57 | val state = RegInit(sIdle) 58 | // memory 59 | val v = RegInit(0.U(nSets.W)) 60 | val d = RegInit(0.U(nSets.W)) 61 | val metaMem = SyncReadMem(nSets, new MetaData(tlen)) 62 | val dataMem = Seq.fill(nWords)(SyncReadMem(nSets, Vec(wBytes, UInt(8.W)))) 63 | 64 | val addr_reg = Reg(chiselTypeOf(io.cpu.req.bits.addr)) 65 | val cpu_data = Reg(chiselTypeOf(io.cpu.req.bits.data)) 66 | val cpu_mask = Reg(chiselTypeOf(io.cpu.req.bits.mask)) 67 | 68 | // Counters 69 | require(dataBeats > 0) 70 | val (read_count, read_wrap_out) = Counter(io.nasti.r.fire, dataBeats) 71 | val (write_count, write_wrap_out) = Counter(io.nasti.w.fire, dataBeats) 72 | 73 | val is_idle = state === sIdle 74 | val is_read = state === sReadCache 75 | val is_write = state === sWriteCache 76 | val is_alloc = state === sRefill && read_wrap_out 77 | val is_alloc_reg = RegNext(is_alloc) 78 | 79 | val hit = Wire(Bool()) 80 | val wen = is_write && (hit || is_alloc_reg) && !io.cpu.abort || is_alloc 81 | val ren = !wen && (is_idle || is_read) && io.cpu.req.valid 82 | val ren_reg = RegNext(ren) 83 | 84 | val addr = io.cpu.req.bits.addr 85 | val idx = addr(slen + blen - 1, blen) 86 | val tag_reg = addr_reg(xlen - 1, slen + blen) 87 | val idx_reg = addr_reg(slen + blen - 1, blen) 88 | val off_reg = addr_reg(blen - 1, byteOffsetBits) 89 | 90 | val rmeta = metaMem.read(idx, ren) 91 | val rdata = Cat((dataMem.map(_.read(idx, ren).asUInt)).reverse) 92 | val rdata_buf = RegEnable(rdata, ren_reg) 93 | val refill_buf = Reg(Vec(dataBeats, UInt(nasti.dataBits.W))) 94 | val read = Mux(is_alloc_reg, refill_buf.asUInt, Mux(ren_reg, rdata, rdata_buf)) 95 | 96 | hit := v(idx_reg) && rmeta.tag === tag_reg 97 | 98 | // Read Mux 99 | io.cpu.resp.bits.data := VecInit.tabulate(nWords)(i => read((i + 1) * xlen - 1, i * xlen))(off_reg) 100 | io.cpu.resp.valid := is_idle || is_read && hit || is_alloc_reg && !cpu_mask.orR 101 | 102 | when(io.cpu.resp.valid) { 103 | addr_reg := addr 104 | cpu_data := io.cpu.req.bits.data 105 | cpu_mask := io.cpu.req.bits.mask 106 | } 107 | 108 | val wmeta = Wire(new MetaData(tlen)) 109 | wmeta.tag := tag_reg 110 | 111 | val wmask = Mux(!is_alloc, (cpu_mask << Cat(off_reg, 0.U(byteOffsetBits.W))).zext, (-1).S) 112 | val wdata = Mux( 113 | !is_alloc, 114 | Fill(nWords, cpu_data), 115 | if (refill_buf.size == 1) io.nasti.r.bits.data 116 | else Cat(io.nasti.r.bits.data, Cat(refill_buf.init.reverse)) 117 | ) 118 | when(wen) { 119 | v := v.bitSet(idx_reg, true.B) 120 | d := d.bitSet(idx_reg, !is_alloc) 121 | when(is_alloc) { 122 | metaMem.write(idx_reg, wmeta) 123 | } 124 | dataMem.zipWithIndex.foreach { 125 | case (mem, i) => 126 | val data = VecInit.tabulate(wBytes)(k => wdata(i * xlen + (k + 1) * 8 - 1, i * xlen + k * 8)) 127 | mem.write(idx_reg, data, wmask((i + 1) * wBytes - 1, i * wBytes).asBools) 128 | mem.suggestName(s"dataMem_${i}") 129 | } 130 | } 131 | 132 | io.nasti.ar.bits := NastiAddressBundle(nasti)( 133 | 0.U, 134 | (Cat(tag_reg, idx_reg) << blen.U).asUInt, 135 | log2Up(nasti.dataBits / 8).U, 136 | (dataBeats - 1).U 137 | ) 138 | io.nasti.ar.valid := false.B 139 | // read data 140 | io.nasti.r.ready := state === sRefill 141 | when(io.nasti.r.fire) { 142 | refill_buf(read_count) := io.nasti.r.bits.data 143 | } 144 | 145 | // write addr 146 | io.nasti.aw.bits := NastiAddressBundle(nasti)( 147 | 0.U, 148 | (Cat(rmeta.tag, idx_reg) << blen.U).asUInt, 149 | log2Up(nasti.dataBits / 8).U, 150 | (dataBeats - 1).U 151 | ) 152 | io.nasti.aw.valid := false.B 153 | // write data 154 | io.nasti.w.bits := NastiWriteDataBundle(nasti)( 155 | VecInit.tabulate(dataBeats)(i => read((i + 1) * nasti.dataBits - 1, i * nasti.dataBits))(write_count), 156 | None, 157 | write_wrap_out 158 | ) 159 | io.nasti.w.valid := false.B 160 | // write resp 161 | io.nasti.b.ready := false.B 162 | 163 | // Cache FSM 164 | val is_dirty = v(idx_reg) && d(idx_reg) 165 | switch(state) { 166 | is(sIdle) { 167 | when(io.cpu.req.valid) { 168 | state := Mux(io.cpu.req.bits.mask.orR, sWriteCache, sReadCache) 169 | } 170 | } 171 | is(sReadCache) { 172 | when(hit) { 173 | when(io.cpu.req.valid) { 174 | state := Mux(io.cpu.req.bits.mask.orR, sWriteCache, sReadCache) 175 | }.otherwise { 176 | state := sIdle 177 | } 178 | }.otherwise { 179 | io.nasti.aw.valid := is_dirty 180 | io.nasti.ar.valid := !is_dirty 181 | when(io.nasti.aw.fire) { 182 | state := sWriteBack 183 | }.elsewhen(io.nasti.ar.fire) { 184 | state := sRefill 185 | } 186 | } 187 | } 188 | is(sWriteCache) { 189 | when(hit || is_alloc_reg || io.cpu.abort) { 190 | state := sIdle 191 | }.otherwise { 192 | io.nasti.aw.valid := is_dirty 193 | io.nasti.ar.valid := !is_dirty 194 | when(io.nasti.aw.fire) { 195 | state := sWriteBack 196 | }.elsewhen(io.nasti.ar.fire) { 197 | state := sRefill 198 | } 199 | } 200 | } 201 | is(sWriteBack) { 202 | io.nasti.w.valid := true.B 203 | when(write_wrap_out) { 204 | state := sWriteAck 205 | } 206 | } 207 | is(sWriteAck) { 208 | io.nasti.b.ready := true.B 209 | when(io.nasti.b.fire) { 210 | state := sRefillReady 211 | } 212 | } 213 | is(sRefillReady) { 214 | io.nasti.ar.valid := true.B 215 | when(io.nasti.ar.fire) { 216 | state := sRefill 217 | } 218 | } 219 | is(sRefill) { 220 | when(read_wrap_out) { 221 | state := Mux(cpu_mask.orR, sWriteCache, sIdle) 222 | } 223 | } 224 | } 225 | } 226 | -------------------------------------------------------------------------------- /src/main/scala/mini/Config.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import junctions.NastiBundleParameters 6 | 7 | case class Config(core: CoreConfig, cache: CacheConfig, nasti: NastiBundleParameters) 8 | 9 | object MiniConfig { 10 | def apply(): Config = { 11 | val xlen = 32 12 | Config( 13 | core = CoreConfig( 14 | xlen = xlen, 15 | makeAlu = new AluArea(_), 16 | makeBrCond = new BrCondArea(_), 17 | makeImmGen = new ImmGenWire(_) 18 | ), 19 | cache = CacheConfig( 20 | nWays = 1, 21 | nSets = 256, 22 | blockBytes = 4 * (xlen / 8) // 4 * 32 bits = 16B 23 | ), 24 | nasti = NastiBundleParameters( 25 | addrBits = 32, 26 | dataBits = 64, 27 | idBits = 5 28 | ) 29 | ) 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /src/main/scala/mini/Control.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | 8 | object Control { 9 | val Y = true.B 10 | val N = false.B 11 | 12 | // pc_sel 13 | val PC_4 = 0.U(2.W) 14 | val PC_ALU = 1.U(2.W) 15 | val PC_0 = 2.U(2.W) 16 | val PC_EPC = 3.U(2.W) 17 | 18 | // A_sel 19 | val A_XXX = 0.U(1.W) 20 | val A_PC = 0.U(1.W) 21 | val A_RS1 = 1.U(1.W) 22 | 23 | // B_sel 24 | val B_XXX = 0.U(1.W) 25 | val B_IMM = 0.U(1.W) 26 | val B_RS2 = 1.U(1.W) 27 | 28 | // imm_sel 29 | val IMM_X = 0.U(3.W) 30 | val IMM_I = 1.U(3.W) 31 | val IMM_S = 2.U(3.W) 32 | val IMM_U = 3.U(3.W) 33 | val IMM_J = 4.U(3.W) 34 | val IMM_B = 5.U(3.W) 35 | val IMM_Z = 6.U(3.W) 36 | 37 | // br_type 38 | val BR_XXX = 0.U(3.W) 39 | val BR_LTU = 1.U(3.W) 40 | val BR_LT = 2.U(3.W) 41 | val BR_EQ = 3.U(3.W) 42 | val BR_GEU = 4.U(3.W) 43 | val BR_GE = 5.U(3.W) 44 | val BR_NE = 6.U(3.W) 45 | 46 | // st_type 47 | val ST_XXX = 0.U(2.W) 48 | val ST_SW = 1.U(2.W) 49 | val ST_SH = 2.U(2.W) 50 | val ST_SB = 3.U(2.W) 51 | 52 | // ld_type 53 | val LD_XXX = 0.U(3.W) 54 | val LD_LW = 1.U(3.W) 55 | val LD_LH = 2.U(3.W) 56 | val LD_LB = 3.U(3.W) 57 | val LD_LHU = 4.U(3.W) 58 | val LD_LBU = 5.U(3.W) 59 | 60 | // wb_sel 61 | val WB_ALU = 0.U(2.W) 62 | val WB_MEM = 1.U(2.W) 63 | val WB_PC4 = 2.U(2.W) 64 | val WB_CSR = 3.U(2.W) 65 | 66 | import Alu._ 67 | import Instructions._ 68 | 69 | // format: off 70 | val default = 71 | // kill wb_en illegal? 72 | // pc_sel A_sel B_sel imm_sel alu_op br_type | st_type ld_type wb_sel | csr_cmd | 73 | // | | | | | | | | | | | | | 74 | List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, Y) 75 | val map = Array( 76 | LUI -> List(PC_4 , A_PC, B_IMM, IMM_U, ALU_COPY_B, BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 77 | AUIPC -> List(PC_4 , A_PC, B_IMM, IMM_U, ALU_ADD , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 78 | JAL -> List(PC_ALU, A_PC, B_IMM, IMM_J, ALU_ADD , BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N), 79 | JALR -> List(PC_ALU, A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N), 80 | BEQ -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_EQ , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 81 | BNE -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_NE , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 82 | BLT -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_LT , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 83 | BGE -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_GE , N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 84 | BLTU -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_LTU, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 85 | BGEU -> List(PC_4 , A_PC, B_IMM, IMM_B, ALU_ADD , BR_GEU, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 86 | LB -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LB , WB_MEM, Y, CSR.N, N), 87 | LH -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LH , WB_MEM, Y, CSR.N, N), 88 | LW -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LW , WB_MEM, Y, CSR.N, N), 89 | LBU -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LBU, WB_MEM, Y, CSR.N, N), 90 | LHU -> List(PC_0 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_LHU, WB_MEM, Y, CSR.N, N), 91 | SB -> List(PC_4 , A_RS1, B_IMM, IMM_S, ALU_ADD , BR_XXX, N, ST_SB , LD_XXX, WB_ALU, N, CSR.N, N), 92 | SH -> List(PC_4 , A_RS1, B_IMM, IMM_S, ALU_ADD , BR_XXX, N, ST_SH , LD_XXX, WB_ALU, N, CSR.N, N), 93 | SW -> List(PC_4 , A_RS1, B_IMM, IMM_S, ALU_ADD , BR_XXX, N, ST_SW , LD_XXX, WB_ALU, N, CSR.N, N), 94 | ADDI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 95 | SLTI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SLT , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 96 | SLTIU -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SLTU , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 97 | XORI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_XOR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 98 | ORI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_OR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 99 | ANDI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_AND , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 100 | SLLI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SLL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 101 | SRLI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SRL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 102 | SRAI -> List(PC_4 , A_RS1, B_IMM, IMM_I, ALU_SRA , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 103 | ADD -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_ADD , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 104 | SUB -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SUB , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 105 | SLL -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SLL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 106 | SLT -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SLT , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 107 | SLTU -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SLTU , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 108 | XOR -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_XOR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 109 | SRL -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SRL , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 110 | SRA -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_SRA , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 111 | OR -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_OR , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 112 | AND -> List(PC_4 , A_RS1, B_RS2, IMM_X, ALU_AND , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, Y, CSR.N, N), 113 | FENCE -> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 114 | FENCEI-> List(PC_0 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N), 115 | CSRRW -> List(PC_0 , A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.W, N), 116 | CSRRS -> List(PC_0 , A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.S, N), 117 | CSRRC -> List(PC_0 , A_RS1, B_XXX, IMM_X, ALU_COPY_A, BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.C, N), 118 | CSRRWI-> List(PC_0 , A_XXX, B_XXX, IMM_Z, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.W, N), 119 | CSRRSI-> List(PC_0 , A_XXX, B_XXX, IMM_Z, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.S, N), 120 | CSRRCI-> List(PC_0 , A_XXX, B_XXX, IMM_Z, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, Y, CSR.C, N), 121 | ECALL -> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N), 122 | EBREAK-> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N), 123 | ERET -> List(PC_EPC, A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, Y, ST_XXX, LD_XXX, WB_CSR, N, CSR.P, N), 124 | WFI -> List(PC_4 , A_XXX, B_XXX, IMM_X, ALU_XXX , BR_XXX, N, ST_XXX, LD_XXX, WB_ALU, N, CSR.N, N)) 125 | // format: on 126 | } 127 | 128 | class ControlSignals extends Bundle { 129 | val inst = Input(UInt(32.W)) 130 | val pc_sel = Output(UInt(2.W)) 131 | val inst_kill = Output(Bool()) 132 | val A_sel = Output(UInt(1.W)) 133 | val B_sel = Output(UInt(1.W)) 134 | val imm_sel = Output(UInt(3.W)) 135 | val alu_op = Output(UInt(4.W)) 136 | val br_type = Output(UInt(3.W)) 137 | val st_type = Output(UInt(2.W)) 138 | val ld_type = Output(UInt(3.W)) 139 | val wb_sel = Output(UInt(2.W)) 140 | val wb_en = Output(Bool()) 141 | val csr_cmd = Output(UInt(3.W)) 142 | val illegal = Output(Bool()) 143 | } 144 | 145 | class Control extends Module { 146 | val io = IO(new ControlSignals) 147 | val ctrlSignals = ListLookup(io.inst, Control.default, Control.map) 148 | 149 | // Control signals for Fetch 150 | io.pc_sel := ctrlSignals(0) 151 | io.inst_kill := ctrlSignals(6).asBool 152 | 153 | // Control signals for Execute 154 | io.A_sel := ctrlSignals(1) 155 | io.B_sel := ctrlSignals(2) 156 | io.imm_sel := ctrlSignals(3) 157 | io.alu_op := ctrlSignals(4) 158 | io.br_type := ctrlSignals(5) 159 | io.st_type := ctrlSignals(7) 160 | 161 | // Control signals for Write Back 162 | io.ld_type := ctrlSignals(8) 163 | io.wb_sel := ctrlSignals(9) 164 | io.wb_en := ctrlSignals(10).asBool 165 | io.csr_cmd := ctrlSignals(11) 166 | io.illegal := ctrlSignals(12) 167 | } 168 | -------------------------------------------------------------------------------- /src/main/scala/mini/Core.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.util.Valid 7 | 8 | case class CoreConfig( 9 | xlen: Int, 10 | makeAlu: Int => Alu = new AluSimple(_), 11 | makeBrCond: Int => BrCond = new BrCondSimple(_), 12 | makeImmGen: Int => ImmGen = new ImmGenWire(_)) 13 | 14 | class HostIO(xlen: Int) extends Bundle { 15 | val fromhost = Flipped(Valid(UInt(xlen.W))) 16 | val tohost = Output(UInt(xlen.W)) 17 | } 18 | 19 | class CoreIO(xlen: Int) extends Bundle { 20 | val host = new HostIO(xlen) 21 | val icache = Flipped(new CacheIO(xlen, xlen)) 22 | val dcache = Flipped(new CacheIO(xlen, xlen)) 23 | } 24 | 25 | class Core(val conf: CoreConfig) extends Module { 26 | val io = IO(new CoreIO(conf.xlen)) 27 | val dpath = Module(new Datapath(conf)) 28 | val ctrl = Module(new Control) 29 | 30 | io.host <> dpath.io.host 31 | dpath.io.icache <> io.icache 32 | dpath.io.dcache <> io.dcache 33 | dpath.io.ctrl <> ctrl.io 34 | } 35 | -------------------------------------------------------------------------------- /src/main/scala/mini/Datapath.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | import chisel3.experimental.BundleLiterals._ 8 | 9 | object Consts { 10 | val PC_START = 0x200 11 | val PC_EVEC = 0x100 12 | } 13 | 14 | class DatapathIO(xlen: Int) extends Bundle { 15 | val host = new HostIO(xlen) 16 | val icache = Flipped(new CacheIO(xlen, xlen)) 17 | val dcache = Flipped(new CacheIO(xlen, xlen)) 18 | val ctrl = Flipped(new ControlSignals) 19 | } 20 | 21 | class FetchExecutePipelineRegister(xlen: Int) extends Bundle { 22 | val inst = chiselTypeOf(Instructions.NOP) 23 | val pc = UInt(xlen.W) 24 | } 25 | 26 | class ExecuteWritebackPipelineRegister(xlen: Int) extends Bundle { 27 | val inst = chiselTypeOf(Instructions.NOP) 28 | val pc = UInt(xlen.W) 29 | val alu = UInt(xlen.W) 30 | val csr_in = UInt(xlen.W) 31 | } 32 | 33 | class Datapath(val conf: CoreConfig) extends Module { 34 | val io = IO(new DatapathIO(conf.xlen)) 35 | val csr = Module(new CSR(conf.xlen)) 36 | val regFile = Module(new RegFile(conf.xlen)) 37 | val alu = Module(conf.makeAlu(conf.xlen)) 38 | val immGen = Module(conf.makeImmGen(conf.xlen)) 39 | val brCond = Module(conf.makeBrCond(conf.xlen)) 40 | 41 | import Control._ 42 | 43 | /** Pipeline State Registers * */ 44 | 45 | /** *** Fetch / Execute Registers **** 46 | */ 47 | val fe_reg = RegInit( 48 | (new FetchExecutePipelineRegister(conf.xlen)).Lit( 49 | _.inst -> Instructions.NOP, 50 | _.pc -> 0.U 51 | ) 52 | ) 53 | 54 | /** *** Execute / Write Back Registers **** 55 | */ 56 | val ew_reg = RegInit( 57 | (new ExecuteWritebackPipelineRegister(conf.xlen)).Lit( 58 | _.inst -> Instructions.NOP, 59 | _.pc -> 0.U, 60 | _.alu -> 0.U, 61 | _.csr_in -> 0.U 62 | ) 63 | ) 64 | 65 | /** **** Control signals **** 66 | */ 67 | val st_type = Reg(io.ctrl.st_type.cloneType) 68 | val ld_type = Reg(io.ctrl.ld_type.cloneType) 69 | val wb_sel = Reg(io.ctrl.wb_sel.cloneType) 70 | val wb_en = Reg(Bool()) 71 | val csr_cmd = Reg(io.ctrl.csr_cmd.cloneType) 72 | val illegal = Reg(Bool()) 73 | val pc_check = Reg(Bool()) 74 | 75 | /** **** Fetch **** 76 | */ 77 | val started = RegNext(reset.asBool) 78 | val stall = !io.icache.resp.valid || !io.dcache.resp.valid 79 | val pc = RegInit(Consts.PC_START.U(conf.xlen.W) - 4.U(conf.xlen.W)) 80 | // Next Program Counter 81 | val next_pc = MuxCase( 82 | pc + 4.U, 83 | IndexedSeq( 84 | stall -> pc, 85 | csr.io.expt -> csr.io.evec, 86 | (io.ctrl.pc_sel === PC_EPC) -> csr.io.epc, 87 | ((io.ctrl.pc_sel === PC_ALU) || (brCond.io.taken)) -> (alu.io.sum >> 1.U << 1.U), 88 | (io.ctrl.pc_sel === PC_0) -> pc 89 | ) 90 | ) 91 | val inst = 92 | Mux(started || io.ctrl.inst_kill || brCond.io.taken || csr.io.expt, Instructions.NOP, io.icache.resp.bits.data) 93 | pc := next_pc 94 | io.icache.req.bits.addr := next_pc 95 | io.icache.req.bits.data := 0.U 96 | io.icache.req.bits.mask := 0.U 97 | io.icache.req.valid := !stall 98 | io.icache.abort := false.B 99 | 100 | // Pipelining 101 | when(!stall) { 102 | fe_reg.pc := pc 103 | fe_reg.inst := inst 104 | } 105 | 106 | /** **** Execute **** 107 | */ 108 | io.ctrl.inst := fe_reg.inst 109 | 110 | // regFile read 111 | val rd_addr = fe_reg.inst(11, 7) 112 | val rs1_addr = fe_reg.inst(19, 15) 113 | val rs2_addr = fe_reg.inst(24, 20) 114 | regFile.io.raddr1 := rs1_addr 115 | regFile.io.raddr2 := rs2_addr 116 | 117 | // gen immdeates 118 | immGen.io.inst := fe_reg.inst 119 | immGen.io.sel := io.ctrl.imm_sel 120 | 121 | // bypass 122 | val wb_rd_addr = ew_reg.inst(11, 7) 123 | val rs1hazard = wb_en && rs1_addr.orR && (rs1_addr === wb_rd_addr) 124 | val rs2hazard = wb_en && rs2_addr.orR && (rs2_addr === wb_rd_addr) 125 | val rs1 = Mux(wb_sel === WB_ALU && rs1hazard, ew_reg.alu, regFile.io.rdata1) 126 | val rs2 = Mux(wb_sel === WB_ALU && rs2hazard, ew_reg.alu, regFile.io.rdata2) 127 | 128 | // ALU operations 129 | alu.io.A := Mux(io.ctrl.A_sel === A_RS1, rs1, fe_reg.pc) 130 | alu.io.B := Mux(io.ctrl.B_sel === B_RS2, rs2, immGen.io.out) 131 | alu.io.alu_op := io.ctrl.alu_op 132 | 133 | // Branch condition calc 134 | brCond.io.rs1 := rs1 135 | brCond.io.rs2 := rs2 136 | brCond.io.br_type := io.ctrl.br_type 137 | 138 | // D$ access 139 | val daddr = Mux(stall, ew_reg.alu, alu.io.sum) >> 2.U << 2.U 140 | val woffset = (alu.io.sum(1) << 4.U).asUInt | (alu.io.sum(0) << 3.U).asUInt 141 | io.dcache.req.valid := !stall && (io.ctrl.st_type.orR || io.ctrl.ld_type.orR) 142 | io.dcache.req.bits.addr := daddr 143 | io.dcache.req.bits.data := rs2 << woffset 144 | io.dcache.req.bits.mask := MuxLookup(Mux(stall, st_type, io.ctrl.st_type), "b0000".U)( 145 | Seq(ST_SW -> "b1111".U, ST_SH -> ("b11".U << alu.io.sum(1, 0)), ST_SB -> ("b1".U << alu.io.sum(1, 0))) 146 | ) 147 | 148 | // Pipelining 149 | when(reset.asBool || !stall && csr.io.expt) { 150 | st_type := 0.U 151 | ld_type := 0.U 152 | wb_en := false.B 153 | csr_cmd := 0.U 154 | illegal := false.B 155 | pc_check := false.B 156 | }.elsewhen(!stall && !csr.io.expt) { 157 | ew_reg.pc := fe_reg.pc 158 | ew_reg.inst := fe_reg.inst 159 | ew_reg.alu := alu.io.out 160 | ew_reg.csr_in := Mux(io.ctrl.imm_sel === IMM_Z, immGen.io.out, rs1) 161 | st_type := io.ctrl.st_type 162 | ld_type := io.ctrl.ld_type 163 | wb_sel := io.ctrl.wb_sel 164 | wb_en := io.ctrl.wb_en 165 | csr_cmd := io.ctrl.csr_cmd 166 | illegal := io.ctrl.illegal 167 | pc_check := io.ctrl.pc_sel === PC_ALU 168 | } 169 | 170 | // Load 171 | val loffset = (ew_reg.alu(1) << 4.U).asUInt | (ew_reg.alu(0) << 3.U).asUInt 172 | val lshift = io.dcache.resp.bits.data >> loffset 173 | val load = MuxLookup(ld_type, io.dcache.resp.bits.data.zext)( 174 | Seq( 175 | LD_LH -> lshift(15, 0).asSInt, 176 | LD_LB -> lshift(7, 0).asSInt, 177 | LD_LHU -> lshift(15, 0).zext, 178 | LD_LBU -> lshift(7, 0).zext 179 | ) 180 | ) 181 | 182 | // CSR access 183 | csr.io.stall := stall 184 | csr.io.in := ew_reg.csr_in 185 | csr.io.cmd := csr_cmd 186 | csr.io.inst := ew_reg.inst 187 | csr.io.pc := ew_reg.pc 188 | csr.io.addr := ew_reg.alu 189 | csr.io.illegal := illegal 190 | csr.io.pc_check := pc_check 191 | csr.io.ld_type := ld_type 192 | csr.io.st_type := st_type 193 | io.host <> csr.io.host 194 | 195 | // Regfile Write 196 | val regWrite = 197 | MuxLookup(wb_sel, ew_reg.alu.zext)( 198 | Seq(WB_MEM -> load, WB_PC4 -> (ew_reg.pc + 4.U).zext, WB_CSR -> csr.io.out.zext) 199 | ).asUInt 200 | 201 | regFile.io.wen := wb_en && !stall && !csr.io.expt 202 | regFile.io.waddr := wb_rd_addr 203 | regFile.io.wdata := regWrite 204 | 205 | // Abort store when there's an excpetion 206 | io.dcache.abort := csr.io.expt 207 | 208 | // TODO: re-enable through AOP 209 | // if (p(Trace)) { 210 | // printf( 211 | // "PC: %x, INST: %x, REG[%d] <- %x\n", 212 | // ew_reg.pc, 213 | // ew_reg.inst, 214 | // Mux(regFile.io.wen, wb_rd_addr, 0.U), 215 | // Mux(regFile.io.wen, regFile.io.wdata, 0.U) 216 | // ) 217 | // } 218 | } 219 | -------------------------------------------------------------------------------- /src/main/scala/mini/ImmGen.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | import mini.Control._ 8 | 9 | class ImmGenIO(xlen: Int) extends Bundle { 10 | val inst = Input(UInt(xlen.W)) 11 | val sel = Input(UInt(3.W)) 12 | val out = Output(UInt(xlen.W)) 13 | } 14 | 15 | trait ImmGen extends Module { 16 | def xlen: Int 17 | val io: ImmGenIO 18 | } 19 | 20 | class ImmGenWire(val xlen: Int) extends ImmGen { 21 | val io = IO(new ImmGenIO(xlen)) 22 | val Iimm = io.inst(31, 20).asSInt 23 | val Simm = Cat(io.inst(31, 25), io.inst(11, 7)).asSInt 24 | val Bimm = Cat(io.inst(31), io.inst(7), io.inst(30, 25), io.inst(11, 8), 0.U(1.W)).asSInt 25 | val Uimm = Cat(io.inst(31, 12), 0.U(12.W)).asSInt 26 | val Jimm = Cat(io.inst(31), io.inst(19, 12), io.inst(20), io.inst(30, 25), io.inst(24, 21), 0.U(1.W)).asSInt 27 | val Zimm = io.inst(19, 15).zext 28 | 29 | io.out := MuxLookup(io.sel, Iimm & (-2).S)( 30 | Seq(IMM_I -> Iimm, IMM_S -> Simm, IMM_B -> Bimm, IMM_U -> Uimm, IMM_J -> Jimm, IMM_Z -> Zimm) 31 | ).asUInt 32 | } 33 | 34 | class ImmGenMux(val xlen: Int) extends ImmGen { 35 | val io = IO(new ImmGenIO(xlen)) 36 | val sign = Mux(io.sel === IMM_Z, 0.S, io.inst(31).asSInt) 37 | val b30_20 = Mux(io.sel === IMM_U, io.inst(30, 20).asSInt, sign) 38 | val b19_12 = Mux(io.sel =/= IMM_U && io.sel =/= IMM_J, sign, io.inst(19, 12).asSInt) 39 | val b11 = Mux( 40 | io.sel === IMM_U || io.sel === IMM_Z, 41 | 0.S, 42 | Mux(io.sel === IMM_J, io.inst(20).asSInt, Mux(io.sel === IMM_B, io.inst(7).asSInt, sign)) 43 | ) 44 | val b10_5 = Mux(io.sel === IMM_U || io.sel === IMM_Z, 0.U, io.inst(30, 25)) 45 | val b4_1 = Mux( 46 | io.sel === IMM_U, 47 | 0.U, 48 | Mux(io.sel === IMM_S || io.sel === IMM_B, io.inst(11, 8), Mux(io.sel === IMM_Z, io.inst(19, 16), io.inst(24, 21))) 49 | ) 50 | val b0 = 51 | Mux(io.sel === IMM_S, io.inst(7), Mux(io.sel === IMM_I, io.inst(20), Mux(io.sel === IMM_Z, io.inst(15), 0.U))) 52 | 53 | io.out := Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt.asUInt 54 | } 55 | -------------------------------------------------------------------------------- /src/main/scala/mini/Instructions.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3.util.BitPat 6 | 7 | object Instructions { 8 | // Loads 9 | def LB = BitPat("b?????????????????000?????0000011") 10 | def LH = BitPat("b?????????????????001?????0000011") 11 | def LW = BitPat("b?????????????????010?????0000011") 12 | def LBU = BitPat("b?????????????????100?????0000011") 13 | def LHU = BitPat("b?????????????????101?????0000011") 14 | // Stores 15 | def SB = BitPat("b?????????????????000?????0100011") 16 | def SH = BitPat("b?????????????????001?????0100011") 17 | def SW = BitPat("b?????????????????010?????0100011") 18 | // Shifts 19 | def SLL = BitPat("b0000000??????????001?????0110011") 20 | def SLLI = BitPat("b0000000??????????001?????0010011") 21 | def SRL = BitPat("b0000000??????????101?????0110011") 22 | def SRLI = BitPat("b0000000??????????101?????0010011") 23 | def SRA = BitPat("b0100000??????????101?????0110011") 24 | def SRAI = BitPat("b0100000??????????101?????0010011") 25 | // Arithmetic 26 | def ADD = BitPat("b0000000??????????000?????0110011") 27 | def ADDI = BitPat("b?????????????????000?????0010011") 28 | def SUB = BitPat("b0100000??????????000?????0110011") 29 | def LUI = BitPat("b?????????????????????????0110111") 30 | def AUIPC = BitPat("b?????????????????????????0010111") 31 | // Logical 32 | def XOR = BitPat("b0000000??????????100?????0110011") 33 | def XORI = BitPat("b?????????????????100?????0010011") 34 | def OR = BitPat("b0000000??????????110?????0110011") 35 | def ORI = BitPat("b?????????????????110?????0010011") 36 | def AND = BitPat("b0000000??????????111?????0110011") 37 | def ANDI = BitPat("b?????????????????111?????0010011") 38 | // Compare 39 | def SLT = BitPat("b0000000??????????010?????0110011") 40 | def SLTI = BitPat("b?????????????????010?????0010011") 41 | def SLTU = BitPat("b0000000??????????011?????0110011") 42 | def SLTIU = BitPat("b?????????????????011?????0010011") 43 | // Branches 44 | def BEQ = BitPat("b?????????????????000?????1100011") 45 | def BNE = BitPat("b?????????????????001?????1100011") 46 | def BLT = BitPat("b?????????????????100?????1100011") 47 | def BGE = BitPat("b?????????????????101?????1100011") 48 | def BLTU = BitPat("b?????????????????110?????1100011") 49 | def BGEU = BitPat("b?????????????????111?????1100011") 50 | // Jump & Link 51 | def JAL = BitPat("b?????????????????????????1101111") 52 | def JALR = BitPat("b?????????????????000?????1100111") 53 | // Synch 54 | def FENCE = BitPat("b0000????????00000000000000001111") 55 | def FENCEI = BitPat("b00000000000000000001000000001111") 56 | // CSR Access 57 | def CSRRW = BitPat("b?????????????????001?????1110011") 58 | def CSRRS = BitPat("b?????????????????010?????1110011") 59 | def CSRRC = BitPat("b?????????????????011?????1110011") 60 | def CSRRWI = BitPat("b?????????????????101?????1110011") 61 | def CSRRSI = BitPat("b?????????????????110?????1110011") 62 | def CSRRCI = BitPat("b?????????????????111?????1110011") 63 | // Change Level 64 | def ECALL = BitPat("b00000000000000000000000001110011") 65 | def EBREAK = BitPat("b00000000000100000000000001110011") 66 | def ERET = BitPat("b00010000000000000000000001110011") 67 | def WFI = BitPat("b00010000001000000000000001110011") 68 | 69 | def NOP = BitPat.bitPatToUInt(BitPat("b00000000000000000000000000010011")) 70 | } 71 | -------------------------------------------------------------------------------- /src/main/scala/mini/Main.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import circt.stage.ChiselStage 6 | object Main extends App { 7 | val config = MiniConfig() 8 | ChiselStage.emitSystemVerilogFile( 9 | new Tile( 10 | coreParams = config.core, 11 | nastiParams = config.nasti, 12 | cacheParams = config.cache 13 | ), 14 | args 15 | ) 16 | } 17 | -------------------------------------------------------------------------------- /src/main/scala/mini/RegFile.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | 7 | class RegFileIO(xlen: Int) extends Bundle { 8 | val raddr1 = Input(UInt(5.W)) 9 | val raddr2 = Input(UInt(5.W)) 10 | val rdata1 = Output(UInt(xlen.W)) 11 | val rdata2 = Output(UInt(xlen.W)) 12 | val wen = Input(Bool()) 13 | val waddr = Input(UInt(5.W)) 14 | val wdata = Input(UInt(xlen.W)) 15 | } 16 | 17 | class RegFile(xlen: Int) extends Module { 18 | val io = IO(new RegFileIO(xlen)) 19 | val regs = Mem(32, UInt(xlen.W)) 20 | io.rdata1 := Mux(io.raddr1.orR, regs(io.raddr1), 0.U) 21 | io.rdata2 := Mux(io.raddr2.orR, regs(io.raddr2), 0.U) 22 | when(io.wen & io.waddr.orR) { 23 | regs(io.waddr) := io.wdata 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /src/main/scala/mini/Tile.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | import junctions._ 8 | 9 | class MemArbiterIO(params: NastiBundleParameters) extends Bundle { 10 | val icache = Flipped(new NastiBundle(params)) 11 | val dcache = Flipped(new NastiBundle(params)) 12 | val nasti = new NastiBundle(params) 13 | } 14 | 15 | object MemArbiterState extends ChiselEnum { 16 | val sIdle, sICacheRead, sDCacheRead, sDCacheWrite, sDCacheAck = Value 17 | } 18 | 19 | class MemArbiter(params: NastiBundleParameters) extends Module { 20 | val io = IO(new MemArbiterIO(params)) 21 | 22 | import MemArbiterState._ 23 | val state = RegInit(sIdle) 24 | 25 | // Write Address 26 | io.nasti.aw.bits := io.dcache.aw.bits 27 | io.nasti.aw.valid := io.dcache.aw.valid && state === sIdle 28 | io.dcache.aw.ready := io.nasti.aw.ready && state === sIdle 29 | io.icache.aw := DontCare 30 | 31 | // Write Data 32 | io.nasti.w.bits := io.dcache.w.bits 33 | io.nasti.w.valid := io.dcache.w.valid && state === sDCacheWrite 34 | io.dcache.w.ready := io.nasti.w.ready && state === sDCacheWrite 35 | io.icache.w := DontCare 36 | 37 | // Write Ack 38 | io.dcache.b.bits := io.nasti.b.bits 39 | io.dcache.b.valid := io.nasti.b.valid && state === sDCacheAck 40 | io.nasti.b.ready := io.dcache.b.ready && state === sDCacheAck 41 | io.icache.b := DontCare 42 | 43 | // Read Address 44 | io.nasti.ar.bits := NastiAddressBundle(params)( 45 | Mux(io.dcache.ar.valid, io.dcache.ar.bits.id, io.icache.ar.bits.id), 46 | Mux(io.dcache.ar.valid, io.dcache.ar.bits.addr, io.icache.ar.bits.addr), 47 | Mux(io.dcache.ar.valid, io.dcache.ar.bits.size, io.icache.ar.bits.size), 48 | Mux(io.dcache.ar.valid, io.dcache.ar.bits.len, io.icache.ar.bits.len) 49 | ) 50 | io.nasti.ar.valid := (io.icache.ar.valid || io.dcache.ar.valid) && 51 | !io.nasti.aw.valid && state === sIdle 52 | io.dcache.ar.ready := io.nasti.ar.ready && !io.nasti.aw.valid && state === sIdle 53 | io.icache.ar.ready := io.dcache.ar.ready && !io.dcache.ar.valid 54 | 55 | // Read Data 56 | io.icache.r.bits := io.nasti.r.bits 57 | io.dcache.r.bits := io.nasti.r.bits 58 | io.icache.r.valid := io.nasti.r.valid && state === sICacheRead 59 | io.dcache.r.valid := io.nasti.r.valid && state === sDCacheRead 60 | io.nasti.r.ready := io.icache.r.ready && state === sICacheRead || 61 | io.dcache.r.ready && state === sDCacheRead 62 | 63 | switch(state) { 64 | is(sIdle) { 65 | when(io.dcache.aw.fire) { 66 | state := sDCacheWrite 67 | }.elsewhen(io.dcache.ar.fire) { 68 | state := sDCacheRead 69 | }.elsewhen(io.icache.ar.fire) { 70 | state := sICacheRead 71 | } 72 | } 73 | is(sICacheRead) { 74 | when(io.nasti.r.fire && io.nasti.r.bits.last) { 75 | state := sIdle 76 | } 77 | } 78 | is(sDCacheRead) { 79 | when(io.nasti.r.fire && io.nasti.r.bits.last) { 80 | state := sIdle 81 | } 82 | } 83 | is(sDCacheWrite) { 84 | when(io.dcache.w.fire && io.dcache.w.bits.last) { 85 | state := sDCacheAck 86 | } 87 | } 88 | is(sDCacheAck) { 89 | when(io.nasti.b.fire) { 90 | state := sIdle 91 | } 92 | } 93 | } 94 | } 95 | 96 | class TileIO(xlen: Int, nastiParams: NastiBundleParameters) extends Bundle { 97 | val host = new HostIO(xlen) 98 | val nasti = new NastiBundle(nastiParams) 99 | } 100 | 101 | object Tile { 102 | def apply(config: Config): Tile = new Tile(config.core, config.nasti, config.cache) 103 | } 104 | 105 | class Tile(val coreParams: CoreConfig, val nastiParams: NastiBundleParameters, val cacheParams: CacheConfig) 106 | extends Module { 107 | val io = IO(new TileIO(coreParams.xlen, nastiParams)) 108 | val core = Module(new Core(coreParams)) 109 | val icache = Module(new Cache(cacheParams, nastiParams, coreParams.xlen)) 110 | val dcache = Module(new Cache(cacheParams, nastiParams, coreParams.xlen)) 111 | val arb = Module(new MemArbiter(nastiParams)) 112 | 113 | io.host <> core.io.host 114 | core.io.icache <> icache.io.cpu 115 | core.io.dcache <> dcache.io.cpu 116 | arb.io.icache <> icache.io.nasti 117 | arb.io.dcache <> dcache.io.nasti 118 | io.nasti <> arb.io.nasti 119 | } 120 | -------------------------------------------------------------------------------- /src/test/scala/mini/ALUTests.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.testers._ 7 | import chisel3.util._ 8 | import chiseltest._ 9 | import chiseltest.formal._ 10 | import org.scalatest.flatspec.AnyFlatSpec 11 | 12 | class AluTester(alu: => Alu) extends BasicTester with TestUtils { 13 | import Alu._ 14 | val dut = Module(alu) 15 | val ctrl = Module(new Control) 16 | val xlen = dut.width 17 | 18 | val (cntr, done) = Counter(true.B, insts.size) 19 | val rs1 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt) 20 | val rs2 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt) 21 | val sum = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt + b.toInt).U(xlen.W) }) 22 | val diff = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt - b.toInt).U(xlen.W) }) 23 | val and = VecInit(rs1.zip(rs2).map { case (a, b) => (a & b).U(xlen.W) }) 24 | val or = VecInit(rs1.zip(rs2).map { case (a, b) => (a | b).U(xlen.W) }) 25 | val xor = VecInit(rs1.zip(rs2).map { case (a, b) => (a ^ b).U(xlen.W) }) 26 | val slt = VecInit(rs1.zip(rs2).map { case (a, b) => (if (a.toInt < b.toInt) 1 else 0).U(xlen.W) }) 27 | val sltu = VecInit(rs1.zip(rs2).map { case (a, b) => (if (a < b) 1 else 0).U(xlen.W) }) 28 | val sll = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt << (b.toInt & 0x1f)).U(xlen.W) }) 29 | val srl = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt >>> (b.toInt & 0x1f)).U(xlen.W) }) 30 | val sra = VecInit(rs1.zip(rs2).map { case (a, b) => toBigInt(a.toInt >> (b.toInt & 0x1f)).U(xlen.W) }) 31 | val out = ( 32 | Mux( 33 | dut.io.alu_op === ALU_ADD, 34 | sum(cntr), 35 | Mux( 36 | dut.io.alu_op === ALU_SUB, 37 | diff(cntr), 38 | Mux( 39 | dut.io.alu_op === ALU_AND, 40 | and(cntr), 41 | Mux( 42 | dut.io.alu_op === ALU_OR, 43 | or(cntr), 44 | Mux( 45 | dut.io.alu_op === ALU_XOR, 46 | xor(cntr), 47 | Mux( 48 | dut.io.alu_op === ALU_SLT, 49 | slt(cntr), 50 | Mux( 51 | dut.io.alu_op === ALU_SLTU, 52 | sltu(cntr), 53 | Mux( 54 | dut.io.alu_op === ALU_SLL, 55 | sll(cntr), 56 | Mux( 57 | dut.io.alu_op === ALU_SRL, 58 | srl(cntr), 59 | Mux(dut.io.alu_op === ALU_SRA, sra(cntr), Mux(dut.io.alu_op === ALU_COPY_A, dut.io.A, dut.io.B)) 60 | ) 61 | ) 62 | ) 63 | ) 64 | ) 65 | ) 66 | ) 67 | ) 68 | ), 69 | Mux(dut.io.alu_op(0), diff(cntr), sum(cntr)) 70 | ) 71 | 72 | ctrl.io.inst := VecInit(insts)(cntr) 73 | dut.io.alu_op := ctrl.io.alu_op 74 | dut.io.A := VecInit(rs1.map(_.U))(cntr) 75 | dut.io.B := VecInit(rs2.map(_.U))(cntr) 76 | 77 | when(done) { stop() } 78 | assert(dut.io.out === out._1) 79 | assert(dut.io.sum === out._2) 80 | printf( 81 | "Counter: %d, OP: 0x%x, A: 0x%x, B: 0x%x, OUT: 0x%x ?= 0x%x, SUM: 0x%x ?= 0x%x\n", 82 | cntr, 83 | dut.io.alu_op, 84 | dut.io.A, 85 | dut.io.B, 86 | dut.io.out, 87 | out._1, 88 | dut.io.sum, 89 | out._2 90 | ) 91 | } 92 | 93 | class ALUTests extends AnyFlatSpec with ChiselScalatestTester with Formal { 94 | "ALUSimple" should "pass" in { 95 | test(new AluTester(new AluSimple(32))).runUntilStop() 96 | } 97 | "AluArea" should "pass" in { 98 | test(new AluTester(new AluArea(32))).runUntilStop() 99 | } 100 | "AluArea" should "be equivalent to AluSimple" in { 101 | // since there is no state (registers/memory) in the ALU, a single cycle check is enough to prove equivalence 102 | verify(new AluEquivalenceCheck(new AluArea(32)), Seq(BoundedCheck(1))) 103 | } 104 | } 105 | 106 | class AluEquivalenceCheck(other: => Alu) extends Module { 107 | val dut = Module(other) 108 | val ref = Module(new AluSimple(dut.width)) 109 | 110 | // arbitrary inputs 111 | val io = IO(chiselTypeOf(dut.io)) 112 | 113 | // connect the same inputs to both modules (the outputs will be overwritten to always connect to the reference) 114 | dut.io <> io; ref.io <> io 115 | 116 | // check to ensure that outputs are the same 117 | assert(ref.io.out === dut.io.out, "out: expected: %d, actual: %d", ref.io.out, dut.io.out) 118 | assert(ref.io.sum === dut.io.sum, "sum: %d, actual: %d", ref.io.sum, dut.io.sum) 119 | } 120 | -------------------------------------------------------------------------------- /src/test/scala/mini/BrCondTests.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.testers._ 7 | import chisel3.util._ 8 | import chiseltest._ 9 | import chiseltest.formal._ 10 | import org.scalatest.flatspec.AnyFlatSpec 11 | 12 | class BrCondTester(br: => BrCond) extends BasicTester with TestUtils { 13 | import Control._ 14 | val dut = Module(br) 15 | val ctrl = Module(new Control) 16 | 17 | override val insts = Seq 18 | .fill(10)( 19 | Seq( 20 | B(Funct3.BEQ, 0, 0, 0), 21 | B(Funct3.BNE, 0, 0, 0), 22 | B(Funct3.BLT, 0, 0, 0), 23 | B(Funct3.BGE, 0, 0, 0), 24 | B(Funct3.BLTU, 0, 0, 0), 25 | B(Funct3.BGEU, 0, 0, 0) 26 | ) 27 | ) 28 | .flatten 29 | 30 | val (cntr, done) = Counter(true.B, insts.size) 31 | val rs1 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt) 32 | val rs2 = Seq.fill(insts.size)(rnd.nextInt()).map(toBigInt) 33 | val eq = VecInit(rs1.zip(rs2).map { case (a, b) => (a == b).B }) 34 | val ne = VecInit(rs1.zip(rs2).map { case (a, b) => (a != b).B }) 35 | val lt = VecInit(rs1.zip(rs2).map { case (a, b) => (a.toInt < b.toInt).B }) 36 | val ge = VecInit(rs1.zip(rs2).map { case (a, b) => (a.toInt >= b.toInt).B }) 37 | val ltu = VecInit(rs1.zip(rs2).map { case (a, b) => (a < b).B }) 38 | val geu = VecInit(rs1.zip(rs2).map { case (a, b) => (a >= b).B }) 39 | val out = Mux( 40 | dut.io.br_type === BR_EQ, 41 | eq(cntr), 42 | Mux( 43 | dut.io.br_type === BR_NE, 44 | ne(cntr), 45 | Mux( 46 | dut.io.br_type === BR_LT, 47 | lt(cntr), 48 | Mux( 49 | dut.io.br_type === BR_GE, 50 | ge(cntr), 51 | Mux(dut.io.br_type === BR_LTU, ltu(cntr), Mux(dut.io.br_type === BR_GEU, geu(cntr), false.B)) 52 | ) 53 | ) 54 | ) 55 | ) 56 | 57 | ctrl.io.inst := VecInit(insts)(cntr) 58 | dut.io.br_type := ctrl.io.br_type 59 | dut.io.rs1 := VecInit(rs1.map(_.U))(cntr) 60 | dut.io.rs2 := VecInit(rs2.map(_.U))(cntr) 61 | 62 | when(done) { stop() } 63 | assert(dut.io.taken === out) 64 | printf( 65 | "Counter: %d, BrType: 0x%x, rs1: 0x%x, rs2: 0x%x, Taken: %d ?= %d\n", 66 | cntr, 67 | dut.io.br_type, 68 | dut.io.rs1, 69 | dut.io.rs2, 70 | dut.io.taken, 71 | out 72 | ) 73 | } 74 | 75 | class BrCondTests extends AnyFlatSpec with ChiselScalatestTester with Formal { 76 | "BrCondSimple" should "pass" in { 77 | test(new BrCondTester(new BrCondSimple(32))).runUntilStop() 78 | } 79 | "BrCondArea" should "pass" in { 80 | test(new BrCondTester(new BrCondArea(32))).runUntilStop() 81 | } 82 | "BrCondArea" should "be equivalent to BrCondSimple" in { 83 | // since there is no state (registers/memory) in the BrCond, a single cycle check is enough to prove equivalence 84 | verify(new BrCondEquivalenceCheck(new BrCondArea(32)), Seq(BoundedCheck(1))) 85 | } 86 | } 87 | 88 | class BrCondEquivalenceCheck(other: => BrCond) extends Module { 89 | val dut = Module(other) 90 | val ref = Module(new BrCondSimple(dut.xlen)) 91 | 92 | // arbitrary inputs 93 | val io = IO(chiselTypeOf(dut.io)) 94 | 95 | // connect the same inputs to both modules (the outputs will be overwritten to always connect to the reference) 96 | dut.io <> io; ref.io <> io 97 | 98 | // check to ensure that outputs are the same 99 | assert(ref.io.taken === dut.io.taken, "taken: expected: %d, actual: %d", ref.io.taken, dut.io.taken) 100 | } 101 | -------------------------------------------------------------------------------- /src/test/scala/mini/CoreTests.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.testers._ 7 | import chisel3.util.experimental.loadMemoryFromFileInline 8 | import chiseltest._ 9 | import org.scalatest.flatspec.AnyFlatSpec 10 | 11 | class CoreTester(core: => Core, benchmark: String, trace: Boolean = false) extends BasicTester { 12 | val originalHexFile = os.rel / "tests" / f"$benchmark.hex" 13 | val resizedHexFile = os.rel / "tests" / "32" / f"$benchmark.hex" 14 | TestUtils.resizeHexFile(os.pwd / originalHexFile, os.pwd / resizedHexFile, 32) // we have 32 bits per memory entry 15 | 16 | val dut = Module(core) 17 | val xlen = dut.conf.xlen 18 | dut.io.host.fromhost.bits := DontCare 19 | dut.io.host.fromhost.valid := false.B 20 | 21 | val imem = Mem(1 << 20, UInt(xlen.W)) 22 | loadMemoryFromFileInline(imem, resizedHexFile.toString()) 23 | val dmem = Mem(1 << 20, UInt(xlen.W)) 24 | loadMemoryFromFileInline(dmem, resizedHexFile.toString()) 25 | 26 | val cycle = RegInit(0.U(32.W)) 27 | val iaddr = dut.io.icache.req.bits.addr / (xlen / 8).U 28 | val daddr = dut.io.dcache.req.bits.addr / (xlen / 8).U 29 | val write = (0 until (xlen / 8)).foldLeft(0.U(xlen.W)) { (write, i) => 30 | write | 31 | (Mux( 32 | (dut.io.dcache.req.valid && dut.io.dcache.req.bits.mask(i)).asBool, 33 | dut.io.dcache.req.bits.data, 34 | dmem(daddr) 35 | )(8 * (i + 1) - 1, 8 * i) << (8 * i).U).asUInt 36 | } 37 | dut.io.icache.resp.valid := !reset.asBool 38 | dut.io.dcache.resp.valid := !reset.asBool 39 | dut.io.icache.resp.bits.data := RegNext(imem(iaddr)) 40 | dut.io.dcache.resp.bits.data := RegNext(dmem(daddr)) 41 | 42 | when(dut.io.icache.req.valid) { 43 | if (trace) printf("INST[%x] => %x\n", iaddr * (xlen / 8).U, imem(iaddr)) 44 | } 45 | when(dut.io.dcache.req.valid) { 46 | when(dut.io.dcache.req.bits.mask.orR) { 47 | dmem(daddr) := write 48 | if (trace) printf("MEM[%x] <= %x\n", daddr * (xlen / 8).U, write) 49 | }.otherwise { 50 | if (trace) printf("MEM[%x] => %x\n", daddr * (xlen / 8).U, dmem(daddr)) 51 | } 52 | } 53 | cycle := cycle + 1.U 54 | when(dut.io.host.tohost =/= 0.U) { 55 | printf("cycles: %d\n", cycle) 56 | assert((dut.io.host.tohost >> 1.U).asUInt === 0.U, "* tohost: %d *\n", dut.io.host.tohost) 57 | stop() 58 | } 59 | } 60 | 61 | object DefaultCoreConfig { 62 | def apply() = MiniConfig().core 63 | } 64 | 65 | class CoreSimpleTests extends AnyFlatSpec with ChiselScalatestTester { 66 | behavior.of("Core") 67 | it should "execute a simple test" in { 68 | test(new CoreTester(new Core(DefaultCoreConfig()), "rv32ui-p-simple")).runUntilStop(100) 69 | } 70 | } 71 | 72 | abstract class CoreTests(cfg: TestConfig, useVerilator: Boolean = false) 73 | extends AnyFlatSpec 74 | with ChiselScalatestTester { 75 | behavior.of("Core") 76 | val opts = if (useVerilator) Seq(VerilatorBackendAnnotation) else Seq() 77 | cfg.tests.foreach { name => 78 | it should s"execute $name" taggedAs IntegrationTest in { 79 | test(new CoreTester(new Core(DefaultCoreConfig()), name)).withAnnotations(opts).runUntilStop(cfg.maxcycles) 80 | } 81 | } 82 | } 83 | 84 | class CoreISATests extends CoreTests(ISATests) 85 | class CoreBmarkTests extends CoreTests(BmarkTests, true) 86 | -------------------------------------------------------------------------------- /src/test/scala/mini/DatapathTests.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.testers._ 7 | import chisel3.util._ 8 | import chiseltest._ 9 | import org.scalatest.flatspec.AnyFlatSpec 10 | 11 | object DatapathTesterState extends ChiselEnum { 12 | val sInit, sRun = Value 13 | } 14 | 15 | class DatapathTester(datapath: => Datapath, testType: DatapathTest) extends BasicTester with TestUtils { 16 | val dut = Module(datapath) 17 | val ctrl = Module(new Control) 18 | val xlen = dut.conf.xlen 19 | 20 | dut.io.ctrl <> ctrl.io 21 | dut.io.host.fromhost.bits := DontCare 22 | dut.io.host.fromhost.valid := false.B 23 | 24 | override val insts = tests(testType) 25 | 26 | import DatapathTesterState._ 27 | val state = RegInit(sInit) 28 | val (cntr, done) = Counter(state === sInit, insts.size) 29 | val timeout = RegInit(0.U(32.W)) 30 | val mem = Mem(1 << 20, UInt(xlen.W)) 31 | val iaddr = dut.io.icache.req.bits.addr / (xlen / 8).U 32 | val daddr = dut.io.dcache.req.bits.addr / (xlen / 8).U 33 | val write = (0 until (xlen / 8)).foldLeft(0.U) { (data, i) => 34 | data | 35 | (Mux(dut.io.dcache.req.bits.mask(i), dut.io.dcache.req.bits.data, mem(daddr)) & (BigInt(0xff) << (8 * i)).U) 36 | } 37 | dut.reset := state === sInit 38 | dut.io.icache.resp.bits.data := RegNext(mem(iaddr)) 39 | dut.io.icache.resp.valid := state === sRun 40 | dut.io.dcache.resp.bits.data := RegNext(mem(daddr)) 41 | dut.io.dcache.resp.valid := state === sRun 42 | 43 | switch(state) { 44 | is(sInit) { 45 | (0 until Consts.PC_START by 4).foreach { addr => 46 | mem((addr / 4).U) := (if (addr == Consts.PC_EVEC + (3 << 6)) fin else nop) 47 | } 48 | mem((Consts.PC_START / (xlen / 8)).U + cntr) := VecInit(insts)(cntr) 49 | when(done) { state := sRun } 50 | } 51 | is(sRun) { 52 | when(dut.io.icache.req.valid) { 53 | printf(s"INST[%x] => %x, iaddr: %x\n", dut.io.icache.req.bits.addr, mem(iaddr), iaddr) 54 | } 55 | when(dut.io.dcache.req.valid) { 56 | when(dut.io.dcache.req.bits.mask.orR) { 57 | mem(daddr) := write 58 | printf("MEM[%x] <= %x\n", dut.io.dcache.req.bits.addr, write) 59 | }.otherwise { 60 | printf("MEM[%x] => %x\n", dut.io.dcache.req.bits.addr, mem(daddr)) 61 | } 62 | } 63 | timeout := timeout + 1.U 64 | assert(timeout < 100.U) 65 | when(dut.io.host.tohost =/= 0.U) { 66 | assert( 67 | dut.io.host.tohost === testResults(testType).U, 68 | s"* tohost: %d != ${testResults(testType)} *", 69 | dut.io.host.tohost 70 | ) 71 | stop() 72 | } 73 | } 74 | } 75 | } 76 | 77 | class DatapathTests extends AnyFlatSpec with ChiselScalatestTester { 78 | val p = MiniConfig() 79 | Seq(BypassTest, ExceptionTest).foreach { tst => 80 | "Datapath" should s"pass $tst" in { 81 | test(new DatapathTester(new Datapath(p.core), tst)).runUntilStop() 82 | } 83 | } 84 | } 85 | -------------------------------------------------------------------------------- /src/test/scala/mini/ImmGenTests.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.testers._ 7 | import chisel3.util._ 8 | import chiseltest._ 9 | import chiseltest.formal._ 10 | import org.scalatest.flatspec.AnyFlatSpec 11 | 12 | class ImmGenTester(imm: => ImmGen) extends BasicTester with TestUtils { 13 | import Control._ 14 | val dut = Module(imm) 15 | val ctrl = Module(new Control) 16 | 17 | val (cntr, done) = Counter(true.B, insts.size) 18 | val i = VecInit(insts.map(iimm)) 19 | val s = VecInit(insts.map(simm)) 20 | val b = VecInit(insts.map(bimm)) 21 | val u = VecInit(insts.map(uimm)) 22 | val j = VecInit(insts.map(jimm)) 23 | val z = VecInit(insts.map(zimm)) 24 | val x = VecInit(insts.map(iimm).map(x => (x.litValue & -2).U)) 25 | val out = Mux( 26 | dut.io.sel === IMM_I, 27 | i(cntr), 28 | Mux( 29 | dut.io.sel === IMM_S, 30 | s(cntr), 31 | Mux( 32 | dut.io.sel === IMM_B, 33 | b(cntr), 34 | Mux( 35 | dut.io.sel === IMM_U, 36 | u(cntr), 37 | Mux(dut.io.sel === IMM_J, j(cntr), Mux(dut.io.sel === IMM_Z, z(cntr), x(cntr))) 38 | ) 39 | ) 40 | ) 41 | ) 42 | 43 | ctrl.io.inst := VecInit(insts)(cntr) 44 | dut.io.inst := ctrl.io.inst 45 | dut.io.sel := ctrl.io.imm_sel 46 | 47 | when(done) { stop() } 48 | assert(dut.io.out === out) 49 | printf("Counter: %d, Type: 0x%x, Out: %x ?= %x\n", cntr, dut.io.sel, dut.io.out, out) 50 | } 51 | 52 | class ImmGenTests extends AnyFlatSpec with ChiselScalatestTester with Formal { 53 | "ImmGenWire" should "pass" in { 54 | test(new ImmGenTester(new ImmGenWire(32))).runUntilStop() 55 | } 56 | "ImmGenMux" should "pass" in { 57 | test(new ImmGenTester(new ImmGenMux(32))).runUntilStop() 58 | } 59 | "ImmGenMux" should "be equivalent to ImmGenWire" in { 60 | // since there is no state (registers/memory) in the ImmGen, a single cycle check is enough to prove equivalence 61 | verify(new ImmGenEquivalenceCheck(new ImmGenMux(32)), Seq(BoundedCheck(1))) 62 | } 63 | } 64 | 65 | class ImmGenEquivalenceCheck(other: => ImmGen) extends Module { 66 | val dut = Module(other) 67 | val ref = Module(new ImmGenWire(dut.xlen)) 68 | 69 | // arbitrary inputs 70 | val io = IO(chiselTypeOf(dut.io)) 71 | 72 | // connect the same inputs to both modules (the outputs will be overwritten to always connect to the reference) 73 | dut.io <> io; ref.io <> io 74 | 75 | // check to ensure that outputs are the same 76 | assert(ref.io.out === dut.io.out, "out: expected: %d, actual: %d", ref.io.out, dut.io.out) 77 | } 78 | -------------------------------------------------------------------------------- /src/test/scala/mini/IntegrationTest.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | package mini 3 | 4 | import org.scalatest.Tag 5 | 6 | object IntegrationTest extends Tag("IntegrationTest") 7 | -------------------------------------------------------------------------------- /src/test/scala/mini/Opcode.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | 7 | object Opcode { 8 | // Special immediate instructions 9 | val LUI = BigInt("0110111", 2).U(7.W) 10 | val AUIPC = BigInt("0010111", 2).U(7.W) 11 | 12 | // Jump instructions 13 | val JAL = BigInt("1101111", 2).U(7.W) 14 | val JALR = BigInt("1100111", 2).U(7.W) 15 | 16 | // Branch instructions 17 | val BRANCH = BigInt("1100011", 2).U(7.W) 18 | 19 | // Load and store instrucdtions 20 | val STORE = BigInt("0100011", 2).U(7.W) 21 | val LOAD = BigInt("0000011", 2).U(7.W) 22 | 23 | // Arithmetic instructions 24 | val RTYPE = BigInt("0110011", 2).U(7.W) 25 | val ITYPE = BigInt("0010011", 2).U(7.W) 26 | 27 | val MEMORY = BigInt("0001111", 2).U(7.W) 28 | val SYSTEM = BigInt("1110011", 2).U(7.W) 29 | } 30 | 31 | object Funct3 { 32 | // Branch function codes 33 | val BEQ = BigInt("000", 2).U(3.W) 34 | val BNE = BigInt("001", 2).U(3.W) 35 | val BLT = BigInt("100", 2).U(3.W) 36 | val BGE = BigInt("101", 2).U(3.W) 37 | val BLTU = BigInt("110", 2).U(3.W) 38 | val BGEU = BigInt("111", 2).U(3.W) 39 | 40 | // Load and store function codes 41 | val LB = BigInt("000", 2).U(3.W) 42 | val LH = BigInt("001", 2).U(3.W) 43 | val LW = BigInt("010", 2).U(3.W) 44 | val LBU = BigInt("100", 2).U(3.W) 45 | val LHU = BigInt("101", 2).U(3.W) 46 | val SB = BigInt("000", 2).U(3.W) 47 | val SH = BigInt("001", 2).U(3.W) 48 | val SW = BigInt("010", 2).U(3.W) 49 | 50 | // Arithmetic R-type and I-type functions codes 51 | val ADD = BigInt("000", 2).U(3.W) 52 | val SLL = BigInt("001", 2).U(3.W) 53 | val SLT = BigInt("010", 2).U(3.W) 54 | val SLTU = BigInt("011", 2).U(3.W) 55 | val XOR = BigInt("100", 2).U(3.W) 56 | val OR = BigInt("110", 2).U(3.W) 57 | val AND = BigInt("111", 2).U(3.W) 58 | val SR = BigInt("101", 2).U(3.W) 59 | 60 | val CSRRW = BigInt("001", 2).U(3.W) 61 | val CSRRS = BigInt("010", 2).U(3.W) 62 | val CSRRC = BigInt("011", 2).U(3.W) 63 | val CSRRWI = BigInt("101", 2).U(3.W) 64 | val CSRRSI = BigInt("110", 2).U(3.W) 65 | val CSRRCI = BigInt("111", 2).U(3.W) 66 | } 67 | 68 | object Funct7 { 69 | val U = BigInt("0000000", 2).U(7.W) 70 | val S = BigInt("0100000", 2).U(7.W) 71 | } 72 | 73 | object Funct12 { 74 | val ECALL = BigInt("000000000000", 2).U(12.W) 75 | val EBREAK = BigInt("000000000001", 2).U(12.W) 76 | val ERET = BigInt("000100000000", 2).U(12.W) 77 | } 78 | -------------------------------------------------------------------------------- /src/test/scala/mini/TestConfig.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | trait TestConfig { 6 | def tests: List[String] 7 | def maxcycles: Int 8 | def namePrefix: String 9 | } 10 | 11 | case object ISATests extends TestConfig { 12 | val tests = List( 13 | "simple", 14 | "add", 15 | "addi", 16 | "auipc", 17 | "and", 18 | "andi", // TODO: "fence_i", 19 | "sb", 20 | "sh", 21 | "sw", 22 | "lb", 23 | "lbu", 24 | "lh", 25 | "lhu", 26 | "lui", 27 | "lw", 28 | "beq", 29 | "bge", 30 | "bgeu", 31 | "blt", 32 | "bltu", 33 | "bne", 34 | "j", 35 | "jal", 36 | "jalr", 37 | "or", 38 | "ori", 39 | "sll", 40 | "slli", 41 | "slt", 42 | "slti", 43 | "sra", 44 | "srai", 45 | "sub", 46 | "xor", 47 | "xori" 48 | ).map(t => s"rv32ui-p-${t}") ++ 49 | List( 50 | "sbreak", 51 | "scall", 52 | "illegal", 53 | "ma_fetch", 54 | "ma_addr", 55 | "csr" //, TODO: "timer" 56 | ).map(t => s"rv32mi-p-$t") 57 | val maxcycles = 15000 58 | val namePrefix = "ISATests" 59 | } 60 | 61 | case object BmarkTests extends TestConfig { 62 | val tests = List( 63 | "median.riscv", 64 | "multiply.riscv", 65 | "qsort.riscv", 66 | "towers.riscv", 67 | "vvadd.riscv" 68 | ) 69 | val maxcycles = 1500000 70 | val namePrefix = "BmarkTests" 71 | } 72 | 73 | case object LargeBmarkTests extends TestConfig { 74 | val tests = List( 75 | "median.riscv-large", 76 | "multiply.riscv-large", 77 | "qsort.riscv-large", 78 | "towers.riscv-large", 79 | "vvadd.riscv-large" 80 | ) 81 | val maxcycles = 5000000 82 | val namePrefix = "LargeBmarkTests" 83 | } 84 | -------------------------------------------------------------------------------- /src/test/scala/mini/TileTester.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | package mini 4 | 5 | import chisel3._ 6 | import chisel3.testers._ 7 | import chisel3.util._ 8 | import chisel3.util.experimental.loadMemoryFromFileInline 9 | import chiseltest._ 10 | import junctions._ 11 | import org.scalatest.flatspec.AnyFlatSpec 12 | 13 | object TileTesterState extends ChiselEnum { 14 | val sIdle, sWrite, sWrAck, sRead = Value 15 | } 16 | 17 | class TileTester(tile: => Tile, benchmark: String, latency: Int = 8, trace: Boolean = false) extends BasicTester { 18 | val originalHexFile = os.rel / "tests" / f"$benchmark.hex" 19 | val resizedHexFile = os.rel / "tests" / "64" / f"$benchmark.hex" 20 | TestUtils.resizeHexFile(os.pwd / originalHexFile, os.pwd / resizedHexFile, 64) // we have 64 bits per memory entry 21 | 22 | val dut = Module(tile) 23 | // extract parameters from design under test 24 | val nasti = dut.nastiParams 25 | 26 | dut.io.host.fromhost.bits := 0.U 27 | dut.io.host.fromhost.valid := false.B 28 | 29 | val _mem = Mem(1 << 20, UInt(nasti.dataBits.W)) 30 | loadMemoryFromFileInline(_mem, resizedHexFile.toString()) 31 | import TileTesterState._ 32 | val state = RegInit(sIdle) 33 | val cycle = RegInit(0.U(32.W)) 34 | 35 | val id = Reg(UInt(nasti.idBits.W)) 36 | val addr = Reg(UInt(nasti.addrBits.W)) 37 | val len = Reg(UInt(NastiConstants.LenBits.W)) 38 | val off = Reg(UInt(NastiConstants.LenBits.W)) 39 | val write = (0 until (nasti.dataBits / 8)).foldLeft(0.U(nasti.dataBits.W)) { (write, i) => 40 | write | 41 | (Mux(dut.io.nasti.w.bits.strb(i), dut.io.nasti.w.bits.data, _mem(addr))( 42 | 8 * (i + 1) - 1, 43 | 8 * i 44 | ) << (8 * i).U).asUInt 45 | } 46 | val bpipe = WireInit(dut.io.nasti.b) 47 | val rpipe = WireInit(dut.io.nasti.r) 48 | 49 | dut.reset := reset.asBool 50 | dut.io.nasti.aw.ready := state === sIdle 51 | dut.io.nasti.ar.ready := state === sIdle 52 | dut.io.nasti.w.ready := state === sWrite 53 | dut.io.nasti.b <> LatencyPipe(bpipe, latency) 54 | dut.io.nasti.r <> LatencyPipe(rpipe, latency) 55 | bpipe.bits := NastiWriteResponseBundle(nasti)(id) 56 | bpipe.valid := state === sWrAck 57 | rpipe.bits := NastiReadDataBundle(nasti)(id, _mem(addr + off), off === len) 58 | rpipe.valid := state === sRead 59 | 60 | val isDone = WireInit(false.B) 61 | val setDone = WireInit(false.B) 62 | 63 | cycle := cycle + 1.U 64 | when(dut.io.host.tohost =/= 0.U) { 65 | isDone := true.B 66 | } 67 | 68 | setDone := isDone 69 | when(setDone) { 70 | printf("cycles: %d\n", cycle) 71 | assert((dut.io.host.tohost >> 1.U) === 0.U, "* tohost: %d *\n", dut.io.host.tohost) 72 | stop() 73 | } 74 | 75 | /** 76 | * Master(Tile) --------- Slaver(Memory) 77 | * 78 | * Address Write > == AW == > 79 | * Data Write > == W == > 80 | * Response < == B == < 81 | * 82 | * Address Read > == AR == > 83 | * Data Read < == R == < 84 | */ 85 | 86 | switch(state) { 87 | is(sIdle) { 88 | when(dut.io.nasti.aw.valid) { 89 | assert((1.U << dut.io.nasti.aw.bits.size).asUInt === (nasti.dataBits / 8).U) 90 | addr := dut.io.nasti.aw.bits.addr / (nasti.dataBits / 8).U 91 | id := dut.io.nasti.aw.bits.id 92 | len := dut.io.nasti.aw.bits.len 93 | off := 0.U 94 | state := sWrite 95 | }.elsewhen(dut.io.nasti.ar.valid) { 96 | assert((1.U << dut.io.nasti.ar.bits.size).asUInt === (nasti.dataBits / 8).U) 97 | addr := dut.io.nasti.ar.bits.addr / (nasti.dataBits / 8).U 98 | id := dut.io.nasti.ar.bits.id 99 | len := dut.io.nasti.ar.bits.len 100 | off := 0.U 101 | state := sRead 102 | } 103 | } 104 | is(sWrite) { 105 | when(dut.io.nasti.w.valid) { 106 | _mem(addr + off) := write 107 | if (trace) printf("MEM[%x] <= %x\n", (addr + off) * (nasti.dataBits / 8).U, write) 108 | when(off === len) { 109 | assert(dut.io.nasti.w.bits.last) 110 | state := sWrAck 111 | }.otherwise { 112 | off := off + 1.U 113 | } 114 | } 115 | } 116 | is(sWrAck) { 117 | when(bpipe.ready) { 118 | state := sIdle 119 | } 120 | } 121 | is(sRead) { 122 | when(rpipe.ready) { 123 | when(off === len) { 124 | state := sIdle 125 | }.otherwise { 126 | off := off + 1.U 127 | } 128 | } 129 | } 130 | } 131 | } 132 | 133 | class LatencyPipeIO[T <: Data](val gen: T) extends Bundle { 134 | val in = Flipped(Decoupled(gen)) 135 | val out = Decoupled(gen) 136 | } 137 | 138 | class LatencyPipe[T <: Data](gen: T, latency: Int) extends Module { 139 | val io = IO(new LatencyPipeIO(chiselTypeOf(gen))) 140 | io := DontCare 141 | io.out <> (0 until latency).foldLeft(io.in)((in, i) => Queue(in, 1, pipe = true)) 142 | } 143 | 144 | object LatencyPipe { 145 | def apply[T <: Data](in: DecoupledIO[T], latency: Int) = { 146 | val pipe = Module(new LatencyPipe(in.bits, latency)) 147 | pipe.io.in <> in 148 | pipe.io.out 149 | } 150 | } 151 | 152 | class TileSimpleTests extends AnyFlatSpec with ChiselScalatestTester { 153 | behavior.of("Tile") 154 | val p = MiniConfig() 155 | it should "execute a simple test" in { 156 | test(new TileTester(Tile(p), "rv32ui-p-simple")).runUntilStop(15000) 157 | } 158 | } 159 | 160 | abstract class TileTests(cfg: TestConfig, useVerilator: Boolean = false) 161 | extends AnyFlatSpec 162 | with ChiselScalatestTester { 163 | behavior.of("Tile") 164 | val opts = if (useVerilator) Seq(VerilatorBackendAnnotation) else Seq() 165 | val p = MiniConfig() 166 | cfg.tests.foreach { name => 167 | it should s"execute $name" taggedAs IntegrationTest in { 168 | test(new TileTester(Tile(p), name)).withAnnotations(opts).runUntilStop(cfg.maxcycles) 169 | } 170 | } 171 | } 172 | 173 | class TileISATests extends TileTests(ISATests, true) 174 | class TileBmarkTests extends TileTests(BmarkTests, true) 175 | class TileLargeBmarkTests extends TileTests(LargeBmarkTests, true) 176 | -------------------------------------------------------------------------------- /tests/rv32mi-p-csr.hex: -------------------------------------------------------------------------------- 1 | 000000000000000000010101464c457f 2 | 00000034000001000000000100f30002 3 | 00280001002000340000000000000738 4 | 00000000000000000000000100020005 5 | 00000005000003d0000003d000000000 6 | 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3412907300828293341022f3fc629ce3 43 | 00000000ffdff06f0000007310000073 44 | 00000000000000000000000000000000 45 | 00000000000000000000000000000000 46 | -------------------------------------------------------------------------------- /tests/rv32mi-p-ma_addr.hex: -------------------------------------------------------------------------------- 1 | 000000000000000000010101464c457f 2 | 00000034000001000000000100f30002 3 | 00280001002000340000000000000590 4 | 00000000000000000000000100020005 5 | 000000050000033c0000033c00000000 6 | 00000000000000000000000000002000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00000000000000000000000000000000 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000000000 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 07ff0c6334102ff3234f0f1300000f17 18 | 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